Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile	(revision 59)
@@ -0,0 +1,24 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT			= ./
+include				$(DIR_COMPONENT)/Makefile.defs
+
+#-----[ Library ]------------------------------------------
+LIBRARY				= $(DIR_LIB)/libLoad_store_unit.a
+
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_component
+
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Component
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.defs
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.defs	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.defs	(revision 59)
@@ -0,0 +1,11 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT_MORPHEO		= ../../../../../../..
+DIR_MORPHEO			= $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.deps	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/Makefile.deps	(revision 59)
@@ -0,0 +1,40 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+# DIR_MORPHEO must be defined
+
+Load_store_unit			= yes
+
+ifndef Behavioural
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
+endif
+ifndef Queue_Control
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Queue_Control/Makefile.deps
+endif
+
+#-----[ Library ]------------------------------------------
+Load_store_unit_LIBRARY		= 	-lLoad_store_unit	\
+					$(Queue_Control_LIBRARY)\
+					$(Behavioural_LIBRARY)	
+
+Load_store_unit_DIR_LIBRARY	=	-L$(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/lib	\
+					$(Queue_Control_DIR_LIBRARY)\
+					$(Behavioural_DIR_LIBRARY)
+
+#-----[ Rules ]--------------------------------------------
+
+Load_store_unit_library		: 
+				@\
+				$(MAKE) Queue_Control_library; \
+				$(MAKE) Behavioural_library; \
+				$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit --makefile=Makefile;
+	
+Load_store_unit_library_clean	: 
+				@\
+				$(MAKE) Queue_Control_library_clean; \
+				$(MAKE) Behavioural_library_clean; \
+				$(MAKE) --directory=$(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit --makefile=Makefile clean;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile	(revision 59)
@@ -0,0 +1,30 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT			= ../
+include				$(DIR_COMPONENT)/Makefile.defs
+
+LIBRARY				= $(Load_store_unit_LIBRARY)
+
+DIR_LIBRARY			= $(Load_store_unit_DIR_LIBRARY)
+
+#-----[ include ]------------------------------------------
+
+all				:
+				@$(MAKE) all_selftest
+
+library				: Load_store_unit_library
+
+library_clean			: Load_store_unit_library_clean
+
+include                         ../Makefile.deps
+include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Selftest
+include 			$(DIR_MORPHEO)/Behavioural/Makefile.Synthesis
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 59)
@@ -0,0 +1,12 @@
+Load_store_unit
+2	2	*2	# store_size_queue       
+2	2	*2	# load_size_queue        
+2	2	*2	# size_speculative_access_queue
+2	2	+1	# nb_port_check
+2	2	+1	# speculative_load       {none,access,commit,bypass}
+2	2	*2	# nb_context             
+16	16	*2	# nb_packet              
+32	32	*2	# size_general_data      
+32	32	*2	# nb_general_register    
+4	4	*2	# nb_operation           
+4	4	*2	# nb_type                
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h	(revision 59)
@@ -0,0 +1,63 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test "RegisterFile"
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#include <string>
+#include <iostream>
+#include <sys/time.h>
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+using namespace std;
+using namespace morpheo;
+using namespace morpheo::behavioural;
+using namespace morpheo::behavioural::core;
+using namespace morpheo::behavioural::core::multi_execute_loop;
+using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop;
+using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit;
+using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit;
+
+using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit;
+
+void test    (string name,
+	      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param);
+
+class Time 
+{
+private : timeval time_begin;
+// private : timeval time_end;
+  
+public  : Time ()
+  {
+    gettimeofday(&time_begin     ,NULL);
+  };
+
+public  : ~Time ()
+  {
+    cout << *this;
+  };
+
+public  : friend ostream& operator<< (ostream& output_stream,
+				      const Time & x)
+  {
+    timeval time_end;
+    
+    gettimeofday(&time_end       ,NULL);
+    
+    uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time());
+
+    double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec);
+    
+    output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl;
+
+    return output_stream;
+  }
+};
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 59)
@@ -0,0 +1,92 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
+
+#define NB_PARAMS 11
+
+void usage (int argc, char * argv[])
+{
+  cerr << "<Usage> " << argv[0] << " name_instance list_params" << endl
+       << "list_params is :" << endl
+       << " - size_store_queue        (uint32_t)" << endl
+       << " - size_load_queue         (uint32_t)" << endl
+       << " - size_speculative_access_queue (uint32_t)" << endl
+       << " - nb_port_check           (uint32_t)" << endl
+       << " - speculative_load        (uint32_t)" << endl
+       << " - nb_context              (uint32_t)" << endl
+       << " - nb_packet               (uint32_t)" << endl
+       << " - size_general_data       (uint32_t)" << endl
+       << " - nb_general_register     (uint32_t)" << endl
+       << " - nb_operation            (uint32_t)" << endl
+       << " - nb_type                 (uint32_t)" << endl
+       << "" << endl;
+
+  for (int i=0; i<argc; i++)
+    cerr << argv[i] << " ";
+  cerr << endl;
+
+  exit (1);
+}
+
+#ifndef SYSTEMC
+int main    (int argc, char * argv[])
+#else
+int sc_main (int argc, char * argv[])
+#endif
+{
+  if (argc != 2+NB_PARAMS)
+    usage (argc, argv);
+
+  const string              name                     = argv[1];
+  const uint32_t            _size_store_queue        = atoi(argv[ 2]);
+  const uint32_t            _size_load_queue         = atoi(argv[ 3]);
+  const uint32_t            _size_speculative_access_queue = atoi(argv[ 4]);
+  const uint32_t            _nb_port_check           = atoi(argv[ 5]);
+  const Tspeculative_load_t _speculative_load        = fromString<Tspeculative_load_t>(argv[ 6]);
+  const uint32_t            _nb_context              = atoi(argv[ 7]);
+  const uint32_t            _nb_packet               = atoi(argv[ 8]);
+  const uint32_t            _size_general_data       = atoi(argv[ 9]);
+  const uint32_t            _nb_general_register     = atoi(argv[10]);
+  const uint32_t            _nb_operation            = atoi(argv[11]);
+  const uint32_t            _nb_type                 = atoi(argv[12]);
+
+  try 
+    {
+      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
+	(
+	 _size_store_queue       ,
+	 _size_load_queue        ,
+	 _size_speculative_access_queue,
+	 _nb_port_check          ,
+	 _speculative_load       ,
+	 _nb_context             ,
+	 _nb_packet              ,
+	 _size_general_data      ,
+	 _nb_general_register    ,
+	 _nb_operation           ,
+	 _nb_type                
+        );
+      
+      cout << param->print(1);
+      
+      test (name,param);
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      cout << "<" << name << "> : " <<  error.what ();
+      exit (EXIT_FAILURE);
+    }
+  catch (...)
+    {
+      cerr << "<" << name << "> : This test must generate a error" << endl;
+      exit (EXIT_FAILURE);
+    }
+
+  return (EXIT_SUCCESS);
+}
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 59)
@@ -0,0 +1,646 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include <queue>
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
+#include "Common/include/Test.h"
+
+#define NB_ITERATION  1
+#define CYCLE_MAX     (128*NB_ITERATION)
+
+#define LABEL(str)                                                                       \
+{                                                                                        \
+  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
+} while(0)
+
+static uint32_t cycle = 0;
+
+#define SC_START(cycle_offset)                                          \
+do                                                                      \
+{                                                                       \
+/*cout << "SC_START (begin)" << endl;*/                                 \
+                                                                        \
+  uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
+  if (cycle_current != cycle)                                           \
+    {                                                                   \
+      cycle = cycle_current;                                            \
+      cout << "##########[ cycle "<< cycle << " ]" << endl;             \
+    }                                                                   \
+                                                                        \
+  if (cycle_current > CYCLE_MAX)                                        \
+    {                                                                   \
+      TEST_KO("Maximal cycles Reached");                                \
+    }                                                                   \
+  sc_start(cycle_offset);                                               \
+/*cout << "SC_START (end  )" << endl;*/                                 \
+} while(0)
+
+
+
+class MemoryRequest_t
+{
+public : double             _cycle                ;
+public : Tcontext_t         _context_id           ;
+public : Tpacket_t          _packet_id            ;
+public : Toperation_t       _operation            ;
+public : Ttype_t            _type                 ;
+public : Tlsq_ptr_t         _store_queue_ptr_write;
+public : Tlsq_ptr_t         _load_queue_ptr_write ;
+public : Tgeneral_data_t    _immediat             ;
+public : Tgeneral_data_t    _data_ra              ;
+public : Tgeneral_data_t    _data_rb              ;
+public : Tcontrol_t         _write_rd             ;
+public : Tgeneral_address_t _num_reg_rd           ;
+public : bool               _write_spec_ko        ;
+
+  MemoryRequest_t (void) 
+  {
+    _cycle                 = 0;
+    _context_id            = 0;
+    _packet_id             = 0;
+    _operation             = 0;
+    _type                  = 0;
+    _store_queue_ptr_write = 0;
+    _load_queue_ptr_write  = 0;
+    _immediat              = 0;
+    _data_ra               = 0;
+    _data_rb               = 0;
+    _write_rd              = 0;
+    _num_reg_rd            = 0;
+    _write_spec_ko         = 0;
+  };
+
+  MemoryRequest_t (double             cycle                ,
+		   Tcontext_t         context_id           ,
+		   Tpacket_t          packet_id            ,
+		   Toperation_t       operation            ,
+		   Ttype_t            type                 ,
+		   Tlsq_ptr_t         store_queue_ptr_write,
+		   Tlsq_ptr_t         load_queue_ptr_write ,
+		   Tgeneral_data_t    immediat             ,
+		   Tgeneral_data_t    data_ra              ,
+		   Tgeneral_data_t    data_rb              ,
+		   Tcontrol_t         write_rd             ,
+		   Tgeneral_address_t num_reg_rd           ,
+		   bool               write_spec_ko        )
+  {
+    _cycle                 = cycle                ;
+    _context_id            = context_id           ;
+    _packet_id             = packet_id            ;
+    _operation             = operation            ;
+    _type                  = type                 ;
+    _store_queue_ptr_write = store_queue_ptr_write;
+    _load_queue_ptr_write  = load_queue_ptr_write ;
+    _immediat              = immediat             ;
+    _data_ra               = data_ra              ;
+    _data_rb               = data_rb              ;
+    _write_rd              = write_rd             ;
+    _num_reg_rd            = num_reg_rd           ;
+    _write_spec_ko         = write_spec_ko        ;
+  }
+
+  void modif (double             cycle                ,
+	      Tcontext_t         context_id           ,
+	      Tpacket_t          packet_id            ,
+	      Toperation_t       operation            ,
+	      Ttype_t            type                 ,
+	      Tlsq_ptr_t         store_queue_ptr_write,
+	      Tlsq_ptr_t         load_queue_ptr_write ,
+	      Tgeneral_data_t    immediat             ,
+	      Tgeneral_data_t    data_ra              ,
+	      Tgeneral_data_t    data_rb              ,
+	      Tcontrol_t         write_rd             ,
+	      Tgeneral_address_t num_reg_rd           ,
+	      bool               write_spec_ko        )
+  {
+    _cycle                 = cycle                ;
+    _context_id            = context_id           ;
+    _packet_id             = packet_id            ;
+    _operation             = operation            ;
+    _type                  = type                 ;
+    _store_queue_ptr_write = store_queue_ptr_write;
+    _load_queue_ptr_write  = load_queue_ptr_write ;
+    _immediat              = immediat             ;
+    _data_ra               = data_ra              ;
+    _data_rb               = data_rb              ;
+    _write_rd              = write_rd             ;
+    _num_reg_rd            = num_reg_rd           ;
+    _write_spec_ko         = write_spec_ko        ;
+  }
+
+  bool operator< (const MemoryRequest_t & right) const 
+  {
+    return _cycle > right._cycle; 
+  }
+
+  friend ostream& operator<<(ostream &, const MemoryRequest_t &);
+};
+
+ostream & operator << (ostream& os, const MemoryRequest_t & x) 
+{
+  return os << "<" << toString(x._cycle) << "> : "
+	    << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
+	    << "\t * " << toString(static_cast<uint32_t>(x._context_id)) << endl
+	    << "\t * " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
+	    << "\t * " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
+	    << "\t * " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
+	    << "\t * " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
+}
+
+void test (string name,
+	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+#ifdef STATISTICS
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+#endif
+
+  Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
+#ifdef STATISTICS
+					     _parameters_statistics,
+#endif
+					     _param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  string rename = "";
+
+  sc_clock                               * in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_VAL                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
+  sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
+  sc_signal<Ttype_t           > *   in_MEMORY_IN_TYPE                  = new sc_signal<Ttype_t           > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+//sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
+  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
+//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
+//sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
+
+  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL        = new sc_signal<Tcontrol_t	 >(rename.c_str());
+  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK        = new sc_signal<Tcontrol_t	 >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Toperation_t      > *  out_MEMORY_OUT_OPERATION  = new sc_signal<Toperation_t      >(rename.c_str());
+  sc_signal<Ttype_t           > *  out_MEMORY_OUT_TYPE       = new sc_signal<Ttype_t           >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD   = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
+  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD    = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+//sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE   = new sc_signal<Tcontrol_t        >(rename.c_str());
+//sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
+//sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE    = new sc_signal<Tspecial_data_t   >(rename.c_str());
+  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION  = new sc_signal<Texception_t      >(rename.c_str());
+
+  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  in_DCACHE_REQ_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > * out_DCACHE_REQ_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
+  sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
+  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_UNCACHED   = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > *  in_DCACHE_RSP_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > * out_DCACHE_RSP_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  in_DCACHE_RSP_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_data_t    > *  in_DCACHE_RSP_RDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL        = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
+  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_CONTEXT_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
+  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG    = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
+  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA       = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
+    
+    for (uint32_t i=0; i<_param->_size_load_queue; i++)
+      {
+	out_BYPASS_MEMORY_VAL        [i] = new sc_signal<Tcontrol_t        >;
+	out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t        >;
+	out_BYPASS_MEMORY_NUM_REG    [i] = new sc_signal<Tgeneral_address_t>;
+	out_BYPASS_MEMORY_DATA       [i] = new sc_signal<Tgeneral_data_t   >;
+      }
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
+  
+  (*(_Load_store_unit->in_CLOCK))        (*(in_CLOCK));
+  (*(_Load_store_unit->in_NRESET))       (*(in_NRESET));
+
+  (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
+  (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
+  (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
+  (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_TYPE                 ))(*( in_MEMORY_IN_TYPE                 ));
+  (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
+  (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
+//(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
+  (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
+//(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
+  (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
+//(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
+//(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
+  
+  (*(_Load_store_unit->out_MEMORY_OUT_VAL        ))(*(out_MEMORY_OUT_VAL        ));
+  (*(_Load_store_unit-> in_MEMORY_OUT_ACK        ))(*( in_MEMORY_OUT_ACK        ));
+  (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));
+  (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID  ))(*(out_MEMORY_OUT_PACKET_ID  ));
+  (*(_Load_store_unit->out_MEMORY_OUT_OPERATION  ))(*(out_MEMORY_OUT_OPERATION  ));
+  (*(_Load_store_unit->out_MEMORY_OUT_TYPE       ))(*(out_MEMORY_OUT_TYPE       ));
+  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD   ))(*(out_MEMORY_OUT_WRITE_RD   ));
+  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));
+  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD    ))(*(out_MEMORY_OUT_DATA_RD    ));
+//(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE   ))(*(out_MEMORY_OUT_WRITE_RE   ));
+//(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));
+//(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE    ))(*(out_MEMORY_OUT_DATA_RE    ));
+  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION  ))(*(out_MEMORY_OUT_EXCEPTION  ));
+
+  (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
+  (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
+  (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
+  (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
+  (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
+  (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
+  (*(_Load_store_unit->out_DCACHE_REQ_UNCACHED  ))(*(out_DCACHE_REQ_UNCACHED  ));
+  (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
+
+  (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
+  (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
+  (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_ERROR     ))(*( in_DCACHE_RSP_ERROR     ));
+
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	{
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL        [i]))(*(out_BYPASS_MEMORY_VAL        [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))(*(out_BYPASS_MEMORY_CONTEXT_ID [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG    [i]))(*(out_BYPASS_MEMORY_NUM_REG    [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA       [i]))(*(out_BYPASS_MEMORY_DATA       [i]));
+	}
+    }
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  Time * _time = new Time();
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  // Initialisation
+
+  const uint32_t seed = 0;
+//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  const uint32_t     nb_request   = _param->_nb_packet;
+  const uint32_t     nb_word      = nb_request;
+
+  const uint32_t     cst_max_cycle                  =   2;
+
+  const int32_t      percent_transaction_memory_in  = 100;
+  const int32_t      percent_transaction_memory_out = 100;
+  const int32_t      percent_transaction_dcache     = 100;
+
+  const int32_t      percent_exception              =   5;
+  const int32_t      percent_type_load              =   0;
+  const int32_t      percent_type_store             = 100;
+  const int32_t      percent_miss_spec              = 100;
+
+  if ((percent_type_load  +
+       percent_type_store ) > 100)
+    TEST_KO("sum of percent_type > 100");
+
+  const int32_t      seuil_type_load    = seuil_type_load;
+  const int32_t      seuil_type_store   = seuil_type_store+percent_type_load;
+
+  uint32_t           nb_request_memory_in ;
+  uint32_t           nb_request_memory_out;
+  uint32_t           nb_request_dcache    ;
+
+  MemoryRequest_t                 tab_request  [nb_request];
+  priority_queue<MemoryRequest_t> fifo_request;
+
+  Tdcache_data_t     cache_data                [_param->_nb_context][nb_word];
+
+  SC_START(0);
+
+  LABEL("Initialisation");
+
+  // emulate a memory
+  for (uint32_t i=0; i<_param->_nb_context; i++)
+    for (uint32_t j=0; j<nb_word; j++)
+      cache_data [i][j] = rand()%(1<<_param->_size_general_data);
+
+  in_MEMORY_IN_VAL ->write(0);
+  in_MEMORY_OUT_ACK->write(0);
+  in_DCACHE_REQ_ACK->write(0);
+  in_DCACHE_RSP_VAL->write(0);
+
+  in_NRESET        ->write(0);
+  SC_START(5);
+  in_NRESET        ->write(5);
+
+  LABEL("Loop of Test");
+
+  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+    {
+      nb_request_memory_in  = 0;
+      nb_request_memory_out = 0;
+      nb_request_dcache     = 0;
+      
+      LABEL("Iteration "+toString(iteration));
+
+      // Fill the request_queue
+      
+      Tlsq_ptr_t         store_queue_ptr_write = 0;
+      Tlsq_ptr_t         load_queue_ptr_write  = 0;
+
+      bool               store_queue_use [_param->_size_store_queue];
+      bool               load_queue_use  [_param->_size_load_queue ];
+
+      for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	store_queue_use [i] = false;
+      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+	load_queue_use  [i] = false;
+
+      double             store_queue_cycle [_param->_size_store_queue];
+      double             load_queue_cycle  [_param->_size_load_queue ];
+      double             current_cycle = sc_simulation_time();
+
+      for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	store_queue_cycle [i] = current_cycle;
+      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+	load_queue_cycle  [i] = current_cycle;
+
+      // Init fifo_request
+      for (uint32_t i=0; i<nb_request; i++)
+	{
+	  double             cycle                     = current_cycle+(rand()%(cst_max_cycle*nb_request));
+	  Tcontext_t         context_id                = rand () % _param->_nb_context;
+	  Tpacket_t          packet_id                 = i;
+	  Tlsq_ptr_t         store_queue_ptr_write_old = store_queue_ptr_write;
+	  Tlsq_ptr_t         load_queue_ptr_write_old  = load_queue_ptr_write ;
+	  Toperation_t       operation;
+	  
+	  int32_t            percent = rand()%100;
+
+	  if (percent < seuil_type_load)
+	    {
+	      operation = OPERATION_MEMORY_LOAD_16_S;
+	      load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
+	    }
+	  else
+	    if (percent < seuil_type_store)
+	      {
+		operation = OPERATION_MEMORY_STORE_16;
+		store_queue_ptr_write = (store_queue_ptr_write+1) % (_param->_size_store_queue);
+	      }
+	    else
+	      {
+		operation = OPERATION_MEMORY_PREFETCH;
+		load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
+	      }
+
+	  // Valid nb cycle ?
+	  if (is_operation_memory_store(operation))
+	    {
+	      if (cycle <= store_queue_cycle[packet_id])
+		cycle = store_queue_cycle[packet_id]+1;
+	    }
+	  else
+	    {
+	      if (cycle <= load_queue_cycle[packet_id])
+		cycle = load_queue_cycle[packet_id]+1;
+	    }
+
+	  Ttype_t            type                  = TYPE_MEMORY;
+
+	  Tgeneral_data_t    address               = rand()%(1<<_param->_size_general_data);
+	  Tgeneral_data_t    offset                = rand()%(1<<_param->_size_general_data);
+
+	  percent = rand()%100;
+	  if (percent > percent_exception) 
+	    address = address & (not mask_memory_access(operation));
+
+	  if (offset > address) // max
+	    offset  = address;
+
+	  Tgeneral_data_t    immediat              = offset;
+	  Tgeneral_data_t    data_ra               = address - offset;
+	  Tgeneral_data_t    data_rb               = rand()%(1<<_param->_size_general_data);
+	  Tcontrol_t         write_rd              = 0;
+	  Tgeneral_address_t num_reg_rd            = 0;
+	  bool               write_spec_ko         = ((rand()%100)<percent_miss_spec);
+
+	  tab_request [i].modif(cycle                ,
+				context_id           ,
+				packet_id            ,
+				operation            ,
+				type                 ,
+				store_queue_ptr_write_old,
+				load_queue_ptr_write_old ,
+				immediat             ,
+				data_ra              ,
+				data_rb              ,
+				write_rd             ,
+				num_reg_rd           ,
+				write_spec_ko
+				);
+
+	  fifo_request.push(tab_request [i]);
+	  
+	  if (is_operation_memory_store(operation))
+	    {
+	      cycle = cycle+((rand()%(10))-4);
+
+	      if (cycle <= store_queue_cycle[packet_id])
+		cycle = store_queue_cycle[packet_id]+1;
+			
+	      fifo_request.push(MemoryRequest_t(cycle,
+						context_id,
+						packet_id,
+						(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
+						type,
+						store_queue_ptr_write_old,
+						0,
+						0,
+						0,
+						0,
+						0,
+						0,
+						write_spec_ko));
+	    }
+
+	  // update nb cycle ?
+	  if (is_operation_memory_store(operation))
+	    {
+	      store_queue_cycle[packet_id] = cycle;
+	    }
+	  else
+	    {
+	      load_queue_cycle [packet_id] = cycle;
+	    }
+	}
+            
+      while (nb_request_memory_out < nb_request)
+	{
+	  bool can_execute = false;
+
+	  if (is_operation_memory_store(fifo_request.top()._operation))
+	    can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);
+	  else
+	    can_execute = not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
+	  
+	  in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 
+				   can_execute                and 
+				   (sc_simulation_time() >= fifo_request.top()._cycle));
+
+	  in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
+	  in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
+	  in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
+	  in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
+	  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
+   	  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
+	  in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
+	  in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
+	  in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
+	  in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
+	  in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
+
+	  in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
+	  
+	  SC_START(0);
+  
+	  SC_START(1);
+
+	  LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	  if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
+	    {
+	      LABEL(" * Accepted MEMORY_IN  : " + toString(nb_request_memory_in));
+	      cout << fifo_request.top();
+
+	      if (is_operation_memory_store(fifo_request.top()._operation))
+		{
+		  if (not is_operation_memory_store_head(fifo_request.top()._operation))
+		    store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
+		}
+	      else
+		load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
+
+	      fifo_request.pop();
+	      
+	      nb_request_memory_in ++;
+	    }
+
+	  LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
+	  if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
+	    {
+	      LABEL(" * Accepted MEMORY_OUT : " + toString(out_MEMORY_OUT_PACKET_ID->read()));
+
+	      if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
+		store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;
+	      else
+		load_queue_use  [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;
+
+	      nb_request_memory_out ++;
+	    }
+	}
+    }
+  
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  TEST_OK ("End of Simulation");
+  delete _time;
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+  delete     in_CLOCK;
+  delete     in_NRESET;
+
+  delete     in_MEMORY_IN_VAL                  ;
+  delete    out_MEMORY_IN_ACK                  ;
+  delete     in_MEMORY_IN_CONTEXT_ID           ;
+  delete     in_MEMORY_IN_PACKET_ID            ;
+  delete     in_MEMORY_IN_OPERATION            ;
+  delete     in_MEMORY_IN_TYPE                 ;
+  delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+  delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
+//delete     in_MEMORY_IN_HAS_IMMEDIAT         ;
+  delete     in_MEMORY_IN_IMMEDIAT             ;
+  delete     in_MEMORY_IN_DATA_RA              ;
+  delete     in_MEMORY_IN_DATA_RB              ;
+//delete     in_MEMORY_IN_DATA_RC              ;
+  delete     in_MEMORY_IN_WRITE_RD             ;
+  delete     in_MEMORY_IN_NUM_REG_RD           ;
+//delete     in_MEMORY_IN_WRITE_RE             ;
+//delete     in_MEMORY_IN_NUM_REG_RE           ;
+
+  delete    out_MEMORY_OUT_VAL       ;
+  delete     in_MEMORY_OUT_ACK       ;
+  delete    out_MEMORY_OUT_CONTEXT_ID;
+  delete    out_MEMORY_OUT_PACKET_ID ;
+  delete    out_MEMORY_OUT_OPERATION ;
+  delete    out_MEMORY_OUT_TYPE      ;
+  delete    out_MEMORY_OUT_WRITE_RD  ;
+  delete    out_MEMORY_OUT_NUM_REG_RD;
+  delete    out_MEMORY_OUT_DATA_RD   ;
+//delete    out_MEMORY_OUT_WRITE_RE  ;
+//delete    out_MEMORY_OUT_NUM_REG_RE;
+//delete    out_MEMORY_OUT_DATA_RE   ;
+  delete    out_MEMORY_OUT_EXCEPTION ;
+
+  delete    out_DCACHE_REQ_VAL       ;
+  delete     in_DCACHE_REQ_ACK       ;
+  delete    out_DCACHE_REQ_CONTEXT_ID;
+  delete    out_DCACHE_REQ_PACKET_ID ;
+  delete    out_DCACHE_REQ_ADDRESS   ;
+  delete    out_DCACHE_REQ_TYPE      ;
+  delete    out_DCACHE_REQ_UNCACHED  ;
+  delete    out_DCACHE_REQ_WDATA     ;
+
+  delete     in_DCACHE_RSP_VAL       ;
+  delete    out_DCACHE_RSP_ACK       ;
+  delete     in_DCACHE_RSP_CONTEXT_ID;
+  delete     in_DCACHE_RSP_PACKET_ID ;
+  delete     in_DCACHE_RSP_RDATA     ;
+  delete     in_DCACHE_RSP_ERROR     ;
+
+  delete [] out_BYPASS_MEMORY_VAL       ;
+  delete [] out_BYPASS_MEMORY_CONTEXT_ID;
+  delete [] out_BYPASS_MEMORY_NUM_REG   ;
+  delete [] out_BYPASS_MEMORY_DATA      ;
+
+#endif
+
+  delete _Load_store_unit;
+#ifdef STATISTICS
+  delete _parameters_statistics;
+#endif
+}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/VERSION
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/VERSION	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/VERSION	(revision 59)
@@ -0,0 +1,4 @@
+v0.6
+
+0.5 modif vhdl_port et vhdl_testbench_port -> ajout d'une macro
+0.6 ajout de la documentation
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Load_store_unit.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Load_store_unit.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Load_store_unit.tex	(revision 59)
@@ -0,0 +1,38 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
+
+\def\dirdoc{tex}
+\def\dirschema{eps}
+
+% Package de variables d'environnement : Titre, command etc ...
+\usepackage{../../../../../../../../Behavioural/doc/sty/doc-style}
+\usepackage{sty/header}
+
+
+%------------------------------------------------------------------------------
+% Début document
+%------------------------------------------------------------------------------
+
+\pagestyle{empty}
+
+\begin{document}
+
+% Créez une page de titre
+\maketitle
+\thispagestyle{empty}
+
+%Table des matières et des figures
+%\tableofcontents
+%\newpage
+%\listoffigures
+
+%------------------------------------------------------------------------------
+% Ajout du corps du documents
+%------------------------------------------------------------------------------
+
+\input{tex/root}
+
+%------------------------------------------------------------------------------
+% Fin d'ajout du corps du document
+%------------------------------------------------------------------------------
+
+\end{document}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Makefile	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/Makefile	(revision 59)
@@ -0,0 +1,19 @@
+# 
+# $Id$
+# 
+# [ Description ]
+# 
+# Makefile
+# 
+
+#-----[ Directory ]----------------------------------------
+DIR_COMPONENT			= ../
+include				$(DIR_COMPONENT)/Makefile.defs
+
+#-----[ include ]------------------------------------------
+
+all				:
+				$(MAKE) all_documentation
+
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Common
+include				$(DIR_MORPHEO)/Behavioural/Makefile.Documentation
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/sty/header.sty
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/sty/header.sty	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/sty/header.sty	(revision 59)
@@ -0,0 +1,12 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{Load\_store\_unit}
+ 
+\author{}
+
+\affiliation{}
+
+\email{}
+
+\date{\review}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/01_introduction.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/01_introduction.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/01_introduction.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Introduction}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/02_features.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/02_features.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/02_features.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Features}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/03_description.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/03_description.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/03_description.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Functional Description}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/04_pinout.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/04_pinout.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/04_pinout.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Pin out}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/05_parameters.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/05_parameters.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/05_parameters.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Parameters}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/06_performance.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/06_performance.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/06_performance.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Performance}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/07_details.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/07_details.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/07_details.tex	(revision 59)
@@ -0,0 +1,1 @@
+\Section{Details}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/08_history.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/08_history.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/08_history.tex	(revision 59)
@@ -0,0 +1,10 @@
+\Section{Revision History}
+
+\begin{tabular}{|c|c|c|}
+\hline
+Revision Date & By  & Modifications\\
+\hline
+\hline
+yyyy/mm/dd    & xxx & Initial document \\
+\hline
+\end{tabular}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/root.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/root.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/doc/tex/root.tex	(revision 59)
@@ -0,0 +1,8 @@
+\input{\dirdoc/01_introduction}
+\input{\dirdoc/02_features}
+\input{\dirdoc/03_description}
+\input{\dirdoc/04_pinout}
+\input{\dirdoc/05_parameters}
+\input{\dirdoc/06_performance}
+\input{\dirdoc/07_details}
+\input{\dirdoc/08_history}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 59)
@@ -0,0 +1,223 @@
+#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h
+#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Load_store_unit_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#ifdef SYSTEMC
+#include "systemc.h"
+#endif
+
+#define HAVE_MEMORY_OUT_OPERATION
+#define HAVE_MEMORY_OUT_TYPE
+
+#include <iostream>
+#include "Common/include/ToString.h"
+#include "Common/include/Debug.h"
+
+#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h"
+#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
+#ifdef STATISTICS
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"
+#endif
+#include "Behavioural/include/Component.h"
+#ifdef VHDL
+#include "Behavioural/include/Vhdl.h"
+#endif
+
+using namespace std;
+using namespace morpheo::behavioural::generic::queue_control;
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+  class Load_store_unit 
+#if SYSTEMC
+    : public sc_module
+#endif
+  {
+    // -----[ fields ]----------------------------------------------------
+    // Parameters
+  protected : const string       _name;
+
+  protected : const Parameters * _param;
+//#ifdef STATISTICS
+//  protected : const morpheo::behavioural::Parameters_Statistics * _param_statistics;
+//#endif
+
+#ifdef STATISTICS
+  private   : Statistics                     * _stat;
+#endif
+
+  public    : Component                      * _component;
+  private   : Interfaces                     * _interfaces;
+
+#ifdef SYSTEMC
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // Interface
+  public    : SC_CLOCK                      *  in_CLOCK        ;
+  public    : SC_IN (Tcontrol_t)            *  in_NRESET       ;
+
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_VAL         ;
+  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_IN_ACK         ;
+  public    : SC_IN (Tcontext_t        )    *  in_MEMORY_IN_CONTEXT_ID  ;
+  public    : SC_IN (Tpacket_t         )    *  in_MEMORY_IN_PACKET_ID   ;
+  public    : SC_IN (Toperation_t      )    *  in_MEMORY_IN_OPERATION   ;
+#ifdef HAVE_MEMORY_OUT_TYPE
+  public    : SC_IN (Ttype_t           )    *  in_MEMORY_IN_TYPE        ;
+#endif
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+  public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE;
+//public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_HAS_IMMEDIAT;
+  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_IMMEDIAT    ; // memory address
+  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RA     ; // memory address
+  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RB     ; // data        (store)
+//public    : SC_IN (Tspecial_data_t   )    *  in_MEMORY_IN_DATA_RC     ;
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RD    ; // = (operation==load)
+  public    : SC_IN (Tgeneral_address_t)    *  in_MEMORY_IN_NUM_REG_RD  ; // destination (load)
+//public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RE    ;
+//public    : SC_IN (Tspecial_address_t)    *  in_MEMORY_IN_NUM_REG_RE  ;
+
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_VAL       ;
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_OUT_ACK       ;
+  public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_CONTEXT_ID;
+  public    : SC_OUT(Tpacket_t         )    * out_MEMORY_OUT_PACKET_ID ;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+  public    : SC_OUT(Toperation_t      )    * out_MEMORY_OUT_OPERATION ;
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+  public    : SC_OUT(Ttype_t           )    * out_MEMORY_OUT_TYPE      ;
+#endif
+  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RD  ; // = (operation==load)
+  public    : SC_OUT(Tgeneral_address_t)    * out_MEMORY_OUT_NUM_REG_RD; // destination (load)
+  public    : SC_OUT(Tgeneral_data_t   )    * out_MEMORY_OUT_DATA_RD   ; // data        (load)
+//public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RE  ;
+//public    : SC_OUT(Tspecial_address_t)    * out_MEMORY_OUT_NUM_REG_RE;
+//public    : SC_OUT(Tspecial_data_t   )    * out_MEMORY_OUT_DATA_RE   ;
+  public    : SC_OUT(Texception_t      )    * out_MEMORY_OUT_EXCEPTION ;
+
+    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_REQ_VAL       ;
+  public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_REQ_ACK       ;
+  public    : SC_OUT(Tcontext_t        )    * out_DCACHE_REQ_CONTEXT_ID;
+  public    : SC_OUT(Tpacket_t         )    * out_DCACHE_REQ_PACKET_ID ;
+  public    : SC_OUT(Tdcache_address_t )    * out_DCACHE_REQ_ADDRESS   ;
+  public    : SC_OUT(Tdcache_type_t    )    * out_DCACHE_REQ_TYPE      ;
+  public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_REQ_UNCACHED  ;
+  public    : SC_OUT(Tdcache_data_t    )    * out_DCACHE_REQ_WDATA     ;
+
+    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_RSP_VAL       ;
+  public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_RSP_ACK       ;
+  public    : SC_IN (Tcontext_t        )    *  in_DCACHE_RSP_CONTEXT_ID;
+  public    : SC_IN (Tpacket_t         )    *  in_DCACHE_RSP_PACKET_ID ;
+  public    : SC_IN (Tdcache_data_t    )    *  in_DCACHE_RSP_RDATA     ;
+  public    : SC_IN (Tdcache_error_t   )    *  in_DCACHE_RSP_ERROR     ;
+
+    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_OUT(Tcontrol_t        )   ** out_BYPASS_MEMORY_VAL       ;
+  public    : SC_OUT(Tcontext_t        )   ** out_BYPASS_MEMORY_CONTEXT_ID;
+  public    : SC_OUT(Tgeneral_address_t)   ** out_BYPASS_MEMORY_NUM_REG   ;
+  public    : SC_OUT(Tgeneral_data_t   )   ** out_BYPASS_MEMORY_DATA      ;
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  protected : Tstore_queue_entry_t                                        * _store_queue;
+  protected : Tload_queue_entry_t                                         * _load_queue;
+  protected : Tspeculative_access_queue_entry_t                           * _speculative_access_queue;
+  protected : morpheo::behavioural::generic::queue_control::Queue_Control * _speculative_access_queue_control;
+
+    // function pointer
+  public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_transition     ) (void);
+  public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMoore       ) (void);
+  public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_dcache) (void);
+  public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_insert) (void);
+  public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void);
+
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+  public    : Tlsq_ptr_t                      internal_MEMORY_STORE_QUEUE_PTR_READ;
+  public    : Tlsq_ptr_t                      internal_MEMORY_LOAD_QUEUE_PTR_READ;
+
+  private   : Tcontrol_t                      internal_MEMORY_IN_ACK;
+  private   : Tcontrol_t                      internal_MEMORY_OUT_VAL;
+  private   : Tselect_queue_t                 internal_MEMORY_OUT_SELECT_QUEUE;
+#endif
+
+    // -----[ methods ]---------------------------------------------------
+
+#ifdef SYSTEMC
+    SC_HAS_PROCESS (Load_store_unit);
+#endif
+  public  :          Load_store_unit              
+  (
+#ifdef SYSTEMC
+   sc_module_name                                name,
+#else					       
+   string                                        name,
+#endif					       
+#ifdef STATISTICS
+   morpheo::behavioural::Parameters_Statistics * param_statistics,
+#endif
+   Parameters                                  * param );
+  public  :          ~Load_store_unit             (void);
+					       
+#ifdef SYSTEMC				       
+  private : void     allocation                (void);
+  private : void     deallocation              (void);
+
+  public  : void     transition                (void);
+  public  : void     genMoore                  (void);
+  public  : void     genMealy_dcache           (void);
+  public  : void     genMealy_insert           (void);
+  public  : void     genMealy_retire           (void);
+   
+  public  : void     function_speculative_load_commit_transition      (void);
+  public  : void     function_speculative_load_commit_genMoore        (void);
+  public  : void     function_speculative_load_commit_genMealy_dcache (void);
+  public  : void     function_speculative_load_commit_genMealy_insert (void);
+  public  : void     function_speculative_load_commit_genMealy_retire (void);
+#endif					       
+#ifdef STATISTICS
+  public  : string   statistics                (uint32_t depth);
+#endif
+					       
+#if VHDL				       
+  public  : void     vhdl                      (void);
+  private : void     vhdl_declaration          (Vhdl * & vhdl);
+  private : void     vhdl_body                 (Vhdl * & vhdl);
+#endif					       
+					       
+#ifdef VHDL_TESTBENCH			       
+  private : void     vhdl_testbench_transition (void);
+#endif
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 59)
@@ -0,0 +1,81 @@
+#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Parameters_h
+#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Parameters_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h"
+#include "Common/include/Debug.h"
+#include "Behavioural/include/Parameters.h"
+#include <math.h>
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+  class Parameters : public morpheo::behavioural::Parameters
+  {
+    //-----[ fields ]------------------------------------------------------------
+  public : const uint32_t            _size_store_queue       ;
+  public : const uint32_t            _size_load_queue        ;
+  public : const uint32_t            _size_speculative_access_queue;
+  public : const uint32_t            _nb_port_check          ;
+  public : const Tspeculative_load_t _speculative_load       ;
+  public : const uint32_t            _nb_context             ;
+  public : const uint32_t            _nb_packet              ;
+  public : const uint32_t            _size_general_data      ;
+  public : const uint32_t            _nb_general_register    ;
+  public : const uint32_t            _nb_operation           ;
+  public : const uint32_t            _nb_type                ;
+
+  public : const uint32_t            _size_address_store_queue             ;
+  public : const uint32_t            _size_address_load_queue              ;
+  public : const uint32_t            _size_address_speculative_access_queue;
+  public : const uint32_t            _size_context_id        ;
+  public : const uint32_t            _size_packet_id         ;
+  public : const uint32_t            _size_general_register  ;
+  public : const uint32_t            _size_operation         ;
+  public : const uint32_t            _size_type              ;
+
+    //-----[ methods ]-----------------------------------------------------------
+  public : Parameters  (uint32_t            size_store_queue       ,
+			uint32_t            size_load_queue        ,
+			uint32_t            size_speculative_access_queue,
+			uint32_t            nb_port_check          ,
+			Tspeculative_load_t speculative_load       ,
+			uint32_t            nb_context             ,
+			uint32_t            nb_packet              ,
+			uint32_t            size_general_data      ,
+			uint32_t            nb_general_register    ,
+			uint32_t            nb_operation           ,
+			uint32_t            nb_type                
+			);
+  public : Parameters  (Parameters & param) ;
+  public : ~Parameters () ;
+
+  public : string msg_error (void);
+
+  public :        string   print      (uint32_t depth);
+  public : friend ostream& operator<< (ostream& output_stream,
+				       morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters & x);
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h	(revision 59)
@@ -0,0 +1,63 @@
+#ifdef STATISTICS
+#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Statistics_h
+#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Statistics_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Common/include/Debug.h"
+#include "Behavioural/include/Statistics.h"
+#include "Behavioural/include/Parameters_Statistics.h"
+//#include "Behavioural/Generic/Group/include/Statistics.h"
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
+
+//using namespace morpheo::behavioural::generic::group;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+  class Statistics : public morpheo::behavioural::Statistics
+  {
+    // -----[ fields ]----------------------------------------------------
+  private  : const Parameters                                 * _parameters;
+
+    // -----[ methods ]---------------------------------------------------
+  public   : Statistics  (string                                        name                       ,
+			  morpheo::behavioural::Parameters_Statistics * parameters_statistics      ,
+			  Parameters                                  * parameters
+			  );
+//public   : Statistics  (Statistics & stat);
+  public   : ~Statistics () ;
+    
+  public   : string   print_body (uint32_t depth);
+  public   : string   print      (uint32_t depth);
+  public   : void     add        ();
+
+  public   : friend ostream& operator<< (ostream& output_stream,
+					 const Statistics & x);
+
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo
+
+#endif
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 59)
@@ -0,0 +1,184 @@
+#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Types_h
+#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_execute_unit_execute_unit_load_store_unit_Types_h
+
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/include/Types.h"
+#include "Common/include/ToString.h"
+#include "Common/include/FromString.h"
+#include "Common/include/ErrorMorpheo.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+  typedef enum 
+    {
+      NO_SPECULATIVE_LOAD    , //each load wait all previous store before the data cache access
+      SPECULATIVE_LOAD_ACCESS, //each load wait all previous store before the commiting
+      SPECULATIVE_LOAD_COMMIT, //each load commit the result before the end of dependence's check
+      SPECULATIVE_LOAD_BYPASS  //each load bypass the result before the end of dependence's check
+    } Tspeculative_load_t; 
+  
+  typedef enum
+    {
+      SELECT_STORE_QUEUE,
+      SELECT_LOAD_QUEUE ,
+      SELECT_LOAD_QUEUE_SPECULATIVE
+    } Tselect_queue_t;
+  
+  // ----------------------------------------------------------
+  // Store Queue
+  // ----------------------------------------------------------
+
+  typedef enum
+    {
+      STORE_QUEUE_EMPTY                    //entry is empty
+      ,STORE_QUEUE_NO_VALID_NO_SPECULATIVE //entry is the top of rob, and operation isn't arrive
+      ,STORE_QUEUE_VALID_SPECULATIVE       //entry is arrive and wait the top of rob
+      ,STORE_QUEUE_VALID_NO_SPECULATIVE    //entry is ok, can be access at a dcache port.
+      ,STORE_QUEUE_COMMIT                  //entry have access at dcache
+    } Tstore_queue_state_t;
+
+  class Tstore_queue_entry_t
+  {
+  public    : Tstore_queue_state_t _state               ;
+  public    : Tcontext_t           _context_id          ;
+  public    : Tpacket_t            _packet_id           ;
+  public    : Taccess_t            _access              ;
+  public    : Tcontrol_t           _uncached            ;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+  public    : Toperation_t         _operation           ;
+#endif				   
+#ifdef HAVE_MEMORY_OUT_TYPE	   	              
+  public    : Ttype_t              _type                ;
+#endif				   
+  public    : Tlsq_ptr_t           _load_queue_ptr_write;
+  public    : Tdcache_data_t       _address             ;
+  public    : Tgeneral_data_t      _wdata               ;
+//public    : Tcontrol_t           _write_rd            ;
+//public    : Tgeneral_address_t   _num_reg_rd          ;
+  public    : Texception_t         _exception           ;
+  };
+
+  // ----------------------------------------------------------
+  // Speculative_Access  Queue
+  // ----------------------------------------------------------
+
+  typedef enum
+    {
+      SPECULATIVE_ACCESS_QUEUE_EMPTY            //entry is empty
+      ,SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE      //entry is valid and can access at the dcache
+      ,SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE //entry wait an empty slot in load queue
+    } Tspeculative_access_queue_state_t;
+
+  class Tspeculative_access_queue_entry_t
+  {
+  public    : Tspeculative_access_queue_state_t  _state                ;
+  public    : Tcontext_t                         _context_id           ;
+  public    : Tpacket_t                          _packet_id            ;
+  public    : Taccess_t                          _access               ;
+  public    : Tcontrol_t                         _uncached             ;
+  public    : Tcontrol_t                         _sign_extension       ;
+#ifdef HAVE_MEMORY_OUT_OPERATION                 		       
+  public    : Toperation_t                       _operation            ;
+#endif				                 		       
+#ifdef HAVE_MEMORY_OUT_TYPE	                 	               
+  public    : Ttype_t                            _type                 ;
+#endif				                 		       
+  public    : Tlsq_ptr_t                         _load_queue_ptr_write ;
+  public    : Tlsq_ptr_t                         _store_queue_ptr_write;
+  public    : Tdcache_address_t                  _address              ;
+  public    : Tgeneral_data_t                    _rdata                ;
+  public    : Tcontrol_t                         _write_rd             ;
+  public    : Tgeneral_address_t                 _num_reg_rd           ;
+  public    : Texception_t                       _exception            ;
+  };
+
+  // ----------------------------------------------------------
+  // Load  Queue
+  // ----------------------------------------------------------
+
+  typedef enum
+    {
+      LOAD_QUEUE_EMPTY         //entry is empty
+      ,LOAD_QUEUE_WAIT_CHECK   //entry must wait the respons and check dependence with store
+      ,LOAD_QUEUE_WAIT         //entry must wait the respons
+      ,LOAD_QUEUE_COMMIT_CHECK //entry must check dependence and can commit speculative
+      ,LOAD_QUEUE_CHECK        //entry must check dependence with store
+      ,LOAD_QUEUE_COMMIT       //entry must commit the instruction
+    } Tload_queue_state_t;
+
+  class Tload_queue_entry_t
+  {
+  public    : Tload_queue_state_t  _state               ;
+  public    : Tcontext_t           _context_id          ;
+  public    : Tpacket_t            _packet_id           ;
+  public    : Taccess_t            _access              ;
+  public    : Tcontrol_t           _uncached            ;
+  public    : Tcontrol_t           _sign_extension      ;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+  public    : Toperation_t         _operation           ;
+#endif				   
+#ifdef HAVE_MEMORY_OUT_TYPE	   	              
+  public    : Ttype_t              _type                ;
+#endif				   
+  public    : Tlsq_ptr_t           _store_queue_ptr_write;
+  public    : Tdcache_address_t    _address             ;
+  public    : Tgeneral_data_t      _rdata               ;
+  public    : Tcontrol_t           _write_rd            ;
+  public    : Tgeneral_address_t   _num_reg_rd          ;
+  public    : Texception_t         _exception           ;
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+}; // end namespace behavioural
+
+  template<> inline std::string toString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t>(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD     : return "no_speculative_load"    ; break;
+      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS : return "speculative_load_access"; break;
+      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT : return "speculative_load_commit"; break;
+      case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS : return "speculative_load_bypass"; break;
+      default    : return ""      ; break;
+      }
+  };
+
+  template<> inline morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t fromString<morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_load_t>(const std::string& x)
+  {
+    if ( (x.compare("0")                       == 0) or
+         (x.compare("no_speculative_load")     == 0))
+      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::NO_SPECULATIVE_LOAD;
+    if ( (x.compare("1")                       == 0) or
+         (x.compare("speculative_load_access") == 0))
+      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_ACCESS;
+    if ( (x.compare("2")                       == 0) or
+         (x.compare("speculative_load_commit") == 0))
+      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_COMMIT;
+    if ( (x.compare("3")                       == 0) or
+         (x.compare("speculative_load_bypass") == 0))
+      return morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_LOAD_BYPASS;
+    
+    throw (ErrorMorpheo ("<fromString> : Unknow string : \""+x+"\""));
+  };
+
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 59)
@@ -0,0 +1,171 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::Load_store_unit"
+#ifdef SYSTEMC
+  Load_store_unit::Load_store_unit (sc_module_name name,
+#else
+  Load_store_unit::Load_store_unit (string name,
+#endif
+#ifdef STATISTICS
+			  morpheo::behavioural::Parameters_Statistics * param_statistics,
+#endif
+			  morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param ):
+			      _name              (name)
+			      ,_param            (param)
+// #ifdef STATISTICS
+// 			      ,_param_statistics (param_statistics)
+// #endif
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+#ifdef SYSTEMC
+    log_printf(INFO,Load_store_unit,FUNCTION,"Allocation");
+
+    allocation ();
+#endif
+
+#ifdef STATISTICS
+    log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics");
+
+    // Allocation of statistics
+    _stat = new Statistics (static_cast<string>(_name),
+			    param_statistics          ,
+			    param);
+#endif
+
+#ifdef VHDL
+    // generate the vhdl
+    log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl");
+
+    vhdl();
+#endif
+
+#ifdef SYSTEMC
+    // Function pointer
+
+    switch (_param->_speculative_load)
+      {
+      case SPECULATIVE_LOAD_COMMIT :
+	{
+	  function_transition      = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_transition     ;
+	  function_genMoore        = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMoore       ;
+	  function_genMealy_dcache = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_dcache;
+	  function_genMealy_insert = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_insert;
+	  function_genMealy_retire = &morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::function_speculative_load_commit_genMealy_retire;
+	  break;
+	}
+      case NO_SPECULATIVE_LOAD     :
+      case SPECULATIVE_LOAD_ACCESS :
+      case SPECULATIVE_LOAD_BYPASS :
+      default                      :
+	{
+	  break;
+	}
+      }
+
+    log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition");
+
+    SC_METHOD (transition);
+    dont_initialize ();
+    sensitive_pos << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+    log_printf(INFO,Load_store_unit,FUNCTION,"Method - genMoore");
+
+    SC_METHOD (genMoore);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+    log_printf(INFO,Load_store_unit,FUNCTION,"Method - genMealy_insert");
+
+    SC_METHOD (genMealy_insert);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+    sensitive     << *(in_MEMORY_IN_OPERATION);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION));
+#endif    
+
+    log_printf(INFO,Load_store_unit,FUNCTION,"Method - genMealy_retire");
+
+    SC_METHOD (genMealy_retire);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+    log_printf(INFO,Load_store_unit,FUNCTION,"Method - genMealy_dcache");
+
+    SC_METHOD (genMealy_dcache);
+    dont_initialize ();
+    sensitive_neg << *(in_CLOCK);
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+#endif    
+
+#endif
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+  
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::~Load_store_unit"
+  Load_store_unit::~Load_store_unit (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+#ifdef STATISTICS
+    log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file");
+
+    _stat->generate_file(statistics(0));
+    
+    delete _stat;
+#endif
+
+#ifdef SYSTEMC
+    log_printf(INFO,Load_store_unit,FUNCTION,"Deallocation");
+
+    deallocation ();
+#endif
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 59)
@@ -0,0 +1,199 @@
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::allocation"
+  void Load_store_unit::allocation (void)
+  {
+    string rename;
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    _component   = new Component ();
+
+    Entity * entity = _component->set_entity (_name       
+					      ,"Load_store_unit"
+#ifdef POSITION
+					      ,COMBINATORY 
+#endif
+					      );
+
+    _interfaces = entity->set_interfaces();
+
+    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface * interface = _interfaces->set_interface(""
+#ifdef POSITION
+							 ,IN
+							 ,SOUTH,
+							 "Generalist interface"
+#endif
+							 );
+      
+      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
+      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
+    }
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface_fifo * interface = _interfaces->set_interface("memory_in"
+#ifdef POSITION
+							      ,IN
+							      ,WEST
+							      ,"Instruction from Reservations station"
+#endif
+							      );
+
+   in_MEMORY_IN_VAL                   = interface->set_signal_valack_in        (VAL);
+  out_MEMORY_IN_ACK                   = interface->set_signal_valack_out       (ACK);
+   in_MEMORY_IN_CONTEXT_ID            = interface->set_signal_in  <Tcontext_t        > ("context_id"  ,_param->_size_context_id       );
+   in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id       );
+   in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
+#ifdef HAVE_MEMORY_OUT_TYPE
+   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
+#endif
+   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue);
+   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
+// in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
+   in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
+   in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
+   in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
+// in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
+   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
+   in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
+// in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
+// in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
+    }
+
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface_fifo * interface = _interfaces->set_interface("memory_out"
+#ifdef POSITION
+							      ,OUT
+							      ,EAST
+							      ,"Instruction to write queue"
+#endif
+							      );
+
+      out_MEMORY_OUT_VAL         = interface->set_signal_valack_out(VAL);
+       in_MEMORY_OUT_ACK         = interface->set_signal_valack_in (ACK);
+      out_MEMORY_OUT_CONTEXT_ID  = interface->set_signal_out <Tcontext_t        > ("context_id"  ,_param->_size_context_id       );
+      out_MEMORY_OUT_PACKET_ID   = interface->set_signal_out <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id        );
+#ifdef HAVE_MEMORY_OUT_OPERATION
+      out_MEMORY_OUT_OPERATION   = interface->set_signal_out <Toperation_t      > ("operation"   ,_param->_size_operation        );
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+      out_MEMORY_OUT_TYPE        = interface->set_signal_out <Ttype_t           > ("type"        ,_param->_size_type             );
+#endif
+      out_MEMORY_OUT_WRITE_RD    = interface->set_signal_out <Tcontrol_t        > ("write_rd"    ,1                              );
+      out_MEMORY_OUT_NUM_REG_RD  = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"  ,_param->_size_general_register );
+      out_MEMORY_OUT_DATA_RD     = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"     ,_param->_size_general_data     );
+//    out_MEMORY_OUT_WRITE_RE    = interface->set_signal_out <Tcontrol_t        > ("write_rd"    ,1                              );
+//    out_MEMORY_OUT_NUM_REG_RE  = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"  ,_param->_size_general_register );
+//    out_MEMORY_OUT_DATA_RE     = interface->set_signal_out <Tspecial_data_t   > ("data_re"     ,_param->_size_general_data     );
+      out_MEMORY_OUT_EXCEPTION   = interface->set_signal_out <Texception_t      > ("exception"   ,_param->_size_exception        );
+
+    }
+
+    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface_fifo * interface = _interfaces->set_interface("dcache_req"
+#ifdef POSITION
+							      ,OUT
+							      ,NORTH
+							      ,"Request port to dcache"
+#endif
+							      );
+
+      out_DCACHE_REQ_VAL        = interface->set_signal_valack_out(VAL);
+       in_DCACHE_REQ_ACK        = interface->set_signal_valack_in (ACK);
+      out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t        > ("context_id",_param->_size_context_id  );
+      out_DCACHE_REQ_PACKET_ID  = interface->set_signal_out <Tpacket_t         > ("packet_id" ,_param->_size_packet_id   );
+      out_DCACHE_REQ_ADDRESS    = interface->set_signal_out <Tdcache_address_t > ("address"   ,_param->_size_dcache_address);
+      out_DCACHE_REQ_TYPE       = interface->set_signal_out <Tdcache_type_t    > ("type"      ,_param->_size_dcache_type );
+      out_DCACHE_REQ_UNCACHED   = interface->set_signal_out <Tcontrol_t        > ("uncached"  ,1);
+      out_DCACHE_REQ_WDATA      = interface->set_signal_out <Tdcache_data_t    > ("wdata"     ,_param->_size_general_data);
+    }
+    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      Interface_fifo * interface = _interfaces->set_interface("dcache_rsp"
+#ifdef POSITION
+							      ,IN
+							      ,NORTH
+							      ,"Respons port from dcache"
+#endif
+							      );
+
+       in_DCACHE_RSP_VAL        = interface->set_signal_valack_in (VAL);
+      out_DCACHE_RSP_ACK        = interface->set_signal_valack_out(ACK);
+       in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in  <Tcontext_t     > ("context_id",_param->_size_context_id  );
+       in_DCACHE_RSP_PACKET_ID  = interface->set_signal_in  <Tpacket_t      > ("packet_id" ,_param->_size_packet_id   );
+       in_DCACHE_RSP_RDATA      = interface->set_signal_in  <Tdcache_data_t > ("rdata"     ,_param->_size_general_data);
+       in_DCACHE_RSP_ERROR      = interface->set_signal_in  <Tdcache_error_t> ("error"     ,_param->_size_dcache_error);
+    }
+    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+      {
+	out_BYPASS_MEMORY_VAL        = new SC_OUT(Tcontrol_t        ) * [_param->_size_load_queue];
+	out_BYPASS_MEMORY_CONTEXT_ID = new SC_OUT(Tcontext_t        ) * [_param->_size_load_queue];
+	out_BYPASS_MEMORY_NUM_REG    = new SC_OUT(Tgeneral_address_t) * [_param->_size_load_queue];
+	out_BYPASS_MEMORY_DATA       = new SC_OUT(Tgeneral_data_t   ) * [_param->_size_load_queue];
+	
+	for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	  {
+	    Interface_fifo * interface = _interfaces->set_interface("memory_out"
+#ifdef POSITION
+								    ,OUT
+								    ,NORTH
+								    ,"Bypass between the load queue and the reservation station"
+#endif
+								    );
+	    
+	    out_BYPASS_MEMORY_VAL        [i] = interface->set_signal_valack_out(VAL);
+	    out_BYPASS_MEMORY_CONTEXT_ID [i] = interface->set_signal_out <Tcontext_t        > ("context_id", _param->_size_context_id);
+	    out_BYPASS_MEMORY_NUM_REG    [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg"   , _param->_size_general_register);
+	    out_BYPASS_MEMORY_DATA       [i] = interface->set_signal_out <Tgeneral_data_t   > ("data"      , _param->_size_general_data);
+	  }
+      }
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+#ifdef POSITION
+    _component->generate_file();
+#endif
+
+    _store_queue                      = new Tstore_queue_entry_t              [_param->_size_store_queue];
+    _load_queue	                      = new Tload_queue_entry_t               [_param->_size_load_queue];
+    _speculative_access_queue         = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];
+    _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 59)
@@ -0,0 +1,117 @@
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::"
+
+#ifdef SYSTEMC
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::deallocation"
+  void Load_store_unit::deallocation (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+    delete    in_CLOCK ;
+//#endif
+    delete    in_NRESET;
+
+    delete     in_MEMORY_IN_VAL         ;
+    delete    out_MEMORY_IN_ACK         ;
+    delete     in_MEMORY_IN_CONTEXT_ID  ;
+    delete     in_MEMORY_IN_PACKET_ID   ;
+    delete     in_MEMORY_IN_OPERATION   ;
+#ifdef HAVE_MEMORY_OUT_TYPE
+    delete     in_MEMORY_IN_TYPE        ;
+#endif
+    delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+    delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
+//  delete     in_MEMORY_IN_HAS_IMMEDIAT;
+    delete     in_MEMORY_IN_IMMEDIAT    ;
+    delete     in_MEMORY_IN_DATA_RA     ;
+    delete     in_MEMORY_IN_DATA_RB     ;
+//  delete     in_MEMORY_IN_DATA_RC     ;
+    delete     in_MEMORY_IN_WRITE_RD    ;
+    delete     in_MEMORY_IN_NUM_REG_RD  ;
+//  delete     in_MEMORY_IN_WRITE_RE    ;
+//  delete     in_MEMORY_IN_NUM_REG_RE  ;
+    
+    delete    out_MEMORY_OUT_VAL       ;
+    delete     in_MEMORY_OUT_ACK       ;
+    delete    out_MEMORY_OUT_CONTEXT_ID;
+    delete    out_MEMORY_OUT_PACKET_ID ;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+    delete    out_MEMORY_OUT_OPERATION ;
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+    delete    out_MEMORY_OUT_TYPE      ;
+#endif
+    delete    out_MEMORY_OUT_WRITE_RD  ;
+    delete    out_MEMORY_OUT_NUM_REG_RD;
+    delete    out_MEMORY_OUT_DATA_RD   ;
+//  delete    out_MEMORY_OUT_WRITE_RE  ;
+//  delete    out_MEMORY_OUT_NUM_REG_RE;
+//  delete    out_MEMORY_OUT_DATA_RE   ;
+    delete    out_MEMORY_OUT_EXCEPTION ;
+    
+    delete    out_DCACHE_REQ_VAL       ;
+    delete     in_DCACHE_REQ_ACK       ;
+    delete    out_DCACHE_REQ_CONTEXT_ID;
+    delete    out_DCACHE_REQ_PACKET_ID ;
+    delete    out_DCACHE_REQ_ADDRESS   ;
+    delete    out_DCACHE_REQ_TYPE      ;
+    delete    out_DCACHE_REQ_UNCACHED  ;
+    delete    out_DCACHE_REQ_WDATA     ;
+    
+    delete     in_DCACHE_RSP_VAL       ;
+    delete    out_DCACHE_RSP_ACK       ;
+    delete     in_DCACHE_RSP_CONTEXT_ID;
+    delete     in_DCACHE_RSP_PACKET_ID ;
+    delete     in_DCACHE_RSP_RDATA     ;
+    delete     in_DCACHE_RSP_ERROR     ;
+    
+    if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+      {
+	delete [] out_BYPASS_MEMORY_VAL       ;
+	delete [] out_BYPASS_MEMORY_CONTEXT_ID;
+	delete [] out_BYPASS_MEMORY_NUM_REG   ;
+	delete [] out_BYPASS_MEMORY_DATA      ;
+      }
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    delete    _component;
+
+    delete [] _store_queue                      ;
+    delete [] _load_queue	                ;
+    delete    _speculative_access_queue_control ;
+    delete [] _speculative_access_queue         ;
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_dcache.cpp	(revision 59)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_dcache"
+  void Load_store_unit::function_speculative_load_commit_genMealy_dcache (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 59)
@@ -0,0 +1,53 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_insert"
+  void Load_store_unit::function_speculative_load_commit_genMealy_insert (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    if (is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) == true)
+      {
+	internal_MEMORY_IN_ACK = 1;
+      }
+    else
+      {
+	internal_MEMORY_IN_ACK = not _speculative_access_queue_control->full();
+      }
+
+    PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK);
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_retire.cpp	(revision 59)
@@ -0,0 +1,40 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMealy_retire"
+  void Load_store_unit::function_speculative_load_commit_genMealy_retire (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 59)
@@ -0,0 +1,105 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
+  void Load_store_unit::function_speculative_load_commit_genMoore (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    // Test store and load queue
+    Tcontext_t         memory_out_context_id = 0;
+    Tpacket_t          memory_out_packet_id  = 0;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+    Toperation_t       memory_out_operation  = 0;
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+    Ttype_t            memory_out_type       = 0;
+#endif
+    Tcontrol_t         memory_out_write_rd   = 0;
+    Tgeneral_address_t memory_out_num_reg_rd = 0;
+    Tgeneral_data_t    memory_out_data_rd    = 0;
+//  Tcontrol_t         memory_out_write_re   = 0;
+//  Tspecial_address_t memory_out_num_reg_re = 0;
+//  Tspecial_data_t    memory_out_data_re    = 0;
+    Texception_t       memory_out_exception  = 0;
+
+    internal_MEMORY_OUT_VAL          = 0;
+
+    // TODO : now only store queue
+
+    // Test an store must be commited.
+
+    
+    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
+      {
+	internal_MEMORY_OUT_VAL          = 1;
+	internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
+	
+	memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
+	memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
+#ifdef HAVE_MEMORY_OUT_OPERATION
+	memory_out_operation = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._operation;
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+  	memory_out_type      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._type;
+#endif
+//	memory_out_write_rd  
+//	memory_out_num_reg_rd
+//	memory_out_data_rd   
+	memory_out_exception = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._exception;
+      }
+
+    PORT_WRITE(out_MEMORY_OUT_VAL       , internal_MEMORY_OUT_VAL);
+
+    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id);
+    PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id );
+#ifdef HAVE_MEMORY_OUT_OPERATION
+    PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation );
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+    PORT_WRITE(out_MEMORY_OUT_TYPE      , memory_out_type      );
+#endif
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RD  , memory_out_write_rd  );
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RD   , memory_out_data_rd   );
+//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE  , memory_out_write_re  );
+//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE, memory_out_num_reg_re);
+//  PORT_WRITE(out_MEMORY_OUT_DATA_RE   , memory_out_data_re   );
+    PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception );
+
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 59)
@@ -0,0 +1,234 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::function_speculative_load_commit_transition"
+  void Load_store_unit::function_speculative_load_commit_transition (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    if (PORT_READ(in_NRESET) == 0)
+      {
+	// Reset : clear all queue
+	_speculative_access_queue_control->clear();
+	internal_MEMORY_STORE_QUEUE_PTR_READ = 0;
+	internal_MEMORY_LOAD_QUEUE_PTR_READ  = 0;
+
+	for (uint32_t i=0; i< _param->_size_store_queue             ; i++)
+	  _store_queue              [i]._state = STORE_QUEUE_EMPTY;
+
+	for (uint32_t i=0; i< _param->_size_load_queue              ; i++)
+	  _load_queue               [i]._state = LOAD_QUEUE_EMPTY;
+
+	for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++)
+	  _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY;
+      }
+    else
+      {
+	//================================================================
+	// Interface "MEMORY_IN"
+	//================================================================
+
+        if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and
+            (    internal_MEMORY_IN_ACK  == 1))
+          {
+	    // Test operation :
+	    //~~~~~~~~~~~~~~~~~
+	    //  store  in store_queue
+	    //  load   in speculation_access_queue
+	    //  others in speculation_access_queue
+
+	    Toperation_t    operation           = PORT_READ(in_MEMORY_IN_OPERATION);
+	    Tgeneral_data_t address             = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
+						   PORT_READ(in_MEMORY_IN_DATA_RA ));
+	    
+	    bool            exception_alignement= (mask_memory_access(operation) & address) != 0;
+						    
+	    if (is_operation_memory_store(operation) == true)
+	      {
+		// =======================
+		// ===== STORE_QUEUE =====
+		// =======================
+		// There a two store request type :
+		//   - first is operation with address and data
+		//   - second is the information of re order buffer : the store become not speculative and can access at the data cache
+
+		log_printf(TRACE,Load_store_unit,FUNCTION,"store_queue");
+		log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");
+		
+		// Write pointer is define in rename stage :
+		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
+		log_printf(TRACE,Load_store_unit,FUNCTION,"   * index         : %d",index);
+		
+		// Need read : state and exception.
+		Tstore_queue_state_t old_state     = _store_queue [index]._state;
+		Tstore_queue_state_t new_state     = old_state;
+		bool                 update_info   = false;
+
+		Texception_t         old_exception = _store_queue [index]._exception;
+		Texception_t         new_exception = old_exception;
+
+		// Compute next state
+		switch (old_state)
+		  {
+		  case STORE_QUEUE_EMPTY                   :
+		    {
+		      if (is_operation_memory_store_head(operation) == true)
+			{
+			  new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE;
+
+			  // test if is a speculation
+			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+			    new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+			}
+		      else
+			{
+			  new_state = STORE_QUEUE_VALID_SPECULATIVE;
+
+			  // Test if have an exception
+			  if (exception_alignement == true)
+			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+			  else
+			    new_exception = EXCEPTION_MEMORY_NONE;
+
+			  update_info = true;
+			}
+		      break;
+		    }
+		  case STORE_QUEUE_NO_VALID_NO_SPECULATIVE :
+		    {
+// 		      if (is_operation_memory_store_head(operation) == false)
+// 			{
+			  new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+
+			  // Test if have a new exception (priority : miss_speculation)
+			  if ((old_exception == EXCEPTION_MEMORY_NONE) and
+			      (exception_alignement == true))
+			    new_exception = EXCEPTION_MEMORY_ALIGNMENT;
+
+			  update_info = true;
+			  break;
+// 			}
+		    }
+		  case STORE_QUEUE_VALID_SPECULATIVE       :
+		    {
+// 		      if (is_operation_memory_store_head(operation) == true)
+// 			{
+			  new_state = STORE_QUEUE_VALID_NO_SPECULATIVE;
+
+			  if (operation == OPERATION_MEMORY_STORE_HEAD_KO)
+			    new_exception = EXCEPTION_MEMORY_MISS_SPECULATION;
+
+			  break;
+// 			}
+		    }
+		  case STORE_QUEUE_VALID_NO_SPECULATIVE    :
+		  case STORE_QUEUE_COMMIT                  :
+		    {
+		      ErrorMorpheo("<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation");
+		    }
+		  }
+
+		_store_queue [index]._state     = new_state;
+		_store_queue [index]._exception = new_exception;
+		
+		if (update_info == true)
+		  {
+		    log_printf(TRACE,Load_store_unit,FUNCTION,"   * Update information");
+
+		    _store_queue [index]._context_id           = PORT_READ(in_MEMORY_IN_CONTEXT_ID  );
+		    _store_queue [index]._packet_id            = PORT_READ(in_MEMORY_IN_PACKET_ID   );
+#ifdef HAVE_MEMORY_OUT_OPERATION
+		    _store_queue [index]._operation            = operation;
+#endif
+#ifdef HAVE_MEMORY_OUT_TYPE
+		    _store_queue [index]._type                 = PORT_READ(in_MEMORY_IN_TYPE        );
+#endif
+		    _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
+		    _store_queue [index]._address              = address;
+		    _store_queue [index]._wdata                = PORT_READ(in_MEMORY_IN_DATA_RB     );
+//                  _store_queue [index]._write_rd             = PORT_READ(in_MEMORY_IN_WRITE_RD    );
+//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  );
+		  }
+	      }
+	    else
+	      {
+// 		// ====================================
+// 		// ===== SPECULATIVE_ACCESS_QUEUE =====
+// 		// ====================================
+
+// 		// In speculative access queue, they are many type's request
+// 		log_printf(TRACE,Load_store_unit,FUNCTION,"speculative_access_queue");
+// 		log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH");
+		
+// 		// Write in reservation station
+// 		uint32_t index = _speculative_access_queue_control->push();
+		
+// 		log_printf(TRACE,Load_store_unit,FUNCTION,"   * index         : %d",index);
+	      }
+	  }
+
+	//================================================================
+	// Interface "MEMORY_OUT"
+	//================================================================
+
+        if ((    internal_MEMORY_OUT_VAL  == 1) and
+            (PORT_READ(in_MEMORY_OUT_ACK) == 1))
+          {
+	    switch (internal_MEMORY_OUT_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY;
+		  
+		  internal_MEMORY_STORE_QUEUE_PTR_READ = (internal_MEMORY_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		break;
+	      }
+	  }
+      }
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_dcache.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_dcache.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_dcache.cpp	(revision 59)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::genMealy_dcache"
+  void Load_store_unit::genMealy_dcache (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    (this->*function_genMealy_dcache) ();
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_insert.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_insert.cpp	(revision 59)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::genMealy_insert"
+  void Load_store_unit::genMealy_insert (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    (this->*function_genMealy_insert) ();
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_retire.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_retire.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMealy_retire.cpp	(revision 59)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::genMealy_retire"
+  void Load_store_unit::genMealy_retire (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    (this->*function_genMealy_retire) ();
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMoore.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_genMoore.cpp	(revision 59)
@@ -0,0 +1,43 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::genMoore"
+  void Load_store_unit::genMoore (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    (this->*function_genMoore) ();
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_statistics.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_statistics.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_statistics.cpp	(revision 59)
@@ -0,0 +1,43 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::statistics"
+  string Load_store_unit::statistics (uint32_t depth)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    string txt = _stat->print(depth);
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return txt;
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_transition.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_transition.cpp	(revision 59)
@@ -0,0 +1,51 @@
+#ifdef SYSTEMC
+//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::transition"
+  void Load_store_unit::transition (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    (this->*function_transition) ();
+
+#ifdef STATISTICS
+    _stat->add();
+#endif    
+
+#ifdef VHDL_TESTBENCH
+    vhdl_testbench_transition ();
+#endif
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
+//#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl.cpp	(revision 59)
@@ -0,0 +1,52 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Vhdl.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::vhdl"
+  void Load_store_unit::vhdl (void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    Vhdl * vhdl = new Vhdl (_name);
+
+    _interfaces->set_port(vhdl);
+    _component->vhdl_instance(vhdl);
+
+    vhdl_declaration (vhdl);
+    vhdl_body        (vhdl);
+
+    vhdl->generate_file();
+
+    delete vhdl;
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_body.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_body.cpp	(revision 59)
@@ -0,0 +1,39 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::vhdl_body"
+  void Load_store_unit::vhdl_body (Vhdl * & vhdl)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    vhdl->set_body ("");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_declaration.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_declaration.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_declaration.cpp	(revision 59)
@@ -0,0 +1,38 @@
+#ifdef VHDL
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::vhdl_declaration"
+  void Load_store_unit::vhdl_declaration (Vhdl * & vhdl)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_testbench_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_testbench_transition.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_vhdl_testbench_transition.cpp	(revision 59)
@@ -0,0 +1,44 @@
+#ifdef VHDL_TESTBENCH
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::vhdl_testbench_transition"
+  void Load_store_unit::vhdl_testbench_transition ()
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    // Evaluation before read the ouput signal
+//     sc_start(0);
+
+    _interfaces->testbench();
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 59)
@@ -0,0 +1,107 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::Parameters"
+  Parameters::Parameters (uint32_t            size_store_queue       ,
+			  uint32_t            size_load_queue        ,
+			  uint32_t            nb_port_check          ,
+			  uint32_t            size_speculative_access_queue,
+			  Tspeculative_load_t speculative_load       ,
+			  uint32_t            nb_context             ,
+			  uint32_t            nb_packet              ,
+			  uint32_t            size_general_data      ,
+			  uint32_t            nb_general_register    ,
+			  uint32_t            nb_operation           ,
+			  uint32_t            nb_type                			  
+			  ):
+    _size_store_queue        (size_store_queue       ),
+    _size_load_queue         (size_load_queue        ),
+    _size_speculative_access_queue (size_speculative_access_queue),
+    _nb_port_check           (nb_port_check          ),
+    _speculative_load        (speculative_load       ),
+    _nb_context              (nb_context             ),
+    _nb_packet               (nb_packet              ),
+    _size_general_data       (size_general_data      ),
+    _nb_general_register     (nb_general_register    ),
+    _nb_operation            (nb_operation           ),
+    _nb_type                 (nb_type                ),
+    
+    _size_address_store_queue              (static_cast<uint32_t>(ceil(log2(size_store_queue             )))),
+    _size_address_load_queue               (static_cast<uint32_t>(ceil(log2(size_load_queue              )))),
+    _size_address_speculative_access_queue (static_cast<uint32_t>(ceil(log2(size_speculative_access_queue)))),
+
+    _size_context_id         (static_cast<uint32_t>(ceil(log2(nb_context         )))),
+    _size_packet_id          (static_cast<uint32_t>(ceil(log2(nb_packet          )))),
+    _size_general_register   (static_cast<uint32_t>(ceil(log2(nb_general_register)))),
+    _size_operation          (static_cast<uint32_t>(ceil(log2(nb_operation       )))),
+    _size_type               (static_cast<uint32_t>(ceil(log2(nb_type            ))))  
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    test();
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+  
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::Parameters (copy)"
+  Parameters::Parameters (Parameters & param):
+    _size_store_queue        (param._size_store_queue       ),
+    _size_load_queue         (param._size_load_queue        ),
+    _size_speculative_access_queue (param._size_speculative_access_queue),
+    _nb_port_check           (param._nb_port_check          ),
+    _speculative_load        (param._speculative_load       ),
+    _nb_context              (param._nb_context             ),
+    _nb_packet               (param._nb_packet              ),
+    _size_general_data       (param._size_general_data      ),
+    _nb_general_register     (param._nb_general_register    ),
+    _nb_operation            (param._nb_operation           ),
+    _nb_type                 (param._nb_type                ),
+
+    _size_address_store_queue              (param._size_address_store_queue             ),
+    _size_address_load_queue               (param._size_address_load_queue              ),
+    _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
+
+    _size_context_id         (param._nb_context             ),
+    _size_packet_id          (param._nb_packet              ),
+    _size_general_register   (param._nb_general_register    ),
+    _size_operation          (param._nb_operation           ),
+    _size_type               (param._nb_type                )
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    test();
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::~Parameters"
+  Parameters::~Parameters () 
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 59)
@@ -0,0 +1,59 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::msg_error"
+  string Parameters::msg_error(void)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    
+    string msg = "";
+
+    switch (_speculative_load)
+      {
+      case SPECULATIVE_LOAD_COMMIT :
+	{
+	  break;
+	}
+      case NO_SPECULATIVE_LOAD     :
+      case SPECULATIVE_LOAD_ACCESS :
+      case SPECULATIVE_LOAD_BYPASS :
+      default                      :
+	{
+	  msg += "  - Speculative load scheme is not supported : " +toString(_speculative_load);
+	  break;
+	}
+      }
+
+    return msg;
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp	(revision 59)
@@ -0,0 +1,71 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h"
+#include "Behavioural/include/XML.h"
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::print"
+  string Parameters::print (uint32_t depth)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    XML xml ("load_store_unit");
+
+    xml.balise_open("load_store_unit");
+    xml.singleton_begin("size_store_queue       "); xml.attribut("value",toString(_size_store_queue       )); xml.singleton_end();
+    xml.singleton_begin("size_load_queue        "); xml.attribut("value",toString(_size_load_queue        )); xml.singleton_end();
+    xml.singleton_begin("size_speculative_access_queue"); xml.attribut("value",toString(_size_speculative_access_queue)); xml.singleton_end();
+    xml.singleton_begin("nb_port_check          "); xml.attribut("value",toString(_nb_port_check          )); xml.singleton_end();
+    xml.singleton_begin("speculative_load       "); xml.attribut("value",toString(_speculative_load       )); xml.singleton_end();
+    xml.singleton_begin("nb_context             "); xml.attribut("value",toString(_nb_context             )); xml.singleton_end();
+    xml.singleton_begin("nb_packet              "); xml.attribut("value",toString(_nb_packet              )); xml.singleton_end();
+    xml.singleton_begin("size_general_data      "); xml.attribut("value",toString(_size_general_data      )); xml.singleton_end();
+    xml.singleton_begin("nb_general_register    "); xml.attribut("value",toString(_nb_general_register    )); xml.singleton_end();
+    xml.singleton_begin("nb_operation           "); xml.attribut("value",toString(_nb_operation           )); xml.singleton_end();
+    xml.singleton_begin("nb_type                "); xml.attribut("value",toString(_nb_type                )); xml.singleton_end();
+    xml.balise_close();
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+    
+    return xml.get_body(depth);
+  };
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::operator<<"
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters & x)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    output_stream << x.print(0);
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return output_stream;
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics.cpp	(revision 59)
@@ -0,0 +1,52 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::Statistics"
+  Statistics::Statistics (string                                        name                       ,
+			  morpheo::behavioural::Parameters_Statistics * parameters_statistics      ,
+			  Parameters                                  * parameters
+			  ) :
+    morpheo::behavioural::Statistics(name                  ,
+				     parameters_statistics ),
+    _parameters(parameters)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+  
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::~Statistics"
+  Statistics::~Statistics () 
+  { 
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_add.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_add.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_add.cpp	(revision 59)
@@ -0,0 +1,41 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::add"
+  void Statistics::add ()
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print.cpp	(revision 59)
@@ -0,0 +1,65 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::print"
+  string Statistics::print (uint32_t depth)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "<load_store_unit name=\"" << _name << "\" >" << endl
+        << print_body(depth+1) << endl
+	<< tab << "</load_store_unit>" << endl;
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return msg.str();
+  };
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::operator<<"
+  ostream& operator<< (ostream& output_stream ,
+		       morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Statistics & x)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    output_stream << x.print(0);
+
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return output_stream;
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print_body.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Statistics_print_body.cpp	(revision 59)
@@ -0,0 +1,49 @@
+#ifdef STATISTICS
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ */
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"
+
+#include <sstream>
+using namespace std;
+
+namespace morpheo                    {
+namespace behavioural {
+namespace core {
+namespace multi_execute_loop {
+namespace execute_loop {
+namespace multi_execute_unit {
+namespace execute_unit {
+namespace load_store_unit {
+
+
+#undef  FUNCTION
+#define FUNCTION "Load_store_unit::print_body"
+  string Statistics::print_body (uint32_t depth)
+  {
+    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    string        tab = string(depth,'\t');
+    ostringstream msg;
+
+    msg << tab << "";
+    
+    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return msg.str();
+  };
+
+}; // end namespace load_store_unit
+}; // end namespace execute_unit
+}; // end namespace multi_execute_unit
+}; // end namespace execute_loop
+}; // end namespace multi_execute_loop
+}; // end namespace core
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile.mkf
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile.mkf	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile.mkf	(revision 59)
@@ -0,0 +1,144 @@
+#
+# Makefile generated by MKF configure script
+#
+
+all: RegisterFile_Multi_Banked_0.ngc RegisterFile_Multi_Banked_1.ngc RegisterFile_Multi_Banked_2.ngc RegisterFile_Multi_Banked_3.ngc RegisterFile_Multi_Banked_4.ngc RegisterFile_Multi_Banked_5.ngc
+
+RegisterFile_Multi_Banked_0.ngc: RegisterFile_Multi_Banked_0.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_0 -ifn RegisterFile_Multi_Banked_0.prj -ofn RegisterFile_Multi_Banked_0.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_0.prj: RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports.vhdl RegisterFile_Multi_Banked_0.vhdl
+	for i in RegisterFile_Multi_Banked_0_bank_Pack.vhdl RegisterFile_Multi_Banked_0_bank.vhdl RegisterFile_Multi_Banked_0_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_0_select_4_ports.vhdl RegisterFile_Multi_Banked_0.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_0.prj
+
+RegisterFile_Multi_Banked_0_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_0_bank.vhdl:
+
+RegisterFile_Multi_Banked_0_Pack.vhdl:
+
+RegisterFile_Multi_Banked_0_select_4_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_0_select_4_ports.vhdl:
+
+RegisterFile_Multi_Banked_0.vhdl:
+
+RegisterFile_Multi_Banked_1.ngc: RegisterFile_Multi_Banked_1.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_1 -ifn RegisterFile_Multi_Banked_1.prj -ofn RegisterFile_Multi_Banked_1.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_1.prj: RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports.vhdl RegisterFile_Multi_Banked_1.vhdl
+	for i in RegisterFile_Multi_Banked_1_bank_Pack.vhdl RegisterFile_Multi_Banked_1_bank.vhdl RegisterFile_Multi_Banked_1_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_1_select_4_ports.vhdl RegisterFile_Multi_Banked_1.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_1.prj
+
+RegisterFile_Multi_Banked_1_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_1_bank.vhdl:
+
+RegisterFile_Multi_Banked_1_Pack.vhdl:
+
+RegisterFile_Multi_Banked_1_select_4_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_1_select_4_ports.vhdl:
+
+RegisterFile_Multi_Banked_1.vhdl:
+
+RegisterFile_Multi_Banked_2.ngc: RegisterFile_Multi_Banked_2.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_2 -ifn RegisterFile_Multi_Banked_2.prj -ofn RegisterFile_Multi_Banked_2.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_2.prj: RegisterFile_Multi_Banked_2_bank_Pack.vhdl RegisterFile_Multi_Banked_2_bank.vhdl RegisterFile_Multi_Banked_2_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports.vhdl RegisterFile_Multi_Banked_2.vhdl
+	for i in RegisterFile_Multi_Banked_2_bank_Pack.vhdl RegisterFile_Multi_Banked_2_bank.vhdl RegisterFile_Multi_Banked_2_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_2_select_4_ports.vhdl RegisterFile_Multi_Banked_2.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_2.prj
+
+RegisterFile_Multi_Banked_2_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_2_bank.vhdl:
+
+RegisterFile_Multi_Banked_2_Pack.vhdl:
+
+RegisterFile_Multi_Banked_2_select_4_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_2_select_4_ports.vhdl:
+
+RegisterFile_Multi_Banked_2.vhdl:
+
+RegisterFile_Multi_Banked_3.ngc: RegisterFile_Multi_Banked_3.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_3 -ifn RegisterFile_Multi_Banked_3.prj -ofn RegisterFile_Multi_Banked_3.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_3.prj: RegisterFile_Multi_Banked_3_bank_Pack.vhdl RegisterFile_Multi_Banked_3_bank.vhdl RegisterFile_Multi_Banked_3_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports.vhdl RegisterFile_Multi_Banked_3.vhdl
+	for i in RegisterFile_Multi_Banked_3_bank_Pack.vhdl RegisterFile_Multi_Banked_3_bank.vhdl RegisterFile_Multi_Banked_3_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_3_select_8_ports.vhdl RegisterFile_Multi_Banked_3.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_3.prj
+
+RegisterFile_Multi_Banked_3_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_3_bank.vhdl:
+
+RegisterFile_Multi_Banked_3_Pack.vhdl:
+
+RegisterFile_Multi_Banked_3_select_8_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_3_select_8_ports.vhdl:
+
+RegisterFile_Multi_Banked_3.vhdl:
+
+RegisterFile_Multi_Banked_4.ngc: RegisterFile_Multi_Banked_4.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_4 -ifn RegisterFile_Multi_Banked_4.prj -ofn RegisterFile_Multi_Banked_4.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_4.prj: RegisterFile_Multi_Banked_4_bank_Pack.vhdl RegisterFile_Multi_Banked_4_bank.vhdl RegisterFile_Multi_Banked_4_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports.vhdl RegisterFile_Multi_Banked_4.vhdl
+	for i in RegisterFile_Multi_Banked_4_bank_Pack.vhdl RegisterFile_Multi_Banked_4_bank.vhdl RegisterFile_Multi_Banked_4_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_4_select_8_ports.vhdl RegisterFile_Multi_Banked_4.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_4.prj
+
+RegisterFile_Multi_Banked_4_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_4_bank.vhdl:
+
+RegisterFile_Multi_Banked_4_Pack.vhdl:
+
+RegisterFile_Multi_Banked_4_select_8_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_4_select_8_ports.vhdl:
+
+RegisterFile_Multi_Banked_4.vhdl:
+
+RegisterFile_Multi_Banked_5.ngc: RegisterFile_Multi_Banked_5.prj
+	echo run -keep_hierarchy yes -iobuf no -top RegisterFile_Multi_Banked_5 -ifn RegisterFile_Multi_Banked_5.prj -ofn RegisterFile_Multi_Banked_5.ngc -p xc5vlx330t-2ff1738 -ifmt mixed | xst
+
+RegisterFile_Multi_Banked_5.prj: RegisterFile_Multi_Banked_5_bank_Pack.vhdl RegisterFile_Multi_Banked_5_bank.vhdl RegisterFile_Multi_Banked_5_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports.vhdl RegisterFile_Multi_Banked_5.vhdl
+	for i in RegisterFile_Multi_Banked_5_bank_Pack.vhdl RegisterFile_Multi_Banked_5_bank.vhdl RegisterFile_Multi_Banked_5_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports_Pack.vhdl RegisterFile_Multi_Banked_5_select_8_ports.vhdl RegisterFile_Multi_Banked_5.vhdl ; do echo "vhdl work $$i" ; done > RegisterFile_Multi_Banked_5.prj
+
+RegisterFile_Multi_Banked_5_bank_Pack.vhdl:
+
+RegisterFile_Multi_Banked_5_bank.vhdl:
+
+RegisterFile_Multi_Banked_5_Pack.vhdl:
+
+RegisterFile_Multi_Banked_5_select_8_ports_Pack.vhdl:
+
+RegisterFile_Multi_Banked_5_select_8_ports.vhdl:
+
+RegisterFile_Multi_Banked_5.vhdl:
+
+clean:
+	rm -f RegisterFile_Multi_Banked_0.ngc
+	rm -f RegisterFile_Multi_Banked_0.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_0.prj
+	rm -f RegisterFile_Multi_Banked_1.ngc
+	rm -f RegisterFile_Multi_Banked_1.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_1.prj
+	rm -f RegisterFile_Multi_Banked_2.ngc
+	rm -f RegisterFile_Multi_Banked_2.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_2.prj
+	rm -f RegisterFile_Multi_Banked_3.ngc
+	rm -f RegisterFile_Multi_Banked_3.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_3.prj
+	rm -f RegisterFile_Multi_Banked_4.ngc
+	rm -f RegisterFile_Multi_Banked_4.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_4.prj
+	rm -f RegisterFile_Multi_Banked_5.ngc
+	rm -f RegisterFile_Multi_Banked_5.lso
+	rm -f -r xst
+	rm -f RegisterFile_Multi_Banked_5.prj
+
+re: clean all
+
+install:
+
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_vhdl_body.cpp	(revision 59)
@@ -38,5 +38,7 @@
     if (_param->_encoding_compact)
       {
-	vhdl->set_body ("out_ENTITY     <=     internal_entity"+std_logic_range(_param->_size_entity-1,                  0)+";");
+	string range = ((_param->_size_entity-1)==0)?"(0)":std_logic_range(_param->_size_entity-1,0);
+
+	vhdl->set_body ("out_ENTITY     <=     internal_entity"+range+";");
 	vhdl->set_body ("out_ENTITY_ACK <= not internal_entity"+std_logic_range(_param->_size_entity  ,_param->_size_entity)+";");
       }	   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 59)
@@ -0,0 +1,583 @@
+#ifndef morpheo_behavioural_Constants_h
+#define morpheo_behavioural_Constants_h
+
+namespace morpheo {
+namespace behavioural {
+
+  //=========================================================[ Type ]=====
+#define TYPE_MEMORY                              0x1      // 00001  
+
+  //====================================================[ Operation ]=====
+
+  //-------------------------------------------------------[ Memory ]-----
+#define OPERATION_MEMORY_LOAD_8_Z                0x0      // 000_0000
+#define OPERATION_MEMORY_LOAD_16_Z               0x20     // 010_0000
+#define OPERATION_MEMORY_LOAD_32_Z               0x40     // 100_0000
+#define OPERATION_MEMORY_LOAD_64_Z               0x60     // 110_0000
+#define OPERATION_MEMORY_LOAD_8_S                0x10     // 001_0000
+#define OPERATION_MEMORY_LOAD_16_S               0x30     // 011_0000
+#define OPERATION_MEMORY_LOAD_32_S               0x50     // 101_0000
+#define OPERATION_MEMORY_LOAD_64_S               0x70     // 111_0000
+
+#define OPERATION_MEMORY_STORE_8                 0x8      // 000_1000
+#define OPERATION_MEMORY_STORE_16                0x9      // 000_1001
+#define OPERATION_MEMORY_STORE_32                0xa      // 000_1010
+#define OPERATION_MEMORY_STORE_64                0xb      // 000_1011
+#define OPERATION_MEMORY_STORE_HEAD_OK           0xc      // 000_1100
+#define OPERATION_MEMORY_STORE_HEAD_KO           0xd      // 000_1101
+
+#define OPERATION_MEMORY_LOCK                    0x1      // 000_0001
+#define OPERATION_MEMORY_INVALIDATE              0x2      // 000_0010
+#define OPERATION_MEMORY_PREFETCH                0x3      // 000_0011
+#define OPERATION_MEMORY_FLUSH                   0x6      // 000_0110
+#define OPERATION_MEMORY_SYNCHRONIZATION         0x7      // 000_0111
+
+#define is_operation_memory_load(x)             \
+	((x == OPERATION_MEMORY_LOAD_8_Z ) or	\
+	 (x == OPERATION_MEMORY_LOAD_16_Z) or	\
+	 (x == OPERATION_MEMORY_LOAD_32_Z) or	\
+	 (x == OPERATION_MEMORY_LOAD_64_Z) or	\
+	 (x == OPERATION_MEMORY_LOAD_8_S ) or	\
+	 (x == OPERATION_MEMORY_LOAD_16_S) or	\
+	 (x == OPERATION_MEMORY_LOAD_32_S) or	\
+	 (x == OPERATION_MEMORY_LOAD_64_S) )
+
+#define is_operation_memory_store(x)                    \
+	((x == OPERATION_MEMORY_STORE_8      ) or	\
+	 (x == OPERATION_MEMORY_STORE_16     ) or	\
+	 (x == OPERATION_MEMORY_STORE_32     ) or	\
+	 (x == OPERATION_MEMORY_STORE_64     ) or	\
+	 (x == OPERATION_MEMORY_STORE_HEAD_OK) or	\
+	 (x == OPERATION_MEMORY_STORE_HEAD_KO))
+
+#define is_operation_memory_store_head(x)               \
+	((x == OPERATION_MEMORY_STORE_HEAD_OK) or	\
+	 (x == OPERATION_MEMORY_STORE_HEAD_KO))
+
+#define MEMORY_ACCESS_8                          0x0
+#define MEMORY_ACCESS_16                         0x1
+#define MEMORY_ACCESS_32                         0x2
+#define MEMORY_ACCESS_64                         0x3
+
+#define MASK_MEMORY_ACCESS_8                     0x0
+#define MASK_MEMORY_ACCESS_16                    0x1
+#define MASK_MEMORY_ACCESS_32                    0x3
+#define MASK_MEMORY_ACCESS_64                    0x7
+
+#define memory_access(x)                                                         \
+	(((x==OPERATION_MEMORY_LOAD_16_Z)or					 \
+	   (x==OPERATION_MEMORY_LOAD_16_S)or					 \
+	   (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16:			 \
+	  (((x==OPERATION_MEMORY_LOAD_32_Z)or					 \
+	    (x==OPERATION_MEMORY_LOAD_32_S)or					 \
+	    (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32:			 \
+	   (((x==OPERATION_MEMORY_LOAD_64_Z)or					 \
+	     (x==OPERATION_MEMORY_LOAD_64_S)or					 \
+	     (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8)))
+    
+#define mask_memory_access(x)                                                    \
+	(((x==OPERATION_MEMORY_LOAD_16_Z)or					 \
+	   (x==OPERATION_MEMORY_LOAD_16_S)or					 \
+	   (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16:	         \
+	  (((x==OPERATION_MEMORY_LOAD_32_Z)or					 \
+	    (x==OPERATION_MEMORY_LOAD_32_S)or					 \
+	    (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32:		 \
+	   (((x==OPERATION_MEMORY_LOAD_64_Z)or					 \
+	     (x==OPERATION_MEMORY_LOAD_64_S)or					 \
+	     (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8)))
+
+    
+  //====================================================[ Exception ]=====
+  // Exception - OpenRISC
+
+#define EXCEPTION_NONE                           0x00 // none exception
+#define EXCEPTION_RESET                          0x01 // software or hardware reset
+#define EXCEPTION_BUS_ERROR                      0x02 // Access at a invalid physical adress
+#define EXCEPTION_DATA_PAGE                      0x03 // No matching or page violation protection in pages tables
+#define EXCEPTION_INSTRUCTION_PAGE               0x04 // No matching or page violation protection in pages tables
+#define EXCEPTION_TICK_TIMER                     0x05 // Tick timer interruption
+#define EXCEPTION_ALIGNMENT                      0x06 // Load/Store access is not aligned
+#define EXCEPTION_ILLEGAL_INSTRUCTION            0x07 // Instruction is illegal (no implemented)
+#define EXCEPTION_INTERRUPT                      0x08 // External interruption 
+#define EXCEPTION_DATA_TLB                       0x09 // DTLB miss
+#define EXCEPTION_INSTRUCTION_TLB                0x0a // ITLB miss
+#define EXCEPTION_RANGE                          0x0b // Overflow or access at a unimplemented register or context
+#define EXCEPTION_SYSCALL                        0x0c // System Call
+#define EXCEPTION_FLOATING_POINT                 0x0d // Caused by a floating instruction
+#define EXCEPTION_TRAP                           0x0e // L.trap or debug unit
+#define EXCEPTION_RESERVED_0                     0x0f // Reserved for a futur usage
+#define EXCEPTION_RESERVED_1                     0x10 // Reserved for a futur usage
+#define EXCEPTION_RESERVED_2                     0x11 // Reserved for a futur usage
+#define EXCEPTION_RESERVED_3                     0x12 // Reserved for a futur usage
+#define EXCEPTION_RESERVED_4                     0x13 // Reserved for a futur usage
+#define EXCEPTION_RESERVED_5                     0x14 // Reserved for a futur usage
+#define EXCEPTION_RESERVED_6                     0x15 // Reserved for implemented specific exceptions
+#define EXCEPTION_RESERVED_7                     0x16 // Reserved for implemented specific exceptions
+#define EXCEPTION_RESERVED_8                     0x17 // Reserved for implemented specific exceptions
+#define EXCEPTION_RESERVED_9                     0x18 // Reserved for implemented specific exceptions
+#define EXCEPTION_CUSTOM_0                       0x19 // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_1                       0x1a // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_2                       0x1b // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_3                       0x1c // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_4                       0x1d // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_5                       0x1e // Reserved for custom exceptions
+#define EXCEPTION_CUSTOM_6                       0x1f // Reserved for custom exceptions
+
+  // Exception Execution
+#define EXCEPTION_MEMORY_NONE                    0x0  // Load/Store access is not aligned
+#define EXCEPTION_MEMORY_ALIGNMENT               0x1  // Load/Store access is not aligned
+#define EXCEPTION_MEMORY_DATA_TLB                0x2  // DTLB miss
+#define EXCEPTION_MEMORY_DATA_PAGE               0x3  // No matching or page violation protection in pages tables
+#define EXCEPTION_MEMORY_BUS_ERROR               0x4  // Access at a invalid physical address
+#define EXCEPTION_MEMORY_MISS_SPECULATION        0x5  // Load miss speculation
+
+  /*
+#define                 _size_instruction             32
+#define                 _size_instruction_log2        5
+
+  //----------------------------------------------------[ Operation ]-----
+// #define                 _nb_operation                 32
+// #define                 _size_operation               5
+
+#define                 _operation_none               0x0
+#define                 _operation_l_adds             0x1
+#define                 _operation_l_addu             0x2
+#define                 _operation_l_subs             0x3
+#define                 _operation_l_and              0x4
+#define                 _operation_l_or               0x5
+#define                 _operation_l_xor              0x6
+#define                 _operation_l_cmove            0x7
+#define                 _operation_l_read_imm         0x8
+#define                 _operation_l_movhi            0x9
+#define                 _operation_l_muls             0xa
+#define                 _operation_l_mulu             0xb
+#define                 _operation_l_divs             0xc
+#define                 _operation_l_divu             0xd
+#define                 _operation_l_exts             0xe
+#define                 _operation_l_extz             0xf
+#define                 _operation_l_ff1              0x10
+#define                 _operation_l_fl1              0x11
+#define                 _operation_l_sll              0x12
+#define                 _operation_l_sla              0x13
+#define                 _operation_l_srl              0x14
+#define                 _operation_l_ror              0x15
+#define                 _operation_l_cmp_eq           0x16
+#define                 _operation_l_cmp_ne           0x17
+#define                 _operation_l_cmp_ges          0x18
+#define                 _operation_l_cmp_geu          0x19
+#define                 _operation_l_cmp_gts          0x1a
+#define                 _operation_l_cmp_gtu          0x1b
+#define                 _operation_l_cmp_les          0x1c
+#define                 _operation_l_cmp_leu          0x1d
+#define                 _operation_l_cmp_lts          0x1e
+#define                 _operation_l_cmp_ltu          0x1f
+
+  //--------------------------------------------------[ destination ]-----
+#define                 _size_destination1            4
+
+#define                  cst_DESTINATION1_NONE        0x0
+#define                 mask_DESTINATION1_GPR         0x1
+#define                 mask_DESTINATION1_MEMORY      0x2
+#define                 mask_DESTINATION1_SPR         0x4
+#define                 mask_DESTINATION1_MAC_UNIT    0x8
+  
+#define                 _size_destination2  3
+
+#define                  cst_DESTINATION2_NONE        0x0
+#define                 mask_DESTINATION2_COMMIT      0x1
+#define                 mask_DESTINATION2_MEMORY      0x2
+#define                 mask_DESTINATION2_SPR         0x4
+  
+  //----------------------------------------------------[ exec_flag ]-----
+#define                 _size_exec_flag               2
+
+#define                 mask_EXEC_FLAG_NONE           0x1
+#define                 mask_EXEC_FLAG_CARRY          0x1
+#define                 mask_EXEC_FLAG_FLAG           0x1
+#define                 mask_EXEC_FLAG_OVERFLOW       0x2
+
+  //---------------------------------------------------[ exec_excep ]-----
+#define                  _size_exec_excep             1
+
+#define                 mask_EXEC_EXCEP_NONE          0x0
+#define                 mask_EXEC_EXCEP_RANGE         0x1
+  
+  //----------------------------------------------------[ Condition ]-----
+#define                 _size_condition               3
+    
+#define                  cst_CONDITION_UNCONDITIONAL  0x0           // None condition (jump)
+#define                 mask_CONDITION_CONDITIONAL    0x2           
+#define                 mask_CONDITION_CONDITIONAL_NF 0x0           // Branch if Flag is clear 
+#define                 mask_CONDITION_CONDITIONAL_F  0x1           // Branch if Flag is set   
+#define                 mask_CONDITION_REG            0x4           // Branch if a register is read
+#define                 mask_CONDITION_STACK          0x8           // Branch with pop  in stack pointer
+
+  //-------------------------------------------------[ branch_state ]-----
+#define                 cst_BRANCH_STATE_NONE         0x0           // 0 0
+#define                 cst_BRANCH_STATE_NSPEC_TAKE   0x1           // 0 1  -> incondionnal
+#define                 cst_BRANCH_STATE_SPEC_NTAKE   0x2           // 1 0
+#define                 cst_BRANCH_STATE_SPEC_TAKE    0x3           // 1 1
+  */
+
+  /*
+#define M_CPU_SIZE_INST       32
+
+//----------------------------------------------------
+// Exception type
+//----------------------------------------------------
+
+#define M_CPU_LOG2_NB_EXCP    5
+#define M_CPU_NB_EXCP         32
+
+#define EXCP_NO               0x00          // none exception
+#define EXCP_RESET            0x01          // software or hardware reset
+#define EXCP_BERR             0x02          // Access at a invalid physical adress
+#define EXCP_D_PAGE           0x03          // No matching or page violation protection in pages tables
+#define EXCP_I_PAGE           0x04          // No matching or page violation protection in pages tables
+#define EXCP_TICK_TIMER       0x05          // Tick timer interruption
+#define EXCP_ALIGNMENT        0x06          // Load/Store access is not aligned
+#define EXCP_ILL_INST         0x07          // Instruction is illegal (no implemented)
+#define EXCP_IRQ              0x08          // External interruption 
+#define EXCP_D_TLB            0x09          // DTLB miss
+#define EXCP_I_TLB            0x0a          // ITLB miss
+#define EXCP_RANGE            0x0b          // Overflow or access at a unimplemented register or context
+#define EXCP_SYSCALL          0x0c          // System Call
+#define EXCP_FP               0x0d          // Caused by a floating instruction
+#define EXCP_TRAP             0x0e          // L.trap or debug unit
+#define EXCP_RES0             0x0f          // Reserved for a futur usage
+#define EXCP_RES1             0x10          // Reserved for a futur usage
+#define EXCP_RES2             0x11          // Reserved for a futur usage
+#define EXCP_RES3             0x12          // Reserved for a futur usage
+#define EXCP_RES4             0x13          // Reserved for a futur usage
+#define EXCP_RES5             0x14          // Reserved for a futur usage
+#define EXCP_RES6             0x15          // Reserved for implemented specific exceptions
+#define EXCP_RES7             0x16          // Reserved for implemented specific exceptions
+#define EXCP_RES8             0x17          // Reserved for implemented specific exceptions
+#define EXCP_RES9             0x18          // Reserved for implemented specific exceptions
+#define EXCP_CUST0            0x19          // Reserved for custom exceptions
+#define EXCP_CUST1            0x1a          // Reserved for custom exceptions
+#define EXCP_CUST2            0x1b          // Reserved for custom exceptions
+#define EXCP_CUST3            0x1c          // Reserved for custom exceptions
+#define EXCP_CUST4            0x1d          // Reserved for custom exceptions
+#define EXCP_CUST5            0x1e          // Reserved for custom exceptions
+#define EXCP_CUST6            0x1f          // Reserved for custom exceptions
+
+//----------------------------------------------------
+// Flags
+//----------------------------------------------------
+
+#define M_CPU_NB_FLAG         3
+
+// Integer flags
+#define FLAG_F                0x1           // Conditionnal branch flag
+#define FLAG_CY               0x2           // Carry was produced by last arithmétic operation
+#define FLAG_OV               0x4           // Overflow occured during last arithmetic operation
+
+// Floating flags
+#define FLAG_OVF              0x004         // Overflow occured during last arithmetic operation
+#define FLAG_UNF              0x008         // Underflow flags
+#define FLAG_SNF              0x010         // Result SNAN
+#define FLAG_QNF              0x020         // Result QNAN
+#define FLAG_ZF               0x040         // Result is nul
+#define FLAG_IXF              0x080         // Result is inexact
+#define FLAG_IVF              0x100         // Result is invalid
+#define FLAG_INF              0x200         // Result is infinite
+#define FLAG_DZF              0x400         // Division by zero
+
+// Position of flag in "rename register SR" (NOT IN "SR")
+#define FLAG_POS_F            0x0           // Conditionnal branch flag
+#define FLAG_POS_CY           0x1           // Carry was produced by last arithmétic operation
+#define FLAG_POS_OV           0x0           // Overflow occured during last arithmetic operation
+
+//----------------------------------------------------
+// Instruction type
+//----------------------------------------------------
+
+#define M_CPU_LOG2_NB_TYPE    4
+
+#define TYPE_NOP              0x0
+#define TYPE_ALU_F            0x1           // Instruction ALU with    flag using (ADD, SUB, ADDC ...)
+#define TYPE_ALU_NF           0x2           // Instruction ALU without flag using (AND, OR ...)
+#define TYPE_MAC              0x3           // Instruction ALU with    utilisation of register HI/LO
+#define TYPE_J                0x4           // Branch instruction
+#define TYPE_SPR_READ         0x5           // Instruction special : l.mfspr
+#define TYPE_SPR_WRITE        0x6           // Instruction special : l.mtspr
+#define TYPE_SPECIAL          0x7           // Instruction execute in decode stage
+#define TYPE_CUSTOM           0x8           // Instruction Custom
+
+#define TYPE_LOAD_Z           0x9           // Load  access (extended by zero)
+#define TYPE_LOAD_S           0xa           // Load  access (sign extended)
+#define TYPE_STORE            0xc           // Store access
+
+//----------------------------------------------------
+// Condition to branch
+//----------------------------------------------------
+
+#define M_CPU_LOG2_NB_COND    4
+
+#define COND_NONE             0x0           // None condition (jump)
+#define COND_F                0x2           // Branch if Flag is set
+#define COND_NF               0x3           // Branch if Flag is clear
+#define COND_REG              0x4           // Branch if a register is read
+#define COND_STACK            0x8           // Branch with pop  in stack pointer
+
+//----------------------------------------------------
+// Event : State and Type
+//----------------------------------------------------
+
+#define EVENT_STATE_NO_EVENT  0             // no event : current case
+#define EVENT_STATE_EVENT     1             // Have a event : make necessary to manage the event
+#define EVENT_STATE_WAITEND   2             // Wait end of manage event (restaure a good context)
+#define EVENT_STATE_END       3             // CPU can continue
+
+#define EVENT_TYPE_MISS       0             // miss of speculation
+#define EVENT_TYPE_EXCP       1             // exception or interruption occure
+
+// SPEC? TAKE?
+#define BRANCH_STATE_NONE         0  // 0     0
+#define BRANCH_STATE_NSPEC_TAKE   1  // 0     1  -> incondionnal
+#define BRANCH_STATE_SPEC_NTAKE   2  // 1     0
+#define BRANCH_STATE_SPEC_TAKE    3  // 1     1
+
+//----------------------------------------------------
+// Name to particular register
+//----------------------------------------------------
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~
+// GENERAL PURPOSE REGISTER
+//~~~~~~~~~~~~~~~~~~~~~~~~~~
+#define M_CPU_LOG2_NB_GPR_LOG 5
+#define M_CPU_NB_GPR_LOG      (1<<M_CPU_LOG2_NB_GPR_LOG)
+
+#define GPR_LOG_LR            0x09          // Link register
+#define REG_PHY_SR            0x00          // Status register
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~
+// SPECIAL PURPOSE REGISTER
+//~~~~~~~~~~~~~~~~~~~~~~~~~~
+#define M_CPU_LOG2_NB_SPR_LOG 1
+#define M_CPU_NB_SPR_LOG      (1<<M_CPU_LOG2_NB_SPR_LOG)
+#define M_CPU_SPR_SIZE_DATA   2             // Size of the most great register 
+
+#define SPR_LOG_SR_F          0x00          // Status register bit F                   (size = 1)
+#define SPR_LOG_SR_CY_OV      0x01          // Status register bit overflow and carry  (size = 2)
+//#define SPR_LOG_SR_LO         0x02          // MAC LSB                                 (size = 32)
+//#define SPR_LOG_SR_HI         0x03          // MAC MSB                                 (size = 32)
+  */
+
+  /*
+//----------------------------------------------------
+// Code Operation (before decode)
+//----------------------------------------------------
+
+// Codop                        - [31:26]      Instructions with immediat
+#define OPCOD_L_J             0x00          // 000_000
+#define OPCOD_L_JAL           0x01          // 000_001
+#define OPCOD_L_BNF           0x03          // 000_011
+#define OPCOD_L_BF            0x04          // 000_100
+#define OPCOD_L_RFE           0x09          // 001_001
+#define OPCOD_L_JR            0x11          // 010_001
+#define OPCOD_L_JALR          0x12          // 010_010
+#define OPCOD_L_MACI          0x13          // 010_011
+#define OPCOD_L_CUST1         0x1c          // 011_100
+#define OPCOD_L_CUST2         0x1d          // 011_101
+#define OPCOD_L_CUST3         0x1e          // 011_110
+#define OPCOD_L_CUST4         0x1f          // 011_111
+#define OPCOD_L_CUST5         0x3c          // 111_100
+#define OPCOD_L_CUST6         0x3d          // 111_101
+#define OPCOD_L_CUST7         0x3e          // 111_110
+#define OPCOD_L_CUST8         0x3f          // 111_111
+#define OPCOD_L_LD            0x20          // 100_000
+#define OPCOD_L_LWZ           0x21          // 100_001
+#define OPCOD_L_LWS           0x22          // 100_010
+#define OPCOD_L_LBZ           0x23          // 100_011
+#define OPCOD_L_LBS           0x24          // 100_100
+#define OPCOD_L_LHZ           0x25          // 100_101
+#define OPCOD_L_LHS           0x26          // 100_110
+#define OPCOD_L_ADDI          0x27          // 100_111
+#define OPCOD_L_ADDIC         0x28          // 101_000
+#define OPCOD_L_ANDI          0x29          // 101_001
+#define OPCOD_L_ORI           0x2a          // 101_010
+#define OPCOD_L_XORI          0x2b          // 101_011
+#define OPCOD_L_MULI          0x2c          // 101_100
+#define OPCOD_L_MFSPR         0x2d          // 101_101
+#define OPCOD_L_MTSPR         0x30          // 110_000
+#define OPCOD_L_SD            0x32          // 110_010
+#define OPCOD_L_SW            0x35          // 110_101
+#define OPCOD_L_SB            0x36          // 110_110
+#define OPCOD_L_SH            0x37          // 110_111
+
+#define OPCOD_INST_LV         0x0a          // 001_010         // Instruction ORVDX64
+#define OPCOD_INST_LF         0x33          // 110_011         // Instruction ORFPX32/64
+
+#define OPCOD_SPECIAL         0x38          // 111_000         // Instructions Register-Register
+#define OPCOD_SPECIAL_1       0x39          // 111_001         // Instructions "set flag" with register
+#define OPCOD_SPECIAL_2       0x2f          // 101_111         // Instructions "set flag" with immediat
+#define OPCOD_SPECIAL_6       0x2e          // 101_110         // Instruction Shift/Rotate with immediat
+#define OPCOD_SPECIAL_7       0x31          // 110_001         // Instructions multiply with HI-LO
+#define OPCOD_SPECIAL_8       0x06          // 000_110         // Instructions acces at HI-LO 
+
+// OPCOD_SPECIAL   instructions - [9:8] [3:0]  Instructions Register-Register
+#define OPCOD_L_ADD           0x00          // 00_0000
+#define OPCOD_L_ADDC          0x01          // 00_0001
+#define OPCOD_L_SUB           0x02          // 00_0010
+#define OPCOD_L_AND           0x03          // 00_0011
+#define OPCOD_L_OR            0x04          // 00_0100
+#define OPCOD_L_XOR           0x05          // 00_0101
+#define OPCOD_L_CMOV          0x0e          // 00_1110
+#define OPCOD_L_FF1           0x0f          // 00_1111
+#define OPCOD_L_FL1           0x1f          // 01_1111
+#define OPCOD_L_MUL           0x36          // 11_0110
+#define OPCOD_L_DIV           0x39          // 11_1001
+#define OPCOD_L_DIVU          0x3a          // 11_1010
+#define OPCOD_L_MULU          0x3b          // 11_1011
+
+#define OPCOD_SPECIAL_3       0xc           // 1100          // Instructions extend
+#define OPCOD_SPECIAL_4       0xd           // 1101          // Instructions extend (64b)
+#define OPCOD_SPECIAL_5       0x8           // 1000          // Instruction Shift/Rotate with register
+
+// OPCOD_SPECIAL_1 instructions - [25:21]      Instructions "set flag" with register
+#define OPCOD_L_SFEQ          0x00          // 00000
+#define OPCOD_L_SFNE          0x01          // 00001
+#define OPCOD_L_SFGTU         0x02          // 00010
+#define OPCOD_L_SFGEU         0x03          // 00011
+#define OPCOD_L_SFLTU         0x04          // 00100
+#define OPCOD_L_SFLEU         0x05          // 00101
+#define OPCOD_L_SFGTS         0x0a          // 01010
+#define OPCOD_L_SFGES         0x0b          // 01011
+#define OPCOD_L_SFLTS         0x0c          // 01100
+#define OPCOD_L_SFLES         0x0d          // 01101
+
+// OPCOD_SPECIAL_2 instructions - [25:21]      Instructions "set flag" with immediat
+#define OPCOD_L_SFEQI         0x00          // 00000
+#define OPCOD_L_SFNEI         0x01          // 00001
+#define OPCOD_L_SFGTUI        0x02          // 00010
+#define OPCOD_L_SFGEUI        0x03          // 00011
+#define OPCOD_L_SFLTUI        0x04          // 00100
+#define OPCOD_L_SFLEUI        0x05          // 00101
+#define OPCOD_L_SFGTSI        0x0a          // 01010
+#define OPCOD_L_SFGESI        0x0b          // 01011
+#define OPCOD_L_SFLTSI        0x0c          // 01100
+#define OPCOD_L_SFLESI        0x0d          // 01101
+
+// OPCOD_SPECIAL_3 instructions - [9:6]          Instructions extend
+#define OPCOD_L_EXTHS         0x0           // 0000
+#define OPCOD_L_EXTHZ         0x2           // 0010
+#define OPCOD_L_EXTBS         0x1           // 0001
+#define OPCOD_L_EXTBZ         0x3           // 0011
+
+// OPCOD_SPECIAL_4 instructions - [9:6]        Instructions extend (64b)
+#define OPCOD_L_EXTWS         0x0           // 0000
+#define OPCOD_L_EXTWZ         0x1           // 0001
+
+// OPCOD_SPECIAL_5 instructions - [7:6]        Instruction Shift/Rotate with register
+#define OPCOD_L_SLL           0x0           // 00
+#define OPCOD_L_SRL           0x1           // 01
+#define OPCOD_L_SRA           0x2           // 10
+#define OPCOD_L_ROR           0x3           // 11
+
+// OPCOD_SPECIAL_6 instructions - [7:6]        Instruction Shift/Rotate with immediat
+#define OPCOD_L_SLLI          0x0           // 00
+#define OPCOD_L_SRLI          0x1           // 01
+#define OPCOD_L_SRAI          0x2           // 10
+#define OPCOD_L_RORI          0x3           // 11
+
+// OPCOD_SPECIAL_7 instructions - [3:0]        Instructions multiply with HI-LO
+#define OPCOD_L_MAC           0x1           // 0001
+#define OPCOD_L_MSB           0x2           // 0010
+
+// OPCOD_SPECIAL_8 instructions - [17]         Instructions acces at HI-LO 
+#define OPCOD_L_MOVHI         0x0           // 0
+#define OPCOD_L_MACRC         0x1           // 1
+
+// Particular case                             Instructions systems
+#define OPCOD_L_MSYNC         0x22000000
+#define OPCOD_L_CSYNC         0x23000000
+#define OPCOD_L_PSYNC         0x22800000
+#define OPCOD_L_NOP           0x1500
+#define OPCOD_L_SYS           0x2000
+#define OPCOD_L_TRAP          0x2100
+
+//----------------------------------------------------
+// Code Operation (after decode)
+//----------------------------------------------------
+
+typedef enum
+  {
+    // ##### WARNING : This opcode must be the first#####
+    INST_L_NO_IMPLEMENTED ,         // Operation is not implemented
+
+    INST_L_ADD            ,         // L.ADD    , L.ADDI   , L.ADDC   , L.ADDIC
+    INST_L_AND            ,         // L.AND    , L.ANDI
+    INST_L_OR             ,         // L.OR     , L.ORI
+    INST_L_XOR            ,         // L.XOR    , L.XORI
+    INST_L_CMOV           ,         // L.CMOV
+    INST_L_SUB            ,         // L.SUB
+    INST_L_FF1            ,         // L.FF1
+    INST_L_EXTBS          ,         // L.EXTBS
+    INST_L_EXTBZ          ,         // L.EXTBZ
+    INST_L_EXTHS          ,         // L.EXTHS
+    INST_L_EXTHZ          ,         // L.EXTHZ
+    INST_L_EXTWS          ,         // L.EXTWS
+    INST_L_EXTWZ          ,         // L.EXTWZ
+    INST_L_e              ,         // 
+    INST_L_f              ,         // 
+    INST_L_MUL            ,         // L.MUL    , L.MULI
+    INST_L_MULU           ,         // L.MULU
+    INST_L_DIV            ,         // L.DIV
+    INST_L_DIVU           ,         // L.DIVU
+    INST_L_SLL            ,         // L.SLL    , L.SLLI
+    INST_L_SRL            ,         // L.SRL    , L.SRLI 
+    INST_L_SRA            ,         // L.SRA    , L.SRAI
+    INST_L_ROR            ,         // L.ROR    , L.RORI
+    INST_L_SFGES          ,         // L.SFGES  , L.SFGESI
+    INST_L_SFGEU          ,         // L.SFGEU  , L.SFGEUI
+    INST_L_SFGTS          ,         // L.SFGTS  , L.SFGTSI
+    INST_L_SFGTU          ,         // L.SFGTU  , L.SFGTUI
+    INST_L_SFLES          ,         // L.SFLES  , L.SFLESI
+    INST_L_SFLEU          ,         // L.SFLEU  , L.SFLEUI
+    INST_L_SFLTS          ,         // L.SFLTS  , L.SFLTSI
+    INST_L_SFLTU          ,         // L.SFLTU  , L.SFLTUI
+    INST_L_SFEQ           ,         // L.SFEQ   , L.SFEQI
+    INST_L_SFNE           ,         // L.SFNE   , L.SFNEI
+    INST_L_READ           ,         // L.BNF    , L.BF     , L.JR
+    INST_L_MOVHI          ,         // L.MOVI
+    INST_L_CSYNC          ,         // L.CSYNC
+    INST_L_MSYNC          ,         // L.MSYNC
+    INST_L_PSYNC          ,         // L.PSYNC
+    INST_L_RFE            ,         // L.RFE
+    INST_L_MAC            ,         // L.MAC    , L.MACI
+    INST_L_MSB            ,         // L.MSB
+    INST_L_MACRC          ,         // L.MACRC
+    INST_L_2b             ,         //
+    INST_L_MEMB           ,         // L.LBS    , L.LBZ    , L.SB  
+    INST_L_MEMH           ,         // L.LHS    , L.LHZ    , L.SH 
+    INST_L_MEMW           ,         // L.LWS    , L.LWZ    , L.SW  
+    INST_L_MEMD           ,         // L.LD                , L.SD  
+    INST_L_CUST1          ,         // L.CUST1
+    INST_L_CUST2          ,         // L.CUST2
+    INST_L_CUST3          ,         // L.CUST3
+    INST_L_CUST4          ,         // L.CUST4
+    INST_L_CUST5          ,         // L.CUST5
+    INST_L_CUST6          ,         // L.CUST6 
+    INST_L_CUST7          ,         // L.CUST7
+    INST_L_CUST8          ,         // L.CUST8
+    INST_L_38             ,         //
+    INST_L_39             ,         //
+    INST_L_3a             ,         //
+    INST_L_3b             ,         //
+    INST_L_3c             ,         //  
+    INST_L_3d             ,         //  
+    INST_L_3e             ,         //  
+    INST_NOP                        // L.NOP
+  } opcod_t;
+
+#define LOG2_NB_INST_L        6
+#define      NB_INST_L        64 // +1 -> INST_L_NO_IMPLEMENTED
+//#define      NB_INST_L        (INST_L_NO_IMPLEMENTED+1)
+  */
+
+}; // end namespace behavioural
+}; // end namespace morpheo              
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h	(revision 59)
@@ -12,5 +12,4 @@
 #include <iostream>
 #include <math.h>
-#include "Behavioural/Constant/Constant_OpenRISC.h"
 #include "Behavioural/include/Environnement.h"
 #include "Common/include/ErrorMorpheo.h"
@@ -18,5 +17,4 @@
 #include "Common/include/Debug.h"
 
-using namespace morpheo::behavioural::constant;
 using namespace std;
 
@@ -28,4 +26,8 @@
   {
     // -----[ fields ]----------------------------------------------------
+  public   : static const uint32_t   _size_exception      = 4 ;
+  public   : static const uint32_t   _size_dcache_address = 32;
+  public   : static const uint32_t   _size_dcache_type    = 4;
+  public   : static const uint32_t   _size_dcache_error   = 1;
 
     // -----[ methods ]---------------------------------------------------
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h	(revision 59)
@@ -135,5 +135,5 @@
 #define FUNCTION "Signal::alloc"
   public    : template <typename T>
-              void              alloc           (void * sc_signal)
+  void              alloc           (void * sc_signal)
     {
       log_printf(FUNC,Behavioural,FUNCTION,"Begin");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h	(revision 59)
@@ -3,8 +3,14 @@
 
 #include "Common/include/Types.h"
+#include "Behavioural/include/Constants.h"
 
 namespace morpheo {
 namespace behavioural {
   
+  //============================================
+  // Type definition
+  //============================================
+
+  // ***** general
   typedef bool          Tcontrol_t;
   typedef uint8_t       Toperation_t;
@@ -16,9 +22,10 @@
 //typedef uint8_t       Tbranch_state_t;
 
+  typedef uint8_t       Texception_t;
   typedef uint8_t       Tcontext_t;
   typedef uint8_t       Tpacket_t;
   typedef uint8_t       Ttype_t;
-  typedef uint8_t       Tlsq_ptr_t;
 
+  // ***** Register
   typedef uint8_t       Tgeneral_address_t;
   typedef uint32_t      Tgeneral_data_t;
@@ -26,4 +33,13 @@
   typedef uint32_t      Tspecial_data_t;
 
+  // ***** component dependant
+  // ~~~~~ load store queue
+  typedef uint8_t       Taccess_t;
+  typedef uint8_t       Tlsq_ptr_t;
+  typedef uint32_t      Tdcache_address_t;
+  typedef uint32_t      Tdcache_data_t;
+  typedef bool          Tdcache_error_t;
+  typedef uint8_t       Tdcache_type_t;
+
 }; // end namespace behavioural
 }; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-07sympa/fr/root.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-07sympa/fr/root.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/article-07sympa/fr/root.tex	(revision 59)
@@ -0,0 +1,13 @@
+TODO : begin reformuler
+L'augmentation de la finesse de gravure des transistors a pour conséquence une augmentation du nombre de transistors par unité de surface. Donc pour une même surface, un composant matériel peut être de plus en plus complexe. 
+TODO : end   reformuler
+
+Concevoir des System On Chip (SOC) devient de plus en plus complexe. Le concepteur doit utiliser des librairies de composants existants et les inter-connectés entre eux. Ces composants sont des boîtes noires et les concepteurs n'ont aucune garantie d'absence de chevaux de troie.
+
+De plus ce sont des composants pour la plupart commerciaux, et il n'y a pas de garantie d'approvisionnement ou de maintient de protocole de communication.
+
+TODO : begin reformuler
+Pour cela utiliser des composants ouverts permet de s'abstraire de ces problèmes.
+TODO : end   reformuler
+
+Le nombre de processeurs ouverts sont assez restreint : l'OpenRISC 1200, le LEON, l'OpenSPARC, \dots. De plus, aucun n'exploite l'Instruction Level Paralellism (ILP). 
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Graph/synthese_FPGA-registerfile.p	(revision 59)
@@ -14,6 +14,7 @@
 set xlabel "Architecture"
 set ylabel "Nombre LUTs"
-set yrange [1:100000]
-unset logscale; set logscale y 
+set yrange [512:100000]
+unset logscale; set logscale y
+   
 set xtics rotate by -25 ('R:1  W:1'    0 , \
 			 'R:2  W:1'   60 , \
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty	(revision 58)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/ppt-style.sty	(revision 59)
@@ -15,5 +15,5 @@
 \addtobeamertemplate{footline}{\insertframenumber/\inserttotalframenumber}
 
-\setbeameroption{show notes on second screen}
+%\setbeameroption{show notes on second screen}
 
 %\useoutertheme{splitbarsbackground}
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.lang
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.lang	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.lang	(revision 59)
@@ -0,0 +1,1 @@
+fr
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.sty
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.sty	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.sty	(revision 59)
@@ -0,0 +1,12 @@
+\def\review{YYYY/MM/DD}
+%\def\review{\number\day/\number\month/\number\year\xspace}
+
+\title{MORPHEO}
+ 
+\author{Mathieu Rosière \and Nathalie Drach-Temam}
+
+\affiliation{Equipe SOC - Laboratoire d'information de Paris VI - France}
+
+\email{\{mathieu.rosiere, nathalie.drach-temam\}@lip6.fr}
+
+\date{\review}
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.tex
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.tex	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.tex	(revision 59)
@@ -0,0 +1,1 @@
+\documentclass[10pt,a4paper,twocolumn]{article}
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.type
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.type	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/article-07sympa.type	(revision 59)
@@ -0,0 +1,1 @@
+doc
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Link/article-07sympa-fr
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Link/article-07sympa-fr	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Link/article-07sympa-fr	(revision 59)
@@ -0,0 +1,1 @@
+link Documents/article-07sympa/fr
Index: trunk/Makefile.tools_path
===================================================================
--- trunk/Makefile.tools_path	(revision 58)
+++ trunk/Makefile.tools_path	(revision 59)
@@ -1,3 +1,2 @@
-#-----[ path ]---------------------------------------------
 SOCLIB					=  /users/outil/soc/soclib
 SYSTEMC_systemc				= /users/outil/systemc/systemc-2.1.v1
Index: trunk/environment.sh
===================================================================
--- trunk/environment.sh	(revision 58)
+++ trunk/environment.sh	(revision 59)
@@ -4,20 +4,20 @@
 
 case ${OS_FOUND} in
-    "SunOS-sun4X")
-	export TARGET_ARCH=gccsparcOS5
-	export EXE_SUFFIX=
-	;;
+#    "SunOS-sun4X")
+#	export TARGET_ARCH=gccsparcOS5
+#	export EXE_SUFFIX=
+#	;;
     "Linux-iX86")
 	export TARGET_ARCH=linux
 	export EXE_SUFFIX=
 	;;
-    "FreeBSD-iX86")
-	export TARGET_ARCH=freebsd
-	export EXE_SUFFIX=
-	;;
-    "CYGWIN_NT-5.1-iX86")
-	export TARGET_ARCH=cygwin
-	export EXE_SUFFIX=.exe
-    	;;	
+#    "FreeBSD-iX86")
+#	export TARGET_ARCH=freebsd
+#	export EXE_SUFFIX=
+#	;;
+#    "CYGWIN_NT-5.1-iX86")
+#	export TARGET_ARCH=cygwin
+#	export EXE_SUFFIX=.exe
+#    	;;	
     *) 
      echo "Unknown OS found"
@@ -32,12 +32,12 @@
 
 echo ""
-echo "OS found : $OS_FOUND"
+echo "OS found : ${OS_FOUND}"
 echo ""
-echo "Modification of environement's variable : "
-echo " - MORPHEO_TOPLEVEL    is set to ${MORPHEO_TOPLEVEL} "
-echo " - MORPHEO_PLATFORMS   is set to ${MORPHEO_PLATFORMS}"
-echo " - MORPHEO_SOFTWARE    is set to ${MORPHEO_SOFTWARE} "
-echo " - MORPHEO_IPS         is set to ${MORPHEO_IPS}      "
-echo " - MORPHEO_SCRIPT      is set to ${MORPHEO_SCRIPT}   "
+echo " * Modification of environement's variable : "
+echo "   - MORPHEO_TOPLEVEL    is set to ${MORPHEO_TOPLEVEL} "
+echo "   - MORPHEO_PLATFORMS   is set to ${MORPHEO_PLATFORMS}"
+echo "   - MORPHEO_SOFTWARE    is set to ${MORPHEO_SOFTWARE} "
+echo "   - MORPHEO_IPS         is set to ${MORPHEO_IPS}      "
+echo "   - MORPHEO_SCRIPT      is set to ${MORPHEO_SCRIPT}   "
 
 # No multiple add
@@ -46,5 +46,5 @@
 if test $? -eq 1; then
 export  PATH=${PATH}:${MORPHEO_SCRIPT}
-echo " - PATH                add       ${MORPHEO_SCRIPT}   "
+echo "   - PATH                add       ${MORPHEO_SCRIPT}   "
 fi;
 
