Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 62)
@@ -10,4 +10,5 @@
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
 #include "Common/include/Test.h"
+#include "Common/include/BitManipulation.h"
 
 #define NB_ITERATION  1
@@ -43,4 +44,5 @@
 
 
+//========================================================={MemoryRequest_t}
 class MemoryRequest_t
 {
@@ -146,11 +148,106 @@
   return os << "<" << toString(x._cycle) << "> : "
 	    << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._context_id)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
+	    << "\t * context_id                        : " << toString(static_cast<uint32_t>(x._context_id)) << endl
+	    << "\t * operation  / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
+	    << "\t * ptr_write store/load              : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
+	    << "\t * immediat / data_ra / data_rb      : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
+	    << "\t * write_rd / num_reg_rd             : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
 }
 
+//================================================================{Memory_t}
+class Memory_t
+{
+private : const uint32_t    _nb_context;
+private : const uint32_t    _nb_word   ;
+private : const uint32_t    _size_data ;
+private : const Tdcache_address_t _mask_addr ;
+private : Tdcache_data_t ** _data;
+  
+public  : Memory_t (uint32_t nb_context, 
+		    uint32_t nb_word, 
+		    uint32_t size_data):
+  _nb_context   (nb_context),
+  _nb_word      (nb_word   ),
+  _size_data    (size_data ),
+  _mask_addr    (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data))))))
+  {
+    _data = new Tdcache_data_t * [nb_context];
+    
+    for (uint32_t i=0; i<nb_context; i++)
+      {
+	_data [i] = new Tdcache_data_t [nb_word];
+	
+	for (uint32_t j=0; j<nb_word; j++)
+	  _data [i][j] = rand()%(size_data);
+      }
+  }
+
+public  : ~Memory_t (void)
+  {
+    delete [] _data;
+  }
+
+public  : Tdcache_data_t access (uint32_t          context, 
+				 Tdcache_address_t address,
+				 Tdcache_type_t    type,
+				 Tdcache_data_t    data)
+  {
+    return 0;
+  }
+
+public  : Tdcache_data_t read (uint32_t          context,
+			       Tdcache_address_t address,
+			       Tdcache_type_t    type)
+  {
+    // Address's Read must be aligned
+
+    if ((address & _mask_addr) != 0)
+      TEST_KO("<Memory_t::read> Address is not aligned");
+
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    if (address>_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+    
+    return _data [context][address];
+  }
+
+public  : void write (uint32_t          context, 
+		      Tdcache_address_t address,
+		      Tdcache_type_t    type,
+		      Tdcache_data_t    data)
+  {
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    if (address>_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+
+    Tdcache_address_t LSB = address &  _mask;
+    Tdcache_address_t MSB = address & ~_mask;
+  
+    Tdcache_data_t write_data = data;
+    Tdcache_data_t read_data  = _data [context][MSB];
+
+    // exemple to size_data = 32b
+    // LSB index_min
+    // 0   0
+    // 1   8
+    // 2   16
+    // 3   24
+    uint32_t index_min = LSB<<3;
+    uint32_t index_max = index_min;
+    // index max, dependant of access's size
+
+    switch (type)
+      {
+
+
+      }
+  }
+};
+
+//===================================================================={test}
 void test (string name,
 	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
@@ -252,5 +349,4 @@
   (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
   (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_TYPE                 ))(*( in_MEMORY_IN_TYPE                 ));
   (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
   (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
@@ -269,6 +365,4 @@
   (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));
   (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID  ))(*(out_MEMORY_OUT_PACKET_ID  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_OPERATION  ))(*(out_MEMORY_OUT_OPERATION  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_TYPE       ))(*(out_MEMORY_OUT_TYPE       ));
   (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD   ))(*(out_MEMORY_OUT_WRITE_RD   ));
   (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));
@@ -322,7 +416,5 @@
   const uint32_t     nb_word      = nb_request;
 
-  const uint32_t     cst_max_cycle                  =   2;
-
-  const int32_t      percent_transaction_memory_in  = 100;
+//const int32_t      percent_transaction_memory_in  = 100;
   const int32_t      percent_transaction_memory_out = 100;
   const int32_t      percent_transaction_dcache     = 100;
@@ -331,5 +423,5 @@
   const int32_t      percent_type_load              =   0;
   const int32_t      percent_type_store             = 100;
-  const int32_t      percent_miss_spec              = 100;
+  const int32_t      percent_miss_spec              =   0;
 
   if ((percent_type_load  +
@@ -337,6 +429,6 @@
     TEST_KO("sum of percent_type > 100");
 
-  const int32_t      seuil_type_load    = seuil_type_load;
-  const int32_t      seuil_type_store   = seuil_type_store+percent_type_load;
+  const int32_t      seuil_type_load    = percent_type_load;
+  const int32_t      seuil_type_store   = percent_type_store+percent_type_load;
 
   uint32_t           nb_request_memory_in ;
@@ -347,4 +439,5 @@
   priority_queue<MemoryRequest_t> fifo_request;
 
+  // emulation of cache
   Tdcache_data_t     cache_data                [_param->_nb_context][nb_word];
 
@@ -371,10 +464,12 @@
   for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
     {
+      LABEL("Iteration "+toString(iteration));
+
+      LABEL("Structure's initialisation");
+
       nb_request_memory_in  = 0;
       nb_request_memory_out = 0;
       nb_request_dcache     = 0;
       
-      LABEL("Iteration "+toString(iteration));
-
       // Fill the request_queue
       
@@ -390,17 +485,12 @@
 	load_queue_use  [i] = false;
 
-      double             store_queue_cycle [_param->_size_store_queue];
-      double             load_queue_cycle  [_param->_size_load_queue ];
       double             current_cycle = sc_simulation_time();
-
-      for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	store_queue_cycle [i] = current_cycle;
-      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
-	load_queue_cycle  [i] = current_cycle;
-
+      double             cycle_min     = current_cycle;
+
+      LABEL("Fifo request initialisation");
       // Init fifo_request
       for (uint32_t i=0; i<nb_request; i++)
 	{
-	  double             cycle                     = current_cycle+(rand()%(cst_max_cycle*nb_request));
+	  double             cycle;
 	  Tcontext_t         context_id                = rand () % _param->_nb_context;
 	  Tpacket_t          packet_id                 = i;
@@ -411,37 +501,37 @@
 	  int32_t            percent = rand()%100;
 
-	  if (percent < seuil_type_load)
+	  uint32_t           size_queue;
+	 
+	  if (percent <= seuil_type_load)
 	    {
-	      operation = OPERATION_MEMORY_LOAD_16_S;
-	      load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
-	    }
-	  else
-	    if (percent < seuil_type_store)
-	      {
-		operation = OPERATION_MEMORY_STORE_16;
-		store_queue_ptr_write = (store_queue_ptr_write+1) % (_param->_size_store_queue);
-	      }
-	    else
-	      {
-		operation = OPERATION_MEMORY_PREFETCH;
-		load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
-	      }
-
-	  // Valid nb cycle ?
-	  if (is_operation_memory_store(operation))
-	    {
-	      if (cycle <= store_queue_cycle[packet_id])
-		cycle = store_queue_cycle[packet_id]+1;
+// 	      LABEL(" * LOAD");
+	      operation            = OPERATION_MEMORY_LOAD_16_S;
+	      size_queue           = _param->_size_load_queue;
+	      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
 	    }
 	  else
 	    {
-	      if (cycle <= load_queue_cycle[packet_id])
-		cycle = load_queue_cycle[packet_id]+1;
+	      if (percent <= seuil_type_store)
+		{
+// 		  LABEL(" * STORE");
+		  operation             = OPERATION_MEMORY_STORE_16;
+		  size_queue            = _param->_size_store_queue;
+		  store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
+		}
+	      else
+		{
+// 		  LABEL(" * OTHERS");
+		  operation            = OPERATION_MEMORY_PREFETCH;
+		  size_queue           = _param->_size_load_queue;
+		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		}
 	    }
 
+	  cycle      = cycle_min;
+	  cycle_min ++;
+
 	  Ttype_t            type                  = TYPE_MEMORY;
-
-	  Tgeneral_data_t    address               = rand()%(1<<_param->_size_general_data);
-	  Tgeneral_data_t    offset                = rand()%(1<<_param->_size_general_data);
+	  Tgeneral_data_t    address               = rand()%(nb_word);
+	  Tgeneral_data_t    offset                = rand()%(nb_word);
 
 	  percent = rand()%100;
@@ -474,14 +564,20 @@
 				);
 
+	  cout << tab_request [i] << endl;
+	
 	  fifo_request.push(tab_request [i]);
-	  
+
+	  double cycle_head = 0;
+
 	  if (is_operation_memory_store(operation))
 	    {
-	      cycle = cycle+((rand()%(10))-4);
-
-	      if (cycle <= store_queue_cycle[packet_id])
-		cycle = store_queue_cycle[packet_id]+1;
-			
-	      fifo_request.push(MemoryRequest_t(cycle,
+	      cycle_head = cycle_min;
+	      cycle_min ++;
+
+	      cout << "         * Write head : " << toString(cycle_head) 
+		   << endl
+		   << endl;
+	      
+	      fifo_request.push(MemoryRequest_t(cycle_head,
 						context_id,
 						packet_id,
@@ -497,18 +593,17 @@
 						write_spec_ko));
 	    }
-
-	  // update nb cycle ?
-	  if (is_operation_memory_store(operation))
-	    {
-	      store_queue_cycle[packet_id] = cycle;
-	    }
-	  else
-	    {
-	      load_queue_cycle [packet_id] = cycle;
-	    }
-	}
-            
+  	}
+        
+      LABEL("Simulation of this iteration ...");
+    
       while (nb_request_memory_out < nb_request)
 	{
+	  // ***** MEMORY_IN *****
+
+	  // memory_in_val depends of three factors :
+	  //  1) request's fifo is not empty ?
+	  //  2) the slot destination is free ?
+	  //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
+
 	  bool can_execute = false;
 
@@ -535,5 +630,8 @@
 
 	  in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
-	  
+
+	  // ***** DCACHE_REQ *****
+	  in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+
 	  SC_START(0);
   
@@ -541,4 +639,11 @@
 
 	  LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	  LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
+	  LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
+	  LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
+	  LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
+	  LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
+	  LABEL("  * can_execute                            : "+toString(can_execute));
+
 	  if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
 	    {
@@ -562,5 +667,5 @@
 	  if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
 	    {
-	      LABEL(" * Accepted MEMORY_OUT : " + toString(out_MEMORY_OUT_PACKET_ID->read()));
+	      LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));
 
 	      if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
@@ -571,4 +676,13 @@
 	      nb_request_memory_out ++;
 	    }
+
+	  LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
+	  if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+	    {
+	      LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));
+
+	      // test type : send or not a respons !
+	    }
+
 	}
     }
