Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 62)
@@ -67,7 +67,4 @@
    in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id       );
    in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
-#ifdef HAVE_MEMORY_OUT_TYPE
-   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
-#endif
    in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue);
    in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
@@ -97,10 +94,4 @@
       out_MEMORY_OUT_CONTEXT_ID  = interface->set_signal_out <Tcontext_t        > ("context_id"  ,_param->_size_context_id       );
       out_MEMORY_OUT_PACKET_ID   = interface->set_signal_out <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id        );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-      out_MEMORY_OUT_OPERATION   = interface->set_signal_out <Toperation_t      > ("operation"   ,_param->_size_operation        );
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-      out_MEMORY_OUT_TYPE        = interface->set_signal_out <Ttype_t           > ("type"        ,_param->_size_type             );
-#endif
       out_MEMORY_OUT_WRITE_RD    = interface->set_signal_out <Tcontrol_t        > ("write_rd"    ,1                              );
       out_MEMORY_OUT_NUM_REG_RD  = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"  ,_param->_size_general_register );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 62)
@@ -38,7 +38,4 @@
     delete     in_MEMORY_IN_PACKET_ID   ;
     delete     in_MEMORY_IN_OPERATION   ;
-#ifdef HAVE_MEMORY_OUT_TYPE
-    delete     in_MEMORY_IN_TYPE        ;
-#endif
     delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
     delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
@@ -57,10 +54,4 @@
     delete    out_MEMORY_OUT_CONTEXT_ID;
     delete    out_MEMORY_OUT_PACKET_ID ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    delete    out_MEMORY_OUT_OPERATION ;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    delete    out_MEMORY_OUT_TYPE      ;
-#endif
     delete    out_MEMORY_OUT_WRITE_RD  ;
     delete    out_MEMORY_OUT_NUM_REG_RD;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 62)
@@ -28,13 +28,6 @@
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-    // Test store and load queue
     Tcontext_t         memory_out_context_id = 0;
     Tpacket_t          memory_out_packet_id  = 0;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    Toperation_t       memory_out_operation  = 0;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    Ttype_t            memory_out_type       = 0;
-#endif
     Tcontrol_t         memory_out_write_rd   = 0;
     Tgeneral_address_t memory_out_num_reg_rd = 0;
@@ -47,9 +40,8 @@
     internal_MEMORY_OUT_VAL          = 0;
 
-    // TODO : now only store queue
+    // Test store and load queue
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
 
     // Test an store must be commited.
-
-    
     if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
       {
@@ -59,10 +51,4 @@
 	memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
 	memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-	memory_out_operation = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._operation;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-  	memory_out_type      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._type;
-#endif
 //	memory_out_write_rd  
 //	memory_out_num_reg_rd
@@ -71,14 +57,9 @@
       }
 
+    // write output
     PORT_WRITE(out_MEMORY_OUT_VAL       , internal_MEMORY_OUT_VAL);
 
     PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id);
     PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation );
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    PORT_WRITE(out_MEMORY_OUT_TYPE      , memory_out_type      );
-#endif
     PORT_WRITE(out_MEMORY_OUT_WRITE_RD  , memory_out_write_rd  );
     PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd);
@@ -89,5 +70,41 @@
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception );
 
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+    Tcontext_t        dcache_req_context_id;
+    Tpacket_t         dcache_req_packet_id ;
+    Tdcache_address_t dcache_req_address   ;
+    Tdcache_type_t    dcache_req_type      ;
+    Tcontrol_t        dcache_req_uncached  ;
+    Tdcache_data_t    dcache_req_wdata     ;
+
+    internal_DCACHE_REQ_VAL          = 0;
+
+    // Test store and load queue
+
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
+
+    // Test an store must be commited.
+    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
+      {
+	internal_DCACHE_REQ_VAL          = 1;
+	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
+
+	dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
+	dcache_req_packet_id  = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
+	dcache_req_address    = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address   ;
+	dcache_req_type       = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type;
+	dcache_req_uncached   = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached  ;
+	dcache_req_wdata      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata     ;
+      }
+
+    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_UNCACHED  , dcache_req_uncached  );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
+    
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 59)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 62)
@@ -57,9 +57,8 @@
 	    //  others in speculation_access_queue
 
-	    Toperation_t    operation           = PORT_READ(in_MEMORY_IN_OPERATION);
-	    Tgeneral_data_t address             = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
-						   PORT_READ(in_MEMORY_IN_DATA_RA ));
-	    
-	    bool            exception_alignement= (mask_memory_access(operation) & address) != 0;
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA ));
+	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
 						    
 	    if (is_operation_memory_store(operation) == true)
@@ -159,10 +158,6 @@
 		    _store_queue [index]._context_id           = PORT_READ(in_MEMORY_IN_CONTEXT_ID  );
 		    _store_queue [index]._packet_id            = PORT_READ(in_MEMORY_IN_PACKET_ID   );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-		    _store_queue [index]._operation            = operation;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-		    _store_queue [index]._type                 = PORT_READ(in_MEMORY_IN_TYPE        );
-#endif
+		    _store_queue [index]._dcache_type          = operation_to_dcache_type(operation);
+		    _store_queue [index]._uncached             = 0; // is the MMU that have this info
 		    _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
 		    _store_queue [index]._address              = address;
@@ -217,4 +212,43 @@
 	      }
 	  }
+
+	//================================================================
+	// Interface "DCACHE_REQ"
+	//================================================================
+        if ((    internal_DCACHE_REQ_VAL  == 1) and
+            (PORT_READ(in_DCACHE_REQ_ACK) == 1))
+          {
+	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		break;
+	      }
+	  }
+
+#if DEBUG>=DEBUG_TRACE
+	// ***** dump store queue
+	cout << "Dump store queue" << endl
+	     << "ptr_read : " << toString(static_cast<uint32_t>(internal_MEMORY_STORE_QUEUE_PTR_READ)) << endl;
+	
+	for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	  {
+	    uint32_t j = (internal_MEMORY_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+	    cout << "{" << j << "}" << endl
+		 << _store_queue[j] << endl;
+	  }
+#endif
       }
 
