Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 62)
@@ -10,4 +10,5 @@
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
 #include "Common/include/Test.h"
+#include "Common/include/BitManipulation.h"
 
 #define NB_ITERATION  1
@@ -43,4 +44,5 @@
 
 
+//========================================================={MemoryRequest_t}
 class MemoryRequest_t
 {
@@ -146,11 +148,106 @@
   return os << "<" << toString(x._cycle) << "> : "
 	    << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._context_id)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
-	    << "\t * " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
+	    << "\t * context_id                        : " << toString(static_cast<uint32_t>(x._context_id)) << endl
+	    << "\t * operation  / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
+	    << "\t * ptr_write store/load              : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
+	    << "\t * immediat / data_ra / data_rb      : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
+	    << "\t * write_rd / num_reg_rd             : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
 }
 
+//================================================================{Memory_t}
+class Memory_t
+{
+private : const uint32_t    _nb_context;
+private : const uint32_t    _nb_word   ;
+private : const uint32_t    _size_data ;
+private : const Tdcache_address_t _mask_addr ;
+private : Tdcache_data_t ** _data;
+  
+public  : Memory_t (uint32_t nb_context, 
+		    uint32_t nb_word, 
+		    uint32_t size_data):
+  _nb_context   (nb_context),
+  _nb_word      (nb_word   ),
+  _size_data    (size_data ),
+  _mask_addr    (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data))))))
+  {
+    _data = new Tdcache_data_t * [nb_context];
+    
+    for (uint32_t i=0; i<nb_context; i++)
+      {
+	_data [i] = new Tdcache_data_t [nb_word];
+	
+	for (uint32_t j=0; j<nb_word; j++)
+	  _data [i][j] = rand()%(size_data);
+      }
+  }
+
+public  : ~Memory_t (void)
+  {
+    delete [] _data;
+  }
+
+public  : Tdcache_data_t access (uint32_t          context, 
+				 Tdcache_address_t address,
+				 Tdcache_type_t    type,
+				 Tdcache_data_t    data)
+  {
+    return 0;
+  }
+
+public  : Tdcache_data_t read (uint32_t          context,
+			       Tdcache_address_t address,
+			       Tdcache_type_t    type)
+  {
+    // Address's Read must be aligned
+
+    if ((address & _mask_addr) != 0)
+      TEST_KO("<Memory_t::read> Address is not aligned");
+
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    if (address>_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+    
+    return _data [context][address];
+  }
+
+public  : void write (uint32_t          context, 
+		      Tdcache_address_t address,
+		      Tdcache_type_t    type,
+		      Tdcache_data_t    data)
+  {
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    if (address>_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+
+    Tdcache_address_t LSB = address &  _mask;
+    Tdcache_address_t MSB = address & ~_mask;
+  
+    Tdcache_data_t write_data = data;
+    Tdcache_data_t read_data  = _data [context][MSB];
+
+    // exemple to size_data = 32b
+    // LSB index_min
+    // 0   0
+    // 1   8
+    // 2   16
+    // 3   24
+    uint32_t index_min = LSB<<3;
+    uint32_t index_max = index_min;
+    // index max, dependant of access's size
+
+    switch (type)
+      {
+
+
+      }
+  }
+};
+
+//===================================================================={test}
 void test (string name,
 	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
@@ -252,5 +349,4 @@
   (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
   (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_TYPE                 ))(*( in_MEMORY_IN_TYPE                 ));
   (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
   (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
@@ -269,6 +365,4 @@
   (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));
   (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID  ))(*(out_MEMORY_OUT_PACKET_ID  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_OPERATION  ))(*(out_MEMORY_OUT_OPERATION  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_TYPE       ))(*(out_MEMORY_OUT_TYPE       ));
   (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD   ))(*(out_MEMORY_OUT_WRITE_RD   ));
   (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));
@@ -322,7 +416,5 @@
   const uint32_t     nb_word      = nb_request;
 
-  const uint32_t     cst_max_cycle                  =   2;
-
-  const int32_t      percent_transaction_memory_in  = 100;
+//const int32_t      percent_transaction_memory_in  = 100;
   const int32_t      percent_transaction_memory_out = 100;
   const int32_t      percent_transaction_dcache     = 100;
@@ -331,5 +423,5 @@
   const int32_t      percent_type_load              =   0;
   const int32_t      percent_type_store             = 100;
-  const int32_t      percent_miss_spec              = 100;
+  const int32_t      percent_miss_spec              =   0;
 
   if ((percent_type_load  +
@@ -337,6 +429,6 @@
     TEST_KO("sum of percent_type > 100");
 
-  const int32_t      seuil_type_load    = seuil_type_load;
-  const int32_t      seuil_type_store   = seuil_type_store+percent_type_load;
+  const int32_t      seuil_type_load    = percent_type_load;
+  const int32_t      seuil_type_store   = percent_type_store+percent_type_load;
 
   uint32_t           nb_request_memory_in ;
@@ -347,4 +439,5 @@
   priority_queue<MemoryRequest_t> fifo_request;
 
+  // emulation of cache
   Tdcache_data_t     cache_data                [_param->_nb_context][nb_word];
 
@@ -371,10 +464,12 @@
   for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
     {
+      LABEL("Iteration "+toString(iteration));
+
+      LABEL("Structure's initialisation");
+
       nb_request_memory_in  = 0;
       nb_request_memory_out = 0;
       nb_request_dcache     = 0;
       
-      LABEL("Iteration "+toString(iteration));
-
       // Fill the request_queue
       
@@ -390,17 +485,12 @@
 	load_queue_use  [i] = false;
 
-      double             store_queue_cycle [_param->_size_store_queue];
-      double             load_queue_cycle  [_param->_size_load_queue ];
       double             current_cycle = sc_simulation_time();
-
-      for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	store_queue_cycle [i] = current_cycle;
-      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
-	load_queue_cycle  [i] = current_cycle;
-
+      double             cycle_min     = current_cycle;
+
+      LABEL("Fifo request initialisation");
       // Init fifo_request
       for (uint32_t i=0; i<nb_request; i++)
 	{
-	  double             cycle                     = current_cycle+(rand()%(cst_max_cycle*nb_request));
+	  double             cycle;
 	  Tcontext_t         context_id                = rand () % _param->_nb_context;
 	  Tpacket_t          packet_id                 = i;
@@ -411,37 +501,37 @@
 	  int32_t            percent = rand()%100;
 
-	  if (percent < seuil_type_load)
+	  uint32_t           size_queue;
+	 
+	  if (percent <= seuil_type_load)
 	    {
-	      operation = OPERATION_MEMORY_LOAD_16_S;
-	      load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
-	    }
-	  else
-	    if (percent < seuil_type_store)
-	      {
-		operation = OPERATION_MEMORY_STORE_16;
-		store_queue_ptr_write = (store_queue_ptr_write+1) % (_param->_size_store_queue);
-	      }
-	    else
-	      {
-		operation = OPERATION_MEMORY_PREFETCH;
-		load_queue_ptr_write = (load_queue_ptr_write+1) % (_param->_size_load_queue);
-	      }
-
-	  // Valid nb cycle ?
-	  if (is_operation_memory_store(operation))
-	    {
-	      if (cycle <= store_queue_cycle[packet_id])
-		cycle = store_queue_cycle[packet_id]+1;
+// 	      LABEL(" * LOAD");
+	      operation            = OPERATION_MEMORY_LOAD_16_S;
+	      size_queue           = _param->_size_load_queue;
+	      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
 	    }
 	  else
 	    {
-	      if (cycle <= load_queue_cycle[packet_id])
-		cycle = load_queue_cycle[packet_id]+1;
+	      if (percent <= seuil_type_store)
+		{
+// 		  LABEL(" * STORE");
+		  operation             = OPERATION_MEMORY_STORE_16;
+		  size_queue            = _param->_size_store_queue;
+		  store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
+		}
+	      else
+		{
+// 		  LABEL(" * OTHERS");
+		  operation            = OPERATION_MEMORY_PREFETCH;
+		  size_queue           = _param->_size_load_queue;
+		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		}
 	    }
 
+	  cycle      = cycle_min;
+	  cycle_min ++;
+
 	  Ttype_t            type                  = TYPE_MEMORY;
-
-	  Tgeneral_data_t    address               = rand()%(1<<_param->_size_general_data);
-	  Tgeneral_data_t    offset                = rand()%(1<<_param->_size_general_data);
+	  Tgeneral_data_t    address               = rand()%(nb_word);
+	  Tgeneral_data_t    offset                = rand()%(nb_word);
 
 	  percent = rand()%100;
@@ -474,14 +564,20 @@
 				);
 
+	  cout << tab_request [i] << endl;
+	
 	  fifo_request.push(tab_request [i]);
-	  
+
+	  double cycle_head = 0;
+
 	  if (is_operation_memory_store(operation))
 	    {
-	      cycle = cycle+((rand()%(10))-4);
-
-	      if (cycle <= store_queue_cycle[packet_id])
-		cycle = store_queue_cycle[packet_id]+1;
-			
-	      fifo_request.push(MemoryRequest_t(cycle,
+	      cycle_head = cycle_min;
+	      cycle_min ++;
+
+	      cout << "         * Write head : " << toString(cycle_head) 
+		   << endl
+		   << endl;
+	      
+	      fifo_request.push(MemoryRequest_t(cycle_head,
 						context_id,
 						packet_id,
@@ -497,18 +593,17 @@
 						write_spec_ko));
 	    }
-
-	  // update nb cycle ?
-	  if (is_operation_memory_store(operation))
-	    {
-	      store_queue_cycle[packet_id] = cycle;
-	    }
-	  else
-	    {
-	      load_queue_cycle [packet_id] = cycle;
-	    }
-	}
-            
+  	}
+        
+      LABEL("Simulation of this iteration ...");
+    
       while (nb_request_memory_out < nb_request)
 	{
+	  // ***** MEMORY_IN *****
+
+	  // memory_in_val depends of three factors :
+	  //  1) request's fifo is not empty ?
+	  //  2) the slot destination is free ?
+	  //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
+
 	  bool can_execute = false;
 
@@ -535,5 +630,8 @@
 
 	  in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
-	  
+
+	  // ***** DCACHE_REQ *****
+	  in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+
 	  SC_START(0);
   
@@ -541,4 +639,11 @@
 
 	  LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	  LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
+	  LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
+	  LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
+	  LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
+	  LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
+	  LABEL("  * can_execute                            : "+toString(can_execute));
+
 	  if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
 	    {
@@ -562,5 +667,5 @@
 	  if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
 	    {
-	      LABEL(" * Accepted MEMORY_OUT : " + toString(out_MEMORY_OUT_PACKET_ID->read()));
+	      LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));
 
 	      if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
@@ -571,4 +676,13 @@
 	      nb_request_memory_out ++;
 	    }
+
+	  LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
+	  if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+	    {
+	      LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));
+
+	      // test type : send or not a respons !
+	    }
+
 	}
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 62)
@@ -7,4 +7,5 @@
  * [ Description ]
  * 
+ * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit
  */
 
@@ -12,7 +13,4 @@
 #include "systemc.h"
 #endif
-
-#define HAVE_MEMORY_OUT_OPERATION
-#define HAVE_MEMORY_OUT_TYPE
 
 #include <iostream>
@@ -79,7 +77,4 @@
   public    : SC_IN (Tpacket_t         )    *  in_MEMORY_IN_PACKET_ID   ;
   public    : SC_IN (Toperation_t      )    *  in_MEMORY_IN_OPERATION   ;
-#ifdef HAVE_MEMORY_OUT_TYPE
-  public    : SC_IN (Ttype_t           )    *  in_MEMORY_IN_TYPE        ;
-#endif
   public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE;
@@ -99,10 +94,4 @@
   public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_CONTEXT_ID;
   public    : SC_OUT(Tpacket_t         )    * out_MEMORY_OUT_PACKET_ID ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-  public    : SC_OUT(Toperation_t      )    * out_MEMORY_OUT_OPERATION ;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-  public    : SC_OUT(Ttype_t           )    * out_MEMORY_OUT_TYPE      ;
-#endif
   public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RD  ; // = (operation==load)
   public    : SC_OUT(Tgeneral_address_t)    * out_MEMORY_OUT_NUM_REG_RD; // destination (load)
@@ -154,10 +143,15 @@
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+    // Registers
   public    : Tlsq_ptr_t                      internal_MEMORY_STORE_QUEUE_PTR_READ;
-  public    : Tlsq_ptr_t                      internal_MEMORY_LOAD_QUEUE_PTR_READ;
-
+  public    : Tlsq_ptr_t                      internal_MEMORY_LOAD_QUEUE_PTR_READ ;
+
+    // signal
   private   : Tcontrol_t                      internal_MEMORY_IN_ACK;
   private   : Tcontrol_t                      internal_MEMORY_OUT_VAL;
   private   : Tselect_queue_t                 internal_MEMORY_OUT_SELECT_QUEUE;
+
+  private   : Tcontrol_t                      internal_DCACHE_REQ_VAL;
+  private   : Tselect_queue_t                 internal_DCACHE_REQ_SELECT_QUEUE;
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 62)
@@ -26,24 +26,25 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : const uint32_t            _size_store_queue       ;
-  public : const uint32_t            _size_load_queue        ;
+  public : const uint32_t            _size_store_queue             ;
+  public : const uint32_t            _size_load_queue              ;
   public : const uint32_t            _size_speculative_access_queue;
-  public : const uint32_t            _nb_port_check          ;
-  public : const Tspeculative_load_t _speculative_load       ;
-  public : const uint32_t            _nb_context             ;
-  public : const uint32_t            _nb_packet              ;
-  public : const uint32_t            _size_general_data      ;
-  public : const uint32_t            _nb_general_register    ;
-  public : const uint32_t            _nb_operation           ;
-  public : const uint32_t            _nb_type                ;
+  public : const uint32_t            _nb_port_check                ;
+  public : const Tspeculative_load_t _speculative_load             ;
+//public : const uint32_t            _nb_cache_port                ;
+  public : const uint32_t            _nb_context                   ;
+  public : const uint32_t            _nb_packet                    ;
+  public : const uint32_t            _size_general_data            ;
+  public : const uint32_t            _nb_general_register          ;
+  public : const uint32_t            _nb_operation                 ;
+  public : const uint32_t            _nb_type                      ;
 
   public : const uint32_t            _size_address_store_queue             ;
   public : const uint32_t            _size_address_load_queue              ;
   public : const uint32_t            _size_address_speculative_access_queue;
-  public : const uint32_t            _size_context_id        ;
-  public : const uint32_t            _size_packet_id         ;
-  public : const uint32_t            _size_general_register  ;
-  public : const uint32_t            _size_operation         ;
-  public : const uint32_t            _size_type              ;
+  public : const uint32_t            _size_context_id                      ;
+  public : const uint32_t            _size_packet_id                       ;
+  public : const uint32_t            _size_general_register                ;
+  public : const uint32_t            _size_operation                       ;
+  public : const uint32_t            _size_type                            ;
 
     //-----[ methods ]-----------------------------------------------------------
@@ -60,4 +61,5 @@
 			uint32_t            nb_type                
 			);
+
   public : Parameters  (Parameters & param) ;
   public : ~Parameters () ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h	(revision 62)
@@ -56,12 +56,6 @@
   public    : Tcontext_t           _context_id          ;
   public    : Tpacket_t            _packet_id           ;
-  public    : Taccess_t            _access              ;
+  public    : Tdcache_type_t       _dcache_type         ;
   public    : Tcontrol_t           _uncached            ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-  public    : Toperation_t         _operation           ;
-#endif				   
-#ifdef HAVE_MEMORY_OUT_TYPE	   	              
-  public    : Ttype_t              _type                ;
-#endif				   
   public    : Tlsq_ptr_t           _load_queue_ptr_write;
   public    : Tdcache_data_t       _address             ;
@@ -70,5 +64,16 @@
 //public    : Tgeneral_address_t   _num_reg_rd          ;
   public    : Texception_t         _exception           ;
+
+    friend ostream & operator << (ostream& os, const Tstore_queue_entry_t & x) 
+    {
+      return os << " * state                   : " << x._state << endl
+		<< "   * packet   - context_id : " << toString(static_cast<uint32_t>(x._packet_id           )) << " - " << toString(static_cast<uint32_t>(x._context_id)) << endl
+		<< "   * type     - uncached   : " << toString(static_cast<uint32_t>(x._dcache_type         )) << " - " << toString(static_cast<uint32_t>(x._uncached  )) << endl
+		<< "   * load_ptr - execption  : " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << " - " << toString(static_cast<uint32_t>(x._exception )) << endl
+		<< "   * address  - wdata      : " << toString(static_cast<uint32_t>(x._address             )) << " - " << toString(static_cast<uint32_t>(x._wdata     )) << endl;
+    }
   };
+  
+  
 
   // ----------------------------------------------------------
@@ -91,10 +96,4 @@
   public    : Tcontrol_t                         _uncached             ;
   public    : Tcontrol_t                         _sign_extension       ;
-#ifdef HAVE_MEMORY_OUT_OPERATION                 		       
-  public    : Toperation_t                       _operation            ;
-#endif				                 		       
-#ifdef HAVE_MEMORY_OUT_TYPE	                 	               
-  public    : Ttype_t                            _type                 ;
-#endif				                 		       
   public    : Tlsq_ptr_t                         _load_queue_ptr_write ;
   public    : Tlsq_ptr_t                         _store_queue_ptr_write;
@@ -128,10 +127,4 @@
   public    : Tcontrol_t           _uncached            ;
   public    : Tcontrol_t           _sign_extension      ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-  public    : Toperation_t         _operation           ;
-#endif				   
-#ifdef HAVE_MEMORY_OUT_TYPE	   	              
-  public    : Ttype_t              _type                ;
-#endif				   
   public    : Tlsq_ptr_t           _store_queue_ptr_write;
   public    : Tdcache_address_t    _address             ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 62)
@@ -67,7 +67,4 @@
    in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id       );
    in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
-#ifdef HAVE_MEMORY_OUT_TYPE
-   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
-#endif
    in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue);
    in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
@@ -97,10 +94,4 @@
       out_MEMORY_OUT_CONTEXT_ID  = interface->set_signal_out <Tcontext_t        > ("context_id"  ,_param->_size_context_id       );
       out_MEMORY_OUT_PACKET_ID   = interface->set_signal_out <Tpacket_t         > ("packet_id"   ,_param->_size_packet_id        );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-      out_MEMORY_OUT_OPERATION   = interface->set_signal_out <Toperation_t      > ("operation"   ,_param->_size_operation        );
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-      out_MEMORY_OUT_TYPE        = interface->set_signal_out <Ttype_t           > ("type"        ,_param->_size_type             );
-#endif
       out_MEMORY_OUT_WRITE_RD    = interface->set_signal_out <Tcontrol_t        > ("write_rd"    ,1                              );
       out_MEMORY_OUT_NUM_REG_RD  = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"  ,_param->_size_general_register );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 62)
@@ -38,7 +38,4 @@
     delete     in_MEMORY_IN_PACKET_ID   ;
     delete     in_MEMORY_IN_OPERATION   ;
-#ifdef HAVE_MEMORY_OUT_TYPE
-    delete     in_MEMORY_IN_TYPE        ;
-#endif
     delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
     delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
@@ -57,10 +54,4 @@
     delete    out_MEMORY_OUT_CONTEXT_ID;
     delete    out_MEMORY_OUT_PACKET_ID ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    delete    out_MEMORY_OUT_OPERATION ;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    delete    out_MEMORY_OUT_TYPE      ;
-#endif
     delete    out_MEMORY_OUT_WRITE_RD  ;
     delete    out_MEMORY_OUT_NUM_REG_RD;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 62)
@@ -28,13 +28,6 @@
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-    // Test store and load queue
     Tcontext_t         memory_out_context_id = 0;
     Tpacket_t          memory_out_packet_id  = 0;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    Toperation_t       memory_out_operation  = 0;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    Ttype_t            memory_out_type       = 0;
-#endif
     Tcontrol_t         memory_out_write_rd   = 0;
     Tgeneral_address_t memory_out_num_reg_rd = 0;
@@ -47,9 +40,8 @@
     internal_MEMORY_OUT_VAL          = 0;
 
-    // TODO : now only store queue
+    // Test store and load queue
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
 
     // Test an store must be commited.
-
-    
     if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
       {
@@ -59,10 +51,4 @@
 	memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
 	memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-	memory_out_operation = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._operation;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-  	memory_out_type      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._type;
-#endif
 //	memory_out_write_rd  
 //	memory_out_num_reg_rd
@@ -71,14 +57,9 @@
       }
 
+    // write output
     PORT_WRITE(out_MEMORY_OUT_VAL       , internal_MEMORY_OUT_VAL);
 
     PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id);
     PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation );
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    PORT_WRITE(out_MEMORY_OUT_TYPE      , memory_out_type      );
-#endif
     PORT_WRITE(out_MEMORY_OUT_WRITE_RD  , memory_out_write_rd  );
     PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd);
@@ -89,5 +70,41 @@
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception );
 
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+    Tcontext_t        dcache_req_context_id;
+    Tpacket_t         dcache_req_packet_id ;
+    Tdcache_address_t dcache_req_address   ;
+    Tdcache_type_t    dcache_req_type      ;
+    Tcontrol_t        dcache_req_uncached  ;
+    Tdcache_data_t    dcache_req_wdata     ;
+
+    internal_DCACHE_REQ_VAL          = 0;
+
+    // Test store and load queue
+
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
+
+    // Test an store must be commited.
+    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
+      {
+	internal_DCACHE_REQ_VAL          = 1;
+	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
+
+	dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
+	dcache_req_packet_id  = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
+	dcache_req_address    = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address   ;
+	dcache_req_type       = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type;
+	dcache_req_uncached   = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached  ;
+	dcache_req_wdata      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata     ;
+      }
+
+    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_UNCACHED  , dcache_req_uncached  );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
+    
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 62)
@@ -57,9 +57,8 @@
 	    //  others in speculation_access_queue
 
-	    Toperation_t    operation           = PORT_READ(in_MEMORY_IN_OPERATION);
-	    Tgeneral_data_t address             = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
-						   PORT_READ(in_MEMORY_IN_DATA_RA ));
-	    
-	    bool            exception_alignement= (mask_memory_access(operation) & address) != 0;
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA ));
+	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
 						    
 	    if (is_operation_memory_store(operation) == true)
@@ -159,10 +158,6 @@
 		    _store_queue [index]._context_id           = PORT_READ(in_MEMORY_IN_CONTEXT_ID  );
 		    _store_queue [index]._packet_id            = PORT_READ(in_MEMORY_IN_PACKET_ID   );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-		    _store_queue [index]._operation            = operation;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-		    _store_queue [index]._type                 = PORT_READ(in_MEMORY_IN_TYPE        );
-#endif
+		    _store_queue [index]._dcache_type          = operation_to_dcache_type(operation);
+		    _store_queue [index]._uncached             = 0; // is the MMU that have this info
 		    _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
 		    _store_queue [index]._address              = address;
@@ -217,4 +212,43 @@
 	      }
 	  }
+
+	//================================================================
+	// Interface "DCACHE_REQ"
+	//================================================================
+        if ((    internal_DCACHE_REQ_VAL  == 1) and
+            (PORT_READ(in_DCACHE_REQ_ACK) == 1))
+          {
+	    switch (internal_DCACHE_REQ_SELECT_QUEUE)
+	      {
+	      case SELECT_STORE_QUEUE :
+		{
+		  // =======================
+		  // ===== STORE_QUEUE =====
+		  // =======================
+		  
+		  // Entry flush and increase the read pointer
+		  
+		  _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT;
+
+		  break;
+		}
+	      case SELECT_LOAD_QUEUE :
+	      case SELECT_LOAD_QUEUE_SPECULATIVE :
+		break;
+	      }
+	  }
+
+#if DEBUG>=DEBUG_TRACE
+	// ***** dump store queue
+	cout << "Dump store queue" << endl
+	     << "ptr_read : " << toString(static_cast<uint32_t>(internal_MEMORY_STORE_QUEUE_PTR_READ)) << endl;
+	
+	for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	  {
+	    uint32_t j = (internal_MEMORY_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
+	    cout << "{" << j << "}" << endl
+		 << _store_queue[j] << endl;
+	  }
+#endif
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 62)
@@ -112,5 +112,5 @@
   sc_signal<Tspecial_address_t>  ***  in_RETIRE_ROB_RE_NEW_NUM_REG    ;
 
-  string rename;
+  string rename = "signal";
 
   in_CLOCK                                = new sc_clock ("clock", 1.0, 0.5);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp	(revision 61)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp	(revision 62)
@@ -370,6 +370,6 @@
 #endif
 	
-	_component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK");
-	_component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
+	_component->port_map(name_component,"in_CLOCK"   , _name, "in_CLOCK");
+	_component->port_map(name_component,"in_NRESET"  , _name, "in_NRESET");
 
 	for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
@@ -733,5 +733,7 @@
       _component->port_map(name_component,"in_CLOCK" , _name, "in_CLOCK" );
       _component->port_map(name_component,"in_NRESET", _name, "in_NRESET");
-    
+      _component->port_map(name_component,"out_CONST_0");
+      _component->port_map(name_component,"out_CONST_1");
+
       for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
 	{
