Changeset 64 for trunk/IPs/systemC/processor/Morpheo
- Timestamp:
- Dec 4, 2007, 8:02:53 PM (17 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration.cfg
r60 r64 1 1 Register_unit 2 1 1 * 2#_nb_ooo_engine3 32 32 * 2#_size_general_data4 32 32 *2#_size_special_data5 1 1 * 2#_nb_gpr_read6 1 1 * 2#_nb_gpr_write7 1 1 * 2#_nb_gpr_bank8 1 1 * 2#_nb_gpr_port_read_by_bank9 1 1 * 2#_nb_gpr_port_write_by_bank10 1 1 * 2#_nb_spr_read11 1 1 * 2#_nb_spr_write12 1 1 * 2#_nb_spr_bank13 1 1 * 2#_nb_spr_port_read_by_bank14 1 1 * 2#_nb_spr_port_write_by_bank15 32 32 *2#_nb_general_register [0]16 32 32 *2#_nb_special_register [0]17 1 1 * 2#_nb_inst_insert_rob [0]18 1 1 * 2#_nb_inst_retire_rob [0]2 1 1 *4 #_nb_ooo_engine 3 32 32 *4 #_size_general_data 4 2 2 *4 #_size_special_data 5 1 1 *4 #_nb_gpr_read 6 1 1 *4 #_nb_gpr_write 7 1 1 *4 #_nb_gpr_bank 8 1 1 *4 #_nb_gpr_port_read_by_bank 9 1 1 *4 #_nb_gpr_port_write_by_bank 10 1 1 *4 #_nb_spr_read 11 1 1 *4 #_nb_spr_write 12 1 1 *4 #_nb_spr_bank 13 1 1 *4 #_nb_spr_port_read_by_bank 14 1 1 *4 #_nb_spr_port_write_by_bank 15 32 32 *4 #_nb_general_register [0] 16 32 32 *4 #_nb_special_register [0] 17 1 1 *4 #_nb_inst_insert_rob [0] 18 1 1 *4 #_nb_inst_retire_rob [0] -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp
r62 r64 11 11 12 12 #define NB_ITERATION 1 13 #define CYCLE_MAX (1 28*NB_ITERATION)13 #define CYCLE_MAX (10240*NB_ITERATION) 14 14 15 15 #define LABEL(str) \ … … 340 340 341 341 // Initialisation 342 uint32_t max_nb_general_register = 0; 343 344 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 345 if (_param->_nb_general_register [i] > max_nb_general_register) 346 max_nb_general_register = _param->_nb_general_register [i]; 347 348 uint32_t max_nb_special_register = 0; 349 350 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 351 if (_param->_nb_special_register [i] > max_nb_special_register) 352 max_nb_special_register = _param->_nb_special_register [i]; 353 354 const int32_t percent_transaction_read = 70; 355 const int32_t percent_transaction_write = 70; 356 const int32_t percent_transaction_insert = 70; 357 const int32_t percent_transaction_insert_use = 70; 358 const int32_t percent_transaction_retire = 70; 359 const int32_t percent_transaction_retire_use = 70; 360 const uint32_t nb_request = max_nb_general_register; 342 361 343 362 const uint32_t seed = 0; … … 346 365 srand(seed); 347 366 367 Tgeneral_data_t gpr [_param->_nb_ooo_engine][max_nb_general_register]; 368 Tcontrol_t gpr_status [_param->_nb_ooo_engine][max_nb_general_register]; 369 Tspecial_data_t spr [_param->_nb_ooo_engine][max_nb_special_register]; 370 Tcontrol_t spr_status [_param->_nb_ooo_engine][max_nb_special_register]; 371 348 372 SC_START(0); 349 373 350 374 LABEL("Initialisation"); 375 376 for (uint32_t i=0; i<_param->_nb_gpr_read ; i++) 377 in_GPR_READ_VAL [i]->write(0); 378 for (uint32_t i=0; i<_param->_nb_gpr_write; i++) 379 in_GPR_WRITE_VAL [i]->write(0); 380 for (uint32_t i=0; i<_param->_nb_spr_read ; i++) 381 in_SPR_READ_VAL [i]->write(0); 382 for (uint32_t i=0; i<_param->_nb_spr_write; i++) 383 in_SPR_WRITE_VAL [i]->write(0); 384 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 385 { 386 for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) 387 in_INSERT_ROB_VAL [i][j]->write(0); 388 for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) 389 in_RETIRE_ROB_VAL [i][j]->write(0); 390 } 391 392 Tgeneral_address_t gpr_address [_param->_nb_gpr_write]; 393 Tgeneral_address_t gpr_address_next; 394 uint32_t nb_port_gpr_active; // number of port active 395 396 Tspecial_address_t spr_address [_param->_nb_spr_write]; 397 Tspecial_address_t spr_address_next; 398 uint32_t nb_port_spr_active; // number of port active 351 399 352 400 LABEL("Loop of Test"); … … 356 404 LABEL("Iteration "+toString(iteration)); 357 405 358 SC_START(1); 406 LABEL("(GPR) Write default value"); 407 408 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 409 for(uint32_t j=0; j<max_nb_general_register; j++) 410 { 411 gpr [i][j] = rand()%_param->_size_general_data; 412 gpr_status [i][j] = 1; 413 } 414 415 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 416 { 417 gpr_address_next = _param->_nb_gpr_write; 418 nb_port_gpr_active = _param->_nb_gpr_write; 419 420 for (uint32_t j=0; j<_param->_nb_gpr_write; j++) 421 { 422 gpr_address[j] = j; 423 if (j >= _param->_nb_general_register [i]) 424 nb_port_gpr_active --; 425 } 426 427 while (nb_port_gpr_active > 0) 428 { 429 for (uint32_t j=0; j<_param->_nb_gpr_write; j++) 430 { 431 in_GPR_WRITE_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and 432 ((rand() % 100) < percent_transaction_write)); 433 in_GPR_WRITE_OOO_ENGINE_ID [j]->write(i); 434 in_GPR_WRITE_NUM_REG [j]->write(gpr_address[j]); 435 in_GPR_WRITE_DATA [j]->write(gpr [i][gpr_address[j]]); 436 } 437 438 SC_START(1); 439 440 // Test if write 441 for (uint32_t j=0; j<_param->_nb_gpr_write; j++) 442 if (in_GPR_WRITE_VAL [j]->read() and out_GPR_WRITE_ACK [j]->read()) 443 { 444 gpr_address[j] = gpr_address_next; 445 446 if (gpr_address_next >= _param->_nb_general_register [i]) 447 nb_port_gpr_active --; 448 449 gpr_address_next ++; 450 } 451 } 452 } 453 454 for (uint32_t i=0; i<_param->_nb_gpr_write; i++) 455 in_GPR_WRITE_VAL [i]->write(0); 456 457 LABEL("(GPR) Read - and test data writted"); 458 459 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 460 { 461 gpr_address_next = _param->_nb_gpr_read; 462 nb_port_gpr_active = _param->_nb_gpr_read; 463 464 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 465 { 466 gpr_address[j] = j; 467 if (j >= _param->_nb_general_register [i]) 468 nb_port_gpr_active --; 469 } 470 471 while (nb_port_gpr_active > 0) 472 { 473 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 474 { 475 in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and 476 ((rand() % 100) < percent_transaction_read)); 477 in_GPR_READ_OOO_ENGINE_ID [j]->write(i); 478 in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); 479 } 480 481 SC_START(1); 482 483 // Test if read 484 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 485 if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) 486 { 487 TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); 488 TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); 489 490 gpr_address[j] = gpr_address_next; 491 492 if (gpr_address_next >= _param->_nb_general_register [i]) 493 nb_port_gpr_active --; 494 495 gpr_address_next ++; 496 } 497 } 498 } 499 500 for (uint32_t i=0; i<_param->_nb_gpr_read; i++) 501 in_GPR_READ_VAL [i]->write(0); 502 503 LABEL("(SPR) Write default value"); 504 505 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 506 for(uint32_t j=0; j<max_nb_special_register; j++) 507 { 508 spr [i][j] = rand()%_param->_size_special_data; 509 spr_status [i][j] = 1; 510 } 511 512 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 513 { 514 spr_address_next = _param->_nb_spr_write; 515 nb_port_spr_active = _param->_nb_spr_write; 516 517 for (uint32_t j=0; j<_param->_nb_spr_write; j++) 518 { 519 spr_address[j] = j; 520 if (j >= _param->_nb_special_register [i]) 521 nb_port_spr_active --; 522 } 523 524 while (nb_port_spr_active > 0) 525 { 526 for (uint32_t j=0; j<_param->_nb_spr_write; j++) 527 { 528 in_SPR_WRITE_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and 529 ((rand() % 100) < percent_transaction_write)); 530 in_SPR_WRITE_OOO_ENGINE_ID [j]->write(i); 531 in_SPR_WRITE_NUM_REG [j]->write(spr_address[j]); 532 in_SPR_WRITE_DATA [j]->write(spr [i][spr_address[j]]); 533 } 534 535 SC_START(1); 536 537 // Test if write 538 for (uint32_t j=0; j<_param->_nb_spr_write; j++) 539 if (in_SPR_WRITE_VAL [j]->read() and out_SPR_WRITE_ACK [j]->read()) 540 { 541 spr_address[j] = spr_address_next; 542 543 if (spr_address_next >= _param->_nb_special_register [i]) 544 nb_port_spr_active --; 545 546 spr_address_next ++; 547 } 548 } 549 } 550 551 for (uint32_t i=0; i<_param->_nb_spr_write; i++) 552 in_SPR_WRITE_VAL [i]->write(0); 553 554 LABEL("(SPR) Read - and test data writted"); 555 556 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 557 { 558 spr_address_next = _param->_nb_spr_read; 559 nb_port_spr_active = _param->_nb_spr_read; 560 561 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 562 { 563 spr_address[j] = j; 564 if (j >= _param->_nb_special_register [i]) 565 nb_port_spr_active --; 566 } 567 568 while (nb_port_spr_active > 0) 569 { 570 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 571 { 572 in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and 573 ((rand() % 100) < percent_transaction_read)); 574 in_SPR_READ_OOO_ENGINE_ID [j]->write(i); 575 in_SPR_READ_NUM_REG [j]->write(spr_address[j]); 576 } 577 578 SC_START(1); 579 580 // Test if read 581 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 582 if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) 583 { 584 TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); 585 TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); 586 587 spr_address[j] = spr_address_next; 588 589 if (spr_address_next >= _param->_nb_special_register [i]) 590 nb_port_spr_active --; 591 592 spr_address_next ++; 593 } 594 } 595 } 596 597 for (uint32_t i=0; i<_param->_nb_spr_read; i++) 598 in_SPR_READ_VAL [i]->write(0); 599 600 LABEL("insert rob"); 601 602 uint32_t cpt = 0; 603 604 while (cpt < nb_request) 605 { 606 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 607 { 608 uint32_t x=_param->_nb_inst_insert_rob [i]; 609 for (uint32_t j=0; j<x; j++) 610 { 611 in_INSERT_ROB_VAL [i][j]->write((rand() % 100) < percent_transaction_insert); 612 in_INSERT_ROB_RD_USE [i][j]->write((rand() % 100) < percent_transaction_insert_use); 613 in_INSERT_ROB_RD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); 614 in_INSERT_ROB_RE_USE [i][j]->write((rand() % 100) < percent_transaction_insert_use); 615 in_INSERT_ROB_RE_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); 616 } 617 } 618 619 SC_START(1); 620 621 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 622 { 623 uint32_t x=_param->_nb_inst_insert_rob [i]; 624 for (uint32_t j=0; j<x; j++) 625 { 626 if (in_INSERT_ROB_VAL [i][j]->read() and out_INSERT_ROB_ACK [i][j]->read()) 627 { 628 cpt ++; 629 630 if (in_INSERT_ROB_RD_USE [i][j]->read()) 631 gpr_status [i][in_INSERT_ROB_RD_NUM_REG [i][j]->read()] = 0; 632 633 if (in_INSERT_ROB_RE_USE [i][j]->read()) 634 spr_status [i][in_INSERT_ROB_RE_NUM_REG [i][j]->read()] = 0; 635 } 636 } 637 } 638 } 639 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 640 for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) 641 in_INSERT_ROB_VAL [i][j]->write(0); 642 643 LABEL("(GPR) Read - and test data writted"); 644 645 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 646 { 647 gpr_address_next = _param->_nb_gpr_read; 648 nb_port_gpr_active = _param->_nb_gpr_read; 649 650 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 651 { 652 gpr_address[j] = j; 653 if (j >= _param->_nb_general_register [i]) 654 nb_port_gpr_active --; 655 } 656 657 while (nb_port_gpr_active > 0) 658 { 659 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 660 { 661 in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and 662 ((rand() % 100) < percent_transaction_read)); 663 in_GPR_READ_OOO_ENGINE_ID [j]->write(i); 664 in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); 665 } 666 667 SC_START(1); 668 669 // Test if read 670 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 671 if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) 672 { 673 TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); 674 TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); 675 676 gpr_address[j] = gpr_address_next; 677 678 if (gpr_address_next >= _param->_nb_general_register [i]) 679 nb_port_gpr_active --; 680 681 gpr_address_next ++; 682 } 683 } 684 } 685 686 for (uint32_t i=0; i<_param->_nb_gpr_read; i++) 687 in_GPR_READ_VAL [i]->write(0); 688 689 LABEL("(SPR) Read - and test data writted"); 690 691 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 692 { 693 spr_address_next = _param->_nb_spr_read; 694 nb_port_spr_active = _param->_nb_spr_read; 695 696 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 697 { 698 spr_address[j] = j; 699 if (j >= _param->_nb_special_register [i]) 700 nb_port_spr_active --; 701 } 702 703 while (nb_port_spr_active > 0) 704 { 705 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 706 { 707 in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and 708 ((rand() % 100) < percent_transaction_read)); 709 in_SPR_READ_OOO_ENGINE_ID [j]->write(i); 710 in_SPR_READ_NUM_REG [j]->write(spr_address[j]); 711 } 712 713 SC_START(1); 714 715 // Test if read 716 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 717 if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) 718 { 719 TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); 720 TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); 721 722 spr_address[j] = spr_address_next; 723 724 if (spr_address_next >= _param->_nb_special_register [i]) 725 nb_port_spr_active --; 726 727 spr_address_next ++; 728 } 729 } 730 } 731 732 LABEL("retire rob"); 733 734 cpt = 0; 735 736 while (cpt < nb_request) 737 { 738 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 739 { 740 uint32_t x=_param->_nb_inst_retire_rob [i]; 741 for (uint32_t j=0; j<x; j++) 742 { 743 in_RETIRE_ROB_VAL [i][j]->write((rand() % 100) < percent_transaction_retire); 744 in_RETIRE_ROB_RD_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); 745 in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); 746 in_RETIRE_ROB_RD_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); 747 in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); 748 in_RETIRE_ROB_RE_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); 749 in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); 750 in_RETIRE_ROB_RE_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); 751 in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); 752 } 753 } 754 755 SC_START(1); 756 757 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 758 { 759 uint32_t x=_param->_nb_inst_retire_rob [i]; 760 for (uint32_t j=0; j<x; j++) 761 { 762 if (in_RETIRE_ROB_VAL [i][j]->read() and out_RETIRE_ROB_ACK [i][j]->read()) 763 { 764 cpt ++; 765 766 if (in_RETIRE_ROB_RD_OLD_USE [i][j]->read()) 767 gpr_status [i][in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->read()] = 0; 768 if (in_RETIRE_ROB_RD_NEW_USE [i][j]->read()) 769 gpr_status [i][in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->read()] = 1; 770 if (in_RETIRE_ROB_RE_OLD_USE [i][j]->read()) 771 spr_status [i][in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->read()] = 0; 772 if (in_RETIRE_ROB_RE_NEW_USE [i][j]->read()) 773 spr_status [i][in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->read()] = 1; 774 } 775 } 776 } 777 } 778 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 779 for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) 780 in_RETIRE_ROB_VAL [i][j]->write(0); 781 782 LABEL("(GPR) Read - and test data writted"); 783 784 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 785 { 786 gpr_address_next = _param->_nb_gpr_read; 787 nb_port_gpr_active = _param->_nb_gpr_read; 788 789 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 790 { 791 gpr_address[j] = j; 792 if (j >= _param->_nb_general_register [i]) 793 nb_port_gpr_active --; 794 } 795 796 while (nb_port_gpr_active > 0) 797 { 798 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 799 { 800 in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and 801 ((rand() % 100) < percent_transaction_read)); 802 in_GPR_READ_OOO_ENGINE_ID [j]->write(i); 803 in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); 804 } 805 806 SC_START(1); 807 808 // Test if read 809 for (uint32_t j=0; j<_param->_nb_gpr_read; j++) 810 if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) 811 { 812 TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); 813 TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); 814 815 gpr_address[j] = gpr_address_next; 816 817 if (gpr_address_next >= _param->_nb_general_register [i]) 818 nb_port_gpr_active --; 819 820 gpr_address_next ++; 821 } 822 } 823 } 824 825 for (uint32_t i=0; i<_param->_nb_gpr_read; i++) 826 in_GPR_READ_VAL [i]->write(0); 827 828 LABEL("(SPR) Read - and test data writted"); 829 830 for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) 831 { 832 spr_address_next = _param->_nb_spr_read; 833 nb_port_spr_active = _param->_nb_spr_read; 834 835 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 836 { 837 spr_address[j] = j; 838 if (j >= _param->_nb_special_register [i]) 839 nb_port_spr_active --; 840 } 841 842 while (nb_port_spr_active > 0) 843 { 844 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 845 { 846 in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and 847 ((rand() % 100) < percent_transaction_read)); 848 in_SPR_READ_OOO_ENGINE_ID [j]->write(i); 849 in_SPR_READ_NUM_REG [j]->write(spr_address[j]); 850 } 851 852 SC_START(1); 853 854 // Test if read 855 for (uint32_t j=0; j<_param->_nb_spr_read; j++) 856 if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) 857 { 858 TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); 859 TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); 860 861 spr_address[j] = spr_address_next; 862 863 if (spr_address_next >= _param->_nb_special_register [i]) 864 nb_port_spr_active --; 865 866 spr_address_next ++; 867 } 868 } 869 } 870 359 871 } 360 872 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags
r62 r64 15 15 #-----[ Flags ]-------------------------------------------- 16 16 MORPHEO_FLAGS = -DSYSTEMC \ 17 -DVHDL \ 18 -DVHDL_TESTBENCH \ 19 -DVHDL_TESTBENCH_ASSERT \ 17 20 -DDEBUG=DEBUG_TRACE 18 21 19 # -DVHDL \20 # -DVHDL_TESTBENCH \21 # -DVHDL_TESTBENCH_ASSERT \22 22 # 23 23 # -DSTATISTICS \
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