Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration.cfg
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration.cfg	(revision 63)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/configuration.cfg	(revision 64)
@@ -1,18 +1,18 @@
 Register_unit
-1	1	*2	#_nb_ooo_engine            
-32	32	*2	#_size_general_data        
-32	32	*2	#_size_special_data        
-1	1	*2	#_nb_gpr_read              
-1	1	*2	#_nb_gpr_write             
-1	1	*2	#_nb_gpr_bank              
-1	1	*2	#_nb_gpr_port_read_by_bank 
-1	1	*2	#_nb_gpr_port_write_by_bank
-1	1	*2	#_nb_spr_read              
-1	1	*2	#_nb_spr_write             
-1	1	*2	#_nb_spr_bank              
-1	1	*2	#_nb_spr_port_read_by_bank 
-1	1	*2	#_nb_spr_port_write_by_bank
-32	32	*2	#_nb_general_register [0]     
-32	32 	*2	#_nb_special_register [0]     
-1	1	*2	#_nb_inst_insert_rob  [0]     
-1	1	*2	#_nb_inst_retire_rob  [0]     
+1	1	*4	#_nb_ooo_engine            
+32	32	*4	#_size_general_data        
+2	2	*4	#_size_special_data        
+1	1	*4	#_nb_gpr_read              
+1	1	*4	#_nb_gpr_write             
+1	1	*4	#_nb_gpr_bank              
+1	1	*4	#_nb_gpr_port_read_by_bank 
+1	1	*4	#_nb_gpr_port_write_by_bank
+1	1	*4	#_nb_spr_read              
+1	1	*4	#_nb_spr_write             
+1	1	*4	#_nb_spr_bank              
+1	1	*4	#_nb_spr_port_read_by_bank 
+1	1	*4	#_nb_spr_port_write_by_bank
+32 	32 	*4	#_nb_general_register [0]     
+32 	32  	*4	#_nb_special_register [0]     
+1	1	*4	#_nb_inst_insert_rob  [0]     
+1	1	*4	#_nb_inst_retire_rob  [0]     
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 63)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp	(revision 64)
@@ -11,5 +11,5 @@
 
 #define NB_ITERATION  1
-#define CYCLE_MAX     (128*NB_ITERATION)
+#define CYCLE_MAX     (10240*NB_ITERATION)
 
 #define LABEL(str)                                                                       \
@@ -340,4 +340,23 @@
 
   // Initialisation
+  uint32_t        max_nb_general_register = 0;
+
+  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+    if (_param->_nb_general_register [i] > max_nb_general_register)
+      max_nb_general_register = _param->_nb_general_register [i];
+
+  uint32_t        max_nb_special_register = 0;
+
+  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+    if (_param->_nb_special_register [i] > max_nb_special_register)
+      max_nb_special_register = _param->_nb_special_register [i];
+
+  const  int32_t percent_transaction_read       = 70;
+  const  int32_t percent_transaction_write      = 70;
+  const  int32_t percent_transaction_insert     = 70;
+  const  int32_t percent_transaction_insert_use = 70;
+  const  int32_t percent_transaction_retire     = 70;
+  const  int32_t percent_transaction_retire_use = 70;
+  const uint32_t nb_request                     = max_nb_general_register;
 
   const uint32_t seed = 0;
@@ -346,7 +365,36 @@
   srand(seed);
 
+  Tgeneral_data_t    gpr        [_param->_nb_ooo_engine][max_nb_general_register];
+  Tcontrol_t         gpr_status [_param->_nb_ooo_engine][max_nb_general_register];
+  Tspecial_data_t    spr        [_param->_nb_ooo_engine][max_nb_special_register];
+  Tcontrol_t         spr_status [_param->_nb_ooo_engine][max_nb_special_register];
+
   SC_START(0);
 
   LABEL("Initialisation");
+
+  for (uint32_t i=0; i<_param->_nb_gpr_read ; i++)
+    in_GPR_READ_VAL  [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
+    in_GPR_WRITE_VAL [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_spr_read ; i++)
+    in_SPR_READ_VAL  [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_spr_write; i++)
+    in_SPR_WRITE_VAL [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+    {
+      for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
+	in_INSERT_ROB_VAL [i][j]->write(0);
+      for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++)
+	in_RETIRE_ROB_VAL [i][j]->write(0);
+    }
+      
+  Tgeneral_address_t gpr_address [_param->_nb_gpr_write];
+  Tgeneral_address_t gpr_address_next;
+  uint32_t           nb_port_gpr_active; // number of port active
+
+  Tspecial_address_t spr_address [_param->_nb_spr_write];
+  Tspecial_address_t spr_address_next;
+  uint32_t           nb_port_spr_active; // number of port active
 
   LABEL("Loop of Test");
@@ -356,5 +404,469 @@
       LABEL("Iteration "+toString(iteration));
 
-      SC_START(1);
+      LABEL("(GPR) Write default value");
+
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	for(uint32_t j=0; j<max_nb_general_register; j++)
+	  {
+	    gpr        [i][j] = rand()%_param->_size_general_data;
+	    gpr_status [i][j] = 1;
+	  }
+
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  gpr_address_next   = _param->_nb_gpr_write;
+	  nb_port_gpr_active = _param->_nb_gpr_write;
+	  
+	  for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+	    {
+	      gpr_address[j] = j;
+	      if (j >= _param->_nb_general_register [i])
+		nb_port_gpr_active --;
+	    }
+	  
+	  while (nb_port_gpr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+		{
+		  in_GPR_WRITE_VAL           [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and
+							((rand() % 100) < percent_transaction_write));
+		  in_GPR_WRITE_OOO_ENGINE_ID [j]->write(i);
+		  in_GPR_WRITE_NUM_REG       [j]->write(gpr_address[j]);
+		  in_GPR_WRITE_DATA          [j]->write(gpr [i][gpr_address[j]]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if write
+	      for (uint32_t j=0; j<_param->_nb_gpr_write; j++)
+		if (in_GPR_WRITE_VAL [j]->read() and out_GPR_WRITE_ACK [j]->read())
+		  {
+		    gpr_address[j] = gpr_address_next;
+
+		    if (gpr_address_next >= _param->_nb_general_register [i])
+		      nb_port_gpr_active --;		    
+		    
+		    gpr_address_next ++;
+		  }
+	    }
+	}
+      
+      for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
+	in_GPR_WRITE_VAL [i]->write(0);
+
+      LABEL("(GPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  gpr_address_next   = _param->_nb_gpr_read;
+	  nb_port_gpr_active = _param->_nb_gpr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+	    {
+	      gpr_address[j] = j;
+	      if (j >= _param->_nb_general_register [i])
+		nb_port_gpr_active --;
+	    }
+	  
+	  while (nb_port_gpr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		{
+		  in_GPR_READ_VAL           [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_GPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_GPR_READ_NUM_REG       [j]->write(gpr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tgeneral_data_t, out_GPR_READ_DATA    [j]->read(), gpr        [i][gpr_address[j]]);
+		    TEST(Tcontrol_t     , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]);
+
+		    gpr_address[j] = gpr_address_next;
+
+		    if (gpr_address_next >= _param->_nb_general_register [i])
+		      nb_port_gpr_active --;		    
+		    
+		    gpr_address_next ++;
+		  }
+	    }
+	}
+
+      for (uint32_t i=0; i<_param->_nb_gpr_read; i++)
+	in_GPR_READ_VAL [i]->write(0);
+
+      LABEL("(SPR) Write default value");
+
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	for(uint32_t j=0; j<max_nb_special_register; j++)
+	  {
+	    spr        [i][j] = rand()%_param->_size_special_data;
+	    spr_status [i][j] = 1;
+	  }
+
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  spr_address_next   = _param->_nb_spr_write;
+	  nb_port_spr_active = _param->_nb_spr_write;
+	  
+	  for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+	    {
+	      spr_address[j] = j;
+	      if (j >= _param->_nb_special_register [i])
+		nb_port_spr_active --;
+	    }
+	  
+	  while (nb_port_spr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+		{
+		  in_SPR_WRITE_VAL           [j]->write((spr_address[j] < _param->_nb_special_register [i]) and
+							((rand() % 100) < percent_transaction_write));
+		  in_SPR_WRITE_OOO_ENGINE_ID [j]->write(i);
+		  in_SPR_WRITE_NUM_REG       [j]->write(spr_address[j]);
+		  in_SPR_WRITE_DATA          [j]->write(spr [i][spr_address[j]]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if write
+	      for (uint32_t j=0; j<_param->_nb_spr_write; j++)
+		if (in_SPR_WRITE_VAL [j]->read() and out_SPR_WRITE_ACK [j]->read())
+		  {
+		    spr_address[j] = spr_address_next;
+
+		    if (spr_address_next >= _param->_nb_special_register [i])
+		      nb_port_spr_active --;		    
+		    
+		    spr_address_next ++;
+		  }
+	    }
+	}
+      
+      for (uint32_t i=0; i<_param->_nb_spr_write; i++)
+	in_SPR_WRITE_VAL [i]->write(0);
+
+      LABEL("(SPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  spr_address_next   = _param->_nb_spr_read;
+	  nb_port_spr_active = _param->_nb_spr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+	    {
+	      spr_address[j] = j;
+	      if (j >= _param->_nb_special_register [i])
+		nb_port_spr_active --;
+	    }
+	  
+	  while (nb_port_spr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		{
+		  in_SPR_READ_VAL           [j]->write((spr_address[j] < _param->_nb_special_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_SPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_SPR_READ_NUM_REG       [j]->write(spr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tspecial_data_t, out_SPR_READ_DATA    [j]->read(), spr        [i][spr_address[j]]);
+		    TEST(Tcontrol_t     , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]);
+
+		    spr_address[j] = spr_address_next;
+
+		    if (spr_address_next >= _param->_nb_special_register [i])
+		      nb_port_spr_active --;		    
+		    
+		    spr_address_next ++;
+		  }
+	    }
+	}
+
+      for (uint32_t i=0; i<_param->_nb_spr_read; i++)
+	in_SPR_READ_VAL [i]->write(0);
+      
+      LABEL("insert rob");
+
+      uint32_t cpt = 0;
+      
+      while (cpt < nb_request)
+	{
+	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	    {
+	      uint32_t x=_param->_nb_inst_insert_rob [i];
+	      for (uint32_t j=0; j<x; j++)
+		{
+		  in_INSERT_ROB_VAL        [i][j]->write((rand() % 100) < percent_transaction_insert);
+		  in_INSERT_ROB_RD_USE     [i][j]->write((rand() % 100) < percent_transaction_insert_use);
+		  in_INSERT_ROB_RD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]);
+		  in_INSERT_ROB_RE_USE     [i][j]->write((rand() % 100) < percent_transaction_insert_use);
+		  in_INSERT_ROB_RE_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]);
+		}
+	    }
+	  
+	  SC_START(1);
+	  
+	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	    {
+	      uint32_t x=_param->_nb_inst_insert_rob [i];
+	      for (uint32_t j=0; j<x; j++)
+		{
+		  if (in_INSERT_ROB_VAL [i][j]->read() and out_INSERT_ROB_ACK [i][j]->read())
+		    {
+		      cpt ++;
+		      
+		      if (in_INSERT_ROB_RD_USE [i][j]->read())
+			gpr_status [i][in_INSERT_ROB_RD_NUM_REG [i][j]->read()] = 0;
+		      
+		      if (in_INSERT_ROB_RE_USE [i][j]->read())
+			spr_status [i][in_INSERT_ROB_RE_NUM_REG [i][j]->read()] = 0;
+		    }
+		}
+	    }
+	}
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++)
+	  in_INSERT_ROB_VAL [i][j]->write(0);
+
+      LABEL("(GPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  gpr_address_next   = _param->_nb_gpr_read;
+	  nb_port_gpr_active = _param->_nb_gpr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+	    {
+	      gpr_address[j] = j;
+	      if (j >= _param->_nb_general_register [i])
+		nb_port_gpr_active --;
+	    }
+	  
+	  while (nb_port_gpr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		{
+		  in_GPR_READ_VAL           [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_GPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_GPR_READ_NUM_REG       [j]->write(gpr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tgeneral_data_t, out_GPR_READ_DATA    [j]->read(), gpr        [i][gpr_address[j]]);
+		    TEST(Tcontrol_t     , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]);
+
+		    gpr_address[j] = gpr_address_next;
+
+		    if (gpr_address_next >= _param->_nb_general_register [i])
+		      nb_port_gpr_active --;		    
+		    
+		    gpr_address_next ++;
+		  }
+	    }
+	}
+
+      for (uint32_t i=0; i<_param->_nb_gpr_read; i++)
+	in_GPR_READ_VAL [i]->write(0);
+
+      LABEL("(SPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  spr_address_next   = _param->_nb_spr_read;
+	  nb_port_spr_active = _param->_nb_spr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+	    {
+	      spr_address[j] = j;
+	      if (j >= _param->_nb_special_register [i])
+		nb_port_spr_active --;
+	    }
+	  
+	  while (nb_port_spr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		{
+		  in_SPR_READ_VAL           [j]->write((spr_address[j] < _param->_nb_special_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_SPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_SPR_READ_NUM_REG       [j]->write(spr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tspecial_data_t, out_SPR_READ_DATA    [j]->read(), spr        [i][spr_address[j]]);
+		    TEST(Tcontrol_t     , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]);
+
+		    spr_address[j] = spr_address_next;
+
+		    if (spr_address_next >= _param->_nb_special_register [i])
+		      nb_port_spr_active --;		    
+		    
+		    spr_address_next ++;
+		  }
+	    }
+	}
+
+      LABEL("retire rob");
+
+      cpt = 0;
+      
+      while (cpt < nb_request)
+	{
+	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	    {
+	      uint32_t x=_param->_nb_inst_retire_rob [i];
+	      for (uint32_t j=0; j<x; j++)
+		{
+		  in_RETIRE_ROB_VAL            [i][j]->write((rand() % 100) < percent_transaction_retire);
+		  in_RETIRE_ROB_RD_OLD_USE     [i][j]->write((rand() % 100) < percent_transaction_retire_use);
+		  in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]);
+		  in_RETIRE_ROB_RD_NEW_USE     [i][j]->write((rand() % 100) < percent_transaction_retire_use);
+		  in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]);	    
+		  in_RETIRE_ROB_RE_OLD_USE     [i][j]->write((rand() % 100) < percent_transaction_retire_use); 
+		  in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]);	    
+		  in_RETIRE_ROB_RE_NEW_USE     [i][j]->write((rand() % 100) < percent_transaction_retire_use);
+		  in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]);	    
+		}
+	    }
+	  
+	  SC_START(1);
+	  
+	  for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	    {
+	      uint32_t x=_param->_nb_inst_retire_rob [i];
+	      for (uint32_t j=0; j<x; j++)
+		{
+		  if (in_RETIRE_ROB_VAL [i][j]->read() and out_RETIRE_ROB_ACK [i][j]->read())
+		    {
+		      cpt ++;
+		      
+		      if (in_RETIRE_ROB_RD_OLD_USE [i][j]->read())
+			gpr_status [i][in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->read()] = 0;
+		      if (in_RETIRE_ROB_RD_NEW_USE [i][j]->read())
+			gpr_status [i][in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->read()] = 1;
+		      if (in_RETIRE_ROB_RE_OLD_USE [i][j]->read())
+			spr_status [i][in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->read()] = 0;
+		      if (in_RETIRE_ROB_RE_NEW_USE [i][j]->read())
+			spr_status [i][in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->read()] = 1;
+		    }
+		}
+	    }
+	}
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++)
+	  in_RETIRE_ROB_VAL [i][j]->write(0);
+
+      LABEL("(GPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  gpr_address_next   = _param->_nb_gpr_read;
+	  nb_port_gpr_active = _param->_nb_gpr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+	    {
+	      gpr_address[j] = j;
+	      if (j >= _param->_nb_general_register [i])
+		nb_port_gpr_active --;
+	    }
+	  
+	  while (nb_port_gpr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		{
+		  in_GPR_READ_VAL           [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_GPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_GPR_READ_NUM_REG       [j]->write(gpr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_gpr_read; j++)
+		if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tgeneral_data_t, out_GPR_READ_DATA    [j]->read(), gpr        [i][gpr_address[j]]);
+		    TEST(Tcontrol_t     , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]);
+
+		    gpr_address[j] = gpr_address_next;
+
+		    if (gpr_address_next >= _param->_nb_general_register [i])
+		      nb_port_gpr_active --;		    
+		    
+		    gpr_address_next ++;
+		  }
+	    }
+	}
+
+      for (uint32_t i=0; i<_param->_nb_gpr_read; i++)
+	in_GPR_READ_VAL [i]->write(0);
+
+      LABEL("(SPR) Read - and test data writted");
+      
+      for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
+	{
+	  spr_address_next   = _param->_nb_spr_read;
+	  nb_port_spr_active = _param->_nb_spr_read;
+	  
+	  for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+	    {
+	      spr_address[j] = j;
+	      if (j >= _param->_nb_special_register [i])
+		nb_port_spr_active --;
+	    }
+	  
+	  while (nb_port_spr_active > 0)
+	    {
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		{
+		  in_SPR_READ_VAL           [j]->write((spr_address[j] < _param->_nb_special_register [i]) and
+						       ((rand() % 100) < percent_transaction_read));
+		  in_SPR_READ_OOO_ENGINE_ID [j]->write(i);
+		  in_SPR_READ_NUM_REG       [j]->write(spr_address[j]);
+		}
+	      
+	      SC_START(1);
+
+	      // Test if read
+	      for (uint32_t j=0; j<_param->_nb_spr_read; j++)
+		if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read())
+		  {
+		    TEST(Tspecial_data_t, out_SPR_READ_DATA    [j]->read(), spr        [i][spr_address[j]]);
+		    TEST(Tcontrol_t     , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]);
+
+		    spr_address[j] = spr_address_next;
+
+		    if (spr_address_next >= _param->_nb_special_register [i])
+		      nb_port_spr_active --;		    
+		    
+		    spr_address_next ++;
+		  }
+	    }
+	}
+
     }
 
Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags
===================================================================
--- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags	(revision 63)
+++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags	(revision 64)
@@ -15,9 +15,9 @@
 #-----[ Flags ]--------------------------------------------
 MORPHEO_FLAGS			=	-DSYSTEMC		\
+					-DVHDL			\
+  					-DVHDL_TESTBENCH	\
+					-DVHDL_TESTBENCH_ASSERT	\
 					-DDEBUG=DEBUG_TRACE	
 
-#					-DVHDL			\
-#  					-DVHDL_TESTBENCH	\
-#					-DVHDL_TESTBENCH_ASSERT	\
 #
 #					-DSTATISTICS 		\