Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 62)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp	(revision 71)
@@ -9,246 +9,35 @@
 #include <queue>
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
-#include "Common/include/Test.h"
-#include "Common/include/BitManipulation.h"
 
 #define NB_ITERATION  1
-#define CYCLE_MAX     (128*NB_ITERATION)
-
-#define LABEL(str)                                                                       \
-{                                                                                        \
-  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
-} while(0)
-
-static uint32_t cycle = 0;
-
-#define SC_START(cycle_offset)                                          \
-do                                                                      \
-{                                                                       \
-/*cout << "SC_START (begin)" << endl;*/                                 \
-                                                                        \
-  uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
-  if (cycle_current != cycle)                                           \
-    {                                                                   \
-      cycle = cycle_current;                                            \
-      cout << "##########[ cycle "<< cycle << " ]" << endl;             \
-    }                                                                   \
-                                                                        \
-  if (cycle_current > CYCLE_MAX)                                        \
-    {                                                                   \
-      TEST_KO("Maximal cycles Reached");                                \
-    }                                                                   \
-  sc_start(cycle_offset);                                               \
-/*cout << "SC_START (end  )" << endl;*/                                 \
-} while(0)
-
-
-
-//========================================================={MemoryRequest_t}
-class MemoryRequest_t
-{
-public : double             _cycle                ;
-public : Tcontext_t         _context_id           ;
-public : Tpacket_t          _packet_id            ;
-public : Toperation_t       _operation            ;
-public : Ttype_t            _type                 ;
-public : Tlsq_ptr_t         _store_queue_ptr_write;
-public : Tlsq_ptr_t         _load_queue_ptr_write ;
-public : Tgeneral_data_t    _immediat             ;
-public : Tgeneral_data_t    _data_ra              ;
-public : Tgeneral_data_t    _data_rb              ;
-public : Tcontrol_t         _write_rd             ;
-public : Tgeneral_address_t _num_reg_rd           ;
-public : bool               _write_spec_ko        ;
-
-  MemoryRequest_t (void) 
-  {
-    _cycle                 = 0;
-    _context_id            = 0;
-    _packet_id             = 0;
-    _operation             = 0;
-    _type                  = 0;
-    _store_queue_ptr_write = 0;
-    _load_queue_ptr_write  = 0;
-    _immediat              = 0;
-    _data_ra               = 0;
-    _data_rb               = 0;
-    _write_rd              = 0;
-    _num_reg_rd            = 0;
-    _write_spec_ko         = 0;
-  };
-
-  MemoryRequest_t (double             cycle                ,
-		   Tcontext_t         context_id           ,
-		   Tpacket_t          packet_id            ,
-		   Toperation_t       operation            ,
-		   Ttype_t            type                 ,
-		   Tlsq_ptr_t         store_queue_ptr_write,
-		   Tlsq_ptr_t         load_queue_ptr_write ,
-		   Tgeneral_data_t    immediat             ,
-		   Tgeneral_data_t    data_ra              ,
-		   Tgeneral_data_t    data_rb              ,
-		   Tcontrol_t         write_rd             ,
-		   Tgeneral_address_t num_reg_rd           ,
-		   bool               write_spec_ko        )
-  {
-    _cycle                 = cycle                ;
-    _context_id            = context_id           ;
-    _packet_id             = packet_id            ;
-    _operation             = operation            ;
-    _type                  = type                 ;
-    _store_queue_ptr_write = store_queue_ptr_write;
-    _load_queue_ptr_write  = load_queue_ptr_write ;
-    _immediat              = immediat             ;
-    _data_ra               = data_ra              ;
-    _data_rb               = data_rb              ;
-    _write_rd              = write_rd             ;
-    _num_reg_rd            = num_reg_rd           ;
-    _write_spec_ko         = write_spec_ko        ;
-  }
-
-  void modif (double             cycle                ,
-	      Tcontext_t         context_id           ,
-	      Tpacket_t          packet_id            ,
-	      Toperation_t       operation            ,
-	      Ttype_t            type                 ,
-	      Tlsq_ptr_t         store_queue_ptr_write,
-	      Tlsq_ptr_t         load_queue_ptr_write ,
-	      Tgeneral_data_t    immediat             ,
-	      Tgeneral_data_t    data_ra              ,
-	      Tgeneral_data_t    data_rb              ,
-	      Tcontrol_t         write_rd             ,
-	      Tgeneral_address_t num_reg_rd           ,
-	      bool               write_spec_ko        )
-  {
-    _cycle                 = cycle                ;
-    _context_id            = context_id           ;
-    _packet_id             = packet_id            ;
-    _operation             = operation            ;
-    _type                  = type                 ;
-    _store_queue_ptr_write = store_queue_ptr_write;
-    _load_queue_ptr_write  = load_queue_ptr_write ;
-    _immediat              = immediat             ;
-    _data_ra               = data_ra              ;
-    _data_rb               = data_rb              ;
-    _write_rd              = write_rd             ;
-    _num_reg_rd            = num_reg_rd           ;
-    _write_spec_ko         = write_spec_ko        ;
-  }
-
-  bool operator< (const MemoryRequest_t & right) const 
-  {
-    return _cycle > right._cycle; 
-  }
-
-  friend ostream& operator<<(ostream &, const MemoryRequest_t &);
-};
-
-ostream & operator << (ostream& os, const MemoryRequest_t & x) 
-{
-  return os << "<" << toString(x._cycle) << "> : "
-	    << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
-	    << "\t * context_id                        : " << toString(static_cast<uint32_t>(x._context_id)) << endl
-	    << "\t * operation  / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
-	    << "\t * ptr_write store/load              : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
-	    << "\t * immediat / data_ra / data_rb      : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
-	    << "\t * write_rd / num_reg_rd             : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
-}
-
-//================================================================{Memory_t}
-class Memory_t
-{
-private : const uint32_t    _nb_context;
-private : const uint32_t    _nb_word   ;
-private : const uint32_t    _size_data ;
-private : const Tdcache_address_t _mask_addr ;
-private : Tdcache_data_t ** _data;
-  
-public  : Memory_t (uint32_t nb_context, 
-		    uint32_t nb_word, 
-		    uint32_t size_data):
-  _nb_context   (nb_context),
-  _nb_word      (nb_word   ),
-  _size_data    (size_data ),
-  _mask_addr    (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data))))))
-  {
-    _data = new Tdcache_data_t * [nb_context];
-    
-    for (uint32_t i=0; i<nb_context; i++)
-      {
-	_data [i] = new Tdcache_data_t [nb_word];
-	
-	for (uint32_t j=0; j<nb_word; j++)
-	  _data [i][j] = rand()%(size_data);
-      }
-  }
-
-public  : ~Memory_t (void)
-  {
-    delete [] _data;
-  }
-
-public  : Tdcache_data_t access (uint32_t          context, 
-				 Tdcache_address_t address,
-				 Tdcache_type_t    type,
-				 Tdcache_data_t    data)
-  {
-    return 0;
-  }
-
-public  : Tdcache_data_t read (uint32_t          context,
-			       Tdcache_address_t address,
-			       Tdcache_type_t    type)
-  {
-    // Address's Read must be aligned
-
-    if ((address & _mask_addr) != 0)
-      TEST_KO("<Memory_t::read> Address is not aligned");
-
-    if (context>_nb_context)
-      TEST_KO("<Memory_t::read> nb context is too high");
-
-    if (address>_nb_word)
-      TEST_KO("<Memory_t::read> address is too high");
-    
-    return _data [context][address];
-  }
-
-public  : void write (uint32_t          context, 
-		      Tdcache_address_t address,
-		      Tdcache_type_t    type,
-		      Tdcache_data_t    data)
-  {
-    if (context>_nb_context)
-      TEST_KO("<Memory_t::read> nb context is too high");
-
-    if (address>_nb_word)
-      TEST_KO("<Memory_t::read> address is too high");
-
-    Tdcache_address_t LSB = address &  _mask;
-    Tdcache_address_t MSB = address & ~_mask;
-  
-    Tdcache_data_t write_data = data;
-    Tdcache_data_t read_data  = _data [context][MSB];
-
-    // exemple to size_data = 32b
-    // LSB index_min
-    // 0   0
-    // 1   8
-    // 2   16
-    // 3   24
-    uint32_t index_min = LSB<<3;
-    uint32_t index_max = index_min;
-    // index max, dependant of access's size
-
-    switch (type)
-      {
-
-
-      }
-  }
-};
+#define CYCLE_MAX     (1024*NB_ITERATION)
+
+#define LABEL(str)							\
+  {									\
+    cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
+  } while(0)
+
+#define SC_START(cycle_offset)						\
+  do									\
+    {									\
+      /*cout << "SC_START (begin)" << endl;*/				\
+									\
+      uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
+      if (cycle_offset != 0)						\
+	{								\
+	  cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
+	}								\
+									\
+      if (cycle_current > CYCLE_MAX)					\
+	{								\
+	  TEST_KO("Maximal cycles Reached");				\
+	}								\
+      sc_start(cycle_offset);						\
+      /*cout << "SC_START (end  )" << endl;*/				\
+    } while(0)
+
 
 //===================================================================={test}
-void test (string name,
+void test1 (string name,
 	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
 {
@@ -256,12 +45,12 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
 #endif
 
   Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
 #ifdef STATISTICS
-					     _parameters_statistics,
+							    _parameters_statistics,
 #endif
-					     _param);
+							    _param);
   
 #ifdef SYSTEMC
@@ -277,4 +66,6 @@
   sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
   sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_FRONT_END_ID          = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_OOO_ENGINE_ID         = new sc_signal<Tcontext_t        > (rename.c_str());
   sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
   sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
@@ -282,27 +73,27 @@
   sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
   sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
-//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
   sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
   sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
   sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-//sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  //sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
+//   sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
   sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
-//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
-//sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
-
-  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL        = new sc_signal<Tcontrol_t	 >(rename.c_str());
-  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK        = new sc_signal<Tcontrol_t	 >(rename.c_str());
-  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Toperation_t      > *  out_MEMORY_OUT_OPERATION  = new sc_signal<Toperation_t      >(rename.c_str());
-  sc_signal<Ttype_t           > *  out_MEMORY_OUT_TYPE       = new sc_signal<Ttype_t           >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD   = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
-  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD    = new sc_signal<Tgeneral_data_t   >(rename.c_str());
-//sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE   = new sc_signal<Tcontrol_t        >(rename.c_str());
-//sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
-//sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE    = new sc_signal<Tspecial_data_t   >(rename.c_str());
-  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION  = new sc_signal<Texception_t      >(rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  //sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
+
+  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID    = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_FRONT_END_ID  = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID     = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD    = new sc_signal<Tgeneral_address_t>(rename.c_str());
+  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD       = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+  //sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  //sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE    = new sc_signal<Tspecial_address_t>(rename.c_str());
+  //sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE       = new sc_signal<Tspecial_data_t   >(rename.c_str());
+  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION     = new sc_signal<Texception_t      >(rename.c_str());
 
   sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
@@ -312,5 +103,4 @@
   sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
   sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
-  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_UNCACHED   = new sc_signal<Tcontrol_t        >(rename.c_str());
   sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
   
@@ -322,16 +112,16 @@
   sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
   
-  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL        = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
-  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_CONTEXT_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
-  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG    = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
-  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA       = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
+  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL           = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
+  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
+  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG       = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
+  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA          = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
     
-    for (uint32_t i=0; i<_param->_size_load_queue; i++)
-      {
-	out_BYPASS_MEMORY_VAL        [i] = new sc_signal<Tcontrol_t        >;
-	out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t        >;
-	out_BYPASS_MEMORY_NUM_REG    [i] = new sc_signal<Tgeneral_address_t>;
-	out_BYPASS_MEMORY_DATA       [i] = new sc_signal<Tgeneral_data_t   >;
-      }
+  for (uint32_t i=0; i<_param->_size_load_queue; i++)
+    {
+      out_BYPASS_MEMORY_VAL           [i] = new sc_signal<Tcontrol_t        >(rename.c_str());
+      out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t        >(rename.c_str());
+      out_BYPASS_MEMORY_NUM_REG       [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
+      out_BYPASS_MEMORY_DATA          [i] = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+    }
   
   /********************************************************
@@ -346,43 +136,56 @@
   (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
   (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
-  (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
-  (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID         ))(*( in_MEMORY_IN_FRONT_END_ID         ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID        ))(*( in_MEMORY_IN_OOO_ENGINE_ID        ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
   (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
   (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
   (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
-//(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
   (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
   (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
   (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
-//(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
+//   (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
   (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
-//(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
-//(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
-  
-  (*(_Load_store_unit->out_MEMORY_OUT_VAL        ))(*(out_MEMORY_OUT_VAL        ));
-  (*(_Load_store_unit-> in_MEMORY_OUT_ACK        ))(*( in_MEMORY_OUT_ACK        ));
-  (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));
-  (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID  ))(*(out_MEMORY_OUT_PACKET_ID  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD   ))(*(out_MEMORY_OUT_WRITE_RD   ));
-  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));
-  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD    ))(*(out_MEMORY_OUT_DATA_RD    ));
-//(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE   ))(*(out_MEMORY_OUT_WRITE_RE   ));
-//(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));
-//(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE    ))(*(out_MEMORY_OUT_DATA_RE    ));
-  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION  ))(*(out_MEMORY_OUT_EXCEPTION  ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
+  
+  (*(_Load_store_unit->out_MEMORY_OUT_VAL           ))(*(out_MEMORY_OUT_VAL           ));
+  (*(_Load_store_unit-> in_MEMORY_OUT_ACK           ))(*( in_MEMORY_OUT_ACK           ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID    ))(*(out_MEMORY_OUT_CONTEXT_ID    ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID  ))(*(out_MEMORY_OUT_FRONT_END_ID  ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID     ))(*(out_MEMORY_OUT_PACKET_ID     ));
+  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD      ))(*(out_MEMORY_OUT_WRITE_RD      ));
+  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD    ))(*(out_MEMORY_OUT_NUM_REG_RD    ));
+  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD       ))(*(out_MEMORY_OUT_DATA_RD       ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE      ))(*(out_MEMORY_OUT_WRITE_RE      ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE    ))(*(out_MEMORY_OUT_NUM_REG_RE    ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE       ))(*(out_MEMORY_OUT_DATA_RE       ));
+  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION     ))(*(out_MEMORY_OUT_EXCEPTION     ));
 
   (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
   (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
-  (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
   (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
   (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
   (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
-  (*(_Load_store_unit->out_DCACHE_REQ_UNCACHED  ))(*(out_DCACHE_REQ_UNCACHED  ));
   (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
 
   (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
   (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
   (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
   (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
@@ -393,8 +196,9 @@
       for (uint32_t i=0; i<_param->_size_load_queue; i++)
 	{
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL        [i]))(*(out_BYPASS_MEMORY_VAL        [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))(*(out_BYPASS_MEMORY_CONTEXT_ID [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG    [i]))(*(out_BYPASS_MEMORY_NUM_REG    [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA       [i]))(*(out_BYPASS_MEMORY_DATA       [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL           [i]))(*(out_BYPASS_MEMORY_VAL           [i]));
+	  if (_param->_have_port_ooo_engine_id)    
+	    (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG       [i]))(*(out_BYPASS_MEMORY_NUM_REG       [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA          [i]))(*(out_BYPASS_MEMORY_DATA          [i]));
 	}
     }
@@ -409,5 +213,5 @@
 
   const uint32_t seed = 0;
-//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+  //const uint32_t seed = static_cast<uint32_t>(time(NULL));
 
   srand(seed);
@@ -416,12 +220,15 @@
   const uint32_t     nb_word      = nb_request;
 
-//const int32_t      percent_transaction_memory_in  = 100;
-  const int32_t      percent_transaction_memory_out = 100;
-  const int32_t      percent_transaction_dcache     = 100;
-
-  const int32_t      percent_exception              =   5;
+  //const int32_t      percent_transaction_memory_in  = 100;
+  const int32_t      percent_transaction_memory_out =  75;
+  const int32_t      percent_transaction_dcache     =  75;
+
+  const int32_t      percent_exception              =   0;
   const int32_t      percent_type_load              =   0;
-  const int32_t      percent_type_store             = 100;
-  const int32_t      percent_miss_spec              =   0;
+  const int32_t      percent_type_store             =  50;
+  const int32_t      percent_miss_spec              =  20;
+  
+  const uint32_t     miss_rate                      =  10;
+  const uint32_t     miss_penality                  =   5;
 
   if ((percent_type_load  +
@@ -439,15 +246,12 @@
   priority_queue<MemoryRequest_t> fifo_request;
 
-  // emulation of cache
-  Tdcache_data_t     cache_data                [_param->_nb_context][nb_word];
+  // emulation of memory
+  Memory_t                      * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data);
+  Cache_t                       * _cache  = new Cache_t  (miss_rate, miss_penality);
+
 
   SC_START(0);
 
   LABEL("Initialisation");
-
-  // emulate a memory
-  for (uint32_t i=0; i<_param->_nb_context; i++)
-    for (uint32_t j=0; j<nb_word; j++)
-      cache_data [i][j] = rand()%(1<<_param->_size_general_data);
 
   in_MEMORY_IN_VAL ->write(0);
@@ -462,229 +266,399 @@
   LABEL("Loop of Test");
 
-  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+  try 
     {
-      LABEL("Iteration "+toString(iteration));
-
-      LABEL("Structure's initialisation");
-
-      nb_request_memory_in  = 0;
-      nb_request_memory_out = 0;
-      nb_request_dcache     = 0;
+      for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+	{
+	  LABEL("Iteration "+toString(iteration));
+
+	  LABEL("Structure's initialisation");
+
+	  nb_request_memory_in  = 0;
+	  nb_request_memory_out = 0;
+	  nb_request_dcache     = 0;
       
-      // Fill the request_queue
+	  // Fill the request_queue
       
-      Tlsq_ptr_t         store_queue_ptr_write = 0;
-      Tlsq_ptr_t         load_queue_ptr_write  = 0;
-
-      bool               store_queue_use [_param->_size_store_queue];
-      bool               load_queue_use  [_param->_size_load_queue ];
-
-      for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	store_queue_use [i] = false;
-      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
-	load_queue_use  [i] = false;
-
-      double             current_cycle = sc_simulation_time();
-      double             cycle_min     = current_cycle;
-
-      LABEL("Fifo request initialisation");
-      // Init fifo_request
-      for (uint32_t i=0; i<nb_request; i++)
-	{
-	  double             cycle;
-	  Tcontext_t         context_id                = rand () % _param->_nb_context;
-	  Tpacket_t          packet_id                 = i;
-	  Tlsq_ptr_t         store_queue_ptr_write_old = store_queue_ptr_write;
-	  Tlsq_ptr_t         load_queue_ptr_write_old  = load_queue_ptr_write ;
-	  Toperation_t       operation;
+	  Tlsq_ptr_t         store_queue_ptr_write = 0;
+	  Tlsq_ptr_t         load_queue_ptr_write  = 0;
+
+	  bool               store_queue_use [_param->_size_store_queue];
+	  uint32_t           nb_store_slot_use = 0;
+	  bool               load_queue_use  [_param->_size_load_queue ];
+
+	  for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	    store_queue_use [i] = false;
+	  for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+	    load_queue_use  [i] = false;
+
+	  double             current_cycle = sc_simulation_time();
+	  double             cycle_min     = current_cycle;
+
+	  Toperation_t       operation_store [4] = {OPERATION_MEMORY_STORE_8,
+						    OPERATION_MEMORY_STORE_16,
+						    OPERATION_MEMORY_STORE_32,
+						    OPERATION_MEMORY_STORE_64};
+
+	  Toperation_t       operation_load  [8] = {OPERATION_MEMORY_LOAD_8_Z,
+						    OPERATION_MEMORY_LOAD_8_S,
+						    OPERATION_MEMORY_LOAD_16_Z,
+						    OPERATION_MEMORY_LOAD_16_S,
+						    OPERATION_MEMORY_LOAD_32_Z,
+						    OPERATION_MEMORY_LOAD_32_S,
+						    OPERATION_MEMORY_LOAD_64_Z,
+						    OPERATION_MEMORY_LOAD_64_S};
+
+	  Toperation_t       operation_other [5] = {OPERATION_MEMORY_LOCK           ,
+						    OPERATION_MEMORY_INVALIDATE     ,
+						    OPERATION_MEMORY_PREFETCH       ,
+						    OPERATION_MEMORY_FLUSH          ,
+						    OPERATION_MEMORY_SYNCHRONIZATION};
+
+
+	  const uint32_t nb_operation_store =   (log2(_param->_size_general_data/8)+1);
+	  const uint32_t nb_operation_load  = 2*(log2(_param->_size_general_data/8)+1);
+	  const uint32_t nb_operation_other = 5;
+
+	  LABEL("Fifo request initialisation");
+	  // Init fifo_request
+	  for (uint32_t i=0; i<nb_request; i++)
+	    {
+	      double       cycle;
+	      Tcontext_t   context_id                = 0;
+	      Tcontext_t   front_end_id              = 0;
+	      Tcontext_t   ooo_engine_id             = rand () % _param->_nb_ooo_engine;
+	      Tpacket_t    packet_id                 = i;
+	      Tlsq_ptr_t   store_queue_ptr_write_old = store_queue_ptr_write;
+	      Tlsq_ptr_t   load_queue_ptr_write_old  = load_queue_ptr_write ;
+	      Toperation_t operation;
 	  
-	  int32_t            percent = rand()%100;
-
-	  uint32_t           size_queue;
+	      int32_t      percent = rand()%100;
+
+	      uint32_t     size_queue;
 	 
-	  if (percent <= seuil_type_load)
-	    {
-// 	      LABEL(" * LOAD");
-	      operation            = OPERATION_MEMORY_LOAD_16_S;
-	      size_queue           = _param->_size_load_queue;
-	      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
-	    }
-	  else
-	    {
-	      if (percent <= seuil_type_store)
+	      if (percent < seuil_type_load)
 		{
-// 		  LABEL(" * STORE");
-		  operation             = OPERATION_MEMORY_STORE_16;
-		  size_queue            = _param->_size_store_queue;
-		  store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
+		  LABEL(" * LOAD");
+		  operation            = operation_load[(rand()%nb_operation_load)];
+		  size_queue           = _param->_size_load_queue;
+		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
 		}
 	      else
 		{
-// 		  LABEL(" * OTHERS");
-		  operation            = OPERATION_MEMORY_PREFETCH;
-		  size_queue           = _param->_size_load_queue;
-		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		  if (percent < seuil_type_store)
+		    {
+		      LABEL(" * STORE");
+		  
+		  
+		      operation             = operation_store[(rand()%nb_operation_store)];
+		      size_queue            = _param->_size_store_queue;
+		      store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
+		    }
+		  else
+		    {
+		      LABEL(" * OTHERS");
+		      operation            = operation_other[(rand()%nb_operation_other)];
+		      // 		  operation            = operation_other[4];
+		      size_queue           = _param->_size_load_queue;
+		      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		    }
+		}
+
+	      cycle = cycle_min;
+	      cycle_min ++;
+
+	      Ttype_t            type    = TYPE_MEMORY;
+	      Tgeneral_data_t    address = rand()%(nb_word);
+	      Tgeneral_data_t    offset  = rand()%(nb_word);
+
+	      // LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset));
+
+	      percent = rand()%100;
+	      if (percent > percent_exception) 
+		address = address & (~ mask_memory_access(operation));
+	  
+	      // LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation))));
+
+	      if (offset > address) // max
+		offset  = address;
+
+	      Tgeneral_data_t    immediat      = offset;
+	      Tgeneral_data_t    data_ra       = address - offset;
+
+	      // LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat));
+	  
+	      Tgeneral_data_t    data_rb       = static_cast<Tgeneral_data_t>(rand());
+	      Tcontrol_t         write_rd      = 0;
+	      Tgeneral_address_t num_reg_rd    = 0;
+	      bool               write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec);
+
+	      tab_request [i].modif(cycle                    ,
+				    context_id               ,
+				    front_end_id             ,
+				    ooo_engine_id            ,
+				    packet_id                ,
+				    operation                ,
+				    type                     ,
+				    store_queue_ptr_write_old,
+				    load_queue_ptr_write_old ,
+				    immediat                 ,
+				    data_ra                  ,
+				    data_rb                  ,
+				    write_rd                 ,
+				    num_reg_rd               ,
+				    write_spec_ko);
+
+	      cout << tab_request [i] << endl;
+	
+	      fifo_request.push(tab_request [i]);
+
+	      double cycle_head = 0;
+
+	      if (is_operation_memory_store(operation))
+		{
+		  cycle_head = cycle_min;
+		  cycle_min ++;
+
+		  cout << "         * Write head : " << toString(cycle_head) 
+		       << endl
+		       << endl;
+	      
+		  fifo_request.push(MemoryRequest_t(cycle_head,
+						    context_id,
+						    front_end_id,
+						    ooo_engine_id,
+						    packet_id,
+						    (write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
+						    type,
+						    store_queue_ptr_write_old,
+						    0,
+						    0,
+						    0,
+						    0,
+						    0,
+						    0,
+						    write_spec_ko));
 		}
 	    }
-
-	  cycle      = cycle_min;
-	  cycle_min ++;
-
-	  Ttype_t            type                  = TYPE_MEMORY;
-	  Tgeneral_data_t    address               = rand()%(nb_word);
-	  Tgeneral_data_t    offset                = rand()%(nb_word);
-
-	  percent = rand()%100;
-	  if (percent > percent_exception) 
-	    address = address & (not mask_memory_access(operation));
-
-	  if (offset > address) // max
-	    offset  = address;
-
-	  Tgeneral_data_t    immediat              = offset;
-	  Tgeneral_data_t    data_ra               = address - offset;
-	  Tgeneral_data_t    data_rb               = rand()%(1<<_param->_size_general_data);
-	  Tcontrol_t         write_rd              = 0;
-	  Tgeneral_address_t num_reg_rd            = 0;
-	  bool               write_spec_ko         = ((rand()%100)<percent_miss_spec);
-
-	  tab_request [i].modif(cycle                ,
-				context_id           ,
-				packet_id            ,
-				operation            ,
-				type                 ,
-				store_queue_ptr_write_old,
-				load_queue_ptr_write_old ,
-				immediat             ,
-				data_ra              ,
-				data_rb              ,
-				write_rd             ,
-				num_reg_rd           ,
-				write_spec_ko
-				);
-
-	  cout << tab_request [i] << endl;
-	
-	  fifo_request.push(tab_request [i]);
-
-	  double cycle_head = 0;
-
-	  if (is_operation_memory_store(operation))
+        
+	  LABEL("Simulation of this iteration ...");
+    
+	  while (nb_request_memory_out < nb_request)
 	    {
-	      cycle_head = cycle_min;
-	      cycle_min ++;
-
-	      cout << "         * Write head : " << toString(cycle_head) 
-		   << endl
-		   << endl;
+	      cout << "*********************************************" << endl;
+	      cout << "Dump STORE_QUEUE_USE : " << endl;
+	      cout << " use " << nb_store_slot_use << endl;
+	      for (uint32_t i=0; i<_param->_size_store_queue; i++)
+		cout << "  [" << i << "] " << store_queue_use [i] << endl;
+	      cout << "Dump LOAD_QUEUE_USE : " << endl;
+	      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+		cout << "  [" << i << "] " << load_queue_use [i] << endl;
+	      cout << "*********************************************" << endl;
+
+
+	      // ***** MEMORY_IN *****
+
+	      // memory_in_val depends of three factors :
+	      //  1) request's fifo is not empty ?
+	      //  2) the slot destination is free ?
+	      //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
+
+	      bool can_execute = false;
+
+	      if (is_operation_memory_store(fifo_request.top()._operation))
+		can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
+	      else
+		can_execute = not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
+	  
+	      in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 
+				       can_execute                and 
+				       (sc_simulation_time() >= fifo_request.top()._cycle));
+
+	      if (_param->_have_port_context_id)
+		in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
+	      if (_param->_have_port_front_end_id)
+		in_MEMORY_IN_FRONT_END_ID         ->write (fifo_request.top()._front_end_id         );
+	      if (_param->_have_port_ooo_engine_id)
+		in_MEMORY_IN_OOO_ENGINE_ID        ->write (fifo_request.top()._ooo_engine_id        );
+	      if (_param->_have_port_packet_id)
+		in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
+	      in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
+	      in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
+	      in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
+	      in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
+	      in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
+	      in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
+	      in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
+// 	      in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
+	      in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
+
+	      in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
+
+	      // ***** DCACHE_REQ *****
+	      in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+
+	      // ***** DCACHE_RSP *****
+	      bool have_rsp = _cache->have_rsp ();
+	      in_DCACHE_RSP_VAL->write(have_rsp);
+
+	      if (have_rsp)
+		{
+		  in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
+		  in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
+		  in_DCACHE_RSP_RDATA     ->write(_cache->front()._rdata     );
+		  in_DCACHE_RSP_ERROR     ->write(_cache->front()._error     );
+		}
+
+	      SC_START(0);
+
+	      LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	      LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
+	      LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
+	      LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
+	      LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
+	      LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
+	      LABEL("  * can_execute                            : "+toString(can_execute));
+
+	      if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
+		{
+		  LABEL(" * Accepted MEMORY_IN  : " + toString(nb_request_memory_in));
+		  cout << fifo_request.top();
+
+		  if (is_operation_memory_store(fifo_request.top()._operation))
+		    {
+		      if (not is_operation_memory_store_head(fifo_request.top()._operation))
+			{
+			  store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
+			  nb_store_slot_use ++;
+			}
+		    }
+		  else
+		    load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
+
+		  fifo_request.pop();
 	      
-	      fifo_request.push(MemoryRequest_t(cycle_head,
-						context_id,
-						packet_id,
-						(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
-						type,
-						store_queue_ptr_write_old,
-						0,
-						0,
-						0,
-						0,
-						0,
-						0,
-						write_spec_ko));
+		  nb_request_memory_in ++;
+		}
+
+	      LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
+	      if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
+		{
+		  Tpacket_t  packet_id = out_MEMORY_OUT_PACKET_ID->read();
+
+		  LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
+
+		  if (is_operation_memory_store(tab_request[packet_id]._operation))
+		    {
+		      store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
+		      nb_store_slot_use --;
+		    }
+		  else
+		    load_queue_use  [tab_request[packet_id]._load_queue_ptr_write] = false;
+
+		  nb_request_memory_out ++;
+
+		  // a lot of test
+		  TEST(Tcontext_t        , out_MEMORY_OUT_CONTEXT_ID   ->read(), tab_request[packet_id]._context_id   );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
+		  TEST(Tpacket_t         , out_MEMORY_OUT_PACKET_ID    ->read(), tab_request[packet_id]._packet_id    );
+		  TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), tab_request[packet_id]._write_rd     );
+		  TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD   ->read(), tab_request[packet_id]._num_reg_rd   );
+
+		  Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
+		  if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))))
+		    TEST(Texception_t      , out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_ALIGNMENT);
+		  else
+		    {
+		      if (tab_request[packet_id]._write_spec_ko)
+			TEST(Texception_t, out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_MISS_SPECULATION);
+		      else
+			{
+			  TEST(Texception_t, out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_NONE);
+
+			  if (is_operation_memory_load(tab_request[packet_id]._operation))
+			    {
+			      Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+									     (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) |
+									     (tab_request[packet_id]._context_id)),
+									    (tab_request[packet_id]._immediat +
+									     tab_request[packet_id]._data_ra), 
+									    tab_request[packet_id]._operation);
+			      cout << "MEMORY_OUT is a LOAD" << endl
+				   << "  * operation       : " << tab_request[packet_id]._operation << endl
+				   << std::hex
+				   << "  * address         : " << (tab_request[packet_id]._immediat +
+								   tab_request[packet_id]._data_ra) << endl
+				   << "  * read_lsq        : " << read_lsq << endl
+				   << "  * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl
+				   << std::dec;
+			  
+// 			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), read_lsq);
+			    }
+			}
+		    }
+		}
+
+	      LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
+	      if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+		{
+		  Tcontext_t   context_id;
+		  Tpacket_t    packet_id ; 
+		  if (_param->_have_port_dcache_context_id)
+		    context_id = out_DCACHE_REQ_CONTEXT_ID->read();
+		  else
+		    context_id = 0;
+
+		  packet_id  = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
+	      
+		  LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
+
+// 		  TEST(Tcontext_t       ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+// 									    (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) |
+// 									    (tab_request[packet_id]._context_id)));
+// 		  TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS   ->read(),(tab_request[packet_id]._immediat +
+// 									    tab_request[packet_id]._data_ra) );
+// 		  TEST(Tdcache_type_t   ,out_DCACHE_REQ_TYPE      ->read(), operation_to_dcache_type(operation));
+		  
+// 		  if (is_operation_memory_store(operation))
+// 		    TEST(Tdcache_data_t   ,out_DCACHE_REQ_WDATA     ->read(),tab_request[packet_id]._data_rb);
+
+		  Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
+
+		  // test type : send or not a respons !
+		  LABEL("   * rdata : " + toString(rdata));
+
+		  if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or
+		      (out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD))
+		    {
+		      LABEL("     * have_dcache_rsp");
+		  
+		      _cache->push (context_id,
+				    out_DCACHE_REQ_PACKET_ID ->read(),
+				    rdata     ,
+				    0);
+		    }
+		}
+
+	      LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
+	      if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
+		{
+		  _cache->pop();
+		}
+
+	      _cache->end_cycle();
+
+	      SC_START(1);
 	    }
-  	}
-        
-      LABEL("Simulation of this iteration ...");
-    
-      while (nb_request_memory_out < nb_request)
-	{
-	  // ***** MEMORY_IN *****
-
-	  // memory_in_val depends of three factors :
-	  //  1) request's fifo is not empty ?
-	  //  2) the slot destination is free ?
-	  //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
-
-	  bool can_execute = false;
-
-	  if (is_operation_memory_store(fifo_request.top()._operation))
-	    can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);
-	  else
-	    can_execute = not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
-	  
-	  in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 
-				   can_execute                and 
-				   (sc_simulation_time() >= fifo_request.top()._cycle));
-
-	  in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
-	  in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
-	  in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
-	  in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
-	  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
-   	  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
-	  in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
-	  in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
-	  in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
-	  in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
-	  in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
-
-	  in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
-
-	  // ***** DCACHE_REQ *****
-	  in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
-
-	  SC_START(0);
-  
-	  SC_START(1);
-
-	  LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
-	  LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
-	  LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
-	  LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
-	  LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
-	  LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
-	  LABEL("  * can_execute                            : "+toString(can_execute));
-
-	  if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
-	    {
-	      LABEL(" * Accepted MEMORY_IN  : " + toString(nb_request_memory_in));
-	      cout << fifo_request.top();
-
-	      if (is_operation_memory_store(fifo_request.top()._operation))
-		{
-		  if (not is_operation_memory_store_head(fifo_request.top()._operation))
-		    store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
-		}
-	      else
-		load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
-
-	      fifo_request.pop();
-	      
-	      nb_request_memory_in ++;
-	    }
-
-	  LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
-	  if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
-	    {
-	      LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));
-
-	      if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
-		store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;
-	      else
-		load_queue_use  [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;
-
-	      nb_request_memory_out ++;
-	    }
-
-	  LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
-	  if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
-	    {
-	      LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));
-
-	      // test type : send or not a respons !
-	    }
-
 	}
     }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      _memory->trace();
+      throw (error);
+    }
+
+  _memory->trace();
+
   
   /********************************************************
@@ -699,36 +673,37 @@
   delete     in_NRESET;
 
-  delete     in_MEMORY_IN_VAL                  ;
-  delete    out_MEMORY_IN_ACK                  ;
-  delete     in_MEMORY_IN_CONTEXT_ID           ;
-  delete     in_MEMORY_IN_PACKET_ID            ;
-  delete     in_MEMORY_IN_OPERATION            ;
-  delete     in_MEMORY_IN_TYPE                 ;
+  delete     in_MEMORY_IN_VAL         ;
+  delete    out_MEMORY_IN_ACK         ;
+  delete     in_MEMORY_IN_CONTEXT_ID  ;
+  delete     in_MEMORY_IN_FRONT_END_ID  ;
+  delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
+  delete     in_MEMORY_IN_PACKET_ID   ;
+  delete     in_MEMORY_IN_OPERATION   ;
   delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
   delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-//delete     in_MEMORY_IN_HAS_IMMEDIAT         ;
-  delete     in_MEMORY_IN_IMMEDIAT             ;
-  delete     in_MEMORY_IN_DATA_RA              ;
-  delete     in_MEMORY_IN_DATA_RB              ;
-//delete     in_MEMORY_IN_DATA_RC              ;
-  delete     in_MEMORY_IN_WRITE_RD             ;
-  delete     in_MEMORY_IN_NUM_REG_RD           ;
-//delete     in_MEMORY_IN_WRITE_RE             ;
-//delete     in_MEMORY_IN_NUM_REG_RE           ;
-
+  //delete     in_MEMORY_IN_HAS_IMMEDIAT;
+  delete     in_MEMORY_IN_IMMEDIAT    ;
+  delete     in_MEMORY_IN_DATA_RA     ;
+  delete     in_MEMORY_IN_DATA_RB     ;
+  //delete     in_MEMORY_IN_DATA_RC     ;
+//   delete     in_MEMORY_IN_WRITE_RD    ;
+  delete     in_MEMORY_IN_NUM_REG_RD  ;
+  //delete     in_MEMORY_IN_WRITE_RE    ;
+  //delete     in_MEMORY_IN_NUM_REG_RE  ;
+    
   delete    out_MEMORY_OUT_VAL       ;
   delete     in_MEMORY_OUT_ACK       ;
   delete    out_MEMORY_OUT_CONTEXT_ID;
+  delete    out_MEMORY_OUT_FRONT_END_ID;
+  delete    out_MEMORY_OUT_OOO_ENGINE_ID;
   delete    out_MEMORY_OUT_PACKET_ID ;
-  delete    out_MEMORY_OUT_OPERATION ;
-  delete    out_MEMORY_OUT_TYPE      ;
   delete    out_MEMORY_OUT_WRITE_RD  ;
   delete    out_MEMORY_OUT_NUM_REG_RD;
   delete    out_MEMORY_OUT_DATA_RD   ;
-//delete    out_MEMORY_OUT_WRITE_RE  ;
-//delete    out_MEMORY_OUT_NUM_REG_RE;
-//delete    out_MEMORY_OUT_DATA_RE   ;
+  //delete    out_MEMORY_OUT_WRITE_RE  ;
+  //delete    out_MEMORY_OUT_NUM_REG_RE;
+  //delete    out_MEMORY_OUT_DATA_RE   ;
   delete    out_MEMORY_OUT_EXCEPTION ;
-
+  
   delete    out_DCACHE_REQ_VAL       ;
   delete     in_DCACHE_REQ_ACK       ;
@@ -737,7 +712,6 @@
   delete    out_DCACHE_REQ_ADDRESS   ;
   delete    out_DCACHE_REQ_TYPE      ;
-  delete    out_DCACHE_REQ_UNCACHED  ;
   delete    out_DCACHE_REQ_WDATA     ;
-
+  
   delete     in_DCACHE_RSP_VAL       ;
   delete    out_DCACHE_RSP_ACK       ;
@@ -746,13 +720,17 @@
   delete     in_DCACHE_RSP_RDATA     ;
   delete     in_DCACHE_RSP_ERROR     ;
-
-  delete [] out_BYPASS_MEMORY_VAL       ;
-  delete [] out_BYPASS_MEMORY_CONTEXT_ID;
-  delete [] out_BYPASS_MEMORY_NUM_REG   ;
-  delete [] out_BYPASS_MEMORY_DATA      ;
-
+  
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      delete [] out_BYPASS_MEMORY_VAL       ;
+      delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
+      delete [] out_BYPASS_MEMORY_NUM_REG   ;
+      delete [] out_BYPASS_MEMORY_DATA      ;
+    }
 #endif
 
   delete _Load_store_unit;
+  delete _memory;
+  delete _cache;
 #ifdef STATISTICS
   delete _parameters_statistics;
