Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 62)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 71)
@@ -1,10 +1,12 @@
 Load_store_unit
-2	2	*2	# store_size_queue       
+3	3	*2	# store_size_queue       
 2	2	*2	# load_size_queue        
 2	2	*2	# size_speculative_access_queue
 2	2	+1	# nb_port_check
 2	2	+1	# speculative_load       {none,access,commit,bypass}
-2	2	*2	# nb_context             
-16	16	*2	# nb_packet              
+2	2	*2	# nb_context             1	1	*2	
+2	2	*2	# nb_front_end		 1	1	*2	
+2	2	*2	# nb_ooo_engine          1	1	*2	
+64	64	*2	# nb_packet              
 32	32	*2	# size_general_data      
 32	32	*2	# nb_general_register    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Cache.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Cache.h	(revision 71)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Cache.h	(revision 71)
@@ -0,0 +1,128 @@
+#ifndef CACHE_H
+#define CACHE_H
+
+#include "Common/include/BitManipulation.h"
+#include "Common/include/Debug.h"
+#include "Common/include/Log2.h"
+#include "Common/include/Test.h"
+#include "Behavioural/include/Constants.h"
+#include "Behavioural/include/Types.h"
+#include <list>
+
+//================================================================={Cache_t}
+
+typedef int32_t cycle_t;
+
+typedef struct 
+{
+  cycle_t                               _cycle     ;
+  morpheo::behavioural::Tcontext_t      _context_id;
+  morpheo::behavioural::Tpacket_t       _packet_id ;
+  morpheo::behavioural::Tdcache_data_t  _rdata     ;
+  morpheo::behavioural::Tdcache_error_t _error     ;
+} cache_rsp_t;
+
+class Cache_t
+{
+private : const uint32_t    _miss_rate;
+private : const uint32_t    _miss_penality;
+private : list<cache_rsp_t> _list_respons;
+					 
+public  : Cache_t (uint32_t miss_rate, uint32_t miss_penality):
+  _miss_rate     (miss_rate    ),
+  _miss_penality (miss_penality)
+  {
+//     srand(0);
+
+    if (miss_rate > 100)
+      throw morpheo::ErrorMorpheo(_("Miss_rate can be higher than 100"));
+  }
+
+public  : ~Cache_t (void)
+  {
+  }
+
+public  : void push (morpheo::behavioural::Tcontext_t      context_id,
+		     morpheo::behavioural::Tpacket_t       packet_id ,
+		     morpheo::behavioural::Tdcache_data_t  rdata     ,
+		     morpheo::behavioural::Tdcache_error_t error     )
+  {
+    cycle_t cycle = ((static_cast<uint32_t>(rand())%100)<_miss_rate)?_miss_penality:1;
+
+    cache_rsp_t rsp;
+
+    rsp._cycle      = cycle     ;
+    rsp._context_id = context_id;
+    rsp._packet_id  = packet_id ;
+    rsp._rdata      = rdata     ;
+    rsp._error      = error     ;
+
+    // find good place
+    list<cache_rsp_t>::iterator i;
+    for(i = _list_respons.begin(); (i != _list_respons.end()) and (i->_cycle<=cycle); i++);
+
+    _list_respons.insert(i,rsp);
+  }
+
+public  : void pop (void)
+  {
+    _list_respons.pop_front();
+  }
+
+public  : cache_rsp_t front (void)
+  {
+    return _list_respons.front();
+  }
+
+public  : bool have_rsp (void)
+  {
+    return (not _list_respons.empty()) and (_list_respons.front()._cycle <= 0);
+  }
+
+public  : void end_cycle (void)
+  {
+    for(list<cache_rsp_t>::iterator i = _list_respons.begin(); i != _list_respons.end(); i++)
+      {
+	i->_cycle --;
+      }
+  }
+
+public  : void print (void)
+  {
+    for(list<cache_rsp_t>::iterator i = _list_respons.begin(); i != _list_respons.end(); i++)
+      {
+	std::cout << "{" << i->_cycle << "}\t" 
+		  << i->_context_id << " - "
+		  << i->_packet_id  << " - "
+		  << i->_rdata      << " - "
+		  << i->_error      << std::endl;
+	  
+      }
+  }
+};
+
+inline void test_Cache_t (void)
+{
+  
+  Cache_t * cache = new Cache_t (30,12);
+
+  uint32_t cpt = 0;
+  for (uint32_t i=0; i<10; i++)
+    {
+      for (uint32_t j=0; j<5; j++)
+	cache->push(0,cpt++,0,0);
+
+      for (uint32_t j=0; j<3; j++)
+	if (cache->have_rsp())
+	  {
+	    std::cout << "pop : " << cache->front()._packet_id << std::endl;
+	    cache->pop();
+	  }
+      cache->print();
+      cache->end_cycle();
+    }
+
+  delete cache;
+}
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 71)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 71)
@@ -0,0 +1,335 @@
+#ifndef MEMORY_H
+#define MEMORY_H
+
+#include <list>
+#include "systemc.h"
+#include "Common/include/BitManipulation.h"
+#include "Common/include/Debug.h"
+#include "Common/include/Log2.h"
+#include "Common/include/Test.h"
+#include "Behavioural/include/Constants.h"
+#include "Behavioural/include/Types.h"
+
+//================================================================{Memory_t}
+typedef struct 
+{
+  double                                  _cycle   ;
+  uint32_t                                _context ;
+  morpheo::behavioural::Tdcache_address_t _address ;
+  morpheo::behavioural::Tdcache_type_t    _type    ;
+  morpheo::behavioural::Tdcache_data_t    _data_old;
+  morpheo::behavioural::Tdcache_data_t    _data_new;
+} trace_memory_t;
+
+class Memory_t
+{
+private : const uint32_t          _nb_context;
+private : const uint32_t          _nb_word   ;
+private : const uint32_t          _size_word ;
+private : const uint32_t          _shift_addr;
+private : const morpheo::behavioural::Tdcache_address_t _mask_addr ;
+private :       morpheo::behavioural::Tdcache_data_t ** _data      ;
+  
+private : std::list<trace_memory_t> _trace_memory;
+
+public  : Memory_t (uint32_t nb_context, 
+		    uint32_t nb_word, 
+		    uint32_t size_word):
+  _nb_context   (nb_context),
+  _nb_word      (nb_word   ),
+  _size_word    (size_word ),
+  _shift_addr   (morpheo::log2(size_word/8)),
+  _mask_addr    (morpheo::gen_mask<morpheo::behavioural::Tdcache_address_t>(_shift_addr))
+  {
+    _data = new morpheo::behavioural::Tdcache_data_t * [nb_context];
+    
+    for (uint32_t i=0; i<nb_context; i++)
+      {
+	_data [i] = new morpheo::behavioural::Tdcache_data_t [nb_word];
+	
+	// random data
+	for (uint32_t j=0; j<nb_word; j++)
+	  _data [i][j] = static_cast<morpheo::behavioural::Tdcache_data_t>(rand());
+      }
+
+    cout << "=====[ Memory's information ]" << endl
+	 << "  * _nb_context : " << _nb_context << endl
+	 << "  * _nb_word    : " << _nb_word    << endl
+	 << "  * _size_word  : " << _size_word  << endl
+	 << "  * _shift_addr : " << _shift_addr << endl
+	 << "  * _mask_addr  : " << hex << _mask_addr << dec << endl;
+  }
+
+public  : ~Memory_t (void)
+  {
+    delete [] _data;
+  }
+
+public  : morpheo::behavioural::Tdcache_data_t access (uint32_t          context, 
+						       morpheo::behavioural::Tdcache_address_t address,
+						       morpheo::behavioural::Tdcache_type_t    type,
+						       morpheo::behavioural::Tdcache_data_t    data)
+  {
+    cout << "<Memory::access>" << endl
+	 << " * context : " << context << endl
+	 << " * address : " << hex << address << dec << endl
+	 << " * type    : " << type << endl
+	 << " * wdata   : " << hex << data << dec << endl;
+
+    morpheo::behavioural::Tdcache_data_t rdata;
+
+    if (type == DCACHE_LOAD)
+      rdata = read  (context, address, type);
+    else
+      if ((type == DCACHE_STORE_8 ) or
+	  (type == DCACHE_STORE_16) or
+	  (type == DCACHE_STORE_32) or
+	  (type == DCACHE_STORE_64) )
+	rdata = write (context, address, type, data);
+      else
+	rdata = other (context, address, type);
+
+    cout << " * rdata   : " << hex << rdata << dec << endl;
+
+    return rdata;
+  }
+
+public  : morpheo::behavioural::Tdcache_data_t read_lsq (uint32_t          context,
+							 morpheo::behavioural::Tdcache_address_t address,
+							 morpheo::behavioural::Tdcache_type_t    type)
+  {
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    morpheo::behavioural::Tdcache_address_t LSB = address &  _mask_addr;
+    morpheo::behavioural::Tdcache_address_t MSB = address >> _shift_addr;
+
+    if (MSB >_nb_word)
+      TEST_KO("<Memory_t::read> address is too high : %8.x", address);
+    
+    morpheo::behavioural::Tdcache_data_t data = _data [context][MSB] >> (LSB<<3);
+
+    switch (type)
+      {
+      case OPERATION_MEMORY_LOAD_8_Z  : 
+      case OPERATION_MEMORY_LOAD_16_Z : 
+      case OPERATION_MEMORY_LOAD_32_Z : 
+      case OPERATION_MEMORY_LOAD_64_Z : 
+      case OPERATION_MEMORY_LOAD_8_S  : 
+      case OPERATION_MEMORY_LOAD_16_S : 
+      case OPERATION_MEMORY_LOAD_32_S : 
+      case OPERATION_MEMORY_LOAD_64_S : return morpheo::extend<morpheo::behavioural::Tdcache_data_t>(_size_word,data, is_operation_memory_load_signed(type),memory_size(type));
+      default : TEST_KO("<Memory_t::read_lsq> invalide type"); return data;
+      }
+  }
+
+private : morpheo::behavioural::Tdcache_data_t read (uint32_t context,
+						     morpheo::behavioural::Tdcache_address_t address,
+						     morpheo::behavioural::Tdcache_type_t type)
+  {
+    // Address's Read must be aligned
+
+    if ((address & _mask_addr) != 0)
+      TEST_KO("<Memory_t::read> Address is not aligned");
+
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    morpheo::behavioural::Tdcache_address_t MSB = address >> _shift_addr;
+
+    if (MSB >_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+
+    morpheo::behavioural::Tdcache_data_t rdata = _data [context][MSB];
+    trace_memory_t trace;
+
+    trace._cycle    = sc_simulation_time();
+    trace._context  = context;
+    trace._address  = address;
+    trace._type     = type;
+    trace._data_old = rdata;
+    trace._data_new = rdata;
+
+    _trace_memory.push_back(trace);
+    
+    return rdata;
+  }
+
+private : morpheo::behavioural::Tdcache_data_t write (uint32_t context, 
+						      morpheo::behavioural::Tdcache_address_t address,
+						      morpheo::behavioural::Tdcache_type_t type,
+						      morpheo::behavioural::Tdcache_data_t data)
+  {
+    cout << "   * write" << endl;
+
+    if (context>_nb_context)
+      TEST_KO("<Memory_t::read> nb context is too high");
+
+    if (address>_nb_word)
+      TEST_KO("<Memory_t::read> address is too high");
+
+    morpheo::behavioural::Tdcache_address_t LSB = address &  _mask_addr;
+    morpheo::behavioural::Tdcache_address_t MSB = address >> _shift_addr;
+
+    cout << hex
+	 << "     * LSB         : " << LSB << endl
+	 << "     * MSB         : " << MSB << endl
+	 << dec;
+  
+    morpheo::behavioural::Tdcache_data_t data_old    = _data [context][MSB];
+
+    // exemple to size_word = 32b
+    // LSB index_min
+    // 0   0
+    // 1   8
+    // 2   16
+    // 3   24
+
+    uint32_t memory_size = ((type==DCACHE_STORE_16)?MEMORY_SIZE_16:
+			    ((type==DCACHE_STORE_32)?MEMORY_SIZE_32:
+			     ((type==DCACHE_STORE_64 )?MEMORY_SIZE_64:MEMORY_SIZE_8)));
+
+    uint32_t index_min = LSB<<3; // *8
+    uint32_t index_max = index_min+memory_size;
+
+    cout << "     * type        : " << type << endl
+	 << "     * memory_size : " << memory_size << endl
+	 << "     * index_min   : " << index_min << endl
+	 << "     * index_max   : " << index_max << endl;
+    
+    morpheo::behavioural::Tdcache_data_t data_insert = data<<index_min; // the data is aligned at LSB
+
+//     cout << "read :" << endl
+// 	 << " * context     : " << context << endl
+// 	 << hex		    
+// 	 << " * address     : " << address << endl
+// 	 << "   * LSB       : " << LSB       << endl
+// 	 << "   * MSB       : " << MSB       << endl
+// 	 << dec
+// 	 << "   * index_min : " << index_min << endl
+// 	 << "   * index_max : " << index_max << endl
+// 	 << " * type        : " << type    << endl;
+
+    if (index_max > _size_word)
+      TEST_KO("<Memory_t::read> illegal value of index_max : %d, size_word is %d.",index_max,_size_word);
+
+    morpheo::behavioural::Tdcache_data_t data_new = morpheo::insert<morpheo::behavioural::Tdcache_data_t>(data_old, data_insert, index_max-1, index_min);
+
+    _data [context][MSB] = data_new;
+    
+    cout << hex
+	 << "     * data_old    : " << data_old << endl
+	 << "     * data_new    : " << data_new << endl
+	 << dec;
+
+
+    trace_memory_t trace;
+
+    trace._cycle    = sc_simulation_time();
+    trace._context  = context;
+    trace._address  = address;
+    trace._type     = type;
+    trace._data_old = data_old;
+    trace._data_new = data_new;
+
+    _trace_memory.push_back(trace);
+  
+    return data_old;
+  }
+
+private : morpheo::behavioural::Tdcache_data_t other (uint32_t context,
+						      morpheo::behavioural::Tdcache_address_t address,
+						      morpheo::behavioural::Tdcache_type_t type)
+  {
+    trace_memory_t trace;
+
+    trace._cycle    = sc_simulation_time();
+    trace._context  = context;
+    trace._address  = address;
+    trace._type     = type;
+    trace._data_old = 0;
+    trace._data_new = 0;
+
+    _trace_memory.push_back(trace);
+
+    return 0;
+  }
+
+public : void trace (void)
+  {
+    for (std::list<trace_memory_t>::iterator i=_trace_memory.begin(); i!= _trace_memory.end(); i++)
+      {
+	std::cout << "{" << i->_cycle << "}\t"
+		  << i->_context << " - ";
+
+	switch(i->_type)
+	  {
+	  case DCACHE_LOAD            : std::cout << "DCACHE_LOAD           "; break;
+	  case DCACHE_LOCK            : std::cout << "DCACHE_LOCK           "; break;
+	  case DCACHE_INVALIDATE      : std::cout << "DCACHE_INVALIDATE     "; break;
+	  case DCACHE_PREFETCH        : std::cout << "DCACHE_PREFETCH       "; break;
+	  case DCACHE_FLUSH           : std::cout << "DCACHE_FLUSH          "; break;
+	  case DCACHE_SYNCHRONIZATION : std::cout << "DCACHE_SYNCHRONIZATION"; break;
+	  case DCACHE_STORE_8         : std::cout << "DCACHE_STORE_8        "; break;
+	  case DCACHE_STORE_16        : std::cout << "DCACHE_STORE_16       "; break;
+	  case DCACHE_STORE_32        : std::cout << "DCACHE_STORE_32       "; break;
+	  case DCACHE_STORE_64        : std::cout << "DCACHE_STORE_64       "; break;
+	  }
+	std::cout << " - "
+		  << hex
+		  << i->_address << " : "
+		  << i->_data_old << " -> "
+		  << i->_data_new << std::endl
+		  << hex;
+      }
+  }
+};
+
+inline void test_Memory_t (void)
+{
+  const uint32_t _nb_context =   4;
+  const uint32_t _size_word  =  32;
+  const uint32_t _nb_word    = 100; 
+  
+  Memory_t * memory = new Memory_t (_nb_context, _nb_word, _size_word);
+  
+  memory -> access (2, 0x10, DCACHE_STORE_32, 0xdeadbeef);
+  memory -> access (2, 0x14, DCACHE_STORE_16, 0xdada5678);
+  memory -> access (2, 0x16, DCACHE_STORE_16, 0xbead1234);
+  memory -> access (2, 0x18, DCACHE_STORE_8 , 0x45675681);
+  memory -> access (2, 0x19, DCACHE_STORE_8 , 0x1f311219);
+  memory -> access (2, 0x1a, DCACHE_STORE_8 , 0x2e075607);
+  memory -> access (2, 0x1b, DCACHE_STORE_8 , 0x19811221);
+  
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> access (2, 0x10, DCACHE_LOAD, 0), 0xdeadbeef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> access (2, 0x14, DCACHE_LOAD, 0), 0x12345678);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> access (2, 0x18, DCACHE_LOAD, 0), 0x21071981);
+
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_8_Z ), 0x000000ef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_8_S ), 0xffffffef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_16_Z), 0x0000beef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_16_S), 0xffffbeef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_32_Z), 0xdeadbeef);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x10, OPERATION_MEMORY_LOAD_32_S), 0xdeadbeef);
+
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x12, OPERATION_MEMORY_LOAD_8_Z ), 0x000000ad);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x12, OPERATION_MEMORY_LOAD_8_S ), 0xffffffad);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x12, OPERATION_MEMORY_LOAD_16_Z), 0x0000dead);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x12, OPERATION_MEMORY_LOAD_16_S), 0xffffdead);
+
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x14, OPERATION_MEMORY_LOAD_8_Z ), 0x00000078);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x14, OPERATION_MEMORY_LOAD_8_S ), 0x00000078);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x18, OPERATION_MEMORY_LOAD_16_Z), 0x00001981);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x18, OPERATION_MEMORY_LOAD_16_S), 0x00001981);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x18, OPERATION_MEMORY_LOAD_32_Z), 0x21071981);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x18, OPERATION_MEMORY_LOAD_32_S), 0x21071981);
+
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x1a, OPERATION_MEMORY_LOAD_8_Z ), 0x00000007);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x1a, OPERATION_MEMORY_LOAD_8_S ), 0x00000007);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x1a, OPERATION_MEMORY_LOAD_16_Z), 0x00002107);
+  TEST(morpheo::behavioural::Tdcache_data_t, memory -> read_lsq (2, 0x1a, OPERATION_MEMORY_LOAD_16_S), 0x00002107);
+
+  delete memory;
+}
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/MemoryRequest.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/MemoryRequest.h	(revision 71)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/MemoryRequest.h	(revision 71)
@@ -0,0 +1,139 @@
+#ifndef MEMORYREQUEST_H
+#define MEMORYREQUEST_H
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
+//========================================================={MemoryRequest_t}
+class MemoryRequest_t
+{
+public : double                                   _cycle                ;
+public : morpheo::behavioural::Tcontext_t         _context_id           ;
+public : morpheo::behavioural::Tcontext_t         _front_end_id         ;
+public : morpheo::behavioural::Tcontext_t         _ooo_engine_id        ;
+public : morpheo::behavioural::Tpacket_t          _packet_id            ;
+public : morpheo::behavioural::Toperation_t       _operation            ;
+public : morpheo::behavioural::Ttype_t            _type                 ;
+public : morpheo::behavioural::Tlsq_ptr_t         _store_queue_ptr_write;
+public : morpheo::behavioural::Tlsq_ptr_t         _load_queue_ptr_write ;
+public : morpheo::behavioural::Tgeneral_data_t    _immediat             ;
+public : morpheo::behavioural::Tgeneral_data_t    _data_ra              ;
+public : morpheo::behavioural::Tgeneral_data_t    _data_rb              ;
+public : morpheo::behavioural::Tcontrol_t         _write_rd             ;
+public : morpheo::behavioural::Tgeneral_address_t _num_reg_rd           ;
+public : bool                                     _write_spec_ko        ;
+public : bool                                     _previous_load_speculative;
+public : morpheo::behavioural::Tgeneral_data_t    _data_wait            ;
+
+  MemoryRequest_t (void) 
+  {
+    _cycle                 = 0;
+    _context_id            = 0;
+    _front_end_id          = 0;
+    _ooo_engine_id         = 0;
+    _packet_id             = 0;
+    _operation             = 0;
+    _type                  = 0;
+    _store_queue_ptr_write = 0;
+    _load_queue_ptr_write  = 0;
+    _immediat              = 0;
+    _data_ra               = 0;
+    _data_rb               = 0;
+    _write_rd              = 0;
+    _num_reg_rd            = 0;
+    _write_spec_ko         = 0;
+    _previous_load_speculative = 0;
+    _data_wait             = 0;
+  };
+
+  MemoryRequest_t (double             cycle                ,
+		   morpheo::behavioural::Tcontext_t         context_id           ,
+		   morpheo::behavioural::Tcontext_t         front_end_id         ,
+		   morpheo::behavioural::Tcontext_t         ooo_engine_id        ,
+		   morpheo::behavioural::Tpacket_t          packet_id            ,
+		   morpheo::behavioural::Toperation_t       operation            ,
+		   morpheo::behavioural::Ttype_t            type                 ,
+		   morpheo::behavioural::Tlsq_ptr_t         store_queue_ptr_write,
+		   morpheo::behavioural::Tlsq_ptr_t         load_queue_ptr_write ,
+		   morpheo::behavioural::Tgeneral_data_t    immediat             ,
+		   morpheo::behavioural::Tgeneral_data_t    data_ra              ,
+		   morpheo::behavioural::Tgeneral_data_t    data_rb              ,
+		   morpheo::behavioural::Tcontrol_t         write_rd             ,
+		   morpheo::behavioural::Tgeneral_address_t num_reg_rd           ,
+		   bool                                     write_spec_ko        ,
+		   morpheo::behavioural::Tgeneral_data_t    data_wait=0)
+  {
+    _cycle                 = cycle                ;
+    _context_id            = context_id           ;
+    _front_end_id          = front_end_id         ;
+    _ooo_engine_id         = ooo_engine_id        ;
+    _packet_id             = packet_id            ;
+    _operation             = operation            ;
+    _type                  = type                 ;
+    _store_queue_ptr_write = store_queue_ptr_write;
+    _load_queue_ptr_write  = load_queue_ptr_write ;
+    _immediat              = immediat             ;
+    _data_ra               = data_ra              ;
+    _data_rb               = data_rb              ;
+    _write_rd              = write_rd             ;
+    _num_reg_rd            = num_reg_rd           ;
+    _write_spec_ko         = write_spec_ko        ;
+    _previous_load_speculative = 0;
+    _data_wait             = data_wait            ;
+  }
+
+  void modif (double             cycle                ,
+	      morpheo::behavioural::Tcontext_t         context_id           ,
+	      morpheo::behavioural::Tcontext_t         front_end_id         ,
+	      morpheo::behavioural::Tcontext_t         ooo_engine_id        ,
+	      morpheo::behavioural::Tpacket_t          packet_id            ,
+	      morpheo::behavioural::Toperation_t       operation            ,
+	      morpheo::behavioural::Ttype_t            type                 ,
+	      morpheo::behavioural::Tlsq_ptr_t         store_queue_ptr_write,
+	      morpheo::behavioural::Tlsq_ptr_t         load_queue_ptr_write ,
+	      morpheo::behavioural::Tgeneral_data_t    immediat             ,
+	      morpheo::behavioural::Tgeneral_data_t    data_ra              ,
+	      morpheo::behavioural::Tgeneral_data_t    data_rb              ,
+	      morpheo::behavioural::Tcontrol_t         write_rd             ,
+	      morpheo::behavioural::Tgeneral_address_t num_reg_rd           ,
+	      bool                                     write_spec_ko        ,
+	      morpheo::behavioural::Tgeneral_data_t    data_wait=0          )
+  {
+    _cycle                 = cycle                ;
+    _context_id            = context_id           ;
+    _front_end_id          = front_end_id         ;
+    _ooo_engine_id         = ooo_engine_id        ;
+    _packet_id             = packet_id            ;
+    _operation             = operation            ;
+    _type                  = type                 ;
+    _store_queue_ptr_write = store_queue_ptr_write;
+    _load_queue_ptr_write  = load_queue_ptr_write ;
+    _immediat              = immediat             ;
+    _data_ra               = data_ra              ;
+    _data_rb               = data_rb              ;
+    _write_rd              = write_rd             ;
+    _num_reg_rd            = num_reg_rd           ;
+    _write_spec_ko         = write_spec_ko        ;
+    _previous_load_speculative = 0;
+    _data_wait             = data_wait            ;
+  }
+
+  bool operator< (const MemoryRequest_t & right) const 
+  {
+    return _cycle > right._cycle; 
+  }
+
+  friend std::ostream& operator<<(std::ostream & os, const MemoryRequest_t & x)
+  {
+    return os << "<" << morpheo::toString(x._cycle) << "> : "
+	      << "{" << morpheo::toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
+	      << "\t * context / front_end / ooo_engine  : " << morpheo::toString(static_cast<uint32_t>(x._context_id   )) << " - " << morpheo::toString(static_cast<uint32_t>(x._front_end_id )) << " - " << morpheo::toString(static_cast<uint32_t>(x._ooo_engine_id)) << endl
+	      << "\t * operation  / type / write_spec_ko : " << morpheo::toString(static_cast<uint32_t>(x._operation)) << " " << morpheo::toString(static_cast<uint32_t>(x._type)) << " " << morpheo::toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
+	      << "\t * ptr_write store/load              : " << morpheo::toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << morpheo::toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
+	      << "\t * immediat / data_ra / data_rb      : " << morpheo::toString(static_cast<uint32_t>(x._immediat)) << " - " << morpheo::toString(static_cast<uint32_t>(x._data_ra)) << " - " << morpheo::toString(static_cast<uint32_t>(x._data_rb)) << endl
+	      << "\t * write_rd / num_reg_rd             : " << morpheo::toString(static_cast<uint32_t>(x._write_rd)) << " " << morpheo::toString(static_cast<uint32_t>(x._num_reg_rd)) << endl
+	      << "\t * data_wait                         : " << morpheo::toString(static_cast<uint32_t>(x._data_wait)) << endl;
+  }
+
+};
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h	(revision 62)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h	(revision 71)
@@ -7,4 +7,13 @@
  */
 
+
+#include "Common/include/Time.h"
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/MemoryRequest.h"
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h"
+
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Cache.h"
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+
 #ifdef SYSTEMC
 #include "systemc.h"
@@ -13,7 +22,4 @@
 #include <string>
 #include <iostream>
-#include <sys/time.h>
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
 
 using namespace std;
@@ -25,39 +31,8 @@
 using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit;
 using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit;
-
 using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit;
 
-void test    (string name,
+void test1   (string name,
 	      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param);
 
-class Time 
-{
-private : timeval time_begin;
-// private : timeval time_end;
-  
-public  : Time ()
-  {
-    gettimeofday(&time_begin     ,NULL);
-  };
-
-public  : ~Time ()
-  {
-    cout << *this;
-  };
-
-public  : friend ostream& operator<< (ostream& output_stream,
-				      const Time & x)
-  {
-    timeval time_end;
-    
-    gettimeofday(&time_end       ,NULL);
-    
-    uint32_t nb_cycles = static_cast<uint32_t>(sc_simulation_time());
-
-    double average = static_cast<double>(nb_cycles) / static_cast<double>(time_end.tv_sec-x.time_begin.tv_sec);
-    
-    output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl;
-
-    return output_stream;
-  }
-};
+void test2   (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 62)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 71)
@@ -8,5 +8,7 @@
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
 
-#define NB_PARAMS 11
+#define number_of_test 2
+
+#define NB_PARAMS 13
 
 void usage (int argc, char * argv[])
@@ -20,4 +22,6 @@
        << " - speculative_load        (uint32_t)" << endl
        << " - nb_context              (uint32_t)" << endl
+       << " - nb_front_end            (uint32_t)" << endl
+       << " - nb_ooo_engine           (uint32_t)" << endl
        << " - nb_packet               (uint32_t)" << endl
        << " - size_general_data       (uint32_t)" << endl
@@ -40,52 +44,94 @@
 #endif
 {
-  if (argc != 2+NB_PARAMS)
-    usage (argc, argv);
+  switch (number_of_test)
+    {
+    case 1 :
+      {
+	
+	if (argc != 2+NB_PARAMS)
+	  usage (argc, argv);
+	
+	uint32_t x=1;
+	
+	const string              name                     = argv[x++];
+	const uint32_t            _size_store_queue        = atoi(argv[x++]);
+	const uint32_t            _size_load_queue         = atoi(argv[x++]);
+	const uint32_t            _size_speculative_access_queue = atoi(argv[x++]);
+	const uint32_t            _nb_port_check           = atoi(argv[x++]);
+	const Tspeculative_load_t _speculative_load        = fromString<Tspeculative_load_t>(argv[x++]);
+	const uint32_t            _nb_context              = atoi(argv[x++]);
+	const uint32_t            _nb_front_end            = atoi(argv[x++]);
+	const uint32_t            _nb_ooo_engine           = atoi(argv[x++]);
+	const uint32_t            _nb_packet               = atoi(argv[x++]);
+	const uint32_t            _size_general_data       = atoi(argv[x++]);
+	const uint32_t            _nb_general_register     = atoi(argv[x++]);
+	const uint32_t            _nb_operation            = atoi(argv[x++]);
+	const uint32_t            _nb_type                 = atoi(argv[x++]);
+	
+	try 
+	  {
+	    morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
+	      (
+	       _size_store_queue       ,
+	       _size_load_queue        ,
+	       _size_speculative_access_queue,
+	       _nb_port_check          ,
+	       _speculative_load       ,
+	       _nb_context             ,
+	       _nb_front_end           ,
+	       _nb_ooo_engine          ,
+	       _nb_packet              ,
+	       _size_general_data      ,
+	       _nb_general_register    ,
+	       _nb_operation           ,
+	       _nb_type                
+	       );
+	    
+	    cout << param->print(1);
+	    
+	    test1 (name,param);
+	    
+	  }
+	catch (morpheo::ErrorMorpheo & error)
+	  {
+	    cout << "<" << name << "> : " <<  error.what ();
+	    exit (EXIT_FAILURE);
+	  }
+	catch (...)
+	  {
+	    cerr << "<" << name << "> : This test must generate a error" << endl;
+	    exit (EXIT_FAILURE);
+	  }
+	
+	break;
+      }
+    case 2 :
+      {
+	try 
+	  {
+	    test2 ();
+	  }
+	catch (morpheo::ErrorMorpheo & error)
+	  {
+	    cout << error.what ();
+	    exit (EXIT_FAILURE);
+	  }
+	catch (...)
+	  {
+	    cerr << "This test must generate a error" << endl;
+	    exit (EXIT_FAILURE);
+	  }
+	
+	break;
+      }
+    default :
+      {
+	std::cerr << "Invalid number of test" << std::endl;
+	exit (EXIT_FAILURE);
 
-  const string              name                     = argv[1];
-  const uint32_t            _size_store_queue        = atoi(argv[ 2]);
-  const uint32_t            _size_load_queue         = atoi(argv[ 3]);
-  const uint32_t            _size_speculative_access_queue = atoi(argv[ 4]);
-  const uint32_t            _nb_port_check           = atoi(argv[ 5]);
-  const Tspeculative_load_t _speculative_load        = fromString<Tspeculative_load_t>(argv[ 6]);
-  const uint32_t            _nb_context              = atoi(argv[ 7]);
-  const uint32_t            _nb_packet               = atoi(argv[ 8]);
-  const uint32_t            _size_general_data       = atoi(argv[ 9]);
-  const uint32_t            _nb_general_register     = atoi(argv[10]);
-  const uint32_t            _nb_operation            = atoi(argv[11]);
-  const uint32_t            _nb_type                 = atoi(argv[12]);
-
-  try 
-    {
-      morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
-	(
-	 _size_store_queue       ,
-	 _size_load_queue        ,
-	 _size_speculative_access_queue,
-	 _nb_port_check          ,
-	 _speculative_load       ,
-	 _nb_context             ,
-	 _nb_packet              ,
-	 _size_general_data      ,
-	 _nb_general_register    ,
-	 _nb_operation           ,
-	 _nb_type                
-        );
-      
-      cout << param->print(1);
-      
-      test (name,param);
+	break;
+      }
     }
-  catch (morpheo::ErrorMorpheo & error)
-    {
-      cout << "<" << name << "> : " <<  error.what ();
-      exit (EXIT_FAILURE);
-    }
-  catch (...)
-    {
-      cerr << "<" << name << "> : This test must generate a error" << endl;
-      exit (EXIT_FAILURE);
-    }
-
+  
   return (EXIT_SUCCESS);
 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp	(revision 62)
+++ 	(revision )
@@ -1,760 +1,0 @@
-/*
- * $Id$
- *
- * [ Description ]
- * 
- * Test
- */
-
-#include <queue>
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
-#include "Common/include/Test.h"
-#include "Common/include/BitManipulation.h"
-
-#define NB_ITERATION  1
-#define CYCLE_MAX     (128*NB_ITERATION)
-
-#define LABEL(str)                                                                       \
-{                                                                                        \
-  cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
-} while(0)
-
-static uint32_t cycle = 0;
-
-#define SC_START(cycle_offset)                                          \
-do                                                                      \
-{                                                                       \
-/*cout << "SC_START (begin)" << endl;*/                                 \
-                                                                        \
-  uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
-  if (cycle_current != cycle)                                           \
-    {                                                                   \
-      cycle = cycle_current;                                            \
-      cout << "##########[ cycle "<< cycle << " ]" << endl;             \
-    }                                                                   \
-                                                                        \
-  if (cycle_current > CYCLE_MAX)                                        \
-    {                                                                   \
-      TEST_KO("Maximal cycles Reached");                                \
-    }                                                                   \
-  sc_start(cycle_offset);                                               \
-/*cout << "SC_START (end  )" << endl;*/                                 \
-} while(0)
-
-
-
-//========================================================={MemoryRequest_t}
-class MemoryRequest_t
-{
-public : double             _cycle                ;
-public : Tcontext_t         _context_id           ;
-public : Tpacket_t          _packet_id            ;
-public : Toperation_t       _operation            ;
-public : Ttype_t            _type                 ;
-public : Tlsq_ptr_t         _store_queue_ptr_write;
-public : Tlsq_ptr_t         _load_queue_ptr_write ;
-public : Tgeneral_data_t    _immediat             ;
-public : Tgeneral_data_t    _data_ra              ;
-public : Tgeneral_data_t    _data_rb              ;
-public : Tcontrol_t         _write_rd             ;
-public : Tgeneral_address_t _num_reg_rd           ;
-public : bool               _write_spec_ko        ;
-
-  MemoryRequest_t (void) 
-  {
-    _cycle                 = 0;
-    _context_id            = 0;
-    _packet_id             = 0;
-    _operation             = 0;
-    _type                  = 0;
-    _store_queue_ptr_write = 0;
-    _load_queue_ptr_write  = 0;
-    _immediat              = 0;
-    _data_ra               = 0;
-    _data_rb               = 0;
-    _write_rd              = 0;
-    _num_reg_rd            = 0;
-    _write_spec_ko         = 0;
-  };
-
-  MemoryRequest_t (double             cycle                ,
-		   Tcontext_t         context_id           ,
-		   Tpacket_t          packet_id            ,
-		   Toperation_t       operation            ,
-		   Ttype_t            type                 ,
-		   Tlsq_ptr_t         store_queue_ptr_write,
-		   Tlsq_ptr_t         load_queue_ptr_write ,
-		   Tgeneral_data_t    immediat             ,
-		   Tgeneral_data_t    data_ra              ,
-		   Tgeneral_data_t    data_rb              ,
-		   Tcontrol_t         write_rd             ,
-		   Tgeneral_address_t num_reg_rd           ,
-		   bool               write_spec_ko        )
-  {
-    _cycle                 = cycle                ;
-    _context_id            = context_id           ;
-    _packet_id             = packet_id            ;
-    _operation             = operation            ;
-    _type                  = type                 ;
-    _store_queue_ptr_write = store_queue_ptr_write;
-    _load_queue_ptr_write  = load_queue_ptr_write ;
-    _immediat              = immediat             ;
-    _data_ra               = data_ra              ;
-    _data_rb               = data_rb              ;
-    _write_rd              = write_rd             ;
-    _num_reg_rd            = num_reg_rd           ;
-    _write_spec_ko         = write_spec_ko        ;
-  }
-
-  void modif (double             cycle                ,
-	      Tcontext_t         context_id           ,
-	      Tpacket_t          packet_id            ,
-	      Toperation_t       operation            ,
-	      Ttype_t            type                 ,
-	      Tlsq_ptr_t         store_queue_ptr_write,
-	      Tlsq_ptr_t         load_queue_ptr_write ,
-	      Tgeneral_data_t    immediat             ,
-	      Tgeneral_data_t    data_ra              ,
-	      Tgeneral_data_t    data_rb              ,
-	      Tcontrol_t         write_rd             ,
-	      Tgeneral_address_t num_reg_rd           ,
-	      bool               write_spec_ko        )
-  {
-    _cycle                 = cycle                ;
-    _context_id            = context_id           ;
-    _packet_id             = packet_id            ;
-    _operation             = operation            ;
-    _type                  = type                 ;
-    _store_queue_ptr_write = store_queue_ptr_write;
-    _load_queue_ptr_write  = load_queue_ptr_write ;
-    _immediat              = immediat             ;
-    _data_ra               = data_ra              ;
-    _data_rb               = data_rb              ;
-    _write_rd              = write_rd             ;
-    _num_reg_rd            = num_reg_rd           ;
-    _write_spec_ko         = write_spec_ko        ;
-  }
-
-  bool operator< (const MemoryRequest_t & right) const 
-  {
-    return _cycle > right._cycle; 
-  }
-
-  friend ostream& operator<<(ostream &, const MemoryRequest_t &);
-};
-
-ostream & operator << (ostream& os, const MemoryRequest_t & x) 
-{
-  return os << "<" << toString(x._cycle) << "> : "
-	    << "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
-	    << "\t * context_id                        : " << toString(static_cast<uint32_t>(x._context_id)) << endl
-	    << "\t * operation  / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
-	    << "\t * ptr_write store/load              : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
-	    << "\t * immediat / data_ra / data_rb      : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
-	    << "\t * write_rd / num_reg_rd             : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
-}
-
-//================================================================{Memory_t}
-class Memory_t
-{
-private : const uint32_t    _nb_context;
-private : const uint32_t    _nb_word   ;
-private : const uint32_t    _size_data ;
-private : const Tdcache_address_t _mask_addr ;
-private : Tdcache_data_t ** _data;
-  
-public  : Memory_t (uint32_t nb_context, 
-		    uint32_t nb_word, 
-		    uint32_t size_data):
-  _nb_context   (nb_context),
-  _nb_word      (nb_word   ),
-  _size_data    (size_data ),
-  _mask_addr    (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data))))))
-  {
-    _data = new Tdcache_data_t * [nb_context];
-    
-    for (uint32_t i=0; i<nb_context; i++)
-      {
-	_data [i] = new Tdcache_data_t [nb_word];
-	
-	for (uint32_t j=0; j<nb_word; j++)
-	  _data [i][j] = rand()%(size_data);
-      }
-  }
-
-public  : ~Memory_t (void)
-  {
-    delete [] _data;
-  }
-
-public  : Tdcache_data_t access (uint32_t          context, 
-				 Tdcache_address_t address,
-				 Tdcache_type_t    type,
-				 Tdcache_data_t    data)
-  {
-    return 0;
-  }
-
-public  : Tdcache_data_t read (uint32_t          context,
-			       Tdcache_address_t address,
-			       Tdcache_type_t    type)
-  {
-    // Address's Read must be aligned
-
-    if ((address & _mask_addr) != 0)
-      TEST_KO("<Memory_t::read> Address is not aligned");
-
-    if (context>_nb_context)
-      TEST_KO("<Memory_t::read> nb context is too high");
-
-    if (address>_nb_word)
-      TEST_KO("<Memory_t::read> address is too high");
-    
-    return _data [context][address];
-  }
-
-public  : void write (uint32_t          context, 
-		      Tdcache_address_t address,
-		      Tdcache_type_t    type,
-		      Tdcache_data_t    data)
-  {
-    if (context>_nb_context)
-      TEST_KO("<Memory_t::read> nb context is too high");
-
-    if (address>_nb_word)
-      TEST_KO("<Memory_t::read> address is too high");
-
-    Tdcache_address_t LSB = address &  _mask;
-    Tdcache_address_t MSB = address & ~_mask;
-  
-    Tdcache_data_t write_data = data;
-    Tdcache_data_t read_data  = _data [context][MSB];
-
-    // exemple to size_data = 32b
-    // LSB index_min
-    // 0   0
-    // 1   8
-    // 2   16
-    // 3   24
-    uint32_t index_min = LSB<<3;
-    uint32_t index_max = index_min;
-    // index max, dependant of access's size
-
-    switch (type)
-      {
-
-
-      }
-  }
-};
-
-//===================================================================={test}
-void test (string name,
-	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
-{
-  cout << "<" << name << "> : Simulation SystemC" << endl;
-
-#ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
-#endif
-
-  Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
-#ifdef STATISTICS
-					     _parameters_statistics,
-#endif
-					     _param);
-  
-#ifdef SYSTEMC
-  /*********************************************************************
-   * Déclarations des signaux
-   *********************************************************************/
-  string rename = "";
-
-  sc_clock                               * in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);
-  sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
-
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_VAL                   = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
-  sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
-  sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
-  sc_signal<Ttype_t           > *   in_MEMORY_IN_TYPE                  = new sc_signal<Ttype_t           > (rename.c_str());
-  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
-  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
-//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-//sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
-//sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
-//sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
-
-  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL        = new sc_signal<Tcontrol_t	 >(rename.c_str());
-  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK        = new sc_signal<Tcontrol_t	 >(rename.c_str());
-  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Toperation_t      > *  out_MEMORY_OUT_OPERATION  = new sc_signal<Toperation_t      >(rename.c_str());
-  sc_signal<Ttype_t           > *  out_MEMORY_OUT_TYPE       = new sc_signal<Ttype_t           >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD   = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
-  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD    = new sc_signal<Tgeneral_data_t   >(rename.c_str());
-//sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE   = new sc_signal<Tcontrol_t        >(rename.c_str());
-//sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
-//sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE    = new sc_signal<Tspecial_data_t   >(rename.c_str());
-  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION  = new sc_signal<Texception_t      >(rename.c_str());
-
-  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  in_DCACHE_REQ_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > * out_DCACHE_REQ_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
-  sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
-  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_UNCACHED   = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
-  
-  sc_signal<Tcontrol_t        > *  in_DCACHE_RSP_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontrol_t        > * out_DCACHE_RSP_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > *  in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > *  in_DCACHE_RSP_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Tdcache_data_t    > *  in_DCACHE_RSP_RDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
-  sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
-  
-  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL        = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
-  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_CONTEXT_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
-  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG    = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
-  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA       = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
-    
-    for (uint32_t i=0; i<_param->_size_load_queue; i++)
-      {
-	out_BYPASS_MEMORY_VAL        [i] = new sc_signal<Tcontrol_t        >;
-	out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t        >;
-	out_BYPASS_MEMORY_NUM_REG    [i] = new sc_signal<Tgeneral_address_t>;
-	out_BYPASS_MEMORY_DATA       [i] = new sc_signal<Tgeneral_data_t   >;
-      }
-  
-  /********************************************************
-   * Instanciation
-   ********************************************************/
-  
-  cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
-  
-  (*(_Load_store_unit->in_CLOCK))        (*(in_CLOCK));
-  (*(_Load_store_unit->in_NRESET))       (*(in_NRESET));
-
-  (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
-  (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
-  (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
-  (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
-  (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
-//(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
-  (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
-  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
-//(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
-  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
-//(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
-//(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
-  
-  (*(_Load_store_unit->out_MEMORY_OUT_VAL        ))(*(out_MEMORY_OUT_VAL        ));
-  (*(_Load_store_unit-> in_MEMORY_OUT_ACK        ))(*( in_MEMORY_OUT_ACK        ));
-  (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID ));
-  (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID  ))(*(out_MEMORY_OUT_PACKET_ID  ));
-  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD   ))(*(out_MEMORY_OUT_WRITE_RD   ));
-  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD ));
-  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD    ))(*(out_MEMORY_OUT_DATA_RD    ));
-//(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE   ))(*(out_MEMORY_OUT_WRITE_RE   ));
-//(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE ));
-//(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE    ))(*(out_MEMORY_OUT_DATA_RE    ));
-  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION  ))(*(out_MEMORY_OUT_EXCEPTION  ));
-
-  (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
-  (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
-  (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
-  (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
-  (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
-  (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
-  (*(_Load_store_unit->out_DCACHE_REQ_UNCACHED  ))(*(out_DCACHE_REQ_UNCACHED  ));
-  (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
-
-  (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
-  (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
-  (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_ERROR     ))(*( in_DCACHE_RSP_ERROR     ));
-
-  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
-    {
-      for (uint32_t i=0; i<_param->_size_load_queue; i++)
-	{
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL        [i]))(*(out_BYPASS_MEMORY_VAL        [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))(*(out_BYPASS_MEMORY_CONTEXT_ID [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG    [i]))(*(out_BYPASS_MEMORY_NUM_REG    [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA       [i]))(*(out_BYPASS_MEMORY_DATA       [i]));
-	}
-    }
-  cout << "<" << name << "> Start Simulation ............" << endl;
-  Time * _time = new Time();
-
-  /********************************************************
-   * Simulation - Begin
-   ********************************************************/
-
-  // Initialisation
-
-  const uint32_t seed = 0;
-//const uint32_t seed = static_cast<uint32_t>(time(NULL));
-
-  srand(seed);
-
-  const uint32_t     nb_request   = _param->_nb_packet;
-  const uint32_t     nb_word      = nb_request;
-
-//const int32_t      percent_transaction_memory_in  = 100;
-  const int32_t      percent_transaction_memory_out = 100;
-  const int32_t      percent_transaction_dcache     = 100;
-
-  const int32_t      percent_exception              =   5;
-  const int32_t      percent_type_load              =   0;
-  const int32_t      percent_type_store             = 100;
-  const int32_t      percent_miss_spec              =   0;
-
-  if ((percent_type_load  +
-       percent_type_store ) > 100)
-    TEST_KO("sum of percent_type > 100");
-
-  const int32_t      seuil_type_load    = percent_type_load;
-  const int32_t      seuil_type_store   = percent_type_store+percent_type_load;
-
-  uint32_t           nb_request_memory_in ;
-  uint32_t           nb_request_memory_out;
-  uint32_t           nb_request_dcache    ;
-
-  MemoryRequest_t                 tab_request  [nb_request];
-  priority_queue<MemoryRequest_t> fifo_request;
-
-  // emulation of cache
-  Tdcache_data_t     cache_data                [_param->_nb_context][nb_word];
-
-  SC_START(0);
-
-  LABEL("Initialisation");
-
-  // emulate a memory
-  for (uint32_t i=0; i<_param->_nb_context; i++)
-    for (uint32_t j=0; j<nb_word; j++)
-      cache_data [i][j] = rand()%(1<<_param->_size_general_data);
-
-  in_MEMORY_IN_VAL ->write(0);
-  in_MEMORY_OUT_ACK->write(0);
-  in_DCACHE_REQ_ACK->write(0);
-  in_DCACHE_RSP_VAL->write(0);
-
-  in_NRESET        ->write(0);
-  SC_START(5);
-  in_NRESET        ->write(5);
-
-  LABEL("Loop of Test");
-
-  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
-    {
-      LABEL("Iteration "+toString(iteration));
-
-      LABEL("Structure's initialisation");
-
-      nb_request_memory_in  = 0;
-      nb_request_memory_out = 0;
-      nb_request_dcache     = 0;
-      
-      // Fill the request_queue
-      
-      Tlsq_ptr_t         store_queue_ptr_write = 0;
-      Tlsq_ptr_t         load_queue_ptr_write  = 0;
-
-      bool               store_queue_use [_param->_size_store_queue];
-      bool               load_queue_use  [_param->_size_load_queue ];
-
-      for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	store_queue_use [i] = false;
-      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
-	load_queue_use  [i] = false;
-
-      double             current_cycle = sc_simulation_time();
-      double             cycle_min     = current_cycle;
-
-      LABEL("Fifo request initialisation");
-      // Init fifo_request
-      for (uint32_t i=0; i<nb_request; i++)
-	{
-	  double             cycle;
-	  Tcontext_t         context_id                = rand () % _param->_nb_context;
-	  Tpacket_t          packet_id                 = i;
-	  Tlsq_ptr_t         store_queue_ptr_write_old = store_queue_ptr_write;
-	  Tlsq_ptr_t         load_queue_ptr_write_old  = load_queue_ptr_write ;
-	  Toperation_t       operation;
-	  
-	  int32_t            percent = rand()%100;
-
-	  uint32_t           size_queue;
-	 
-	  if (percent <= seuil_type_load)
-	    {
-// 	      LABEL(" * LOAD");
-	      operation            = OPERATION_MEMORY_LOAD_16_S;
-	      size_queue           = _param->_size_load_queue;
-	      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
-	    }
-	  else
-	    {
-	      if (percent <= seuil_type_store)
-		{
-// 		  LABEL(" * STORE");
-		  operation             = OPERATION_MEMORY_STORE_16;
-		  size_queue            = _param->_size_store_queue;
-		  store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
-		}
-	      else
-		{
-// 		  LABEL(" * OTHERS");
-		  operation            = OPERATION_MEMORY_PREFETCH;
-		  size_queue           = _param->_size_load_queue;
-		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
-		}
-	    }
-
-	  cycle      = cycle_min;
-	  cycle_min ++;
-
-	  Ttype_t            type                  = TYPE_MEMORY;
-	  Tgeneral_data_t    address               = rand()%(nb_word);
-	  Tgeneral_data_t    offset                = rand()%(nb_word);
-
-	  percent = rand()%100;
-	  if (percent > percent_exception) 
-	    address = address & (not mask_memory_access(operation));
-
-	  if (offset > address) // max
-	    offset  = address;
-
-	  Tgeneral_data_t    immediat              = offset;
-	  Tgeneral_data_t    data_ra               = address - offset;
-	  Tgeneral_data_t    data_rb               = rand()%(1<<_param->_size_general_data);
-	  Tcontrol_t         write_rd              = 0;
-	  Tgeneral_address_t num_reg_rd            = 0;
-	  bool               write_spec_ko         = ((rand()%100)<percent_miss_spec);
-
-	  tab_request [i].modif(cycle                ,
-				context_id           ,
-				packet_id            ,
-				operation            ,
-				type                 ,
-				store_queue_ptr_write_old,
-				load_queue_ptr_write_old ,
-				immediat             ,
-				data_ra              ,
-				data_rb              ,
-				write_rd             ,
-				num_reg_rd           ,
-				write_spec_ko
-				);
-
-	  cout << tab_request [i] << endl;
-	
-	  fifo_request.push(tab_request [i]);
-
-	  double cycle_head = 0;
-
-	  if (is_operation_memory_store(operation))
-	    {
-	      cycle_head = cycle_min;
-	      cycle_min ++;
-
-	      cout << "         * Write head : " << toString(cycle_head) 
-		   << endl
-		   << endl;
-	      
-	      fifo_request.push(MemoryRequest_t(cycle_head,
-						context_id,
-						packet_id,
-						(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
-						type,
-						store_queue_ptr_write_old,
-						0,
-						0,
-						0,
-						0,
-						0,
-						0,
-						write_spec_ko));
-	    }
-  	}
-        
-      LABEL("Simulation of this iteration ...");
-    
-      while (nb_request_memory_out < nb_request)
-	{
-	  // ***** MEMORY_IN *****
-
-	  // memory_in_val depends of three factors :
-	  //  1) request's fifo is not empty ?
-	  //  2) the slot destination is free ?
-	  //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
-
-	  bool can_execute = false;
-
-	  if (is_operation_memory_store(fifo_request.top()._operation))
-	    can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);
-	  else
-	    can_execute = not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
-	  
-	  in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 
-				   can_execute                and 
-				   (sc_simulation_time() >= fifo_request.top()._cycle));
-
-	  in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
-	  in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
-	  in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
-	  in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
-	  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
-   	  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
-	  in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
-	  in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
-	  in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
-	  in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
-	  in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
-
-	  in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
-
-	  // ***** DCACHE_REQ *****
-	  in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
-
-	  SC_START(0);
-  
-	  SC_START(1);
-
-	  LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
-	  LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
-	  LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
-	  LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
-	  LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
-	  LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
-	  LABEL("  * can_execute                            : "+toString(can_execute));
-
-	  if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
-	    {
-	      LABEL(" * Accepted MEMORY_IN  : " + toString(nb_request_memory_in));
-	      cout << fifo_request.top();
-
-	      if (is_operation_memory_store(fifo_request.top()._operation))
-		{
-		  if (not is_operation_memory_store_head(fifo_request.top()._operation))
-		    store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
-		}
-	      else
-		load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
-
-	      fifo_request.pop();
-	      
-	      nb_request_memory_in ++;
-	    }
-
-	  LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
-	  if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
-	    {
-	      LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));
-
-	      if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
-		store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;
-	      else
-		load_queue_use  [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;
-
-	      nb_request_memory_out ++;
-	    }
-
-	  LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
-	  if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
-	    {
-	      LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));
-
-	      // test type : send or not a respons !
-	    }
-
-	}
-    }
-  
-  /********************************************************
-   * Simulation - End
-   ********************************************************/
-
-  TEST_OK ("End of Simulation");
-  delete _time;
-  cout << "<" << name << "> ............ Stop Simulation" << endl;
-
-  delete     in_CLOCK;
-  delete     in_NRESET;
-
-  delete     in_MEMORY_IN_VAL                  ;
-  delete    out_MEMORY_IN_ACK                  ;
-  delete     in_MEMORY_IN_CONTEXT_ID           ;
-  delete     in_MEMORY_IN_PACKET_ID            ;
-  delete     in_MEMORY_IN_OPERATION            ;
-  delete     in_MEMORY_IN_TYPE                 ;
-  delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
-  delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-//delete     in_MEMORY_IN_HAS_IMMEDIAT         ;
-  delete     in_MEMORY_IN_IMMEDIAT             ;
-  delete     in_MEMORY_IN_DATA_RA              ;
-  delete     in_MEMORY_IN_DATA_RB              ;
-//delete     in_MEMORY_IN_DATA_RC              ;
-  delete     in_MEMORY_IN_WRITE_RD             ;
-  delete     in_MEMORY_IN_NUM_REG_RD           ;
-//delete     in_MEMORY_IN_WRITE_RE             ;
-//delete     in_MEMORY_IN_NUM_REG_RE           ;
-
-  delete    out_MEMORY_OUT_VAL       ;
-  delete     in_MEMORY_OUT_ACK       ;
-  delete    out_MEMORY_OUT_CONTEXT_ID;
-  delete    out_MEMORY_OUT_PACKET_ID ;
-  delete    out_MEMORY_OUT_OPERATION ;
-  delete    out_MEMORY_OUT_TYPE      ;
-  delete    out_MEMORY_OUT_WRITE_RD  ;
-  delete    out_MEMORY_OUT_NUM_REG_RD;
-  delete    out_MEMORY_OUT_DATA_RD   ;
-//delete    out_MEMORY_OUT_WRITE_RE  ;
-//delete    out_MEMORY_OUT_NUM_REG_RE;
-//delete    out_MEMORY_OUT_DATA_RE   ;
-  delete    out_MEMORY_OUT_EXCEPTION ;
-
-  delete    out_DCACHE_REQ_VAL       ;
-  delete     in_DCACHE_REQ_ACK       ;
-  delete    out_DCACHE_REQ_CONTEXT_ID;
-  delete    out_DCACHE_REQ_PACKET_ID ;
-  delete    out_DCACHE_REQ_ADDRESS   ;
-  delete    out_DCACHE_REQ_TYPE      ;
-  delete    out_DCACHE_REQ_UNCACHED  ;
-  delete    out_DCACHE_REQ_WDATA     ;
-
-  delete     in_DCACHE_RSP_VAL       ;
-  delete    out_DCACHE_RSP_ACK       ;
-  delete     in_DCACHE_RSP_CONTEXT_ID;
-  delete     in_DCACHE_RSP_PACKET_ID ;
-  delete     in_DCACHE_RSP_RDATA     ;
-  delete     in_DCACHE_RSP_ERROR     ;
-
-  delete [] out_BYPASS_MEMORY_VAL       ;
-  delete [] out_BYPASS_MEMORY_CONTEXT_ID;
-  delete [] out_BYPASS_MEMORY_NUM_REG   ;
-  delete [] out_BYPASS_MEMORY_DATA      ;
-
-#endif
-
-  delete _Load_store_unit;
-#ifdef STATISTICS
-  delete _parameters_statistics;
-#endif
-}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp	(revision 71)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test1.cpp	(revision 71)
@@ -0,0 +1,738 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include <queue>
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
+
+#define NB_ITERATION  1
+#define CYCLE_MAX     (1024*NB_ITERATION)
+
+#define LABEL(str)							\
+  {									\
+    cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
+  } while(0)
+
+#define SC_START(cycle_offset)						\
+  do									\
+    {									\
+      /*cout << "SC_START (begin)" << endl;*/				\
+									\
+      uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
+      if (cycle_offset != 0)						\
+	{								\
+	  cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
+	}								\
+									\
+      if (cycle_current > CYCLE_MAX)					\
+	{								\
+	  TEST_KO("Maximal cycles Reached");				\
+	}								\
+      sc_start(cycle_offset);						\
+      /*cout << "SC_START (end  )" << endl;*/				\
+    } while(0)
+
+
+//===================================================================={test}
+void test1 (string name,
+	   morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
+{
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+#ifdef STATISTICS
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
+#endif
+
+  Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
+#ifdef STATISTICS
+							    _parameters_statistics,
+#endif
+							    _param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  string rename = "";
+
+  sc_clock                               * in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_VAL                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_FRONT_END_ID          = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_OOO_ENGINE_ID         = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
+  sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
+  sc_signal<Ttype_t           > *   in_MEMORY_IN_TYPE                  = new sc_signal<Ttype_t           > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  //sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
+//   sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  //sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
+
+  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID    = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_FRONT_END_ID  = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID     = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD    = new sc_signal<Tgeneral_address_t>(rename.c_str());
+  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD       = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+  //sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  //sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE    = new sc_signal<Tspecial_address_t>(rename.c_str());
+  //sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE       = new sc_signal<Tspecial_data_t   >(rename.c_str());
+  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION     = new sc_signal<Texception_t      >(rename.c_str());
+
+  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  in_DCACHE_REQ_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > * out_DCACHE_REQ_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
+  sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
+  sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > *  in_DCACHE_RSP_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > * out_DCACHE_RSP_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  in_DCACHE_RSP_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_data_t    > *  in_DCACHE_RSP_RDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL           = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
+  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
+  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG       = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
+  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA          = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
+    
+  for (uint32_t i=0; i<_param->_size_load_queue; i++)
+    {
+      out_BYPASS_MEMORY_VAL           [i] = new sc_signal<Tcontrol_t        >(rename.c_str());
+      out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t        >(rename.c_str());
+      out_BYPASS_MEMORY_NUM_REG       [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
+      out_BYPASS_MEMORY_DATA          [i] = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+    }
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
+  
+  (*(_Load_store_unit->in_CLOCK))        (*(in_CLOCK));
+  (*(_Load_store_unit->in_NRESET))       (*(in_NRESET));
+
+  (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
+  (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID         ))(*( in_MEMORY_IN_FRONT_END_ID         ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID        ))(*( in_MEMORY_IN_OOO_ENGINE_ID        ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
+  (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
+  (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
+//   (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
+  
+  (*(_Load_store_unit->out_MEMORY_OUT_VAL           ))(*(out_MEMORY_OUT_VAL           ));
+  (*(_Load_store_unit-> in_MEMORY_OUT_ACK           ))(*( in_MEMORY_OUT_ACK           ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID    ))(*(out_MEMORY_OUT_CONTEXT_ID    ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID  ))(*(out_MEMORY_OUT_FRONT_END_ID  ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID     ))(*(out_MEMORY_OUT_PACKET_ID     ));
+  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD      ))(*(out_MEMORY_OUT_WRITE_RD      ));
+  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD    ))(*(out_MEMORY_OUT_NUM_REG_RD    ));
+  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD       ))(*(out_MEMORY_OUT_DATA_RD       ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE      ))(*(out_MEMORY_OUT_WRITE_RE      ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE    ))(*(out_MEMORY_OUT_NUM_REG_RE    ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE       ))(*(out_MEMORY_OUT_DATA_RE       ));
+  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION     ))(*(out_MEMORY_OUT_EXCEPTION     ));
+
+  (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
+  (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
+  (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
+  (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
+  (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
+  (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
+
+  (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
+  (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
+  (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_ERROR     ))(*( in_DCACHE_RSP_ERROR     ));
+
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	{
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL           [i]))(*(out_BYPASS_MEMORY_VAL           [i]));
+	  if (_param->_have_port_ooo_engine_id)    
+	    (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG       [i]))(*(out_BYPASS_MEMORY_NUM_REG       [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA          [i]))(*(out_BYPASS_MEMORY_DATA          [i]));
+	}
+    }
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  Time * _time = new Time();
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  // Initialisation
+
+  const uint32_t seed = 0;
+  //const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  const uint32_t     nb_request   = _param->_nb_packet;
+  const uint32_t     nb_word      = nb_request;
+
+  //const int32_t      percent_transaction_memory_in  = 100;
+  const int32_t      percent_transaction_memory_out =  75;
+  const int32_t      percent_transaction_dcache     =  75;
+
+  const int32_t      percent_exception              =   0;
+  const int32_t      percent_type_load              =   0;
+  const int32_t      percent_type_store             =  50;
+  const int32_t      percent_miss_spec              =  20;
+  
+  const uint32_t     miss_rate                      =  10;
+  const uint32_t     miss_penality                  =   5;
+
+  if ((percent_type_load  +
+       percent_type_store ) > 100)
+    TEST_KO("sum of percent_type > 100");
+
+  const int32_t      seuil_type_load    = percent_type_load;
+  const int32_t      seuil_type_store   = percent_type_store+percent_type_load;
+
+  uint32_t           nb_request_memory_in ;
+  uint32_t           nb_request_memory_out;
+  uint32_t           nb_request_dcache    ;
+
+  MemoryRequest_t                 tab_request  [nb_request];
+  priority_queue<MemoryRequest_t> fifo_request;
+
+  // emulation of memory
+  Memory_t                      * _memory = new Memory_t (1<<_param->_size_dcache_context_id, nb_word, _param->_size_general_data);
+  Cache_t                       * _cache  = new Cache_t  (miss_rate, miss_penality);
+
+
+  SC_START(0);
+
+  LABEL("Initialisation");
+
+  in_MEMORY_IN_VAL ->write(0);
+  in_MEMORY_OUT_ACK->write(0);
+  in_DCACHE_REQ_ACK->write(0);
+  in_DCACHE_RSP_VAL->write(0);
+
+  in_NRESET        ->write(0);
+  SC_START(5);
+  in_NRESET        ->write(5);
+
+  LABEL("Loop of Test");
+
+  try 
+    {
+      for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+	{
+	  LABEL("Iteration "+toString(iteration));
+
+	  LABEL("Structure's initialisation");
+
+	  nb_request_memory_in  = 0;
+	  nb_request_memory_out = 0;
+	  nb_request_dcache     = 0;
+      
+	  // Fill the request_queue
+      
+	  Tlsq_ptr_t         store_queue_ptr_write = 0;
+	  Tlsq_ptr_t         load_queue_ptr_write  = 0;
+
+	  bool               store_queue_use [_param->_size_store_queue];
+	  uint32_t           nb_store_slot_use = 0;
+	  bool               load_queue_use  [_param->_size_load_queue ];
+
+	  for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	    store_queue_use [i] = false;
+	  for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+	    load_queue_use  [i] = false;
+
+	  double             current_cycle = sc_simulation_time();
+	  double             cycle_min     = current_cycle;
+
+	  Toperation_t       operation_store [4] = {OPERATION_MEMORY_STORE_8,
+						    OPERATION_MEMORY_STORE_16,
+						    OPERATION_MEMORY_STORE_32,
+						    OPERATION_MEMORY_STORE_64};
+
+	  Toperation_t       operation_load  [8] = {OPERATION_MEMORY_LOAD_8_Z,
+						    OPERATION_MEMORY_LOAD_8_S,
+						    OPERATION_MEMORY_LOAD_16_Z,
+						    OPERATION_MEMORY_LOAD_16_S,
+						    OPERATION_MEMORY_LOAD_32_Z,
+						    OPERATION_MEMORY_LOAD_32_S,
+						    OPERATION_MEMORY_LOAD_64_Z,
+						    OPERATION_MEMORY_LOAD_64_S};
+
+	  Toperation_t       operation_other [5] = {OPERATION_MEMORY_LOCK           ,
+						    OPERATION_MEMORY_INVALIDATE     ,
+						    OPERATION_MEMORY_PREFETCH       ,
+						    OPERATION_MEMORY_FLUSH          ,
+						    OPERATION_MEMORY_SYNCHRONIZATION};
+
+
+	  const uint32_t nb_operation_store =   (log2(_param->_size_general_data/8)+1);
+	  const uint32_t nb_operation_load  = 2*(log2(_param->_size_general_data/8)+1);
+	  const uint32_t nb_operation_other = 5;
+
+	  LABEL("Fifo request initialisation");
+	  // Init fifo_request
+	  for (uint32_t i=0; i<nb_request; i++)
+	    {
+	      double       cycle;
+	      Tcontext_t   context_id                = 0;
+	      Tcontext_t   front_end_id              = 0;
+	      Tcontext_t   ooo_engine_id             = rand () % _param->_nb_ooo_engine;
+	      Tpacket_t    packet_id                 = i;
+	      Tlsq_ptr_t   store_queue_ptr_write_old = store_queue_ptr_write;
+	      Tlsq_ptr_t   load_queue_ptr_write_old  = load_queue_ptr_write ;
+	      Toperation_t operation;
+	  
+	      int32_t      percent = rand()%100;
+
+	      uint32_t     size_queue;
+	 
+	      if (percent < seuil_type_load)
+		{
+		  LABEL(" * LOAD");
+		  operation            = operation_load[(rand()%nb_operation_load)];
+		  size_queue           = _param->_size_load_queue;
+		  load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		}
+	      else
+		{
+		  if (percent < seuil_type_store)
+		    {
+		      LABEL(" * STORE");
+		  
+		  
+		      operation             = operation_store[(rand()%nb_operation_store)];
+		      size_queue            = _param->_size_store_queue;
+		      store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
+		    }
+		  else
+		    {
+		      LABEL(" * OTHERS");
+		      operation            = operation_other[(rand()%nb_operation_other)];
+		      // 		  operation            = operation_other[4];
+		      size_queue           = _param->_size_load_queue;
+		      load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
+		    }
+		}
+
+	      cycle = cycle_min;
+	      cycle_min ++;
+
+	      Ttype_t            type    = TYPE_MEMORY;
+	      Tgeneral_data_t    address = rand()%(nb_word);
+	      Tgeneral_data_t    offset  = rand()%(nb_word);
+
+	      // LABEL ("Address step 1 : "+toString(address)+" - "+toString(offset));
+
+	      percent = rand()%100;
+	      if (percent > percent_exception) 
+		address = address & (~ mask_memory_access(operation));
+	  
+	      // LABEL ("Address step 2 : "+toString(address)+" - mask : "+toString((~ mask_memory_access(operation))));
+
+	      if (offset > address) // max
+		offset  = address;
+
+	      Tgeneral_data_t    immediat      = offset;
+	      Tgeneral_data_t    data_ra       = address - offset;
+
+	      // LABEL ("Address step 3 : "+toString(address)+", "+toString(data_ra)+" - "+toString(immediat));
+	  
+	      Tgeneral_data_t    data_rb       = static_cast<Tgeneral_data_t>(rand());
+	      Tcontrol_t         write_rd      = 0;
+	      Tgeneral_address_t num_reg_rd    = 0;
+	      bool               write_spec_ko = is_operation_memory_store(operation) and ((rand()%100)<percent_miss_spec);
+
+	      tab_request [i].modif(cycle                    ,
+				    context_id               ,
+				    front_end_id             ,
+				    ooo_engine_id            ,
+				    packet_id                ,
+				    operation                ,
+				    type                     ,
+				    store_queue_ptr_write_old,
+				    load_queue_ptr_write_old ,
+				    immediat                 ,
+				    data_ra                  ,
+				    data_rb                  ,
+				    write_rd                 ,
+				    num_reg_rd               ,
+				    write_spec_ko);
+
+	      cout << tab_request [i] << endl;
+	
+	      fifo_request.push(tab_request [i]);
+
+	      double cycle_head = 0;
+
+	      if (is_operation_memory_store(operation))
+		{
+		  cycle_head = cycle_min;
+		  cycle_min ++;
+
+		  cout << "         * Write head : " << toString(cycle_head) 
+		       << endl
+		       << endl;
+	      
+		  fifo_request.push(MemoryRequest_t(cycle_head,
+						    context_id,
+						    front_end_id,
+						    ooo_engine_id,
+						    packet_id,
+						    (write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
+						    type,
+						    store_queue_ptr_write_old,
+						    0,
+						    0,
+						    0,
+						    0,
+						    0,
+						    0,
+						    write_spec_ko));
+		}
+	    }
+        
+	  LABEL("Simulation of this iteration ...");
+    
+	  while (nb_request_memory_out < nb_request)
+	    {
+	      cout << "*********************************************" << endl;
+	      cout << "Dump STORE_QUEUE_USE : " << endl;
+	      cout << " use " << nb_store_slot_use << endl;
+	      for (uint32_t i=0; i<_param->_size_store_queue; i++)
+		cout << "  [" << i << "] " << store_queue_use [i] << endl;
+	      cout << "Dump LOAD_QUEUE_USE : " << endl;
+	      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+		cout << "  [" << i << "] " << load_queue_use [i] << endl;
+	      cout << "*********************************************" << endl;
+
+
+	      // ***** MEMORY_IN *****
+
+	      // memory_in_val depends of three factors :
+	      //  1) request's fifo is not empty ?
+	      //  2) the slot destination is free ?
+	      //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
+
+	      bool can_execute = false;
+
+	      if (is_operation_memory_store(fifo_request.top()._operation))
+		can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
+	      else
+		can_execute = not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
+	  
+	      in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and 
+				       can_execute                and 
+				       (sc_simulation_time() >= fifo_request.top()._cycle));
+
+	      if (_param->_have_port_context_id)
+		in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
+	      if (_param->_have_port_front_end_id)
+		in_MEMORY_IN_FRONT_END_ID         ->write (fifo_request.top()._front_end_id         );
+	      if (_param->_have_port_ooo_engine_id)
+		in_MEMORY_IN_OOO_ENGINE_ID        ->write (fifo_request.top()._ooo_engine_id        );
+	      if (_param->_have_port_packet_id)
+		in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
+	      in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
+	      in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
+	      in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
+	      in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
+	      in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
+	      in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
+	      in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
+// 	      in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
+	      in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
+
+	      in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
+
+	      // ***** DCACHE_REQ *****
+	      in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+
+	      // ***** DCACHE_RSP *****
+	      bool have_rsp = _cache->have_rsp ();
+	      in_DCACHE_RSP_VAL->write(have_rsp);
+
+	      if (have_rsp)
+		{
+		  in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
+		  in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
+		  in_DCACHE_RSP_RDATA     ->write(_cache->front()._rdata     );
+		  in_DCACHE_RSP_ERROR     ->write(_cache->front()._error     );
+		}
+
+	      SC_START(0);
+
+	      LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	      LABEL("  * fifo_request.empty                     : "+toString(fifo_request.empty()));
+	      LABEL("  * fifo_request.top.cycle                 : "+toString(fifo_request.top()._cycle));
+	      LABEL("  * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
+	      LABEL("  * fifo_request.top.load_queue_ptr_write  : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
+	      LABEL("  * fifo_request.top.operation             : "+toString(static_cast<uint32_t>(fifo_request.top()._operation           )));
+	      LABEL("  * can_execute                            : "+toString(can_execute));
+
+	      if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
+		{
+		  LABEL(" * Accepted MEMORY_IN  : " + toString(nb_request_memory_in));
+		  cout << fifo_request.top();
+
+		  if (is_operation_memory_store(fifo_request.top()._operation))
+		    {
+		      if (not is_operation_memory_store_head(fifo_request.top()._operation))
+			{
+			  store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
+			  nb_store_slot_use ++;
+			}
+		    }
+		  else
+		    load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
+
+		  fifo_request.pop();
+	      
+		  nb_request_memory_in ++;
+		}
+
+	      LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
+	      if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
+		{
+		  Tpacket_t  packet_id = out_MEMORY_OUT_PACKET_ID->read();
+
+		  LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
+
+		  if (is_operation_memory_store(tab_request[packet_id]._operation))
+		    {
+		      store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
+		      nb_store_slot_use --;
+		    }
+		  else
+		    load_queue_use  [tab_request[packet_id]._load_queue_ptr_write] = false;
+
+		  nb_request_memory_out ++;
+
+		  // a lot of test
+		  TEST(Tcontext_t        , out_MEMORY_OUT_CONTEXT_ID   ->read(), tab_request[packet_id]._context_id   );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
+		  TEST(Tpacket_t         , out_MEMORY_OUT_PACKET_ID    ->read(), tab_request[packet_id]._packet_id    );
+		  TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), tab_request[packet_id]._write_rd     );
+		  TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD   ->read(), tab_request[packet_id]._num_reg_rd   );
+
+		  Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
+		  if (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))))
+		    TEST(Texception_t      , out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_ALIGNMENT);
+		  else
+		    {
+		      if (tab_request[packet_id]._write_spec_ko)
+			TEST(Texception_t, out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_MISS_SPECULATION);
+		      else
+			{
+			  TEST(Texception_t, out_MEMORY_OUT_EXCEPTION    ->read(), EXCEPTION_MEMORY_NONE);
+
+			  if (is_operation_memory_load(tab_request[packet_id]._operation))
+			    {
+			      Tgeneral_data_t read_lsq = _memory->read_lsq (((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+									     (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) |
+									     (tab_request[packet_id]._context_id)),
+									    (tab_request[packet_id]._immediat +
+									     tab_request[packet_id]._data_ra), 
+									    tab_request[packet_id]._operation);
+			      cout << "MEMORY_OUT is a LOAD" << endl
+				   << "  * operation       : " << tab_request[packet_id]._operation << endl
+				   << std::hex
+				   << "  * address         : " << (tab_request[packet_id]._immediat +
+								   tab_request[packet_id]._data_ra) << endl
+				   << "  * read_lsq        : " << read_lsq << endl
+				   << "  * memory_out_data : " << out_MEMORY_OUT_DATA_RD->read() << endl
+				   << std::dec;
+			  
+// 			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), read_lsq);
+			    }
+			}
+		    }
+		}
+
+	      LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
+	      if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+		{
+		  Tcontext_t   context_id;
+		  Tpacket_t    packet_id ; 
+		  if (_param->_have_port_dcache_context_id)
+		    context_id = out_DCACHE_REQ_CONTEXT_ID->read();
+		  else
+		    context_id = 0;
+
+		  packet_id  = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
+	      
+		  LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
+
+// 		  TEST(Tcontext_t       ,out_DCACHE_REQ_CONTEXT_ID->read(),((tab_request[packet_id]._ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
+// 									    (tab_request[packet_id]._front_end_id <<(_param->_size_context_id)) |
+// 									    (tab_request[packet_id]._context_id)));
+// 		  TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS   ->read(),(tab_request[packet_id]._immediat +
+// 									    tab_request[packet_id]._data_ra) );
+// 		  TEST(Tdcache_type_t   ,out_DCACHE_REQ_TYPE      ->read(), operation_to_dcache_type(operation));
+		  
+// 		  if (is_operation_memory_store(operation))
+// 		    TEST(Tdcache_data_t   ,out_DCACHE_REQ_WDATA     ->read(),tab_request[packet_id]._data_rb);
+
+		  Tdcache_data_t rdata = _memory->access (context_id, out_DCACHE_REQ_ADDRESS->read(), out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
+
+		  // test type : send or not a respons !
+		  LABEL("   * rdata : " + toString(rdata));
+
+		  if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or
+		      (out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD))
+		    {
+		      LABEL("     * have_dcache_rsp");
+		  
+		      _cache->push (context_id,
+				    out_DCACHE_REQ_PACKET_ID ->read(),
+				    rdata     ,
+				    0);
+		    }
+		}
+
+	      LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
+	      if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
+		{
+		  _cache->pop();
+		}
+
+	      _cache->end_cycle();
+
+	      SC_START(1);
+	    }
+	}
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      _memory->trace();
+      throw (error);
+    }
+
+  _memory->trace();
+
+  
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  TEST_OK ("End of Simulation");
+  delete _time;
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+  delete     in_CLOCK;
+  delete     in_NRESET;
+
+  delete     in_MEMORY_IN_VAL         ;
+  delete    out_MEMORY_IN_ACK         ;
+  delete     in_MEMORY_IN_CONTEXT_ID  ;
+  delete     in_MEMORY_IN_FRONT_END_ID  ;
+  delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
+  delete     in_MEMORY_IN_PACKET_ID   ;
+  delete     in_MEMORY_IN_OPERATION   ;
+  delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+  delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
+  //delete     in_MEMORY_IN_HAS_IMMEDIAT;
+  delete     in_MEMORY_IN_IMMEDIAT    ;
+  delete     in_MEMORY_IN_DATA_RA     ;
+  delete     in_MEMORY_IN_DATA_RB     ;
+  //delete     in_MEMORY_IN_DATA_RC     ;
+//   delete     in_MEMORY_IN_WRITE_RD    ;
+  delete     in_MEMORY_IN_NUM_REG_RD  ;
+  //delete     in_MEMORY_IN_WRITE_RE    ;
+  //delete     in_MEMORY_IN_NUM_REG_RE  ;
+    
+  delete    out_MEMORY_OUT_VAL       ;
+  delete     in_MEMORY_OUT_ACK       ;
+  delete    out_MEMORY_OUT_CONTEXT_ID;
+  delete    out_MEMORY_OUT_FRONT_END_ID;
+  delete    out_MEMORY_OUT_OOO_ENGINE_ID;
+  delete    out_MEMORY_OUT_PACKET_ID ;
+  delete    out_MEMORY_OUT_WRITE_RD  ;
+  delete    out_MEMORY_OUT_NUM_REG_RD;
+  delete    out_MEMORY_OUT_DATA_RD   ;
+  //delete    out_MEMORY_OUT_WRITE_RE  ;
+  //delete    out_MEMORY_OUT_NUM_REG_RE;
+  //delete    out_MEMORY_OUT_DATA_RE   ;
+  delete    out_MEMORY_OUT_EXCEPTION ;
+  
+  delete    out_DCACHE_REQ_VAL       ;
+  delete     in_DCACHE_REQ_ACK       ;
+  delete    out_DCACHE_REQ_CONTEXT_ID;
+  delete    out_DCACHE_REQ_PACKET_ID ;
+  delete    out_DCACHE_REQ_ADDRESS   ;
+  delete    out_DCACHE_REQ_TYPE      ;
+  delete    out_DCACHE_REQ_WDATA     ;
+  
+  delete     in_DCACHE_RSP_VAL       ;
+  delete    out_DCACHE_RSP_ACK       ;
+  delete     in_DCACHE_RSP_CONTEXT_ID;
+  delete     in_DCACHE_RSP_PACKET_ID ;
+  delete     in_DCACHE_RSP_RDATA     ;
+  delete     in_DCACHE_RSP_ERROR     ;
+  
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      delete [] out_BYPASS_MEMORY_VAL       ;
+      delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
+      delete [] out_BYPASS_MEMORY_NUM_REG   ;
+      delete [] out_BYPASS_MEMORY_DATA      ;
+    }
+#endif
+
+  delete _Load_store_unit;
+  delete _memory;
+  delete _cache;
+#ifdef STATISTICS
+  delete _parameters_statistics;
+#endif
+}
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 71)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 71)
@@ -0,0 +1,780 @@
+/*
+ * $Id$
+ *
+ * [ Description ]
+ * 
+ * Test
+ */
+
+#include <queue>
+#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
+
+#define CYCLE_MAX     1024
+
+#define LABEL(str)							\
+  {									\
+    cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
+  } while(0)
+
+#define SC_START(cycle_offset)						\
+  do									\
+    {									\
+      /*cout << "SC_START (begin)" << endl;*/				\
+									\
+      uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
+      if (cycle_offset != 0)						\
+	{								\
+	  cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
+	}								\
+									\
+      if (cycle_current > CYCLE_MAX)					\
+	{								\
+	  TEST_KO("Maximal cycles Reached");				\
+	}								\
+      sc_start(cycle_offset);						\
+      /*cout << "SC_START (end  )" << endl;*/				\
+    } while(0)
+
+
+//===================================================================={test}
+void test2 (void)
+{
+  std::string name = "Test_Load_store_queue_manual";
+
+  cout << "<" << name << "> : Simulation SystemC" << endl;
+
+
+  morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
+	(
+	 4,  //_size_store_queue       
+	 4,  //_size_load_queue        
+	 2,  //_size_speculative_access_queue
+	 2,  //_nb_port_check          
+	 SPECULATIVE_LOAD_COMMIT,  //_speculative_load       
+	 1,  //_nb_context             
+	 1,  //_nb_front_end           
+	 2,  //_nb_ooo_engine          
+	 128,//_nb_packet              
+	 32, //_size_general_data      
+	 64, //_nb_general_register    
+	 4,  //_nb_operation           
+	 4   //_nb_type                
+        );
+
+#ifdef STATISTICS
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
+#endif
+
+  Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
+#ifdef STATISTICS
+							    _parameters_statistics,
+#endif
+							    _param);
+  
+#ifdef SYSTEMC
+  /*********************************************************************
+   * Déclarations des signaux
+   *********************************************************************/
+  string rename = "";
+
+  sc_clock                               * in_CLOCK  = new sc_clock ("clock", 1.0, 0.5);
+  sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
+
+  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_VAL                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_FRONT_END_ID          = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tcontext_t        > *   in_MEMORY_IN_OOO_ENGINE_ID         = new sc_signal<Tcontext_t        > (rename.c_str());
+  sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
+  sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
+  sc_signal<Ttype_t           > *   in_MEMORY_IN_TYPE                  = new sc_signal<Ttype_t           > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
+  //sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
+//   sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
+  //sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
+  //sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
+
+  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK           = new sc_signal<Tcontrol_t	  >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID    = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_FRONT_END_ID  = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID     = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD    = new sc_signal<Tgeneral_address_t>(rename.c_str());
+  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD       = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+  //sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE      = new sc_signal<Tcontrol_t        >(rename.c_str());
+  //sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE    = new sc_signal<Tspecial_address_t>(rename.c_str());
+  //sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE       = new sc_signal<Tspecial_data_t   >(rename.c_str());
+  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION     = new sc_signal<Texception_t      >(rename.c_str());
+
+  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > *  in_DCACHE_REQ_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > * out_DCACHE_REQ_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
+  sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
+  sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > *  in_DCACHE_RSP_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontrol_t        > * out_DCACHE_RSP_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
+  sc_signal<Tcontext_t        > *  in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
+  sc_signal<Tpacket_t         > *  in_DCACHE_RSP_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
+  sc_signal<Tdcache_data_t    > *  in_DCACHE_RSP_RDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
+  sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
+  
+  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL           = new sc_signal<Tcontrol_t        > * [_param->_size_load_queue];
+  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t        > * [_param->_size_load_queue];
+  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG       = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
+  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA          = new sc_signal<Tgeneral_data_t   > * [_param->_size_load_queue];
+    
+  for (uint32_t i=0; i<_param->_size_load_queue; i++)
+    {
+      out_BYPASS_MEMORY_VAL           [i] = new sc_signal<Tcontrol_t        >(rename.c_str());
+      out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t        >(rename.c_str());
+      out_BYPASS_MEMORY_NUM_REG       [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
+      out_BYPASS_MEMORY_DATA          [i] = new sc_signal<Tgeneral_data_t   >(rename.c_str());
+    }
+  
+  /********************************************************
+   * Instanciation
+   ********************************************************/
+  
+  cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
+  
+  (*(_Load_store_unit->in_CLOCK))        (*(in_CLOCK));
+  (*(_Load_store_unit->in_NRESET))       (*(in_NRESET));
+
+  (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
+  (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID         ))(*( in_MEMORY_IN_FRONT_END_ID         ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID        ))(*( in_MEMORY_IN_OOO_ENGINE_ID        ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
+  (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
+  (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
+  (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
+  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
+//   (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
+  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
+  //(*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
+  
+  (*(_Load_store_unit->out_MEMORY_OUT_VAL           ))(*(out_MEMORY_OUT_VAL           ));
+  (*(_Load_store_unit-> in_MEMORY_OUT_ACK           ))(*( in_MEMORY_OUT_ACK           ));
+  if (_param->_have_port_context_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID    ))(*(out_MEMORY_OUT_CONTEXT_ID    ));
+  if (_param->_have_port_front_end_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID  ))(*(out_MEMORY_OUT_FRONT_END_ID  ));
+  if (_param->_have_port_ooo_engine_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID ));
+  if (_param->_have_port_packet_id)
+    (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID     ))(*(out_MEMORY_OUT_PACKET_ID     ));
+  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD      ))(*(out_MEMORY_OUT_WRITE_RD      ));
+  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD    ))(*(out_MEMORY_OUT_NUM_REG_RD    ));
+  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD       ))(*(out_MEMORY_OUT_DATA_RD       ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE      ))(*(out_MEMORY_OUT_WRITE_RE      ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE    ))(*(out_MEMORY_OUT_NUM_REG_RE    ));
+  //(*(_Load_store_unit->out_MEMORY_OUT_DATA_RE       ))(*(out_MEMORY_OUT_DATA_RE       ));
+  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION     ))(*(out_MEMORY_OUT_EXCEPTION     ));
+
+  (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
+  (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
+  (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
+  (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
+  (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
+  (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
+
+  (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
+  (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
+  if (_param->_have_port_dcache_context_id)
+    (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
+  (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
+  (*(_Load_store_unit-> in_DCACHE_RSP_ERROR     ))(*( in_DCACHE_RSP_ERROR     ));
+
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	{
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL           [i]))(*(out_BYPASS_MEMORY_VAL           [i]));
+	  if (_param->_have_port_ooo_engine_id)    
+	    (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG       [i]))(*(out_BYPASS_MEMORY_NUM_REG       [i]));
+	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA          [i]))(*(out_BYPASS_MEMORY_DATA          [i]));
+	}
+    }
+  cout << "<" << name << "> Start Simulation ............" << endl;
+  Time * _time = new Time();
+
+  /********************************************************
+   * Simulation - Begin
+   ********************************************************/
+
+  // Initialisation
+
+  const uint32_t seed = 0;
+  //const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  const int32_t      percent_transaction_memory_out = 100;
+  const int32_t      percent_transaction_dcache     = 100;
+  const uint32_t     miss_rate                      =   0;
+  const uint32_t     miss_penality                  =   0;
+
+  uint32_t           nb_request_memory_out=0;
+
+  MemoryRequest_t                 tab_request  [_param->_nb_packet];
+  priority_queue<MemoryRequest_t> fifo_request;
+
+  const uint32_t     size_memory = 0x100;
+  // emulation of memory
+  Memory_t                      * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
+  Cache_t                       * _cache  = new Cache_t  (miss_rate, miss_penality);
+
+  SC_START(0);
+
+  LABEL("Initialisation");
+
+  in_MEMORY_IN_VAL ->write(0);
+  in_MEMORY_OUT_ACK->write(0);
+  in_DCACHE_REQ_ACK->write(0);
+  in_DCACHE_RSP_VAL->write(0);
+
+  in_NRESET        ->write(0);
+  SC_START(5);
+  in_NRESET        ->write(5);
+
+  LABEL("Loop of Test");
+
+  try 
+    {
+	  LABEL("Structure's initialisation");
+
+	  bool               store_queue_use [_param->_size_store_queue];
+	  uint32_t           nb_store_slot_use = 0;
+	  bool               load_queue_use  [_param->_size_load_queue ];
+
+	  for (uint32_t i=0; i<_param->_size_store_queue; i++)
+	    store_queue_use [i] = false;
+	  for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+	    load_queue_use  [i] = false;
+
+	  
+	  //--------------------------------------------------------------------------------------------------------------
+	  //                    c  c f o p  o                              t           s l i     d     d          w n w 
+	  //                    y  o r o a  p                              y           t o m     a     a          r u r 
+	  //                    c  n o o c  e                              p           o a m     t     t          i m i 
+	  //                    l  t n _ k  r                              e           r d e     a     a          t _ t 
+	  //                    e  e t e e  a                                          e _ d     _     _          e r e  
+	  //                       x _ n t  t                                          _ p i     r     r          _ _ _
+	  //                       t e g _  i                                          p t a     a     b          r g s
+	  //                       _ n i i  o                                          t r t                      d _ p 
+	  //                       i d n d  n                                          r _                          r e 
+	  //                       d _ e                                               _ w                          d c 
+	  //                         i _                                               w r                            _ 
+	  //                         d i                                               r i                            k 
+	  //                           d                                               i t                            o 
+	  //                                                                           t e                              
+	  //                                                                           e                               
+	  //                                                                                                        
+	  tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,0,0,0x0  ,0x10 ,0xdead1234,0,0,0);
+
+	  tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0  ,0x0  ,0x0       ,0,0,0);
+
+	  // READ 32b 
+	  tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,1,0,0x10 ,0x0  ,0x0       ,1,1,0,0xdead1234);
+	  tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S    ,TYPE_MEMORY,1,1,0x10 ,0x0  ,0x0       ,1,2,0,0xdead1234);
+
+	  // READ 16b 
+	  tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z    ,TYPE_MEMORY,1,2,0x10 ,0x0  ,0x0       ,1,3,0,0x00001234);
+	  tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z    ,TYPE_MEMORY,1,3,0x12 ,0x0  ,0x0       ,1,4,0,0x0000dead);
+	  tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S    ,TYPE_MEMORY,1,0,0x10 ,0x0  ,0x0       ,1,5,0,0x00001234);
+	  tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S    ,TYPE_MEMORY,1,1,0x12 ,0x0  ,0x0       ,1,6,0,0xffffdead);
+
+	  // READ  8b 
+	  tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z     ,TYPE_MEMORY,1,0,0x10 ,0x0  ,0x0       ,1,7,0,0x00000034);
+	  tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z     ,TYPE_MEMORY,1,1,0x11 ,0x0  ,0x0       ,1,8,0,0x00000012);
+	  tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z     ,TYPE_MEMORY,1,2,0x12 ,0x0  ,0x0       ,1,9,0,0x000000ad);
+	  tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z     ,TYPE_MEMORY,1,3,0x13 ,0x0  ,0x0       ,1,1,0,0x000000de);
+	  tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,1,0,0x10 ,0x0  ,0x0       ,1,2,0,0x00000034);
+	  tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,1,1,0x11 ,0x0  ,0x0       ,1,3,0,0x00000012);
+	  tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,1,2,0x12 ,0x0  ,0x0       ,1,4,0,0xffffffad);
+	  tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,1,3,0x13 ,0x0  ,0x0       ,1,5,0,0xffffffde);
+
+	  // STORE 16b
+	  tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16     ,TYPE_MEMORY,1,0,0x20 ,0x0  ,0xffffabcd,0,0,0);
+	  tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16     ,TYPE_MEMORY,2,0,0x22 ,0x0  ,0xffffdcba,0,0,0);
+	  tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,3,0,0x20 ,0x0  ,0x0       ,1,0,0,0xdcbaabcd);
+
+	  // STORE  8b and head / valid out order
+	  tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8      ,TYPE_MEMORY,3,0,0x1  ,0x4  ,0xffffff56,0,0,0);
+	  tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8      ,TYPE_MEMORY,0,0,0x0  ,0x4  ,0xffffff78,0,0,0);
+	  tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8      ,TYPE_MEMORY,1,0,0x3  ,0x4  ,0xffffff12,0,0,0);
+	  tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8      ,TYPE_MEMORY,2,0,0x2  ,0x4  ,0xffffff34,0,0,0);
+	  tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,3,1,0x2  ,0x2  ,0x0       ,1,0,0,0x12345678);
+
+	  // CHECK - with a store not present, store format is >=
+	  tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,3,0,0x0  ,0x30 ,0x21071981,0,0,0);
+	  tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,2,0x0  ,0x30 ,0x0       ,1,0,0,0x21071981);
+	  tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z    ,TYPE_MEMORY,0,3,0x0  ,0x30 ,0x0       ,1,0,0,0x00001981);
+	  tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z    ,TYPE_MEMORY,0,0,0x0  ,0x32 ,0x0       ,1,0,0,0x00002107);
+	  tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,0,1,0x0  ,0x31 ,0x0       ,1,0,0,0x00000019);
+
+	  // CHECK - with a store not present, multiple store and format is different
+	  tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,0,0,0x0  ,0x40 ,0xffffffff,0,0,0);
+	  tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16     ,TYPE_MEMORY,1,0,0x0  ,0x42 ,0xbaba    ,0,0,0);
+	  tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8      ,TYPE_MEMORY,2,0,0x0  ,0x42 ,0xbe      ,0,0,0);
+	  tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16     ,TYPE_MEMORY,3,0,0x0  ,0x40 ,0xf00d    ,0,0,0);
+	  tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,2,0x0  ,0x40 ,0x0       ,1,0,0,0xbabef00d);
+	  tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,2,3,0x0  ,0x40 ,0x0       ,1,0,0,0xbabaffff);
+	  tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,3,0,0x0  ,0x40 ,0x0       ,1,0,0,0xbabeffff);
+	  tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S     ,TYPE_MEMORY,3,1,0x0  ,0x42 ,0x0       ,1,0,0,0xffffffbe);
+
+
+	  // CHECK - with different ooo_engine_id
+	  tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,0,0,0x0  ,0x0  ,0xdad1900d,0,0,0);
+	  tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,1,0,0x0  ,0x0  ,0x55508570,0,0,0);
+	  tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0  ,0x0  ,0x0       ,0,0,0);
+
+
+	  tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S    ,TYPE_MEMORY,2,2,0x0  ,0x2  ,0x0       ,1,0,0,0xffffdad1);
+	  tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S    ,TYPE_MEMORY,2,3,0x0  ,0x0  ,0x0       ,1,0,0,0xffff8570);
+
+
+	  // with a little exception
+	  tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16     ,TYPE_MEMORY,2,0,0x0  ,0x0  ,0xffff6996,0,0,1);
+	  tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0  ,0x0  ,0x0       ,0,0,0);
+	  tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z     ,TYPE_MEMORY,3,0,0x0  ,0x1  ,0x0       ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
+	  tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,3,1,0x0  ,0x0  ,0x0       ,1,0,0,0x55508570); // the memory have not change
+
+
+	  // multiple event
+	  //   * store : miss_spec and aligment, priority : miss_spec > aligment
+	  //   * load  : miss_spec and aligment, priority : miss_spec > aligment
+	  tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,3,0,0x0  ,0x1  ,0x0       ,0,0,1);
+	  tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0  ,0x0  ,0x0       ,0,0,0);
+
+	  tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,2,0x0  ,0x0  ,0x0       ,1,0,0,0xdad1900d);
+	  tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,3,0x0  ,0x3  ,0x0       ,1,0,0); // miss_spec and alignment
+	  tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,0,0x0  ,size_memory  ,0x0       ,1,0,0); // bus error and alignement
+	  tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,0,1,0x0  ,size_memory+1,0x0       ,1,0,0); // bus error and alignement
+
+
+	  
+	  tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32     ,TYPE_MEMORY,0,0,0x0  ,size_memory  ,0x0       ,0,0,0); // bus error
+	  tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0  ,0x0          ,0x0       ,0,0,0);
+	  tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z    ,TYPE_MEMORY,1,0,0x0  ,0x0          ,0x0       ,1,0,0,0x55508570); // just to wait the dcache_rsp
+
+	  const uint32_t nb_request = 64;//_param->_nb_packet;
+        
+	  for (uint32_t i=0; i<nb_request; i++)
+	    {
+	      std::cout << tab_request [i] << std::endl;
+	      fifo_request.push(tab_request [i]);
+	    }
+	  LABEL("Simulation ...");
+    
+	  while (nb_request_memory_out < nb_request)
+	    {
+	      cout << "*********************************************" << endl;
+	      cout << "Dump STORE_QUEUE_USE : " << endl;
+	      cout << " use " << nb_store_slot_use << endl;
+	      for (uint32_t i=0; i<_param->_size_store_queue; i++)
+		cout << "  [" << i << "] " << store_queue_use [i] << endl;
+	      cout << "Dump LOAD_QUEUE_USE : " << endl;
+	      for (uint32_t i=0; i<_param->_size_load_queue ; i++)
+		cout << "  [" << i << "] " << load_queue_use [i] << endl;
+	      cout << "*********************************************" << endl;
+
+
+	      // ***** MEMORY_IN *****
+
+	      // memory_in_val depends of three factors :
+	      //  1) request's fifo is not empty ?
+	      //  2) the slot destination is free ?
+	      //  3) The head of request's fifo can be issue : the number of cycle is more than current cycle
+
+	      bool can_execute = false;
+
+	      if (not fifo_request.empty())
+		{
+		  can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
+		  if (is_operation_memory_store(fifo_request.top()._operation))
+		    can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
+		  else
+		    can_execute &= not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
+		}
+	      in_MEMORY_IN_VAL ->write(can_execute);
+	
+	      if (not fifo_request.empty())
+		{
+		  if (_param->_have_port_context_id)
+		    in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
+		  if (_param->_have_port_front_end_id)
+		    in_MEMORY_IN_FRONT_END_ID         ->write (fifo_request.top()._front_end_id         );
+		  if (_param->_have_port_ooo_engine_id)
+		    in_MEMORY_IN_OOO_ENGINE_ID        ->write (fifo_request.top()._ooo_engine_id        );
+		  if (_param->_have_port_packet_id)
+		    in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
+		  in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
+		  in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
+		  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
+		  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
+		  in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
+		  in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
+		  in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
+// 		  in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
+		  in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
+		}
+	      in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
+
+	      // ***** DCACHE_REQ *****
+	      in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+
+	      // ***** DCACHE_RSP *****
+	      bool have_rsp = _cache->have_rsp ();
+	      in_DCACHE_RSP_VAL->write(have_rsp);
+
+	      if (have_rsp)
+		{
+		  in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
+		  in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
+		  in_DCACHE_RSP_RDATA     ->write(_cache->front()._rdata     );
+		  in_DCACHE_RSP_ERROR     ->write(_cache->front()._error     );
+		}
+
+	      SC_START(0);
+
+	      LABEL("MEMORY_IN  : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
+	      if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
+		{
+		  Tpacket_t  packet_id = in_MEMORY_IN_PACKET_ID->read();
+
+		  LABEL(" * Accepted MEMORY_IN  : " + toString(packet_id));
+		  cout << fifo_request.top();
+
+		  if (is_operation_memory_store(fifo_request.top()._operation))
+		    {
+		      if (not is_operation_memory_store_head(fifo_request.top()._operation))
+			{
+			  store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
+			  nb_store_slot_use ++;
+			}
+		    }
+		  else
+		    load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
+
+		  fifo_request.pop();
+		}
+
+	      LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
+	      if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
+		{
+		  Tpacket_t  packet_id = out_MEMORY_OUT_PACKET_ID->read();
+
+		  LABEL(" * Accepted MEMORY_OUT : " + toString(packet_id));
+
+		  if (is_operation_memory_store(tab_request[packet_id]._operation))
+		    {
+		      store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
+		      nb_store_slot_use --;
+		      nb_request_memory_out +=2;
+
+		    }
+		  else
+		    {
+		      if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
+			{
+			  nb_request_memory_out ++;
+
+			  load_queue_use  [tab_request[packet_id]._load_queue_ptr_write] = false;
+			}
+		      else
+			{
+			  std::cout << "seth - have a load_speculative." << std::endl;
+			  tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
+			  tab_request[packet_id]._previous_load_speculative = 1;
+			}
+		    }
+		  
+		  std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
+
+		  // a lot of test
+		  TEST(Tpacket_t         , out_MEMORY_OUT_PACKET_ID    ->read(), tab_request[packet_id]._packet_id    );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_CONTEXT_ID   ->read(), tab_request[packet_id]._context_id   );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
+
+		  if (is_operation_memory_load (tab_request[packet_id]._operation))
+		    {
+		      TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD   ->read(), tab_request[packet_id]._num_reg_rd   );
+		    }
+
+		  Tgeneral_data_t address         = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
+
+		  bool            error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
+		  bool            berr            = (address >= size_memory);
+		  Texception_t    exception       = out_MEMORY_OUT_EXCEPTION->read();
+
+		  if (is_operation_memory_store(tab_request[packet_id]._operation))
+		    {
+		      TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), 0);
+
+		      // store.
+		      // prioritary : miss_speculation > aligmnent > DBERR
+		      
+			  bool test_result_ko = false;
+			  
+			  if (tab_request[packet_id]._write_spec_ko)
+			    {
+			      TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
+			    }
+			  else
+			    if (error_alignment)
+			      {
+				TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
+				test_result_ko = true;
+			      }
+			    else
+			      if (berr)
+				{
+				  // TODO NOT SUPPORTED
+// 				  TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
+
+				  //test_result_ko = true;
+				}
+			      else
+				{
+				  TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
+				}
+			  // In all case : test data
+			  if (test_result_ko)
+			    {
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), address);
+			    }
+		    }
+		  else
+		    {
+		      // load
+		      // prioritary : miss_speculation > aligmnent > DBERR
+		      
+		      bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
+
+		      if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
+			{
+			  bool test_result_ko = false;
+			  
+			  if (tab_request[packet_id]._write_spec_ko)
+			    {
+			      // IS A LOAD :D
+			      TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
+			      TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
+			    }
+			  else
+			    if (error_alignment)
+			      {
+				TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
+				TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
+				test_result_ko = true;
+			      }
+			    else
+			      if (berr)
+				{
+				  TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
+				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD->read(), is_load);
+				  test_result_ko = true;
+				}
+			      else
+				{
+				  TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
+				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
+				}
+			  // In all case : test data
+			  if (test_result_ko)
+			    {
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), address);
+			    }
+			  else
+			    {
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
+			    }
+			}
+		      else
+			{
+			  TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), 1);
+			}
+		    }
+		}
+
+	      LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
+	      if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+		{
+		  Tcontext_t        context_id;
+		  Tpacket_t         packet_id ; 
+		  Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
+		  Tdcache_data_t    rdata;
+		  Tdcache_error_t   error = 0;
+		  if (_param->_have_port_dcache_context_id)
+		    context_id = out_DCACHE_REQ_CONTEXT_ID->read();
+		  else
+		    context_id = 0;
+
+		  packet_id  = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
+	      
+		  LABEL(" * Accepted DCACHE_REQ : " + toString(packet_id));
+
+		  if (address >= size_memory)
+		    {
+		      // Bus error
+		      error = 1;
+		      rdata = address; // convention : cache return the address fautive !
+		    }
+		  else
+		    {
+		      rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
+		      LABEL("   * rdata : " + toString(rdata));
+		    }
+
+		  // test type : send or not a respons !
+		  if ((out_DCACHE_REQ_TYPE->read() == DCACHE_SYNCHRONIZATION) or
+		      (out_DCACHE_REQ_TYPE->read() == DCACHE_LOAD) or
+		      ((error == 1) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_8 ) or
+					 (out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_16) or
+					 (out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_32) or
+					 (out_DCACHE_REQ_TYPE->read() == DCACHE_STORE_64) )))
+		    {
+		      LABEL("     * have_dcache_rsp");
+		  
+		      _cache->push (context_id,
+				    out_DCACHE_REQ_PACKET_ID ->read(),
+				    rdata,
+				    error);
+		    }
+		}
+
+	      LABEL("DCACHE_RSP : "+toString(in_DCACHE_RSP_VAL->read())+" - "+toString(out_DCACHE_RSP_ACK ->read()));
+	      if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
+		{
+		  _cache->pop();
+		}
+
+	      _cache->end_cycle();
+
+	      SC_START(1);
+	    }
+    }
+  catch (morpheo::ErrorMorpheo & error)
+    {
+      _memory->trace();
+      throw (error);
+    }
+
+  _memory->trace();
+
+  
+  /********************************************************
+   * Simulation - End
+   ********************************************************/
+
+  TEST_OK ("End of Simulation");
+  delete _time;
+  cout << "<" << name << "> ............ Stop Simulation" << endl;
+
+  delete     in_CLOCK;
+  delete     in_NRESET;
+
+  delete     in_MEMORY_IN_VAL         ;
+  delete    out_MEMORY_IN_ACK         ;
+  delete     in_MEMORY_IN_CONTEXT_ID  ;
+  delete     in_MEMORY_IN_FRONT_END_ID  ;
+  delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
+  delete     in_MEMORY_IN_PACKET_ID   ;
+  delete     in_MEMORY_IN_OPERATION   ;
+  delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+  delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
+  //delete     in_MEMORY_IN_HAS_IMMEDIAT;
+  delete     in_MEMORY_IN_IMMEDIAT    ;
+  delete     in_MEMORY_IN_DATA_RA     ;
+  delete     in_MEMORY_IN_DATA_RB     ;
+  //delete     in_MEMORY_IN_DATA_RC     ;
+//   delete     in_MEMORY_IN_WRITE_RD    ;
+  delete     in_MEMORY_IN_NUM_REG_RD  ;
+  //delete     in_MEMORY_IN_WRITE_RE    ;
+  //delete     in_MEMORY_IN_NUM_REG_RE  ;
+    
+  delete    out_MEMORY_OUT_VAL       ;
+  delete     in_MEMORY_OUT_ACK       ;
+  delete    out_MEMORY_OUT_CONTEXT_ID;
+  delete    out_MEMORY_OUT_FRONT_END_ID;
+  delete    out_MEMORY_OUT_OOO_ENGINE_ID;
+  delete    out_MEMORY_OUT_PACKET_ID ;
+  delete    out_MEMORY_OUT_WRITE_RD  ;
+  delete    out_MEMORY_OUT_NUM_REG_RD;
+  delete    out_MEMORY_OUT_DATA_RD   ;
+  //delete    out_MEMORY_OUT_WRITE_RE  ;
+  //delete    out_MEMORY_OUT_NUM_REG_RE;
+  //delete    out_MEMORY_OUT_DATA_RE   ;
+  delete    out_MEMORY_OUT_EXCEPTION ;
+  
+  delete    out_DCACHE_REQ_VAL       ;
+  delete     in_DCACHE_REQ_ACK       ;
+  delete    out_DCACHE_REQ_CONTEXT_ID;
+  delete    out_DCACHE_REQ_PACKET_ID ;
+  delete    out_DCACHE_REQ_ADDRESS   ;
+  delete    out_DCACHE_REQ_TYPE      ;
+  delete    out_DCACHE_REQ_WDATA     ;
+  
+  delete     in_DCACHE_RSP_VAL       ;
+  delete    out_DCACHE_RSP_ACK       ;
+  delete     in_DCACHE_RSP_CONTEXT_ID;
+  delete     in_DCACHE_RSP_PACKET_ID ;
+  delete     in_DCACHE_RSP_RDATA     ;
+  delete     in_DCACHE_RSP_ERROR     ;
+  
+  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+    {
+      delete [] out_BYPASS_MEMORY_VAL       ;
+      delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
+      delete [] out_BYPASS_MEMORY_NUM_REG   ;
+      delete [] out_BYPASS_MEMORY_DATA      ;
+    }
+#endif
+
+  delete _Load_store_unit;
+  delete _memory;
+  delete _cache;
+#ifdef STATISTICS
+  delete _parameters_statistics;
+#endif
+  delete _param;
+}
