Changeset 71 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include
- Timestamp:
- Jan 19, 2008, 12:09:01 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include
- Files:
-
- 1 deleted
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r62 r71 24 24 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h" 25 25 #ifdef STATISTICS 26 #include "Behavioural/ Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Statistics.h"26 #include "Behavioural/include/Stat.h" 27 27 #endif 28 28 #include "Behavioural/include/Component.h" … … 54 54 55 55 protected : const Parameters * _param; 56 //#ifdef STATISTICS 57 // protected : const morpheo::behavioural::Parameters_Statistics * _param_statistics; 58 //#endif 59 60 #ifdef STATISTICS 61 private : Statistics * _stat; 56 57 #ifdef STATISTICS 58 private : Stat * _stat; 59 60 private : counter_t * _stat_use_store_queue; 61 private : counter_t * _stat_use_load_queue; 62 private : counter_t * _stat_use_speculative_access_queue; 63 64 private : counter_t * _stat_average_use_store_queue; 65 private : counter_t * _stat_average_use_load_queue; 66 private : counter_t * _stat_average_use_speculative_access_queue; 67 68 private : counter_t * _stat_percent_use_store_queue; 69 private : counter_t * _stat_percent_use_load_queue; 70 private : counter_t * _stat_percent_use_speculative_access_queue; 71 72 // private : counter_t * _stat_nb_load_miss_speculation; 73 // private : counter_t * _stat_nb_head_ko; 74 75 // private : counter_t * _stat_nb_inst_load; 76 // private : counter_t * _stat_nb_inst_store; 77 // private : counter_t * _stat_nb_inst_lock; 78 // private : counter_t * _stat_nb_inst_prefetch; 79 // private : counter_t * _stat_nb_inst_invalid; 80 // private : counter_t * _stat_nb_inst_flush; 81 // private : counter_t * _stat_nb_inst_sync; 62 82 #endif 63 83 … … 75 95 public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ; 76 96 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_CONTEXT_ID ; 97 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_FRONT_END_ID; 98 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_OOO_ENGINE_ID; 77 99 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; 78 100 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; … … 84 106 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ; // data (store) 85 107 //public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ; 86 108 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load) 87 109 public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ; // destination (load) 88 110 //public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ; … … 93 115 public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ; 94 116 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID; 117 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_FRONT_END_ID; 118 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID; 95 119 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; 96 120 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) … … 109 133 public : SC_OUT(Tdcache_address_t ) * out_DCACHE_REQ_ADDRESS ; 110 134 public : SC_OUT(Tdcache_type_t ) * out_DCACHE_REQ_TYPE ; 111 public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_UNCACHED ;112 135 public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ; 113 136 … … 122 145 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 123 146 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; 124 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_ CONTEXT_ID;147 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; 125 148 public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; 126 149 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; … … 144 167 145 168 // Registers 146 public : Tlsq_ptr_t internal_MEMORY_STORE_QUEUE_PTR_READ; 147 public : Tlsq_ptr_t internal_MEMORY_LOAD_QUEUE_PTR_READ ; 169 public : Tlsq_ptr_t reg_STORE_QUEUE_PTR_READ; 170 //public : Tlsq_ptr_t reg_LOAD_QUEUE_PTR_READ ; 171 public : Tlsq_ptr_t reg_LOAD_QUEUE_CHECK_PRIORITY ; 148 172 149 173 // signal 174 public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ; 175 150 176 private : Tcontrol_t internal_MEMORY_IN_ACK; 151 177 private : Tcontrol_t internal_MEMORY_OUT_VAL; 152 178 private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; 153 179 public : Tlsq_ptr_t internal_MEMORY_OUT_PTR; 180 181 private : Tcontrol_t internal_DCACHE_RSP_ACK; 154 182 private : Tcontrol_t internal_DCACHE_REQ_VAL; 155 183 private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; … … 190 218 public : void function_speculative_load_commit_genMealy_retire (void); 191 219 #endif 192 #ifdef STATISTICS 193 public : string statistics (uint32_t depth); 220 221 #ifdef STATISTICS 222 public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); 223 public : string statistics_print (uint32_t depth); 194 224 #endif 195 225 … … 200 230 #endif 201 231 202 #if def VHDL_TESTBENCH203 private : void vhdl_testbench_transition(void);232 #if defined(STATISTICS) or defined(VHDL_TESTBENCH) 233 private : void end_cycle (void); 204 234 #endif 205 235 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
r62 r71 12 12 #include "Common/include/Debug.h" 13 13 #include "Behavioural/include/Parameters.h" 14 #include "Common/include/BitManipulation.h" 14 15 #include <math.h> 15 16 … … 33 34 //public : const uint32_t _nb_cache_port ; 34 35 public : const uint32_t _nb_context ; 36 public : const uint32_t _nb_front_end ; 37 public : const uint32_t _nb_ooo_engine ; 35 38 public : const uint32_t _nb_packet ; 36 39 public : const uint32_t _size_general_data ; … … 43 46 public : const uint32_t _size_address_speculative_access_queue; 44 47 public : const uint32_t _size_context_id ; 48 public : const uint32_t _size_front_end_id ; 49 public : const uint32_t _size_ooo_engine_id ; 45 50 public : const uint32_t _size_packet_id ; 46 51 public : const uint32_t _size_general_register ; 47 52 public : const uint32_t _size_operation ; 48 53 public : const uint32_t _size_type ; 54 public : const uint32_t _size_dcache_context_id ; 55 public : const uint32_t _size_dcache_packet_id ; 56 57 public : const bool _have_port_context_id ; 58 public : const bool _have_port_front_end_id ; 59 public : const bool _have_port_ooo_engine_id ; 60 public : const bool _have_port_packet_id ; 61 public : const bool _have_port_dcache_context_id ; 62 63 public : const Tdcache_address_t _mask_address_lsb ; 64 public : const Tdcache_address_t _mask_address_msb ; 49 65 50 66 //-----[ methods ]----------------------------------------------------------- … … 55 71 Tspeculative_load_t speculative_load , 56 72 uint32_t nb_context , 73 uint32_t nb_front_end , 74 uint32_t nb_ooo_engine , 57 75 uint32_t nb_packet , 58 76 uint32_t size_general_data , … … 65 83 public : ~Parameters () ; 66 84 67 public : st ring msg_error (void);85 public : std::string msg_error (void); 68 86 69 public : st ring print (uint32_t depth);70 public : friend ostream& operator<< (ostream& output_stream,71 87 public : std::string print (uint32_t depth); 88 public : friend std::ostream& operator<< (std::ostream& output_stream, 89 morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters & x); 72 90 }; 73 91 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h
r62 r71 13 13 #include "Common/include/FromString.h" 14 14 #include "Common/include/ErrorMorpheo.h" 15 #include <ostream> 15 16 16 17 namespace morpheo { … … 23 24 namespace load_store_unit { 24 25 26 #define DCACHE_REQ_IS_LOAD(x) (x<<1) 27 #define DCACHE_REQ_IS_STORE(x) ((x<<1)|1) 28 29 #define DCACHE_RSP_IS_LOAD(x) ((x&1)==0) 30 #define DCACHE_RSP_IS_STORE(x) ((x&1)==1) 31 32 25 33 typedef enum 26 34 { … … 44 52 typedef enum 45 53 { 46 STORE_QUEUE_EMPTY 54 STORE_QUEUE_EMPTY //entry is empty 47 55 ,STORE_QUEUE_NO_VALID_NO_SPECULATIVE //entry is the top of rob, and operation isn't arrive 48 56 ,STORE_QUEUE_VALID_SPECULATIVE //entry is arrive and wait the top of rob … … 55 63 public : Tstore_queue_state_t _state ; 56 64 public : Tcontext_t _context_id ; 65 public : Tcontext_t _front_end_id ; 66 public : Tcontext_t _ooo_engine_id ; 57 67 public : Tpacket_t _packet_id ; 58 public : Tdcache_type_t _dcache_type ; 59 public : Tcontrol_t _uncached ; 68 public : Toperation_t _operation ; 60 69 public : Tlsq_ptr_t _load_queue_ptr_write; 61 public : Tdcache_ data_t_address ;70 public : Tdcache_address_t _address ; 62 71 public : Tgeneral_data_t _wdata ; 63 72 //public : Tcontrol_t _write_rd ; … … 65 74 public : Texception_t _exception ; 66 75 67 friend ostream & operator << (ostream& os, const Tstore_queue_entry_t & x) 68 { 69 return os << " * state : " << x._state << endl 70 << " * packet - context_id : " << toString(static_cast<uint32_t>(x._packet_id )) << " - " << toString(static_cast<uint32_t>(x._context_id)) << endl 71 << " * type - uncached : " << toString(static_cast<uint32_t>(x._dcache_type )) << " - " << toString(static_cast<uint32_t>(x._uncached )) << endl 72 << " * load_ptr - execption : " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << " - " << toString(static_cast<uint32_t>(x._exception )) << endl 73 << " * address - wdata : " << toString(static_cast<uint32_t>(x._address )) << " - " << toString(static_cast<uint32_t>(x._wdata )) << endl; 76 friend std::ostream & operator << (std::ostream& os, const Tstore_queue_entry_t & x) 77 { 78 return os << " * state : " << x._state << std::endl 79 << " * packet : " << toString(x._packet_id) << std::endl 80 << " * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl 81 << " * operation : " << toString(x._operation) << std::endl 82 << " * load_ptr : " << toString(x._load_queue_ptr_write) << std::endl 83 << " * exception : " << toString(x._exception) << std::endl 84 << std::hex 85 << " * address : " << toString(x._address)<< std::endl 86 << " * wdata : " << toString(x._wdata) << std::endl 87 << std::dec; 74 88 } 75 89 }; … … 92 106 public : Tspeculative_access_queue_state_t _state ; 93 107 public : Tcontext_t _context_id ; 108 public : Tcontext_t _front_end_id ; 109 public : Tcontext_t _ooo_engine_id ; 94 110 public : Tpacket_t _packet_id ; 95 public : Taccess_t _access ; 96 public : Tcontrol_t _uncached ; 97 public : Tcontrol_t _sign_extension ; 111 public : Toperation_t _operation ; 98 112 public : Tlsq_ptr_t _load_queue_ptr_write ; 99 113 public : Tlsq_ptr_t _store_queue_ptr_write; 100 114 public : Tdcache_address_t _address ; 101 public : Tgeneral_data_t _rdata ;102 115 public : Tcontrol_t _write_rd ; 103 116 public : Tgeneral_address_t _num_reg_rd ; 104 117 public : Texception_t _exception ; 118 119 friend std::ostream & operator << (std::ostream& os, const Tspeculative_access_queue_entry_t & x) 120 { 121 return os << " * state : " << x._state << std::endl 122 << " * packet : " << toString(x._packet_id) << std::endl 123 << " * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl 124 << " * operation : " << toString(x._operation) << std::endl 125 << " * load, store ptr_write : " << toString(x._load_queue_ptr_write) << " - " << toString(x._store_queue_ptr_write) << std::endl 126 << " * exception : " << toString(x._exception) << std::endl 127 << std::hex 128 << " * address : " << toString(x._address)<< std::endl 129 << std::dec 130 << " * write_rd, num_reg_rd : " << toString(x._write_rd) << " - " << toString(x._num_reg_rd)<< std::endl; 131 } 105 132 }; 106 133 … … 109 136 // ---------------------------------------------------------- 110 137 138 // HAVE_DCACHE_RSP MUST_CHECK STD::DECOD_BARRIER 139 // OPERATION_MEMORY_LOAD X X - 140 // OPERATION_MEMORY_LOCK - - - 141 // OPERATION_MEMORY_INVALIDATE - - X 142 // OPERATION_MEMORY_PREFETCH - - - 143 // OPERATION_MEMORY_FLUSH - - X 144 // OPERATION_MEMORY_SYNCHRONIZATION X - X 145 146 #define have_dcache_rsp(x) (is_operation_memory_load(x) or (x==OPERATION_MEMORY_SYNCHRONIZATION)) 147 #define must_check(x) (is_operation_memory_load(x)) 148 149 #define MASK_CHECK_BYTE_HIT 0xff // 1111_1111 150 111 151 typedef enum 112 152 { … … 121 161 class Tload_queue_entry_t 122 162 { 123 public : Tload_queue_state_t _state 124 public : Tcontext_t _context_id 125 public : T packet_t _packet_id;126 public : T access_t _access;127 public : T control_t _uncached;128 public : T control_t _sign_extension;163 public : Tload_queue_state_t _state ; 164 public : Tcontext_t _context_id ; 165 public : Tcontext_t _front_end_id ; 166 public : Tcontext_t _ooo_engine_id ; 167 public : Tpacket_t _packet_id ; 168 public : Toperation_t _operation ; 129 169 public : Tlsq_ptr_t _store_queue_ptr_write; 130 public : Tdcache_address_t _address ; 131 public : Tgeneral_data_t _rdata ; 132 public : Tcontrol_t _write_rd ; 133 public : Tgeneral_address_t _num_reg_rd ; 134 public : Texception_t _exception ; 170 public : Tdcache_address_t _address ; 171 public : Tdcache_address_t _check_hit_byte ; 172 public : Tcontrol_t _check_hit ; 173 public : Tdcache_address_t _shift ; 174 public : Tcontrol_t _is_load_signed ; 175 public : Taccess_t _access_size ; 176 public : Tgeneral_data_t _rdata ; 177 public : Tcontrol_t _write_rd ; 178 public : Tgeneral_address_t _num_reg_rd ; 179 public : Texception_t _exception ; 180 181 friend std::ostream & operator << (std::ostream& os, const Tload_queue_entry_t & x) 182 { 183 return os << " * state : " << x._state << std::endl 184 << " * packet : " << toString(x._packet_id) << std::endl 185 << " * context, front_end, ooo_engine_id : " << toString(x._context_id) << " - " << toString(x._front_end_id) << " - " << toString(x._ooo_engine_id) << std::endl 186 << " * operation : " << toString(x._operation) << std::endl 187 << " * store_queue_ptr_write : " << toString(x._store_queue_ptr_write) << std::endl 188 << " * exception : " << toString(x._exception) << std::endl 189 << " * check_hit, check_hit_byte : " << toString(x._check_hit) << " - " << toString(x._check_hit_byte) << std::endl 190 << std::hex 191 << " * address : " << toString(x._address)<< std::endl 192 << " * rdata : " << toString(x._rdata) << std::endl 193 << std::dec 194 << " * write_rd, num_reg_rd : " << toString(x._write_rd) << " - " << toString(x._num_reg_rd)<< std::endl; 195 } 196 135 197 }; 136 198
Note: See TracChangeset
for help on using the changeset viewer.