Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 76)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 78)
@@ -5,5 +5,5 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  * Ce composant peut être amélioré en placant deux ptr de lecture au lieu d'un : un pour l'accès au cache et un pour le commit
@@ -46,5 +46,5 @@
 #endif
   {
-    // -----[ fields ]----------------------------------------------------
+    // -----[ fields ]----------------------------------------------------
     // Parameters
   protected : const std::string       _name;
@@ -53,5 +53,5 @@
 
 #ifdef STATISTICS
-  private   : Stat                           * _stat;
+  public    : Stat                           * _stat;
 
   private   : counter_t                      * _stat_use_store_queue;
@@ -83,10 +83,10 @@
 
 #ifdef SYSTEMC
-    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     // Interface
   public    : SC_CLOCK                      *  in_CLOCK        ;
   public    : SC_IN (Tcontrol_t)            *  in_NRESET       ;
 
-    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_VAL         ;
   public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_IN_ACK         ;
@@ -96,18 +96,18 @@
   public    : SC_IN (Tpacket_t         )    *  in_MEMORY_IN_PACKET_ID   ;
   public    : SC_IN (Toperation_t      )    *  in_MEMORY_IN_OPERATION   ;
-//public    : SC_IN (Ttype_t           )    *  in_MEMORY_IN_TYPE        ;
+  public    : SC_IN (Ttype_t           )    *  in_MEMORY_IN_TYPE        ;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
   public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-//public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_HAS_IMMEDIAT;
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_HAS_IMMEDIAT;
   public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_IMMEDIAT    ; // memory address
   public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RA     ; // memory address
   public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RB     ; // data        (store)
-//public    : SC_IN (Tspecial_data_t   )    *  in_MEMORY_IN_DATA_RC     ;
-//public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RD    ; // = (operation==load)
+  public    : SC_IN (Tspecial_data_t   )    *  in_MEMORY_IN_DATA_RC     ;
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RD    ; // = (operation==load)
   public    : SC_IN (Tgeneral_address_t)    *  in_MEMORY_IN_NUM_REG_RD  ; // destination (load)
-//public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RE    ;
-//public    : SC_IN (Tspecial_address_t)    *  in_MEMORY_IN_NUM_REG_RE  ;
-
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RE    ;
+  public    : SC_IN (Tspecial_address_t)    *  in_MEMORY_IN_NUM_REG_RE  ;
+
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_VAL       ;
   public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_OUT_ACK       ;
@@ -116,13 +116,18 @@
   public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_OOO_ENGINE_ID;
   public    : SC_OUT(Tpacket_t         )    * out_MEMORY_OUT_PACKET_ID ;
+//public    : SC_OUT(Toperation_t      )    * out_MEMORY_OUT_OPERATION ;
+  public    : SC_OUT(Ttype_t           )    * out_MEMORY_OUT_TYPE      ;
   public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RD  ; // = (operation==load)
   public    : SC_OUT(Tgeneral_address_t)    * out_MEMORY_OUT_NUM_REG_RD; // destination (load)
   public    : SC_OUT(Tgeneral_data_t   )    * out_MEMORY_OUT_DATA_RD   ; // data        (load)
-//public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RE  ;
-//public    : SC_OUT(Tspecial_address_t)    * out_MEMORY_OUT_NUM_REG_RE;
-//public    : SC_OUT(Tspecial_data_t   )    * out_MEMORY_OUT_DATA_RE   ;
+  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RE  ;
+  public    : SC_OUT(Tspecial_address_t)    * out_MEMORY_OUT_NUM_REG_RE;
+  public    : SC_OUT(Tspecial_data_t   )    * out_MEMORY_OUT_DATA_RE   ;
   public    : SC_OUT(Texception_t      )    * out_MEMORY_OUT_EXCEPTION ;
-
-    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_NO_SEQUENCE;
+  public    : SC_OUT(Tgeneral_data_t   )    * out_MEMORY_OUT_ADDRESS   ;
+    
+
+    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_REQ_VAL       ;
   public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_REQ_ACK       ;
@@ -133,5 +138,5 @@
   public    : SC_OUT(Tdcache_data_t    )    * out_DCACHE_REQ_WDATA     ;
 
-    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_RSP_VAL       ;
   public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_RSP_ACK       ;
@@ -141,5 +146,5 @@
   public    : SC_IN (Tdcache_error_t   )    *  in_DCACHE_RSP_ERROR     ;
 
-    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   public    : SC_OUT(Tcontrol_t        )   ** out_BYPASS_MEMORY_VAL       ;
   public    : SC_OUT(Tcontext_t        )   ** out_BYPASS_MEMORY_OOO_ENGINE_ID;
@@ -147,5 +152,5 @@
   public    : SC_OUT(Tgeneral_data_t   )   ** out_BYPASS_MEMORY_DATA      ;
 
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
   protected : Tstore_queue_entry_t                                        * _store_queue;
   protected : Tload_queue_entry_t                                         * _load_queue;
@@ -160,7 +165,7 @@
   public    : void (morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit::*function_genMealy_retire) (void);
 
-    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-
-    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
     // Registers
@@ -182,5 +187,5 @@
 #endif
 
-    // -----[ methods ]---------------------------------------------------
+    // -----[ methods ]---------------------------------------------------
 
 #ifdef SYSTEMC
