Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 78)
@@ -69,5 +69,5 @@
       case NO_SPECULATIVE_LOAD     :
       case SPECULATIVE_LOAD_ACCESS :
-      case SPECULATIVE_LOAD_BYPASS :
+	//case SPECULATIVE_LOAD_BYPASS :
       default                      :
 	{
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 78)
@@ -72,15 +72,17 @@
    in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"    ,_param->_size_packet_id       );
    in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
+   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
    in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage
+   if (_param->_have_port_load_queue_ptr)
    in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
-// in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
+   in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
    in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
    in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
    in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
-// in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
-//    in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
+   in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
+   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
    in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
-// in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
-// in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
+   in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
+   in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
     }
 
@@ -105,11 +107,15 @@
       if (_param->_have_port_packet_id)       
       out_MEMORY_OUT_PACKET_ID     = interface->set_signal_out <Tpacket_t         > ("packet_id"     ,_param->_size_packet_id        );
+//    out_MEMORY_OUT_OPERATION     = interface->set_signal_out <Toperation_t      > ("operation"     ,_param->_size_operation        );
+      out_MEMORY_OUT_TYPE          = interface->set_signal_out <Ttype_t           > ("type"          ,_param->_size_type             );
       out_MEMORY_OUT_WRITE_RD      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
       out_MEMORY_OUT_NUM_REG_RD    = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"    ,_param->_size_general_register );
       out_MEMORY_OUT_DATA_RD       = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"       ,_param->_size_general_data     );
-//    out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
-//    out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
-//    out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
+      out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_re"      ,1                              );
+      out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
+      out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
       out_MEMORY_OUT_EXCEPTION     = interface->set_signal_out <Texception_t      > ("exception"     ,_param->_size_exception        );
+      out_MEMORY_OUT_NO_SEQUENCE   = interface->set_signal_out <Tcontrol_t        > ("no_sequence"   ,1                              );
+      out_MEMORY_OUT_ADDRESS       = interface->set_signal_out <Tgeneral_data_t   > ("address"       ,_param->_size_general_data     );
     }
 
@@ -153,13 +159,13 @@
     // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-    if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
+//  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
       {
-	out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_size_load_queue];
+	out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_nb_bypass_memory];
 	if (_param->_have_port_ooo_engine_id)    
-	out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_size_load_queue];
-	out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_size_load_queue];
-	out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_size_load_queue];
+	out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_nb_bypass_memory];
+	out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory];
+	out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_nb_bypass_memory];
 	
-	for (uint32_t i=0; i<_param->_size_load_queue; i++)
+	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
 	  {
 	    Interface_fifo * interface = _interfaces->set_interface("memory_out"
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 78)
@@ -44,15 +44,17 @@
     delete     in_MEMORY_IN_PACKET_ID   ;
     delete     in_MEMORY_IN_OPERATION   ;
+    delete     in_MEMORY_IN_TYPE        ;
     delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
+    if (_param->_have_port_load_queue_ptr)
     delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-//  delete     in_MEMORY_IN_HAS_IMMEDIAT;
+    delete     in_MEMORY_IN_HAS_IMMEDIAT;
     delete     in_MEMORY_IN_IMMEDIAT    ;
     delete     in_MEMORY_IN_DATA_RA     ;
     delete     in_MEMORY_IN_DATA_RB     ;
-//  delete     in_MEMORY_IN_DATA_RC     ;
-//  delete     in_MEMORY_IN_WRITE_RD    ;
+    delete     in_MEMORY_IN_DATA_RC     ;
+    delete     in_MEMORY_IN_WRITE_RD    ;
     delete     in_MEMORY_IN_NUM_REG_RD  ;
-//  delete     in_MEMORY_IN_WRITE_RE    ;
-//  delete     in_MEMORY_IN_NUM_REG_RE  ;
+    delete     in_MEMORY_IN_WRITE_RE    ;
+    delete     in_MEMORY_IN_NUM_REG_RE  ;
     
     delete    out_MEMORY_OUT_VAL       ;
@@ -66,11 +68,15 @@
     if (_param->_have_port_packet_id)
     delete    out_MEMORY_OUT_PACKET_ID ;
+//  delete    out_MEMORY_OUT_OPERATION ;
+    delete    out_MEMORY_OUT_TYPE      ;
     delete    out_MEMORY_OUT_WRITE_RD  ;
     delete    out_MEMORY_OUT_NUM_REG_RD;
     delete    out_MEMORY_OUT_DATA_RD   ;
-//  delete    out_MEMORY_OUT_WRITE_RE  ;
-//  delete    out_MEMORY_OUT_NUM_REG_RE;
-//  delete    out_MEMORY_OUT_DATA_RE   ;
+    delete    out_MEMORY_OUT_WRITE_RE  ;
+    delete    out_MEMORY_OUT_NUM_REG_RE;
+    delete    out_MEMORY_OUT_DATA_RE   ;
     delete    out_MEMORY_OUT_EXCEPTION ;
+    delete    out_MEMORY_OUT_NO_SEQUENCE;
+    delete    out_MEMORY_OUT_ADDRESS   ;
     
     delete    out_DCACHE_REQ_VAL       ;
@@ -91,12 +97,9 @@
     delete     in_DCACHE_RSP_ERROR     ;
     
-    if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
-      {
-	delete [] out_BYPASS_MEMORY_VAL       ;
-	if (_param->_have_port_ooo_engine_id)    
-	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
-	delete [] out_BYPASS_MEMORY_NUM_REG   ;
-	delete [] out_BYPASS_MEMORY_DATA      ;
-      }
+    delete [] out_BYPASS_MEMORY_VAL       ;
+    if (_param->_have_port_ooo_engine_id)    
+    delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
+    delete [] out_BYPASS_MEMORY_NUM_REG   ;
+    delete [] out_BYPASS_MEMORY_DATA      ;
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 78)
@@ -120,4 +120,6 @@
     if (_param->_have_port_packet_id)
     PORT_WRITE(out_MEMORY_OUT_PACKET_ID    , memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    , memory_out_operation    );
+    PORT_WRITE(out_MEMORY_OUT_TYPE         , TYPE_MEMORY             );
     PORT_WRITE(out_MEMORY_OUT_WRITE_RD     , memory_out_write_rd     );
     PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   , memory_out_num_reg_rd   );
@@ -126,6 +128,10 @@
 //  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , memory_out_num_reg_re   );
 //  PORT_WRITE(out_MEMORY_OUT_DATA_RE      , memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      , 0);
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION    , memory_out_exception    );
-
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  , 0);
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      , 0);
     // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 78)
@@ -265,4 +265,8 @@
 	    //  others in speculation_access_queue
 
+#ifdef DEBUG_TEST
+	    if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY)
+	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
+#endif
 	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
 	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
@@ -376,5 +380,5 @@
 		    _store_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID   );
 		    _store_queue [index]._operation            = operation;
-		    _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
+		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
 		    _store_queue [index]._address              = address;
 
@@ -415,5 +419,5 @@
 
 		_speculative_access_queue [index]._operation            = operation;
-		_speculative_access_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
+		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
 		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
 		_speculative_access_queue [index]._address              = address;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 78)
@@ -25,4 +25,5 @@
 			  uint32_t            nb_port_check          ,
 			  Tspeculative_load_t speculative_load       ,
+			  uint32_t            nb_bypass_memory       ,
 			  uint32_t            nb_context             ,
 			  uint32_t            nb_front_end           ,
@@ -30,5 +31,7 @@
 			  uint32_t            nb_packet              ,
 			  uint32_t            size_general_data      ,
-			  uint32_t            nb_general_register    ):
+			  uint32_t            size_special_data      ,
+			  uint32_t            nb_general_register    ,
+			  uint32_t            nb_special_register    ):
     _size_store_queue        (size_store_queue       ),
     _size_load_queue         (size_load_queue        ),
@@ -36,4 +39,5 @@
     _nb_port_check           (nb_port_check          ),
     _speculative_load        (speculative_load       ),
+    _nb_bypass_memory        (nb_bypass_memory       ),
     _nb_context              (nb_context             ),
     _nb_front_end            (nb_front_end           ),
@@ -41,5 +45,7 @@
     _nb_packet               (nb_packet              ),
     _size_general_data       (size_general_data      ),
+    _size_special_data       (size_special_data      ),
     _nb_general_register     (nb_general_register    ),
+    _nb_special_register     (nb_special_register    ),
     
     _size_address_store_queue              (log2(size_store_queue             )),
@@ -52,4 +58,5 @@
     _size_packet_id          (log2(nb_packet          )),
     _size_general_register   (log2(nb_general_register)),
+    _size_special_register   (log2(nb_special_register)),
     _size_dcache_context_id  (_size_context_id + _size_front_end_id + _size_ooo_engine_id),
     _size_dcache_packet_id   ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1),
@@ -60,4 +67,5 @@
     _have_port_packet_id         (_size_packet_id    >0),
     _have_port_dcache_context_id (_size_dcache_context_id>0),
+    _have_port_load_queue_ptr    (_size_load_queue>1),
 
     _mask_address_lsb            (gen_mask<Tdcache_address_t>(log2(size_general_data/8))),
@@ -77,4 +85,5 @@
     _nb_port_check           (param._nb_port_check          ),
     _speculative_load        (param._speculative_load       ),
+    _nb_bypass_memory        (param._nb_bypass_memory       ),
     _nb_context              (param._nb_context             ),
     _nb_front_end            (param._nb_front_end           ),
@@ -82,5 +91,7 @@
     _nb_packet               (param._nb_packet              ),
     _size_general_data       (param._size_general_data      ),
+    _size_special_data       (param._size_special_data      ),
     _nb_general_register     (param._nb_general_register    ),
+    _nb_special_register     (param._nb_special_register    ),
 
     _size_address_store_queue              (param._size_address_store_queue             ),
@@ -93,4 +104,5 @@
     _size_packet_id          (param._size_packet_id         ),
     _size_general_register   (param._size_general_register  ),
+    _size_special_register   (param._size_special_register  ),
     _size_dcache_context_id  (param._size_dcache_context_id ),
     _size_dcache_packet_id   (param._size_dcache_packet_id  ),
@@ -100,6 +112,6 @@
     _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
     _have_port_packet_id     (param._have_port_packet_id    ),
-
     _have_port_dcache_context_id(param._have_port_dcache_context_id),
+    _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
 
     _mask_address_lsb        (param._mask_address_lsb),
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 78)
@@ -21,9 +21,9 @@
 #undef  FUNCTION
 #define FUNCTION "Load_store_unit::msg_error"
-  std::string Parameters::msg_error(void)
+  Parameters_test Parameters::msg_error(void)
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
     
-    std::string msg = "";
+    Parameters_test test("Load_store_unit");
 
     switch (_speculative_load)
@@ -31,19 +31,32 @@
       case SPECULATIVE_LOAD_COMMIT :
 	{
+	  if (not (_nb_bypass_memory == 0))
+	    test.error("Bypass memory is not supported. Please wait a next revision.");
+ 
 	  break;
 	}
       case NO_SPECULATIVE_LOAD     :
       case SPECULATIVE_LOAD_ACCESS :
-      case SPECULATIVE_LOAD_BYPASS :
+      // case SPECULATIVE_LOAD_BYPASS :
       default                      :
 	{
-	  msg += "  - Speculative load scheme is not supported : " +toString(_speculative_load);
+	  if (not (_nb_bypass_memory == 0))
+	    test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");
+
+	  test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");
 	  break;
 	}
       }
 
-    return msg;
+    if (not (_size_store_queue >= 2))
+      test.error("Store queue must have at less two slot.");
+
+    if (not (_nb_bypass_memory <= _size_load_queue))
+      test.error("Bypass number must be less than load_queue's size.");
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+
+    return test;
+
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_print.cpp	(revision 78)
@@ -33,4 +33,5 @@
     xml.singleton_begin("nb_port_check                "); xml.attribut("value",toString(_nb_port_check                )); xml.singleton_end();
     xml.singleton_begin("speculative_load             "); xml.attribut("value",toString(_speculative_load             )); xml.singleton_end();
+    xml.singleton_begin("nb_bypass_memory             "); xml.attribut("value",toString(_nb_bypass_memory             )); xml.singleton_end();
     xml.singleton_begin("nb_context                   "); xml.attribut("value",toString(_nb_context                   )); xml.singleton_end();
     xml.singleton_begin("nb_front_end                 "); xml.attribut("value",toString(_nb_front_end                 )); xml.singleton_end();
