Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 77)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 78)
@@ -161,13 +161,22 @@
 #  define OPERATION_FIND_L_FL1                     0x2        // 000_0000 l.fl1
 
-#  define OPERATION_SPECIAL_L_MFSPR                0x1        // 000_0000 l.mfspr
-#  define OPERATION_SPECIAL_L_MTSPR                0x2        // 000_0000 l.mtspr
-#  define OPERATION_SPECIAL_L_MAC                  0x4        // 000_0000 l.mac   , l.maci
-#  define OPERATION_SPECIAL_L_MACRC                0x8        // 000_0000 l.macrc
-#  define OPERATION_SPECIAL_L_MSB                  0x10       // 000_0000 l.msb
-
-#  define OPERATION_BRANCH_L_TEST_NF               0x1        // 000_0000 l.bnf
-#  define OPERATION_BRANCH_L_TEST_F                0x2        // 000_0000 l.bf
-#  define OPERATION_BRANCH_L_JALR                  0x4        // 000_0000 l.jal   , l.jalr , l.jr
+#  define OPERATION_SPECIAL_L_NOP                  0xff       // 000_0000 l.nop   
+#  define OPERATION_SPECIAL_L_MFSPR                0x1        // 000_0001 l.mfspr
+#  define OPERATION_SPECIAL_L_MTSPR                0x2        // 000_0010 l.mtspr
+#  define OPERATION_SPECIAL_L_RFE                  0x4        // 000_0100 l.rfe  
+#  define OPERATION_SPECIAL_L_MAC                  0x11       // 001_0001 l.mac   , l.maci
+#  define OPERATION_SPECIAL_L_MACRC                0x12       // 001_0010 l.macrc
+#  define OPERATION_SPECIAL_L_MSB                  0x14       // 001_0100 l.msb
+#  define OPERATION_SPECIAL_L_MSYNC                0x21       // 010_0001 l.msync
+#  define OPERATION_SPECIAL_L_PSYNC                0x22       // 010_0010 l.psync
+#  define OPERATION_SPECIAL_L_CSYNC                0x24       // 010_0100 l.csync
+#  define OPERATION_SPECIAL_L_SYS                  0x41       // 100_0001 l.sys  
+#  define OPERATION_SPECIAL_L_TRAP                 0x42       // 100_0010 l.trap 
+
+
+#  define OPERATION_BRANCH_NONE                    0x1        // 000_0000 l.j
+#  define OPERATION_BRANCH_L_TEST_NF               0x2        // 000_0000 l.bnf
+#  define OPERATION_BRANCH_L_TEST_F                0x4        // 000_0000 l.bf
+#  define OPERATION_BRANCH_L_JALR                  0x8        // 000_0000 l.jal   , l.jalr , l.jr
 
   //-------------------------------------------------------[ Custom ]-----
@@ -195,4 +204,10 @@
 
 #  define SIZE_EXCEPTION                           5
+#  define SIZE_EXCEPTION_USE                       4
+#  define SIZE_EXCEPTION_MEMORY                    3
+#  define SIZE_EXCEPTION_CUSTOM                    3
+#  define SIZE_EXCEPTION_ALU                       2
+#  define SIZE_EXCEPTION_DECOD                     2
+#  define SIZE_EXCEPTION_IFETCH                    2
 
 #  define EXCEPTION_NONE                           0x00       // none exception
@@ -229,4 +244,5 @@
 #  define EXCEPTION_CUSTOM_6                       0x1f       // Reserved for custom exceptions
 
+
 #define exception_to_address(x) (x<<8)
 
@@ -253,4 +269,50 @@
 #  define EXCEPTION_ALU_SPR_ACCESS_INVALID         0x2        // SPR     present in ALU but not compatible privilege
 #  define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE    0x3        // SPR not present in ALU
+
+#  define EXCEPTION_DECOD_NONE                     0x0        // none exception
+#  define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION      0x1        // Instruction is illegal (no implemented)
+#  define EXCEPTION_DECOD_SYSCALL                  0x2        // System Call
+//#define EXCEPTION_DECOD_TRAP                     0x4        // L.trap or debug unit (note : must read SR !)
+
+#  define EXCEPTION_IFETCH_NONE                    0x0        // Fetch Unit generate none exception
+#  define EXCEPTION_IFETCH_INSTRUCTION_TLB         0x1        // ITLB miss
+#  define EXCEPTION_IFETCH_INSTRUCTION_PAGE        0x2        // No matching or page violation protection in pages tables
+#  define EXCEPTION_IFETCH_BUS_ERROR               0x3        // Access at a invalid physical address
+
+#  define EXCEPTION_USE_NONE                       0x0        // 
+#  define EXCEPTION_USE_ILLEGAL_INSTRUCTION        0x1        // illegal_instruction
+#  define EXCEPTION_USE_RANGE                      0x2        // range
+#  define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT      0x3        // TLB miss, page fault, bus error, alignment
+#  define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT   0x4        // TLB miss, page fault, bus error
+#  define EXCEPTION_USE_SYSCALL                    0x5        // syscall
+#  define EXCEPTION_USE_TRAP                       0x6        // trap
+#  define EXCEPTION_USE_CUSTOM_0                   0x7        // 
+#  define EXCEPTION_USE_CUSTOM_1                   0x8        // 
+#  define EXCEPTION_USE_CUSTOM_2                   0x9        // 
+#  define EXCEPTION_USE_CUSTOM_3                   0xa        // 
+#  define EXCEPTION_USE_CUSTOM_4                   0xb        // 
+#  define EXCEPTION_USE_CUSTOM_5                   0xc        // 
+#  define EXCEPTION_USE_CUSTOM_6                   0xd        // 
+
+  //=======================================================[ icache ]=====
+
+  //--------------------------------------------------[ icache_type ]-----
+
+#  define SIZE_ICACHE_TYPE                              2
+
+#  define ICACHE_TYPE_LOAD                              0x0        // 0000
+#  define ICACHE_TYPE_LOCK                              0x1        // 0001
+#  define ICACHE_TYPE_INVALIDATE                        0x2        // 0010
+#  define ICACHE_TYPE_PREFETCH                          0x3        // 0011
+
+// just take the 2 less significative bits.
+#define operation_to_icache_type(x) (x&0x3)
+
+  //-------------------------------------------------[ icache_error ]-----
+
+#  define SIZE_ICACHE_ERROR                             1
+
+#  define ICACHE_ERROR_NONE                             0x0
+#  define ICACHE_ERROR_BUS_ERROR                        0x1
 
   //=======================================================[ dcache ]=====
@@ -377,4 +439,11 @@
 #  define SPR_MACHI                                2          // MAC High
 
+#  define NB_SPR_LOGIC                             2
+#  define LOG2_NB_SPR_LOGIC                        1
+  // SPR_LOGIC[0] = F
+  // SPR_LOGIC[1] = Carry, Overflow
+#  define SPR_LOGIC_SR_F                           0x0        // Status register bit F                   (size = 1)
+#  define SPR_LOGIC_SR_CY_OV                       0x1        // Status register bit overflow and carry  (size = 2)
+
   //----------------------------------------------[ spr_mode_access ]-----
 
@@ -385,44 +454,415 @@
 #  define SPR_ACCESS_MODE_READ_ONLY_COND           0x5        // 101 special read
 
+  //--------------------------------------------------------[ event ]-----
+#  define SIZE_EVENT_STATE                         2
+
+#  define EVENT_STATE_NO_EVENT                     0          // no event : current case
+#  define EVENT_STATE_EVENT                        1          // Have a event : make necessary to manage the event
+#  define EVENT_STATE_WAITEND                      2          // Wait end of manage event (restaure a good context)
+#  define EVENT_STATE_END                          3          // CPU can continue
+
+#  define SIZE_EVENT_TYPE                          3
+
+#  define EVENT_TYPE_NONE                          0          // no event
+#  define EVENT_TYPE_MISS_SPECULATION              1          // miss of speculation (load or branch miss speculation)
+#  define EVENT_TYPE_EXCEPTION                     2          // exception or interruption occure
+#  define EVENT_TYPE_BRANCH_NO_ACCURATE            3          // branch is no accurate (old speculation is a miss)
+#  define EVENT_TYPE_SPR_ACCESS                    4          // decod a mtspr or mfspr instruction
+#  define EVENT_TYPE_MSYNC                         5          // decod a memory   synchronization
+#  define EVENT_TYPE_PSYNC                         6          // decod a pipeline synchronization
+#  define EVENT_TYPE_CSYNC                         7          // decod a context  synchronization
+
+  //-------------------------------------------------[ branch_state ]-----
+#  define SIZE_BRANCH_STATE                        2
+
+#  define BRANCH_STATE_NONE                        0x0        // 0 0
+#  define BRANCH_STATE_NSPEC_TAKE                  0x1        // 0 1  -> incondionnal
+#  define BRANCH_STATE_SPEC_NTAKE                  0x2        // 1 0
+#  define BRANCH_STATE_SPEC_TAKE                   0x3        // 1 1
+
+  //---------------------------------------------[ branch_condition ]-----
+
+#  define SIZE_BRANCH_CONDITION                    4
+
+#  define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK          0x0        // None condition (jump)
+#  define BRANCH_CONDITION_NONE_WITH_WRITE_STACK             0x8        // None condition (jump)
+#  define BRANCH_CONDITION_FLAG_UNSET                        0x2        // Branch if Flag is clear
+#  define BRANCH_CONDITION_FLAG_SET                          0x3        // Branch if Flag is set
+#  define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4        // Branch if a register is read
+#  define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK    0xc        // Branch if a register is read
+#  define BRANCH_CONDITION_READ_STACK                        0xf        // Branch with pop  in stack pointer
+
+  //--------------------------------------------------[ instruction ]-----
+#  define NB_INSTRUCTION                           213        // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format)
+
+  enum 
+    {
+      // ORBIS
+      INSTRUCTION_L_ADD,
+      INSTRUCTION_L_ADDC,
+      INSTRUCTION_L_ADDI,
+      INSTRUCTION_L_ADDIC,
+      INSTRUCTION_L_AND,
+      INSTRUCTION_L_ANDI,
+      INSTRUCTION_L_BF,
+      INSTRUCTION_L_BNF,
+      INSTRUCTION_L_CMOV,
+      INSTRUCTION_L_CSYNC,
+      INSTRUCTION_L_CUST1,
+      INSTRUCTION_L_CUST2,
+      INSTRUCTION_L_CUST3,
+      INSTRUCTION_L_CUST4,
+      INSTRUCTION_L_CUST5,
+      INSTRUCTION_L_CUST6,
+      INSTRUCTION_L_CUST7,
+      INSTRUCTION_L_CUST8,
+      INSTRUCTION_L_DIV,
+      INSTRUCTION_L_DIVU,
+      INSTRUCTION_L_EXTBS,
+      INSTRUCTION_L_EXTBZ,
+      INSTRUCTION_L_EXTHS,
+      INSTRUCTION_L_EXTHZ,
+      INSTRUCTION_L_EXTWS,
+      INSTRUCTION_L_EXTWZ,
+      INSTRUCTION_L_FF1,
+      INSTRUCTION_L_FL1,
+      INSTRUCTION_L_J,
+      INSTRUCTION_L_JAL,
+      INSTRUCTION_L_JALR,
+      INSTRUCTION_L_JR,
+      INSTRUCTION_L_LBS,
+      INSTRUCTION_L_LBZ,
+      INSTRUCTION_L_LD,
+      INSTRUCTION_L_LHS,
+      INSTRUCTION_L_LHZ,
+      INSTRUCTION_L_LWS,
+      INSTRUCTION_L_LWZ,
+      INSTRUCTION_L_MAC,
+      INSTRUCTION_L_MACI,
+      INSTRUCTION_L_MACRC,
+      INSTRUCTION_L_MFSPR,
+      INSTRUCTION_L_MOVHI,
+      INSTRUCTION_L_MSB,
+      INSTRUCTION_L_MSYNC,
+      INSTRUCTION_L_MTSPR,
+      INSTRUCTION_L_MUL,
+      INSTRUCTION_L_MULI,
+      INSTRUCTION_L_MULU,
+      INSTRUCTION_L_NOP,
+      INSTRUCTION_L_OR,
+      INSTRUCTION_L_ORI,
+      INSTRUCTION_L_PSYNC,
+      INSTRUCTION_L_RFE,
+      INSTRUCTION_L_ROR,
+      INSTRUCTION_L_RORI,
+      INSTRUCTION_L_SB,
+      INSTRUCTION_L_SD,
+      INSTRUCTION_L_SFEQ,
+      INSTRUCTION_L_SFEQI,
+      INSTRUCTION_L_SFGES,
+      INSTRUCTION_L_SFGESI,
+      INSTRUCTION_L_SFGEU,
+      INSTRUCTION_L_SFGEUI,
+      INSTRUCTION_L_SFGTS,
+      INSTRUCTION_L_SFGTSI,
+      INSTRUCTION_L_SFGTU,
+      INSTRUCTION_L_SFGTUI,
+      INSTRUCTION_L_SFLES,
+      INSTRUCTION_L_SFLESI,
+      INSTRUCTION_L_SFLEU,
+      INSTRUCTION_L_SFLEUI,
+      INSTRUCTION_L_SFLTS,
+      INSTRUCTION_L_SFLTSI,
+      INSTRUCTION_L_SFLTU,
+      INSTRUCTION_L_SFLTUI,
+      INSTRUCTION_L_SFNE,
+      INSTRUCTION_L_SFNEI,
+      INSTRUCTION_L_SH,
+      INSTRUCTION_L_SLL,
+      INSTRUCTION_L_SLLI,
+      INSTRUCTION_L_SRA,
+      INSTRUCTION_L_SRAI,
+      INSTRUCTION_L_SRL,
+      INSTRUCTION_L_SRLI,
+      INSTRUCTION_L_SUB,
+      INSTRUCTION_L_SW,
+      INSTRUCTION_L_SYS,
+      INSTRUCTION_L_TRAP,
+      INSTRUCTION_L_XOR,
+      INSTRUCTION_L_XORI,
+      // ORFPX
+      INSTRUCTION_LF_ADD_D,
+      INSTRUCTION_LF_ADD_S,
+      INSTRUCTION_LF_CUST1_D,
+      INSTRUCTION_LF_CUST1_S,
+      INSTRUCTION_LF_DIV_D,
+      INSTRUCTION_LF_DIV_S,
+      INSTRUCTION_LF_FTOI_D,
+      INSTRUCTION_LF_FTOI_S,
+      INSTRUCTION_LF_ITOF_D,
+      INSTRUCTION_LF_ITOF_S,
+      INSTRUCTION_LF_MADD_D,
+      INSTRUCTION_LF_MADD_S,
+      INSTRUCTION_LF_MUL_D,
+      INSTRUCTION_LF_MUL_S,
+      INSTRUCTION_LF_REM_D,
+      INSTRUCTION_LF_REM_S,
+      INSTRUCTION_LF_SFEQ_D,
+      INSTRUCTION_LF_SFEQ_S,
+      INSTRUCTION_LF_SFGE_D,
+      INSTRUCTION_LF_SFGE_S,
+      INSTRUCTION_LF_SFGT_D,
+      INSTRUCTION_LF_SFGT_S,
+      INSTRUCTION_LF_SFLE_D,
+      INSTRUCTION_LF_SFLE_S,
+      INSTRUCTION_LF_SFLT_D,
+      INSTRUCTION_LF_SFLT_S,
+      INSTRUCTION_LF_SFNE_D,
+      INSTRUCTION_LF_SFNE_S,
+      INSTRUCTION_LF_SUB_D,
+      INSTRUCTION_LF_SUB_S,
+      // ORVDX
+      INSTRUCTION_LV_ADD_B,
+      INSTRUCTION_LV_ADD_H,
+      INSTRUCTION_LV_ADDS_B,
+      INSTRUCTION_LV_ADDS_H,
+      INSTRUCTION_LV_ADDU_B,
+      INSTRUCTION_LV_ADDU_H,
+      INSTRUCTION_LV_ADDUS_B,
+      INSTRUCTION_LV_ADDUS_H,
+      INSTRUCTION_LV_ALL_EQ_B,
+      INSTRUCTION_LV_ALL_EQ_H,
+      INSTRUCTION_LV_ALL_GE_B,
+      INSTRUCTION_LV_ALL_GE_H,
+      INSTRUCTION_LV_ALL_GT_B,
+      INSTRUCTION_LV_ALL_GT_H,
+      INSTRUCTION_LV_ALL_LE_B,
+      INSTRUCTION_LV_ALL_LE_H,
+      INSTRUCTION_LV_ALL_LT_B,
+      INSTRUCTION_LV_ALL_LT_H,
+      INSTRUCTION_LV_ALL_NE_B,
+      INSTRUCTION_LV_ALL_NE_H,
+      INSTRUCTION_LV_AND,
+      INSTRUCTION_LV_ANY_EQ_B,
+      INSTRUCTION_LV_ANY_EQ_H,
+      INSTRUCTION_LV_ANY_GE_B,
+      INSTRUCTION_LV_ANY_GE_H,
+      INSTRUCTION_LV_ANY_GT_B,
+      INSTRUCTION_LV_ANY_GT_H,
+      INSTRUCTION_LV_ANY_LE_B,
+      INSTRUCTION_LV_ANY_LE_H,
+      INSTRUCTION_LV_ANY_LT_B,
+      INSTRUCTION_LV_ANY_LT_H,
+      INSTRUCTION_LV_ANY_NE_B,
+      INSTRUCTION_LV_ANY_NE_H,
+      INSTRUCTION_LV_AVG_B,
+      INSTRUCTION_LV_AVG_H,
+      INSTRUCTION_LV_CMP_EQ_B,
+      INSTRUCTION_LV_CMP_EQ_H,
+      INSTRUCTION_LV_CMP_GE_B,
+      INSTRUCTION_LV_CMP_GE_H,
+      INSTRUCTION_LV_CMP_GT_B,
+      INSTRUCTION_LV_CMP_GT_H,
+      INSTRUCTION_LV_CMP_LE_B,
+      INSTRUCTION_LV_CMP_LE_H,
+      INSTRUCTION_LV_CMP_LT_B,
+      INSTRUCTION_LV_CMP_LT_H,
+      INSTRUCTION_LV_CMP_NE_B,
+      INSTRUCTION_LV_CMP_NE_H,
+      INSTRUCTION_LV_CUST1,
+      INSTRUCTION_LV_CUST2,
+      INSTRUCTION_LV_CUST3,
+      INSTRUCTION_LV_CUST4,
+      INSTRUCTION_LV_MADDS_H,
+      INSTRUCTION_LV_MAX_B,
+      INSTRUCTION_LV_MAX_H,
+      INSTRUCTION_LV_MERGE_B,
+      INSTRUCTION_LV_MERGE_H,
+      INSTRUCTION_LV_MIN_B,
+      INSTRUCTION_LV_MIN_H,
+      INSTRUCTION_LV_MSUBS_H,
+      INSTRUCTION_LV_MULS_H,
+      INSTRUCTION_LV_NAND,
+      INSTRUCTION_LV_NOR,
+      INSTRUCTION_LV_OR,
+      INSTRUCTION_LV_PACK_B,
+      INSTRUCTION_LV_PACK_H,
+      INSTRUCTION_LV_PACKS_B,
+      INSTRUCTION_LV_PACKS_H,
+      INSTRUCTION_LV_PACKUS_B,
+      INSTRUCTION_LV_PACKUS_H,
+      INSTRUCTION_LV_PERM_N,
+      INSTRUCTION_LV_RL_B,
+      INSTRUCTION_LV_RL_H,
+      INSTRUCTION_LV_SLL,
+      INSTRUCTION_LV_SLL_B,
+      INSTRUCTION_LV_SLL_H,
+      INSTRUCTION_LV_SRA_B,
+      INSTRUCTION_LV_SRA_H,
+      INSTRUCTION_LV_SRL,
+      INSTRUCTION_LV_SRL_B,
+      INSTRUCTION_LV_SRL_H,
+      INSTRUCTION_LV_SUB_B,
+      INSTRUCTION_LV_SUB_H,
+      INSTRUCTION_LV_SUBS_B,
+      INSTRUCTION_LV_SUBS_H,
+      INSTRUCTION_LV_SUBU_B,
+      INSTRUCTION_LV_SUBU_H,
+      INSTRUCTION_LV_SUBUS_B,
+      INSTRUCTION_LV_SUBUS_H,
+      INSTRUCTION_LV_UNPACK_B,
+      INSTRUCTION_LV_UNPACK_H,
+      INSTRUCTION_LV_XOR
+    };
+
+  //-----------------------------------------------[ Code Operation ]-----
+
+#  define MAX_OPCOD_0                              64            // Instructions with immediat
+#  define MAX_OPCOD_1                              64            // Instruction ORFPX32/64                  
+#  define MAX_OPCOD_2                              256           // Instruction ORVDX64
+#  define MAX_OPCOD_3                              256           // Instructions Register-Register
+#  define MAX_OPCOD_4                              32            // Instructions "set flag" with register
+#  define MAX_OPCOD_5                              32            // Instructions "set flag" with immediat
+#  define MAX_OPCOD_6                              4             // Instruction Shift/Rotate with immediat
+#  define MAX_OPCOD_7                              16            // Instructions multiply with HI-LO
+#  define MAX_OPCOD_8                              2             // Instructions acces at HI-LO 
+#  define MAX_OPCOD_9                              8             // Instructions special	
+#  define MAX_OPCOD_10                             4             // Instructions no operation
+#  define MAX_OPCOD_11                             4             // Instruction Shift/Rotate with register
+#  define MAX_OPCOD_12                             4             // Instructions extend
+#  define MAX_OPCOD_13                             4             // Instructions extend (64b)
+
+// OPCOD_0                                         - [31:26]      Instructions with immediat
+#  define OPCOD_L_J                                0x00          // 000_000
+#  define OPCOD_L_JAL                              0x01          // 000_001
+#  define OPCOD_L_BNF                              0x03          // 000_011
+#  define OPCOD_L_BF                               0x04          // 000_100
+#  define OPCOD_L_RFE                              0x09          // 001_001
+#  define OPCOD_L_JR                               0x11          // 010_001
+#  define OPCOD_L_JALR                             0x12          // 010_010
+#  define OPCOD_L_MACI                             0x13          // 010_011
+#  define OPCOD_L_CUST1                            0x1c          // 011_100
+#  define OPCOD_L_CUST2                            0x1d          // 011_101
+#  define OPCOD_L_CUST3                            0x1e          // 011_110
+#  define OPCOD_L_CUST4                            0x1f          // 011_111
+#  define OPCOD_L_CUST5                            0x3c          // 111_100
+#  define OPCOD_L_CUST6                            0x3d          // 111_101
+#  define OPCOD_L_CUST7                            0x3e          // 111_110
+#  define OPCOD_L_CUST8                            0x3f          // 111_111
+#  define OPCOD_L_LD                               0x20          // 100_000
+#  define OPCOD_L_LWZ                              0x21          // 100_001
+#  define OPCOD_L_LWS                              0x22          // 100_010
+#  define OPCOD_L_LBZ                              0x23          // 100_011
+#  define OPCOD_L_LBS                              0x24          // 100_100
+#  define OPCOD_L_LHZ                              0x25          // 100_101
+#  define OPCOD_L_LHS                              0x26          // 100_110
+#  define OPCOD_L_ADDI                             0x27          // 100_111
+#  define OPCOD_L_ADDIC                            0x28          // 101_000
+#  define OPCOD_L_ANDI                             0x29          // 101_001
+#  define OPCOD_L_ORI                              0x2a          // 101_010
+#  define OPCOD_L_XORI                             0x2b          // 101_011
+#  define OPCOD_L_MULI                             0x2c          // 101_100
+#  define OPCOD_L_MFSPR                            0x2d          // 101_101
+#  define OPCOD_L_MTSPR                            0x30          // 110_000
+#  define OPCOD_L_SD                               0x34          // 110_100
+#  define OPCOD_L_SW                               0x35          // 110_101
+#  define OPCOD_L_SB                               0x36          // 110_110
+#  define OPCOD_L_SH                               0x37          // 110_111
+				                   
+#  define OPCOD_1                                  0x33          // 110_011         // Instruction ORFPX32/64
+#  define OPCOD_2                                  0x0a          // 001_010         // Instruction ORVDX64
+#  define OPCOD_3                                  0x38          // 111_000         // Instructions Register-Register
+#  define OPCOD_4                                  0x39          // 111_001         // Instructions "set flag" with register
+#  define OPCOD_5                                  0x2f          // 101_111         // Instructions "set flag" with immediat
+#  define OPCOD_6                                  0x2e          // 101_110         // Instruction Shift/Rotate with immediat
+#  define OPCOD_7                                  0x31          // 110_001         // Instructions multiply with HI-LO
+#  define OPCOD_8                                  0x06          // 000_110         // Instructions acces at HI-LO 
+#  define OPCOD_9                                  0x08          // 001_000         // Instructions special
+#  define OPCOD_10                                 0x05          // 000_101         // Instructions no operation
+				                   
+// OPCOD_3         instructions                    - [9:8] [3:0]  Instructions Register-Register
+#  define OPCOD_L_ADD                              0x00          // 00_0000
+#  define OPCOD_L_ADDC                             0x01          // 00_0001
+#  define OPCOD_L_SUB                              0x02          // 00_0010
+#  define OPCOD_L_AND                              0x03          // 00_0011
+#  define OPCOD_L_OR                               0x04          // 00_0100
+#  define OPCOD_L_XOR                              0x05          // 00_0101
+#  define OPCOD_L_CMOV                             0x0e          // 00_1110
+#  define OPCOD_L_FF1                              0x0f          // 00_1111
+#  define OPCOD_L_FL1                              0x1f          // 01_1111
+#  define OPCOD_L_MUL                              0x36          // 11_0110
+#  define OPCOD_L_DIV                              0x39          // 11_1001
+#  define OPCOD_L_DIVU                             0x3a          // 11_1010
+#  define OPCOD_L_MULU                             0x3b          // 11_1011
+				                   
+#  define OPCOD_11                                 0x8           // 1000          // Instruction Shift/Rotate with register
+#  define OPCOD_12                                 0xc           // 1100          // Instructions extend
+#  define OPCOD_13                                 0xd           // 1101          // Instructions extend (64b)
+				                   
+// OPCOD_4         instructions                    - [25:21]      Instructions "set flag" with register
+#  define OPCOD_L_SFEQ                             0x00          // 00000
+#  define OPCOD_L_SFNE                             0x01          // 00001
+#  define OPCOD_L_SFGTU                            0x02          // 00010
+#  define OPCOD_L_SFGEU                            0x03          // 00011
+#  define OPCOD_L_SFLTU                            0x04          // 00100
+#  define OPCOD_L_SFLEU                            0x05          // 00101
+#  define OPCOD_L_SFGTS                            0x0a          // 01010
+#  define OPCOD_L_SFGES                            0x0b          // 01011
+#  define OPCOD_L_SFLTS                            0x0c          // 01100
+#  define OPCOD_L_SFLES                            0x0d          // 01101
+				                   
+// OPCOD_5         instructions                    - [25:21]      Instructions "set flag" with immediat
+#  define OPCOD_L_SFEQI                            0x00          // 00000
+#  define OPCOD_L_SFNEI                            0x01          // 00001
+#  define OPCOD_L_SFGTUI                           0x02          // 00010
+#  define OPCOD_L_SFGEUI                           0x03          // 00011
+#  define OPCOD_L_SFLTUI                           0x04          // 00100
+#  define OPCOD_L_SFLEUI                           0x05          // 00101
+#  define OPCOD_L_SFGTSI                           0x0a          // 01010
+#  define OPCOD_L_SFGESI                           0x0b          // 01011
+#  define OPCOD_L_SFLTSI                           0x0c          // 01100
+#  define OPCOD_L_SFLESI                           0x0d          // 01101
+				                   
+// OPCOD_6         instructions                    - [7:6]        Instruction Shift/Rotate with immediat
+#  define OPCOD_L_SLLI                             0x0           // 00
+#  define OPCOD_L_SRLI                             0x1           // 01
+#  define OPCOD_L_SRAI                             0x2           // 10
+#  define OPCOD_L_RORI                             0x3           // 11
+				                   
+// OPCOD_7         instructions                    - [3:0]        Instructions multiply with HI-LO
+#  define OPCOD_L_MAC                              0x1           // 0001
+#  define OPCOD_L_MSB                              0x2           // 0010
+				                   
+// OPCOD_8         instructions                    - [17]         Instructions acces at HI-LO 
+#  define OPCOD_L_MOVHI                            0x0           // 0
+#  define OPCOD_L_MACRC                            0x1           // 1
+
+// OPCOD_9         instructions                    - [25:23]      Instruction special
+#  define OPCOD_L_SYS                              0x0           // 000
+#  define OPCOD_L_TRAP                             0x2           // 010
+#  define OPCOD_L_MSYNC                            0x4           // 100
+#  define OPCOD_L_PSYNC                            0x5           // 101
+#  define OPCOD_L_CSYNC                            0x6           // 110
+
+// OPCOD_10        instructions                    - [25:24]      Instruction no operation
+#  define OPCOD_L_NOP                              0x1           // 01
+				                   
+// OPCOD_11        instructions                    - [7:6]        Instruction Shift/Rotate with register
+#  define OPCOD_L_SLL                              0x0           // 00
+#  define OPCOD_L_SRL                              0x1           // 01
+#  define OPCOD_L_SRA                              0x2           // 10
+#  define OPCOD_L_ROR                              0x3           // 11
+				                   
+// OPCOD_12        instructions                    - [9:6]          Instructions extend
+#  define OPCOD_L_EXTHS                            0x0           // 0000
+#  define OPCOD_L_EXTHZ                            0x2           // 0010
+#  define OPCOD_L_EXTBS                            0x1           // 0001
+#  define OPCOD_L_EXTBZ                            0x3           // 0011
+				                   
+// OPCOD_13        instructions                    - [9:6]        Instructions extend (64b)
+#  define OPCOD_L_EXTWS                            0x0           // 0000
+#  define OPCOD_L_EXTWZ                            0x1           // 0001
+
   /*
-#define                 _size_instruction             32
-#define                 _size_instruction_log2        5
-
-  //----------------------------------------------------[ Operation ]-----
-// #define                 _nb_operation                 32
-// #define                 _size_operation               5
-
-#define                 _operation_none               0x0
-#define                 _operation_l_adds             0x1
-#define                 _operation_l_addu             0x2
-#define                 _operation_l_subs             0x3
-#define                 _operation_l_and              0x4
-#define                 _operation_l_or               0x5
-#define                 _operation_l_xor              0x6
-#define                 _operation_l_cmove            0x7
-#define                 _operation_l_read_imm         0x8
-#define                 _operation_l_movhi            0x9
-#define                 _operation_l_muls             0xa
-#define                 _operation_l_mulu             0xb
-#define                 _operation_l_divs             0xc
-#define                 _operation_l_divu             0xd
-#define                 _operation_l_exts             0xe
-#define                 _operation_l_extz             0xf
-#define                 _operation_l_ff1              0x10
-#define                 _operation_l_fl1              0x11
-#define                 _operation_l_sll              0x12
-#define                 _operation_l_sla              0x13
-#define                 _operation_l_srl              0x14
-#define                 _operation_l_ror              0x15
-#define                 _operation_l_cmp_eq           0x16
-#define                 _operation_l_cmp_ne           0x17
-#define                 _operation_l_cmp_ges          0x18
-#define                 _operation_l_cmp_geu          0x19
-#define                 _operation_l_cmp_gts          0x1a
-#define                 _operation_l_cmp_gtu          0x1b
-#define                 _operation_l_cmp_les          0x1c
-#define                 _operation_l_cmp_leu          0x1d
-#define                 _operation_l_cmp_lts          0x1e
-#define                 _operation_l_cmp_ltu          0x1f
 
   //--------------------------------------------------[ destination ]-----
@@ -466,9 +906,4 @@
 #define                 mask_CONDITION_STACK          0x8           // Branch with pop  in stack pointer
 
-  //-------------------------------------------------[ branch_state ]-----
-#define                 cst_BRANCH_STATE_NONE         0x0           // 0 0
-#define                 cst_BRANCH_STATE_NSPEC_TAKE   0x1           // 0 1  -> incondionnal
-#define                 cst_BRANCH_STATE_SPEC_NTAKE   0x2           // 1 0
-#define                 cst_BRANCH_STATE_SPEC_TAKE    0x3           // 1 1
   */
 
@@ -620,213 +1055,4 @@
 
   /*
-//----------------------------------------------------
-// Code Operation (before decode)
-//----------------------------------------------------
-
-// Codop                        - [31:26]      Instructions with immediat
-#define OPCOD_L_J             0x00          // 000_000
-#define OPCOD_L_JAL           0x01          // 000_001
-#define OPCOD_L_BNF           0x03          // 000_011
-#define OPCOD_L_BF            0x04          // 000_100
-#define OPCOD_L_RFE           0x09          // 001_001
-#define OPCOD_L_JR            0x11          // 010_001
-#define OPCOD_L_JALR          0x12          // 010_010
-#define OPCOD_L_MACI          0x13          // 010_011
-#define OPCOD_L_CUST1         0x1c          // 011_100
-#define OPCOD_L_CUST2         0x1d          // 011_101
-#define OPCOD_L_CUST3         0x1e          // 011_110
-#define OPCOD_L_CUST4         0x1f          // 011_111
-#define OPCOD_L_CUST5         0x3c          // 111_100
-#define OPCOD_L_CUST6         0x3d          // 111_101
-#define OPCOD_L_CUST7         0x3e          // 111_110
-#define OPCOD_L_CUST8         0x3f          // 111_111
-#define OPCOD_L_LD            0x20          // 100_000
-#define OPCOD_L_LWZ           0x21          // 100_001
-#define OPCOD_L_LWS           0x22          // 100_010
-#define OPCOD_L_LBZ           0x23          // 100_011
-#define OPCOD_L_LBS           0x24          // 100_100
-#define OPCOD_L_LHZ           0x25          // 100_101
-#define OPCOD_L_LHS           0x26          // 100_110
-#define OPCOD_L_ADDI          0x27          // 100_111
-#define OPCOD_L_ADDIC         0x28          // 101_000
-#define OPCOD_L_ANDI          0x29          // 101_001
-#define OPCOD_L_ORI           0x2a          // 101_010
-#define OPCOD_L_XORI          0x2b          // 101_011
-#define OPCOD_L_MULI          0x2c          // 101_100
-#define OPCOD_L_MFSPR         0x2d          // 101_101
-#define OPCOD_L_MTSPR         0x30          // 110_000
-#define OPCOD_L_SD            0x32          // 110_010
-#define OPCOD_L_SW            0x35          // 110_101
-#define OPCOD_L_SB            0x36          // 110_110
-#define OPCOD_L_SH            0x37          // 110_111
-
-#define OPCOD_INST_LV         0x0a          // 001_010         // Instruction ORVDX64
-#define OPCOD_INST_LF         0x33          // 110_011         // Instruction ORFPX32/64
-
-#define OPCOD_SPECIAL         0x38          // 111_000         // Instructions Register-Register
-#define OPCOD_SPECIAL_1       0x39          // 111_001         // Instructions "set flag" with register
-#define OPCOD_SPECIAL_2       0x2f          // 101_111         // Instructions "set flag" with immediat
-#define OPCOD_SPECIAL_6       0x2e          // 101_110         // Instruction Shift/Rotate with immediat
-#define OPCOD_SPECIAL_7       0x31          // 110_001         // Instructions multiply with HI-LO
-#define OPCOD_SPECIAL_8       0x06          // 000_110         // Instructions acces at HI-LO 
-
-// OPCOD_SPECIAL   instructions - [9:8] [3:0]  Instructions Register-Register
-#define OPCOD_L_ADD           0x00          // 00_0000
-#define OPCOD_L_ADDC          0x01          // 00_0001
-#define OPCOD_L_SUB           0x02          // 00_0010
-#define OPCOD_L_AND           0x03          // 00_0011
-#define OPCOD_L_OR            0x04          // 00_0100
-#define OPCOD_L_XOR           0x05          // 00_0101
-#define OPCOD_L_CMOV          0x0e          // 00_1110
-#define OPCOD_L_FF1           0x0f          // 00_1111
-#define OPCOD_L_FL1           0x1f          // 01_1111
-#define OPCOD_L_MUL           0x36          // 11_0110
-#define OPCOD_L_DIV           0x39          // 11_1001
-#define OPCOD_L_DIVU          0x3a          // 11_1010
-#define OPCOD_L_MULU          0x3b          // 11_1011
-
-#define OPCOD_SPECIAL_3       0xc           // 1100          // Instructions extend
-#define OPCOD_SPECIAL_4       0xd           // 1101          // Instructions extend (64b)
-#define OPCOD_SPECIAL_5       0x8           // 1000          // Instruction Shift/Rotate with register
-
-// OPCOD_SPECIAL_1 instructions - [25:21]      Instructions "set flag" with register
-#define OPCOD_L_SFEQ          0x00          // 00000
-#define OPCOD_L_SFNE          0x01          // 00001
-#define OPCOD_L_SFGTU         0x02          // 00010
-#define OPCOD_L_SFGEU         0x03          // 00011
-#define OPCOD_L_SFLTU         0x04          // 00100
-#define OPCOD_L_SFLEU         0x05          // 00101
-#define OPCOD_L_SFGTS         0x0a          // 01010
-#define OPCOD_L_SFGES         0x0b          // 01011
-#define OPCOD_L_SFLTS         0x0c          // 01100
-#define OPCOD_L_SFLES         0x0d          // 01101
-
-// OPCOD_SPECIAL_2 instructions - [25:21]      Instructions "set flag" with immediat
-#define OPCOD_L_SFEQI         0x00          // 00000
-#define OPCOD_L_SFNEI         0x01          // 00001
-#define OPCOD_L_SFGTUI        0x02          // 00010
-#define OPCOD_L_SFGEUI        0x03          // 00011
-#define OPCOD_L_SFLTUI        0x04          // 00100
-#define OPCOD_L_SFLEUI        0x05          // 00101
-#define OPCOD_L_SFGTSI        0x0a          // 01010
-#define OPCOD_L_SFGESI        0x0b          // 01011
-#define OPCOD_L_SFLTSI        0x0c          // 01100
-#define OPCOD_L_SFLESI        0x0d          // 01101
-
-// OPCOD_SPECIAL_3 instructions - [9:6]          Instructions extend
-#define OPCOD_L_EXTHS         0x0           // 0000
-#define OPCOD_L_EXTHZ         0x2           // 0010
-#define OPCOD_L_EXTBS         0x1           // 0001
-#define OPCOD_L_EXTBZ         0x3           // 0011
-
-// OPCOD_SPECIAL_4 instructions - [9:6]        Instructions extend (64b)
-#define OPCOD_L_EXTWS         0x0           // 0000
-#define OPCOD_L_EXTWZ         0x1           // 0001
-
-// OPCOD_SPECIAL_5 instructions - [7:6]        Instruction Shift/Rotate with register
-#define OPCOD_L_SLL           0x0           // 00
-#define OPCOD_L_SRL           0x1           // 01
-#define OPCOD_L_SRA           0x2           // 10
-#define OPCOD_L_ROR           0x3           // 11
-
-// OPCOD_SPECIAL_6 instructions - [7:6]        Instruction Shift/Rotate with immediat
-#define OPCOD_L_SLLI          0x0           // 00
-#define OPCOD_L_SRLI          0x1           // 01
-#define OPCOD_L_SRAI          0x2           // 10
-#define OPCOD_L_RORI          0x3           // 11
-
-// OPCOD_SPECIAL_7 instructions - [3:0]        Instructions multiply with HI-LO
-#define OPCOD_L_MAC           0x1           // 0001
-#define OPCOD_L_MSB           0x2           // 0010
-
-// OPCOD_SPECIAL_8 instructions - [17]         Instructions acces at HI-LO 
-#define OPCOD_L_MOVHI         0x0           // 0
-#define OPCOD_L_MACRC         0x1           // 1
-
-// Particular case                             Instructions systems
-#define OPCOD_L_MSYNC         0x22000000
-#define OPCOD_L_CSYNC         0x23000000
-#define OPCOD_L_PSYNC         0x22800000
-#define OPCOD_L_NOP           0x1500
-#define OPCOD_L_SYS           0x2000
-#define OPCOD_L_TRAP          0x2100
-
-//----------------------------------------------------
-// Code Operation (after decode)
-//----------------------------------------------------
-
-typedef enum
-  {
-    // ##### WARNING : This opcode must be the first#####
-    INST_L_NO_IMPLEMENTED ,         // Operation is not implemented
-
-    INST_L_ADD            ,         // L.ADD    , L.ADDI   , L.ADDC   , L.ADDIC
-    INST_L_AND            ,         // L.AND    , L.ANDI
-    INST_L_OR             ,         // L.OR     , L.ORI
-    INST_L_XOR            ,         // L.XOR    , L.XORI
-    INST_L_CMOV           ,         // L.CMOV
-    INST_L_SUB            ,         // L.SUB
-    INST_L_FF1            ,         // L.FF1
-    INST_L_EXTBS          ,         // L.EXTBS
-    INST_L_EXTBZ          ,         // L.EXTBZ
-    INST_L_EXTHS          ,         // L.EXTHS
-    INST_L_EXTHZ          ,         // L.EXTHZ
-    INST_L_EXTWS          ,         // L.EXTWS
-    INST_L_EXTWZ          ,         // L.EXTWZ
-    INST_L_e              ,         // 
-    INST_L_f              ,         // 
-    INST_L_MUL            ,         // L.MUL    , L.MULI
-    INST_L_MULU           ,         // L.MULU
-    INST_L_DIV            ,         // L.DIV
-    INST_L_DIVU           ,         // L.DIVU
-    INST_L_SLL            ,         // L.SLL    , L.SLLI
-    INST_L_SRL            ,         // L.SRL    , L.SRLI 
-    INST_L_SRA            ,         // L.SRA    , L.SRAI
-    INST_L_ROR            ,         // L.ROR    , L.RORI
-    INST_L_SFGES          ,         // L.SFGES  , L.SFGESI
-    INST_L_SFGEU          ,         // L.SFGEU  , L.SFGEUI
-    INST_L_SFGTS          ,         // L.SFGTS  , L.SFGTSI
-    INST_L_SFGTU          ,         // L.SFGTU  , L.SFGTUI
-    INST_L_SFLES          ,         // L.SFLES  , L.SFLESI
-    INST_L_SFLEU          ,         // L.SFLEU  , L.SFLEUI
-    INST_L_SFLTS          ,         // L.SFLTS  , L.SFLTSI
-    INST_L_SFLTU          ,         // L.SFLTU  , L.SFLTUI
-    INST_L_SFEQ           ,         // L.SFEQ   , L.SFEQI
-    INST_L_SFNE           ,         // L.SFNE   , L.SFNEI
-    INST_L_READ           ,         // L.BNF    , L.BF     , L.JR
-    INST_L_MOVHI          ,         // L.MOVI
-    INST_L_CSYNC          ,         // L.CSYNC
-    INST_L_MSYNC          ,         // L.MSYNC
-    INST_L_PSYNC          ,         // L.PSYNC
-    INST_L_RFE            ,         // L.RFE
-    INST_L_MAC            ,         // L.MAC    , L.MACI
-    INST_L_MSB            ,         // L.MSB
-    INST_L_MACRC          ,         // L.MACRC
-    INST_L_2b             ,         //
-    INST_L_MEMB           ,         // L.LBS    , L.LBZ    , L.SB  
-    INST_L_MEMH           ,         // L.LHS    , L.LHZ    , L.SH 
-    INST_L_MEMW           ,         // L.LWS    , L.LWZ    , L.SW  
-    INST_L_MEMD           ,         // L.LD                , L.SD  
-    INST_L_CUST1          ,         // L.CUST1
-    INST_L_CUST2          ,         // L.CUST2
-    INST_L_CUST3          ,         // L.CUST3
-    INST_L_CUST4          ,         // L.CUST4
-    INST_L_CUST5          ,         // L.CUST5
-    INST_L_CUST6          ,         // L.CUST6 
-    INST_L_CUST7          ,         // L.CUST7
-    INST_L_CUST8          ,         // L.CUST8
-    INST_L_38             ,         //
-    INST_L_39             ,         //
-    INST_L_3a             ,         //
-    INST_L_3b             ,         //
-    INST_L_3c             ,         //  
-    INST_L_3d             ,         //  
-    INST_L_3e             ,         //  
-    INST_NOP                        // L.NOP
-  } opcod_t;
-
-#define LOG2_NB_INST_L        6
-#define      NB_INST_L        64 // +1 -> INST_L_NO_IMPLEMENTED
-//#define      NB_INST_L        (INST_L_NO_IMPLEMENTED+1)
   */
 
