Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-free_list.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-free_list.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-free_list.fig	(revision 78)
@@ -0,0 +1,149 @@
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative.fig	(revision 78)
@@ -0,0 +1,101 @@
+#FIG 3.2  Produced by xfig version 3.2.5
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative_bypass.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative_bypass.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-commit_speculative_bypass.fig	(revision 78)
@@ -0,0 +1,120 @@
+#FIG 3.2  Produced by xfig version 3.2.5
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-load_speculative.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-load_speculative.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-load_speculative.fig	(revision 78)
@@ -0,0 +1,98 @@
+#FIG 3.2  Produced by xfig version 3.2.5
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-ooo.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-ooo.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_component-load_store_queue-ooo.fig	(revision 78)
@@ -0,0 +1,85 @@
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080225.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080225.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080225.fig	(revision 78)
@@ -0,0 +1,176 @@
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Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080327.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080327.fig	(revision 78)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview-20080327.fig	(revision 78)
@@ -0,0 +1,172 @@
+#FIG 3.2  Produced by xfig version 3.2.5
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+2 4 0 1 0 1 50 -1 20 4.000 0 0 7 0 0 5
+	 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870
+2 4 0 1 0 1 50 -1 20 3.000 0 0 7 0 0 5
+	 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510
+2 4 0 0 0 1 49 -1 20 2.000 0 0 7 0 0 5
+	 5490 4140 5490 3690 5130 3690 5130 4140 5490 4140
+2 4 0 1 0 7 50 -1 20 4.000 0 0 7 0 0 5
+	 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140
+2 4 0 1 0 7 50 -1 20 4.000 0 0 7 0 0 5
+	 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510
+2 4 0 0 0 4 49 -1 20 2.000 0 0 7 0 0 5
+	 4230 3060 4230 3510 4590 3510 4590 3060 4230 3060
+2 4 0 1 0 1 50 -1 20 4.000 0 0 7 0 0 5
+	 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140
+2 4 0 1 0 1 50 -1 20 4.000 0 0 7 0 0 5
+	 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140
+4 1 0 50 -1 -1 12 0.0000 4 195 660 10170 4905 register\001
+4 1 0 50 -1 -1 12 1.5708 4 150 510 10935 3915 select\001
+4 1 0 50 -1 -1 12 1.5708 4 150 510 9495 3915 select\001
+4 0 1 50 -1 -1 12 0.0000 4 150 435 1710 2205 Core\001
+4 0 1 50 -1 -1 12 0.0000 4 150 855 2790 2790 Front End\001
+4 0 1 50 -1 -1 12 0.0000 4 195 1365 8190 3015 Execution Loop\001
+4 0 1 50 -1 -1 12 0.0000 4 195 1770 5760 2520 Out Of Order Engine\001
+4 1 0 50 -1 -1 12 1.5708 4 150 510 7875 3600 select\001
+4 1 0 50 -1 -1 12 0.0000 4 120 690 10170 4230 execute\001
+4 1 0 50 -1 -1 12 0.0000 4 150 720 10170 3690 memory\001
+4 0 0 50 -1 -1 12 0.0000 4 195 1575 2340 5310 SystemC + VHDL\001
+4 0 0 50 -1 -1 12 0.0000 4 195 795 2340 5040 SystemC\001
+4 1 0 48 -1 -1 12 0.0000 4 195 780 4230 3330 predictor\001
+4 1 0 48 -1 -1 12 0.0000 4 150 525 5130 3960 decod\001
+4 1 0 50 -1 -1 12 0.0000 4 150 435 3330 3960 fetch\001
+4 1 0 50 -1 -1 12 0.0000 4 105 660 6210 3960 rename\001
Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig	(revision 63)
+++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig	(revision 78)
@@ -1,3 +1,3 @@
-#FIG 3.2
+#FIG 3.2  Produced by xfig version 3.2.5
 Landscape
 Center
@@ -8,56 +8,41 @@
 -2
 1200 2
-6 4770 3690 5490 4140
-2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
-	 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140
-4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001
--6
 6 4770 3240 5490 3690
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690
-4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001
-4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001
--6
-6 5850 3690 6570 4140
-2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
-	 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140
-4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001
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 -6
 6 8370 3690 9090 4140
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140
-4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001
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 -6
 6 11250 3690 11970 4140
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140
-4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001
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 -6
 6 9810 2475 10530 2925
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925
-4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001
-4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001
--6
-6 6570 3015 7290 3465
-2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
-	 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465
-4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001
+4 1 0 50 -1 -1 12 0.0000 4 165 345 10170 2835 port\001
+4 1 0 50 -1 -1 12 0.0000 4 150 630 10170 2655 dcache\001
 -6
 6 3825 3060 4635 3510
 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
 	 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510
-4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001
+4 1 0 50 -1 -1 12 0.0000 4 195 780 4230 3330 predictor\001
 -6
 6 2970 3690 3690 4140
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140
-4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001
+4 1 0 50 -1 -1 12 0.0000 4 150 435 3330 3960 fetch\001
 -6
 6 1890 3690 2610 4140
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140
-4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001
-4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001
+4 1 0 50 -1 -1 12 0.0000 4 165 345 2250 4050 port\001
+4 1 0 50 -1 -1 12 0.0000 4 150 570 2250 3870 icache\001
 -6
 6 1800 4590 5265 5355
@@ -68,7 +53,17 @@
 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
 	 2160 5310 1800 5310 1800 5130 2160 5130 2160 5310
-4 0 0 50 -1 -1 12 0.0000 4 180 555 2340 4770 Groupe\001
-4 0 0 50 -1 -1 12 0.0000 4 180 2280 2340 5310 Une occurence dans le groupe\001
-4 0 0 50 -1 -1 12 0.0000 4 180 2760 2340 5040 Plusieurs occurences dans le groupe\001
+4 0 0 50 -1 -1 12 0.0000 4 195 660 2340 4770 Groupe\001
+4 0 0 50 -1 -1 12 0.0000 4 195 2610 2340 5310 Une occurence dans le groupe\001
+4 0 0 50 -1 -1 12 0.0000 4 195 3120 2340 5040 Plusieurs occurences dans le groupe\001
+-6
+6 6570 3015 7290 3465
+2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
+	 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465
+4 1 0 50 -1 -1 12 0.0000 4 150 645 6930 3285 commit\001
+-6
+6 4770 3690 5490 4140
+2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5
+	 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140
+4 1 0 50 -1 0 12 0.0000 4 150 525 5130 3960 decod\001
 -6
 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4
@@ -170,12 +165,15 @@
 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5
 	 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870
-4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001
-4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001
-4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001
-4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001
-4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001
-4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001
-4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001
-4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001
-4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001
-4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001
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