Changeset 81 for trunk/IPs/systemC/Environment
- Timestamp:
- Apr 15, 2008, 8:40:01 PM (17 years ago)
- Location:
- trunk/IPs/systemC/Environment
- Files:
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- 113 added
- 64 edited
- 2 moved
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trunk/IPs/systemC/Environment/Cache/Makefile
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r80 r81 5 5 #-----[ Variable ]----------------------------------------- 6 6 7 OBJECTS_DEPS = $(patsubst $(DIR_QUEUE)/ %.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_QUEUE)/*.cpp))7 OBJECTS_DEPS = $(patsubst $(DIR_QUEUE)/$(DIR_SRC)/%.cpp,$(DIR_QUEUE)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_QUEUE)/$(DIR_SRC)/*.cpp)) 8 8 9 9 #-----[ Rules ]-------------------------------------------- -
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trunk/IPs/systemC/Environment/Cache/include/Cache.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_MultiLevel.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_MultiLevel_Access.h
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r80 r81 17 17 public : Access () 18 18 { 19 this->num_port = 0; 20 this->hit = MISS; 21 this->latence = 0; 22 this->last_nb_level = 0; 19 23 } 20 24 -
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trunk/IPs/systemC/Environment/Cache/include/Cache_MultiLevel_Parameters.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel.h
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r80 r81 8 8 #include "Cache_OneLevel_Parameters.h" 9 9 #include "../../Queue/include/Sort_Queue_Dynamic.h" 10 #include "../../Common/include/Debug.h" 10 11 11 12 namespace environment { -
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel_Access_Port.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel_Address.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel_Parameters.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel_Tag.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel_Write_Buffer.h
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trunk/IPs/systemC/Environment/Cache/include/Cache_Parameters.h
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r80 r81 14 14 public : uint32_t nb_cache_dedicated; 15 15 public : uint32_t nb_iport; 16 public : uint32_t nb_dport; 16 17 17 18 public : cache_multilevel::Parameters ** param_icache_dedicated; … … 47 48 this->nb_cache_dedicated = nb_cache_dedicated; 48 49 50 if (nb_cache_dedicated == 0) 51 { 52 std::cerr << "[ ERROR ] nb_cache_dedicated > 0" << std::endl; 53 exit(0); 54 } 55 49 56 uint32_t cache_shared_nb_port = 0; 50 uint32_t nb_iport = 0; 57 nb_iport = 0; 58 nb_dport = 0; 59 51 60 for (uint32_t i=0; i<nb_cache_dedicated; i++) 52 61 { 53 62 nb_iport += icache_dedicated_nb_port [i]; 63 nb_dport += dcache_dedicated_nb_port [i]; 54 64 cache_shared_nb_port += icache_dedicated_nb_port [i]; 55 65 cache_shared_nb_port += dcache_dedicated_nb_port [i]; … … 108 118 { 109 119 std::string tab (depth,'\t'); 110 std::stringstream str ;120 std::stringstream str (""); 111 121 112 122 str << tab << "* Nb Cache dedicated : " << nb_cache_dedicated << std::endl 113 << tab << "* Nb iport : " << nb_iport << std::endl; 123 << tab << "* Nb iport : " << nb_iport << std::endl 124 << tab << "* Nb dport : " << nb_dport << std::endl 125 ; 114 126 115 127 for (uint32_t i=0; i<nb_cache_dedicated; i++) -
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trunk/IPs/systemC/Environment/Cache/include/Types.h
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trunk/IPs/systemC/Environment/Cache/selftest/main.cpp
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r80 r81 1 #include "../include/Cache.h" 1 2 #include <iostream> 2 #include "../include/Cache.h"3 3 4 4 using namespace std; … … 6 6 using namespace environment::cache; 7 7 8 #define TEST(x,y) \ 9 { \ 10 cout << "Line " << __LINE__ << " : "; \ 11 if (x==y) \ 12 { \ 13 cout << "Test OK" << endl; \ 14 } \ 15 else \ 16 { \ 17 cout << "Test KO" << endl; \ 18 exit (EXIT_FAILURE); \ 19 } \ 8 #define TEST(x,y) \ 9 { \ 10 if (x==y) \ 11 { \ 12 cout << "Line " << __LINE__ << " : " << "Test OK" << endl; \ 13 } \ 14 else \ 15 { \ 16 cout << "Line " << __LINE__ << " : " << "Test KO" << endl; \ 17 exit (EXIT_FAILURE); \ 18 } \ 20 19 } while (0) 21 20 22 21 23 22 24 int main (void) 23 #ifdef SYSTEMC 24 int sc_main (int argc, char * argv[]) 25 #else 26 int main (int argc, char * argv[]) 27 #endif 25 28 { 26 29 cout << "<main> Begin" << endl; … … 38 41 ); 39 42 40 cout << *param << endl;43 // cout << *param << endl; 41 44 42 45 cache_onelevel::Cache_OneLevel * cache = new cache_onelevel::Cache_OneLevel ("my_cache",param); 43 46 cache->reset(); 44 47 45 cout << *cache << endl;48 // cout << *cache << endl; 46 49 47 50 cache->transition(); 48 51 cache->transition(); 49 52 50 cout << *cache << endl;53 // cout << *cache << endl; 51 54 52 55 TEST(cache->access(0, 0x100, 0, CACHED, WRITE), MISS); … … 89 92 90 93 cache->transition(); // miss cycle 1 91 cout << *cache << endl;94 // cout << *cache << endl; 92 95 93 96 TEST(cache->access(0, 0x200, 0, CACHED, WRITE), MISS ); … … 99 102 cache->transition(); // miss cycle 2 100 103 cache->transition(); // miss cycle 3 101 cout << *cache << endl;104 // cout << *cache << endl; 102 105 103 106 // line 0 : all way is use … … 113 116 114 117 cache->transition(); 115 cout << *cache << endl;118 // cout << *cache << endl; 116 119 117 120 TEST(cache->access(0, 0x500, 0, CACHED, WRITE), MISS ); … … 141 144 TEST(cache->latence(3), 5); 142 145 143 cout << *cache << endl;146 // cout << *cache << endl; 144 147 145 148 delete cache; … … 174 177 ); 175 178 176 cout << *param << endl;179 // cout << *param << endl; 177 180 178 181 cache_multilevel::Cache_MultiLevel * cache = new cache_multilevel::Cache_MultiLevel ("my_cache",param); 179 182 180 cout << *cache << endl;181 183 cache->reset(); 182 cout << *cache << endl;184 // cout << *cache << endl; 183 185 184 186 cache_multilevel::Access access; … … 202 204 cache->transition(); //11 203 205 cache->transition(); //10 204 cout << *cache << endl;206 // cout << *cache << endl; 205 207 206 208 access = cache->access (0, 0x100, 0, CACHED, WRITE); … … 238 240 TEST(access.latence , 1); 239 241 TEST(access.last_nb_level, 0); 240 cout << *cache << endl;242 // cout << *cache << endl; 241 243 242 244 cache->transition(); … … 303 305 cache->transition(); //11 304 306 cache->transition(); //10 305 cout << *cache << endl;307 // cout << *cache << endl; 306 308 307 309 access = cache->access (0, 0x100, 0, CACHED, WRITE); … … 358 360 359 361 access = cache->access (1, 0x100, 0, CACHED, WRITE); 360 cout << access<< endl;362 // cout << access<< endl; 361 363 362 364 cache->update_access(access); … … 367 369 TEST(access.last_nb_level, 1); 368 370 369 cout << *cache << endl;371 // cout << *cache << endl; 370 372 delete cache; 371 373 delete param; … … 389 391 cache_shared_size_line [0] = 8 ; 390 392 cache_shared_size_word [0] = 4 ; 391 cache_shared_associativity [0] = 4;393 cache_shared_associativity [0] = 8 ; 392 394 cache_shared_hit_latence [0] = 2 ; 393 395 cache_shared_miss_penality [0] = 5 ; … … 467 469 468 470 dcache_nb_level [1] = 2; 469 dcache_nb_port [1] = 2;471 dcache_nb_port [1] = 8; // to test 470 472 dcache_nb_line [1] = new uint32_t [2]; 471 473 dcache_size_line [1] = new uint32_t [2]; … … 519 521 ); 520 522 521 cout << *param << endl;523 // cout << *param << endl; 522 524 523 525 cache::Cache * cache = new cache::Cache ("my_cache",param); 524 526 527 cache->reset(); 528 // cout << *cache << endl; 529 530 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16); 531 cache->transition(); 532 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15); 533 cache->transition(); 534 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 14); 535 cache->transition(); 536 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 13); 537 cache->transition(); 538 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 12); 539 cache->transition(); 540 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11); 541 cache->transition(); 542 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10); 543 cache->transition(); 544 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 9); 545 cache->transition(); 546 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 8); 547 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 16); // miss thread != 548 TEST(cache->latence (DATA_CACHE, 0, 0, 0x100, 0, CACHED, WRITE), 6); // miss L1, hit L2 549 cache->transition(); 550 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 7); 551 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 15); 552 cache->transition(); 553 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 6); 554 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 14); 555 cache->transition(); 556 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); 557 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 13); 558 cache->transition(); 559 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); 560 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 12); 561 cache->transition(); 562 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); 563 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 11); 564 cache->transition(); 565 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); 566 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 10); 567 cache->transition(); 568 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 569 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 9); 570 cache->transition(); 571 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 572 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 8); 573 cache->transition(); 574 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 575 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 7); 576 cache->transition(); 577 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 578 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 6); 579 cache->transition(); 580 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 581 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); 582 cache->transition(); 583 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 584 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); 585 cache->transition(); 586 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 587 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); 588 cache->transition(); 589 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 590 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); 591 cache->transition(); 592 593 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); // L1 is direct map, hit L2 594 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); // write in L1 595 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 16); 596 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 16); 597 cache->transition(); 598 599 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); 600 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 601 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 15); 602 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 15); 603 cache->transition(); 604 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); 605 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 606 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 14); 607 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 14); 608 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 16); 609 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 16); 610 cache->transition(); 611 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); 612 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 613 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 13); 614 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 13); 615 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 15); 616 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 15); 617 618 619 cache->transition(); 620 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 621 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); 622 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 12); 623 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 12); 624 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 14); 625 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 14); 626 627 628 cache->transition(); 629 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 630 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); 631 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 11); 632 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11); 633 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 13); 634 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 13); 635 636 // in cache L2 : context 0,1,2,3 637 638 cache->transition(); 639 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 640 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); 641 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 10); 642 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10); 643 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 12); 644 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 12); 645 646 cache->transition(); 647 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 648 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); 649 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 9); 650 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 9); 651 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 11); 652 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 11); 653 654 cache->transition(); 655 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); 656 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 657 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 8); 658 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 8); 659 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 10); // write in L2 660 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 10); // write in L2 661 662 cache->transition(); 663 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); 664 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 665 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 7); 666 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 7); 667 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 9); 668 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 9); 669 670 cache->transition(); 671 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); 672 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 673 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 6); 674 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 6); 675 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 8); 676 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 8); 677 678 cache->transition(); 679 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); 680 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 681 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 5); 682 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 5); 683 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 7); 684 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 7); 685 686 cache->transition(); 687 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 688 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); 689 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 4); 690 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 4); 691 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 6); 692 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 6); 693 694 cache->transition(); 695 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 696 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); 697 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 3); 698 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 3); 699 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 5); 700 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 5); 701 702 cache->transition(); 703 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); 704 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); 705 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 2); 706 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 2); 707 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 4); 708 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 4); 709 525 710 cout << *cache << endl; 526 cache->reset(); 527 cout << *cache << endl; 528 529 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16); 530 cache->transition(); 531 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15); 532 cache->transition(); 533 534 cout << *cache << endl; 535 711 712 cache->transition(); 713 // In L2 : context 1,2,4,5 : also context 0 and 3 miss L1 and L2, hit L3 714 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11); 715 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); 716 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 1); 717 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11); 718 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 3); 719 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 3); 720 721 cache->transition(); 722 TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10); 723 TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); 724 TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 5); 725 TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10); 726 TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 2); 727 TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 2); 728 729 // // cout << *cache << endl; 536 730 537 731 delete cache; 732 538 733 delete param; 539 734 delete [] cache_shared_nb_line ; -
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trunk/IPs/systemC/Environment/Cache/src/Cache.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_access.cpp
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r80 r81 16 16 { 17 17 hit = hierarchy_cache[i]->access (num_port,address,trdid,type,dir); 18 time += hierarchy_cache[i]->latence(num_port); 18 uint32_t latence = hierarchy_cache[i]->latence(num_port); 19 time += latence; 19 20 20 std::cout << "SETH : " 21 << " * i : " << i 22 << " * hit : " << hit 23 << " * time :" << time << std::endl; 24 21 _cout(CACHE," * Level [%d] - type_hit %d, latence %d, Sum latence %d\n",i,hit,latence,time); 22 25 23 if ( (hit == HIT_CACHE) or 26 24 (hit == HIT_WRITE_BUFFER) or -
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_information.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_latence.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_print.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_reset.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_update_access.cpp
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r80 r81 8 8 uint32_t Cache_MultiLevel::update_access (Access cur_access) 9 9 { 10 if (cur_access.last_nb_level > 0)10 // if (cur_access.last_nb_level > 0) 11 11 { 12 12 uint32_t latence = cur_access.latence; 13 14 _cout(CACHE,"Cache_MultiLevel::update_access [%d] : latence : %d, last_nb_level : %d (nb_level : %d)\n",cur_access.num_port,latence,cur_access.last_nb_level,param->nb_level); 13 15 14 for (uint32_t it = 0; it <= cur_access.last_nb_level; it ++) 15 latence = hierarchy_cache [it]->update_latence (cur_access.num_port,latence); 16 16 for (uint32_t it = 0; it < cur_access.last_nb_level; it ++) 17 { 18 latence = hierarchy_cache [it]->update_latence (cur_access.num_port,latence); 19 } 17 20 // if (latence != 0) 18 21 // { -
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_cached.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_access_flush.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_hit_access_port.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_latence.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_transition.cpp
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r80 r81 34 34 35 35 // Test if a write_buffer have the result 36 while ((write_buffer->empty() == false) && (write_buffer->read(0)._delay == 0)) 36 while ((write_buffer->empty() == false) and 37 (write_buffer->read(0)._delay == 0)) 37 38 { 38 39 // Save in the cache 39 Write_Buffer val 40 Write_Buffer val = write_buffer->pop(); 40 41 41 uint32_t num_tag = val.address.tag;42 uint32_t num_familly = val.address.familly;42 uint32_t num_tag = val.address.tag; 43 uint32_t num_familly = val.address.familly; 43 44 uint32_t num_associativity = index_victim(num_familly); 44 45 -
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_translate_address.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_update_latence.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_information.cpp
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trunk/IPs/systemC/Environment/Cache/src/Cache_latence.cpp
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r80 r81 22 22 23 23 cache_multilevel::Cache_MultiLevel * cache; 24 cache_multilevel::Parameters * param_cache_dedicated; 25 _cout(CACHE," * Access Cache_Dedicated_"); 24 26 if (type_cache == INSTRUCTION_CACHE) 25 cache = icache_dedicated [num_entity]; 27 { 28 _cout(CACHE,"Instruction"); 29 cache = icache_dedicated [num_entity]; 30 param_cache_dedicated = param->param_icache_dedicated [num_entity]; 31 } 26 32 else 27 cache = dcache_dedicated [num_entity]; 33 { 34 _cout(CACHE,"Data"); 35 cache = dcache_dedicated [num_entity]; 36 param_cache_dedicated = param->param_dcache_dedicated [num_entity]; 37 } 38 _cout(CACHE," [%d] - entity : %d, address : 0x%.x\n",num_port,num_entity,address); 28 39 29 40 if (num_port >= cache->param->nb_port) … … 34 45 35 46 // Make a access with this level "dedicated" 36 std::cout << "cache dedicated : access" << std::endl;37 47 cache_multilevel::Access access_dedicated = cache->access(num_port,address,trdid,type,dir); 38 48 39 49 if (access_dedicated.hit == MISS) 40 50 { 41 std::cout << "cache shared : access" << std::endl; 51 _cout(CACHE," * Access Cache_shared"); 52 42 53 // Make a access with this level "shared" 43 54 cache_multilevel::Access access_shared = cache_shared->access(range_port (type_cache,num_entity)+num_port,address,trdid,type,dir); … … 45 56 cache_shared->update_access (access_shared); 46 57 47 access_dedicated.last_nb_level = param ->nb_cache_dedicated-1; // Update all cache58 access_dedicated.last_nb_level = param_cache_dedicated->nb_level; // Update all cache 48 59 access_dedicated.latence += access_shared.latence; 49 60 } 50 61 51 std::cout << "end access, update access" << std::endl;52 53 62 cache->update_access (access_dedicated); 54 63 55 std::cout << "end access, update access" << std::endl; 56 64 _cout(CACHE,"Access latence : %d\n",access_dedicated.latence); 57 65 return access_dedicated.latence; 58 66 } -
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r80 r81 16 16 else 17 17 { 18 std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;18 // std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl; 19 19 nb_port_dedicated += param->nb_iport; 20 std::cout << "nb_port_dedicated : " << param->nb_iport<< std::endl;20 // std::cout << "nb_port_dedicated : " << param->nb_iport<< std::endl; 21 21 22 22 for (uint32_t i = 1; i < num_entity; i++) … … 24 24 } 25 25 26 std::cout << "nb_port_dedicated : " << num_entity << std::endl;27 std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;26 // std::cout << "nb_port_dedicated : " << num_entity << std::endl; 27 // std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl; 28 28 29 29 return nb_port_dedicated; -
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r80 r81 1 1 include $(MORPHEO_TOPLEVEL)/Makefile.tools 2 include $(MORPHEO_IPS)/processor/Morpheo/Behavioural/Makefile.flags 2 3 3 4 #-----[ Directory ]---------------------------------------- … … 10 11 #-----[ Compilation ]-------------------------------------- 11 12 INCDIR = $(SYSTEMC_INCDIR_$(SIMULATOR)) \ 12 -I$(DIR_INC) 13 -I$(DIR_INC) \ 14 -I../processor/Morpheo 13 15 14 LIBDIR = 16 LIBDIR = $(SYSTEMC_LIBDIR_$(SIMULATOR)) 15 17 16 FLAGS = $(SYSTEMC_CFLAGS_$(SIMULATOR))\17 $(CXX_FLAGS)18 LIBNAME = $(SYSTEMC_LIBNAME_$(SIMULATOR)) \ 19 -lbfd 18 20 19 CFLAGS = $(MORPHEO_FLAGS) $(FLAGS) $(INCDIR) 20 LFLAGS = $(MORPHEO_FLAGS) $(FLAGS) $(LIBDIR) 21 FLAGS = $(SYSTEMC_CFLAGS_$(SIMULATOR)) 22 23 MORPHEO_CC_FLAGS = $(MORPHEO_FLAGS) $(CC_FLAGS) $(INCDIR) 24 MORPHEO_CXX_FLAGS = $(MORPHEO_FLAGS) $(CXX_FLAGS) $(FLAGS) $(INCDIR) 25 MORPHEO_L_FLAGS = $(MORPHEO_FLAGS) $(CXX_FLAGS) $(FLAGS) $(LIBDIR) 21 26 22 27 #-----[ Variable ]----------------------------------------- … … 24 29 ENTITY = `$(BASENAME) $$PWD` 25 30 26 OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) 31 OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) \ 32 $(patsubst $(DIR_SRC)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.c)) 27 33 OBJECTS_BIN = $(patsubst $(DIR_TST)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_TST)/*.cpp)) 28 34 … … 31 37 EXE = $(DIR_BIN)/soft.x 32 38 39 EXEC_PREFIX = 40 #$(VALGRIND) 41 33 42 #-----[ Rules ]-------------------------------------------- 34 43 … … 36 45 37 46 test_env : 38 @$(ECHO) "-------------------[ $(ENTITY) ]" 47 @\ 48 $(ECHO) "-------------------| $(ENTITY)" 39 49 40 50 $(DIR_OBJ)/%.o : $(DIR_SRC)/%.cpp $(HEADERS) 41 51 @\ 42 52 $(ECHO) "Compilation : $*";\ 43 $(CXX) $(CFLAGS) -c -o $@ $<; 53 $(DISTCXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; 54 55 $(DIR_OBJ)/%.o : $(DIR_SRC)/%.c $(HEADERS) 56 @\ 57 $(ECHO) "Compilation : $*";\ 58 $(DISTCC) $(MORPHEO_CC_FLAGS) -c -o $@ $<; 44 59 45 60 $(DIR_OBJ)/%.o : $(DIR_TST)/%.cpp $(HEADERS) 46 61 @\ 47 62 $(ECHO) "Compilation : $*";\ 48 $( CXX) $(CFLAGS) -c -o $@ $<;63 $(DISTCXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; 49 64 50 65 $(DIR_BIN)/%.x : $(OBJECTS_DEPS) $(OBJECTS) $(OBJECTS_BIN) 51 66 \ 52 67 $(ECHO) "Compilation : $*";\ 53 $(CXX) $( LFLAGS) -o $@ $^;68 $(CXX) $(MORPHEO_L_FLAGS) -o $@ $^ $(LIBNAME); 54 69 55 70 $(DIR_OBJ) : … … 64 79 65 80 66 exe : all _environment81 exe : all 67 82 @\ 68 $(VALGRIND) ./$(EXE)83 export SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(EXEC_PREFIX) ./$(EXE) $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR)) 69 84 70 all_environment : test_env $(DIR_OBJ) $(DIR_BIN) 85 86 all_environment : test_env $(DIR_OBJ) $(DIR_BIN) 71 87 @\ 72 88 $(MAKE) $(EXE) … … 80 96 $(DIR_TST)/*~ \ 81 97 $(DIR_SRC)/*~ \ 82 $(DIR_INC)/*~; 98 $(DIR_INC)/*~ \ 99 *.dot \ 100 *.txt; 83 101 84 102 environment_help : -
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trunk/IPs/systemC/Environment/Queue/Makefile
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trunk/IPs/systemC/Environment/Queue/include/Queue.h
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r80 r81 61 61 // *****[ pop ]***** 62 62 // read the queue, and update the pointer 63 public : virtual T pop () {return T();};63 public : virtual T pop () = 0; 64 64 65 65 // *****[ pop ]***** 66 66 // read the queue, and update the pointer 67 public : virtual T pop (uint32_t num) {return T();};67 public : virtual T pop (uint32_t num) = 0; 68 68 69 69 // *****[ push ]***** 70 70 // Push a new value (they must have a slot free) 71 public : virtual bool push (T val) {return false;};71 public : virtual bool push (T val) = 0; 72 72 73 73 }; // Queue -
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trunk/IPs/systemC/Environment/Queue/include/Sort_Queue.h
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r80 r81 25 25 Parameters * param) : Queue <T> (name,param->_size) 26 26 { 27 _ptr_read = 0; 28 _ptr_write = 0; 27 29 }; 28 30 … … 104 106 105 107 // *****[ push ]***** 108 public : bool push (T val) 109 { 110 return push (0, val); 111 } 112 106 113 // Push a new value (they must have a slot free) 107 114 // Is sort by delay -
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r80 r81 143 143 // Reorganize the queue 144 144 145 for (uint32_t it = num; it < Queue <T>::_nb_slot; it ++)145 for (uint32_t it = num; it+1 < Queue <T>::_nb_slot; it ++) 146 146 { 147 147 uint32_t ptr = (it); 148 148 uint32_t ptr_next = (it+1); 149 149 150 // std::cout << "ptr : " << ptr << std::endl 151 // << "ptr_next : " << ptr_next << std::endl 152 // << "nb_slot : " << Queue <T>::_nb_slot << std::endl; 153 150 154 Queue <T>::_slot [ptr] = Queue <T>::_slot [ptr_next]; 151 155 } … … 157 161 158 162 // *****[ push ]***** 163 public : bool push (T val) 164 { 165 return push (0, val); 166 } 167 159 168 // Push a new value (they must have a slot free) 160 169 // Is sort by delay -
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trunk/IPs/systemC/Environment/Queue/selftest/main.cpp
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r80 r81 1 #include <iostream>2 1 #include "../include/Sort_Queue.h" 3 2 #include "../include/Sort_Queue_Dynamic.h" 3 #include <iostream> 4 4 5 5 using namespace std; … … 52 52 53 53 54 int main (void) 54 #ifdef SYSTEMC 55 int sc_main (int argc, char * argv[]) 56 #else 57 int main (int argc, char * argv[]) 58 #endif 55 59 { 56 60 cout << "<main> Begin" << endl; -
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r80 r81 5 5 #include <iostream> 6 6 7 #include " Parameters.h"7 #include "RamLock_Parameters.h" 8 8 9 9 namespace environment { -
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trunk/IPs/systemC/Environment/RamLock/selftest/main.cpp
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r80 r81 1 #include "../include/RamLock.h" 1 2 #include <iostream> 2 #include "../include/RamLock.h"3 3 4 4 using namespace std; … … 24 24 25 25 26 int main (void) 26 #ifdef SYSTEMC 27 int sc_main (int argc, char * argv[]) 28 #else 29 int main (int argc, char * argv[]) 30 #endif 27 31 { 28 32 cout << "<main> Begin" << endl; -
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trunk/IPs/systemC/Environment/RamLock/src/RamLock.cpp
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trunk/IPs/systemC/Environment/RamLock/src/RamLock_test.cpp
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r80 r81 8 8 // return num_lock < _param->_size; 9 9 // } 10 10 11 }; 11 12 }; -
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