Changeset 81 for trunk/IPs/systemC/Environment/Cache

Timestamp:

Apr 15, 2008, 8:40:01 PM (17 years ago)

Author:

rosiere

Message:

• Finish Environment (and test)
• Continue predictor_unit
• Add external tools
• svn keyword "Id" set

Location:

trunk/IPs/systemC/Environment/Cache

Files:

• Makefile (modified) (1 diff, 1 prop)
• include/Cache.h (modified) (1 prop)
• include/Cache_MultiLevel.h (modified) (1 prop)
• include/Cache_MultiLevel_Access.h (modified) (1 diff, 1 prop)
• include/Cache_MultiLevel_Parameters.h (modified) (1 prop)
• include/Cache_OneLevel.h (modified) (1 diff, 1 prop)
• include/Cache_OneLevel_Access_Port.h (modified) (1 prop)
• include/Cache_OneLevel_Address.h (modified) (1 prop)
• include/Cache_OneLevel_Parameters.h (modified) (1 prop)
• include/Cache_OneLevel_Tag.h (modified) (1 prop)
• include/Cache_OneLevel_Write_Buffer.h (modified) (1 prop)
• include/Cache_Parameters.h (modified) (3 diffs, 1 prop)
• include/Types.h (modified) (1 prop)
• selftest/main.cpp (modified) (16 diffs, 1 prop)
• src/Cache.cpp (modified) (1 prop)
• src/Cache_MultiLevel.cpp (modified) (1 prop)
• src/Cache_MultiLevel_access.cpp (modified) (1 diff, 1 prop)
• src/Cache_MultiLevel_information.cpp (modified) (1 prop)
• src/Cache_MultiLevel_latence.cpp (modified) (1 prop)
• src/Cache_MultiLevel_print.cpp (modified) (1 prop)
• src/Cache_MultiLevel_reset.cpp (modified) (1 prop)
• src/Cache_MultiLevel_transition.cpp (modified) (1 prop)
• src/Cache_MultiLevel_update_access.cpp (modified) (1 diff, 1 prop)
• src/Cache_OneLevel.cpp (modified) (1 prop)
• src/Cache_OneLevel_access.cpp (modified) (1 prop)
• src/Cache_OneLevel_access_cached.cpp (modified) (1 prop)
• src/Cache_OneLevel_access_flush.cpp (modified) (1 prop)
• src/Cache_OneLevel_access_invalidate.cpp (modified) (1 prop)
• src/Cache_OneLevel_access_uncached.cpp (modified) (1 prop)
• src/Cache_OneLevel_hit_access_port.cpp (modified) (1 prop)
• src/Cache_OneLevel_hit_cache.cpp (modified) (1 prop)
• src/Cache_OneLevel_hit_write_buffer.cpp (modified) (1 prop)
• src/Cache_OneLevel_index_victim.cpp (modified) (1 prop)
• src/Cache_OneLevel_information.cpp (modified) (1 prop)
• src/Cache_OneLevel_latence.cpp (modified) (1 prop)
• src/Cache_OneLevel_need_slot.cpp (modified) (1 prop)
• src/Cache_OneLevel_print.cpp (modified) (1 prop)
• src/Cache_OneLevel_reset.cpp (modified) (1 prop)
• src/Cache_OneLevel_transition.cpp (modified) (1 diff, 1 prop)
• src/Cache_OneLevel_translate_address.cpp (modified) (1 prop)
• src/Cache_OneLevel_update_latence.cpp (modified) (1 prop)
• src/Cache_OneLevel_update_lru.cpp (modified) (1 prop)
• src/Cache_information.cpp (modified) (1 prop)
• src/Cache_latence.cpp (modified) (3 diffs, 1 prop)
• src/Cache_print.cpp (modified) (1 prop)
• src/Cache_range_port.cpp (modified) (2 diffs, 1 prop)
• src/Cache_reset.cpp (modified) (1 prop)
• src/Cache_transition.cpp (modified) (1 prop)

trunk/IPs/systemC/Environment/Cache/Makefile

@@ -5 +5 @@
 #-----[ Variable ]-----------------------------------------
 
-OBJECTS_DEPS                    = $(patsubst $(DIR_QUEUE)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_QUEUE)/*.cpp))
+OBJECTS_DEPS                    = $(patsubst $(DIR_QUEUE)/$(DIR_SRC)/%.cpp,$(DIR_QUEUE)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_QUEUE)/$(DIR_SRC)/*.cpp))
 
 #-----[ Rules ]--------------------------------------------

trunk/IPs/systemC/Environment/Cache/include/Cache_MultiLevel_Access.h

@@ -17 +17 @@
   public : Access ()
     {
+      this->num_port      = 0;
+      this->hit           = MISS;
+      this->latence       = 0;
+      this->last_nb_level = 0;
     }
 

trunk/IPs/systemC/Environment/Cache/include/Cache_OneLevel.h

@@ -8 +8 @@
 #include "Cache_OneLevel_Parameters.h"
 #include "../../Queue/include/Sort_Queue_Dynamic.h"
+#include "../../Common/include/Debug.h"
 
 namespace environment {

trunk/IPs/systemC/Environment/Cache/include/Cache_Parameters.h

@@ -14 +14 @@
   public : uint32_t nb_cache_dedicated;
   public : uint32_t nb_iport;
+  public : uint32_t nb_dport;
 
   public : cache_multilevel::Parameters ** param_icache_dedicated;
@@ -47 +48 @@
       this->nb_cache_dedicated = nb_cache_dedicated;
 
+      if (nb_cache_dedicated == 0)
+        {
+          std::cerr << "[  ERROR  ] nb_cache_dedicated > 0" << std::endl;
+          exit(0);
+        }
+
       uint32_t cache_shared_nb_port = 0;
-      uint32_t nb_iport = 0;
+      nb_iport = 0;
+      nb_dport = 0;
+
       for (uint32_t i=0; i<nb_cache_dedicated; i++)
         {
           nb_iport             += icache_dedicated_nb_port [i];
+          nb_dport             += dcache_dedicated_nb_port [i];
           cache_shared_nb_port += icache_dedicated_nb_port [i];
           cache_shared_nb_port += dcache_dedicated_nb_port [i];
@@ -108 +118 @@
     {
       std::string tab (depth,'\t');
-      std::stringstream str;
+      std::stringstream str ("");
 
       str << tab << "* Nb Cache dedicated    : " << nb_cache_dedicated << std::endl
-          << tab << "* Nb iport              : " << nb_iport << std::endl;
+          << tab << "* Nb iport              : " << nb_iport << std::endl
+          << tab << "* Nb dport              : " << nb_dport << std::endl
+;
 
       for (uint32_t i=0; i<nb_cache_dedicated; i++)

trunk/IPs/systemC/Environment/Cache/selftest/main.cpp

@@ +1 @@
+#include "../include/Cache.h"
 #include <iostream>
-#include "../include/Cache.h"
 
 using namespace std;
@@ -6 +6 @@
 using namespace environment::cache;
 
-#define TEST(x,y)                               \
-  {                                             \
-    cout << "Line " << __LINE__ << " : ";       \
-    if (x==y)                                   \
-      {                                         \
-        cout << "Test OK" << endl;              \
-      }                                         \
-    else                                        \
-      {                                         \
-        cout << "Test KO" << endl;              \
-        exit (EXIT_FAILURE);                    \
-      }                                         \
+#define TEST(x,y)                                                       \
+  {                                                                     \
+    if (x==y)                                                           \
+      {                                                                 \
+        cout << "Line " << __LINE__ << " : " << "Test OK" << endl;      \
+      }                                                                 \
+    else                                                                \
+      {                                                                 \
+        cout << "Line " << __LINE__ << " : " << "Test KO" << endl;      \
+        exit (EXIT_FAILURE);                                            \
+      }                                                                 \
   } while (0)
     
 
 
-int main (void)
+#ifdef SYSTEMC
+int sc_main (int argc, char * argv[])
+#else
+int    main (int argc, char * argv[])
+#endif
 {
   cout << "<main> Begin" << endl;
@@ -38 +41 @@
        );
 
-    cout << *param << endl;
+//     cout << *param << endl;
 
     cache_onelevel::Cache_OneLevel * cache = new cache_onelevel::Cache_OneLevel ("my_cache",param);
     cache->reset();
     
-    cout << *cache << endl;
+//     cout << *cache << endl;
     
     cache->transition();
     cache->transition();
 
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     TEST(cache->access(0, 0x100, 0, CACHED, WRITE), MISS);
@@ -89 +92 @@
 
     cache->transition(); // miss cycle 1
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     TEST(cache->access(0, 0x200, 0, CACHED, WRITE), MISS      );
@@ -99 +102 @@
     cache->transition(); // miss cycle 2
     cache->transition(); // miss cycle 3
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     // line 0 : all way is use
@@ -113 +116 @@
 
     cache->transition();
-    cout << *cache << endl;
+//     cout << *cache << endl;
     
     TEST(cache->access(0, 0x500, 0,  CACHED, WRITE), MISS      );
@@ -141 +144 @@
     TEST(cache->latence(3), 5);
     
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     delete cache;
@@ -174 +177 @@
        );
 
-    cout << *param << endl;
+//     cout << *param << endl;
   
     cache_multilevel::Cache_MultiLevel * cache = new cache_multilevel::Cache_MultiLevel ("my_cache",param);
 
-    cout << *cache << endl;
     cache->reset();
-    cout << *cache << endl;
+//     cout << *cache << endl;
   
     cache_multilevel::Access access;
@@ -202 +204 @@
     cache->transition(); //11
     cache->transition(); //10
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     access = cache->access (0, 0x100, 0, CACHED, WRITE);
@@ -238 +240 @@
     TEST(access.latence      , 1);
     TEST(access.last_nb_level, 0);
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     cache->transition();
@@ -303 +305 @@
     cache->transition(); //11
     cache->transition(); //10
-    cout << *cache << endl;
+//     cout << *cache << endl;
 
     access = cache->access (0, 0x100, 0, CACHED, WRITE);
@@ -358 +360 @@
 
     access = cache->access (1, 0x100, 0, CACHED, WRITE);
-    cout << access<< endl;
+//     cout << access<< endl;
     
     cache->update_access(access);
@@ -367 +369 @@
     TEST(access.last_nb_level, 1);
 
-    cout << *cache << endl;
+//     cout << *cache << endl;
     delete cache;
     delete param;
@@ -389 +391 @@
     cache_shared_size_line     [0] = 8 ;
     cache_shared_size_word     [0] = 4 ;
-    cache_shared_associativity [0] = 4 ;
+    cache_shared_associativity [0] = 8 ;
     cache_shared_hit_latence   [0] = 2 ;
     cache_shared_miss_penality [0] = 5 ;
@@ -467 +469 @@
 
     dcache_nb_level      [1]    = 2;
-    dcache_nb_port       [1]    = 2;
+    dcache_nb_port       [1]    = 8; // to test
     dcache_nb_line       [1]    = new uint32_t [2];
     dcache_size_line     [1]    = new uint32_t [2];
@@ -519 +521 @@
        );
 
-    cout << *param << endl;
+//     cout << *param << endl;
 
     cache::Cache * cache = new cache::Cache ("my_cache",param);
 
+    cache->reset();
+//     cout << *cache << endl;
+
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 14);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 13);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 12);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  9);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  8);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 16); // miss thread !=
+    TEST(cache->latence (DATA_CACHE, 0, 0, 0x100, 0, CACHED, WRITE),  6); // miss L1, hit L2
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  7);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 15);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  6);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 14);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 13);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 12);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 11);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 10);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  9);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  8);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  7);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  6);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  5);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  4);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  3);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  2);
+    cache->transition();
+
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  5); // L1 is direct map, hit L2
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1); // write in L1
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 16);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 16);
+    cache->transition();
+
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 15);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 15);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 14);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 14);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 16);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 16);
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 13);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 13);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 15);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 15);
+
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 12);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 12);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 14);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 14);
+
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 11);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 13);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 13);
+
+    // in cache L2 : context 0,1,2,3
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 10);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 12);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 12);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  9);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  9);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 11);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 11);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  8);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  8);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 10); // write in L2
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 10); // write in L2
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  7);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  7);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  9);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  9);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  6);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  6);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  8);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  8);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  7);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  7);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  6);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  6);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  5);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  4);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  4);
+
     cout << *cache << endl;
-    cache->reset();
-    cout << *cache << endl;
-
-    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16);
-    cache->transition();
-    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15);
-    cache->transition();
-
-    cout << *cache << endl;
-
+
+    cache->transition();
+    // In L2 : context 1,2,4,5 : also context 0 and 3 miss L1 and L2, hit L3
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  3);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  3);
+
+    cache->transition();
+    TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10);
+    TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE),  1);
+    TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE),  5);
+    TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10);
+    TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE),  2);
+    TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE),  2);
+
+// //     cout << *cache << endl;
 
     delete    cache;
+
     delete    param;
     delete [] cache_shared_nb_line      ;

trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_access.cpp

@@ -16 +16 @@
       {
         hit   = hierarchy_cache[i]->access (num_port,address,trdid,type,dir);
-        time += hierarchy_cache[i]->latence(num_port);
+        uint32_t latence = hierarchy_cache[i]->latence(num_port);
+        time += latence;
 
-        std::cout << "SETH : "
-                  << " * i    : " << i
-                  << " * hit  : " << hit
-                  << " * time  :" << time << std::endl;
-        
+        _cout(CACHE,"    * Level [%d] - type_hit %d, latence %d, Sum latence %d\n",i,hit,latence,time);
+
         if ( (hit == HIT_CACHE)        or
              (hit == HIT_WRITE_BUFFER) or

trunk/IPs/systemC/Environment/Cache/src/Cache_MultiLevel_update_access.cpp

@@ -8 +8 @@
   uint32_t Cache_MultiLevel::update_access (Access cur_access)
   {
-    if (cur_access.last_nb_level > 0)
+//     if (cur_access.last_nb_level > 0)
       {
         uint32_t latence = cur_access.latence;
+
+        _cout(CACHE,"Cache_MultiLevel::update_access [%d] : latence : %d, last_nb_level : %d (nb_level : %d)\n",cur_access.num_port,latence,cur_access.last_nb_level,param->nb_level);
         
-        for (uint32_t it = 0; it <= cur_access.last_nb_level; it ++)
-          latence = hierarchy_cache [it]->update_latence (cur_access.num_port,latence);
-        
+        for (uint32_t it = 0; it < cur_access.last_nb_level; it ++)
+          {
+            latence = hierarchy_cache [it]->update_latence (cur_access.num_port,latence);
+          }
 //      if (latence != 0)
 //        {

trunk/IPs/systemC/Environment/Cache/src/Cache_OneLevel_transition.cpp

@@ -34 +34 @@
 
     // Test if a write_buffer have the result
-    while ((write_buffer->empty() == false) && (write_buffer->read(0)._delay == 0))
+    while ((write_buffer->empty() == false) and 
+           (write_buffer->read(0)._delay == 0))
       {
         // Save in the cache
-        Write_Buffer val     = write_buffer->pop();
+        Write_Buffer val = write_buffer->pop();
         
-        uint32_t num_tag     = val.address.tag;
-        uint32_t num_familly = val.address.familly;
+        uint32_t num_tag           = val.address.tag;
+        uint32_t num_familly       = val.address.familly;
         uint32_t num_associativity = index_victim(num_familly);
         

trunk/IPs/systemC/Environment/Cache/src/Cache_latence.cpp

@@ -22 +22 @@
 
     cache_multilevel::Cache_MultiLevel * cache;
+    cache_multilevel::Parameters * param_cache_dedicated;
+    _cout(CACHE," * Access Cache_Dedicated_");
     if (type_cache == INSTRUCTION_CACHE)
-      cache = icache_dedicated [num_entity];
+      {
+        _cout(CACHE,"Instruction");
+        cache                 = icache_dedicated [num_entity];
+        param_cache_dedicated = param->param_icache_dedicated [num_entity];
+      }
     else
-      cache = dcache_dedicated [num_entity];
+      {
+        _cout(CACHE,"Data");
+        cache                 = dcache_dedicated [num_entity];
+        param_cache_dedicated = param->param_dcache_dedicated [num_entity];
+      }
+    _cout(CACHE," [%d] - entity : %d, address : 0x%.x\n",num_port,num_entity,address);
 
     if (num_port >= cache->param->nb_port)
@@ -34 +45 @@
 
     // Make a access with this level "dedicated"
-    std::cout << "cache dedicated : access" << std::endl;
     cache_multilevel::Access access_dedicated = cache->access(num_port,address,trdid,type,dir);
 
     if (access_dedicated.hit == MISS)
       {
-        std::cout << "cache shared    : access" << std::endl;
+        _cout(CACHE," * Access Cache_shared");
+
         // Make a access with this level "shared"
         cache_multilevel::Access access_shared  = cache_shared->access(range_port (type_cache,num_entity)+num_port,address,trdid,type,dir);
@@ -45 +56 @@
         cache_shared->update_access (access_shared);
         
-        access_dedicated.last_nb_level = param->nb_cache_dedicated-1; // Update all cache
+        access_dedicated.last_nb_level = param_cache_dedicated->nb_level; // Update all cache
         access_dedicated.latence += access_shared.latence;
       }
 
-    std::cout << "end access, update access" << std::endl;
-
     cache->update_access (access_dedicated);
 
-    std::cout << "end access, update access" << std::endl;
-
+    _cout(CACHE,"Access latence : %d\n",access_dedicated.latence);
     return access_dedicated.latence;
   }

trunk/IPs/systemC/Environment/Cache/src/Cache_range_port.cpp

@@ -16 +16 @@
     else
       {
-        std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;
+//      std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;
         nb_port_dedicated += param->nb_iport;
-        std::cout << "nb_port_dedicated : " << param->nb_iport<< std::endl;
+//      std::cout << "nb_port_dedicated : " << param->nb_iport<< std::endl;
     
         for (uint32_t i = 1; i < num_entity; i++)
@@ -24 +24 @@
       }
 
-    std::cout << "nb_port_dedicated : " << num_entity << std::endl;
-    std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;
+//     std::cout << "nb_port_dedicated : " << num_entity << std::endl;
+//     std::cout << "nb_port_dedicated : " << nb_port_dedicated<< std::endl;
         
     return nb_port_dedicated;