Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg	(revision 82)
@@ -0,0 +1,10 @@
+Branch_Target_Buffer_Register
+1	1	+1	# nb_context     
+1 	1  	*2	# nb_instruction [0] [nb_context]
+1 	1	*4	# size_buffer    
+1 	1	*4	# associativity  
+32	32	*2	# size_address   
+2	2	+1	# size_counter   
+1	1	*4	# nb_inst_predict
+1	1	*4	# nb_inst_decod  
+1	1  	*4	# nb_inst_commit 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp	(revision 82)
@@ -7,40 +7,11 @@
  */
 
+#define NB_ITERATION  1024
+#define CYCLE_MAX     (128*NB_ITERATION)
+
 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test.h"
 #include "Common/include/Test.h"
 #include "Common/include/BitManipulation.h"
 #include "Behavioural/include/Allocation.h"
-
-#define NB_ITERATION  1024
-#define CYCLE_MAX     (128*NB_ITERATION)
-
-#define LABEL(str...)							\
-  {									\
-    msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time()));	\
-    msg (str);								\
-    msg (_("\n"));							\
-  } while(0)
-
-#define SC_START(cycle_offset)                                                       \
-  do									             \
-    {									             \
-      /*cout << "SC_START (begin)" << endl;*/				             \
-									             \
-      uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time());          \
-      if (cycle_offset != 0)						             \
-	{								             \
-	  cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
-	}								             \
-									             \
-      if (cycle_current > CYCLE_MAX)					             \
-	{								             \
-	  TEST_KO("Maximal cycles Reached");				             \
-	}								             \
-									             \
-      sc_start(cycle_offset);						             \
-									             \
-      /*cout << "SC_START (end  )" << endl;*/				             \
-    } while(0)
-
 
   class entry_t
@@ -120,9 +91,11 @@
 #endif
 
-  Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register (name.c_str(),
+  Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register 
+    (name.c_str(),
 #ifdef STATISTICS
-					     _parameters_statistics,
+     _parameters_statistics,
 #endif
-					     _param);
+     _param,
+     USE_ALL);
   
 #ifdef SYSTEMC
@@ -156,4 +129,5 @@
   ALLOC1_SC_SIGNAL( in_DECOD_LAST_TAKE       ," in_DECOD_LAST_TAKE       ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_DECOD_MISS_PREDICTION ," in_DECOD_MISS_PREDICTION ",Tcontrol_t         ,_param->_nb_inst_decod);
+  ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE     ," in_DECOD_IS_ACCURATE     ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_UPDATE_VAL            ," in_UPDATE_VAL            ",Tcontrol_t         ,_param->_nb_inst_update);
   ALLOC1_SC_SIGNAL(out_UPDATE_ACK            ,"out_UPDATE_ACK            ",Tcontrol_t         ,_param->_nb_inst_update);
@@ -191,9 +165,10 @@
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VAL             ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_ACK             ,_param->_nb_inst_decod);
+  if (_param->_have_port_victim)
+    {
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT             ,_param->_nb_inst_decod);
-  if (_param->_have_port_victim)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_DECOD_HIT_INDEX       ,_param->_nb_inst_decod);
-  if (_param->_have_port_victim)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_VICTIM          ,_param->_nb_inst_decod);
+    }
   if (_param->_have_port_context_id)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_CONTEXT_ID      ,_param->_nb_inst_decod);
@@ -203,12 +178,14 @@
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_LAST_TAKE       ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod);
+  INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_DECOD_IS_ACCURATE     ,_param->_nb_inst_decod);
 
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VAL            ,_param->_nb_inst_update);
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_ACK            ,_param->_nb_inst_update);
+  if (_param->_have_port_victim)
+    {
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT            ,_param->_nb_inst_update);
-  if (_param->_have_port_victim)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register,out_UPDATE_HIT_INDEX      ,_param->_nb_inst_update);
-  if (_param->_have_port_victim)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_VICTIM         ,_param->_nb_inst_update);
+    }
   if (_param->_have_port_context_id)
   INSTANCE1_SC_SIGNAL(_Branch_Target_Buffer_Register, in_UPDATE_CONTEXT_ID     ,_param->_nb_inst_update);
@@ -297,4 +274,5 @@
 	  in_DECOD_LAST_TAKE       [i]->write(rand()%2);
 	  in_DECOD_MISS_PREDICTION [i]->write(rand()%2);
+	  in_DECOD_IS_ACCURATE     [i]->write(rand()%2);
 	}
 
@@ -478,4 +456,5 @@
   delete []  in_DECOD_LAST_TAKE       ;
   delete []  in_DECOD_MISS_PREDICTION ;
+  delete []  in_DECOD_IS_ACCURATE     ;
   delete []  in_UPDATE_VAL            ;
   delete [] out_UPDATE_ACK            ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Branch_Target_Buffer_Register.h	(revision 82)
@@ -87,4 +87,5 @@
   public    : SC_IN (Tcontrol_t         )  **  in_DECOD_LAST_TAKE       ; //[nb_inst_decod]
   public    : SC_IN (Tcontrol_t         )  **  in_DECOD_MISS_PREDICTION ; //[nb_inst_decod]
+  public    : SC_IN (Tcontrol_t         )  **  in_DECOD_IS_ACCURATE     ; //[nb_inst_decod]
 
     // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -134,5 +135,5 @@
 #endif
    Parameters                                  * param,
-   morpheo::behavioural::Tusage_t                usage=USE_ALL
+   morpheo::behavioural::Tusage_t                usage
    );
   public  :          ~Branch_Target_Buffer_Register             (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp	(revision 82)
@@ -139,4 +139,6 @@
 # endif
 
+	if (_param->_have_port_victim)
+	  {
 	log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Method - genMealy_decod");
 
@@ -161,14 +163,14 @@
 	    (*(out_DECOD_HIT [i])) (*(in_DECOD_CONTEXT_ID  [i]));
 
-	    if (_param->_have_port_victim)
-	      {
 	    (*(out_DECOD_HIT_INDEX [i])) (*(in_DECOD_VAL         [i]));
 	    (*(out_DECOD_HIT_INDEX [i])) (*(in_DECOD_ADDRESS_SRC [i]));
 	    if (_param->_have_port_context_id)
 	    (*(out_DECOD_HIT_INDEX [i])) (*(in_DECOD_CONTEXT_ID  [i]));
-	      }
-	  }
-#endif
-
+	  }
+	  }
+#endif
+
+	if (_param->_have_port_victim)
+	  {
 	log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Method - genMealy_update");
 
@@ -193,11 +195,9 @@
 	    (*(out_UPDATE_HIT [i])) (*(in_UPDATE_CONTEXT_ID  [i]));
 
-	    if (_param->_have_port_victim)
-	      {
 	    (*(out_UPDATE_HIT_INDEX [i])) (*(in_UPDATE_VAL         [i]));
 	    (*(out_UPDATE_HIT_INDEX [i])) (*(in_UPDATE_ADDRESS_SRC [i]));
 	    if (_param->_have_port_context_id)
 	    (*(out_UPDATE_HIT_INDEX [i])) (*(in_UPDATE_CONTEXT_ID  [i]));
-	      }
+	  }
 	  }
 # endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp	(revision 82)
@@ -84,7 +84,10 @@
       ALLOC1_VALACK_IN ( in_DECOD_VAL            ,VAL);
       ALLOC1_VALACK_OUT(out_DECOD_ACK            ,ACK);
+      if (_param->_have_port_victim)
+	{
       ALLOC1_SIGNAL_OUT(out_DECOD_HIT            ,"hit"            ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_OUT(out_DECOD_HIT_INDEX      ,"hit_index"      ,Tptr_t             ,_param->_size_victim);
       ALLOC1_SIGNAL_IN ( in_DECOD_VICTIM         ,"victim"         ,Tptr_t             ,_param->_size_victim);
+	}
       ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
       ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
@@ -93,4 +96,5 @@
       ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t         ,1);
+      ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE    ,"is_accurate"    ,Tcontrol_t         ,1);
     }
 
@@ -101,7 +105,10 @@
       ALLOC1_VALACK_IN ( in_UPDATE_VAL            ,VAL);
       ALLOC1_VALACK_OUT(out_UPDATE_ACK            ,ACK);
+      if (_param->_have_port_victim)
+	{
       ALLOC1_SIGNAL_OUT(out_UPDATE_HIT            ,"hit"            ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_OUT(out_UPDATE_HIT_INDEX      ,"hit_index"      ,Tptr_t             ,_param->_size_victim);
       ALLOC1_SIGNAL_IN ( in_UPDATE_VICTIM         ,"victim"         ,Tptr_t             ,_param->_size_victim);
+	}
       ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
       ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp	(revision 82)
@@ -54,4 +54,5 @@
 	delete []  in_DECOD_LAST_TAKE       ;
 	delete []  in_DECOD_MISS_PREDICTION ;
+	delete []  in_DECOD_IS_ACCURATE     ;
 	delete []  in_UPDATE_VAL            ;
 	delete [] out_UPDATE_ACK            ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp	(revision 82)
@@ -48,7 +48,9 @@
 	internal_DECOD_NUM_ENTRY [i] = num_entry;
 
+	if (_param->_have_port_victim)
+	  {
 	PORT_WRITE(out_DECOD_HIT       [i], hit);
-	if (_param->_have_port_victim)
 	PORT_WRITE(out_DECOD_HIT_INDEX [i], num_entry);
+	  }
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp	(revision 82)
@@ -48,7 +48,9 @@
 	internal_UPDATE_NUM_ENTRY [i] = num_entry;
 
+	if (_param->_have_port_victim)
+	  {
 	PORT_WRITE(out_UPDATE_HIT [i], hit);
-	if (_param->_have_port_victim)
 	PORT_WRITE(out_UPDATE_HIT_INDEX [i], num_entry);
+	  }
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 82)
@@ -32,4 +32,10 @@
     else
       {
+	if (not _param->_have_port_victim)
+	  {
+	    genMealy_decod  ();
+	    genMealy_update ();
+	  }
+
 	// =======================================================
 	// =====[ PREDICT ]=======================================
@@ -66,5 +72,5 @@
 		  reg_BTB[num_bank][num_entry]._condition        = cond;
 		  reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_DECOD_LAST_TAKE    [i]);
-		  reg_BTB[num_bank][num_entry]._accurate         = _param->_first_accurate_if_hit;
+		  reg_BTB[num_bank][num_entry]._accurate         = (PORT_READ(in_DECOD_IS_ACCURATE [i]))?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss;
 		}
 	      // else (hit) : no update -> it's not the last result of the branch
@@ -116,15 +122,18 @@
 
 		  accurate_new =  (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
+
+		  reg_BTB[num_bank][num_entry]._val              = 1;
+		  reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+		  reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
+		  reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
+		  reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
 		}
 
 	      // =====[ All Case ]
-	      reg_BTB[num_bank][num_entry]._val              = 1;
-	      reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
-	      reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
-	      reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
-
-	      reg_BTB[num_bank][num_entry]._address_dest_val = 1;
-	      reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
-	      reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
+	      if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
+		{
+		  reg_BTB[num_bank][num_entry]._address_dest_val = 1;
+		  reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
+		}
 	      reg_BTB[num_bank][num_entry]._accurate         = accurate_new;
 	    }
