Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg	(revision 84)
@@ -1,4 +1,4 @@
 Address_management
 1	8	*2	# nb_instruction               
-32	32	*2	# size_address                 
+30	30 	*2	# size_address                 
 1	4	*4	# size_branch_update_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 84)
@@ -115,5 +115,5 @@
   const  int32_t percent_transaction_address = 75;
   const  int32_t percent_transaction_predict = 75;
-  const  int32_t percent_transaction_event   = 10;
+  const  int32_t percent_transaction_event   =  5;
 
   SC_START(0);
@@ -136,23 +136,21 @@
   TEST(Tcontrol_t, out_EVENT_ACK->read()  , true ); // can receveive an event
 
-  Tcontrol_t      p_val  = false;
-  Tcontrol_t      c_val  = false;
-  Tcontrol_t      n_val  = false;
-
-  Tgeneral_data_t p_addr = 0x100;
-  Tgeneral_data_t c_addr = 0x100;
-  Tgeneral_data_t n_addr = 0x100;
+  uint32_t        jump      = 7 ;// packet
+  uint32_t        nb_packet = 1;
+
+  Tcontrol_t      c_val   = false;
+  Tcontrol_t      n_val   = false;
+  Tcontrol_t      nn_val  = false;
+
+  Tgeneral_data_t c_addr  = 0x100;
+  Tgeneral_data_t n_addr  = 0x100;
+  Tgeneral_data_t nn_addr = 0x100;
+
   Tcontrol_t      c_enable [_param->_nb_instruction];
   Tcontrol_t      n_enable [_param->_nb_instruction];
 
-  Tcontrol_t         c_is_ds_take   = 0;
-  Tinst_ifetch_ptr_t c_ifetch_ptr   = 0;
-  Tbranch_state_t    c_branch_state = BRANCH_STATE_NONE;
-  Tprediction_ptr_t  c_branch_ptr   = 0;
-
-  Tcontrol_t         n_is_ds_take   = 0;		
-  Tinst_ifetch_ptr_t n_ifetch_ptr   = 0;		
-  Tbranch_state_t    n_branch_state = BRANCH_STATE_NONE;
-  Tprediction_ptr_t  n_branch_ptr   = 0;
+  Tcontrol_t      c_is_ds_take   = 0;
+  Tcontrol_t      n_is_ds_take   = 0;		
+  Tcontrol_t      nn_is_ds_take  = 0;
 
   c_enable [0] = 1;
@@ -164,9 +162,11 @@
     {
       in_EVENT_VAL    ->write(1);
-      in_EVENT_ADDRESS->write(c_addr);
+      in_EVENT_ADDRESS->write(n_addr);
       SC_START(1);  
     } while (out_EVENT_ACK->read() == false);
   in_EVENT_VAL    ->write(0);
 
+  n_val = 1;
+  
   LABEL("Loop of Test");
 
@@ -175,28 +175,41 @@
       LABEL("Iteration %d",iteration);
 
-      in_ADDRESS_ACK  ->write((rand()%100)<percent_transaction_address);
+      // PREDICT
+      {
+	in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
+	
+	SC_START(0);
+
+	Taddress_t addr  = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
+
+	uint32_t   begin = addr%_param->_nb_instruction;
+	uint32_t   end   = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
+	Tcontrol_t take  = (nb_packet%jump)==0;
+	
+	if (take)
+	  addr += 0x100;
+	else
+	  addr += end-begin+1;
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
+	in_PREDICT_PC_NEXT                    ->write(addr);
+	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
+	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+	in_PREDICT_BRANCH_STATE               ->write(0);
+	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
+      }
+      
+      // ADDRESS
+      {
+	in_ADDRESS_ACK  ->write((rand()%100)<percent_transaction_address);
+      }
+
       in_EVENT_VAL    ->write((rand()%100)<percent_transaction_event  );
-      in_EVENT_ADDRESS->write(rand() << 2);
-
-      uint32_t begin = rand() % _param->_nb_instruction;
-      uint32_t end   = (begin + (rand() % _param->_nb_instruction));
-      end = (end > _param->_nb_instruction)?_param->_nb_instruction:end;
-
-      in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
-      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-      in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
-      in_PREDICT_PC_NEXT                    ->write(rand() << 2);
-      in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(rand()%2);
-      in_PREDICT_INST_IFETCH_PTR            ->write(begin);
-      in_PREDICT_BRANCH_STATE               ->write(c_addr%SIZE_BRANCH_STATE);
-      in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction);
-
+      in_EVENT_ADDRESS->write(0x100);
+
+      //-------------------------------------------------
       SC_START(0);
-
-      LABEL("---------------------");
-      LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-      LABEL("  * pc   : %d %.8x",c_val, c_addr);
-      LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-      LABEL("---------------------");
+      //-------------------------------------------------
 
       if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
@@ -204,9 +217,17 @@
 	  LABEL("PREDICT    : Transaction accepted");
 
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),p_addr);
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),c_addr);
-	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take);
+	  if (c_val)
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),c_addr      );
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),n_addr      );
+	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
+
+	  nn_val        = true;
+	  nn_addr       = in_PREDICT_PC_NEXT           ->read();
+	  nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
+	
+	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
 	}
-
+ 
       if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
 	{
@@ -218,69 +239,31 @@
 	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),c_enable[i]);
 	  if (_param->_have_port_instruction_ptr)
-	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),c_ifetch_ptr  );
-	  TEST(Tbranch_state_t   ,out_ADDRESS_BRANCH_STATE               ->read(),c_branch_state);
+	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),0);
+	  TEST(Tbranch_state_t   ,out_ADDRESS_BRANCH_STATE               ->read(),0);
 	  if (_param->_have_port_branch_update_prediction_id)
-	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr  );
-
-	  p_val          = true;
-	  c_val          = n_val;
-
-	  p_addr = c_addr;
-
-	  if (n_val)
+	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
+
+	  c_val = 0;
+	  nb_packet ++;
+	}
+
+
+      if (not c_val)
+	{
+	  if (n_val and nn_val)
 	    {
-	      c_addr = n_addr;
-	      
-	      c_ifetch_ptr   = n_ifetch_ptr  ;
-	      c_branch_state = n_branch_state;
-	      c_branch_ptr   = n_branch_ptr  ;
-	      c_is_ds_take   = n_is_ds_take  ;
+	      c_val        = 1;
+	      c_addr       = n_addr;
+	      c_is_ds_take = n_is_ds_take;
 
 	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
 		c_enable [i] = n_enable [i];
+	      
+	      n_val        = 1;
+	      n_addr       = nn_addr;
+	      n_is_ds_take = nn_is_ds_take;
+	      
+	      nn_val       = 0;
 	    }
-
-	  n_val          = false;
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-	}
-
-      if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
-	{
-	  LABEL("PREDICT    : Update information");
-
-	  if (c_val)
-	    {
-	      LABEL("  * current is     valid -> new next");
-	      n_val = true;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      n_enable   [i] = in_PREDICT_INSTRUCTION_ENABLE     [i] ->read();
-	      n_addr         = in_PREDICT_PC_NEXT                    ->read();
-	      n_is_ds_take   = in_PREDICT_PC_NEXT_IS_DS_TAKE         ->read();
-	      n_ifetch_ptr   = in_PREDICT_INST_IFETCH_PTR            ->read();
-	      n_branch_state = in_PREDICT_BRANCH_STATE               ->read();
-	      n_branch_ptr   = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
-	    }
-	  else
-	    {
-	      LABEL("  * current is not valid -> new current");
-	      c_val = true;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      c_enable   [i] = in_PREDICT_INSTRUCTION_ENABLE     [i] ->read();
-	      c_addr         = in_PREDICT_PC_NEXT                    ->read();
-	      c_is_ds_take   = in_PREDICT_PC_NEXT_IS_DS_TAKE         ->read();
-	      c_ifetch_ptr   = in_PREDICT_INST_IFETCH_PTR            ->read();
-	      c_branch_state = in_PREDICT_BRANCH_STATE               ->read();
-	      c_branch_ptr   = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
-	    }
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-
 	}
 
@@ -289,22 +272,44 @@
 	  LABEL("EVENT      : Transaction accepted");
 
-	  c_val          = true;
-	  n_val          = false;
-
-	  c_addr         = in_EVENT_ADDRESS->read();
-	  c_ifetch_ptr   = 0;
-	  c_branch_state = BRANCH_STATE_NONE;
-	  c_branch_ptr   = 0;
-	  c_is_ds_take   = 0;
-
-	  c_enable [0] = 1;
+	  c_val           = false;
+	  n_val           = true;
+	  nn_val          = false;
+
+	  n_addr         = in_EVENT_ADDRESS->read();
+	  n_is_ds_take   = 0;
+
+	  n_enable [0] = 1;
 	  for (uint32_t i=1; i<_param->_nb_instruction; i++)
-	    c_enable [i] = 0;
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
+	    n_enable [i] = 0;
 	}
+
+      
+      {
+	string str_c_enable = "";
+	string str_n_enable = "";
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    str_c_enable += " " + toString(c_enable [i]);
+	    str_n_enable += " " + toString(n_enable [i]);
+	  }
+
+	LABEL("-----------------------------------");
+	LABEL("  * nb_packet : %d",nb_packet);
+	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
+	if (nn_val)
+	  {
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
+	  }
+	else
+	  {
+	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
+	  }
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+	LABEL("-----------------------------------");
+      }
+
       SC_START(1);
+      
     }
 
