Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/configuration.cfg	(revision 84)
@@ -1,4 +1,4 @@
 Address_management
 1	8	*2	# nb_instruction               
-32	32	*2	# size_address                 
+30	30 	*2	# size_address                 
 1	4	*4	# size_branch_update_prediction
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp	(revision 84)
@@ -115,5 +115,5 @@
   const  int32_t percent_transaction_address = 75;
   const  int32_t percent_transaction_predict = 75;
-  const  int32_t percent_transaction_event   = 10;
+  const  int32_t percent_transaction_event   =  5;
 
   SC_START(0);
@@ -136,23 +136,21 @@
   TEST(Tcontrol_t, out_EVENT_ACK->read()  , true ); // can receveive an event
 
-  Tcontrol_t      p_val  = false;
-  Tcontrol_t      c_val  = false;
-  Tcontrol_t      n_val  = false;
-
-  Tgeneral_data_t p_addr = 0x100;
-  Tgeneral_data_t c_addr = 0x100;
-  Tgeneral_data_t n_addr = 0x100;
+  uint32_t        jump      = 7 ;// packet
+  uint32_t        nb_packet = 1;
+
+  Tcontrol_t      c_val   = false;
+  Tcontrol_t      n_val   = false;
+  Tcontrol_t      nn_val  = false;
+
+  Tgeneral_data_t c_addr  = 0x100;
+  Tgeneral_data_t n_addr  = 0x100;
+  Tgeneral_data_t nn_addr = 0x100;
+
   Tcontrol_t      c_enable [_param->_nb_instruction];
   Tcontrol_t      n_enable [_param->_nb_instruction];
 
-  Tcontrol_t         c_is_ds_take   = 0;
-  Tinst_ifetch_ptr_t c_ifetch_ptr   = 0;
-  Tbranch_state_t    c_branch_state = BRANCH_STATE_NONE;
-  Tprediction_ptr_t  c_branch_ptr   = 0;
-
-  Tcontrol_t         n_is_ds_take   = 0;		
-  Tinst_ifetch_ptr_t n_ifetch_ptr   = 0;		
-  Tbranch_state_t    n_branch_state = BRANCH_STATE_NONE;
-  Tprediction_ptr_t  n_branch_ptr   = 0;
+  Tcontrol_t      c_is_ds_take   = 0;
+  Tcontrol_t      n_is_ds_take   = 0;		
+  Tcontrol_t      nn_is_ds_take  = 0;
 
   c_enable [0] = 1;
@@ -164,9 +162,11 @@
     {
       in_EVENT_VAL    ->write(1);
-      in_EVENT_ADDRESS->write(c_addr);
+      in_EVENT_ADDRESS->write(n_addr);
       SC_START(1);  
     } while (out_EVENT_ACK->read() == false);
   in_EVENT_VAL    ->write(0);
 
+  n_val = 1;
+  
   LABEL("Loop of Test");
 
@@ -175,28 +175,41 @@
       LABEL("Iteration %d",iteration);
 
-      in_ADDRESS_ACK  ->write((rand()%100)<percent_transaction_address);
+      // PREDICT
+      {
+	in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
+	
+	SC_START(0);
+
+	Taddress_t addr  = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
+
+	uint32_t   begin = addr%_param->_nb_instruction;
+	uint32_t   end   = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
+	Tcontrol_t take  = (nb_packet%jump)==0;
+	
+	if (take)
+	  addr += 0x100;
+	else
+	  addr += end-begin+1;
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
+	in_PREDICT_PC_NEXT                    ->write(addr);
+	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
+	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+	in_PREDICT_BRANCH_STATE               ->write(0);
+	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
+      }
+      
+      // ADDRESS
+      {
+	in_ADDRESS_ACK  ->write((rand()%100)<percent_transaction_address);
+      }
+
       in_EVENT_VAL    ->write((rand()%100)<percent_transaction_event  );
-      in_EVENT_ADDRESS->write(rand() << 2);
-
-      uint32_t begin = rand() % _param->_nb_instruction;
-      uint32_t end   = (begin + (rand() % _param->_nb_instruction));
-      end = (end > _param->_nb_instruction)?_param->_nb_instruction:end;
-
-      in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
-      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-      in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
-      in_PREDICT_PC_NEXT                    ->write(rand() << 2);
-      in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(rand()%2);
-      in_PREDICT_INST_IFETCH_PTR            ->write(begin);
-      in_PREDICT_BRANCH_STATE               ->write(c_addr%SIZE_BRANCH_STATE);
-      in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction);
-
+      in_EVENT_ADDRESS->write(0x100);
+
+      //-------------------------------------------------
       SC_START(0);
-
-      LABEL("---------------------");
-      LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-      LABEL("  * pc   : %d %.8x",c_val, c_addr);
-      LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-      LABEL("---------------------");
+      //-------------------------------------------------
 
       if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
@@ -204,9 +217,17 @@
 	  LABEL("PREDICT    : Transaction accepted");
 
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),p_addr);
-	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),c_addr);
-	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take);
+	  if (c_val)
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),c_addr      );
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),n_addr      );
+	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
+
+	  nn_val        = true;
+	  nn_addr       = in_PREDICT_PC_NEXT           ->read();
+	  nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
+	
+	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
 	}
-
+ 
       if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
 	{
@@ -218,69 +239,31 @@
 	  TEST(Tcontrol_t        ,out_ADDRESS_INSTRUCTION_ENABLE     [i] ->read(),c_enable[i]);
 	  if (_param->_have_port_instruction_ptr)
-	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),c_ifetch_ptr  );
-	  TEST(Tbranch_state_t   ,out_ADDRESS_BRANCH_STATE               ->read(),c_branch_state);
+	  TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR            ->read(),0);
+	  TEST(Tbranch_state_t   ,out_ADDRESS_BRANCH_STATE               ->read(),0);
 	  if (_param->_have_port_branch_update_prediction_id)
-	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr  );
-
-	  p_val          = true;
-	  c_val          = n_val;
-
-	  p_addr = c_addr;
-
-	  if (n_val)
+	  TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
+
+	  c_val = 0;
+	  nb_packet ++;
+	}
+
+
+      if (not c_val)
+	{
+	  if (n_val and nn_val)
 	    {
-	      c_addr = n_addr;
-	      
-	      c_ifetch_ptr   = n_ifetch_ptr  ;
-	      c_branch_state = n_branch_state;
-	      c_branch_ptr   = n_branch_ptr  ;
-	      c_is_ds_take   = n_is_ds_take  ;
+	      c_val        = 1;
+	      c_addr       = n_addr;
+	      c_is_ds_take = n_is_ds_take;
 
 	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
 		c_enable [i] = n_enable [i];
+	      
+	      n_val        = 1;
+	      n_addr       = nn_addr;
+	      n_is_ds_take = nn_is_ds_take;
+	      
+	      nn_val       = 0;
 	    }
-
-	  n_val          = false;
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-	}
-
-      if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
-	{
-	  LABEL("PREDICT    : Update information");
-
-	  if (c_val)
-	    {
-	      LABEL("  * current is     valid -> new next");
-	      n_val = true;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      n_enable   [i] = in_PREDICT_INSTRUCTION_ENABLE     [i] ->read();
-	      n_addr         = in_PREDICT_PC_NEXT                    ->read();
-	      n_is_ds_take   = in_PREDICT_PC_NEXT_IS_DS_TAKE         ->read();
-	      n_ifetch_ptr   = in_PREDICT_INST_IFETCH_PTR            ->read();
-	      n_branch_state = in_PREDICT_BRANCH_STATE               ->read();
-	      n_branch_ptr   = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
-	    }
-	  else
-	    {
-	      LABEL("  * current is not valid -> new current");
-	      c_val = true;
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      c_enable   [i] = in_PREDICT_INSTRUCTION_ENABLE     [i] ->read();
-	      c_addr         = in_PREDICT_PC_NEXT                    ->read();
-	      c_is_ds_take   = in_PREDICT_PC_NEXT_IS_DS_TAKE         ->read();
-	      c_ifetch_ptr   = in_PREDICT_INST_IFETCH_PTR            ->read();
-	      c_branch_state = in_PREDICT_BRANCH_STATE               ->read();
-	      c_branch_ptr   = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
-	    }
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
-
 	}
 
@@ -289,22 +272,44 @@
 	  LABEL("EVENT      : Transaction accepted");
 
-	  c_val          = true;
-	  n_val          = false;
-
-	  c_addr         = in_EVENT_ADDRESS->read();
-	  c_ifetch_ptr   = 0;
-	  c_branch_state = BRANCH_STATE_NONE;
-	  c_branch_ptr   = 0;
-	  c_is_ds_take   = 0;
-
-	  c_enable [0] = 1;
+	  c_val           = false;
+	  n_val           = true;
+	  nn_val          = false;
+
+	  n_addr         = in_EVENT_ADDRESS->read();
+	  n_is_ds_take   = 0;
+
+	  n_enable [0] = 1;
 	  for (uint32_t i=1; i<_param->_nb_instruction; i++)
-	    c_enable [i] = 0;
-
-	  LABEL("  * pc-4 : %d %.8x",p_val, p_addr);
-	  LABEL("  * pc   : %d %.8x",c_val, c_addr);
-	  LABEL("  * pc+4 : %d %.8x",n_val, n_addr);
+	    n_enable [i] = 0;
 	}
+
+      
+      {
+	string str_c_enable = "";
+	string str_n_enable = "";
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    str_c_enable += " " + toString(c_enable [i]);
+	    str_n_enable += " " + toString(n_enable [i]);
+	  }
+
+	LABEL("-----------------------------------");
+	LABEL("  * nb_packet : %d",nb_packet);
+	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
+	if (nn_val)
+	  {
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
+	  }
+	else
+	  {
+	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
+	  }
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+	LABEL("-----------------------------------");
+      }
+
       SC_START(1);
+      
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h	(revision 84)
@@ -50,4 +50,8 @@
 #ifdef STATISTICS
   public    : Stat                           * _stat;
+  public    : counter_t                      * _stat_nb_transaction_address;
+  public    : counter_t                      * _stat_nb_transaction_predict;
+  public    : counter_t                      * _stat_nb_transaction_event  ;
+  public    : counter_t                      * _stat_sum_packet_size       ;
 #endif
 
@@ -91,22 +95,27 @@
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  private   : Tcontrol_t                      reg_PC_PREVIOUS_VAL;
-  private   : Tgeneral_address_t              reg_PC_PREVIOUS;
+  private   : Tcontrol_t                      reg_PC_CURRENT_VAL                          ;
+  private   : Tgeneral_address_t              reg_PC_CURRENT                              ;
+  private   : Tcontrol_t                      reg_PC_CURRENT_IS_DS_TAKE                   ;
+  private   : Tcontrol_t                    * reg_PC_CURRENT_INSTRUCTION_ENABLE           ; //[nb_instruction]
+  private   : Tinst_ifetch_ptr_t              reg_PC_CURRENT_INST_IFETCH_PTR              ;
+  private   : Tbranch_state_t                 reg_PC_CURRENT_BRANCH_STATE                 ;
+  private   : Tprediction_ptr_t               reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID  ;
 
-  private   : Tcontrol_t                      reg_PC_CURRENT_VAL;
-  private   : Tgeneral_address_t              reg_PC_CURRENT;
-  private   : Tcontrol_t                      reg_PC_CURRENT_IS_DS_TAKE;
-  private   : Tcontrol_t                    * reg_PC_CURRENT_INSTRUCTION_ENABLE         ; //[nb_instruction]
-  private   : Tinst_ifetch_ptr_t              reg_PC_CURRENT_INST_IFETCH_PTR            ;
-  private   : Tbranch_state_t                 reg_PC_CURRENT_BRANCH_STATE               ;
-  private   : Tprediction_ptr_t               reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;
+  private   : Tcontrol_t                      reg_PC_NEXT_VAL                             ;
+  private   : Tgeneral_address_t              reg_PC_NEXT                                 ;
+  private   : Tcontrol_t                      reg_PC_NEXT_IS_DS_TAKE                      ;
+  private   : Tcontrol_t                    * reg_PC_NEXT_INSTRUCTION_ENABLE              ; //[nb_instruction]
+  private   : Tinst_ifetch_ptr_t              reg_PC_NEXT_INST_IFETCH_PTR                 ;
+  private   : Tbranch_state_t                 reg_PC_NEXT_BRANCH_STATE                    ;
+  private   : Tprediction_ptr_t               reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID     ;
 
-  private   : Tcontrol_t                      reg_PC_NEXT_VAL;
-  private   : Tgeneral_address_t              reg_PC_NEXT;
-  private   : Tcontrol_t                      reg_PC_NEXT_IS_DS_TAKE;
-  private   : Tcontrol_t                    * reg_PC_NEXT_INSTRUCTION_ENABLE         ; //[nb_instruction]
-  private   : Tinst_ifetch_ptr_t              reg_PC_NEXT_INST_IFETCH_PTR            ;
-  private   : Tbranch_state_t                 reg_PC_NEXT_BRANCH_STATE               ;
-  private   : Tprediction_ptr_t               reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+  private   : Tcontrol_t                      reg_PC_NEXT_NEXT_VAL                        ;
+  private   : Tgeneral_address_t              reg_PC_NEXT_NEXT                            ;
+  private   : Tcontrol_t                      reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
+//private   : Tcontrol_t                    * reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE         ; //[nb_instruction]
+//private   : Tinst_ifetch_ptr_t              reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
+//private   : Tbranch_state_t                 reg_PC_NEXT_NEXT_BRANCH_STATE               ;
+//private   : Tprediction_ptr_t               reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
 
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp	(revision 84)
@@ -45,13 +45,11 @@
     // =========================================
 
-    internal_PREDICT_VAL = reg_PC_PREVIOUS_VAL and not reg_PC_NEXT_VAL;
+    internal_PREDICT_VAL = not reg_PC_NEXT_NEXT_VAL;
 
     PORT_WRITE(out_PREDICT_VAL                  ,internal_PREDICT_VAL);
-    PORT_WRITE(out_PREDICT_PC_PREVIOUS          ,reg_PC_PREVIOUS          );
-    PORT_WRITE(out_PREDICT_PC_CURRENT           ,reg_PC_CURRENT           );
-    PORT_WRITE(out_PREDICT_PC_CURRENT_IS_DS_TAKE,reg_PC_CURRENT_IS_DS_TAKE);
+    PORT_WRITE(out_PREDICT_PC_PREVIOUS          ,reg_PC_CURRENT        );
+    PORT_WRITE(out_PREDICT_PC_CURRENT           ,reg_PC_NEXT           );
+    PORT_WRITE(out_PREDICT_PC_CURRENT_IS_DS_TAKE,reg_PC_NEXT_IS_DS_TAKE);
     
-
-
     log_printf(FUNC,Address_management,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_statistics_allocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_statistics_allocation.cpp	(revision 84)
@@ -27,4 +27,14 @@
 		      "Address_management",
 		      param_statistics);
+
+    _stat_nb_transaction_address = _stat->create_variable("nb_transaction_address");
+    _stat_nb_transaction_predict = _stat->create_variable("nb_transaction_predict");
+    _stat_nb_transaction_event   = _stat->create_variable("nb_transaction_event"  );
+    _stat_sum_packet_size        = _stat->create_variable("sum_packet_size"       );
+
+    _stat->create_expr_average_by_cycle("average_transaction_address", "nb_transaction_address", "", _("Average transaction in Address interface by cycle"));
+    _stat->create_expr_average_by_cycle("average_transaction_predict", "nb_transaction_predict", "", _("Average transaction in Predict interface by cycle"));
+    _stat->create_expr_average_by_cycle("average_transaction_event"  , "nb_transaction_event"  , "", _("Average transaction in Event interface by cycle"  ));
+    _stat->create_expr                 ("average_packet_size"        , "/ sum_packet_size nb_transaction_address", TYPE_COUNTER, "", _("Average of Packet size per request"));
     
     log_printf(FUNC,Address_management,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp	(revision 84)
@@ -26,76 +26,82 @@
     if (PORT_READ(in_NRESET) == 0)
       {
-	reg_PC_PREVIOUS_VAL = 0;
-	reg_PC_CURRENT_VAL  = 0;
-	reg_PC_NEXT_VAL     = 0;	
+	// nothing is valid
+	reg_PC_CURRENT_VAL   = 0;
+	reg_PC_NEXT_VAL      = 0;
+	reg_PC_NEXT_NEXT_VAL = 0;
       }
     else
       {
 	// =========================================
+	// ===== PREDICT ===========================
+	// =========================================
+	if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
+	  {
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	    reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
+	    if (_param->_have_port_instruction_ptr)
+	    reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
+	    reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
+	    if (_param->_have_port_branch_update_prediction_id)
+	    reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
+	    
+	    reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
+	    reg_PC_NEXT_NEXT                        = PORT_READ(in_PREDICT_PC_NEXT                    );
+	    reg_PC_NEXT_NEXT_IS_DS_TAKE             = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
+
+#ifdef STATISTICS
+	    (*_stat_nb_transaction_predict) ++;
+#endif
+	  }
+
+	// =========================================
 	// ===== ADDRESS ===========================
 	// =========================================
 	// transaction with icache
-	if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
+	if ( (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK)) or not reg_PC_CURRENT_VAL)
 	  {
-	    // current pc became previous pc 
-	    reg_PC_PREVIOUS_VAL                        = 1;
-	    reg_PC_PREVIOUS                            = reg_PC_CURRENT    ;
-	    
-	    // next    pc became next     pc
-	    reg_PC_CURRENT_VAL                         = reg_PC_NEXT_VAL; // can be not valid
+#ifdef STATISTICS
+	    if (reg_PC_CURRENT_VAL)
+	      {
+		(*_stat_nb_transaction_address) ++;
+
+		for (uint32_t i=0; i<_param->_nb_instruction; i++)
+		  if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
+		    (*_stat_sum_packet_size) ++;
+	      }
+#endif
+
+
+	    Tcontrol_t pc_next_val = reg_PC_NEXT_VAL and reg_PC_NEXT_NEXT_VAL;
+
+	    // next pc became current pc
+	    reg_PC_CURRENT_VAL                             = pc_next_val;
 
 	    // if pc_next is not valid : don't erase PC and PC_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
-	    if (reg_PC_NEXT_VAL)
+	    if (pc_next_val)
 	      {
-	    reg_PC_CURRENT                             = reg_PC_NEXT    ;
-	    reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+		reg_PC_CURRENT                             = reg_PC_NEXT                            ;
+		reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
+		reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
+		reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
+		reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
+
+		for (uint32_t i=0; i<_param->_nb_instruction; i++)
+		reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
+	    
+		reg_PC_NEXT_VAL                            = reg_PC_NEXT_NEXT_VAL       ;
+		// if pc_next_next is not valid : don't erase PC_NEXT and PC_NEXT_IS_DS_TAKE : this register is send a the predict (to compute pc_next)
+		if (reg_PC_NEXT_NEXT_VAL)
+		  {
+		    reg_PC_NEXT                            = reg_PC_NEXT_NEXT           ;
+		    reg_PC_NEXT_IS_DS_TAKE                 = reg_PC_NEXT_NEXT_IS_DS_TAKE;
+		  }
+		
+		// invalid next next pc
+		reg_PC_NEXT_NEXT_VAL                       = 0;
 	      }
 
-	    reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
-	    reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
-	    reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
-
-	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
-	      reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
-
-	    // have not next pc
-	    reg_PC_NEXT_VAL                            = 0;
 	  }
 	
-	// =========================================
-	// ===== PREDICT ===========================
-	// =========================================
-	bool new_pc_current = not reg_PC_CURRENT_VAL;
-	if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
-	  if (new_pc_current)
-	    {
-	      reg_PC_CURRENT_VAL                         = 1;
-	      reg_PC_CURRENT                             = PORT_READ(in_PREDICT_PC_NEXT                    );
-	      reg_PC_CURRENT_IS_DS_TAKE                  = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
-	      if (_param->_have_port_instruction_ptr)
-	      reg_PC_CURRENT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
-	      reg_PC_CURRENT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
-	      if (_param->_have_port_branch_update_prediction_id)
-	      reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
-
-// #error "INSTRUCTION_ENABLE : ERROR implémentation, remplacer PC_PREVIOUS par PC_NEXT_NEXT"
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
-	    }
-	  else
-	    {
-	      reg_PC_NEXT_VAL                         = 1;
-	      reg_PC_NEXT                             = PORT_READ(in_PREDICT_PC_NEXT                    );
-	      reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
-	      if (_param->_have_port_instruction_ptr)
-	      reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
-	      reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
-	      if (_param->_have_port_branch_update_prediction_id)
-	      reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
-
-	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
-		reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
-	    }
 
 	// =========================================
@@ -104,22 +110,35 @@
 	if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
 	  {
-	    reg_PC_CURRENT_VAL                         = 1;
-	    reg_PC_CURRENT                             = PORT_READ(in_EVENT_ADDRESS);
+	    log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction");
+	    reg_PC_CURRENT_VAL                      = 0;
+	    reg_PC_NEXT_VAL                         = 1;
+	    reg_PC_NEXT                             = PORT_READ(in_EVENT_ADDRESS);
 	    // Event is never is ds_take :
 	    //  * branch miss speculation : can't be place a branch in delay slot
 	    //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
 	    //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
-	    reg_PC_CURRENT_IS_DS_TAKE                  = 0;
-	    reg_PC_CURRENT_INST_IFETCH_PTR             = 0;
-	    reg_PC_CURRENT_BRANCH_STATE                = BRANCH_STATE_NONE;
-	    reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = 0;
+	    reg_PC_NEXT_IS_DS_TAKE                  = 0;
+// 	    reg_PC_NEXT_INST_IFETCH_PTR             = 0;
+// 	    reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
+// 	    reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
 	    
-	    reg_PC_CURRENT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
-	    for (uint32_t i=1; i<_param->_nb_instruction; i++)
-	      reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = 0;
+// 	    reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
+// 	    for (uint32_t i=1; i<_param->_nb_instruction; i++)
+// 	      reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
 
-	    reg_PC_NEXT_VAL                            = 0; // cancel all prediction (event is send at the predict unit)
+	    reg_PC_NEXT_NEXT_VAL                    = 0; // cancel all prediction (event is send at the predict unit)
+
+#ifdef STATISTICS
+	    (*_stat_nb_transaction_event) ++;
+#endif
 	  }
       }
+
+#if DEBUG >= DEBUG_TRACE
+    log_printf(TRACE,Address_management,FUNCTION,"Address_Management : ");
+    log_printf(TRACE,Address_management,FUNCTION,"Current   : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT);
+    log_printf(TRACE,Address_management,FUNCTION,"Next      : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT);    
+    log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT);    
+#endif 
 
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
