Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Types.h	(revision 85)
@@ -66,4 +66,19 @@
 }; // end namespace core
 }; // end namespace behavioural
+  
+  template<> inline std::string toString<morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t>(const morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::ifetch_queue_state_t& x)
+  {
+    switch (x)
+      {
+      case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_EMPTY          : return "empty"         ; break;
+//    case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_WAIT_REQ       : return "wait_req"      ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_WAIT_RSP       : return "wait_rsp"      ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_HAVE_RSP       : return "have_rsp"      ; break;
+      case morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : return "error_wait_rsp"; break;
+      default    : return ""      ; break;
+      }
+  };
+
+
 }; // end namespace morpheo              
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp	(revision 85)
@@ -34,4 +34,7 @@
     else
       {
+	log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS));
+    
+
 	// ==========================================================
 	// =====[ ADDRESS ]==========================================
@@ -55,4 +58,5 @@
 		_queue[reg_PTR_WRITE]->_instruction_enable [i]      = enable;
 	      }
+
 	    _queue[reg_PTR_WRITE]->_address                     = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS        );
 	    _queue[reg_PTR_WRITE]->_inst_ifetch_ptr             = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR            ):0;
@@ -133,13 +137,16 @@
 	  }
 
-// 	log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_WRITE : %d",reg_PTR_WRITE);
-// 	log_printf(TRACE,Ifetch_queue,FUNCTION,"reg_PTR_READ  : %d",reg_PTR_READ );
-// 	for (uint32_t i=0; i<_param->_size_queue; i++)
-// 	  {
-// 	    log_printf(TRACE,Ifetch_queue,FUNCTION,"[%d] %d %.8x %d - %d %d %d", i, _queue [i]->_state, _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
-
-// 	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
-// 	      log_printf(TRACE,Ifetch_queue,FUNCTION,"  * %d %.8x", _queue [i]->_instruction_enable[i], _queue [i]->_instruction[i]);
-// 	  }
+#if DEBUG >= DEBUG_TRACE
+	log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue");
+	log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE);
+	log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ  : %d",reg_PTR_READ );
+	for (uint32_t i=0; i<_param->_size_queue; i++)
+	  {
+	    log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception);
+	    
+	    for (uint32_t j=0; j<_param->_nb_instruction; j++)
+	      log_printf(TRACE,Ifetch_queue,FUNCTION,"    * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]);
+	  }
+#endif
 
 #ifdef STATISTICS
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/configuration.cfg	(revision 85)
@@ -1,1 +1,2 @@
 Ifetch_unit_Glue
+30	30	+32	# size_address
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp	(revision 85)
@@ -8,5 +8,5 @@
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/include/test.h"
 
-#define NB_PARAMS 0
+#define NB_PARAMS 1
 
 void usage (int argc, char * argv[])
@@ -14,5 +14,5 @@
   err (_("<Usage> %s name_instance list_params.\n"),argv[0]);
   err (_("list_params is :\n"));
-  err (_(" * ()\n"));
+  err (_(" * size_address (uint32_t)\n"));
 
   exit (1);
@@ -30,7 +30,6 @@
   uint32_t x = 1;
 
-  string name = argv[x++];
-//const uint32_t size_data = atoi(argv[x++]);
-//const uint32_t nb_port   = atoi(argv[x++]);
+  string   name = argv[x++];
+  uint32_t _size_address = fromString<uint32_t>(argv[x++]);
 
   int _return = EXIT_SUCCESS;
@@ -38,7 +37,5 @@
     {
       morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters
-	(//size_data,
-	 //nb_port  
-        );
+	(_size_address);
       
       msg(_("%s"),param->print(1).c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp	(revision 85)
@@ -47,4 +47,7 @@
   ALLOC_SC_SIGNAL( in_ICACHE_REQ_QUEUE_ACK  ," in_ICACHE_REQ_QUEUE_ACK  ",Tcontrol_t);
   ALLOC_SC_SIGNAL(out_ICACHE_REQ_TYPE       ,"out_ICACHE_REQ_TYPE       ",Ticache_type_t);
+  ALLOC_SC_SIGNAL(out_ICACHE_REQ_ADDRESS        ,"out_ICACHE_REQ_ADDRESS        ",Taddress_t);
+  ALLOC_SC_SIGNAL( in_ICACHE_REQ_ADDRESS_ADDRESS," in_ICACHE_REQ_ADDRESS_ADDRESS",Taddress_t);
+  ALLOC_SC_SIGNAL(out_ICACHE_REQ_QUEUE_ADDRESS  ,"out_ICACHE_REQ_QUEUE_ADDRESS  ",Taddress_t);
   ALLOC_SC_SIGNAL( in_EVENT_VAL             ," in_EVENT_VAL             ",Tcontrol_t);
   ALLOC_SC_SIGNAL(out_EVENT_ADDRESS_VAL     ,"out_EVENT_ADDRESS_VAL     ",Tcontrol_t);
@@ -69,4 +72,7 @@
   INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS_ACK);
   INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_QUEUE_ACK  );
+  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_ADDRESS        );
+  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_ICACHE_REQ_ADDRESS_ADDRESS);
+  INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_QUEUE_ADDRESS  );
   INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue,out_ICACHE_REQ_TYPE       );
   INSTANCE_SC_SIGNAL(_Ifetch_unit_Glue, in_EVENT_VAL             );
@@ -127,4 +133,7 @@
   delete out_ICACHE_REQ_ADDRESS_ACK;
   delete  in_ICACHE_REQ_QUEUE_ACK  ;
+  delete out_ICACHE_REQ_ADDRESS        ;
+  delete  in_ICACHE_REQ_ADDRESS_ADDRESS;
+  delete out_ICACHE_REQ_QUEUE_ADDRESS  ;
   delete out_ICACHE_REQ_TYPE       ;
   delete  in_EVENT_VAL             ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Ifetch_unit_Glue.h	(revision 85)
@@ -72,4 +72,8 @@
     
   public    : SC_OUT(Ticache_type_t       ) * out_ICACHE_REQ_TYPE        ;
+
+  public    : SC_OUT(Taddress_t           ) * out_ICACHE_REQ_ADDRESS        ;
+  public    : SC_IN (Taddress_t           ) *  in_ICACHE_REQ_ADDRESS_ADDRESS;
+  public    : SC_OUT(Taddress_t           ) * out_ICACHE_REQ_QUEUE_ADDRESS  ;
 
     // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h	(revision 85)
@@ -24,7 +24,8 @@
   {
     //-----[ fields ]------------------------------------------------------------
+  public : uint32_t _size_address;
 
     //-----[ methods ]-----------------------------------------------------------
-  public : Parameters  ();
+  public : Parameters  (uint32_t size_address);
 //   public : Parameters  (Parameters & param) ;
   public : ~Parameters () ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp	(revision 85)
@@ -88,5 +88,7 @@
 	sensitive << (*(in_ICACHE_REQ_ADDRESS_VAL))
 		  << (*(in_ICACHE_REQ_ACK        ))
-		  << (*(in_ICACHE_REQ_QUEUE_ACK  ));
+		  << (*(in_ICACHE_REQ_QUEUE_ACK  ))
+		  << (*(in_ICACHE_REQ_ADDRESS_ADDRESS))
+	  ;
 	
 # ifdef SYSTEMCASS_SPECIFIC
@@ -100,4 +102,8 @@
 	(*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_QUEUE_ACK  ));
 	(*(out_ICACHE_REQ_ADDRESS_ACK)) (*( in_ICACHE_REQ_ACK        ));
+
+	(*(out_ICACHE_REQ_ADDRESS      )) (*( in_ICACHE_REQ_ADDRESS_ADDRESS));
+	(*(out_ICACHE_REQ_QUEUE_ADDRESS)) (*( in_ICACHE_REQ_ADDRESS_ADDRESS));
+
 # endif    
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp	(revision 85)
@@ -60,11 +60,14 @@
       ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction Cache request.");
 
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL        ,"val"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL,"address_val",Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL  ,"queue_val"  ,Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK        ,"ack"        ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK,"address_ack",Tcontrol_t,1);
-      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK  ,"queue_ack"  ,Tcontrol_t,1);
-      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE       ,"type"       ,Ticache_type_t,_param->_size_icache_type);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_VAL            ,"val"            ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_VAL    ,"address_val"    ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_VAL      ,"queue_val"      ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ACK            ,"ack"            ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS_ACK    ,"address_ack"    ,Tcontrol_t,1);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK      ,"queue_ack"      ,Tcontrol_t,1);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE           ,"type"           ,Ticache_type_t,_param->_size_icache_type);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS        ,"address"        ,Taddress_t,_param->_size_address);
+      ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_address);
+      ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS  ,"queue_address"  ,Taddress_t,_param->_size_address);
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp	(revision 85)
@@ -35,4 +35,7 @@
 	delete     in_ICACHE_REQ_QUEUE_ACK   ;
 	delete    out_ICACHE_REQ_TYPE        ;
+	delete    out_ICACHE_REQ_ADDRESS         ;
+	delete     in_ICACHE_REQ_ADDRESS_ADDRESS ;
+	delete    out_ICACHE_REQ_QUEUE_ADDRESS   ;
 	
 	delete     in_EVENT_VAL              ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_genMealy_icache_req.cpp	(revision 85)
@@ -31,4 +31,8 @@
     PORT_WRITE(out_ICACHE_REQ_ADDRESS_ACK, ack         and queue_ack); // cache can accept a new transaction and queue have a slot empty
     PORT_WRITE(out_ICACHE_REQ_QUEUE_VAL  , address_val and ack); // cache can accept a new transaction and the address is valid
+
+    Taddress_t address     = PORT_READ(in_ICACHE_REQ_ADDRESS_ADDRESS);
+    PORT_WRITE(out_ICACHE_REQ_ADDRESS      ,address);
+    PORT_WRITE(out_ICACHE_REQ_QUEUE_ADDRESS,address);
     
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp	(revision 85)
@@ -19,7 +19,10 @@
 #undef  FUNCTION
 #define FUNCTION "Ifetch_unit_Glue::Parameters"
-  Parameters::Parameters ()
+  Parameters::Parameters (uint32_t size_address)
   {
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin");
+
+    _size_address = size_address;
+
     test();
     log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp	(revision 85)
@@ -27,5 +27,5 @@
 
     xml.balise_open("ifetch_unit_glue");
-//  xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end();
+    xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end();
     xml.balise_close();
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config.cfg	(revision 85)
@@ -3,3 +3,3 @@
 1	8	*2	# _nb_instruction               
 1	1	*2	# _size_branch_update_prediction
-32	32	*2	# _size_general_data            
+30	30	*2	# _size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/config_min.cfg	(revision 85)
@@ -3,3 +3,3 @@
 1	1	*2	# nb_instruction               
 1	1	*2	# size_branch_update_prediction
-32	32	*2	# size_general_data            
+30	30	*2	# size_general_data            
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp	(revision 85)
@@ -7,10 +7,27 @@
  */
 
-#define NB_ITERATION  1
+#define NB_ITERATION  128
 #define CYCLE_MAX     (128*NB_ITERATION)
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/include/test.h"
+#include "../../../../../../../../Environment/Queue/include/Sort_Queue.h"
 #include "Common/include/Test.h"
 #include "Behavioural/include/Allocation.h"
+
+//using namespace environment;
+using namespace environment::queue;
+
+class cache_req_t
+{
+public : Tpacket_t  packet;
+public : Taddress_t address;
+
+public : cache_req_t (Tpacket_t  packet,
+		      Taddress_t address)
+  {
+    this->packet  = packet ;
+    this->address = address;
+  }
+};
 
 void test (string name,
@@ -20,5 +37,5 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1024);
 #endif
 
@@ -142,6 +159,47 @@
   srand(seed);
 
+  const  int32_t percent_transaction_icache_req = 75;
+  const  int32_t percent_transaction_icache_rsp = 75;
+  const  int32_t percent_transaction_predict    = 75;
+  const  int32_t percent_transaction_event      =  5;
+  const  int32_t percent_hit                    = 90;
+  const uint32_t delay_miss_min                 =  5;
+  const uint32_t delay_miss_max                 = 10;
+
   SC_START(0);
   LABEL("Initialisation");
+
+  uint32_t        jump          = 7 ;// packet
+  uint32_t        nb_packet_in  = 1;
+  uint32_t        nb_packet_out = 1;
+
+  Tcontrol_t      c_val   = false;
+  Tcontrol_t      n_val   = false;
+  Tcontrol_t      nn_val  = false;
+
+  Tgeneral_data_t c_addr  = 0x100;
+  Tgeneral_data_t n_addr  = 0x100;
+  Tgeneral_data_t nn_addr = 0x100;
+
+  Tcontrol_t      c_enable [_param->_nb_instruction];
+  Tcontrol_t      n_enable [_param->_nb_instruction];
+
+  Tcontrol_t      c_is_ds_take   = 0;
+  Tcontrol_t      n_is_ds_take   = 0;		
+  Tcontrol_t      nn_is_ds_take  = 0;
+
+  bool            slot_use [_param->_size_queue];
+
+  environment::queue::Parameters * param_cache = new environment::queue::Parameters(_param->_size_queue);
+  Sort_Queue<cache_req_t*>       * cache       = new Sort_Queue<cache_req_t*>      ("cache",param_cache);
+
+  cache->reset();
+
+  for (uint32_t i=0; i<_param->_size_queue; i++)
+    slot_use [i] = false;
+
+  c_enable [0] = 1;
+  for (uint32_t i=1; i<_param->_nb_instruction; i++)
+    c_enable [i] = 0;
 
   LABEL("Reset");
@@ -150,4 +208,25 @@
   in_NRESET->write(1);  
 
+  LABEL("Test no out val/ack");
+  
+  TEST(Tcontrol_t,out_ICACHE_REQ_VAL->read(), 0);
+  TEST(Tcontrol_t,out_ICACHE_RSP_ACK->read(), 1);
+  TEST(Tcontrol_t,out_PREDICT_VAL   ->read(), 1);
+  TEST(Tcontrol_t,out_EVENT_ACK     ->read(), 1);
+
+  for (uint32_t i=0; i<_param->_nb_instruction; i++)
+    TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0);
+
+  LABEL("Send Reset");
+  do 
+    {
+      in_EVENT_VAL    ->write(1);
+      in_EVENT_ADDRESS->write(n_addr);
+      SC_START(1);  
+    } while (out_EVENT_ACK->read() == false);
+  in_EVENT_VAL    ->write(0);
+
+  n_val = 1;
+
   LABEL("Loop of Test");
 
@@ -156,5 +235,212 @@
       LABEL("Iteration %d",iteration);
 
-      SC_START(100);
+      // PREDICT
+      {
+	in_PREDICT_ACK  ->write((rand()%100)<percent_transaction_predict);
+	
+	SC_START(0);
+
+	Taddress_t addr  = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
+
+	uint32_t   begin = addr%_param->_nb_instruction;
+	uint32_t   end   = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
+	Tcontrol_t take  = (nb_packet_in%jump)==0;
+	
+	if (take)
+	  addr += 0x100;
+	else
+	  addr += end-begin+1;
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	in_PREDICT_INSTRUCTION_ENABLE     [i] ->write((i>=begin) and (i<=end));
+	in_PREDICT_PC_NEXT                    ->write(addr);
+	in_PREDICT_PC_NEXT_IS_DS_TAKE         ->write(take);
+	in_PREDICT_INST_IFETCH_PTR            ->write(0);
+	in_PREDICT_BRANCH_STATE               ->write(0);
+	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
+      }
+
+      // DECOD
+      {
+	uint32_t nb_decod = (rand()%_param->_nb_instruction);
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  in_DECOD_ACK [i]->write(i<=nb_decod);
+      }
+
+      // EVENT
+      in_EVENT_VAL    ->write((rand()%100)<percent_transaction_event  );
+      in_EVENT_ADDRESS->write(0x100);
+
+      // ICACHE_REQ
+      in_ICACHE_REQ_ACK->write((rand()%100)<percent_transaction_icache_req);
+
+      // ICACHE_RSP
+      {
+	Tcontrol_t val = false;
+	if (not cache->empty())
+	  {
+	    slot_t<cache_req_t *> cache_rsp = cache->read();
+
+	    val = (cache_rsp._delay == 0);
+	    
+	    Tpacket_t  packet  = cache_rsp._data->packet ;
+	    Taddress_t address = cache_rsp._data->address;
+	    
+	    in_ICACHE_RSP_PACKET_ID      ->write(packet);
+	    for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	    in_ICACHE_RSP_INSTRUCTION [i]->write(address+i);
+	    in_ICACHE_RSP_ERROR          ->write(0);
+	  }
+
+	in_ICACHE_RSP_VAL->write(val);
+      }
+
+      //-------------------------------------------------
+      SC_START(0);
+      //-------------------------------------------------
+
+      if (out_ICACHE_REQ_VAL->read() and in_ICACHE_REQ_ACK->read())
+	{
+	  LABEL("ICACHE_REQ : Transaction accepted");
+
+	  Tpacket_t  packet  = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0;
+	  Taddress_t address = out_ICACHE_REQ_ADDRESS->read();
+
+	  TEST(bool      ,slot_use[packet], false);
+	  TEST(Taddress_t,address         ,c_addr);
+
+	  slot_use[packet] = true;
+
+	  uint32_t delay;
+	  if ((rand()%100)<percent_hit)
+	    delay = 1;
+	  else
+	    delay = delay_miss_min + (rand()%(delay_miss_max-delay_miss_min+1));
+
+	  cache_req_t * cache_req = new cache_req_t(packet,address);
+	  cache->push(delay,cache_req);
+
+	  c_val = 0;
+	  nb_packet_in ++;
+	}
+
+      {
+	bool find=false;
+
+	Taddress_t addr=out_DECOD_ADDRESS->read();
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  if (out_DECOD_VAL[i]->read() and in_DECOD_ACK [i]->read())
+	    {
+	      Tinstruction_t inst = out_DECOD_INSTRUCTION[i]->read();
+	      LABEL("DECOD [%d]  : Transaction accepted",i);
+	      LABEL("  address     : 0x%x",addr);
+	      LABEL("  instruction : 0x%x",inst);
+
+	      find = true;
+	      TEST(Tinstruction_t,inst,addr+i);
+	    }
+
+	if (find)
+	  {
+	    if (_param->_have_port_instruction_ptr)
+	    TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR            ->read(), 0);
+	    TEST(Tbranch_state_t   , out_DECOD_BRANCH_STATE               ->read(), 0);
+	    if (_param->_have_port_branch_update_prediction_id)
+	    TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0);
+	    TEST(Texception_t      , out_DECOD_EXCEPTION                  ->read(), 0);
+	  }
+      }
+      
+      if (in_ICACHE_RSP_VAL->read() and out_ICACHE_RSP_ACK->read())
+	{
+	  LABEL("ICACHE_RSP : Transaction accepted");
+
+	  slot_use[cache->read()._data->packet] = false;
+
+	  cache->pop();
+	}
+
+      if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
+	{
+	  LABEL("PREDICT    : Transaction accepted");
+
+	  if (c_val)
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS          ->read(),c_addr      );
+	  TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT           ->read(),n_addr      );
+	  TEST(Tcontrol_t        ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
+
+	  nn_val        = true;
+	  nn_addr       = in_PREDICT_PC_NEXT           ->read();
+	  nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
+	
+	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  n_enable [i]  = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
+	}
+
+      if (not c_val)
+	{
+	  if (n_val and nn_val)
+	    {
+	      c_val        = 1;
+	      c_addr       = n_addr;
+	      c_is_ds_take = n_is_ds_take;
+
+	      for (uint32_t i=0; i<_param->_nb_instruction; i++)
+		c_enable [i] = n_enable [i];
+	      
+	      n_val        = 1;
+	      n_addr       = nn_addr;
+	      n_is_ds_take = nn_is_ds_take;
+	      
+	      nn_val       = 0;
+	    }
+	}
+
+      if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
+	{
+	  LABEL("EVENT      : Transaction accepted");
+
+	  c_val           = false;
+	  n_val           = true;
+	  nn_val          = false;
+
+	  n_addr         = in_EVENT_ADDRESS->read();
+	  n_is_ds_take   = 0;
+
+	  n_enable [0] = 1;
+	  for (uint32_t i=1; i<_param->_nb_instruction; i++)
+	    n_enable [i] = 0;
+	}
+
+      
+      {
+	string str_c_enable = "";
+	string str_n_enable = "";
+
+	for (uint32_t i=0; i<_param->_nb_instruction; i++)
+	  {
+	    str_c_enable += " " + toString(c_enable [i]);
+	    str_n_enable += " " + toString(n_enable [i]);
+	  }
+
+	LABEL("-----------------------------------");
+	LABEL("  * nb_packet_in  : %d",nb_packet_in);
+	LABEL("  * nb_packet_out : %d",nb_packet_out);
+	LABEL("  * pc   : %d %d %.8x %s",c_val  ,c_is_ds_take , c_addr ,str_c_enable.c_str());
+	if (nn_val)
+	  {
+	LABEL("  * pc+4 : %d %d %.8x %s",n_val  ,n_is_ds_take , n_addr ,str_n_enable.c_str());
+	  }
+	else
+	  {
+	LABEL("  * pc+4 : %d %d %.8x"   ,n_val  ,n_is_ds_take , n_addr );
+	  }
+	LABEL("  * pc+8 : %d %d %.8x"   ,nn_val ,nn_is_ds_take, nn_addr);
+	LABEL("-----------------------------------");
+      }
+
+      SC_START(1);
+      cache->transition();
     }
 
@@ -210,4 +496,7 @@
   delete    out_EVENT_ACK                           ;
   delete     in_EVENT_ADDRESS                       ;
+
+  delete    param_cache;
+  delete    cache;
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp	(revision 85)
@@ -213,39 +213,38 @@
 
       {
-	dest = _name;
-
-#ifdef POSITION
-	_component->interface_map (src ,"address",
-				   dest,"icache_req");
-	_component->interface_map (src                     ,"address",
-				   dest+"_ifetch_unit_glue","address");
-#endif
+	dest = _name+"_ifetch_queue";
 
 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  {
 #ifdef POSITION
-	    _component->interface_map (src                 ,"address_"+toString(i),
-				       dest+"_ifetch_queue","address_"+toString(i));
-#endif
-	    PORT_MAP(_component,src                 ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
-		                dest+"_ifetch_queue", "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
+	    _component->interface_map (src ,"address_"+toString(i),
+				       dest,"address_"+toString(i));
+#endif
+	    COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
+		                     dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
 	  }
 
-	PORT_MAP(_component,src ,"out_ADDRESS_VAL"                        ,
-		            dest+"_ifetch_unit_glue", "in_ICACHE_REQ_ADDRESS_VAL"         );
-	PORT_MAP(_component,src , "in_ADDRESS_ACK"                        ,
-		            dest+"_ifetch_unit_glue","out_ICACHE_REQ_ADDRESS_ACK"         );
-	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS"        ,
-		            dest,"out_ICACHE_REQ_ADDRESS");
-	PORT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS"        ,
-		            dest+"_ifetch_queue", "in_ADDRESS_INSTRUCTION_ADDRESS"        );
 	if (_param->_have_port_instruction_ptr)
-	PORT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR"            ,
-		            dest+"_ifetch_queue", "in_ADDRESS_INST_IFETCH_PTR"            );
-	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE"               ,
-		            dest+"_ifetch_queue", "in_ADDRESS_BRANCH_STATE"               );
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR"            ,
+		                 dest, "in_ADDRESS_INST_IFETCH_PTR"            );
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE"               ,
+		                 dest, "in_ADDRESS_BRANCH_STATE"               );
 	if (_param->_have_port_branch_update_prediction_id)
-	PORT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
-		            dest+"_ifetch_queue", "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
+		                 dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
+
+	dest = _name+"_ifetch_unit_glue";
+
+#ifdef POSITION
+	_component->interface_map (src ,"address",
+				   dest,"address");
+#endif
+
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL"           ,
+		                 dest, "in_ICACHE_REQ_ADDRESS_VAL");
+	COMPONENT_MAP(_component,src , "in_ADDRESS_ACK"           ,
+		                 dest,"out_ICACHE_REQ_ADDRESS_ACK");
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS",
+		                 dest, "in_ICACHE_REQ_ADDRESS_ADDRESS");
       }
 
@@ -302,7 +301,10 @@
 #endif
 
-	PORT_MAP(_component,src , "in_EVENT_VAL"    ,dest ,"out_EVENT_ADDRESS_VAL");
-	PORT_MAP(_component,src ,"out_EVENT_ACK"    ,dest , "in_EVENT_ADDRESS_ACK");
-	PORT_MAP(_component,src , "in_EVENT_ADDRESS",_name, "in_EVENT_ADDRESS");
+	COMPONENT_MAP(_component,src , "in_EVENT_VAL"    ,dest ,"out_EVENT_ADDRESS_VAL");
+	COMPONENT_MAP(_component,src ,"out_EVENT_ACK"    ,dest , "in_EVENT_ADDRESS_ACK");
+
+
+	dest = _name;
+	PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS");
       }
     }
@@ -333,4 +335,8 @@
 #endif
 
+	if (_param->_have_port_queue_ptr)
+	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID"            ,
+		            dest,"out_ICACHE_REQ_PACKET_ID"               );
+
 	for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  {
@@ -339,26 +345,19 @@
 				       dest+"_address_management","address_"+toString(i));
 #endif
-	    
-	    PORT_MAP(_component,src                       , "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE"         ,
-		                dest+"_address_management","out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE"         );
+
+	    //out_ADDRESS_INSTRUCTION_ENABLE - address_management
 	  }
 
-	PORT_MAP(_component,src , "in_ADDRESS_VAL"                        ,
-		            dest+"_ifetch_unit_glue"  ,"out_ICACHE_REQ_QUEUE_VAL"                        );
-	PORT_MAP(_component,src ,"out_ADDRESS_ACK"                        ,
-		            dest+"_ifetch_unit_glue"  , "in_ICACHE_REQ_QUEUE_ACK"                        );
-	if (_param->_have_port_queue_ptr)
-	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID"            ,
-		            dest                      ,"out_ICACHE_REQ_PACKET_ID"               );
-	PORT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS"        ,
-		            dest+"_address_management","out_ADDRESS_INSTRUCTION_ADDRESS"        );
-	if (_param->_have_port_instruction_ptr)
-	PORT_MAP(_component,src , "in_ADDRESS_INST_IFETCH_PTR"            ,
-		            dest+"_address_management","out_ADDRESS_INST_IFETCH_PTR"            );
-	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_STATE"               ,
-		            dest+"_address_management","out_ADDRESS_BRANCH_STATE"               );
-	if (_param->_have_port_branch_update_prediction_id)
-	PORT_MAP(_component,src , "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
-		            dest+"_address_management","out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
+	dest = _name+"_ifetch_unit_glue";
+
+	COMPONENT_MAP(_component,src , "in_ADDRESS_VAL"         ,
+		                 dest,"out_ICACHE_REQ_QUEUE_VAL");
+	COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK"         ,
+		                 dest, "in_ICACHE_REQ_QUEUE_ACK");
+	COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS",
+		                 dest,"out_ICACHE_REQ_QUEUE_ADDRESS");
+	// in_ADDRESS_INST_IFETCH_PTR             - address_management
+	// in_ADDRESS_BRANCH_STATE                - address_management
+	// in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management
       }
 
@@ -428,6 +427,6 @@
 #endif
 
-	PORT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
-	PORT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
+	COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
+	COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
       }
     }
@@ -458,11 +457,16 @@
 #endif
 	
-	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL"        ,dest                      ,"out_ICACHE_REQ_VAL");
-	PORT_MAP(_component,src , "in_ICACHE_REQ_ADDRESS_VAL",dest+"_address_management","out_ADDRESS_VAL");
-	PORT_MAP(_component,src ,"out_ICACHE_REQ_QUEUE_VAL"  ,dest+"_ifetch_queue"      , "in_ADDRESS_VAL"  );
-	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK"        ,dest                      , "in_ICACHE_REQ_ACK");
-	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS_ACK",dest+"_address_management", "in_ADDRESS_ACK");
-	PORT_MAP(_component,src , "in_ICACHE_REQ_QUEUE_ACK"  ,dest+"_ifetch_queue"      ,"out_ADDRESS_ACK");
-	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE"       ,dest                      ,"out_ICACHE_REQ_TYPE");
+	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL"    ,dest,"out_ICACHE_REQ_VAL");
+	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK"    ,dest, "in_ICACHE_REQ_ACK");
+	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE"   ,dest,"out_ICACHE_REQ_TYPE");
+	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS");
+
+	// in_ICACHE_REQ_ADDRESS_VAL     - address_management
+	//out_ICACHE_REQ_QUEUE_VAL       - ifetch_queue      
+	//out_ICACHE_REQ_ADDRESS_ACK     - address_management
+	// in_ICACHE_REQ_QUEUE_ACK       - ifetch_queue      
+	// in_ICACHE_REQ_ADDRESS_ADDRESS - address_management
+	//out_ICACHE_REQ_QUEUE_ADDRESS   - ifetch_queue      
+
       }
 
@@ -476,14 +480,16 @@
 
 	PORT_MAP(_component,src , "in_EVENT_VAL"        ,dest                      , "in_EVENT_VAL"        );
-	PORT_MAP(_component,src ,"out_EVENT_ADDRESS_VAL",dest+"_address_management", "in_EVENT_VAL"        );
-	PORT_MAP(_component,src ,"out_EVENT_QUEUE_VAL"  ,dest+"_ifetch_queue"      , "in_EVENT_RESET_VAL"  );
 	PORT_MAP(_component,src ,"out_EVENT_ACK"        ,dest                      ,"out_EVENT_ACK"        );
-	PORT_MAP(_component,src , "in_EVENT_ADDRESS_ACK",dest+"_address_management","out_EVENT_ACK"        );
-	PORT_MAP(_component,src , "in_EVENT_QUEUE_ACK"  ,dest+"_ifetch_queue"      ,"out_EVENT_RESET_ACK"  );
+
+	//out_EVENT_ADDRESS_VAL - address_management
+	//out_EVENT_QUEUE_VAL   - ifetch_queue      
+	// in_EVENT_ADDRESS_ACK - address_management
+	// in_EVENT_QUEUE_ACK   - ifetch_queue      
       }
     }
 
     // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 
-     _component->test_map();
+    if (DEBUG_Ifetch_unit == true)
+      _component->test_map();
 
 #ifdef POSITION
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp	(revision 84)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp	(revision 85)
@@ -49,5 +49,5 @@
        size_address                 );
     _param_ifetch_unit_glue   = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::  Parameters
-      ();
+      (size_address);
     
     log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
