Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 88)
@@ -39,4 +39,10 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
+#if DEBUG_Load_store_unit == true
+    log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+    std::cout << *param << std::endl;
+#endif    
+
 #ifdef SYSTEMC
     log_printf(INFO,Load_store_unit,FUNCTION,"Allocation");
@@ -46,17 +52,25 @@
 
 #ifdef STATISTICS
-    log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics");
-
-    statistics_declaration(param_statistics);
+    if (usage_is_set(_usage,USE_STATISTICS))
+      {	
+        log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics");
+        
+        statistics_declaration(param_statistics);
+      }
 #endif
 
 #ifdef VHDL
-    // generate the vhdl
-    log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl");
-
-    vhdl();
-#endif
-
-#ifdef SYSTEMC
+    if (usage_is_set(_usage,USE_VHDL))
+      {	
+        // generate the vhdl
+        log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl");
+        
+        vhdl();
+      }
+#endif
+
+#ifdef SYSTEMC
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {	
     // Function pointer
 
@@ -84,5 +98,15 @@
 
     internal_DCACHE_RSP_ACK = 1;
-    PORT_WRITE(out_DCACHE_RSP_ACK, 1);
+    PORT_WRITE(out_DCACHE_RSP_ACK [0], internal_DCACHE_RSP_ACK);
+    for (uint32_t i=1; i<_param->_nb_cache_port; ++i)
+      {
+	PORT_WRITE(out_DCACHE_RSP_ACK [i], 0);
+	PORT_WRITE(out_DCACHE_REQ_VAL [i], 0);
+      }
+
+    for (uint32_t i=1; i<_param->_nb_inst_memory; i++)
+      {
+	PORT_WRITE(out_MEMORY_OUT_VAL [i], 0);
+      }
 
     log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition");
@@ -111,9 +135,16 @@
     dont_initialize ();
     sensitive_neg << *(in_CLOCK);
-    sensitive     << *(in_MEMORY_IN_OPERATION);
-
-#ifdef SYSTEMCASS_SPECIFIC
-    // List dependency information
-    (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION));
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      sensitive << (*(in_MEMORY_IN_VAL       [i]))
+		<< (*(in_MEMORY_IN_OPERATION [i]));
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+//       for (uint32_t x=0; x<_param->_nb_inst_memory; x++)
+	{
+	  (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_VAL       [i]));
+	  (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_OPERATION [i]));
+	}
 #endif    
 
@@ -137,5 +168,5 @@
     // List dependency information
 #endif    
-
+      }
 #endif
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
@@ -149,7 +180,10 @@
 
 #ifdef STATISTICS
-    log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file");
-
-    delete _stat;
+    if (usage_is_set(_usage,USE_STATISTICS))
+      {	
+        log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file");
+        
+        delete _stat;
+      }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 88)
@@ -3,9 +3,10 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -37,5 +38,5 @@
     _interfaces = entity->set_interfaces();
 
-    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
       Interface * interface = _interfaces->set_interface(""
@@ -43,5 +44,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -50,142 +51,106 @@
       in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
     }
-    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("memory_in"
-#ifdef POSITION
-							      ,IN
-							      ,WEST
-							      ,"Instruction from Reservations station"
-#endif
-							      );
+      ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory);
 
-   in_MEMORY_IN_VAL                   = interface->set_signal_valack_in        (VAL);
-  out_MEMORY_IN_ACK                   = interface->set_signal_valack_out       (ACK);
-
-  if (_param->_have_port_context_id)
-   in_MEMORY_IN_CONTEXT_ID            = interface->set_signal_in  <Tcontext_t        > ("context_id"   ,_param->_size_context_id       );
-  if (_param->_have_port_front_end_id)
-   in_MEMORY_IN_FRONT_END_ID          = interface->set_signal_in  <Tcontext_t        > ("front_end_id" ,_param->_size_front_end_id     );
-  if (_param->_have_port_ooo_engine_id)
-   in_MEMORY_IN_OOO_ENGINE_ID         = interface->set_signal_in  <Tcontext_t        > ("ooo_engine_id",_param->_size_ooo_engine_id    );
-  if (_param->_have_port_packet_id)
-   in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"    ,_param->_size_packet_id       );
-   in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
-   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
-   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage
-   if (_param->_have_port_load_queue_ptr)
-   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
-   in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
-   in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
-   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
-   in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
-   in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
-   in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
+      ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL                  ,VAL);
+      ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK                  ,ACK);
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id           );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID        ,"ooo_engine_id"        ,Tcontext_t        ,_param->_size_ooo_engine_id        );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID            ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr              );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation            );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                 );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr      );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr       );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA              ,"data_ra"              ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB              ,"data_rb"              ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC              ,"data_rc"              ,Tspecial_data_t   ,_param->_size_special_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD           ,"num_reg_rd"           ,Tgeneral_address_t,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE           ,"num_reg_re"           ,Tspecial_address_t,1                                  );
     }
 
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("memory_out"
-#ifdef POSITION
-							      ,OUT
-							      ,EAST
-							      ,"Instruction to write queue"
-#endif
-							      );
+      ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory);
 
-      out_MEMORY_OUT_VAL           = interface->set_signal_valack_out(VAL);
-       in_MEMORY_OUT_ACK           = interface->set_signal_valack_in (ACK);
-      if (_param->_have_port_context_id)       
-      out_MEMORY_OUT_CONTEXT_ID    = interface->set_signal_out <Tcontext_t        > ("context_id"    ,_param->_size_context_id       );
-      if (_param->_have_port_front_end_id)     
-      out_MEMORY_OUT_FRONT_END_ID  = interface->set_signal_out <Tcontext_t        > ("front_end_id"  ,_param->_size_front_end_id     );
-      if (_param->_have_port_ooo_engine_id)    
-      out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t        > ("ooo_engine_id" ,_param->_size_ooo_engine_id    );
-      if (_param->_have_port_packet_id)       
-      out_MEMORY_OUT_PACKET_ID     = interface->set_signal_out <Tpacket_t         > ("packet_id"     ,_param->_size_packet_id        );
-//    out_MEMORY_OUT_OPERATION     = interface->set_signal_out <Toperation_t      > ("operation"     ,_param->_size_operation        );
-      out_MEMORY_OUT_TYPE          = interface->set_signal_out <Ttype_t           > ("type"          ,_param->_size_type             );
-      out_MEMORY_OUT_WRITE_RD      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
-      out_MEMORY_OUT_NUM_REG_RD    = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"    ,_param->_size_general_register );
-      out_MEMORY_OUT_DATA_RD       = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"       ,_param->_size_general_data     );
-      out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_re"      ,1                              );
-      out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
-      out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
-      out_MEMORY_OUT_EXCEPTION     = interface->set_signal_out <Texception_t      > ("exception"     ,_param->_size_exception        );
-      out_MEMORY_OUT_NO_SEQUENCE   = interface->set_signal_out <Tcontrol_t        > ("no_sequence"   ,1                              );
-      out_MEMORY_OUT_ADDRESS       = interface->set_signal_out <Tgeneral_data_t   > ("address"       ,_param->_size_general_data     );
+      ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL          ,VAL);
+      ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK          ,ACK);
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID   ,"context_id"    ,Tcontext_t        ,_param->_size_context_id       );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id"  ,Tcontext_t        ,_param->_size_front_end_id     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t        ,_param->_size_ooo_engine_id    );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID    ,"packet_id"     ,Tpacket_t         ,_param->_size_rob_ptr          );
+//    ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION    ,"operation"     ,Toperation_t      ,_param->_size_operation        );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE         ,"type"          ,Ttype_t           ,_param->_size_type             );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD     ,"write_rd"      ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD   ,"num_reg_rd"    ,Tgeneral_address_t,_param->_size_general_register );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD      ,"data_rd"       ,Tgeneral_data_t   ,_param->_size_general_data     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE     ,"write_re"      ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE   ,"num_reg_re"    ,Tspecial_address_t,_param->_size_general_register );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE      ,"data_re"       ,Tspecial_data_t   ,_param->_size_general_data     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION    ,"exception"     ,Texception_t      ,_param->_size_exception        );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE  ,"no_sequence"   ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS      ,"address"       ,Tgeneral_data_t   ,_param->_size_general_data     );
     }
 
-    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("dcache_req"
-#ifdef POSITION
-							      ,OUT
-							      ,NORTH
-							      ,"Request port to dcache"
-#endif
-							      );
+      ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port);
 
-      out_DCACHE_REQ_VAL        = interface->set_signal_valack_out(VAL);
-       in_DCACHE_REQ_ACK        = interface->set_signal_valack_in (ACK);
-       if (_param->_have_port_dcache_context_id)
-      out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t        > ("context_id",_param->_size_dcache_context_id  );
-      out_DCACHE_REQ_PACKET_ID  = interface->set_signal_out <Tpacket_t         > ("packet_id" ,_param->_size_dcache_packet_id   );
-      out_DCACHE_REQ_ADDRESS    = interface->set_signal_out <Tdcache_address_t > ("address"   ,_param->_size_general_data);
-      out_DCACHE_REQ_TYPE       = interface->set_signal_out <Tdcache_type_t    > ("type"      ,_param->_size_dcache_type );
-      out_DCACHE_REQ_WDATA      = interface->set_signal_out <Tdcache_data_t    > ("wdata"     ,_param->_size_general_data);
+      ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL        ,VAL);
+      ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK        ,ACK);
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t       ,_param->_size_dcache_context_id  );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID  ,"packet_id" ,Tpacket_t        ,_param->_size_dcache_packet_id   );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS    ,"address"   ,Tdcache_address_t,_param->_size_general_data);
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE       ,"type"      ,Tdcache_type_t   ,_param->_size_dcache_type );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA      ,"wdata"     ,Tdcache_data_t   ,_param->_size_general_data);
     }
-    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("dcache_rsp"
-#ifdef POSITION
-							      ,IN
-							      ,NORTH
-							      ,"Respons port from dcache"
-#endif
-							      );
+      ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port);
 
-       in_DCACHE_RSP_VAL        = interface->set_signal_valack_in (VAL);
-      out_DCACHE_RSP_ACK        = interface->set_signal_valack_out(ACK);
-       if (_param->_have_port_dcache_context_id)
-       in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in  <Tcontext_t     > ("context_id",_param->_size_dcache_context_id  );
-       in_DCACHE_RSP_PACKET_ID  = interface->set_signal_in  <Tpacket_t      > ("packet_id" ,_param->_size_dcache_packet_id   );
-       in_DCACHE_RSP_RDATA      = interface->set_signal_in  <Tdcache_data_t > ("rdata"     ,_param->_size_general_data);
-       in_DCACHE_RSP_ERROR      = interface->set_signal_in  <Tdcache_error_t> ("error"     ,_param->_size_dcache_error);
+      ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL        ,VAL);
+      ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK        ,ACK);
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t     ,_param->_size_dcache_context_id  );
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID  ,"packet_id" ,Tpacket_t      ,_param->_size_dcache_packet_id   );
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA      ,"rdata"     ,Tdcache_data_t ,_param->_size_general_data);
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR      ,"error"     ,Tdcache_error_t,_param->_size_dcache_error);
     }
-    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-//  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
-      {
-	out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_nb_bypass_memory];
-	if (_param->_have_port_ooo_engine_id)    
-	out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_nb_bypass_memory];
-	out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory];
-	out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_nb_bypass_memory];
-	
-	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
-	  {
-	    Interface_fifo * interface = _interfaces->set_interface("memory_out"
-#ifdef POSITION
-								    ,OUT
-								    ,NORTH
-								    ,"Bypass between the load queue and the reservation station"
-#endif
-								    );
+    {
+      ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory);
 	    
-	    out_BYPASS_MEMORY_VAL           [i] = interface->set_signal_valack_out(VAL);
-	    if (_param->_have_port_ooo_engine_id)
-	    out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t        > ("ooo_engine_id", _param->_size_ooo_engine_id);
-	    out_BYPASS_MEMORY_NUM_REG       [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg"      , _param->_size_general_register);
-	    out_BYPASS_MEMORY_DATA          [i] = interface->set_signal_out <Tgeneral_data_t   > ("data"         , _param->_size_general_data);
-	  }
-      }
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+      ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL           ,VAL);
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t        , _param->_size_ooo_engine_id   );
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG       ,"num_reg"      ,Tgeneral_address_t, _param->_size_general_register);
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA          ,"data"         ,Tgeneral_data_t   , _param->_size_general_data    );
+    }
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+//     internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port];
+
+//     internal_MEMORY_IN_ACK           = new Tcontrol_t      [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_VAL          = new Tcontrol_t      [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_PTR          = new Tlsq_ptr_t      [_param->_nb_inst_memory];
+    
+//     internal_DCACHE_RSP_ACK          = new Tcontrol_t      [_param->_nb_cache_port];
+//     internal_DCACHE_REQ_VAL          = new Tcontrol_t      [_param->_nb_cache_port];
+//     internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port];
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
 #ifdef POSITION
-    _component->generate_file();
+    if (usage_is_set(_usage,USE_POSITION))
+      _component->generate_file();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 88)
@@ -6,9 +6,10 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -28,4 +29,6 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     delete    in_CLOCK ;
@@ -33,74 +36,77 @@
     delete    in_NRESET;
 
-    delete     in_MEMORY_IN_VAL         ;
-    delete    out_MEMORY_IN_ACK         ;
-    if (_param->_have_port_context_id)
-    delete     in_MEMORY_IN_CONTEXT_ID  ;
-    if (_param->_have_port_front_end_id)
-    delete     in_MEMORY_IN_FRONT_END_ID  ;
-    if (_param->_have_port_ooo_engine_id)
-    delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
-    if (_param->_have_port_packet_id)
-    delete     in_MEMORY_IN_PACKET_ID   ;
-    delete     in_MEMORY_IN_OPERATION   ;
-    delete     in_MEMORY_IN_TYPE        ;
-    delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
-    if (_param->_have_port_load_queue_ptr)
-    delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-    delete     in_MEMORY_IN_HAS_IMMEDIAT;
-    delete     in_MEMORY_IN_IMMEDIAT    ;
-    delete     in_MEMORY_IN_DATA_RA     ;
-    delete     in_MEMORY_IN_DATA_RB     ;
-    delete     in_MEMORY_IN_DATA_RC     ;
-    delete     in_MEMORY_IN_WRITE_RD    ;
-    delete     in_MEMORY_IN_NUM_REG_RD  ;
-    delete     in_MEMORY_IN_WRITE_RE    ;
-    delete     in_MEMORY_IN_NUM_REG_RE  ;
+    DELETE1_SIGNAL( in_MEMORY_IN_VAL                  ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL(out_MEMORY_IN_ACK                  ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL( in_MEMORY_IN_CONTEXT_ID           ,_param->_nb_inst_memory,_param->_size_context_id           );
+    DELETE1_SIGNAL( in_MEMORY_IN_FRONT_END_ID         ,_param->_nb_inst_memory,_param->_size_front_end_id         );
+    DELETE1_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID        ,_param->_nb_inst_memory,_param->_size_ooo_engine_id        );
+    DELETE1_SIGNAL( in_MEMORY_IN_PACKET_ID            ,_param->_nb_inst_memory,_param->_size_rob_ptr              );
+    DELETE1_SIGNAL( in_MEMORY_IN_OPERATION            ,_param->_nb_inst_memory,_param->_size_operation            );
+    DELETE1_SIGNAL( in_MEMORY_IN_TYPE                 ,_param->_nb_inst_memory,_param->_size_type                 );
+    DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr      );
+    DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr       );
+    DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT         ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_IMMEDIAT             ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RA              ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RB              ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RC              ,_param->_nb_inst_memory,_param->_size_special_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RD             ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RD           ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RE             ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RE           ,_param->_nb_inst_memory,1                                  );
+
+    DELETE1_SIGNAL(out_MEMORY_OUT_VAL          ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL( in_MEMORY_OUT_ACK          ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL(out_MEMORY_OUT_CONTEXT_ID   ,_param->_nb_inst_memory,_param->_size_context_id       );
+    DELETE1_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory,_param->_size_ooo_engine_id    );
+    DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID    ,_param->_nb_inst_memory,_param->_size_rob_ptr          );
+//  DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION    ,_param->_nb_inst_memory,_param->_size_operation        );
+    DELETE1_SIGNAL(out_MEMORY_OUT_TYPE         ,_param->_nb_inst_memory,_param->_size_type             );
+    DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD     ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD   ,_param->_nb_inst_memory,_param->_size_general_register );
+    DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RD      ,_param->_nb_inst_memory,_param->_size_general_data     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RE     ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RE   ,_param->_nb_inst_memory,_param->_size_general_register );
+    DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RE      ,_param->_nb_inst_memory,_param->_size_general_data     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_EXCEPTION    ,_param->_nb_inst_memory,_param->_size_exception        );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE  ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_ADDRESS      ,_param->_nb_inst_memory,_param->_size_general_data     );
+
+    DELETE1_SIGNAL(out_DCACHE_REQ_VAL        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL( in_DCACHE_REQ_ACK        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id  );
+    DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID  ,_param->_nb_cache_port,_param->_size_dcache_packet_id   );
+    DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS    ,_param->_nb_cache_port,_param->_size_general_data);
+    DELETE1_SIGNAL(out_DCACHE_REQ_TYPE       ,_param->_nb_cache_port,_param->_size_dcache_type );
+    DELETE1_SIGNAL(out_DCACHE_REQ_WDATA      ,_param->_nb_cache_port,_param->_size_general_data);
+
+    DELETE1_SIGNAL( in_DCACHE_RSP_VAL        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL(out_DCACHE_RSP_ACK        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id  );
+    DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID  ,_param->_nb_cache_port,_param->_size_dcache_packet_id   );
+    DELETE1_SIGNAL( in_DCACHE_RSP_RDATA      ,_param->_nb_cache_port,_param->_size_general_data);
+    DELETE1_SIGNAL( in_DCACHE_RSP_ERROR      ,_param->_nb_cache_port,_param->_size_dcache_error);
+
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_VAL           ,_param->_nb_bypass_memory,1);
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory,_param->_size_ooo_engine_id   );
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_NUM_REG       ,_param->_nb_bypass_memory,_param->_size_general_register);
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_DATA          ,_param->_nb_bypass_memory,_param->_size_general_data    );
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
-    delete    out_MEMORY_OUT_VAL       ;
-    delete     in_MEMORY_OUT_ACK       ;
-    if (_param->_have_port_context_id)
-    delete    out_MEMORY_OUT_CONTEXT_ID;
-    if (_param->_have_port_front_end_id)
-    delete    out_MEMORY_OUT_FRONT_END_ID;
-    if (_param->_have_port_ooo_engine_id)
-      delete    out_MEMORY_OUT_OOO_ENGINE_ID;
-    if (_param->_have_port_packet_id)
-    delete    out_MEMORY_OUT_PACKET_ID ;
-//  delete    out_MEMORY_OUT_OPERATION ;
-    delete    out_MEMORY_OUT_TYPE      ;
-    delete    out_MEMORY_OUT_WRITE_RD  ;
-    delete    out_MEMORY_OUT_NUM_REG_RD;
-    delete    out_MEMORY_OUT_DATA_RD   ;
-    delete    out_MEMORY_OUT_WRITE_RE  ;
-    delete    out_MEMORY_OUT_NUM_REG_RE;
-    delete    out_MEMORY_OUT_DATA_RE   ;
-    delete    out_MEMORY_OUT_EXCEPTION ;
-    delete    out_MEMORY_OUT_NO_SEQUENCE;
-    delete    out_MEMORY_OUT_ADDRESS   ;
+//     delete [] internal_MEMORY_IN_ACK          ;
+//     delete [] internal_MEMORY_OUT_VAL         ;
+//     delete [] internal_MEMORY_OUT_SELECT_QUEUE;
+//     delete [] internal_MEMORY_OUT_PTR         ;
     
-    delete    out_DCACHE_REQ_VAL       ;
-    delete     in_DCACHE_REQ_ACK       ;
-    if (_param->_have_port_dcache_context_id)
-    delete    out_DCACHE_REQ_CONTEXT_ID;
-    delete    out_DCACHE_REQ_PACKET_ID ;
-    delete    out_DCACHE_REQ_ADDRESS   ;
-    delete    out_DCACHE_REQ_TYPE      ;
-    delete    out_DCACHE_REQ_WDATA     ;
-    
-    delete     in_DCACHE_RSP_VAL       ;
-    delete    out_DCACHE_RSP_ACK       ;
-    if (_param->_have_port_dcache_context_id)
-    delete     in_DCACHE_RSP_CONTEXT_ID;
-    delete     in_DCACHE_RSP_PACKET_ID ;
-    delete     in_DCACHE_RSP_RDATA     ;
-    delete     in_DCACHE_RSP_ERROR     ;
-    
-    delete [] out_BYPASS_MEMORY_VAL       ;
-    if (_param->_have_port_ooo_engine_id)    
-    delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
-    delete [] out_BYPASS_MEMORY_NUM_REG   ;
-    delete [] out_BYPASS_MEMORY_DATA      ;
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+//     delete [] internal_DCACHE_RSP_ACK         ;
+//     delete [] internal_DCACHE_REQ_VAL         ;
+//     delete [] internal_DCACHE_REQ_SELECT_QUEUE;
+
+//     delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ;
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
     delete    _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp	(revision 88)
@@ -26,5 +26,6 @@
 
 #ifdef STATISTICS
-    _stat->end_cycle();
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
 #endif    
 
@@ -32,5 +33,6 @@
     // Evaluation before read the ouput signal
 //  sc_start(0);
-    _interfaces->testbench();
+    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
+      _interfaces->testbench();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 88)
@@ -27,9 +27,28 @@
 
     // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    
+    // Initialisation
+    internal_MEMORY_IN_PORT = 0;
+    Tcontrol_t ack [_param->_nb_inst_memory];
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      ack [i] = 0;
 
+    // find first valid entry
     // store queue is never full (pointer is manage by rename stage)
-    internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) or not _speculative_access_queue_control->full();
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      if (PORT_READ(in_MEMORY_IN_VAL [i]))
+	{
+	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
 
-    PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK);
+	  if (internal_MEMORY_IN_ACK)
+	    {
+	      ack [i] = 1;
+	      internal_MEMORY_IN_PORT = i;
+	      break; // end
+	    }
+	}
+
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 88)
@@ -4,5 +4,5 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
@@ -26,5 +26,5 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
     Tcontext_t         memory_out_context_id    = 0;
@@ -110,29 +110,30 @@
       }
     // write output
-    PORT_WRITE(out_MEMORY_OUT_VAL          , internal_MEMORY_OUT_VAL);
+    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
 
     if (_param->_have_port_context_id)
-    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   , memory_out_context_id   );
+    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
     if (_param->_have_port_front_end_id)
-    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID , memory_out_front_end_id );
+    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
     if (_param->_have_port_ooo_engine_id)
-    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID, memory_out_ooo_engine_id);
-    if (_param->_have_port_packet_id)
-    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    , memory_out_packet_id    );
-//  PORT_WRITE(out_MEMORY_OUT_OPERATION    , memory_out_operation    );
-    PORT_WRITE(out_MEMORY_OUT_TYPE         , TYPE_MEMORY             );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     , memory_out_write_rd     );
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   , memory_out_num_reg_rd   );
-    PORT_WRITE(out_MEMORY_OUT_DATA_RD      , memory_out_data_rd      );
-//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , memory_out_write_re     );
-//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , memory_out_num_reg_re   );
-//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      , memory_out_data_re      );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , 0);
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , 0);
-    PORT_WRITE(out_MEMORY_OUT_DATA_RE      , 0);
-    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    , memory_out_exception    );
-    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  , 0);
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      , 0);
-    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
+    if (_param->_have_port_rob_ptr)
+    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
+    PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
+    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
+//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
+//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
+//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
+
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
     Tcontext_t        dcache_req_context_id;
@@ -201,11 +202,11 @@
       }
 
-    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
+    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
     if (_param->_have_port_dcache_context_id)
-    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
-    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
-    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
-    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
-    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
     
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 88)
@@ -255,6 +255,6 @@
 	// Interface "MEMORY_IN"
 	//================================================================
-
-        if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and
+	
+        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
             (    internal_MEMORY_IN_ACK  == 1))
           {
@@ -266,10 +266,10 @@
 
 #ifdef DEBUG_TEST
-	    if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY)
+	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
 	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
 #endif
-	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
-	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
-						    PORT_READ(in_MEMORY_IN_DATA_RA ));
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
 	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
 						    
@@ -287,5 +287,5 @@
 		
 		// Write pointer is define in rename stage :
-		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
+		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		log_printf(TRACE,Load_store_unit,FUNCTION,"   * index         : %d",index);
 		
@@ -375,15 +375,15 @@
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"   * Update information");
 
-		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID);
-		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID);
-		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID);
-		    _store_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID   );
+		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
 		    _store_queue [index]._operation            = operation;
-		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
+		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		    _store_queue [index]._address              = address;
 
 		    // reordering data
-		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB), memory_size(operation), 0);
-//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  );
+		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0);
+//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
 		  }
 	      }
@@ -413,16 +413,16 @@
 		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
 		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
-		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID);
-		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID);
-		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID);
-		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);
+		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
 
 		_speculative_access_queue [index]._operation            = operation;
-		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
-		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
+		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		_speculative_access_queue [index]._address              = address;
 		// NOTE : is operation is a load, then they are a result and must write in the register file
 		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
-		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  );
+		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
 
 		_speculative_access_queue [index]._exception            = exception;
@@ -437,5 +437,5 @@
 
         if ((    internal_MEMORY_OUT_VAL  == 1) and
-            (PORT_READ(in_MEMORY_OUT_ACK) == 1))
+            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
           {
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction");
@@ -495,5 +495,5 @@
 
         if ((    internal_DCACHE_REQ_VAL  == 1) and
-            (PORT_READ(in_DCACHE_REQ_ACK) == 1))
+            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
           {
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ");
@@ -598,5 +598,5 @@
 	// Interface "DCACHE_RSP"
 	//================================================================
-        if ((PORT_READ(in_DCACHE_RSP_VAL)== 1) and
+        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
             (    internal_DCACHE_RSP_ACK == 1))
           {
@@ -604,8 +604,8 @@
 
 	    // don't use context_id : because there are one queue for all thread
-	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID); 
-	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID );
-	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     );
-	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     );
+	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
+	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
+	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
+	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
 
 	    log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id);
@@ -662,5 +662,5 @@
 	
 	
-#if DEBUG>=DEBUG_TRACE
+#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
 	// ***** dump store queue
 	std::cout << "Dump STORE_QUEUE :" << std::endl
@@ -694,17 +694,19 @@
 		 << _load_queue[j] << std::endl;
 	  }
-	
 #endif
 	
 #ifdef STATISTICS
-	for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	  if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
-	    (*_stat_use_store_queue) ++;
-	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-	  if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
-	    (*_stat_use_speculative_access_queue) ++;
-	for (uint32_t i=0; i<_param->_size_load_queue; i++)
-	  if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
-	    (*_stat_use_load_queue) ++;
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_size_store_queue; i++)
+              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
+                (*_stat_use_store_queue) ++;
+            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
+                (*_stat_use_speculative_access_queue) ++;
+            for (uint32_t i=0; i<_param->_size_load_queue; i++)
+              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
+                (*_stat_use_load_queue) ++;
+          }
 #endif
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 88)
@@ -26,4 +26,6 @@
 			  Tspeculative_load_t speculative_load       ,
 			  uint32_t            nb_bypass_memory       ,
+			  uint32_t            nb_cache_port          ,
+			  uint32_t            nb_inst_memory         ,
 			  uint32_t            nb_context             ,
 			  uint32_t            nb_front_end           ,
@@ -33,97 +35,120 @@
 			  uint32_t            size_special_data      ,
 			  uint32_t            nb_general_register    ,
-			  uint32_t            nb_special_register    ):
-    _size_store_queue        (size_store_queue       ),
-    _size_load_queue         (size_load_queue        ),
-    _size_speculative_access_queue (size_speculative_access_queue),
-    _nb_port_check           (nb_port_check          ),
-    _speculative_load        (speculative_load       ),
-    _nb_bypass_memory        (nb_bypass_memory       ),
-    _nb_context              (nb_context             ),
-    _nb_front_end            (nb_front_end           ),
-    _nb_ooo_engine           (nb_ooo_engine          ),
-    _nb_packet               (nb_packet              ),
-    _size_general_data       (size_general_data      ),
-    _size_special_data       (size_special_data      ),
-    _nb_general_register     (nb_general_register    ),
-    _nb_special_register     (nb_special_register    ),
-    
-    _size_address_store_queue              (log2(size_store_queue             )),
-    _size_address_load_queue               (log2(size_load_queue              )),
-    _size_address_speculative_access_queue (log2(size_speculative_access_queue)),
-
-    _size_context_id         (log2(nb_context         )),
-    _size_front_end_id       (log2(nb_front_end       )),
-    _size_ooo_engine_id      (log2(nb_ooo_engine      )),
-    _size_packet_id          (log2(nb_packet          )),
-    _size_general_register   (log2(nb_general_register)),
-    _size_special_register   (log2(nb_special_register)),
-    _size_dcache_context_id  (_size_context_id + _size_front_end_id + _size_ooo_engine_id),
-    _size_dcache_packet_id   ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1),
-
-    _have_port_context_id        (_size_context_id   >0),
-    _have_port_front_end_id      (_size_front_end_id >0),
-    _have_port_ooo_engine_id     (_size_ooo_engine_id>0),
-    _have_port_packet_id         (_size_packet_id    >0),
-    _have_port_dcache_context_id (_size_dcache_context_id>0),
-    _have_port_load_queue_ptr    (_size_load_queue>1),
-
-    _mask_address_lsb            (gen_mask<Tdcache_address_t>(log2(size_general_data/8))),
-    _mask_address_msb            (gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8))
+			  uint32_t            nb_special_register    ,
+                          bool                is_toplevel)
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    _size_store_queue                      = size_store_queue       ;
+    _size_load_queue                       = size_load_queue        ;
+    _size_speculative_access_queue         = size_speculative_access_queue;
+    _nb_port_check                         = nb_port_check          ;
+    _speculative_load                      = speculative_load       ;
+    _nb_bypass_memory                      = nb_bypass_memory       ;
+    _nb_cache_port                         = nb_cache_port          ;
+    _nb_inst_memory                        = nb_inst_memory         ;
+    _nb_context                            = nb_context             ;
+    _nb_front_end                          = nb_front_end           ;
+    _nb_ooo_engine                         = nb_ooo_engine          ;
+    _nb_packet                             = nb_packet              ;
+    _nb_general_register                   = nb_general_register    ;
+    _nb_special_register                   = nb_special_register    ;
+    
+    _size_speculative_access_queue_ptr     = log2(size_speculative_access_queue);
+
+    _size_dcache_context_id                = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine);
+    _size_dcache_packet_id                 = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1;
+
+    _have_port_dcache_context_id           = _size_dcache_context_id>0;
+
+    _mask_address_lsb                      = gen_mask<Tdcache_address_t>(log2(size_general_data/8));
+    _mask_address_msb                      = gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8);
+
     test();
+
+    if (is_toplevel)
+      {
+        _size_context_id                       = log2(nb_context         );
+        _size_front_end_id                     = log2(nb_front_end       );
+        _size_ooo_engine_id                    = log2(nb_ooo_engine      );
+        _size_rob_ptr                          = log2(nb_packet          );
+        _size_general_register                 = log2(nb_general_register);
+        _size_special_register                 = log2(nb_special_register);
+        _size_store_queue_ptr                  = log2(size_store_queue   );
+        _size_load_queue_ptr                   = log2(size_load_queue    );
+        _size_general_data                     = size_general_data      ;
+        _size_special_data                     = size_special_data      ;
+
+        _have_port_context_id                  = _size_context_id    >0;
+        _have_port_front_end_id                = _size_front_end_id  >0;
+        _have_port_ooo_engine_id               = _size_ooo_engine_id >0;
+        _have_port_rob_ptr                     = _size_rob_ptr       >0;
+        _have_port_load_queue_ptr              = _size_load_queue_ptr>0;
+
+        copy();
+      }
+
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
   
+// #undef  FUNCTION
+// #define FUNCTION "Load_store_unit::Parameters (copy)"
+//   Parameters::Parameters (Parameters & param):
+//     _size_store_queue        (param._size_store_queue       ),
+//     _size_load_queue         (param._size_load_queue        ),
+//     _size_speculative_access_queue (param._size_speculative_access_queue),
+//     _nb_port_check           (param._nb_port_check          ),
+//     _speculative_load        (param._speculative_load       ),
+//     _nb_bypass_memory        (param._nb_bypass_memory       ),
+//     _nb_cache_port           (param._nb_cache_port          ),
+//     _nb_inst_memory          (param._nb_inst_memory         ),
+//     _nb_context              (param._nb_context             ),
+//     _nb_front_end            (param._nb_front_end           ),
+//     _nb_ooo_engine           (param._nb_ooo_engine          ),
+//     _nb_packet               (param._nb_packet              ),
+//     _size_general_data       (param._size_general_data      ),
+//     _size_special_data       (param._size_special_data      ),
+//     _nb_general_register     (param._nb_general_register    ),
+//     _nb_special_register     (param._nb_special_register    ),
+
+//     _size_address_store_queue              (param._size_address_store_queue             ),
+//     _size_address_load_queue               (param._size_address_load_queue              ),
+//     _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
+
+//     _size_context_id         (param._size_context_id        ),
+//     _size_front_end_id       (param._size_front_end_id      ),
+//     _size_ooo_engine_id      (param._size_ooo_engine_id     ),
+//     _size_packet_id          (param._size_packet_id         ),
+//     _size_general_register   (param._size_general_register  ),
+//     _size_special_register   (param._size_special_register  ),
+//     _size_dcache_context_id  (param._size_dcache_context_id ),
+//     _size_dcache_packet_id   (param._size_dcache_packet_id  ),
+
+//     _have_port_context_id    (param._have_port_context_id   ),
+//     _have_port_front_end_id  (param._have_port_front_end_id ),
+//     _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
+//     _have_port_packet_id     (param._have_port_packet_id    ),
+//     _have_port_dcache_context_id(param._have_port_dcache_context_id),
+//     _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
+
+//     _mask_address_lsb        (param._mask_address_lsb),
+//     _mask_address_msb        (param._mask_address_msb)
+//   {
+//     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+//     test();
+//     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+//   };
+
 #undef  FUNCTION
-#define FUNCTION "Load_store_unit::Parameters (copy)"
-  Parameters::Parameters (Parameters & param):
-    _size_store_queue        (param._size_store_queue       ),
-    _size_load_queue         (param._size_load_queue        ),
-    _size_speculative_access_queue (param._size_speculative_access_queue),
-    _nb_port_check           (param._nb_port_check          ),
-    _speculative_load        (param._speculative_load       ),
-    _nb_bypass_memory        (param._nb_bypass_memory       ),
-    _nb_context              (param._nb_context             ),
-    _nb_front_end            (param._nb_front_end           ),
-    _nb_ooo_engine           (param._nb_ooo_engine          ),
-    _nb_packet               (param._nb_packet              ),
-    _size_general_data       (param._size_general_data      ),
-    _size_special_data       (param._size_special_data      ),
-    _nb_general_register     (param._nb_general_register    ),
-    _nb_special_register     (param._nb_special_register    ),
-
-    _size_address_store_queue              (param._size_address_store_queue             ),
-    _size_address_load_queue               (param._size_address_load_queue              ),
-    _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
-
-    _size_context_id         (param._size_context_id        ),
-    _size_front_end_id       (param._size_front_end_id      ),
-    _size_ooo_engine_id      (param._size_ooo_engine_id     ),
-    _size_packet_id          (param._size_packet_id         ),
-    _size_general_register   (param._size_general_register  ),
-    _size_special_register   (param._size_special_register  ),
-    _size_dcache_context_id  (param._size_dcache_context_id ),
-    _size_dcache_packet_id   (param._size_dcache_packet_id  ),
-
-    _have_port_context_id    (param._have_port_context_id   ),
-    _have_port_front_end_id  (param._have_port_front_end_id ),
-    _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
-    _have_port_packet_id     (param._have_port_packet_id    ),
-    _have_port_dcache_context_id(param._have_port_dcache_context_id),
-    _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
-
-    _mask_address_lsb        (param._mask_address_lsb),
-    _mask_address_msb        (param._mask_address_msb)
+#define FUNCTION "Load_store_unit::~Parameters"
+  Parameters::~Parameters (void) 
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
-    test();
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
 
 #undef  FUNCTION
-#define FUNCTION "Load_store_unit::~Parameters"
-  Parameters::~Parameters () 
+#define FUNCTION "Load_store_unit::copy"
+  void Parameters::copy (void) 
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 88)
@@ -32,5 +32,5 @@
 	{
 	  if (not (_nb_bypass_memory == 0))
-	    test.error("Bypass memory is not supported. Please wait a next revision.");
+	    test.error(_("Bypass memory is not supported. Please wait a next revision.\n"));
  
 	  break;
@@ -42,7 +42,7 @@
 	{
 	  if (not (_nb_bypass_memory == 0))
-	    test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");
+	    test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str()));
 
-	  test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");
+	  test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str()));
 	  break;
 	}
@@ -50,8 +50,14 @@
 
     if (not (_size_store_queue >= 2))
-      test.error("Store queue must have at less two slot.");
+      test.error(_("Store queue must have at less two slot.\n"));
 
     if (not (_nb_bypass_memory <= _size_load_queue))
-      test.error("Bypass number must be less than load_queue's size.");
+      test.error(_("Bypass number must be less than load_queue's size.\n"));
+
+    if (_nb_cache_port > 1)
+      test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); 
+
+    if (_nb_inst_memory > 1)
+      test.warning(_("nb_inst_memory > 1 is unsupported (Coming Soon).\n")); 
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
