Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp	(revision 88)
@@ -8,14 +8,5 @@
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h"
-
-#define neg(data)                  (~(data)+1)
-#define sign(data)                 ((data)>>(param->_size_data-1))
-#define unsigned(data)             (data)
-#define signed(data)               ((sign(data)==0)?(data):neg(data))
-#define ovf(op1, op2, res)         ((sign(op1) == sign(op2))?(sign(op1) xor sign(res)):0)
-#define carry(op1, op2, res)       (((res)<(op1)) or ((res)<(op2)))
-#define set_flag(data,flag,is_set) (((is_set)==1)?((data)|(flag)):((data)&~(flag)))
-#define get_flag(data,flag)	   (((data)&(flag))!=0)
-#define concatenation_bool(a,b)    (((a)<<1) | (b))
+#include "Behavioural/include/Operation.h"
 
 namespace morpheo                    {
@@ -43,11 +34,11 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_add");
 
-    Tgeneral_data_t gpr1      = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2      = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1      = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2      = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     
     Tgeneral_data_t gpr3      = param->_mask_data & (gpr1 + gpr2);
 
-    bool            overflow  = ovf  (gpr1,gpr2,gpr3);
-    bool            carry_out = carry(gpr1,gpr2,gpr3);
+    bool            overflow  = ovf  (param->_size_data,gpr1,gpr2,gpr3);
+    bool            carry_out = carry(param->_size_data,gpr1,gpr2,gpr3);
 
     // Result
@@ -70,10 +61,10 @@
     Tgeneral_data_t carry_in   = get_flag(op->_data_rc,FLAG_CY);
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = param->_mask_data & (gpr1 + gpr2 + carry_in);
 
-    bool            overflow   = ovf  (gpr1,gpr2,gpr3);
-    bool            carry_out  = carry(gpr1,gpr2,gpr3);
+    bool            overflow   = ovf  (param->_size_data,gpr1,gpr2,gpr3);
+    bool            carry_out  = carry(param->_size_data,gpr1,gpr2,gpr3);
 
     // Result
@@ -94,10 +85,10 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sub");
 
-    Tgeneral_data_t gpr1      =     unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2      = neg(unsigned(op->_data_rb));
+    Tgeneral_data_t gpr1      =                       unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2      = neg(param->_size_data,unsigned(param->_size_data,op->_data_rb));
     Tgeneral_data_t gpr3      = param->_mask_data & (gpr1 + gpr2);
 
-    bool            overflow  = ovf  (gpr1,gpr2,gpr3);
-    bool            carry_out = carry(gpr1,gpr2,gpr3);
+    bool            overflow  = ovf  (param->_size_data,gpr1,gpr2,gpr3);
+    bool            carry_out = carry(param->_size_data,gpr1,gpr2,gpr3);
 
     // Result
@@ -118,6 +109,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_and");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = (gpr1 & gpr2);
 
@@ -137,6 +128,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_or");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = (gpr1 | gpr2);
 
@@ -156,6 +147,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_xor");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = (gpr1 ^ gpr2);
 
@@ -175,5 +166,5 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_movhi");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_immediat);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_immediat);
     Tgeneral_data_t gpr2       = param->_mask_data & (gpr1<<16);
 
@@ -195,6 +186,6 @@
     Tgeneral_data_t f_in       = get_flag(op->_data_rc,FLAG_F);
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned(op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,op->_data_rb);
     Tgeneral_data_t gpr3       = ((f_in==0)?gpr2:gpr1);
 
@@ -215,5 +206,5 @@
 
     Tgeneral_data_t f_in       = get_flag(op->_data_rc,FLAG_F);
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
 
     // Result
@@ -233,5 +224,5 @@
 
     Tgeneral_data_t f_in       = get_flag(op->_data_rc,FLAG_F);
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
 
     // Result
@@ -254,6 +245,6 @@
 
 
-    Tgeneral_data_t gpr        = unsigned(op->_data_rb);
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
+    Tgeneral_data_t gpr        = unsigned(param->_size_data,op->_data_rb);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
 
     // Result
@@ -272,6 +263,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_extend_s");
 
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
     Tgeneral_data_t gpr2       = extend<Tgeneral_data_t>(param->_size_data, gpr1, true , imm);
 
@@ -291,6 +282,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_extend_z");
 
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
     Tgeneral_data_t gpr2       = extend<Tgeneral_data_t>(param->_size_data, gpr1, false , imm);
 
@@ -310,6 +301,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sll");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = shift_logic_left<Tgeneral_data_t>(param->_size_data, gpr1, gpr2);
 
@@ -329,6 +320,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_srl");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = shift_logic_right<Tgeneral_data_t>(param->_size_data, gpr1, gpr2);
 
@@ -348,6 +339,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sra");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = shift_arithmetic_right<Tgeneral_data_t>(param->_size_data, gpr1, gpr2);
 
@@ -367,6 +358,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_ror");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     Tgeneral_data_t gpr3       = rotate_right<Tgeneral_data_t>(param->_size_data, gpr1, gpr2);
 
@@ -386,5 +377,5 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_ff1");
 
-    Tgeneral_data_t gpr        = unsigned(op->_data_ra);
+    Tgeneral_data_t gpr        = unsigned(param->_size_data,op->_data_ra);
     Tgeneral_data_t index;
 
@@ -406,5 +397,5 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_fl1");
 
-    Tgeneral_data_t gpr        = unsigned(op->_data_ra);
+    Tgeneral_data_t gpr        = unsigned(param->_size_data,op->_data_ra);
     Tgeneral_data_t index;
 
@@ -426,6 +417,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfeq");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 == gpr2);
@@ -446,6 +437,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfne");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 != gpr2);
@@ -466,6 +457,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfgeu");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 >= gpr2);
@@ -486,6 +477,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfgtu");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 >  gpr2);
@@ -506,6 +497,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfleu");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 <= gpr2);
@@ -526,6 +517,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfltu");
 
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
 
     bool            f_out      = (gpr1 <  gpr2);
@@ -549,16 +540,16 @@
     Tgeneral_data_t gpr2       =   (op->_has_immediat==1)?op->_immediat:op->_data_rb;
     
-    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra  : %.8x",unsigned(op->_data_ra));
-    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x",  signed(op->_data_ra));
-    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb  : %.8x",unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb));
-    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x",  signed((op->_has_immediat==1)?op->_immediat:op->_data_rb));
+    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra  : %.8x",unsigned(param->_size_data,op->_data_ra));
+    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x",  signed(param->_size_data,op->_data_ra));
+    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb  : %.8x",unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb));
+    log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x",  signed(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb));
     
     bool            f_out;
 
-    switch (concatenation_bool(sign(gpr1),sign(gpr2)))
+    switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2)))
       {
       case 1 /*b01*/ : f_out = 1                               ; break;
       case 2 /*b10*/ : f_out = 0                               ; break;
-      default        : f_out = signed(gpr1) >= signed(gpr2); break;
+      default        : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break;
       }
 
@@ -585,9 +576,9 @@
     bool            f_out;
 
-    switch (concatenation_bool(sign(gpr1),sign(gpr2)))
+    switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2)))
       {
       case 1 /*b01*/ : f_out = 1; break;
       case 2 /*b10*/ : f_out = 0; break;
-      default        : f_out = signed(gpr1) >  signed(gpr2); break;
+      default        : f_out = signed(param->_size_data,gpr1) >  signed(param->_size_data,gpr2); break;
       }
 
@@ -612,9 +603,9 @@
     bool            f_out;
 
-    switch (concatenation_bool(sign(gpr1),sign(gpr2)))
+    switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2)))
       {
       case 1 /*b01*/ : f_out = 0; break;
       case 2 /*b10*/ : f_out = 1; break;
-      default        : f_out = signed(gpr1) <= signed(gpr2); break;
+      default        : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break;
       }
     
@@ -639,9 +630,9 @@
     bool            f_out;
 
-    switch (concatenation_bool(sign(gpr1),sign(gpr2)))
+    switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2)))
       {
       case 1 /*b01*/ : f_out = 0; break;
       case 2 /*b10*/ : f_out = 1; break;
-      default        : f_out = signed(gpr1) <  signed(gpr2); break;
+      default        : f_out = signed(param->_size_data,gpr1) <  signed(param->_size_data,gpr2); break;
       }
 
@@ -661,7 +652,7 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mtspr");
 
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2       = unsigned(op->_data_rb);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2       = unsigned(param->_size_data,op->_data_rb);
     Tgeneral_data_t addr       = range<Tgeneral_data_t>(gpr1|imm,16);
 
@@ -694,5 +685,5 @@
     else
       {
-	exception = EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE;
+	exception = EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE;
       }
     
@@ -712,6 +703,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mfspr");
 
-    Tgeneral_data_t imm        = unsigned(op->_immediat);
-    Tgeneral_data_t gpr1       = unsigned(op->_data_ra);
+    Tgeneral_data_t imm        = unsigned(param->_size_data,op->_immediat);
+    Tgeneral_data_t gpr1       = unsigned(param->_size_data,op->_data_ra);
     Tgeneral_data_t gpr2       = 0;
     Tgeneral_data_t addr       = range<Tgeneral_data_t>(gpr1|imm,16);
@@ -745,5 +736,5 @@
     else
       {
-	exception = EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE;
+	exception = EXCEPTION_ALU_SPR_ACCESS_MUST_READ;
       }
 
@@ -784,6 +775,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mac");
 
-    Tgeneral_data_t gpr1 = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     uint64_t        temp = range<uint64_t>(gpr1 * gpr2, 32);
 
@@ -808,6 +799,6 @@
     log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_msb");
 
-    Tgeneral_data_t gpr1 = unsigned(op->_data_ra);
-    Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb);
+    Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra);
+    Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb);
     uint64_t        temp = range<uint64_t>(gpr1 * gpr2, 32);
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Functionnal_unit_library_clean
 
+local_clean			:
+
 include                         $(DIR_COMPONENT)/Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp	(revision 88)
@@ -75,5 +75,6 @@
 	 size_load_queue     ,
 	 timing              ,
-	 &(morpheo::behavioural::custom::example_get_custom_information)
+	 &(morpheo::behavioural::custom::example_get_custom_information),
+         true // is_toplevel
         );
       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp	(revision 88)
@@ -69,8 +69,8 @@
   _data_rc       (data_rc      & gen_mask<Tspecial_data_t>(param->_size_special_data)),
   _write_rd      (write_rd     ),
-  _num_reg_rd    (num_reg_rd   % param->_nb_special_register),
+  _num_reg_rd    (num_reg_rd   % (1<<param->_size_general_register)),
   _data_rd       (data_rd      & gen_mask<Tgeneral_data_t>(param->_size_general_data)),
   _write_re      (write_re     ),
-  _num_reg_re    (num_reg_re   % param->_nb_special_register),
+  _num_reg_re    (num_reg_re   % (1<<param->_size_special_register)),
   _data_re       (data_re      & gen_mask<Tspecial_data_t>(param->_size_special_data)),
   _exception     (exception    ),
@@ -88,6 +88,16 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Functionnal_unit * _Functionnal_unit = new Functionnal_unit (name.c_str(),
@@ -96,5 +106,5 @@
 #endif
 							       _param,
-							       USE_ALL);
+							       _usage);
   
 #ifdef SYSTEMC
@@ -162,5 +172,5 @@
   if (_param->_have_port_ooo_engine_id)
   (*(_Functionnal_unit-> in_EXECUTE_IN_OOO_ENGINE_ID )) ( in_EXECUTE_IN_OOO_ENGINE_ID );
-  if (_param->_have_port_packet_id)
+  if (_param->_have_port_rob_ptr)
   (*(_Functionnal_unit-> in_EXECUTE_IN_PACKET_ID     )) ( in_EXECUTE_IN_PACKET_ID     );
   (*(_Functionnal_unit-> in_EXECUTE_IN_OPERATION     )) ( in_EXECUTE_IN_OPERATION     );
@@ -187,5 +197,5 @@
   if (_param->_have_port_ooo_engine_id)
   (*(_Functionnal_unit->out_EXECUTE_OUT_OOO_ENGINE_ID)) (out_EXECUTE_OUT_OOO_ENGINE_ID);
-  if (_param->_have_port_packet_id)
+  if (_param->_have_port_rob_ptr)
   (*(_Functionnal_unit->out_EXECUTE_OUT_PACKET_ID    )) (out_EXECUTE_OUT_PACKET_ID    );
 //(*(_Functionnal_unit->out_EXECUTE_OUT_OPERATION    )) (out_EXECUTE_OUT_OPERATION    );
@@ -475,6 +485,6 @@
   transaction_in.push_back(execute_transaction(_param,0,0,0,301,OPERATION_TEST_L_SFLTS   ,TYPE_TEST,0,0         ,0x11111111,0xdeadbeef,0              ,0,63,0x0       ,1,15,0              ,EXCEPTION_NONE     ,0)); // + <  - (in unsigned)
 
-  transaction_in.push_back(execute_transaction(_param,0,0,0,400,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_ICACHE<<11,   3,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE,0,(GROUP_ICACHE<<11)|   3));
-  transaction_in.push_back(execute_transaction(_param,0,0,0,401,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_ICACHE<<11,   5,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE,0,(GROUP_ICACHE<<11)|   5));
+  transaction_in.push_back(execute_transaction(_param,0,0,0,400,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_ICACHE<<11,   3,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE  ,0,(GROUP_ICACHE<<11)|   3));
+  transaction_in.push_back(execute_transaction(_param,0,0,0,401,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_ICACHE<<11,   5,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE  ,0,(GROUP_ICACHE<<11)|   5));
   transaction_in.push_back(execute_transaction(_param,0,0,0,402,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_MAC   <<11,   0,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_SPR_ACCESS_INVALID     ,0,(GROUP_MAC   <<11)|   0));
   transaction_in.push_back(execute_transaction(_param,0,0,0,403,OPERATION_SPECIAL_L_MTSPR   ,TYPE_SPECIAL,1,GROUP_MAC   <<11,   1,0xdeadbeef,0              ,0,63,0xdeadbeef,0, 0,0              ,EXCEPTION_ALU_NONE                   ,0,(GROUP_MAC   <<11)|   1));
@@ -590,5 +600,5 @@
 	      if (_param->_have_port_ooo_engine_id)
 	      in_EXECUTE_IN_OOO_ENGINE_ID .write(transaction_in.front()._ooo_engine_id);
-	      if (_param->_have_port_packet_id)
+	      if (_param->_have_port_rob_ptr)
 	      in_EXECUTE_IN_PACKET_ID     .write(transaction_in.front()._packet_id    );
 	      in_EXECUTE_IN_OPERATION     .write(transaction_in.front()._operation    );
@@ -613,5 +623,5 @@
 	    {
 	      // TEST
-	      if (_param->_have_port_packet_id)
+	      if (_param->_have_port_rob_ptr)
 	      TEST(Tpacket_t         , out_EXECUTE_OUT_PACKET_ID    .read(), transaction_out.front()._packet_id    );
 	      if (_param->_have_port_context_id)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h	(revision 88)
@@ -124,7 +124,9 @@
   private   : Tcontrol_t                      internal_EXECUTE_IN_ACK;
   private   : Tcontrol_t                      internal_EXECUTE_OUT_VAL;
-  private   : bool                            reg_BUSY;
+  private   : bool                            reg_BUSY_IN ;
+  private   : bool                            reg_BUSY_OUT;
 
-  private   : execute_operation_t           * _execute_operation;
+  private   : execute_operation_t           * _execute_operation_in ;
+  private   : execute_operation_t           * _execute_operation_out;
   private   : execute_register_t         **** _execute_register;
   private   : execute_param_t               * _execute_param;
@@ -158,6 +160,4 @@
   public  : void        transition                (void);
   public  : void        genMoore                  (void);
-  public  : void        genMealy                  (void);
-
 
 #endif					       
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h	(revision 88)
@@ -25,36 +25,35 @@
 namespace functionnal_unit {
 
-
   class Parameters : public morpheo::behavioural::Parameters
   {
     //-----[ fields ]------------------------------------------------------------
-  public : const uint32_t            _nb_context                   ;
-  public : const uint32_t            _nb_front_end                 ;
-  public : const uint32_t            _nb_ooo_engine                ;
-  public : const uint32_t            _nb_packet                    ;
-  public : const uint32_t            _size_general_data            ;
-  public : const uint32_t            _nb_general_register          ;
-  public : const uint32_t            _size_special_data            ;
-  public : const uint32_t            _nb_special_register          ;
-  public : const uint32_t            _size_store_queue             ;
-  public : const uint32_t            _size_load_queue              ;
+  public : uint32_t            _nb_context                   ;
+  public : uint32_t            _nb_front_end                 ;
+  public : uint32_t            _nb_ooo_engine                ;
+  public : uint32_t            _nb_packet                    ;
+//public : uint32_t            _size_general_data            ;
+//public : uint32_t            _size_special_data            ;
+//public : uint32_t            _nb_general_register          ;
+//public : uint32_t            _nb_special_register          ;
+//public : uint32_t            _size_store_queue             ;
+//public : uint32_t            _size_load_queue              ;
 
-  public :       execute_timing_t ** _timing                       ;
-  public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t);
+  public : execute_timing_t ** _timing                       ;
+  public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void);
 
-  public : const uint32_t            _size_context_id              ;
-  public : const uint32_t            _size_front_end_id            ;
-  public : const uint32_t            _size_ooo_engine_id           ;
-  public : const uint32_t            _size_packet_id               ;
-  public : const uint32_t            _size_general_register        ;
-  public : const uint32_t            _size_special_register        ;
+//public : uint32_t            _size_context_id              ;
+//public : uint32_t            _size_front_end_id            ;
+//public : uint32_t            _size_ooo_engine_id           ;
+//public : uint32_t            _size_packet_id               ;
+//public : uint32_t            _size_general_register        ;
+//public : uint32_t            _size_special_register        ;
 
-  public : const bool                _have_port_context_id         ;
-  public : const bool                _have_port_front_end_id       ;
-  public : const bool                _have_port_ooo_engine_id      ;
-  public : const bool                _have_port_packet_id          ;
-  public : const bool                _have_port_load_queue_ptr     ;
+//public : bool                _have_port_context_id         ;
+//public : bool                _have_port_front_end_id       ;
+//public : bool                _have_port_ooo_engine_id      ;
+//public : bool                _have_port_packet_id          ;
+//public : bool                _have_port_load_queue_ptr     ;
 
-  public : const bool                _have_groupe_MAC              ;
+  public : bool                _have_groupe_MAC              ;
 
     //-----[ methods ]-----------------------------------------------------------
@@ -70,7 +69,11 @@
 			uint32_t           size_load_queue    ,
 			execute_timing_t** timing             ,
-			morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t));
-  public : Parameters  (Parameters & param) ;
+			morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void),
+                        bool               is_toplevel=true
+                        );
+//   public : Parameters  (Parameters & param) ;
   public : ~Parameters () ;
+
+  public :        void            copy       (void);
 
   public :        Parameters_test msg_error  (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp	(revision 88)
@@ -42,6 +42,12 @@
     allocation ();
 
+#if DEBUG_Functionnal_unit == true
+    log_printf(INFO,Functionnal_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+    std::cout << *param << std::endl;
+#endif    
+
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {	
 	log_printf(INFO,Functionnal_unit,FUNCTION,"Allocation of statistics");
@@ -52,5 +58,5 @@
 
 #ifdef VHDL
-    if (_usage & USE_VHDL)
+    if (usage_is_set(_usage,USE_VHDL))
       {
 	// generate the vhdl
@@ -62,5 +68,5 @@
 
 #ifdef SYSTEMC
-    if (_usage & USE_SYSTEMC)
+    if (usage_is_set(_usage,USE_SYSTEMC))
       {
 	log_printf(INFO,Functionnal_unit,FUNCTION,"Method - transition");
@@ -84,16 +90,4 @@
 # endif    
 
-	log_printf(INFO,Functionnal_unit,FUNCTION,"Method - genMealy");
-
-	SC_METHOD (genMealy);
-	dont_initialize ();
-	sensitive << (*(in_CLOCK)).neg()
-		  << (*(in_EXECUTE_OUT_ACK));
-	
-# ifdef SYSTEMCASS_SPECIFIC
-	// List dependency information
-	(*(out_EXECUTE_IN_ACK)) (*(in_EXECUTE_OUT_ACK));
-# endif    
-	
 #endif
       }
@@ -108,5 +102,5 @@
 
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {
 	log_printf(INFO,Functionnal_unit,FUNCTION,"Generate Statistics file");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp	(revision 88)
@@ -67,11 +67,11 @@
       if (_param->_have_port_ooo_engine_id)
        in_EXECUTE_IN_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t        > ("ooo_engine_id", _param->_size_ooo_engine_id);
-      if (_param->_have_port_packet_id)
-       in_EXECUTE_IN_PACKET_ID     = interface->set_signal_in <Tpacket_t         > ("packet_id"    , _param->_size_packet_id    );
+      if (_param->_have_port_rob_ptr)
+       in_EXECUTE_IN_PACKET_ID     = interface->set_signal_in <Tpacket_t         > ("packet_id"    , _param->_size_rob_ptr    );
        in_EXECUTE_IN_OPERATION     = interface->set_signal_in <Toperation_t      > ("operation"    , _param->_size_operation    );
        in_EXECUTE_IN_TYPE          = interface->set_signal_in <Ttype_t           > ("type"         , _param->_size_type         );
-       in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("store_queue_ptr_write",log2(_param->_size_store_queue));
+       in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t> ("store_queue_ptr_write",_param->_size_store_queue_ptr);
        if (_param->_have_port_load_queue_ptr)
-       in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in <Tlsq_ptr_t> ("load_queue_ptr_write" ,log2(_param->_size_load_queue));
+       in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in <Tlsq_ptr_t> ("load_queue_ptr_write" ,_param->_size_load_queue_ptr);
        in_EXECUTE_IN_HAS_IMMEDIAT  = interface->set_signal_in <Tcontrol_t        > ("has_immediat" , 1);
        in_EXECUTE_IN_IMMEDIAT      = interface->set_signal_in <Tgeneral_data_t   > ("immediat"     , _param->_size_general_data);
@@ -102,6 +102,6 @@
        if (_param->_have_port_ooo_engine_id)
        out_EXECUTE_OUT_OOO_ENGINE_ID  = interface->set_signal_out<Tcontext_t        > ("ooo_engine_id",_param->_size_ooo_engine_id);
-       if (_param->_have_port_packet_id)
-       out_EXECUTE_OUT_PACKET_ID      = interface->set_signal_out<Tpacket_t         > ("packet_id"    ,_param->_size_packet_id    );
+       if (_param->_have_port_rob_ptr)
+       out_EXECUTE_OUT_PACKET_ID      = interface->set_signal_out<Tpacket_t         > ("packet_id"    ,_param->_size_rob_ptr    );
      //out_EXECUTE_OUT_OPERATION      = interface->set_signal_out<Toperation_t      > ("operation"    ,_param->_size_operation    );
        out_EXECUTE_OUT_TYPE           = interface->set_signal_out<Ttype_t           > ("type"         ,_param->_size_type         );
@@ -117,8 +117,11 @@
      }
 
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-     _execute_operation = new execute_operation_t;
-     _execute_param     = new execute_param_t(_param->_size_general_data,
-					      _param->_timing);
+     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+     if (usage_is_set(_usage,USE_SYSTEMC))
+       {
+     _execute_operation_in  = new execute_operation_t;
+     _execute_operation_out = new execute_operation_t;
+     _execute_param         = new execute_param_t(_param->_size_general_data,
+						  _param->_timing);
 
      _execute_register = new execute_register_t *** [_param->_nb_context];
@@ -134,7 +137,7 @@
 	     for (uint32_t k=0; k<_param->_nb_ooo_engine; k++)
 	       {
-		 uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
-						      j,_param->_size_front_end_id,
-						      k,_param->_size_ooo_engine_id);
+// 		 uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
+// 						      j,_param->_size_front_end_id,
+// 						      k,_param->_size_ooo_engine_id);
 
 		 _execute_register [i][j][k] = new execute_register_t;
@@ -144,11 +147,11 @@
 
 		 for (uint32_t x=GROUP_CUSTOM_1; x<GROUP_CUSTOM_8; x++)
-		   if ((_param->_get_custom_information(num_thread))._get_valid_group(x) == true)
+		   if ((_param->_get_custom_information())._get_valid_group(x) == true)
 		     {
-		       uint32_t nb_reg = (_param->_get_custom_information(num_thread))._get_nb_register(x);
+		       uint32_t nb_reg = (_param->_get_custom_information())._get_nb_register(x);
 		       _execute_register[i][j][k]->implement_group(x,nb_reg);
 
 		       for (uint32_t y=0; y<nb_reg; y++)
-			 _execute_register[i][j][k]->_spr_access_mode->change_mode(x,y,(_param->_get_custom_information(num_thread))._get_access_mode(x,y));
+			 _execute_register[i][j][k]->_spr_access_mode->change_mode(x,y,(_param->_get_custom_information())._get_access_mode(x,y));
 		     }
 	       }
@@ -211,12 +214,12 @@
      if (_param->_timing[TYPE_TEST   ][OPERATION_TEST_L_SFNE       ]._latence > 0) 
        _function_execute[TYPE_TEST   ][OPERATION_TEST_L_SFNE       ] = &(operation_l_sfne    );
-//   if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MUL     ]._latence > 0) 
-//     _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MUL     ] = &(operation_l_mul     );
-//   if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MULU    ]._latence > 0) 
-//     _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MULU    ] = &(operation_l_mulu    );
-//   if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIV     ]._latence > 0) 
-//     _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIV     ] = &(operation_l_div     );
-//   if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIVU    ]._latence > 0) 
-//     _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIVU    ] = &(operation_l_divu    );
+//   if (_param->_timing[TYPE_MUL    ][OPERATION_MUL_L_MUL         ]._latence > 0) 
+//     _function_execute[TYPE_MUL    ][OPERATION_MUL_L_MUL         ] = &(operation_l_mul     );
+//   if (_param->_timing[TYPE_MUL    ][OPERATION_MUL_L_MULU        ]._latence > 0) 
+//     _function_execute[TYPE_DIV    ][OPERATION_MUL_L_MULU        ] = &(operation_l_mulu    );
+//   if (_param->_timing[TYPE_DIV    ][OPERATION_DIV_L_DIV         ]._latence > 0) 
+//     _function_execute[TYPE_DIV    ][OPERATION_DIV_L_DIV         ] = &(operation_l_div     );
+//   if (_param->_timing[TYPE_DIV    ][OPERATION_DIV_L_DIVU        ]._latence > 0) 
+//     _function_execute[TYPE_DIV    ][OPERATION_DIV_L_DIVU        ] = &(operation_l_divu    );
      if (_param->_timing[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ]._latence > 0) 
        _function_execute[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ] = &(operation_l_extend_s);
@@ -243,9 +246,9 @@
      if (_param->_timing[TYPE_BRANCH ][OPERATION_BRANCH_L_JALR     ]._latence > 0) 
        _function_execute[TYPE_BRANCH ][OPERATION_BRANCH_L_JALR     ] = &(operation_l_jalr    );
-
-
-
-#ifdef POSITION
-    _component->generate_file();
+       }
+
+#ifdef POSITION
+     if (usage_is_set(_usage,USE_POSITION))
+       _component->generate_file();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp	(revision 88)
@@ -24,5 +24,5 @@
     log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
 
-    if (_usage & USE_SYSTEMC)
+    if (usage_is_set(_usage,USE_SYSTEMC))
       {
 	delete    in_CLOCK ;
@@ -37,5 +37,5 @@
 	if (_param->_have_port_ooo_engine_id)
 	delete  in_EXECUTE_IN_OOO_ENGINE_ID ;
-	if (_param->_have_port_packet_id)
+	if (_param->_have_port_rob_ptr)
 	delete  in_EXECUTE_IN_PACKET_ID     ;
 	delete  in_EXECUTE_IN_OPERATION     ;
@@ -62,5 +62,5 @@
 	if (_param->_have_port_ooo_engine_id)
 	delete out_EXECUTE_OUT_OOO_ENGINE_ID  ; 
-	if (_param->_have_port_packet_id)
+	if (_param->_have_port_rob_ptr)
 	delete out_EXECUTE_OUT_PACKET_ID      ; 
       //delete out_EXECUTE_OUT_OPERATION      ; 
@@ -75,11 +75,13 @@
 	delete out_EXECUTE_OUT_NO_SEQUENCE    ;
 	delete out_EXECUTE_OUT_ADDRESS        ;
+
+        // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+        
+        delete [] _execute_register;
+        delete    _execute_param;
+        delete    _execute_operation_in;
+        delete    _execute_operation_out;
+        delete [] _function_execute;
       }
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-
-    delete [] _execute_register;
-    delete    _execute_param;
-    delete    _execute_operation;
-    delete [] _function_execute;
 
     delete    _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp	(revision 88)
@@ -26,5 +26,6 @@
 
 #ifdef STATISTICS
-    _stat->end_cycle();
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
 #endif    
 
@@ -32,5 +33,6 @@
     // Evaluation before read the ouput signal
 //  sc_start(0);
-    _interfaces->testbench();
+    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
+      _interfaces->testbench();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp	(revision 82)
+++ 	(revision )
@@ -1,46 +1,0 @@
-#ifdef SYSTEMC
-/*
- * $Id$
- *
- * [ Description ]
- * 
- */
-
-#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h"
-
-namespace morpheo                    {
-namespace behavioural {
-namespace core {
-namespace multi_execute_loop {
-namespace execute_loop {
-namespace multi_execute_unit {
-namespace execute_unit {
-namespace functionnal_unit {
-
-
-#undef  FUNCTION
-#define FUNCTION "Functionnal_unit::genMealy"
-  void Functionnal_unit::genMealy (void)
-  {
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
-
-    bool execute_out_transaction = (PORT_READ(in_EXECUTE_OUT_ACK) and
-				    (reg_BUSY and (_execute_operation->_timing._latence == 0)));
-
-    internal_EXECUTE_IN_ACK = not reg_BUSY or (reg_BUSY and execute_out_transaction);
-
-    PORT_WRITE(out_EXECUTE_IN_ACK, internal_EXECUTE_IN_ACK);
-
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
-  };
-
-}; // end namespace functionnal_unit
-}; // end namespace execute_unit
-}; // end namespace multi_execute_unit
-}; // end namespace execute_loop
-}; // end namespace multi_execute_loop
-}; // end namespace core
-
-}; // end namespace behavioural
-}; // end namespace morpheo              
-#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp	(revision 88)
@@ -23,30 +23,39 @@
   void Functionnal_unit::genMoore (void)
   {
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
+    log_begin(Functionnal_unit,FUNCTION);
+    log_function(Functionnal_unit,FUNCTION,_name.c_str());
 
-    internal_EXECUTE_OUT_VAL = reg_BUSY and (_execute_operation->_timing._latence == 0);
+    {
+      internal_EXECUTE_IN_ACK = not reg_BUSY_IN;
+      
+      PORT_WRITE(out_EXECUTE_IN_ACK           , internal_EXECUTE_IN_ACK);
+    }
 
-    PORT_WRITE(out_EXECUTE_OUT_VAL          , internal_EXECUTE_OUT_VAL);
-    if (_param->_have_port_context_id)
-    PORT_WRITE(out_EXECUTE_OUT_CONTEXT_ID   ,_execute_operation->_context_id   );
-    if (_param->_have_port_front_end_id)
-    PORT_WRITE(out_EXECUTE_OUT_FRONT_END_ID ,_execute_operation->_front_end_id );
-    if (_param->_have_port_ooo_engine_id)
-    PORT_WRITE(out_EXECUTE_OUT_OOO_ENGINE_ID,_execute_operation->_ooo_engine_id);
-    if (_param->_have_port_packet_id)
-    PORT_WRITE(out_EXECUTE_OUT_PACKET_ID    ,_execute_operation->_packet_id    );
-  //PORT_WRITE(out_EXECUTE_OUT_OPERATION    ,_execute_operation->_operation    );
-    PORT_WRITE(out_EXECUTE_OUT_TYPE         ,_execute_operation->_type         );
-    PORT_WRITE(out_EXECUTE_OUT_WRITE_RD     ,_execute_operation->_write_rd     );
-    PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD   ,_execute_operation->_num_reg_rd   );
-    PORT_WRITE(out_EXECUTE_OUT_DATA_RD      ,_execute_operation->_data_rd      );
-    PORT_WRITE(out_EXECUTE_OUT_WRITE_RE     ,_execute_operation->_write_re     );
-    PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RE   ,_execute_operation->_num_reg_re   );
-    PORT_WRITE(out_EXECUTE_OUT_DATA_RE      ,_execute_operation->_data_re      );
-    PORT_WRITE(out_EXECUTE_OUT_EXCEPTION    ,_execute_operation->_exception    );
-    PORT_WRITE(out_EXECUTE_OUT_NO_SEQUENCE  ,_execute_operation->_no_sequence  );
-    PORT_WRITE(out_EXECUTE_OUT_ADDRESS      ,_execute_operation->_address      );
+    {
+      internal_EXECUTE_OUT_VAL = reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0);
+      
+      PORT_WRITE(out_EXECUTE_OUT_VAL          , internal_EXECUTE_OUT_VAL);
+      if (_param->_have_port_context_id)
+      PORT_WRITE(out_EXECUTE_OUT_CONTEXT_ID   ,_execute_operation_out->_context_id   );
+      if (_param->_have_port_front_end_id)
+      PORT_WRITE(out_EXECUTE_OUT_FRONT_END_ID ,_execute_operation_out->_front_end_id );
+      if (_param->_have_port_ooo_engine_id)
+      PORT_WRITE(out_EXECUTE_OUT_OOO_ENGINE_ID,_execute_operation_out->_ooo_engine_id);
+      if (_param->_have_port_rob_ptr)
+      PORT_WRITE(out_EXECUTE_OUT_PACKET_ID    ,_execute_operation_out->_packet_id    );
+  //  PORT_WRITE(out_EXECUTE_OUT_OPERATION    ,_execute_operation_out->_operation    );
+      PORT_WRITE(out_EXECUTE_OUT_TYPE         ,_execute_operation_out->_type         );
+      PORT_WRITE(out_EXECUTE_OUT_WRITE_RD     ,_execute_operation_out->_write_rd     );
+      PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD   ,_execute_operation_out->_num_reg_rd   );
+      PORT_WRITE(out_EXECUTE_OUT_DATA_RD      ,_execute_operation_out->_data_rd      );
+      PORT_WRITE(out_EXECUTE_OUT_WRITE_RE     ,_execute_operation_out->_write_re     );
+      PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RE   ,_execute_operation_out->_num_reg_re   );
+      PORT_WRITE(out_EXECUTE_OUT_DATA_RE      ,_execute_operation_out->_data_re      );
+      PORT_WRITE(out_EXECUTE_OUT_EXCEPTION    ,_execute_operation_out->_exception    );
+      PORT_WRITE(out_EXECUTE_OUT_NO_SEQUENCE  ,_execute_operation_out->_no_sequence  );
+      PORT_WRITE(out_EXECUTE_OUT_ADDRESS      ,_execute_operation_out->_address      );
+    }
 
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
+    log_end(Functionnal_unit,FUNCTION);
   };
 
@@ -57,5 +66,4 @@
 }; // end namespace multi_execute_loop
 }; // end namespace core
-
 }; // end namespace behavioural
 }; // end namespace morpheo              
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp	(revision 88)
@@ -23,9 +23,11 @@
   void Functionnal_unit::transition (void)
   {
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
+    log_begin(Functionnal_unit,FUNCTION);
+    log_function(Functionnal_unit,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
       {
-	reg_BUSY = false;
+	reg_BUSY_IN  = false;
+	reg_BUSY_OUT = false;
 	
 	for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -33,11 +35,11 @@
 	    for (uint32_t k=0; k<_param->_nb_ooo_engine; k++)
 	      {
-		uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
-						     j,_param->_size_front_end_id,
-						     k,_param->_size_ooo_engine_id);
+// 		uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
+// 						     j,_param->_size_front_end_id,
+// 						     k,_param->_size_ooo_engine_id);
 		
 		for (uint32_t x=GROUP_CUSTOM_1; x<GROUP_CUSTOM_8; x++)
 		  {
-		    function_execute_end_cycle_t * fct = (_param->_get_custom_information(num_thread)._get_custom_execute_reset(x));
+		    function_execute_end_cycle_t * fct = (_param->_get_custom_information()._get_custom_execute_reset(x));
 		    
 		    if (fct != NULL)
@@ -51,6 +53,7 @@
 	if (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK))
 	  {
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"  * EXECUTE_OUT : Transaction Accepted");
 	    // transaction
-	    reg_BUSY = false;
+	    reg_BUSY_OUT = false;
 	  }
 	
@@ -60,29 +63,47 @@
 	if (PORT_READ(in_EXECUTE_IN_VAL) and internal_EXECUTE_IN_ACK)
 	  {
-	    reg_BUSY = true;
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"  * EXECUTE_IN : Transaction Accepted");
+
+	    reg_BUSY_IN = true;
 
 	    Tcontext_t   context_id    = (_param->_have_port_context_id   )?PORT_READ(in_EXECUTE_IN_CONTEXT_ID   ):0;
 	    Tcontext_t   front_end_id  = (_param->_have_port_front_end_id )?PORT_READ(in_EXECUTE_IN_FRONT_END_ID ):0;
 	    Tcontext_t   ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_IN_OOO_ENGINE_ID):0;
-	    Tcontext_t   packet_id     = (_param->_have_port_packet_id    )?PORT_READ(in_EXECUTE_IN_PACKET_ID    ):0;
+	    Tcontext_t   packet_id     = (_param->_have_port_rob_ptr      )?PORT_READ(in_EXECUTE_IN_PACKET_ID    ):0;
 	    Toperation_t operation     = PORT_READ(in_EXECUTE_IN_OPERATION);
 	    Ttype_t      type          = PORT_READ(in_EXECUTE_IN_TYPE);
 	    
-	    _execute_operation->_context_id    = context_id   ;
-	    _execute_operation->_front_end_id  = front_end_id ;
-	    _execute_operation->_ooo_engine_id = ooo_engine_id;
-	    _execute_operation->_packet_id     = packet_id    ;
-	    _execute_operation->_operation     = operation    ;
-	    _execute_operation->_type          = type         ;
-	    _execute_operation->_has_immediat  = PORT_READ(in_EXECUTE_IN_HAS_IMMEDIAT);
-	    _execute_operation->_immediat      = PORT_READ(in_EXECUTE_IN_IMMEDIAT    );
-	    _execute_operation->_data_ra       = PORT_READ(in_EXECUTE_IN_DATA_RA     );
-	    _execute_operation->_data_rb       = PORT_READ(in_EXECUTE_IN_DATA_RB     );
-	    _execute_operation->_data_rc       = PORT_READ(in_EXECUTE_IN_DATA_RC     );
-	    _execute_operation->_write_rd      = PORT_READ(in_EXECUTE_IN_WRITE_RD    );
-	    _execute_operation->_num_reg_rd    = PORT_READ(in_EXECUTE_IN_NUM_REG_RD  );
-	    _execute_operation->_write_re      = PORT_READ(in_EXECUTE_IN_WRITE_RE    );
-	    _execute_operation->_num_reg_re    = PORT_READ(in_EXECUTE_IN_NUM_REG_RE  );
-
+	    _execute_operation_in->_context_id    = context_id   ;
+	    _execute_operation_in->_front_end_id  = front_end_id ;
+	    _execute_operation_in->_ooo_engine_id = ooo_engine_id;
+	    _execute_operation_in->_packet_id     = packet_id    ;
+	    _execute_operation_in->_operation     = operation    ;
+	    _execute_operation_in->_type          = type         ;
+	    _execute_operation_in->_has_immediat  = PORT_READ(in_EXECUTE_IN_HAS_IMMEDIAT);
+	    _execute_operation_in->_immediat      = PORT_READ(in_EXECUTE_IN_IMMEDIAT    );
+	    _execute_operation_in->_data_ra       = PORT_READ(in_EXECUTE_IN_DATA_RA     );
+	    _execute_operation_in->_data_rb       = PORT_READ(in_EXECUTE_IN_DATA_RB     );
+	    _execute_operation_in->_data_rc       = PORT_READ(in_EXECUTE_IN_DATA_RC     );
+	    _execute_operation_in->_write_rd      = PORT_READ(in_EXECUTE_IN_WRITE_RD    );
+	    _execute_operation_in->_num_reg_rd    = PORT_READ(in_EXECUTE_IN_NUM_REG_RD  );
+	    _execute_operation_in->_write_re      = PORT_READ(in_EXECUTE_IN_WRITE_RE    );
+	    _execute_operation_in->_num_reg_re    = PORT_READ(in_EXECUTE_IN_NUM_REG_RE  );
+
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * context_id    : %d",_execute_operation_in->_context_id   );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * front_end_id  : %d",_execute_operation_in->_front_end_id );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * ooo_engine_id : %d",_execute_operation_in->_ooo_engine_id);
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * packet_id     : %d",_execute_operation_in->_packet_id    );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * operation     : %d",_execute_operation_in->_operation    );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * type          : %s",toString_type(_execute_operation_in->_type).c_str());
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * has_immediat  : %d",_execute_operation_in->_has_immediat );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * immediat      : %.8x",_execute_operation_in->_immediat     );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * data_ra       : %.8x",_execute_operation_in->_data_ra      );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * data_rb       : %.8x",_execute_operation_in->_data_rb      );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * data_rc       : %.8x",_execute_operation_in->_data_rc      );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * write_rd      : %d"  ,_execute_operation_in->_write_rd     );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * num_reg_rd    : %d"  ,_execute_operation_in->_num_reg_rd   );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * write_re      : %d"  ,_execute_operation_in->_write_re     );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * num_reg_re    : %d"  ,_execute_operation_in->_num_reg_re   );
+            
 #ifdef DEBUG_TEST
 	    if (type >= _param->_nb_type)
@@ -98,18 +119,30 @@
 	    if (type == TYPE_CUSTOM)
 	      {
-		uint32_t num_thread = get_num_thread(context_id   ,_param->_size_context_id,
-						     front_end_id ,_param->_size_front_end_id,
-						     ooo_engine_id,_param->_size_ooo_engine_id);
-
-		(*(_param->_get_custom_information(num_thread)._get_custom_execute_genMoore(operation))) (_execute_operation, execute_register, _execute_param);
+// 		uint32_t num_thread = get_num_thread(context_id   ,_param->_size_context_id,
+// 						     front_end_id ,_param->_size_front_end_id,
+// 						     ooo_engine_id,_param->_size_ooo_engine_id);
+
+		(*(_param->_get_custom_information()._get_custom_execute_genMoore(operation))) (_execute_operation_in, execute_register, _execute_param);
 	      }
 	    else
-	      (*(_function_execute[type][operation])) (_execute_operation, execute_register, _execute_param);
-
+	      (*(_function_execute[type][operation])) (_execute_operation_in, execute_register, _execute_param);
+
+
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    -----------------");
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * latence       : %.8x",_execute_operation_in->_timing._latence);
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * delay         : %.8x",_execute_operation_in->_timing._delay);
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * data_rd       : %.8x",_execute_operation_in->_data_rd    );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * data_re       : %.8x",_execute_operation_in->_data_re    );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * exception     : %d"  ,_execute_operation_in->_exception  );
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * no_sequence   : %d"  ,_execute_operation_in->_no_sequence);
+            log_printf(TRACE,Functionnal_unit,FUNCTION,"    * address       : %.8x",_execute_operation_in->_address    );
 
 #ifdef STATISTICS
-            (*_stat_use_functionnal_unit) ++;
-	    (*_stat_sum_delay)   += _execute_operation->_timing._delay;
-	    (*_stat_sum_latence) += _execute_operation->_timing._latence;
+            if (usage_is_set(_usage,USE_STATISTICS))
+              {
+                (*_stat_use_functionnal_unit) ++;
+                (*_stat_sum_delay)   += _execute_operation_in->_timing._delay;
+                (*_stat_sum_latence) += _execute_operation_in->_timing._latence;
+              }
 #endif
 	  }
@@ -121,11 +154,11 @@
 	      for (uint32_t k=0; k<_param->_nb_ooo_engine; k++)
 		{
-		  uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
-						       j,_param->_size_front_end_id,
-						       k,_param->_size_ooo_engine_id);
+// 		  uint32_t num_thread = get_num_thread(i,_param->_size_context_id,
+// 						       j,_param->_size_front_end_id,
+// 						       k,_param->_size_ooo_engine_id);
 
 		  for (uint32_t x=GROUP_CUSTOM_1; x<GROUP_CUSTOM_8; x++)
 		    {
-		      function_execute_end_cycle_t * fct = (_param->_get_custom_information(num_thread)._get_custom_execute_transition(x));
+		      function_execute_end_cycle_t * fct = (_param->_get_custom_information()._get_custom_execute_transition(x));
 		      
 		      if (fct != NULL)
@@ -142,9 +175,37 @@
 	    }
 	}
+
+	if (reg_BUSY_IN and not reg_BUSY_OUT)
+	  {
+	    reg_BUSY_OUT = reg_BUSY_IN;
+	    reg_BUSY_IN  = false;
+
+	    _execute_operation_out->_timing        = _execute_operation_in->_timing       ;
+	    _execute_operation_out->_context_id    = _execute_operation_in->_context_id   ;
+	    _execute_operation_out->_front_end_id  = _execute_operation_in->_front_end_id ;
+	    _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id;
+	    _execute_operation_out->_packet_id     = _execute_operation_in->_packet_id    ;
+	    _execute_operation_out->_operation     = _execute_operation_in->_operation    ;
+	    _execute_operation_out->_type          = _execute_operation_in->_type         ;
+	    _execute_operation_out->_has_immediat  = _execute_operation_in->_has_immediat ;
+	    _execute_operation_out->_immediat      = _execute_operation_in->_immediat     ;
+	    _execute_operation_out->_data_ra       = _execute_operation_in->_data_ra      ;
+	    _execute_operation_out->_data_rb       = _execute_operation_in->_data_rb      ;
+	    _execute_operation_out->_data_rc       = _execute_operation_in->_data_rc      ;
+	    _execute_operation_out->_data_rd       = _execute_operation_in->_data_rd      ;
+	    _execute_operation_out->_data_re       = _execute_operation_in->_data_re      ;
+	    _execute_operation_out->_write_rd      = _execute_operation_in->_write_rd     ;
+	    _execute_operation_out->_num_reg_rd    = _execute_operation_in->_num_reg_rd   ;
+	    _execute_operation_out->_write_re      = _execute_operation_in->_write_re     ;
+	    _execute_operation_out->_num_reg_re    = _execute_operation_in->_num_reg_re   ;
+	    _execute_operation_out->_exception     = _execute_operation_in->_exception    ;
+	    _execute_operation_out->_no_sequence   = _execute_operation_in->_no_sequence  ;
+	    _execute_operation_out->_address       = _execute_operation_in->_address      ;
+	  }
+	
+	// each cycle : decrease the latence
+	if (reg_BUSY_OUT and (_execute_operation_out->_timing._latence > 0))
+	  _execute_operation_out->_timing._latence --;
       }
-
-    // each cycle : decrease the latence
-    if (reg_BUSY and (_execute_operation->_timing._latence > 0))
-      _execute_operation->_timing._latence --;
 
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
@@ -152,5 +213,5 @@
 #endif
 
-    log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
+    log_end(Functionnal_unit,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp	(revision 88)
@@ -31,36 +31,38 @@
 			  uint32_t           size_load_queue    ,
 			  execute_timing_t** timing             ,
-			  morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)) :
-    _nb_context              (nb_context            ),
-    _nb_front_end            (nb_front_end          ),
-    _nb_ooo_engine           (nb_ooo_engine         ),
-    _nb_packet               (nb_packet             ),
-    _size_general_data       (size_general_data     ),
-    _nb_general_register     (nb_general_register   ),
-    _size_special_data       (size_special_data     ),
-    _nb_special_register     (nb_special_register   ),
-    _size_store_queue        (size_store_queue      ),
-    _size_load_queue         (size_load_queue       ),
-
-    _size_context_id         (log2(nb_context      )),
-    _size_front_end_id       (log2(nb_front_end    )),
-    _size_ooo_engine_id      (log2(nb_ooo_engine   )),
-    _size_packet_id          (log2(nb_packet       )),
-    _size_general_register   (log2(nb_general_register)),
-    _size_special_register   (log2(nb_special_register)),
-
-    _have_port_context_id    (_size_context_id    > 0),
-    _have_port_front_end_id  (_size_front_end_id  > 0),
-    _have_port_ooo_engine_id (_size_ooo_engine_id > 0),
-    _have_port_packet_id     (_size_packet_id     > 0),
-    _have_port_load_queue_ptr(_size_load_queue    > 1),
-
-    _have_groupe_MAC         ( (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC  ]._latence > 0) or
-			       (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence > 0) or
-			       (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB  ]._latence > 0))
+			  morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void),
+                          bool               is_toplevel)
   {
     log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
 
-    _timing                 = timing;
+    _nb_context              = nb_context            ;
+    _nb_front_end            = nb_front_end          ;
+    _nb_ooo_engine           = nb_ooo_engine         ;
+    _nb_packet               = nb_packet             ;
+//  _size_general_data       = size_general_data     ;
+//  _size_special_data       = size_special_data     ;
+//  _nb_general_register     = nb_general_register   ;
+//  _nb_special_register     = nb_special_register   ;
+//  _size_store_queue        = size_store_queue      ;
+//  _size_load_queue         = size_load_queue       ;
+
+//  _size_context_id         = log2(nb_context         );
+//  _size_front_end_id       = log2(nb_front_end       );
+//  _size_ooo_engine_id      = log2(nb_ooo_engine      );
+//  _size_packet_id          = log2(nb_packet          );
+//  _size_general_register   = log2(nb_general_register);
+//  _size_special_register   = log2(nb_special_register);
+
+//  _have_port_context_id    = _size_context_id    > 0;
+//  _have_port_front_end_id  = _size_front_end_id  > 0;
+//  _have_port_ooo_engine_id = _size_ooo_engine_id > 0;
+//  _have_port_packet_id     = _size_packet_id     > 0;
+//  _have_port_load_queue_ptr= _size_load_queue    > 1;
+
+    _have_groupe_MAC         = ( (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC  ]._latence > 0) or
+                                 (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence > 0) or
+                                 (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB  ]._latence > 0));
+
+    _timing                  = timing;
 
     if (get_custom_information == NULL)
@@ -71,48 +73,82 @@
     test();
 
+    if (is_toplevel)
+      {
+        _size_context_id         = log2(nb_context         );
+        _size_front_end_id       = log2(nb_front_end       );
+        _size_ooo_engine_id      = log2(nb_ooo_engine      );
+        _size_rob_ptr            = log2(nb_packet          );
+        _size_general_register   = log2(nb_general_register);
+        _size_special_register   = log2(nb_special_register);
+
+        _size_general_data       = size_general_data     ;
+        _size_special_data       = size_special_data     ;
+        _size_general_register   = log2(nb_general_register);
+        _size_special_register   = log2(nb_special_register);
+
+        _size_load_queue_ptr     = log2(size_load_queue );
+        _size_store_queue_ptr    = log2(size_store_queue);
+   
+        _have_port_context_id    = _size_context_id    > 0;
+        _have_port_front_end_id  = _size_front_end_id  > 0;
+        _have_port_ooo_engine_id = _size_ooo_engine_id > 0;
+        _have_port_rob_ptr       = _size_rob_ptr       > 0;
+        _have_port_load_queue_ptr= _size_load_queue_ptr> 0;
+
+        copy();
+      }
+
     log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
   };
   
+// #undef  FUNCTION
+// #define FUNCTION "Functionnal_unit::Parameters (copy)"
+//   Parameters::Parameters (Parameters & param):
+//     _nb_context              (param._nb_context             ),
+//     _nb_front_end            (param._nb_front_end           ),
+//     _nb_ooo_engine           (param._nb_ooo_engine          ),
+//     _nb_packet               (param._nb_packet              ),
+//     _size_general_data       (param._size_general_data      ),
+//     _nb_general_register     (param._nb_general_register    ),
+//     _size_special_data       (param._size_special_data      ),
+//     _nb_special_register     (param._nb_special_register    ),
+//     _size_store_queue        (param._size_store_queue       ),
+//     _size_load_queue         (param._size_load_queue        ),
+
+//     _size_context_id         (param._size_context_id        ),
+//     _size_front_end_id       (param._size_front_end_id      ),
+//     _size_ooo_engine_id      (param._size_ooo_engine_id     ),
+//     _size_packet_id          (param._size_packet_id         ),
+//     _size_general_register   (param._size_general_register  ),
+//     _size_special_register   (param._size_special_register  ),
+
+//     _have_port_context_id    (param._have_port_context_id   ),
+//     _have_port_front_end_id  (param._have_port_front_end_id ),
+//     _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
+//     _have_port_packet_id     (param._have_port_packet_id    ),
+//     _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
+
+//     _have_groupe_MAC         (param._have_groupe_MAC        )
+//   {
+//     log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
+
+//     _timing                 = param._timing;
+//     _get_custom_information = param._get_custom_information;
+
+//     test();
+//     log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
+//   };
+
 #undef  FUNCTION
-#define FUNCTION "Functionnal_unit::Parameters (copy)"
-  Parameters::Parameters (Parameters & param):
-    _nb_context              (param._nb_context             ),
-    _nb_front_end            (param._nb_front_end           ),
-    _nb_ooo_engine           (param._nb_ooo_engine          ),
-    _nb_packet               (param._nb_packet              ),
-    _size_general_data       (param._size_general_data      ),
-    _nb_general_register     (param._nb_general_register    ),
-    _size_special_data       (param._size_special_data      ),
-    _nb_special_register     (param._nb_special_register    ),
-    _size_store_queue        (param._size_store_queue       ),
-    _size_load_queue         (param._size_load_queue        ),
-
-    _size_context_id         (param._size_context_id        ),
-    _size_front_end_id       (param._size_front_end_id      ),
-    _size_ooo_engine_id      (param._size_ooo_engine_id     ),
-    _size_packet_id          (param._size_packet_id         ),
-    _size_general_register   (param._size_general_register  ),
-    _size_special_register   (param._size_special_register  ),
-
-    _have_port_context_id    (param._have_port_context_id   ),
-    _have_port_front_end_id  (param._have_port_front_end_id ),
-    _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
-    _have_port_packet_id     (param._have_port_packet_id    ),
-    _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
-
-    _have_groupe_MAC         (param._have_groupe_MAC        )
+#define FUNCTION "Functionnal_unit::~Parameters"
+  Parameters::~Parameters (void)
   {
     log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
-
-    _timing                 = param._timing;
-    _get_custom_information = param._get_custom_information;
-
-    test();
     log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
   };
 
 #undef  FUNCTION
-#define FUNCTION "Functionnal_unit::~Parameters"
-  Parameters::~Parameters () 
+#define FUNCTION "Functionnal_unit::copy"
+  void Parameters::copy (void)
   {
     log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp	(revision 88)
@@ -31,10 +31,10 @@
       for (uint32_t j=0; j<_nb_operation; j++)
 	if (_timing[i][j]._delay != _timing[i][j]._latence)
-	  test.error("For the type '"+toString(i)+"', and the operation '"+toString(j)+"', the delay and the latence must be equal.");
+	  test.error(toString(_("For the type '%d', and the operation '%d', the delay and the latence must be equal.\n"),i,j));
 
     if (_have_groupe_MAC and ((_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC  ]._latence == 0) or
 			      (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence == 0) or
 			      (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB  ]._latence == 0)))
-      test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0.");
+      test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0.\n");
 
     log_printf(FUNC,Functionnal_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp	(revision 88)
@@ -32,7 +32,7 @@
     xml.singleton_begin("nb_packet          "); xml.attribut("value",toString(_nb_packet          )); xml.singleton_end();
     xml.singleton_begin("size_general_data  "); xml.attribut("value",toString(_size_general_data  )); xml.singleton_end();
-    xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end();
+//  xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end();
     xml.singleton_begin("size_special_data  "); xml.attribut("value",toString(_size_special_data  )); xml.singleton_end();
-    xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end();
+//  xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end();
     xml.balise_close();
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Load_store_unit_library_clean
 
+local_clean			:
+
 include                         ../Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg	(revision 88)
@@ -6,4 +6,6 @@
 2	2	+1	# speculative_load       {none,access,commit,bypass}
 0	0	+1	# bypass_memory
+1	1	+1	# nb_cache_port 
+1	1	+1	# nb_inst_memory
 2	2	*2	# nb_context             1	1	*2	
 2	2	*2	# nb_front_end		 1	1	*2	
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h	(revision 88)
@@ -287,5 +287,5 @@
 		  << i->_data_old << " -> "
 		  << i->_data_new << std::endl
-		  << std::hex;
+		  << std::dec;
       }
   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp	(revision 88)
@@ -22,4 +22,6 @@
        << " - speculative_load        (uint32_t)" << endl
        << " - nb_bypass_memory        (uint32_t)" << endl
+       << " - nb_cache_port           (uint32_t)" << endl
+       << " - nb_inst_memory          (uint32_t)" << endl
        << " - nb_context              (uint32_t)" << endl
        << " - nb_front_end            (uint32_t)" << endl
@@ -62,4 +64,6 @@
 	const Tspeculative_load_t _speculative_load        = fromString<Tspeculative_load_t>(argv[x++]);
 	const uint32_t            _nb_bypass_memory        = atoi(argv[x++]);
+	const uint32_t            _nb_cache_port           = atoi(argv[x++]);
+	const uint32_t            _nb_inst_memory          = atoi(argv[x++]);
 	const uint32_t            _nb_context              = atoi(argv[x++]);
 	const uint32_t            _nb_front_end            = atoi(argv[x++]);
@@ -81,4 +85,6 @@
 	       _speculative_load       ,
 	       _nb_bypass_memory       ,
+	       _nb_cache_port          ,
+	       _nb_inst_memory         ,
 	       _nb_context             ,
 	       _nb_front_end           ,
@@ -88,5 +94,7 @@
 	       _size_special_data      ,
 	       _nb_general_register    ,
-	       _nb_special_register    );
+	       _nb_special_register    ,
+               true //is_toplevel
+               );
 	    
 	    cout << param->print(1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp	(revision 88)
@@ -9,4 +9,5 @@
 #include <queue>
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
+#include "Behavioural/include/Allocation.h"
 
 //===================================================================={test}
@@ -26,4 +27,6 @@
 	 SPECULATIVE_LOAD_COMMIT,  //_speculative_load       
 	 0,  //_nb_bypass_memory
+	 1,  //_nb_cache_port
+	 1,  //_nb_inst_memory
 	 1,  //_nb_context             
 	 1,  //_nb_front_end           
@@ -33,5 +36,6 @@
 	 2 , //_size_special_data      
 	 64, //_nb_general_register    
-	 16  //_nb_special_register    
+	 16, //_nb_special_register    
+         true //is_toplevel
         );
 
@@ -39,4 +43,14 @@
   morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
@@ -45,5 +59,5 @@
 #endif
 							    _param,
-							    USE_ALL);
+							    _usage);
   
 #ifdef SYSTEMC
@@ -56,69 +70,58 @@
   sc_signal<Tcontrol_t>                  * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_VAL                   = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_IN_ACK                   = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tcontext_t        > *   in_MEMORY_IN_CONTEXT_ID            = new sc_signal<Tcontext_t        > (rename.c_str());
-  sc_signal<Tcontext_t        > *   in_MEMORY_IN_FRONT_END_ID          = new sc_signal<Tcontext_t        > (rename.c_str());
-  sc_signal<Tcontext_t        > *   in_MEMORY_IN_OOO_ENGINE_ID         = new sc_signal<Tcontext_t        > (rename.c_str());
-  sc_signal<Tpacket_t         > *   in_MEMORY_IN_PACKET_ID             = new sc_signal<Tpacket_t         > (rename.c_str());
-  sc_signal<Toperation_t      > *   in_MEMORY_IN_OPERATION             = new sc_signal<Toperation_t      > (rename.c_str());
-  sc_signal<Ttype_t           > *   in_MEMORY_IN_TYPE                  = new sc_signal<Ttype_t           > (rename.c_str());
-  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
-  sc_signal<Tlsq_ptr_t        > *   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = new sc_signal<Tlsq_ptr_t        > (rename.c_str());
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_HAS_IMMEDIAT          = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_IMMEDIAT              = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RA               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-  sc_signal<Tgeneral_data_t   > *   in_MEMORY_IN_DATA_RB               = new sc_signal<Tgeneral_data_t   > (rename.c_str());
-  sc_signal<Tspecial_data_t   > *   in_MEMORY_IN_DATA_RC               = new sc_signal<Tspecial_data_t   > (rename.c_str());
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RD              = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tgeneral_address_t> *   in_MEMORY_IN_NUM_REG_RD            = new sc_signal<Tgeneral_address_t> (rename.c_str());
-  sc_signal<Tcontrol_t        > *   in_MEMORY_IN_WRITE_RE              = new sc_signal<Tcontrol_t        > (rename.c_str());
-  sc_signal<Tspecial_address_t> *   in_MEMORY_IN_NUM_REG_RE            = new sc_signal<Tspecial_address_t> (rename.c_str());
-
-  sc_signal<Tcontrol_t	      > *  out_MEMORY_OUT_VAL           = new sc_signal<Tcontrol_t	  >(rename.c_str());
-  sc_signal<Tcontrol_t	      > *   in_MEMORY_OUT_ACK           = new sc_signal<Tcontrol_t	  >(rename.c_str());
-  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_CONTEXT_ID    = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_FRONT_END_ID  = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > *  out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > *  out_MEMORY_OUT_PACKET_ID     = new sc_signal<Tpacket_t         >(rename.c_str());
-//   sc_signal<Toperation_t      > *  out_MEMORY_OUT_OPERATION     = new sc_signal<Toperation_t      >(rename.c_str());
-  sc_signal<Ttype_t           > *  out_MEMORY_OUT_TYPE          = new sc_signal<Ttype_t           >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RD      = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tgeneral_address_t> *  out_MEMORY_OUT_NUM_REG_RD    = new sc_signal<Tgeneral_address_t>(rename.c_str());
-  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_DATA_RD       = new sc_signal<Tgeneral_data_t   >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_WRITE_RE      = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tspecial_address_t> *  out_MEMORY_OUT_NUM_REG_RE    = new sc_signal<Tspecial_address_t>(rename.c_str());
-  sc_signal<Tspecial_data_t   > *  out_MEMORY_OUT_DATA_RE       = new sc_signal<Tspecial_data_t   >(rename.c_str());
-  sc_signal<Texception_t      > *  out_MEMORY_OUT_EXCEPTION     = new sc_signal<Texception_t      >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  out_MEMORY_OUT_NO_SEQUENCE   = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tgeneral_data_t   > *  out_MEMORY_OUT_ADDRESS       = new sc_signal<Tgeneral_data_t   >(rename.c_str());
-
-  sc_signal<Tcontrol_t        > * out_DCACHE_REQ_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontrol_t        > *  in_DCACHE_REQ_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > * out_DCACHE_REQ_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS    = new sc_signal<Tdcache_address_t >(rename.c_str());
-  sc_signal<Tdcache_type_t    > * out_DCACHE_REQ_TYPE       = new sc_signal<Tdcache_type_t    >(rename.c_str());
-  sc_signal<Tdcache_data_t    > * out_DCACHE_REQ_WDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
-  
-  sc_signal<Tcontrol_t        > *  in_DCACHE_RSP_VAL        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontrol_t        > * out_DCACHE_RSP_ACK        = new sc_signal<Tcontrol_t        >(rename.c_str());
-  sc_signal<Tcontext_t        > *  in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t        >(rename.c_str());
-  sc_signal<Tpacket_t         > *  in_DCACHE_RSP_PACKET_ID  = new sc_signal<Tpacket_t         >(rename.c_str());
-  sc_signal<Tdcache_data_t    > *  in_DCACHE_RSP_RDATA      = new sc_signal<Tdcache_data_t    >(rename.c_str());
-  sc_signal<Tdcache_error_t   > *  in_DCACHE_RSP_ERROR      = new sc_signal<Tdcache_error_t   >(rename.c_str());
-  
-  sc_signal<Tcontrol_t        > ** out_BYPASS_MEMORY_VAL           = new sc_signal<Tcontrol_t        > * [_param->_nb_bypass_memory];
-  sc_signal<Tcontext_t        > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t        > * [_param->_nb_bypass_memory];
-  sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG       = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory];
-  sc_signal<Tgeneral_data_t   > ** out_BYPASS_MEMORY_DATA          = new sc_signal<Tgeneral_data_t   > * [_param->_nb_bypass_memory];
-    
-  for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
-    {
-      out_BYPASS_MEMORY_VAL           [i] = new sc_signal<Tcontrol_t        >(rename.c_str());
-      out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t        >(rename.c_str());
-      out_BYPASS_MEMORY_NUM_REG       [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
-      out_BYPASS_MEMORY_DATA          [i] = new sc_signal<Tgeneral_data_t   >(rename.c_str());
-    }
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL                  ," in_MEMORY_IN_VAL                  ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK                  ,"out_MEMORY_IN_ACK                  ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID           ," in_MEMORY_IN_CONTEXT_ID           ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID         ," in_MEMORY_IN_FRONT_END_ID         ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID        ," in_MEMORY_IN_OOO_ENGINE_ID        ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID            ," in_MEMORY_IN_PACKET_ID            ",Tpacket_t         ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_OPERATION            ," in_MEMORY_IN_OPERATION            ",Toperation_t      ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_TYPE                 ," in_MEMORY_IN_TYPE                 ",Ttype_t           ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE," in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ," in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT         ," in_MEMORY_IN_HAS_IMMEDIAT         ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT             ," in_MEMORY_IN_IMMEDIAT             ",Tgeneral_data_t   ,_param->_nb_inst_memory); // memory address
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RA              ," in_MEMORY_IN_DATA_RA              ",Tgeneral_data_t   ,_param->_nb_inst_memory); // memory address
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RB              ," in_MEMORY_IN_DATA_RB              ",Tgeneral_data_t   ,_param->_nb_inst_memory); // data        (store)
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RC              ," in_MEMORY_IN_DATA_RC              ",Tspecial_data_t   ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD             ," in_MEMORY_IN_WRITE_RD             ",Tcontrol_t        ,_param->_nb_inst_memory); // = (operation==load)
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD           ," in_MEMORY_IN_NUM_REG_RD           ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load)
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE             ," in_MEMORY_IN_WRITE_RE             ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE           ," in_MEMORY_IN_NUM_REG_RE           ",Tspecial_address_t,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_VAL                 ,"out_MEMORY_OUT_VAL                 ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL( in_MEMORY_OUT_ACK                 ," in_MEMORY_OUT_ACK                 ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID          ,"out_MEMORY_OUT_CONTEXT_ID          ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID        ,"out_MEMORY_OUT_FRONT_END_ID        ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID       ,"out_MEMORY_OUT_OOO_ENGINE_ID       ",Tcontext_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID           ,"out_MEMORY_OUT_PACKET_ID           ",Tpacket_t         ,_param->_nb_inst_memory);
+//ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION           ,"out_MEMORY_OUT_OPERATION           ",Toperation_t      ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE                ,"out_MEMORY_OUT_TYPE                ",Ttype_t           ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD            ,"out_MEMORY_OUT_WRITE_RD            ",Tcontrol_t        ,_param->_nb_inst_memory); // = (operation==load)
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD          ,"out_MEMORY_OUT_NUM_REG_RD          ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load)
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD             ,"out_MEMORY_OUT_DATA_RD             ",Tgeneral_data_t   ,_param->_nb_inst_memory); // data        (load)
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE            ,"out_MEMORY_OUT_WRITE_RE            ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE          ,"out_MEMORY_OUT_NUM_REG_RE          ",Tspecial_address_t,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE             ,"out_MEMORY_OUT_DATA_RE             ",Tspecial_data_t   ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION           ,"out_MEMORY_OUT_EXCEPTION           ",Texception_t      ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE         ,"out_MEMORY_OUT_NO_SEQUENCE         ",Tcontrol_t        ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS             ,"out_MEMORY_OUT_ADDRESS             ",Tgeneral_data_t   ,_param->_nb_inst_memory);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL                 ,"out_DCACHE_REQ_VAL                 ",Tcontrol_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK                 ," in_DCACHE_REQ_ACK                 ",Tcontrol_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID          ,"out_DCACHE_REQ_CONTEXT_ID          ",Tcontext_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID           ,"out_DCACHE_REQ_PACKET_ID           ",Tpacket_t         ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS             ,"out_DCACHE_REQ_ADDRESS             ",Tdcache_address_t ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE                ,"out_DCACHE_REQ_TYPE                ",Tdcache_type_t    ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA               ,"out_DCACHE_REQ_WDATA               ",Tdcache_data_t    ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL                 ," in_DCACHE_RSP_VAL                 ",Tcontrol_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK                 ,"out_DCACHE_RSP_ACK                 ",Tcontrol_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID          ," in_DCACHE_RSP_CONTEXT_ID          ",Tcontext_t        ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID           ," in_DCACHE_RSP_PACKET_ID           ",Tpacket_t         ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA               ," in_DCACHE_RSP_RDATA               ",Tdcache_data_t    ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR               ," in_DCACHE_RSP_ERROR               ",Tdcache_error_t   ,_param->_nb_cache_port);
+  ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_VAL              ,"out_BYPASS_MEMORY_VAL              ",Tcontrol_t        ,_param->_nb_bypass_memory);
+  ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID    ,"out_BYPASS_MEMORY_OOO_ENGINE_ID    ",Tcontext_t        ,_param->_nb_bypass_memory);
+  ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG          ,"out_BYPASS_MEMORY_NUM_REG          ",Tgeneral_address_t,_param->_nb_bypass_memory);
+  ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_DATA             ,"out_BYPASS_MEMORY_DATA             ",Tgeneral_data_t   ,_param->_nb_bypass_memory);
   
   /********************************************************
@@ -131,78 +134,74 @@
   (*(_Load_store_unit->in_NRESET))       (*(in_NRESET));
 
-  (*(_Load_store_unit-> in_MEMORY_IN_VAL                  ))(*( in_MEMORY_IN_VAL                  ));
-  (*(_Load_store_unit->out_MEMORY_IN_ACK                  ))(*(out_MEMORY_IN_ACK                  ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_VAL                  ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_IN_ACK                  ,_param->_nb_inst_memory);
   if (_param->_have_port_context_id)
-    (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID           ))(*( in_MEMORY_IN_CONTEXT_ID           ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_CONTEXT_ID           ,_param->_nb_inst_memory);
   if (_param->_have_port_front_end_id)
-    (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID         ))(*( in_MEMORY_IN_FRONT_END_ID         ));
-  if (_param->_have_port_ooo_engine_id)
-    (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID        ))(*( in_MEMORY_IN_OOO_ENGINE_ID        ));
-  if (_param->_have_port_packet_id)
-    (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID            ))(*( in_MEMORY_IN_PACKET_ID            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_OPERATION            ))(*( in_MEMORY_IN_OPERATION            ));
-  (*(_Load_store_unit-> in_MEMORY_IN_TYPE                 ))(*( in_MEMORY_IN_TYPE                 ));
-  (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
-  if (_param->_have_port_load_queue_ptr)
-  (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
-  (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT         ))(*( in_MEMORY_IN_HAS_IMMEDIAT         ));
-  (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT             ))(*( in_MEMORY_IN_IMMEDIAT             ));
-  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA              ))(*( in_MEMORY_IN_DATA_RA              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB              ))(*( in_MEMORY_IN_DATA_RB              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC              ))(*( in_MEMORY_IN_DATA_RC              ));
-  (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD             ))(*( in_MEMORY_IN_WRITE_RD             ));
-  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD           ))(*( in_MEMORY_IN_NUM_REG_RD           ));
-  (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE             ))(*( in_MEMORY_IN_WRITE_RE             ));
-  (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE           ))(*( in_MEMORY_IN_NUM_REG_RE           ));
-  
-  (*(_Load_store_unit->out_MEMORY_OUT_VAL           ))(*(out_MEMORY_OUT_VAL           ));
-  (*(_Load_store_unit-> in_MEMORY_OUT_ACK           ))(*( in_MEMORY_OUT_ACK           ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_FRONT_END_ID         ,_param->_nb_inst_memory);
+  if (_param->_have_port_ooo_engine_id)    
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OOO_ENGINE_ID        ,_param->_nb_inst_memory);
+  if (_param->_have_port_rob_ptr)
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_PACKET_ID            ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OPERATION            ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_TYPE                 ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_HAS_IMMEDIAT         ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_IMMEDIAT             ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RA              ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RB              ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RC              ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RD             ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RD           ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RE             ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RE           ,_param->_nb_inst_memory);
+
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_VAL          ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_OUT_ACK          ,_param->_nb_inst_memory);
   if (_param->_have_port_context_id)
-    (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID    ))(*(out_MEMORY_OUT_CONTEXT_ID    ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_CONTEXT_ID   ,_param->_nb_inst_memory);
   if (_param->_have_port_front_end_id)
-    (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID  ))(*(out_MEMORY_OUT_FRONT_END_ID  ));
-  if (_param->_have_port_ooo_engine_id)
-    (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID ));
-  if (_param->_have_port_packet_id)
-    (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID     ))(*(out_MEMORY_OUT_PACKET_ID     ));
-//   (*(_Load_store_unit->out_MEMORY_OUT_OPERATION     ))(*(out_MEMORY_OUT_OPERATION     ));
-  (*(_Load_store_unit->out_MEMORY_OUT_TYPE          ))(*(out_MEMORY_OUT_TYPE          ));
-  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD      ))(*(out_MEMORY_OUT_WRITE_RD      ));
-  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD    ))(*(out_MEMORY_OUT_NUM_REG_RD    ));
-  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD       ))(*(out_MEMORY_OUT_DATA_RD       ));
-  (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE      ))(*(out_MEMORY_OUT_WRITE_RE      ));
-  (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE    ))(*(out_MEMORY_OUT_NUM_REG_RE    ));
-  (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE       ))(*(out_MEMORY_OUT_DATA_RE       ));
-  (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION     ))(*(out_MEMORY_OUT_EXCEPTION     ));
-  (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE   ))(*(out_MEMORY_OUT_NO_SEQUENCE   ));
-  (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS       ))(*(out_MEMORY_OUT_ADDRESS       ));
-
-  (*(_Load_store_unit->out_DCACHE_REQ_VAL       ))(*(out_DCACHE_REQ_VAL       ));
-  (*(_Load_store_unit-> in_DCACHE_REQ_ACK       ))(*( in_DCACHE_REQ_ACK       ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory);
+  if (_param->_have_port_ooo_engine_id)    
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory);
+  if (_param->_have_port_rob_ptr)
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID    ,_param->_nb_inst_memory);
+//INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION    ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE         ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD     ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD   ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RD      ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RE     ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RE   ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RE      ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_EXCEPTION    ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NO_SEQUENCE  ,_param->_nb_inst_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_ADDRESS      ,_param->_nb_inst_memory);
+
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_VAL        ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_REQ_ACK        ,_param->_nb_cache_port);
   if (_param->_have_port_dcache_context_id)
-    (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID));
-  (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID ));
-  (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS   ))(*(out_DCACHE_REQ_ADDRESS   ));
-  (*(_Load_store_unit->out_DCACHE_REQ_TYPE      ))(*(out_DCACHE_REQ_TYPE      ));
-  (*(_Load_store_unit->out_DCACHE_REQ_WDATA     ))(*(out_DCACHE_REQ_WDATA     ));
-
-  (*(_Load_store_unit-> in_DCACHE_RSP_VAL       ))(*( in_DCACHE_RSP_VAL       ));
-  (*(_Load_store_unit->out_DCACHE_RSP_ACK       ))(*(out_DCACHE_RSP_ACK       ));
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_PACKET_ID  ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_ADDRESS    ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_TYPE       ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_WDATA      ,_param->_nb_cache_port);
+
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_VAL        ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_RSP_ACK        ,_param->_nb_cache_port);
   if (_param->_have_port_dcache_context_id)
-    (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID));
-  (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_RDATA     ))(*( in_DCACHE_RSP_RDATA     ));
-  (*(_Load_store_unit-> in_DCACHE_RSP_ERROR     ))(*( in_DCACHE_RSP_ERROR     ));
-
-    {
-      for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
-	{
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_VAL           [i]))(*(out_BYPASS_MEMORY_VAL           [i]));
-	  if (_param->_have_port_ooo_engine_id)    
-	    (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG       [i]))(*(out_BYPASS_MEMORY_NUM_REG       [i]));
-	  (*(_Load_store_unit->out_BYPASS_MEMORY_DATA          [i]))(*(out_BYPASS_MEMORY_DATA          [i]));
-	}
-    }
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_PACKET_ID  ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_RDATA      ,_param->_nb_cache_port);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_ERROR      ,_param->_nb_cache_port);
+
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_VAL           ,_param->_nb_bypass_memory);
+  if (_param->_have_port_ooo_engine_id)    
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_NUM_REG       ,_param->_nb_bypass_memory);
+  INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_DATA          ,_param->_nb_bypass_memory);
+
+
   cout << "<" << name << "> Start Simulation ............" << endl;
   Time * _time = new Time();
@@ -238,8 +237,8 @@
   LABEL("Initialisation");
 
-  in_MEMORY_IN_VAL ->write(0);
-  in_MEMORY_OUT_ACK->write(0);
-  in_DCACHE_REQ_ACK->write(0);
-  in_DCACHE_RSP_VAL->write(0);
+  in_MEMORY_IN_VAL [0]->write(0);
+  in_MEMORY_OUT_ACK[0]->write(0);
+  in_DCACHE_REQ_ACK[0]->write(0);
+  in_DCACHE_RSP_VAL[0]->write(0);
 
   in_NRESET        ->write(0);
@@ -419,50 +418,50 @@
 		    can_execute &= not load_queue_use  [fifo_request.top()._load_queue_ptr_write];
 		}
-	      in_MEMORY_IN_VAL ->write(can_execute);
+	      in_MEMORY_IN_VAL [0]->write(can_execute);
 	
 	      if (not fifo_request.empty())
 		{
 		  if (_param->_have_port_context_id)
-		    in_MEMORY_IN_CONTEXT_ID           ->write (fifo_request.top()._context_id           );
+		    in_MEMORY_IN_CONTEXT_ID           [0]->write (fifo_request.top()._context_id           );
 		  if (_param->_have_port_front_end_id)
-		    in_MEMORY_IN_FRONT_END_ID         ->write (fifo_request.top()._front_end_id         );
+		    in_MEMORY_IN_FRONT_END_ID         [0]->write (fifo_request.top()._front_end_id         );
 		  if (_param->_have_port_ooo_engine_id)
-		    in_MEMORY_IN_OOO_ENGINE_ID        ->write (fifo_request.top()._ooo_engine_id        );
-		  if (_param->_have_port_packet_id)
-		    in_MEMORY_IN_PACKET_ID            ->write (fifo_request.top()._packet_id            );
-		  in_MEMORY_IN_OPERATION            ->write (fifo_request.top()._operation            );
-		  in_MEMORY_IN_TYPE                 ->write (fifo_request.top()._type                 );
-		  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
+		    in_MEMORY_IN_OOO_ENGINE_ID        [0]->write (fifo_request.top()._ooo_engine_id        );
+		  if (_param->_have_port_rob_ptr)
+		    in_MEMORY_IN_PACKET_ID            [0]->write (fifo_request.top()._packet_id            );
+		  in_MEMORY_IN_OPERATION            [0]->write (fifo_request.top()._operation            );
+		  in_MEMORY_IN_TYPE                 [0]->write (fifo_request.top()._type                 );
+		  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[0]->write (fifo_request.top()._store_queue_ptr_write);
 		  if (_param->_have_port_load_queue_ptr)
-		  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
-		  in_MEMORY_IN_IMMEDIAT             ->write (fifo_request.top()._immediat             );
-		  in_MEMORY_IN_DATA_RA              ->write (fifo_request.top()._data_ra              );
-		  in_MEMORY_IN_DATA_RB              ->write (fifo_request.top()._data_rb              );
-// 		  in_MEMORY_IN_WRITE_RD             ->write (fifo_request.top()._write_rd             );
-		  in_MEMORY_IN_NUM_REG_RD           ->write (fifo_request.top()._num_reg_rd           );
+		  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE [0]->write (fifo_request.top()._load_queue_ptr_write );
+		  in_MEMORY_IN_IMMEDIAT             [0]->write (fifo_request.top()._immediat             );
+		  in_MEMORY_IN_DATA_RA              [0]->write (fifo_request.top()._data_ra              );
+		  in_MEMORY_IN_DATA_RB              [0]->write (fifo_request.top()._data_rb              );
+// 		  in_MEMORY_IN_WRITE_RD             [0]->write (fifo_request.top()._write_rd             );
+		  in_MEMORY_IN_NUM_REG_RD           [0]->write (fifo_request.top()._num_reg_rd           );
 		}
-	      in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
+	      in_MEMORY_OUT_ACK[0]->write((rand()%100)<percent_transaction_memory_out);
 
 	      // ***** DCACHE_REQ *****
-	      in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
+	      in_DCACHE_REQ_ACK[0]->write((rand()%100)<percent_transaction_dcache);
 
 	      // ***** DCACHE_RSP *****
 	      bool have_rsp = _cache->have_rsp ();
-	      in_DCACHE_RSP_VAL->write(have_rsp);
+	      in_DCACHE_RSP_VAL[0]->write(have_rsp);
 
 	      if (have_rsp)
 		{
-		  in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
-		  in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
-		  in_DCACHE_RSP_RDATA     ->write(_cache->front()._rdata     );
-		  in_DCACHE_RSP_ERROR     ->write(_cache->front()._error     );
+		  in_DCACHE_RSP_CONTEXT_ID[0]->write(_cache->front()._context_id);
+		  in_DCACHE_RSP_PACKET_ID [0]->write(_cache->front()._packet_id );
+		  in_DCACHE_RSP_RDATA     [0]->write(_cache->front()._rdata     );
+		  in_DCACHE_RSP_ERROR     [0]->write(_cache->front()._error     );
 		}
 
 	      SC_START(0);
 
-	      LABEL("MEMORY_IN  : %d - %d",in_MEMORY_IN_VAL ->read(),out_MEMORY_IN_ACK ->read());
-	      if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
+	      LABEL("MEMORY_IN  : %d - %d",in_MEMORY_IN_VAL [0]->read(),out_MEMORY_IN_ACK [0]->read());
+	      if ( in_MEMORY_IN_VAL [0]->read() and out_MEMORY_IN_ACK [0]->read())
 		{
-		  Tpacket_t  packet_id = in_MEMORY_IN_PACKET_ID->read();
+		  Tpacket_t  packet_id = in_MEMORY_IN_PACKET_ID[0]->read();
 
 		  LABEL(" * Accepted MEMORY_IN  : %d",packet_id);
@@ -483,8 +482,8 @@
 		}
 
-	      LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL->read(),in_MEMORY_OUT_ACK ->read());
-	      if (out_MEMORY_OUT_VAL->read() and  in_MEMORY_OUT_ACK->read())
+	      LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL[0]->read(),in_MEMORY_OUT_ACK [0]->read());
+	      if (out_MEMORY_OUT_VAL[0]->read() and  in_MEMORY_OUT_ACK[0]->read())
 		{
-		  Tpacket_t  packet_id = out_MEMORY_OUT_PACKET_ID->read();
+		  Tpacket_t  packet_id = out_MEMORY_OUT_PACKET_ID[0]->read();
 
 		  LABEL(" * Accepted MEMORY_OUT : %d",packet_id);
@@ -499,5 +498,5 @@
 		  else
 		    {
-		      if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
+		      if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
 			{
 			  nb_request_memory_out ++;
@@ -508,5 +507,5 @@
 			{
 			  std::cout << "seth - have a load_speculative." << std::endl;
-			  tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
+			  tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD[0]->read() != tab_request[packet_id]._data_wait);
 			  tab_request[packet_id]._previous_load_speculative = 1;
 			}
@@ -516,14 +515,14 @@
 
 		  // a lot of test
-		  TEST(Tpacket_t         , out_MEMORY_OUT_PACKET_ID    ->read(), tab_request[packet_id]._packet_id    );
-		  TEST(Tcontext_t        , out_MEMORY_OUT_CONTEXT_ID   ->read(), tab_request[packet_id]._context_id   );
-		  TEST(Tcontext_t        , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
-		  TEST(Tcontext_t        , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
-// 		  TEST(Toperation_t      , out_MEMORY_OUT_OPERATION    ->read(), tab_request[packet_id]._operation    );
-		  TEST(Ttype_t           , out_MEMORY_OUT_TYPE         ->read(), TYPE_MEMORY                          );
+		  TEST(Tpacket_t         , out_MEMORY_OUT_PACKET_ID    [0]->read(), tab_request[packet_id]._packet_id    );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_CONTEXT_ID   [0]->read(), tab_request[packet_id]._context_id   );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_FRONT_END_ID [0]->read(), tab_request[packet_id]._front_end_id );
+		  TEST(Tcontext_t        , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id);
+// 		  TEST(Toperation_t      , out_MEMORY_OUT_OPERATION    [0]->read(), tab_request[packet_id]._operation    );
+		  TEST(Ttype_t           , out_MEMORY_OUT_TYPE         [0]->read(), TYPE_MEMORY                          );
 
 		  if (is_operation_memory_load (tab_request[packet_id]._operation))
 		    {
-		      TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD   ->read(), tab_request[packet_id]._num_reg_rd   );
+		      TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD   [0]->read(), tab_request[packet_id]._num_reg_rd   );
 		    }
 
@@ -532,9 +531,9 @@
 		  bool            error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
 		  bool            berr            = (address >= size_memory);
-		  Texception_t    exception       = out_MEMORY_OUT_EXCEPTION->read();
+		  Texception_t    exception       = out_MEMORY_OUT_EXCEPTION[0]->read();
 
 		  if (is_operation_memory_store(tab_request[packet_id]._operation))
 		    {
-		      TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), 0);
+		      TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     [0]->read(), 0);
 
 		      // store.
@@ -568,5 +567,5 @@
 			  if (test_result_ko)
 			    {
-			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), address);
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD[0]->read(), address);
 			    }
 		    }
@@ -578,5 +577,5 @@
 		      bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
 
-		      if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
+		      if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
 			{
 			  bool test_result_ko = false;
@@ -586,5 +585,5 @@
 			      // IS A LOAD :D
 			      TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
-			      TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
+			      TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), 1);
 			    }
 			  else
@@ -592,5 +591,5 @@
 			      {
 				TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
-				TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
+				TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), is_load);
 				test_result_ko = true;
 			      }
@@ -599,5 +598,5 @@
 				{
 				  TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
-				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD->read(), is_load);
+				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load);
 				  test_result_ko = true;
 				}
@@ -605,37 +604,37 @@
 				{
 				  TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
-				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
+				  TEST(Tcontrol_t  , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
 				}
 			  // In all case : test data
 			  if (test_result_ko)
 			    {
-			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), address);
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD[0]->read(), address);
 			    }
 			  else
 			    {
-			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
+			      TEST(Tgeneral_data_t   , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait);
 			    }
 			}
 		      else
 			{
-			  TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     ->read(), 1);
+			  TEST(Tcontrol_t        , out_MEMORY_OUT_WRITE_RD     [0]->read(), 1);
 			}
 		    }
 		}
 
-	      LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL->read(),in_DCACHE_REQ_ACK ->read());
-	      if (out_DCACHE_REQ_VAL->read() and  in_DCACHE_REQ_ACK->read())
+	      LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL[0]->read(),in_DCACHE_REQ_ACK [0]->read());
+	      if (out_DCACHE_REQ_VAL[0]->read() and  in_DCACHE_REQ_ACK[0]->read())
 		{
 		  Tcontext_t        context_id;
 		  Tpacket_t         packet_id ; 
-		  Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
+		  Tdcache_address_t address = out_DCACHE_REQ_ADDRESS[0]->read();
 		  Tdcache_data_t    rdata;
 		  Tdcache_error_t   error = 0;
 		  if (_param->_have_port_dcache_context_id)
-		    context_id = out_DCACHE_REQ_CONTEXT_ID->read();
+		    context_id = out_DCACHE_REQ_CONTEXT_ID[0]->read();
 		  else
 		    context_id = 0;
 
-		  packet_id  = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
+		  packet_id  = (out_DCACHE_REQ_PACKET_ID [0]->read())>>1;
 	      
 		  LABEL(" * Accepted DCACHE_REQ : %d",packet_id);
@@ -649,23 +648,23 @@
 		  else
 		    {
-		      rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
+		      rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE[0]->read(), out_DCACHE_REQ_WDATA[0]->read());
 		      LABEL("   * rdata : 0x%x",rdata);
 		    }
 
 		  // test type : send or not a respons !
-		  if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
-		      (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or
-		      (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or
-		      (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or
-		      (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64) or
-		      ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or
-							 (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or
-							 (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or
-							 (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) )))
+		  if ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_SYNCHRONIZATION) or
+		      (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_8 ) or
+		      (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_16) or
+		      (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_32) or
+		      (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_64) or
+		      ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_8 ) or
+							 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_16) or
+							 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_32) or
+							 (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_64) )))
 		    {
 		      LABEL("     * have_dcache_rsp");
 		  
 		      _cache->push (context_id,
-				    out_DCACHE_REQ_PACKET_ID ->read(),
+				    out_DCACHE_REQ_PACKET_ID [0]->read(),
 				    rdata,
 				    error);
@@ -673,6 +672,6 @@
 		}
 
-	      LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL->read(),out_DCACHE_RSP_ACK ->read());
-	      if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
+	      LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL[0]->read(),out_DCACHE_RSP_ACK [0]->read());
+	      if (in_DCACHE_RSP_VAL[0]->read() and out_DCACHE_RSP_ACK[0]->read())
 		{
 		  _cache->pop();
@@ -704,62 +703,61 @@
   delete     in_NRESET;
 
-  delete     in_MEMORY_IN_VAL         ;
-  delete    out_MEMORY_IN_ACK         ;
-  delete     in_MEMORY_IN_CONTEXT_ID  ;
-  delete     in_MEMORY_IN_FRONT_END_ID  ;
-  delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
-  delete     in_MEMORY_IN_PACKET_ID   ;
-  delete     in_MEMORY_IN_OPERATION   ;
-  delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
-  delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-  delete     in_MEMORY_IN_HAS_IMMEDIAT;
-  delete     in_MEMORY_IN_IMMEDIAT    ;
-  delete     in_MEMORY_IN_DATA_RA     ;
-  delete     in_MEMORY_IN_DATA_RB     ;
-  delete     in_MEMORY_IN_DATA_RC     ;
-  delete     in_MEMORY_IN_WRITE_RD    ;
-  delete     in_MEMORY_IN_NUM_REG_RD  ;
-  delete     in_MEMORY_IN_WRITE_RE    ;
-  delete     in_MEMORY_IN_NUM_REG_RE  ;
-    
-  delete    out_MEMORY_OUT_VAL       ;
-  delete     in_MEMORY_OUT_ACK       ;
-  delete    out_MEMORY_OUT_CONTEXT_ID;
-  delete    out_MEMORY_OUT_FRONT_END_ID;
-  delete    out_MEMORY_OUT_OOO_ENGINE_ID;
-  delete    out_MEMORY_OUT_PACKET_ID ;
-//   delete    out_MEMORY_OUT_OPERATION ;
-  delete    out_MEMORY_OUT_TYPE      ;
-  delete    out_MEMORY_OUT_WRITE_RD  ;
-  delete    out_MEMORY_OUT_NUM_REG_RD;
-  delete    out_MEMORY_OUT_DATA_RD   ;
-  delete    out_MEMORY_OUT_WRITE_RE  ;
-  delete    out_MEMORY_OUT_NUM_REG_RE;
-  delete    out_MEMORY_OUT_DATA_RE   ;
-  delete    out_MEMORY_OUT_EXCEPTION ;
-  delete    out_MEMORY_OUT_NO_SEQUENCE;
-  delete    out_MEMORY_OUT_ADDRESS   ;
-  
-  delete    out_DCACHE_REQ_VAL       ;
-  delete     in_DCACHE_REQ_ACK       ;
-  delete    out_DCACHE_REQ_CONTEXT_ID;
-  delete    out_DCACHE_REQ_PACKET_ID ;
-  delete    out_DCACHE_REQ_ADDRESS   ;
-  delete    out_DCACHE_REQ_TYPE      ;
-  delete    out_DCACHE_REQ_WDATA     ;
-  
-  delete     in_DCACHE_RSP_VAL       ;
-  delete    out_DCACHE_RSP_ACK       ;
-  delete     in_DCACHE_RSP_CONTEXT_ID;
-  delete     in_DCACHE_RSP_PACKET_ID ;
-  delete     in_DCACHE_RSP_RDATA     ;
-  delete     in_DCACHE_RSP_ERROR     ;
-  
-    {
-      delete [] out_BYPASS_MEMORY_VAL       ;
-      delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
-      delete [] out_BYPASS_MEMORY_NUM_REG   ;
-      delete [] out_BYPASS_MEMORY_DATA      ;
-    }
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_VAL                  ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_IN_ACK                  ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID           ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID         ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID        ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID            ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_OPERATION            ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_TYPE                 ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT         ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT             ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RA              ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RB              ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RC              ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD             ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD           ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE             ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE           ,_param->_nb_inst_memory);
+
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_VAL          ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL( in_MEMORY_OUT_ACK          ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID   ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID    ,_param->_nb_inst_memory);
+//DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION    ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE         ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD     ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD   ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD      ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE     ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE   ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE      ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION    ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE  ,_param->_nb_inst_memory);
+  DELETE1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS      ,_param->_nb_inst_memory);
+
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL        ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK        ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID  ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS    ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE       ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA      ,_param->_nb_cache_port);
+
+  DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL        ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK        ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID  ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA      ,_param->_nb_cache_port);
+  DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR      ,_param->_nb_cache_port);
+
+  DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_VAL           ,_param->_nb_bypass_memory);
+  DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory);
+  DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG       ,_param->_nb_bypass_memory);
+  DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_DATA          ,_param->_nb_bypass_memory);
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h	(revision 88)
@@ -90,66 +90,65 @@
 
     // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_VAL         ;
-  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_IN_ACK         ;
-  public    : SC_IN (Tcontext_t        )    *  in_MEMORY_IN_CONTEXT_ID  ;
-  public    : SC_IN (Tcontext_t        )    *  in_MEMORY_IN_FRONT_END_ID;
-  public    : SC_IN (Tcontext_t        )    *  in_MEMORY_IN_OOO_ENGINE_ID;
-  public    : SC_IN (Tpacket_t         )    *  in_MEMORY_IN_PACKET_ID   ;
-  public    : SC_IN (Toperation_t      )    *  in_MEMORY_IN_OPERATION   ;
-  public    : SC_IN (Ttype_t           )    *  in_MEMORY_IN_TYPE        ;
-  public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
-  public    : SC_IN (Tlsq_ptr_t        )    *  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_HAS_IMMEDIAT;
-  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_IMMEDIAT    ; // memory address
-  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RA     ; // memory address
-  public    : SC_IN (Tgeneral_data_t   )    *  in_MEMORY_IN_DATA_RB     ; // data        (store)
-  public    : SC_IN (Tspecial_data_t   )    *  in_MEMORY_IN_DATA_RC     ;
-  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RD    ; // = (operation==load)
-  public    : SC_IN (Tgeneral_address_t)    *  in_MEMORY_IN_NUM_REG_RD  ; // destination (load)
-  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_IN_WRITE_RE    ;
-  public    : SC_IN (Tspecial_address_t)    *  in_MEMORY_IN_NUM_REG_RE  ;
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_VAL                  ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontrol_t        )   ** out_MEMORY_IN_ACK                  ;//[nb_inst_memory]
+  public    : SC_IN (Tcontext_t        )   **  in_MEMORY_IN_CONTEXT_ID           ;//[nb_inst_memory]
+  public    : SC_IN (Tcontext_t        )   **  in_MEMORY_IN_FRONT_END_ID         ;//[nb_inst_memory]
+  public    : SC_IN (Tcontext_t        )   **  in_MEMORY_IN_OOO_ENGINE_ID        ;//[nb_inst_memory]
+  public    : SC_IN (Tpacket_t         )   **  in_MEMORY_IN_PACKET_ID            ;//[nb_inst_memory]
+  public    : SC_IN (Toperation_t      )   **  in_MEMORY_IN_OPERATION            ;//[nb_inst_memory]
+  public    : SC_IN (Ttype_t           )   **  in_MEMORY_IN_TYPE                 ;//[nb_inst_memory]
+  public    : SC_IN (Tlsq_ptr_t        )   **  in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory]
+  public    : SC_IN (Tlsq_ptr_t        )   **  in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory]
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_HAS_IMMEDIAT         ;//[nb_inst_memory]
+  public    : SC_IN (Tgeneral_data_t   )   **  in_MEMORY_IN_IMMEDIAT             ;//[nb_inst_memory] // memory address
+  public    : SC_IN (Tgeneral_data_t   )   **  in_MEMORY_IN_DATA_RA              ;//[nb_inst_memory] // memory address
+  public    : SC_IN (Tgeneral_data_t   )   **  in_MEMORY_IN_DATA_RB              ;//[nb_inst_memory] // data        (store)
+  public    : SC_IN (Tspecial_data_t   )   **  in_MEMORY_IN_DATA_RC              ;//[nb_inst_memory]
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_WRITE_RD             ;//[nb_inst_memory] // = (operation==load)
+  public    : SC_IN (Tgeneral_address_t)   **  in_MEMORY_IN_NUM_REG_RD           ;//[nb_inst_memory] // destination (load)
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_IN_WRITE_RE             ;//[nb_inst_memory]
+  public    : SC_IN (Tspecial_address_t)   **  in_MEMORY_IN_NUM_REG_RE           ;//[nb_inst_memory]
 
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_VAL       ;
-  public    : SC_IN (Tcontrol_t        )    *  in_MEMORY_OUT_ACK       ;
-  public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_CONTEXT_ID;
-  public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_FRONT_END_ID;
-  public    : SC_OUT(Tcontext_t        )    * out_MEMORY_OUT_OOO_ENGINE_ID;
-  public    : SC_OUT(Tpacket_t         )    * out_MEMORY_OUT_PACKET_ID ;
-//public    : SC_OUT(Toperation_t      )    * out_MEMORY_OUT_OPERATION ;
-  public    : SC_OUT(Ttype_t           )    * out_MEMORY_OUT_TYPE      ;
-  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RD  ; // = (operation==load)
-  public    : SC_OUT(Tgeneral_address_t)    * out_MEMORY_OUT_NUM_REG_RD; // destination (load)
-  public    : SC_OUT(Tgeneral_data_t   )    * out_MEMORY_OUT_DATA_RD   ; // data        (load)
-  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_WRITE_RE  ;
-  public    : SC_OUT(Tspecial_address_t)    * out_MEMORY_OUT_NUM_REG_RE;
-  public    : SC_OUT(Tspecial_data_t   )    * out_MEMORY_OUT_DATA_RE   ;
-  public    : SC_OUT(Texception_t      )    * out_MEMORY_OUT_EXCEPTION ;
-  public    : SC_OUT(Tcontrol_t        )    * out_MEMORY_OUT_NO_SEQUENCE;
-  public    : SC_OUT(Tgeneral_data_t   )    * out_MEMORY_OUT_ADDRESS   ;
+  public    : SC_OUT(Tcontrol_t        )   ** out_MEMORY_OUT_VAL                 ;//[nb_inst_memory]
+  public    : SC_IN (Tcontrol_t        )   **  in_MEMORY_OUT_ACK                 ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontext_t        )   ** out_MEMORY_OUT_CONTEXT_ID          ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontext_t        )   ** out_MEMORY_OUT_FRONT_END_ID        ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontext_t        )   ** out_MEMORY_OUT_OOO_ENGINE_ID       ;//[nb_inst_memory]
+  public    : SC_OUT(Tpacket_t         )   ** out_MEMORY_OUT_PACKET_ID           ;//[nb_inst_memory]
+//public    : SC_OUT(Toperation_t      )   ** out_MEMORY_OUT_OPERATION           ;//[nb_inst_memory]
+  public    : SC_OUT(Ttype_t           )   ** out_MEMORY_OUT_TYPE                ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontrol_t        )   ** out_MEMORY_OUT_WRITE_RD            ;//[nb_inst_memory] // = (operation==load)
+  public    : SC_OUT(Tgeneral_address_t)   ** out_MEMORY_OUT_NUM_REG_RD          ;//[nb_inst_memory] // destination (load)
+  public    : SC_OUT(Tgeneral_data_t   )   ** out_MEMORY_OUT_DATA_RD             ;//[nb_inst_memory] // data        (load)
+  public    : SC_OUT(Tcontrol_t        )   ** out_MEMORY_OUT_WRITE_RE            ;//[nb_inst_memory]
+  public    : SC_OUT(Tspecial_address_t)   ** out_MEMORY_OUT_NUM_REG_RE          ;//[nb_inst_memory]
+  public    : SC_OUT(Tspecial_data_t   )   ** out_MEMORY_OUT_DATA_RE             ;//[nb_inst_memory]
+  public    : SC_OUT(Texception_t      )   ** out_MEMORY_OUT_EXCEPTION           ;//[nb_inst_memory]
+  public    : SC_OUT(Tcontrol_t        )   ** out_MEMORY_OUT_NO_SEQUENCE         ;//[nb_inst_memory]
+  public    : SC_OUT(Tgeneral_data_t   )   ** out_MEMORY_OUT_ADDRESS             ;//[nb_inst_memory]
     
-
     // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_REQ_VAL       ;
-  public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_REQ_ACK       ;
-  public    : SC_OUT(Tcontext_t        )    * out_DCACHE_REQ_CONTEXT_ID;
-  public    : SC_OUT(Tpacket_t         )    * out_DCACHE_REQ_PACKET_ID ;
-  public    : SC_OUT(Tdcache_address_t )    * out_DCACHE_REQ_ADDRESS   ;
-  public    : SC_OUT(Tdcache_type_t    )    * out_DCACHE_REQ_TYPE      ;
-  public    : SC_OUT(Tdcache_data_t    )    * out_DCACHE_REQ_WDATA     ;
+  public    : SC_OUT(Tcontrol_t        )   ** out_DCACHE_REQ_VAL                 ;//[nb_cache_port]
+  public    : SC_IN (Tcontrol_t        )   **  in_DCACHE_REQ_ACK                 ;//[nb_cache_port]
+  public    : SC_OUT(Tcontext_t        )   ** out_DCACHE_REQ_CONTEXT_ID          ;//[nb_cache_port]
+  public    : SC_OUT(Tpacket_t         )   ** out_DCACHE_REQ_PACKET_ID           ;//[nb_cache_port]
+  public    : SC_OUT(Tdcache_address_t )   ** out_DCACHE_REQ_ADDRESS             ;//[nb_cache_port]
+  public    : SC_OUT(Tdcache_type_t    )   ** out_DCACHE_REQ_TYPE                ;//[nb_cache_port]
+  public    : SC_OUT(Tdcache_data_t    )   ** out_DCACHE_REQ_WDATA               ;//[nb_cache_port]
 
     // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tcontrol_t        )    *  in_DCACHE_RSP_VAL       ;
-  public    : SC_OUT(Tcontrol_t        )    * out_DCACHE_RSP_ACK       ;
-  public    : SC_IN (Tcontext_t        )    *  in_DCACHE_RSP_CONTEXT_ID;
-  public    : SC_IN (Tpacket_t         )    *  in_DCACHE_RSP_PACKET_ID ;
-  public    : SC_IN (Tdcache_data_t    )    *  in_DCACHE_RSP_RDATA     ;
-  public    : SC_IN (Tdcache_error_t   )    *  in_DCACHE_RSP_ERROR     ;
+  public    : SC_IN (Tcontrol_t        )   **  in_DCACHE_RSP_VAL                 ;//[nb_cache_port]
+  public    : SC_OUT(Tcontrol_t        )   ** out_DCACHE_RSP_ACK                 ;//[nb_cache_port]
+  public    : SC_IN (Tcontext_t        )   **  in_DCACHE_RSP_CONTEXT_ID          ;//[nb_cache_port]
+  public    : SC_IN (Tpacket_t         )   **  in_DCACHE_RSP_PACKET_ID           ;//[nb_cache_port]
+  public    : SC_IN (Tdcache_data_t    )   **  in_DCACHE_RSP_RDATA               ;//[nb_cache_port]
+  public    : SC_IN (Tdcache_error_t   )   **  in_DCACHE_RSP_ERROR               ;//[nb_cache_port]
 
     // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_OUT(Tcontrol_t        )   ** out_BYPASS_MEMORY_VAL       ;
-  public    : SC_OUT(Tcontext_t        )   ** out_BYPASS_MEMORY_OOO_ENGINE_ID;
-  public    : SC_OUT(Tgeneral_address_t)   ** out_BYPASS_MEMORY_NUM_REG   ;
-  public    : SC_OUT(Tgeneral_data_t   )   ** out_BYPASS_MEMORY_DATA      ;
+  public    : SC_OUT(Tcontrol_t        )   ** out_BYPASS_MEMORY_VAL          ; //[nb_bypass_memory]
+  public    : SC_OUT(Tcontext_t        )   ** out_BYPASS_MEMORY_OOO_ENGINE_ID; //[nb_bypass_memory]
+  public    : SC_OUT(Tgeneral_address_t)   ** out_BYPASS_MEMORY_NUM_REG      ; //[nb_bypass_memory]
+  public    : SC_OUT(Tgeneral_data_t   )   ** out_BYPASS_MEMORY_DATA         ; //[nb_bypass_memory]
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
@@ -177,12 +176,14 @@
     // signal
   public    : Tlsq_ptr_t                      internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ;
-
-  private   : Tcontrol_t                      internal_MEMORY_IN_ACK;
-  private   : Tcontrol_t                      internal_MEMORY_OUT_VAL;
+					     
+  private   : Tcontrol_t                      internal_MEMORY_IN_ACK          ;
+  private   : uint32_t                        internal_MEMORY_IN_PORT         ;
+
+  private   : Tcontrol_t                      internal_MEMORY_OUT_VAL         ;
   private   : Tselect_queue_t                 internal_MEMORY_OUT_SELECT_QUEUE;
-  public    : Tlsq_ptr_t                      internal_MEMORY_OUT_PTR;
-
-  private   : Tcontrol_t                      internal_DCACHE_RSP_ACK;
-  private   : Tcontrol_t                      internal_DCACHE_REQ_VAL;
+  private   : Tlsq_ptr_t                      internal_MEMORY_OUT_PTR         ;
+					     
+  private   : Tcontrol_t                      internal_DCACHE_RSP_ACK         ;
+  private   : Tcontrol_t                      internal_DCACHE_REQ_VAL         ;
   private   : Tselect_queue_t                 internal_DCACHE_REQ_SELECT_QUEUE;
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h	(revision 88)
@@ -27,41 +27,42 @@
   {
     //-----[ fields ]------------------------------------------------------------
-  public : const uint32_t            _size_store_queue             ;
-  public : const uint32_t            _size_load_queue              ;
-  public : const uint32_t            _size_speculative_access_queue;
-  public : const uint32_t            _nb_port_check                ;
-  public : const Tspeculative_load_t _speculative_load             ;
-  public : const uint32_t            _nb_bypass_memory             ;
-//public : const uint32_t            _nb_cache_port                ;
-  public : const uint32_t            _nb_context                   ;
-  public : const uint32_t            _nb_front_end                 ;
-  public : const uint32_t            _nb_ooo_engine                ;
-  public : const uint32_t            _nb_packet                    ;
-  public : const uint32_t            _size_general_data            ;
-  public : const uint32_t            _size_special_data            ;
-  public : const uint32_t            _nb_general_register          ;
-  public : const uint32_t            _nb_special_register          ;
+  public : uint32_t            _size_store_queue             ;
+  public : uint32_t            _size_load_queue              ;
+  public : uint32_t            _size_speculative_access_queue;
+  public : uint32_t            _nb_port_check                ;
+  public : Tspeculative_load_t _speculative_load             ;
+  public : uint32_t            _nb_bypass_memory             ;
+  public : uint32_t            _nb_cache_port                ;
+  public : uint32_t            _nb_inst_memory               ;
+  public : uint32_t            _nb_context                   ;
+  public : uint32_t            _nb_front_end                 ;
+  public : uint32_t            _nb_ooo_engine                ;
+  public : uint32_t            _nb_packet                    ;
+//public : uint32_t            _size_general_data            ;
+//public : uint32_t            _size_special_data            ;
+  public : uint32_t            _nb_general_register          ;
+  public : uint32_t            _nb_special_register          ;
 
-  public : const uint32_t            _size_address_store_queue             ;
-  public : const uint32_t            _size_address_load_queue              ;
-  public : const uint32_t            _size_address_speculative_access_queue;
-  public : const uint32_t            _size_context_id                      ;
-  public : const uint32_t            _size_front_end_id                    ;
-  public : const uint32_t            _size_ooo_engine_id                   ;
-  public : const uint32_t            _size_packet_id                       ;
-  public : const uint32_t            _size_general_register                ;
-  public : const uint32_t            _size_special_register                ;
-  public : const uint32_t            _size_dcache_context_id               ;
-  public : const uint32_t            _size_dcache_packet_id                ;
+//public : uint32_t            _size_address_store_queue             ;
+//public : uint32_t            _size_address_load_queue              ;
+  public : uint32_t            _size_speculative_access_queue_ptr    ;
+//public : uint32_t            _size_context_id                      ;
+//public : uint32_t            _size_front_end_id                    ;
+//public : uint32_t            _size_ooo_engine_id                   ;
+//public : uint32_t            _size_packet_id                       ;
+//public : uint32_t            _size_general_register                ;
+//public : uint32_t            _size_special_register                ;
+  public : uint32_t            _size_dcache_context_id               ;
+  public : uint32_t            _size_dcache_packet_id                ;
 
-  public : const bool                _have_port_context_id                 ;
-  public : const bool                _have_port_front_end_id               ;
-  public : const bool                _have_port_ooo_engine_id              ;
-  public : const bool                _have_port_packet_id                  ;
-  public : const bool                _have_port_dcache_context_id          ;
-  public : const bool                _have_port_load_queue_ptr             ;
+//public : bool                _have_port_context_id                 ;
+//public : bool                _have_port_front_end_id               ;
+//public : bool                _have_port_ooo_engine_id              ;
+//public : bool                _have_port_packet_id                  ;
+  public : bool                _have_port_dcache_context_id          ;
+//public : bool                _have_port_load_queue_ptr             ;
 
-  public : const Tdcache_address_t   _mask_address_lsb                     ;
-  public : const Tdcache_address_t   _mask_address_msb                     ;
+  public : Tdcache_address_t   _mask_address_lsb                     ;
+  public : Tdcache_address_t   _mask_address_msb                     ;
 
     //-----[ methods ]-----------------------------------------------------------
@@ -72,4 +73,6 @@
 			Tspeculative_load_t speculative_load       ,
 			uint32_t            nb_bypass_memory       ,
+			uint32_t            nb_cache_port          ,
+			uint32_t            nb_inst_memory         ,
 			uint32_t            nb_context             ,
 			uint32_t            nb_front_end           ,
@@ -79,8 +82,12 @@
 			uint32_t            size_special_data      ,
 			uint32_t            nb_general_register    ,
-			uint32_t            nb_special_register    );
+			uint32_t            nb_special_register    ,
+                        bool                is_toplevel=false);
 
-  public : Parameters  (Parameters & param) ;
+//   public : Parameters  (Parameters & param) ;
+
   public : ~Parameters () ;
+
+  public : void            copy      (void);
 
   public : Parameters_test msg_error (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp	(revision 88)
@@ -39,4 +39,10 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
+#if DEBUG_Load_store_unit == true
+    log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+    std::cout << *param << std::endl;
+#endif    
+
 #ifdef SYSTEMC
     log_printf(INFO,Load_store_unit,FUNCTION,"Allocation");
@@ -46,17 +52,25 @@
 
 #ifdef STATISTICS
-    log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics");
-
-    statistics_declaration(param_statistics);
+    if (usage_is_set(_usage,USE_STATISTICS))
+      {	
+        log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics");
+        
+        statistics_declaration(param_statistics);
+      }
 #endif
 
 #ifdef VHDL
-    // generate the vhdl
-    log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl");
-
-    vhdl();
-#endif
-
-#ifdef SYSTEMC
+    if (usage_is_set(_usage,USE_VHDL))
+      {	
+        // generate the vhdl
+        log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl");
+        
+        vhdl();
+      }
+#endif
+
+#ifdef SYSTEMC
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {	
     // Function pointer
 
@@ -84,5 +98,15 @@
 
     internal_DCACHE_RSP_ACK = 1;
-    PORT_WRITE(out_DCACHE_RSP_ACK, 1);
+    PORT_WRITE(out_DCACHE_RSP_ACK [0], internal_DCACHE_RSP_ACK);
+    for (uint32_t i=1; i<_param->_nb_cache_port; ++i)
+      {
+	PORT_WRITE(out_DCACHE_RSP_ACK [i], 0);
+	PORT_WRITE(out_DCACHE_REQ_VAL [i], 0);
+      }
+
+    for (uint32_t i=1; i<_param->_nb_inst_memory; i++)
+      {
+	PORT_WRITE(out_MEMORY_OUT_VAL [i], 0);
+      }
 
     log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition");
@@ -111,9 +135,16 @@
     dont_initialize ();
     sensitive_neg << *(in_CLOCK);
-    sensitive     << *(in_MEMORY_IN_OPERATION);
-
-#ifdef SYSTEMCASS_SPECIFIC
-    // List dependency information
-    (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION));
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      sensitive << (*(in_MEMORY_IN_VAL       [i]))
+		<< (*(in_MEMORY_IN_OPERATION [i]));
+
+#ifdef SYSTEMCASS_SPECIFIC
+    // List dependency information
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+//       for (uint32_t x=0; x<_param->_nb_inst_memory; x++)
+	{
+	  (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_VAL       [i]));
+	  (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_OPERATION [i]));
+	}
 #endif    
 
@@ -137,5 +168,5 @@
     // List dependency information
 #endif    
-
+      }
 #endif
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
@@ -149,7 +180,10 @@
 
 #ifdef STATISTICS
-    log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file");
-
-    delete _stat;
+    if (usage_is_set(_usage,USE_STATISTICS))
+      {	
+        log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file");
+        
+        delete _stat;
+      }
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp	(revision 88)
@@ -3,9 +3,10 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -37,5 +38,5 @@
     _interfaces = entity->set_interfaces();
 
-    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
       Interface * interface = _interfaces->set_interface(""
@@ -43,5 +44,5 @@
 							 ,IN
 							 ,SOUTH,
-							 "Generalist interface"
+							 _("Generalist interface")
 #endif
 							 );
@@ -50,142 +51,106 @@
       in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
     }
-    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("memory_in"
-#ifdef POSITION
-							      ,IN
-							      ,WEST
-							      ,"Instruction from Reservations station"
-#endif
-							      );
+      ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory);
 
-   in_MEMORY_IN_VAL                   = interface->set_signal_valack_in        (VAL);
-  out_MEMORY_IN_ACK                   = interface->set_signal_valack_out       (ACK);
-
-  if (_param->_have_port_context_id)
-   in_MEMORY_IN_CONTEXT_ID            = interface->set_signal_in  <Tcontext_t        > ("context_id"   ,_param->_size_context_id       );
-  if (_param->_have_port_front_end_id)
-   in_MEMORY_IN_FRONT_END_ID          = interface->set_signal_in  <Tcontext_t        > ("front_end_id" ,_param->_size_front_end_id     );
-  if (_param->_have_port_ooo_engine_id)
-   in_MEMORY_IN_OOO_ENGINE_ID         = interface->set_signal_in  <Tcontext_t        > ("ooo_engine_id",_param->_size_ooo_engine_id    );
-  if (_param->_have_port_packet_id)
-   in_MEMORY_IN_PACKET_ID             = interface->set_signal_in  <Tpacket_t         > ("packet_id"    ,_param->_size_packet_id       );
-   in_MEMORY_IN_OPERATION             = interface->set_signal_in  <Toperation_t      > ("operation"   ,_param->_size_operation        );
-   in_MEMORY_IN_TYPE                  = interface->set_signal_in  <Ttype_t           > ("type"        ,_param->_size_type             );
-   in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in  <Tlsq_ptr_t        > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage
-   if (_param->_have_port_load_queue_ptr)
-   in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE  = interface->set_signal_in  <Tlsq_ptr_t        > ("load_queue_ptr_write"  ,_param->_size_address_load_queue );
-   in_MEMORY_IN_HAS_IMMEDIAT          = interface->set_signal_in  <Tcontrol_t        > ("has_immediat",1                              );
-   in_MEMORY_IN_IMMEDIAT              = interface->set_signal_in  <Tgeneral_data_t   > ("immediat"    ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RA               = interface->set_signal_in  <Tgeneral_data_t   > ("data_ra"     ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RB               = interface->set_signal_in  <Tgeneral_data_t   > ("data_rb"     ,_param->_size_general_data     );
-   in_MEMORY_IN_DATA_RC               = interface->set_signal_in  <Tspecial_data_t   > ("data_rc"     ,_param->_size_special_data     );
-   in_MEMORY_IN_WRITE_RD              = interface->set_signal_in  <Tcontrol_t        > ("write_rd"    ,1                              );
-   in_MEMORY_IN_NUM_REG_RD            = interface->set_signal_in  <Tgeneral_address_t> ("num_reg_rd"  ,1                              );
-   in_MEMORY_IN_WRITE_RE              = interface->set_signal_in  <Tcontrol_t        > ("write_re"    ,1                              );
-   in_MEMORY_IN_NUM_REG_RE            = interface->set_signal_in  <Tspecial_address_t> ("num_reg_re"  ,1                              );
+      ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL                  ,VAL);
+      ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK                  ,ACK);
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id           );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID        ,"ooo_engine_id"        ,Tcontext_t        ,_param->_size_ooo_engine_id        );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID            ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr              );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation            );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                 );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr      );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr       );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA              ,"data_ra"              ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB              ,"data_rb"              ,Tgeneral_data_t   ,_param->_size_general_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC              ,"data_rc"              ,Tspecial_data_t   ,_param->_size_special_data         );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD           ,"num_reg_rd"           ,Tgeneral_address_t,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                  );
+      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE           ,"num_reg_re"           ,Tspecial_address_t,1                                  );
     }
 
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("memory_out"
-#ifdef POSITION
-							      ,OUT
-							      ,EAST
-							      ,"Instruction to write queue"
-#endif
-							      );
+      ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory);
 
-      out_MEMORY_OUT_VAL           = interface->set_signal_valack_out(VAL);
-       in_MEMORY_OUT_ACK           = interface->set_signal_valack_in (ACK);
-      if (_param->_have_port_context_id)       
-      out_MEMORY_OUT_CONTEXT_ID    = interface->set_signal_out <Tcontext_t        > ("context_id"    ,_param->_size_context_id       );
-      if (_param->_have_port_front_end_id)     
-      out_MEMORY_OUT_FRONT_END_ID  = interface->set_signal_out <Tcontext_t        > ("front_end_id"  ,_param->_size_front_end_id     );
-      if (_param->_have_port_ooo_engine_id)    
-      out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t        > ("ooo_engine_id" ,_param->_size_ooo_engine_id    );
-      if (_param->_have_port_packet_id)       
-      out_MEMORY_OUT_PACKET_ID     = interface->set_signal_out <Tpacket_t         > ("packet_id"     ,_param->_size_packet_id        );
-//    out_MEMORY_OUT_OPERATION     = interface->set_signal_out <Toperation_t      > ("operation"     ,_param->_size_operation        );
-      out_MEMORY_OUT_TYPE          = interface->set_signal_out <Ttype_t           > ("type"          ,_param->_size_type             );
-      out_MEMORY_OUT_WRITE_RD      = interface->set_signal_out <Tcontrol_t        > ("write_rd"      ,1                              );
-      out_MEMORY_OUT_NUM_REG_RD    = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd"    ,_param->_size_general_register );
-      out_MEMORY_OUT_DATA_RD       = interface->set_signal_out <Tgeneral_data_t   > ("data_rd"       ,_param->_size_general_data     );
-      out_MEMORY_OUT_WRITE_RE      = interface->set_signal_out <Tcontrol_t        > ("write_re"      ,1                              );
-      out_MEMORY_OUT_NUM_REG_RE    = interface->set_signal_out <Tspecial_address_t> ("num_reg_re"    ,_param->_size_general_register );
-      out_MEMORY_OUT_DATA_RE       = interface->set_signal_out <Tspecial_data_t   > ("data_re"       ,_param->_size_general_data     );
-      out_MEMORY_OUT_EXCEPTION     = interface->set_signal_out <Texception_t      > ("exception"     ,_param->_size_exception        );
-      out_MEMORY_OUT_NO_SEQUENCE   = interface->set_signal_out <Tcontrol_t        > ("no_sequence"   ,1                              );
-      out_MEMORY_OUT_ADDRESS       = interface->set_signal_out <Tgeneral_data_t   > ("address"       ,_param->_size_general_data     );
+      ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL          ,VAL);
+      ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK          ,ACK);
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID   ,"context_id"    ,Tcontext_t        ,_param->_size_context_id       );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id"  ,Tcontext_t        ,_param->_size_front_end_id     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t        ,_param->_size_ooo_engine_id    );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID    ,"packet_id"     ,Tpacket_t         ,_param->_size_rob_ptr          );
+//    ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION    ,"operation"     ,Toperation_t      ,_param->_size_operation        );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE         ,"type"          ,Ttype_t           ,_param->_size_type             );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD     ,"write_rd"      ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD   ,"num_reg_rd"    ,Tgeneral_address_t,_param->_size_general_register );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD      ,"data_rd"       ,Tgeneral_data_t   ,_param->_size_general_data     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE     ,"write_re"      ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE   ,"num_reg_re"    ,Tspecial_address_t,_param->_size_general_register );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE      ,"data_re"       ,Tspecial_data_t   ,_param->_size_general_data     );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION    ,"exception"     ,Texception_t      ,_param->_size_exception        );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE  ,"no_sequence"   ,Tcontrol_t        ,1                              );
+      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS      ,"address"       ,Tgeneral_data_t   ,_param->_size_general_data     );
     }
 
-    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("dcache_req"
-#ifdef POSITION
-							      ,OUT
-							      ,NORTH
-							      ,"Request port to dcache"
-#endif
-							      );
+      ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port);
 
-      out_DCACHE_REQ_VAL        = interface->set_signal_valack_out(VAL);
-       in_DCACHE_REQ_ACK        = interface->set_signal_valack_in (ACK);
-       if (_param->_have_port_dcache_context_id)
-      out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t        > ("context_id",_param->_size_dcache_context_id  );
-      out_DCACHE_REQ_PACKET_ID  = interface->set_signal_out <Tpacket_t         > ("packet_id" ,_param->_size_dcache_packet_id   );
-      out_DCACHE_REQ_ADDRESS    = interface->set_signal_out <Tdcache_address_t > ("address"   ,_param->_size_general_data);
-      out_DCACHE_REQ_TYPE       = interface->set_signal_out <Tdcache_type_t    > ("type"      ,_param->_size_dcache_type );
-      out_DCACHE_REQ_WDATA      = interface->set_signal_out <Tdcache_data_t    > ("wdata"     ,_param->_size_general_data);
+      ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL        ,VAL);
+      ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK        ,ACK);
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t       ,_param->_size_dcache_context_id  );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID  ,"packet_id" ,Tpacket_t        ,_param->_size_dcache_packet_id   );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS    ,"address"   ,Tdcache_address_t,_param->_size_general_data);
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE       ,"type"      ,Tdcache_type_t   ,_param->_size_dcache_type );
+      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA      ,"wdata"     ,Tdcache_data_t   ,_param->_size_general_data);
     }
-    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      Interface_fifo * interface = _interfaces->set_interface("dcache_rsp"
-#ifdef POSITION
-							      ,IN
-							      ,NORTH
-							      ,"Respons port from dcache"
-#endif
-							      );
+      ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port);
 
-       in_DCACHE_RSP_VAL        = interface->set_signal_valack_in (VAL);
-      out_DCACHE_RSP_ACK        = interface->set_signal_valack_out(ACK);
-       if (_param->_have_port_dcache_context_id)
-       in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in  <Tcontext_t     > ("context_id",_param->_size_dcache_context_id  );
-       in_DCACHE_RSP_PACKET_ID  = interface->set_signal_in  <Tpacket_t      > ("packet_id" ,_param->_size_dcache_packet_id   );
-       in_DCACHE_RSP_RDATA      = interface->set_signal_in  <Tdcache_data_t > ("rdata"     ,_param->_size_general_data);
-       in_DCACHE_RSP_ERROR      = interface->set_signal_in  <Tdcache_error_t> ("error"     ,_param->_size_dcache_error);
+      ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL        ,VAL);
+      ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK        ,ACK);
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t     ,_param->_size_dcache_context_id  );
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID  ,"packet_id" ,Tpacket_t      ,_param->_size_dcache_packet_id   );
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA      ,"rdata"     ,Tdcache_data_t ,_param->_size_general_data);
+      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR      ,"error"     ,Tdcache_error_t,_param->_size_dcache_error);
     }
-    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-//  if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
-      {
-	out_BYPASS_MEMORY_VAL          = new SC_OUT(Tcontrol_t        ) * [_param->_nb_bypass_memory];
-	if (_param->_have_port_ooo_engine_id)    
-	out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t        ) * [_param->_nb_bypass_memory];
-	out_BYPASS_MEMORY_NUM_REG      = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory];
-	out_BYPASS_MEMORY_DATA         = new SC_OUT(Tgeneral_data_t   ) * [_param->_nb_bypass_memory];
-	
-	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
-	  {
-	    Interface_fifo * interface = _interfaces->set_interface("memory_out"
-#ifdef POSITION
-								    ,OUT
-								    ,NORTH
-								    ,"Bypass between the load queue and the reservation station"
-#endif
-								    );
+    {
+      ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory);
 	    
-	    out_BYPASS_MEMORY_VAL           [i] = interface->set_signal_valack_out(VAL);
-	    if (_param->_have_port_ooo_engine_id)
-	    out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t        > ("ooo_engine_id", _param->_size_ooo_engine_id);
-	    out_BYPASS_MEMORY_NUM_REG       [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg"      , _param->_size_general_register);
-	    out_BYPASS_MEMORY_DATA          [i] = interface->set_signal_out <Tgeneral_data_t   > ("data"         , _param->_size_general_data);
-	  }
-      }
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+      ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL           ,VAL);
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t        , _param->_size_ooo_engine_id   );
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG       ,"num_reg"      ,Tgeneral_address_t, _param->_size_general_register);
+      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA          ,"data"         ,Tgeneral_data_t   , _param->_size_general_data    );
+    }
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+//     internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port];
+
+//     internal_MEMORY_IN_ACK           = new Tcontrol_t      [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_VAL          = new Tcontrol_t      [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory];
+//     internal_MEMORY_OUT_PTR          = new Tlsq_ptr_t      [_param->_nb_inst_memory];
+    
+//     internal_DCACHE_RSP_ACK          = new Tcontrol_t      [_param->_nb_cache_port];
+//     internal_DCACHE_REQ_VAL          = new Tcontrol_t      [_param->_nb_cache_port];
+//     internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port];
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
 #ifdef POSITION
-    _component->generate_file();
+    if (usage_is_set(_usage,USE_POSITION))
+      _component->generate_file();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp	(revision 88)
@@ -6,9 +6,10 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -28,4 +29,6 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
 //#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     delete    in_CLOCK ;
@@ -33,74 +36,77 @@
     delete    in_NRESET;
 
-    delete     in_MEMORY_IN_VAL         ;
-    delete    out_MEMORY_IN_ACK         ;
-    if (_param->_have_port_context_id)
-    delete     in_MEMORY_IN_CONTEXT_ID  ;
-    if (_param->_have_port_front_end_id)
-    delete     in_MEMORY_IN_FRONT_END_ID  ;
-    if (_param->_have_port_ooo_engine_id)
-    delete     in_MEMORY_IN_OOO_ENGINE_ID  ;
-    if (_param->_have_port_packet_id)
-    delete     in_MEMORY_IN_PACKET_ID   ;
-    delete     in_MEMORY_IN_OPERATION   ;
-    delete     in_MEMORY_IN_TYPE        ;
-    delete     in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
-    if (_param->_have_port_load_queue_ptr)
-    delete     in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
-    delete     in_MEMORY_IN_HAS_IMMEDIAT;
-    delete     in_MEMORY_IN_IMMEDIAT    ;
-    delete     in_MEMORY_IN_DATA_RA     ;
-    delete     in_MEMORY_IN_DATA_RB     ;
-    delete     in_MEMORY_IN_DATA_RC     ;
-    delete     in_MEMORY_IN_WRITE_RD    ;
-    delete     in_MEMORY_IN_NUM_REG_RD  ;
-    delete     in_MEMORY_IN_WRITE_RE    ;
-    delete     in_MEMORY_IN_NUM_REG_RE  ;
+    DELETE1_SIGNAL( in_MEMORY_IN_VAL                  ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL(out_MEMORY_IN_ACK                  ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL( in_MEMORY_IN_CONTEXT_ID           ,_param->_nb_inst_memory,_param->_size_context_id           );
+    DELETE1_SIGNAL( in_MEMORY_IN_FRONT_END_ID         ,_param->_nb_inst_memory,_param->_size_front_end_id         );
+    DELETE1_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID        ,_param->_nb_inst_memory,_param->_size_ooo_engine_id        );
+    DELETE1_SIGNAL( in_MEMORY_IN_PACKET_ID            ,_param->_nb_inst_memory,_param->_size_rob_ptr              );
+    DELETE1_SIGNAL( in_MEMORY_IN_OPERATION            ,_param->_nb_inst_memory,_param->_size_operation            );
+    DELETE1_SIGNAL( in_MEMORY_IN_TYPE                 ,_param->_nb_inst_memory,_param->_size_type                 );
+    DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr      );
+    DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr       );
+    DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT         ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_IMMEDIAT             ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RA              ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RB              ,_param->_nb_inst_memory,_param->_size_general_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_DATA_RC              ,_param->_nb_inst_memory,_param->_size_special_data         );
+    DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RD             ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RD           ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RE             ,_param->_nb_inst_memory,1                                  );
+    DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RE           ,_param->_nb_inst_memory,1                                  );
+
+    DELETE1_SIGNAL(out_MEMORY_OUT_VAL          ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL( in_MEMORY_OUT_ACK          ,_param->_nb_inst_memory,1);
+    DELETE1_SIGNAL(out_MEMORY_OUT_CONTEXT_ID   ,_param->_nb_inst_memory,_param->_size_context_id       );
+    DELETE1_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory,_param->_size_ooo_engine_id    );
+    DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID    ,_param->_nb_inst_memory,_param->_size_rob_ptr          );
+//  DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION    ,_param->_nb_inst_memory,_param->_size_operation        );
+    DELETE1_SIGNAL(out_MEMORY_OUT_TYPE         ,_param->_nb_inst_memory,_param->_size_type             );
+    DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD     ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD   ,_param->_nb_inst_memory,_param->_size_general_register );
+    DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RD      ,_param->_nb_inst_memory,_param->_size_general_data     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RE     ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RE   ,_param->_nb_inst_memory,_param->_size_general_register );
+    DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RE      ,_param->_nb_inst_memory,_param->_size_general_data     );
+    DELETE1_SIGNAL(out_MEMORY_OUT_EXCEPTION    ,_param->_nb_inst_memory,_param->_size_exception        );
+    DELETE1_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE  ,_param->_nb_inst_memory,1                              );
+    DELETE1_SIGNAL(out_MEMORY_OUT_ADDRESS      ,_param->_nb_inst_memory,_param->_size_general_data     );
+
+    DELETE1_SIGNAL(out_DCACHE_REQ_VAL        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL( in_DCACHE_REQ_ACK        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id  );
+    DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID  ,_param->_nb_cache_port,_param->_size_dcache_packet_id   );
+    DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS    ,_param->_nb_cache_port,_param->_size_general_data);
+    DELETE1_SIGNAL(out_DCACHE_REQ_TYPE       ,_param->_nb_cache_port,_param->_size_dcache_type );
+    DELETE1_SIGNAL(out_DCACHE_REQ_WDATA      ,_param->_nb_cache_port,_param->_size_general_data);
+
+    DELETE1_SIGNAL( in_DCACHE_RSP_VAL        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL(out_DCACHE_RSP_ACK        ,_param->_nb_cache_port,1);
+    DELETE1_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id  );
+    DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID  ,_param->_nb_cache_port,_param->_size_dcache_packet_id   );
+    DELETE1_SIGNAL( in_DCACHE_RSP_RDATA      ,_param->_nb_cache_port,_param->_size_general_data);
+    DELETE1_SIGNAL( in_DCACHE_RSP_ERROR      ,_param->_nb_cache_port,_param->_size_dcache_error);
+
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_VAL           ,_param->_nb_bypass_memory,1);
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory,_param->_size_ooo_engine_id   );
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_NUM_REG       ,_param->_nb_bypass_memory,_param->_size_general_register);
+    DELETE1_SIGNAL(out_BYPASS_MEMORY_DATA          ,_param->_nb_bypass_memory,_param->_size_general_data    );
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
-    delete    out_MEMORY_OUT_VAL       ;
-    delete     in_MEMORY_OUT_ACK       ;
-    if (_param->_have_port_context_id)
-    delete    out_MEMORY_OUT_CONTEXT_ID;
-    if (_param->_have_port_front_end_id)
-    delete    out_MEMORY_OUT_FRONT_END_ID;
-    if (_param->_have_port_ooo_engine_id)
-      delete    out_MEMORY_OUT_OOO_ENGINE_ID;
-    if (_param->_have_port_packet_id)
-    delete    out_MEMORY_OUT_PACKET_ID ;
-//  delete    out_MEMORY_OUT_OPERATION ;
-    delete    out_MEMORY_OUT_TYPE      ;
-    delete    out_MEMORY_OUT_WRITE_RD  ;
-    delete    out_MEMORY_OUT_NUM_REG_RD;
-    delete    out_MEMORY_OUT_DATA_RD   ;
-    delete    out_MEMORY_OUT_WRITE_RE  ;
-    delete    out_MEMORY_OUT_NUM_REG_RE;
-    delete    out_MEMORY_OUT_DATA_RE   ;
-    delete    out_MEMORY_OUT_EXCEPTION ;
-    delete    out_MEMORY_OUT_NO_SEQUENCE;
-    delete    out_MEMORY_OUT_ADDRESS   ;
+//     delete [] internal_MEMORY_IN_ACK          ;
+//     delete [] internal_MEMORY_OUT_VAL         ;
+//     delete [] internal_MEMORY_OUT_SELECT_QUEUE;
+//     delete [] internal_MEMORY_OUT_PTR         ;
     
-    delete    out_DCACHE_REQ_VAL       ;
-    delete     in_DCACHE_REQ_ACK       ;
-    if (_param->_have_port_dcache_context_id)
-    delete    out_DCACHE_REQ_CONTEXT_ID;
-    delete    out_DCACHE_REQ_PACKET_ID ;
-    delete    out_DCACHE_REQ_ADDRESS   ;
-    delete    out_DCACHE_REQ_TYPE      ;
-    delete    out_DCACHE_REQ_WDATA     ;
-    
-    delete     in_DCACHE_RSP_VAL       ;
-    delete    out_DCACHE_RSP_ACK       ;
-    if (_param->_have_port_dcache_context_id)
-    delete     in_DCACHE_RSP_CONTEXT_ID;
-    delete     in_DCACHE_RSP_PACKET_ID ;
-    delete     in_DCACHE_RSP_RDATA     ;
-    delete     in_DCACHE_RSP_ERROR     ;
-    
-    delete [] out_BYPASS_MEMORY_VAL       ;
-    if (_param->_have_port_ooo_engine_id)    
-    delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
-    delete [] out_BYPASS_MEMORY_NUM_REG   ;
-    delete [] out_BYPASS_MEMORY_DATA      ;
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+//     delete [] internal_DCACHE_RSP_ACK         ;
+//     delete [] internal_DCACHE_REQ_VAL         ;
+//     delete [] internal_DCACHE_REQ_SELECT_QUEUE;
+
+//     delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ;
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
     delete    _component;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp	(revision 88)
@@ -26,5 +26,6 @@
 
 #ifdef STATISTICS
-    _stat->end_cycle();
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
 #endif    
 
@@ -32,5 +33,6 @@
     // Evaluation before read the ouput signal
 //  sc_start(0);
-    _interfaces->testbench();
+    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
+      _interfaces->testbench();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp	(revision 88)
@@ -27,9 +27,28 @@
 
     // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    
+    // Initialisation
+    internal_MEMORY_IN_PORT = 0;
+    Tcontrol_t ack [_param->_nb_inst_memory];
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      ack [i] = 0;
 
+    // find first valid entry
     // store queue is never full (pointer is manage by rename stage)
-    internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) or not _speculative_access_queue_control->full();
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      if (PORT_READ(in_MEMORY_IN_VAL [i]))
+	{
+	  internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full();
 
-    PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK);
+	  if (internal_MEMORY_IN_ACK)
+	    {
+	      ack [i] = 1;
+	      internal_MEMORY_IN_PORT = i;
+	      break; // end
+	    }
+	}
+
+    for (uint32_t i=0; i<_param->_nb_inst_memory; i++)
+      PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]);
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp	(revision 88)
@@ -4,5 +4,5 @@
  * $Id$
  *
- * [ Description ]
+ * [ Description ]
  * 
  */
@@ -26,5 +26,5 @@
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
 
-    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
     Tcontext_t         memory_out_context_id    = 0;
@@ -110,29 +110,30 @@
       }
     // write output
-    PORT_WRITE(out_MEMORY_OUT_VAL          , internal_MEMORY_OUT_VAL);
+    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
 
     if (_param->_have_port_context_id)
-    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   , memory_out_context_id   );
+    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
     if (_param->_have_port_front_end_id)
-    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID , memory_out_front_end_id );
+    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
     if (_param->_have_port_ooo_engine_id)
-    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID, memory_out_ooo_engine_id);
-    if (_param->_have_port_packet_id)
-    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    , memory_out_packet_id    );
-//  PORT_WRITE(out_MEMORY_OUT_OPERATION    , memory_out_operation    );
-    PORT_WRITE(out_MEMORY_OUT_TYPE         , TYPE_MEMORY             );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     , memory_out_write_rd     );
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   , memory_out_num_reg_rd   );
-    PORT_WRITE(out_MEMORY_OUT_DATA_RD      , memory_out_data_rd      );
-//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , memory_out_write_re     );
-//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , memory_out_num_reg_re   );
-//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      , memory_out_data_re      );
-    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     , 0);
-    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   , 0);
-    PORT_WRITE(out_MEMORY_OUT_DATA_RE      , 0);
-    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    , memory_out_exception    );
-    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  , 0);
-    PORT_WRITE(out_MEMORY_OUT_ADDRESS      , 0);
-    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
+    if (_param->_have_port_rob_ptr)
+    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
+//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
+    PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
+    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
+//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
+//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
+//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
+    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
+    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
+    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
+
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
     Tcontext_t        dcache_req_context_id;
@@ -201,11 +202,11 @@
       }
 
-    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
+    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
     if (_param->_have_port_dcache_context_id)
-    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
-    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
-    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
-    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
-    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
     
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp	(revision 88)
@@ -255,6 +255,6 @@
 	// Interface "MEMORY_IN"
 	//================================================================
-
-        if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and
+	
+        if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and
             (    internal_MEMORY_IN_ACK  == 1))
           {
@@ -266,10 +266,10 @@
 
 #ifdef DEBUG_TEST
-	    if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY)
+	    if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY)
 	      throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'");
 #endif
-	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION);
-	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT) +
-						    PORT_READ(in_MEMORY_IN_DATA_RA ));
+	    Toperation_t    operation            = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]);
+	    Tgeneral_data_t address              = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) +
+						    PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT]));
 	    bool            exception_alignement = (mask_memory_access(operation) & address) != 0;
 						    
@@ -287,5 +287,5 @@
 		
 		// Write pointer is define in rename stage :
-		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
+		Tlsq_ptr_t           index         = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		log_printf(TRACE,Load_store_unit,FUNCTION,"   * index         : %d",index);
 		
@@ -375,15 +375,15 @@
 		    log_printf(TRACE,Load_store_unit,FUNCTION,"   * Update information");
 
-		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID);
-		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID);
-		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID);
-		    _store_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID   );
+		    _store_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		    _store_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
 		    _store_queue [index]._operation            = operation;
-		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
+		    _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		    _store_queue [index]._address              = address;
 
 		    // reordering data
-		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB), memory_size(operation), 0);
-//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  );
+		    _store_queue [index]._wdata                = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0);
+//                  _store_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
 		  }
 	      }
@@ -413,16 +413,16 @@
 		// NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits)
 		_speculative_access_queue [index]._state                = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE;
-		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID);
-		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID);
-		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID);
-		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_packet_id    )?0:PORT_READ(in_MEMORY_IN_PACKET_ID);
+		_speculative_access_queue [index]._context_id           = (not _param->_have_port_context_id   )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID   [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._front_end_id         = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._ooo_engine_id        = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._packet_id            = (not _param->_have_port_rob_ptr      )?0:PORT_READ(in_MEMORY_IN_PACKET_ID    [internal_MEMORY_IN_PORT]);
 
 		_speculative_access_queue [index]._operation            = operation;
-		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE);
-		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE);
+		_speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
+		_speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]);
 		_speculative_access_queue [index]._address              = address;
 		// NOTE : is operation is a load, then they are a result and must write in the register file
 		_speculative_access_queue [index]._write_rd             = is_operation_memory_load(operation);
-		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  );
+		_speculative_access_queue [index]._num_reg_rd           = PORT_READ(in_MEMORY_IN_NUM_REG_RD  [internal_MEMORY_IN_PORT]);
 
 		_speculative_access_queue [index]._exception            = exception;
@@ -437,5 +437,5 @@
 
         if ((    internal_MEMORY_OUT_VAL  == 1) and
-            (PORT_READ(in_MEMORY_OUT_ACK) == 1))
+            (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1))
           {
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction");
@@ -495,5 +495,5 @@
 
         if ((    internal_DCACHE_REQ_VAL  == 1) and
-            (PORT_READ(in_DCACHE_REQ_ACK) == 1))
+            (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1))
           {
 	    log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ");
@@ -598,5 +598,5 @@
 	// Interface "DCACHE_RSP"
 	//================================================================
-        if ((PORT_READ(in_DCACHE_RSP_VAL)== 1) and
+        if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and
             (    internal_DCACHE_RSP_ACK == 1))
           {
@@ -604,8 +604,8 @@
 
 	    // don't use context_id : because there are one queue for all thread
-	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID); 
-	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID );
-	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     );
-	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     );
+	    //Tcontext_t      context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); 
+	    Tpacket_t       packet_id  = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]);
+	    Tdcache_data_t  rdata      = PORT_READ(in_DCACHE_RSP_RDATA     [0]);
+	    Tdcache_error_t error      = PORT_READ(in_DCACHE_RSP_ERROR     [0]);
 
 	    log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id);
@@ -662,5 +662,5 @@
 	
 	
-#if DEBUG>=DEBUG_TRACE
+#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE)
 	// ***** dump store queue
 	std::cout << "Dump STORE_QUEUE :" << std::endl
@@ -694,17 +694,19 @@
 		 << _load_queue[j] << std::endl;
 	  }
-	
 #endif
 	
 #ifdef STATISTICS
-	for (uint32_t i=0; i<_param->_size_store_queue; i++)
-	  if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
-	    (*_stat_use_store_queue) ++;
-	for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
-	  if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
-	    (*_stat_use_speculative_access_queue) ++;
-	for (uint32_t i=0; i<_param->_size_load_queue; i++)
-	  if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
-	    (*_stat_use_load_queue) ++;
+        if (usage_is_set(_usage,USE_STATISTICS))
+          {
+            for (uint32_t i=0; i<_param->_size_store_queue; i++)
+              if (_store_queue[i]._state != STORE_QUEUE_EMPTY)
+                (*_stat_use_store_queue) ++;
+            for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++)
+              if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY)
+                (*_stat_use_speculative_access_queue) ++;
+            for (uint32_t i=0; i<_param->_size_load_queue; i++)
+              if (_load_queue[i]._state != LOAD_QUEUE_EMPTY)
+                (*_stat_use_load_queue) ++;
+          }
 #endif
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp	(revision 88)
@@ -26,4 +26,6 @@
 			  Tspeculative_load_t speculative_load       ,
 			  uint32_t            nb_bypass_memory       ,
+			  uint32_t            nb_cache_port          ,
+			  uint32_t            nb_inst_memory         ,
 			  uint32_t            nb_context             ,
 			  uint32_t            nb_front_end           ,
@@ -33,97 +35,120 @@
 			  uint32_t            size_special_data      ,
 			  uint32_t            nb_general_register    ,
-			  uint32_t            nb_special_register    ):
-    _size_store_queue        (size_store_queue       ),
-    _size_load_queue         (size_load_queue        ),
-    _size_speculative_access_queue (size_speculative_access_queue),
-    _nb_port_check           (nb_port_check          ),
-    _speculative_load        (speculative_load       ),
-    _nb_bypass_memory        (nb_bypass_memory       ),
-    _nb_context              (nb_context             ),
-    _nb_front_end            (nb_front_end           ),
-    _nb_ooo_engine           (nb_ooo_engine          ),
-    _nb_packet               (nb_packet              ),
-    _size_general_data       (size_general_data      ),
-    _size_special_data       (size_special_data      ),
-    _nb_general_register     (nb_general_register    ),
-    _nb_special_register     (nb_special_register    ),
-    
-    _size_address_store_queue              (log2(size_store_queue             )),
-    _size_address_load_queue               (log2(size_load_queue              )),
-    _size_address_speculative_access_queue (log2(size_speculative_access_queue)),
-
-    _size_context_id         (log2(nb_context         )),
-    _size_front_end_id       (log2(nb_front_end       )),
-    _size_ooo_engine_id      (log2(nb_ooo_engine      )),
-    _size_packet_id          (log2(nb_packet          )),
-    _size_general_register   (log2(nb_general_register)),
-    _size_special_register   (log2(nb_special_register)),
-    _size_dcache_context_id  (_size_context_id + _size_front_end_id + _size_ooo_engine_id),
-    _size_dcache_packet_id   ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1),
-
-    _have_port_context_id        (_size_context_id   >0),
-    _have_port_front_end_id      (_size_front_end_id >0),
-    _have_port_ooo_engine_id     (_size_ooo_engine_id>0),
-    _have_port_packet_id         (_size_packet_id    >0),
-    _have_port_dcache_context_id (_size_dcache_context_id>0),
-    _have_port_load_queue_ptr    (_size_load_queue>1),
-
-    _mask_address_lsb            (gen_mask<Tdcache_address_t>(log2(size_general_data/8))),
-    _mask_address_msb            (gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8))
+			  uint32_t            nb_special_register    ,
+                          bool                is_toplevel)
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+
+    _size_store_queue                      = size_store_queue       ;
+    _size_load_queue                       = size_load_queue        ;
+    _size_speculative_access_queue         = size_speculative_access_queue;
+    _nb_port_check                         = nb_port_check          ;
+    _speculative_load                      = speculative_load       ;
+    _nb_bypass_memory                      = nb_bypass_memory       ;
+    _nb_cache_port                         = nb_cache_port          ;
+    _nb_inst_memory                        = nb_inst_memory         ;
+    _nb_context                            = nb_context             ;
+    _nb_front_end                          = nb_front_end           ;
+    _nb_ooo_engine                         = nb_ooo_engine          ;
+    _nb_packet                             = nb_packet              ;
+    _nb_general_register                   = nb_general_register    ;
+    _nb_special_register                   = nb_special_register    ;
+    
+    _size_speculative_access_queue_ptr     = log2(size_speculative_access_queue);
+
+    _size_dcache_context_id                = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine);
+    _size_dcache_packet_id                 = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1;
+
+    _have_port_dcache_context_id           = _size_dcache_context_id>0;
+
+    _mask_address_lsb                      = gen_mask<Tdcache_address_t>(log2(size_general_data/8));
+    _mask_address_msb                      = gen_mask<Tdcache_address_t>(size_general_data) << log2(size_general_data/8);
+
     test();
+
+    if (is_toplevel)
+      {
+        _size_context_id                       = log2(nb_context         );
+        _size_front_end_id                     = log2(nb_front_end       );
+        _size_ooo_engine_id                    = log2(nb_ooo_engine      );
+        _size_rob_ptr                          = log2(nb_packet          );
+        _size_general_register                 = log2(nb_general_register);
+        _size_special_register                 = log2(nb_special_register);
+        _size_store_queue_ptr                  = log2(size_store_queue   );
+        _size_load_queue_ptr                   = log2(size_load_queue    );
+        _size_general_data                     = size_general_data      ;
+        _size_special_data                     = size_special_data      ;
+
+        _have_port_context_id                  = _size_context_id    >0;
+        _have_port_front_end_id                = _size_front_end_id  >0;
+        _have_port_ooo_engine_id               = _size_ooo_engine_id >0;
+        _have_port_rob_ptr                     = _size_rob_ptr       >0;
+        _have_port_load_queue_ptr              = _size_load_queue_ptr>0;
+
+        copy();
+      }
+
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
   
+// #undef  FUNCTION
+// #define FUNCTION "Load_store_unit::Parameters (copy)"
+//   Parameters::Parameters (Parameters & param):
+//     _size_store_queue        (param._size_store_queue       ),
+//     _size_load_queue         (param._size_load_queue        ),
+//     _size_speculative_access_queue (param._size_speculative_access_queue),
+//     _nb_port_check           (param._nb_port_check          ),
+//     _speculative_load        (param._speculative_load       ),
+//     _nb_bypass_memory        (param._nb_bypass_memory       ),
+//     _nb_cache_port           (param._nb_cache_port          ),
+//     _nb_inst_memory          (param._nb_inst_memory         ),
+//     _nb_context              (param._nb_context             ),
+//     _nb_front_end            (param._nb_front_end           ),
+//     _nb_ooo_engine           (param._nb_ooo_engine          ),
+//     _nb_packet               (param._nb_packet              ),
+//     _size_general_data       (param._size_general_data      ),
+//     _size_special_data       (param._size_special_data      ),
+//     _nb_general_register     (param._nb_general_register    ),
+//     _nb_special_register     (param._nb_special_register    ),
+
+//     _size_address_store_queue              (param._size_address_store_queue             ),
+//     _size_address_load_queue               (param._size_address_load_queue              ),
+//     _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
+
+//     _size_context_id         (param._size_context_id        ),
+//     _size_front_end_id       (param._size_front_end_id      ),
+//     _size_ooo_engine_id      (param._size_ooo_engine_id     ),
+//     _size_packet_id          (param._size_packet_id         ),
+//     _size_general_register   (param._size_general_register  ),
+//     _size_special_register   (param._size_special_register  ),
+//     _size_dcache_context_id  (param._size_dcache_context_id ),
+//     _size_dcache_packet_id   (param._size_dcache_packet_id  ),
+
+//     _have_port_context_id    (param._have_port_context_id   ),
+//     _have_port_front_end_id  (param._have_port_front_end_id ),
+//     _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
+//     _have_port_packet_id     (param._have_port_packet_id    ),
+//     _have_port_dcache_context_id(param._have_port_dcache_context_id),
+//     _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
+
+//     _mask_address_lsb        (param._mask_address_lsb),
+//     _mask_address_msb        (param._mask_address_msb)
+//   {
+//     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
+//     test();
+//     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
+//   };
+
 #undef  FUNCTION
-#define FUNCTION "Load_store_unit::Parameters (copy)"
-  Parameters::Parameters (Parameters & param):
-    _size_store_queue        (param._size_store_queue       ),
-    _size_load_queue         (param._size_load_queue        ),
-    _size_speculative_access_queue (param._size_speculative_access_queue),
-    _nb_port_check           (param._nb_port_check          ),
-    _speculative_load        (param._speculative_load       ),
-    _nb_bypass_memory        (param._nb_bypass_memory       ),
-    _nb_context              (param._nb_context             ),
-    _nb_front_end            (param._nb_front_end           ),
-    _nb_ooo_engine           (param._nb_ooo_engine          ),
-    _nb_packet               (param._nb_packet              ),
-    _size_general_data       (param._size_general_data      ),
-    _size_special_data       (param._size_special_data      ),
-    _nb_general_register     (param._nb_general_register    ),
-    _nb_special_register     (param._nb_special_register    ),
-
-    _size_address_store_queue              (param._size_address_store_queue             ),
-    _size_address_load_queue               (param._size_address_load_queue              ),
-    _size_address_speculative_access_queue (param._size_address_speculative_access_queue),
-
-    _size_context_id         (param._size_context_id        ),
-    _size_front_end_id       (param._size_front_end_id      ),
-    _size_ooo_engine_id      (param._size_ooo_engine_id     ),
-    _size_packet_id          (param._size_packet_id         ),
-    _size_general_register   (param._size_general_register  ),
-    _size_special_register   (param._size_special_register  ),
-    _size_dcache_context_id  (param._size_dcache_context_id ),
-    _size_dcache_packet_id   (param._size_dcache_packet_id  ),
-
-    _have_port_context_id    (param._have_port_context_id   ),
-    _have_port_front_end_id  (param._have_port_front_end_id ),
-    _have_port_ooo_engine_id (param._have_port_ooo_engine_id),
-    _have_port_packet_id     (param._have_port_packet_id    ),
-    _have_port_dcache_context_id(param._have_port_dcache_context_id),
-    _have_port_load_queue_ptr(param._have_port_load_queue_ptr),
-
-    _mask_address_lsb        (param._mask_address_lsb),
-    _mask_address_msb        (param._mask_address_msb)
+#define FUNCTION "Load_store_unit::~Parameters"
+  Parameters::~Parameters (void) 
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
-    test();
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };
 
 #undef  FUNCTION
-#define FUNCTION "Load_store_unit::~Parameters"
-  Parameters::~Parameters () 
+#define FUNCTION "Load_store_unit::copy"
+  void Parameters::copy (void) 
   {
     log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp	(revision 88)
@@ -32,5 +32,5 @@
 	{
 	  if (not (_nb_bypass_memory == 0))
-	    test.error("Bypass memory is not supported. Please wait a next revision.");
+	    test.error(_("Bypass memory is not supported. Please wait a next revision.\n"));
  
 	  break;
@@ -42,7 +42,7 @@
 	{
 	  if (not (_nb_bypass_memory == 0))
-	    test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass.");
+	    test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str()));
 
-	  test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision.");
+	  test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str()));
 	  break;
 	}
@@ -50,8 +50,14 @@
 
     if (not (_size_store_queue >= 2))
-      test.error("Store queue must have at less two slot.");
+      test.error(_("Store queue must have at less two slot.\n"));
 
     if (not (_nb_bypass_memory <= _size_load_queue))
-      test.error("Bypass number must be less than load_queue's size.");
+      test.error(_("Bypass number must be less than load_queue's size.\n"));
+
+    if (_nb_cache_port > 1)
+      test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); 
+
+    if (_nb_inst_memory > 1)
+      test.warning(_("nb_inst_memory > 1 is unsupported (Coming Soon).\n")); 
 
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
