Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Read_unit_library_clean
 
+local_clean			:
+
 include                         $(DIR_COMPONENT)/Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg	(revision 88)
@@ -1,8 +1,8 @@
 Read_unit
-4	4	*2	# size_read_queue         
-4	4	*2	# size_reservation_station
+4	8	*2	# size_read_queue         
+4	8	*2	# size_reservation_station
 1	1	*2	# nb_context              
 1	1	*2	# nb_front_end            
-1	4	*2	# nb_ooo_engine           
+1	4	*4	# nb_ooo_engine           
 64	64	*2 	# nb_packet               
 32	32	*2	# size_general_data       
@@ -10,9 +10,9 @@
 64	64	*2	# nb_general_register     
 16	16	*2	# nb_special_register     
-2	2	*2	# nb_gpr_write            
-2	2	*2	# nb_spr_write            
-4	4	*2	# size_store_queue        
-1	4	*4	# size_load_queue         
-2	2	*2	# nb_inst_retire          
-2	2	*2	# nb_bypass_write         
-2	2	*2	# nb_bypass_memory        
+4	4	*4	# nb_gpr_write            
+4	4	*4	# nb_spr_write            
+4	4	*2	# size_store_queue
+4	4	*4	# size_load_queue         
+4	4	*4	# nb_inst_retire          
+4	4	*4	# nb_bypass_write         
+4	4	*4	# nb_bypass_memory        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp	(revision 88)
@@ -85,5 +85,7 @@
 	 _nb_inst_retire          ,
 	 _nb_bypass_write         ,
-	 _nb_bypass_memory        );
+	 _nb_bypass_memory        ,
+         true // is_toplevel
+         );
       
       msg(_("%s"),param->print(1).c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp	(revision 88)
@@ -7,10 +7,24 @@
  */
 
-#define NB_ITERATION  1
-#define CYCLE_MAX     (128*NB_ITERATION)
+#define NB_ITERATION  16
+#define CYCLE_MAX     (1024*NB_ITERATION)
 
 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/include/test.h"
 #include "Common/include/Test.h"
+#include "Common/include/BitManipulation.h"
 #include "Behavioural/include/Allocation.h"
+
+class write_req_t
+{
+  public : uint32_t ooo;
+  public : uint32_t reg;
+
+  write_req_t (uint32_t ooo,
+	       uint32_t reg)
+  {
+    this->ooo = ooo;
+    this->reg = reg;
+  }
+};
 
 void test (string name,
@@ -22,4 +36,14 @@
   morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Read_unit * _Read_unit = new Read_unit 
@@ -29,5 +53,5 @@
 #endif
      _param,
-     USE_ALL);
+     _usage);
   
 #ifdef SYSTEMC
@@ -130,5 +154,5 @@
   if (_param->_have_port_ooo_engine_id)
   INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID         );
-  if (_param->_have_port_packet_id)
+  if (_param->_have_port_rob_ptr)
   INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_PACKET_ID             );
   INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OPERATION             );
@@ -157,5 +181,5 @@
   if (_param->_have_port_ooo_engine_id)
   INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OOO_ENGINE_ID        ,_param->_nb_inst_retire);
-  if (_param->_have_port_packet_id)
+  if (_param->_have_port_rob_ptr)
   INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_PACKET_ID            ,_param->_nb_inst_retire);
   INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OPERATION            ,_param->_nb_inst_retire);
@@ -213,4 +237,12 @@
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
     
+  // Initialisation
+  const uint32_t seed = 0;
+//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  SC_START(0);
+
   Time * _time = new Time();
 
@@ -218,19 +250,42 @@
    * Simulation - Begin
    ********************************************************/
-
+  {
   // Initialisation
 
-  const uint32_t seed = 0;
-//const uint32_t seed = static_cast<uint32_t>(time(NULL));
-
-  srand(seed);
-
-  SC_START(0);
+  const uint32_t nb_request = _param->_nb_packet;
+
+  Tcontext_t         _ooo_engine_id [nb_request];
+  Tcontrol_t         _read_ra    [nb_request];
+  Tgeneral_address_t _num_reg_ra [nb_request];
+  Tcontrol_t         _read_rb    [nb_request];
+  Tgeneral_address_t _num_reg_rb [nb_request];
+  Tcontrol_t         _read_rc    [nb_request];
+  Tspecial_address_t _num_reg_rc [nb_request];
+
+  // emulation of registerFile
+  Tcontrol_t         _gpr_val    [_param->_nb_general_register][_param->_nb_ooo_engine];
+  Tgeneral_data_t    _gpr        [_param->_nb_general_register][_param->_nb_ooo_engine];
+  Tcontrol_t         _spr_val    [_param->_nb_special_register][_param->_nb_ooo_engine];
+  Tspecial_data_t    _spr        [_param->_nb_special_register][_param->_nb_ooo_engine];
+
   LABEL("Initialisation");
-
-  LABEL("Reset");
+  in_READ_UNIT_IN_VAL ->write(0);
+  for (uint32_t i=0; i<_param->_nb_inst_retire  ; i++)
+    in_READ_UNIT_OUT_ACK [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_gpr_write    ; i++)
+    in_GPR_WRITE_VAL               [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_spr_write    ; i++)
+    in_SPR_WRITE_VAL               [i]->write(0);
+  for (uint32_t i=0; i<_param->_nb_bypass_write ; i++)
+    {
+      in_BYPASS_WRITE_GPR_VAL      [i]->write(0);
+      in_BYPASS_WRITE_SPR_VAL      [i]->write(0);
+    }
+  for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
+    in_BYPASS_MEMORY_VAL           [i]->write(0);
+
   in_NRESET->write(0);
   SC_START(5);
-  in_NRESET->write(1);  
+  in_NRESET->write(1);
 
   LABEL("Loop of Test");
@@ -240,6 +295,422 @@
       LABEL("Iteration %d",iteration);
 
-      SC_START(1);
+      int32_t percent_transaction_queue_in     = (rand()%50)+25;
+      int32_t percent_transaction_queue_out    = (rand()%50)+25;
+      int32_t percent_registerfile_valid       = (rand()%50)+25;
+      int32_t percent_transaction_registerfile = (rand()%50)+25;
+      int32_t percent_transaction_bypass       = (rand()%50)+25;
+      
+      LABEL("Initialisation");
+
+      for (uint32_t i=0; i<nb_request; i++)
+	{
+	  _ooo_engine_id   [i] = rand()% _param->_nb_ooo_engine            ;
+	  _read_ra         [i] = rand()% 2                              ;
+	  _num_reg_ra      [i] = rand()% _param->_nb_general_register   ;
+	  _read_rb         [i] = rand()% 2                              ;
+	  _num_reg_rb      [i] = rand()% _param->_nb_general_register   ;
+	  _read_rc         [i] = rand()% 2                              ;
+	  _num_reg_rc      [i] = rand()% _param->_nb_special_register   ;
+	}
+      
+      // emulation of registerFile
+      for (uint32_t j=0; j<_param->_nb_ooo_engine; j++)
+	{
+	  for (uint32_t i=0; i<_param->_nb_general_register; i++)
+	    {
+	      _gpr_val      [i][j] = ((rand()%100) < percent_registerfile_valid);
+	      _gpr          [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
+	    }
+	  for (uint32_t i=0; i<_param->_nb_special_register; i++)
+	    {
+	      _spr_val      [i][j] = ((rand()%100) < percent_registerfile_valid);
+	      _spr          [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data);
+	    }
+	}
+      // End initialisation .......
+
+      uint32_t request_in  = 0;
+      uint32_t request_out = 0;
+      bool     request_out_wait [nb_request];
+
+      for (uint32_t i=0; i<nb_request; i++)
+	request_out_wait [i] = true;
+      
+//       bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
+//       bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
+
+      list<write_req_t> write_req_gpr;
+      list<write_req_t> write_req_spr;
+
+      while (request_out < nb_request)
+	{
+	  LABEL("request_in         : %d",request_in );
+	  LABEL("request_out        : %d",request_out);
+	  for (uint32_t i=0; i<nb_request; i++)
+	    if (request_out_wait [i])
+	      LABEL("request_out_wait   : %d",i);
+	  LABEL("write_req_gpr size : %d",write_req_gpr.size());
+	  LABEL("write_req_spr size : %d",write_req_spr.size());
+
+// 	  for (uint32_t j=0; j<_param->_nb_ooo_engine; j++)
+// 	    {
+// 	      for (uint32_t i=0; i<_param->_nb_general_register; i++)
+// 		can_gpr_use [j][i] = true;
+// 	      for (uint32_t i=0; i<_param->_nb_special_register; i++)
+// 		can_spr_use [j][i] = true;
+// 	    }
+
+	  Tcontrol_t         read_unit_in_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in);
+	  Tcontext_t         read_unit_in_ooo_engine_id;
+	  Tgeneral_address_t read_unit_in_num_reg_ra;
+	  Tgeneral_address_t read_unit_in_num_reg_rb;
+	  Tspecial_address_t read_unit_in_num_reg_rc;
+
+	  in_READ_UNIT_IN_VAL         ->write(read_unit_in_val);
+	  if (read_unit_in_val)
+	    {
+	      bool               data_val;
+	      read_unit_in_ooo_engine_id = _ooo_engine_id [request_in];
+	      read_unit_in_num_reg_ra    = _num_reg_ra [request_in];
+	      read_unit_in_num_reg_rb    = _num_reg_rb [request_in];
+	      read_unit_in_num_reg_rc    = _num_reg_rc [request_in];
+
+	      if (_param->_have_port_context_id)
+              in_READ_UNIT_IN_CONTEXT_ID     ->write((2*read_unit_in_ooo_engine_id)%_param->_nb_context  );
+	      if (_param->_have_port_front_end_id)
+              in_READ_UNIT_IN_FRONT_END_ID   ->write((3*read_unit_in_ooo_engine_id)%_param->_nb_front_end);
+   	      if (_param->_have_port_ooo_engine_id)
+              in_READ_UNIT_IN_OOO_ENGINE_ID  ->write(read_unit_in_ooo_engine_id);
+   	      if (_param->_have_port_rob_ptr)
+              in_READ_UNIT_IN_PACKET_ID   ->write(request_in);
+   	      in_READ_UNIT_IN_OPERATION   ->write(0);
+   	      in_READ_UNIT_IN_TYPE        ->write(0);
+   	      in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE->write(0);
+	      if (_param->_have_port_load_queue_ptr)
+   	      in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ->write(0);
+   	      in_READ_UNIT_IN_HAS_IMMEDIAT->write(0);
+   	      in_READ_UNIT_IN_IMMEDIAT    ->write(0);
+	      in_READ_UNIT_IN_READ_RA     ->write(_read_ra[request_in]);
+	      data_val = not(_read_ra[request_in]) or _gpr_val[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id];
+
+ 	      if (not data_val)
+		if (rand ()%2)
+		  write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra));
+		else
+		  write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra));
+
+
+	      in_READ_UNIT_IN_NUM_REG_RA  ->write(read_unit_in_num_reg_ra);
+//    	      in_READ_UNIT_IN_DATA_RA_VAL ->write(data_val);
+//    	      in_READ_UNIT_IN_DATA_RA     ->write((data_val)?_gpr[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]:0);
+	      in_READ_UNIT_IN_READ_RB     ->write(_read_rb[request_in]);
+	      data_val = not(_read_rb[request_in]) or _gpr_val[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id];
+
+ 	      if (not data_val)
+  		if (rand ()%2)
+		  write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb));
+		else
+		  write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb));
+
+
+   	      in_READ_UNIT_IN_NUM_REG_RB  ->write(read_unit_in_num_reg_rb);			       
+//    	      in_READ_UNIT_IN_DATA_RB_VAL ->write(data_val);			       
+//    	      in_READ_UNIT_IN_DATA_RB     ->write((data_val)?_gpr[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]:0);
+	      in_READ_UNIT_IN_READ_RC     ->write(_read_rc[request_in]);
+	      data_val = not(_read_rc[request_in]) or _spr_val[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id];
+
+	      if (not data_val)
+		if (rand ()%2)
+		  write_req_spr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc));
+		else
+		  write_req_spr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc));
+
+   	      in_READ_UNIT_IN_NUM_REG_RC  ->write(read_unit_in_num_reg_rc);			       
+//    	      in_READ_UNIT_IN_DATA_RC_VAL ->write(data_val);			       
+//    	      in_READ_UNIT_IN_DATA_RC     ->write((data_val)?_spr[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]:0);
+   	      in_READ_UNIT_IN_WRITE_RD    ->write(0);
+   	      in_READ_UNIT_IN_NUM_REG_RD  ->write(0);
+   	      in_READ_UNIT_IN_WRITE_RE    ->write(0);
+   	      in_READ_UNIT_IN_NUM_REG_RE  ->write(0);
+
+// 	      can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_ra] = false;
+// 	      can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rb] = false;
+// 	      can_spr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rc] = false;
+	    }
+	  	  
+	  for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+	    in_READ_UNIT_OUT_ACK[i]->write((rand()%100)<percent_transaction_queue_out);
+
+	  // RegisterFile access
+	  for (uint32_t i=0; i<_param->_nb_gpr_read ; i++)
+	    {
+	      Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile;
+	      in_GPR_READ_ACK      [i]->write(ack);
+
+	      SC_START(0);
+
+	      if (out_GPR_READ_VAL [i]->read())
+		{
+		  Tgeneral_address_t num_reg    = out_GPR_READ_NUM_REG       [i]->read();
+		  Tcontext_t         ooo_engine = (_param->_have_port_ooo_engine_id)?out_GPR_READ_OOO_ENGINE_ID [i]->read():0;
+		  Tgeneral_data_t    data       = _gpr    [num_reg][ooo_engine];
+		  Tcontrol_t         data_val   = _gpr_val[num_reg][ooo_engine];
+		  
+		  if (ack)
+		    LABEL(" * GPR_READ      [%d] - gpr[%d][%d] ->  (%d) 0x%x",i,num_reg,ooo_engine,data_val,data);
+		  
+		  in_GPR_READ_DATA     [i]->write(data);
+		  in_GPR_READ_DATA_VAL [i]->write(data_val);
+		}
+	    }
+
+	  for (uint32_t i=0; i<_param->_nb_spr_read ; i++)
+	    {
+	      Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile;
+	      in_SPR_READ_ACK      [i]->write(ack);
+
+	      SC_START(0);
+
+	      if (out_SPR_READ_VAL [i]->read())
+		{
+		  Tspecial_address_t num_reg    = out_SPR_READ_NUM_REG       [i]->read();
+		  Tcontext_t         ooo_engine = (_param->_have_port_ooo_engine_id)?out_SPR_READ_OOO_ENGINE_ID [i]->read():0;
+		  Tspecial_data_t    data       = _spr    [num_reg][ooo_engine];
+		  Tcontrol_t         data_val   = _spr_val[num_reg][ooo_engine];
+		  
+		  if (ack)
+		    LABEL(" * SPR_READ      [%d] - spr[%d][%d] ->  (%d) 0x%x",i,num_reg,ooo_engine,data_val,data);
+		  
+		  in_SPR_READ_DATA     [i]->write(data);
+		  in_SPR_READ_DATA_VAL [i]->write(data_val);
+		}
+	    }
+
+	  list<write_req_t>::iterator it_gpr = write_req_gpr.begin();
+	  list<write_req_t>::iterator it_spr = write_req_spr.begin();
+
+	  LABEL("Bypass Network :");
+	  for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
+	    {
+	      Tcontext_t         ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
+	      Tgeneral_address_t num_reg    = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
+	      Tcontrol_t         val     = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0;
+	      Tgeneral_data_t    data    = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
+	    
+	      val = (val// and can_spr_use [ooo_engine][num_reg]
+		     and (it_gpr != write_req_gpr.end()));
+
+	      in_GPR_WRITE_VAL            [i]->write(val);	      
+	      if (_param->_have_port_ooo_engine_id)
+              in_GPR_WRITE_OOO_ENGINE_ID  [i]->write(ooo_engine);
+	      in_GPR_WRITE_NUM_REG        [i]->write(num_reg);
+	      in_GPR_WRITE_DATA           [i]->write(data);
+
+	      if (val)
+		{
+		  LABEL(" * GPR_WRITE     [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
+
+// 		  can_gpr_use [ooo_engine][num_reg] = false;
+
+		  _gpr     [num_reg][ooo_engine] = data;
+		  _gpr_val [num_reg][ooo_engine] = 1;
+		}
+
+	      if (it_gpr != write_req_gpr.end())
+		it_gpr ++;
+	    }
+	  for (uint32_t i=0; i<_param->_nb_spr_write; i++)
+	    {
+	      Tcontext_t         ooo_engine = (it_spr != write_req_spr.end())?(*it_spr).ooo:0;
+	      Tgeneral_address_t num_reg    = (it_spr != write_req_spr.end())?(*it_spr).reg:0;
+
+	      Tcontrol_t         val     = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0;
+	      Tspecial_data_t    data    = range<Tspecial_data_t>(rand(),_param->_size_special_data);
+
+	      val = (val // and can_spr_use [ooo_engine][num_reg]
+		     and (it_spr != write_req_spr.end()));
+
+	      in_SPR_WRITE_VAL            [i]->write(val);	      
+	      if (_param->_have_port_ooo_engine_id)
+              in_SPR_WRITE_OOO_ENGINE_ID  [i]->write(ooo_engine);
+	      in_SPR_WRITE_NUM_REG        [i]->write(num_reg);
+	      in_SPR_WRITE_DATA           [i]->write(data);
+
+	      if (val == 1)
+		{
+		  LABEL(" * SPR_WRITE     [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
+		  
+// 		  can_spr_use [ooo_engine][num_reg] = false;
+
+		  _spr     [num_reg][ooo_engine] = data;
+		  _spr_val [num_reg][ooo_engine] = 1;
+		}
+
+	      if (it_spr != write_req_spr.end())
+		it_spr ++;
+
+	    }
+
+	  for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
+	    {
+	      Tcontext_t         ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
+	      Tgeneral_address_t gpr_num_reg= (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
+
+	      if (_param->_have_port_ooo_engine_id)
+              in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine);
+
+	      Tcontrol_t         gpr_val     = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
+	      Tgeneral_data_t    gpr_data    = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
+	      
+	      gpr_val = (gpr_val // and can_gpr_use [ooo_engine][gpr_num_reg]
+			 and (it_gpr != write_req_gpr.end()));
+
+	      in_BYPASS_WRITE_GPR_VAL    [i]->write(gpr_val);	      
+	      in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg);
+	      in_BYPASS_WRITE_GPR_DATA   [i]->write(gpr_data);
+
+	      if (gpr_val)
+		{
+		  LABEL(" * BYPASS_WRITE  [%d] - gpr[%d][%d] <- 0x%x",i,gpr_num_reg,ooo_engine,gpr_data);
+// 		  can_gpr_use [ooo_engine][gpr_num_reg] = false;
+
+		  _gpr     [gpr_num_reg][ooo_engine] = gpr_data;
+		  _gpr_val [gpr_num_reg][ooo_engine] = 1;
+		}
+
+ 	      if (it_gpr != write_req_gpr.end())
+		it_gpr ++;
+
+	      Tspecial_address_t spr_num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0;
+	      Tcontrol_t         spr_val     = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
+	      Tspecial_data_t    spr_data    = range<Tspecial_data_t>(rand(),_param->_size_special_data);
+	      
+	      spr_val = (spr_val // and can_spr_use [ooo_engine][spr_num_reg]
+			 and (it_spr != write_req_spr.end()) and ((*it_spr).ooo == ooo_engine));
+
+	      in_BYPASS_WRITE_SPR_VAL    [i]->write(spr_val);	      
+	      in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg);
+	      in_BYPASS_WRITE_SPR_DATA   [i]->write(spr_data);
+
+	      if (spr_val)
+		{
+		  LABEL(" * BYPASS_WRITE  [%d] - spr[%d][%d] <- 0x%x",i,spr_num_reg,ooo_engine,spr_data);
+
+// 		  can_spr_use [ooo_engine][spr_num_reg] = false;
+
+		  _spr     [spr_num_reg][ooo_engine] = spr_data;
+		  _spr_val [spr_num_reg][ooo_engine] = 1;
+		}
+
+	      if (it_spr != write_req_spr.end())
+		it_spr ++;
+	    }
+
+	  for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
+	    {
+	      Tcontext_t         ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0;
+	      Tgeneral_address_t num_reg    = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0;
+
+	      if (_param->_have_port_ooo_engine_id)
+              in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine);
+
+	      Tcontrol_t         val     = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0;
+	      Tgeneral_data_t    data    = range<Tgeneral_data_t>(rand(),_param->_size_general_data);
+	      
+	      val = (val // and can_gpr_use [ooo_engine][num_reg]
+		     and (it_gpr != write_req_gpr.end()));
+
+	      in_BYPASS_MEMORY_VAL    [i]->write(val);	      
+	      in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg);
+	      in_BYPASS_MEMORY_DATA   [i]->write(data);
+
+	      if (val)
+		{
+		  LABEL(" * BYPASS_MEMORY [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data);
+		  
+// 		  can_gpr_use [ooo_engine][num_reg] = false;
+
+		  _gpr     [num_reg][ooo_engine] = data;
+		  _gpr_val [num_reg][ooo_engine] = 1;
+		}
+
+	      if (it_gpr != write_req_gpr.end())
+		it_gpr ++;
+	    }
+
+	  SC_START(0); // to mealy function
+	  
+// 	  LABEL("Test     READ_UNIT_IN  : "+toString(in_READ_UNIT_IN_VAL->read())+","+toString(out_READ_UNIT_IN_ACK->read()));
+	  if (( in_READ_UNIT_IN_VAL->read() == 1) and
+	      (out_READ_UNIT_IN_ACK->read() == 1))
+	    {
+	      LABEL("Accepted READ_UNIT_IN  number : %d",request_in);
+	      request_in  ++;
+	    }
+
+	  for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
+	    {
+ 	      LABEL("Test     READ_UNIT_OUT %d : %d,%d",i,out_READ_UNIT_OUT_VAL[i]->read(),in_READ_UNIT_OUT_ACK[i]->read());
+	      if ((out_READ_UNIT_OUT_VAL [i]->read() == 1) and
+		  ( in_READ_UNIT_OUT_ACK [i]->read() == 1))
+		{
+		  Tpacket_t  packet_id;
+		  if (_param->_have_port_rob_ptr)
+		    packet_id = out_READ_UNIT_OUT_PACKET_ID [i]->read();
+		  else
+		    packet_id = 0;
+		  LABEL("Accepted READ_UNIT_OUT [%d] number : %d, request number : %d",i,packet_id,request_out);
+		  TEST(bool, request_out_wait [packet_id] , true);
+
+		  request_out ++;
+		  request_out_wait [packet_id] = false;
+
+		  Tcontext_t ooo_engine_id = _ooo_engine_id [packet_id];
+		  
+		  if (_param->_have_port_context_id)
+		  TEST(Tcontext_t        ,out_READ_UNIT_OUT_CONTEXT_ID   [i]->read(),(2*ooo_engine_id)%_param->_nb_context  );
+		  if (_param->_have_port_front_end_id)
+		  TEST(Tcontext_t        ,out_READ_UNIT_OUT_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end);
+		  if (_param->_have_port_ooo_engine_id)
+		  TEST(Tcontext_t        ,out_READ_UNIT_OUT_OOO_ENGINE_ID[i]->read(),ooo_engine_id);
+
+		  if (_read_ra [packet_id])
+		  TEST(Tgeneral_data_t   ,out_READ_UNIT_OUT_DATA_RA   [i]->read(),_gpr[_num_reg_ra[packet_id]][ooo_engine_id]);
+		  
+		  if (_read_rb [packet_id])
+		  TEST(Tgeneral_data_t   ,out_READ_UNIT_OUT_DATA_RB   [i]->read(),_gpr[_num_reg_rb[packet_id]][ooo_engine_id]);
+		  
+		  if (_read_rc [packet_id])
+		  TEST(Tspecial_data_t   ,out_READ_UNIT_OUT_DATA_RC   [i]->read(),_spr[_num_reg_rc[packet_id]][ooo_engine_id]);
+		}
+	    }
+	  
+	  SC_START(1);	  
+
+	  for (list<write_req_t>::iterator it = write_req_gpr.begin();
+	       it != write_req_gpr.end();
+	       )
+	    {
+	      if (_gpr_val [(*it).reg][(*it).ooo] == 1)
+		it = write_req_gpr.erase(it);
+	      else
+		it ++;
+	    }
+
+	  for (list<write_req_t>::iterator it = write_req_spr.begin();
+	       it != write_req_spr.end();
+	       )
+	    {
+	      if (_spr_val [(*it).reg][(*it).ooo] == 1)
+		it = write_req_spr.erase(it);
+	      else
+		it ++;
+	    }
+	}
+
+      for (uint32_t i=0; i<nb_request; i++)
+	TEST(bool, request_out_wait [i] , false);
     }
+  }
 
   /********************************************************
