Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 83)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 88)
@@ -22,4 +22,5 @@
   {
     log_begin(Context_State,FUNCTION);
+    log_function(Context_State,FUNCTION,_name.c_str());
 
     // -------------------------------------------------------------------
@@ -30,22 +31,36 @@
 	context_state_t state = reg_STATE [i];
 
-	internal_EVENT_VAL [i] = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
-				  (state == CONTEXT_STATE_KO_MISS_ADDR ) or
-				  (state == CONTEXT_STATE_KO_PSYNC_ADDR) or 
-				  (state == CONTEXT_STATE_KO_CSYNC_ADDR));
-
+        Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
+                                       (state == CONTEXT_STATE_KO_MISS_ADDR ) or
+                                       (state == CONTEXT_STATE_KO_PSYNC_ADDR) or 
+                                       (state == CONTEXT_STATE_KO_CSYNC_ADDR));
+        
+        // SR can't change in this cycle
+        // Exception Prefix High
+        Taddress_t address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
+        Taddress_t address_next     = reg_EVENT_ADDRESS_EPCR [i];
+        Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
+        Tcontrol_t is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
 	// excep : address exception
 	// miss  : address delay_slot, and address dest
 	// psync : address next
 	// csync : address next
-	PORT_WRITE(out_EVENT_VAL              [i], internal_EVENT_VAL     [i]);
-	PORT_WRITE(out_EVENT_ADDRESS          [i], reg_EVENT_ADDRESS      [i]);
-	PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], reg_EVENT_ADDRESS_EPCR [i]); 
-	PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]));
-	PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]));
+        internal_EVENT_VAL [i] = val;
+	PORT_WRITE(out_EVENT_VAL              [i], val);
+	PORT_WRITE(out_EVENT_ADDRESS          [i], address);
+	PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], address_next); 
+	PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
+	PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
+
+	log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
+	log_printf(TRACE,Context_State,FUNCTION,"    * VAL              : %d", val);
+	log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS          : %.8x (%.8x)", address     , address     <<2);
+	log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)", address_next, address_next<<2); 
+	log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
+	log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
       }
 
     // -------------------------------------------------------------------
-    // -----[ SPR ]-------------------------------------------------------
+    // -----[ SPR_EVENT ]-------------------------------------------------
     // -------------------------------------------------------------------
     for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -53,12 +68,12 @@
 	context_state_t state = reg_STATE [i];
 
-	internal_SPR_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
+	internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
 
-	PORT_WRITE(out_SPR_VAL       [i], internal_SPR_VAL           [i]);
-	PORT_WRITE(out_SPR_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
-	PORT_WRITE(out_SPR_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
-	PORT_WRITE(out_SPR_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
-	PORT_WRITE(out_SPR_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
-	PORT_WRITE(out_SPR_SR_TO_ESR [i], 1);
+	PORT_WRITE(out_SPR_EVENT_VAL       [i], internal_SPR_EVENT_VAL     [i]);
+	PORT_WRITE(out_SPR_EVENT_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
+	PORT_WRITE(out_SPR_EVENT_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
+	PORT_WRITE(out_SPR_EVENT_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
+	PORT_WRITE(out_SPR_EVENT_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
+	PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1);
       }
 
