Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Decod_library_clean
 
+local_clean			:
+
 include                         $(DIR_COMPONENT)/Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg	(revision 88)
@@ -1,8 +1,7 @@
 Decod
 1	1	*4	# nb_context           
-1	1	*4	# nb_inst_fetch        [0] [nb_context]
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
 1	1	*4	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-0	0	+1	# size_branch_update_prediction
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
 1	1	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg	(revision 88)
@@ -1,8 +1,7 @@
 Decod
 1	1	*4	# nb_context           
-4	16	*4	# nb_inst_fetch        [0] [nb_context]
-1	4 	*4	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-0	2	+1	# size_branch_update_prediction
+4	16	*4	# nb_inst_fetch                 [0] [nb_context]
+1	4 	*4	# nb_inst_decod         
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
 1	1	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg	(revision 88)
@@ -1,11 +1,13 @@
 Decod
 4	4	*4	# nb_context           
-1	1	*4	# nb_inst_fetch        [0] [nb_context]
-2	2	*4	# nb_inst_fetch        [1] [nb_context]
-4	4	*4	# nb_inst_fetch        [2] [nb_context]
-8	8	*4	# nb_inst_fetch        [3] [nb_context]
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
+2	2	*4	# nb_inst_fetch                 [1] [nb_context]
+4	4	*4	# nb_inst_fetch                 [2] [nb_context]
+8	8	*4	# nb_inst_fetch                 [3] [nb_context]
 1	8	*2	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-2	2	*2	# size_branch_update_prediction
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
+0	0	*2	# nb_branch_speculated          [1] [nb_context]
+1	1	*2	# nb_branch_speculated          [2] [nb_context]
+2	2	*2	# nb_branch_speculated          [3] [nb_context]
 1	4	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h	(revision 88)
@@ -32,4 +32,5 @@
   public : Ttype_t             _type                       ;
   public : Toperation_t        _operation                  ;
+  public : Tcontrol_t          _no_execute                 ;
   public : Tcontrol_t          _is_delay_slot              ;
   public : Tcontrol_t          _has_immediat               ;
@@ -46,4 +47,6 @@
   public : Tspecial_address_t  _num_reg_re                 ;
   public : Texception_t        _exception_use              ;
+  public : Texception_t        _exception_ifetch           ;
+  public : Texception_t        _exception_decod            ;
   public : Tevent_type_t       _context_event_type         ;
 
@@ -64,4 +67,5 @@
 		    Ttype_t             type                       ,
 		    Toperation_t        operation                  ,
+// 		    Tcontrol_t          no_execute                 ,
 		    Tcontrol_t          is_delay_slot              ,
 		    Tcontrol_t          has_immediat               ,
@@ -78,4 +82,6 @@
 		    Tspecial_address_t  num_reg_re                 ,
 		    Texception_t        exception_use              ,
+//                     Texception_t        exception_ifetch           ,
+//                     Texception_t        exception_decod            ,
 		    Tevent_type_t       context_event_type         )
     {
@@ -110,4 +116,8 @@
       _exception_use               = exception_use              ;
       _context_event_type          = context_event_type         ;
+
+      _no_execute                  = 0                          ;
+      _exception_ifetch            = EXCEPTION_IFETCH_NONE      ;
+      _exception_decod             = EXCEPTION_DECOD_NONE       ;
     }
   };
@@ -246,5 +256,5 @@
     0xe3caa309,x,y,z,
     BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
-    0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIV,false,
+    0,TYPE_DIV,OPERATION_DIV_L_DIV,false,
     0,0x0,1,10,1,20,0,0                 ,1,30,1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -265,5 +275,5 @@
     0xe3caa30a,x,y,z,
     BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
-    0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIVU,true,
+    0,TYPE_DIV,OPERATION_DIV_L_DIVU,true,
     0,0x0,1,10,1,20,0,0                 ,1,30,1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -622,5 +632,5 @@
     0xe3caa306,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -631,5 +641,5 @@
     0xb3ca03fa,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     1,0x3fa, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -640,5 +650,5 @@
     0xb3cafc06,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     1,0xfffffc06, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -649,5 +659,5 @@
     0xe3caa30b,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MULU,false,
+    TYPE_MUL,OPERATION_MUL_L_MULU,false,
     0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp	(revision 88)
@@ -9,5 +9,5 @@
 #include "Behavioural/Custom/include/Custom_example.h"
 
-#define NB_PARAMS 8
+#define NB_PARAMS 6
 
 void usage (int argc, char * argv[])
@@ -15,13 +15,12 @@
   err (_("<Usage> %s name_instance list_params.\n"),argv[0]);
   err (_("list_params is :\n"));
-  err (_(" * nb_context                                (uint32_t         )\n"));
-  err (_(" * nb_inst_fetch                [nb_context] (uint32_t         )\n"));
-  err (_(" * nb_inst_decod                             (uint32_t         )\n"));
-  err (_(" * nb_branch_speculated                      (uint32_t         )\n"));
-  err (_(" * size_branch_update_prediction             (uint32_t         )\n"));
-  err (_(" * nb_context_select                         (uint32_t         )\n"));
-  err (_(" * size_general_data                         (uint32_t         )\n"));
-  err (_(" * priority                                  (Tpriority_t      )\n"));
-  err (_(" * load_balancing                            (Tload_balancing_t)\n"));
+  err (_(" * nb_context                                 (uint32_t         )\n"));
+  err (_(" * nb_inst_fetch                 [nb_context] (uint32_t         )\n"));
+  err (_(" * nb_inst_decod                              (uint32_t         )\n"));
+  err (_(" * nb_branch_speculated          [nb_context] (uint32_t         )\n"));
+  err (_(" * nb_context_select                          (uint32_t         )\n"));
+  err (_(" * size_general_data                          (uint32_t         )\n"));
+  err (_(" * priority                                   (Tpriority_t      )\n"));
+  err (_(" * load_balancing                             (Tload_balancing_t)\n"));
 
   exit (1);
@@ -42,14 +41,21 @@
   uint32_t            _nb_context           = fromString<uint32_t         >(argv[x++]);
 
-  if (argc != static_cast<int>(2+NB_PARAMS+_nb_context))
+  if (argc != static_cast<int>(2+NB_PARAMS+2*_nb_context))
     usage (argc, argv);
   
-  uint32_t          * _nb_inst_fetch        = new uint32_t [_nb_context];
+  uint32_t          * _nb_inst_fetch                = new uint32_t [_nb_context];
   for (uint32_t i=0;i<_nb_context; i++)
     _nb_inst_fetch [i] = fromString<uint32_t>(argv[x++]);
 
   uint32_t            _nb_inst_decod                = fromString<uint32_t         >(argv[x++]);
-  uint32_t            _nb_branch_speculated         = fromString<uint32_t         >(argv[x++]);
-  uint32_t            _size_branch_update_prediction= fromString<uint32_t         >(argv[x++]);
+
+  uint32_t          * _nb_branch_speculated         = new uint32_t [_nb_context];
+  for (uint32_t i=0;i<_nb_context; i++)
+    _nb_branch_speculated [i] = fromString<uint32_t>(argv[x++]);
+
+//   uint32_t          * _size_branch_update_prediction= new uint32_t [_nb_context];
+//   for (uint32_t i=0;i<_nb_context; i++)
+//     _size_branch_update_prediction[i] = fromString<uint32_t>(argv[x++]);
+
   uint32_t            _nb_context_select            = fromString<uint32_t         >(argv[x++]);
   uint32_t            _size_general_data            = fromString<uint32_t         >(argv[x++]);
@@ -63,5 +69,5 @@
       
       for (uint32_t j=0; j<NB_INSTRUCTION; j++)
-	_instruction_implemeted [i][j] = true;
+        _instruction_implemeted [i][j] = true;
     }
 
@@ -70,16 +76,17 @@
     {
       morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters
-	(_nb_context                   ,
-	 _nb_inst_fetch                ,
-	 _nb_inst_decod                ,
-	 _nb_branch_speculated         ,
-	 _size_branch_update_prediction,
-	 _nb_context_select            ,
-	 _size_general_data            ,
-	 _priority                     ,
-	 _load_balancing               ,
-	 _instruction_implemeted       ,
-	 &(morpheo::behavioural::custom::example_get_custom_information)
-	 );
+        (_nb_context                   ,
+         _nb_inst_fetch                ,
+         _nb_inst_decod                ,
+         _nb_branch_speculated         ,
+//          _size_branch_update_prediction,
+         _nb_context_select            ,
+         _size_general_data            ,
+         _priority                     ,
+         _load_balancing               ,
+         _instruction_implemeted       ,
+         &(morpheo::behavioural::custom::example_get_custom_information),
+         true // is_toplevel
+         );
       
       msg(_("%s"),param->print(1).c_str());
@@ -100,4 +107,7 @@
   delete _nb_inst_fetch;
   delete _instruction_implemeted;
+  delete _nb_branch_speculated;
+//   delete _size_branch_update_prediction;
+
   return (_return);
 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 88)
@@ -22,6 +22,16 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Decod * _Decod = new Decod 
@@ -31,5 +41,5 @@
 #endif
      _param,
-     USE_ALL);
+     _usage);
   
 #ifdef SYSTEMC
@@ -42,7 +52,7 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC2_SC_SIGNAL( in_IFETCH_VAL                         ," in_IFETCH_VAL                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  ALLOC2_SC_SIGNAL(out_IFETCH_ACK                         ,"out_IFETCH_ACK                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION                 ," in_IFETCH_INSTRUCTION                 ",Tinstruction_t     ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
+  ALLOC2_SC_SIGNAL( in_IFETCH_VAL                         ," in_IFETCH_VAL                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  ALLOC2_SC_SIGNAL(out_IFETCH_ACK                         ,"out_IFETCH_ACK                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION                 ," in_IFETCH_INSTRUCTION                 ",Tinstruction_t     ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
   ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID                  ," in_IFETCH_CONTEXT_ID                  ",Tcontext_t         ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS                     ," in_IFETCH_ADDRESS                     ",Tgeneral_address_t ,_param->_nb_context);
@@ -51,4 +61,6 @@
   ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE                ," in_IFETCH_BRANCH_STATE                ",Tbranch_state_t    ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t  ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION                   ," in_IFETCH_EXCEPTION                   ",Texception_t       ,_param->_nb_context);
+
   ALLOC1_SC_SIGNAL(out_DECOD_VAL                          ,"out_DECOD_VAL                          ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_DECOD_ACK                          ," in_DECOD_ACK                          ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -57,4 +69,5 @@
   ALLOC1_SC_SIGNAL(out_DECOD_TYPE                         ,"out_DECOD_TYPE                         ",Ttype_t            ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_OPERATION                    ,"out_DECOD_OPERATION                    ",Toperation_t       ,_param->_nb_inst_decod);
+  ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE                   ,"out_DECOD_NO_EXECUTE                   ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,"out_DECOD_IS_DELAY_SLOT                ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_data_t    ,_param->_nb_inst_decod);
@@ -72,4 +85,5 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE                   ,"out_DECOD_NUM_REG_RE                   ",Tspecial_address_t ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE                ,"out_DECOD_EXCEPTION_USE                ",Texception_t       ,_param->_nb_inst_decod);
+  ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Texception_t       ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -89,4 +103,5 @@
   ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK                  ," in_CONTEXT_EVENT_ACK                  ",Tcontrol_t         );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID           ,"out_CONTEXT_EVENT_CONTEXT_ID           ",Tcontext_t         );
+  ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH                ,"out_CONTEXT_EVENT_DEPTH                ",Tdepth_t           );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE                 ,"out_CONTEXT_EVENT_TYPE                 ",Tevent_type_t      );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT        ,"out_CONTEXT_EVENT_IS_DELAY_SLOT        ",Tcontrol_t         );
@@ -103,16 +118,23 @@
   (*(_Decod->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL                         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK                         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION                 ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
+  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL                         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK                         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION                 ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
   if (_param->_have_port_context_id)
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID                  ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS                     ,_param->_nb_context);
 //   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT                ,_param->_nb_context);
-  if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR             ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE                ,_param->_nb_context);
-  if (_param->_have_port_branch_update_prediction_id)
-  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION                   ,_param->_nb_context);
+
+  for (uint32_t i=0; i<_param->_nb_context; i++)
+    {
+      if (_param->_have_port_inst_ifetch_ptr)
+        INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
+//       if (_param->_have_port_branch_update_prediction_id)
+      if (_param->_have_port_depth)
+        INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
+    }
+
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL                          ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK                          ,_param->_nb_inst_decod);
@@ -123,4 +145,5 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE                         ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION                    ,_param->_nb_inst_decod);
+  INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS                      ,_param->_nb_inst_decod);
@@ -138,4 +161,5 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE                ,_param->_nb_inst_decod);
+  INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION                    ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL                        ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK                        ,_param->_nb_inst_decod);
@@ -144,5 +168,6 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR      ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE               ,_param->_nb_inst_decod);
-  if (_param->_have_port_branch_update_prediction_id)
+//   if (_param->_have_port_branch_update_prediction_id)
+  if (_param->_have_port_depth)
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION           ,_param->_nb_inst_decod);
@@ -153,10 +178,13 @@
 //   INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE               ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE               ,_param->_nb_context);
-  if (_param->_have_port_depth)
-  INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH                      ,_param->_nb_context);
+  for (uint32_t i=0; i<_param->_nb_context; i++)
+    if (_param->_have_port_depth)
+      INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL                  );
   INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK                  );
   if (_param->_have_port_context_id)
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID           );
+  if (_param->_have_port_depth)
+  INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH                );
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE                 );
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT        );
@@ -236,4 +264,5 @@
 		      if (_param->_have_port_inst_ifetch_ptr)
 		      in_IFETCH_INST_IFETCH_PTR [i]->write(0);
+		      in_IFETCH_EXCEPTION       [i]->write(EXCEPTION_IFETCH_NONE);
 
 		      // Alignement
@@ -336,5 +365,6 @@
 		    TEST(Tcontrol_t         , out_PREDICT_MATCH_INST_IFETCH_PTR       [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
 		    TEST(Tbranch_state_t    , out_PREDICT_BRANCH_STATE                [i]->read(), request [context].front()._branch_state               );
-		    if (_param->_have_port_branch_update_prediction_id)
+// 		    if (_param->_have_port_branch_update_prediction_id)
+ 		    if (_param->_have_port_depth)
 		    TEST(Tprediction_ptr_t  , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
 		    TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION            [i]->read(), request [context].front()._branch_condition           );
@@ -358,4 +388,6 @@
 		    if (_param->_have_port_context_id)
 		    TEST(Tcontext_t     ,out_CONTEXT_EVENT_CONTEXT_ID   ->read(), context);
+		    if (_param->_have_port_depth )
+		    TEST(Tcontext_t     ,out_CONTEXT_EVENT_DEPTH        ->read(), request [context].front()._depth        );
 		    TEST(Tevent_type_t  ,out_CONTEXT_EVENT_TYPE         ->read(), request [context].front()._context_event_type);
 		    TEST(Tcontrol_t     ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
@@ -403,4 +435,5 @@
   delete []  in_IFETCH_BRANCH_STATE                ;
   delete []  in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
+  delete []  in_IFETCH_EXCEPTION                   ;
   
   delete [] out_DECOD_VAL                          ;
@@ -410,4 +443,5 @@
   delete [] out_DECOD_TYPE                         ;
   delete [] out_DECOD_OPERATION                    ;
+  delete [] out_DECOD_NO_EXECUTE                   ;
   delete [] out_DECOD_IS_DELAY_SLOT                ;
   delete [] out_DECOD_ADDRESS                      ;
@@ -425,4 +459,5 @@
   delete [] out_DECOD_NUM_REG_RE                   ;
   delete [] out_DECOD_EXCEPTION_USE                ;
+  delete [] out_DECOD_EXCEPTION                    ;
   
   delete [] out_PREDICT_VAL                        ;
@@ -445,4 +480,5 @@
   delete     in_CONTEXT_EVENT_ACK                  ;
   delete    out_CONTEXT_EVENT_CONTEXT_ID           ;
+  delete    out_CONTEXT_EVENT_DEPTH                ;
   delete    out_CONTEXT_EVENT_TYPE                 ;
   delete    out_CONTEXT_EVENT_IS_DELAY_SLOT        ;
