Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h	(revision 88)
@@ -39,4 +39,5 @@
     Ttype_t             _type              ;
     Toperation_t        _operation         ;
+    Tcontrol_t          _no_execute        ;
     Tcontrol_t          _has_immediat      ;
     Tgeneral_data_t     _immediat          ;
@@ -52,4 +53,5 @@
     Tspecial_address_t  _num_reg_re        ;
     Texception_t        _exception_use     ;
+    Texception_t        _exception         ;
     Tbranch_condition_t _branch_condition  ;
 //     Tcontrol_t          _branch_stack_write;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 88)
@@ -14,4 +14,5 @@
 #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h"
 #include "Behavioural/include/Constants.h"
+#include "Behavioural/include/Operation.h"
 
 namespace morpheo {
@@ -124,4 +125,5 @@
 	
     inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION;
+    inst->_exception     = EXCEPTION_ILLEGAL_INSTRUCTION;
 
     if (inst->_is_delay_slot)
@@ -138,16 +140,16 @@
 
     uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
-
-    inst->_type = TYPE_CUSTOM;
+    
     switch (opcod)
       {
-      case OPCOD_L_CUST1 : {inst->_operation = OPERATION_CUSTOM_L_1; break;}
-      case OPCOD_L_CUST2 : {inst->_operation = OPERATION_CUSTOM_L_2; break;}
-      case OPCOD_L_CUST3 : {inst->_operation = OPERATION_CUSTOM_L_3; break;}
-      case OPCOD_L_CUST4 : {inst->_operation = OPERATION_CUSTOM_L_4; break;}
-      case OPCOD_L_CUST5 : {inst->_operation = OPERATION_CUSTOM_L_5; break;}
-      case OPCOD_L_CUST6 : {inst->_operation = OPERATION_CUSTOM_L_6; break;}
-      case OPCOD_L_CUST7 : {inst->_operation = OPERATION_CUSTOM_L_7; break;}
-      case OPCOD_L_CUST8 : {inst->_operation = OPERATION_CUSTOM_L_8; break;}
+      case OPCOD_L_CUST1 : {inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation; break;}
+      case OPCOD_L_CUST2 : {inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation; break;}
+      case OPCOD_L_CUST3 : {inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation; break;}
+      case OPCOD_L_CUST4 : {inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation; break;}
+      case OPCOD_L_CUST5 : {inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation; break;}
+      case OPCOD_L_CUST6 : {inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation; break;}
+      case OPCOD_L_CUST7 : {inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation; break;}
+      case OPCOD_L_CUST8 : {inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation; break;}
+
       default            : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));}
       }
@@ -164,9 +166,8 @@
     uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
 
-    inst->_type = TYPE_CUSTOM;
     switch (opcod)
       {
-//       case OPCOD_LF_CUST1_D : {inst->_operation = OPERATION_CUSTOM_LF_1_D; break;}
-//       case OPCOD_LF_CUST1_S : {inst->_operation = OPERATION_CUSTOM_LF_1_S; break;}
+//       case OPCOD_LF_CUST1_D : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation; break;}
+//       case OPCOD_LF_CUST1_S : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation; break;}
       default               : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));}
       }
@@ -183,11 +184,10 @@
     uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
 
-    inst->_type = TYPE_CUSTOM;
     switch (opcod)
       {
-//       case OPCOD_LV_CUST1 : {inst->_operation = OPERATION_CUSTOM_LV_1; break;}
-//       case OPCOD_LV_CUST2 : {inst->_operation = OPERATION_CUSTOM_LV_2; break;}
-//       case OPCOD_LV_CUST3 : {inst->_operation = OPERATION_CUSTOM_LV_3; break;}
-//       case OPCOD_LV_CUST4 : {inst->_operation = OPERATION_CUSTOM_LV_4; break;}
+//       case OPCOD_LV_CUST1 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation; break;}
+//       case OPCOD_LV_CUST2 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation; break;}
+//       case OPCOD_LV_CUST3 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation; break;}
+//       case OPCOD_LV_CUST4 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation; break;}
       default             : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));}
       }
@@ -252,6 +252,6 @@
   {
     log_printf(TRACE,Decod,"instruction_l_add","  * instruction   : l.add");
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_ADD;
+    inst->_type               = instruction_information(INSTRUCTION_L_ADD)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -267,8 +267,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -278,6 +280,6 @@
     log_printf(TRACE,Decod,"instruction_l_addc","  * instruction   : l.addc");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_ADD;
+    inst->_type               = instruction_information(INSTRUCTION_L_ADDC)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -293,8 +295,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -304,6 +308,6 @@
     log_printf(TRACE,Decod,"instruction_l_addi","  * instruction   : l.addi");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_ADD;
+    inst->_type               = instruction_information(INSTRUCTION_L_ADDI)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -319,8 +323,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -330,6 +336,6 @@
     log_printf(TRACE,Decod,"instruction_l_addic","  * instruction   : l.addic");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_ADD;
+    inst->_type               = instruction_information(INSTRUCTION_L_ADDIC)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -345,8 +351,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -356,23 +364,25 @@
     log_printf(TRACE,Decod,"instruction_l_and","  * instruction   : l.and");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_AND;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_AND)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -382,6 +392,6 @@
     log_printf(TRACE,Decod,"instruction_l_andi","  * instruction   : l.andi");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_AND;
+    inst->_type               = instruction_information(INSTRUCTION_L_ANDI)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -397,8 +407,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -408,8 +420,9 @@
     log_printf(TRACE,Decod,"instruction_l_bf","  * instruction   : l.bf");
 
-    Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
-
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_L_TEST_F;
+    Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
+                                                   );
+
+    inst->_type               = instruction_information(INSTRUCTION_L_BF)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F;
     inst->_has_immediat       = 1;
     inst->_immediat           = address_next;
@@ -425,4 +438,5 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
     inst->_branch_condition   = BRANCH_CONDITION_FLAG_SET;
 //  inst->_branch_stack_write = 0;
@@ -430,4 +444,5 @@
     inst->_branch_direction   = range<Tgeneral_data_t   >(inst->_instruction,25,25);
     inst->_address_next       = address_next;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -437,8 +452,9 @@
     log_printf(TRACE,Decod,"instruction_l_bnf","  * instruction   : l.bnf");
 
-    Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
-
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_L_TEST_NF;
+    Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
+                                                   );
+
+    inst->_type               = instruction_information(INSTRUCTION_L_BNF)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF;
     inst->_has_immediat       = 1;
     inst->_immediat           = address_next;
@@ -454,8 +470,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
     inst->_branch_condition   = BRANCH_CONDITION_FLAG_UNSET;
 //  inst->_branch_stack_write = 0;
     inst->_branch_direction   = range<Tgeneral_data_t   >(inst->_instruction,25,25);
     inst->_address_next       = address_next;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -465,6 +483,6 @@
     log_printf(TRACE,Decod,"instruction_l_cmov","  * instruction   : l.cmov");
 
-    inst->_type               = TYPE_MOVE;
-    inst->_operation          = OPERATION_MOVE_L_CMOV;
+    inst->_type               = instruction_information(INSTRUCTION_L_CMOV)._type     ; //TYPE_MOVE;
+    inst->_operation          = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -480,8 +498,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -497,6 +517,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_CSYNC;
+    inst->_type               = instruction_information(INSTRUCTION_L_CSYNC)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -512,8 +532,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_CSYNC;
       }
@@ -533,6 +555,6 @@
     log_printf(TRACE,Decod,"instruction_l_div","  * instruction   : l.div");
 
-    inst->_type               = TYPE_MUL_DIV;
-    inst->_operation          = OPERATION_MUL_DIV_L_DIV;
+    inst->_type               = instruction_information(INSTRUCTION_L_DIV)._type     ; //TYPE_DIV;
+    inst->_operation          = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -548,8 +570,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -559,6 +583,6 @@
     log_printf(TRACE,Decod,"instruction_l_divu","  * instruction   : l.divu");
 
-    inst->_type               = TYPE_MUL_DIV;
-    inst->_operation          = OPERATION_MUL_DIV_L_DIVU;
+    inst->_type               = instruction_information(INSTRUCTION_L_DIVU)._type     ; //TYPE_DIV;
+    inst->_operation          = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -574,8 +598,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -585,6 +611,6 @@
     log_printf(TRACE,Decod,"instruction_l_extbs","  * instruction   : l.extbs");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTBS)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = 8;
@@ -600,8 +626,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -611,6 +639,6 @@
     log_printf(TRACE,Decod,"instruction_l_extbz","  * instruction   : l.extbz");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTBZ)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = 8;
@@ -626,8 +654,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -637,6 +667,6 @@
     log_printf(TRACE,Decod,"instruction_l_exths","  * instruction   : l.exths");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTHS)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = 16;
@@ -652,8 +682,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -663,6 +695,6 @@
     log_printf(TRACE,Decod,"instruction_l_exthz","  * instruction   : l.exthz");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTHZ)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = 16;
@@ -678,8 +710,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -689,6 +723,6 @@
     log_printf(TRACE,Decod,"instruction_l_extws","  * instruction   : l.extws");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTWS)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = 32;
@@ -704,8 +738,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -715,6 +751,6 @@
     log_printf(TRACE,Decod,"instruction_l_extwz","  * instruction   : l.extwz");
 
-    inst->_type               = TYPE_EXTEND;
-    inst->_operation          = OPERATION_EXTEND_L_EXTEND_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_EXTWZ)._type     ; //TYPE_EXTEND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = 32;
@@ -730,8 +766,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -741,23 +779,25 @@
     log_printf(TRACE,Decod,"instruction_l_ff1","  * instruction   : l.ff1");
 
-    inst->_type               = TYPE_FIND;
-    inst->_operation          = OPERATION_FIND_L_FF1;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_FF1)._type     ; //TYPE_FIND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+//  inst->_num_reg_rb         = ;
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -767,23 +807,25 @@
     log_printf(TRACE,Decod,"instruction_l_fl1","  * instruction   : l.fl1");
 
-    inst->_type               = TYPE_FIND;
-    inst->_operation          = OPERATION_FIND_L_FL1;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_FL1)._type     ; //TYPE_FIND;
+    inst->_operation          = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+//  inst->_num_reg_rb         = ;
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -793,6 +835,6 @@
     log_printf(TRACE,Decod,"instruction_l_j","  * instruction   : l.j");
 
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_NONE;
+    inst->_type               = instruction_information(INSTRUCTION_L_J)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -808,8 +850,11 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
     inst->_branch_condition   = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK;
 //  inst->_branch_stack_write = 0;
     inst->_branch_direction   = 1;
-    inst->_address_next       = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
+    inst->_address_next       = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
+                                                               );
+    inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -819,6 +864,6 @@
     log_printf(TRACE,Decod,"instruction_l_jal","  * instruction   : l.jal");
 
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_L_JALR;
+    inst->_type               = instruction_information(INSTRUCTION_L_JAL)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 1;
     inst->_immediat           = inst->_address_next+1;
@@ -834,8 +879,11 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
     inst->_branch_condition   = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump
 //  inst->_branch_stack_write = 1;
     inst->_branch_direction   = 1;
-    inst->_address_next       = inst->_address+(EXTENDS(inst->_instruction,26)<<2);
+    inst->_address_next       = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
+                                                );
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -853,6 +901,6 @@
     else
       {
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_L_JALR;
+    inst->_type               = instruction_information(INSTRUCTION_L_JALR)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -868,4 +916,5 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER;
     inst->_branch_condition   = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK;
@@ -873,4 +922,5 @@
     inst->_branch_direction   = 1;
 //  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
       }
@@ -881,6 +931,6 @@
     log_printf(TRACE,Decod,"instruction_l_jr","  * instruction   : l.jr");
 
-    inst->_type               = TYPE_BRANCH;
-    inst->_operation          = OPERATION_BRANCH_L_JALR;
+    inst->_type               = instruction_information(INSTRUCTION_L_JR)._type     ; //TYPE_BRANCH;
+    inst->_operation          = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -896,8 +946,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
     inst->_branch_condition   = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK;
 //  inst->_branch_stack_write = 0;
     inst->_branch_direction   = 1;
 //  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -907,6 +959,6 @@
     log_printf(TRACE,Decod,"instruction_l_lbs","  * instruction   : l.lbs");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_8_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_LBS)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -922,8 +974,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -933,6 +987,6 @@
     log_printf(TRACE,Decod,"instruction_l_lbz","  * instruction   : l.lbz");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_8_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_LBZ)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -948,8 +1002,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -959,6 +1015,6 @@
     log_printf(TRACE,Decod,"instruction_l_ld","  * instruction   : l.ld");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_64_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_LD)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -974,8 +1030,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -985,6 +1043,6 @@
     log_printf(TRACE,Decod,"instruction_l_lhs","  * instruction   : l.lhs");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_16_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_LHS)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1000,8 +1058,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1011,6 +1071,6 @@
     log_printf(TRACE,Decod,"instruction_l_lhz","  * instruction   : l.lhz");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_16_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_LHZ)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1026,8 +1086,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1037,6 +1099,6 @@
     log_printf(TRACE,Decod,"instruction_l_lws","  * instruction   : l.lws");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_32_S;
+    inst->_type               = instruction_information(INSTRUCTION_L_LWS)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1052,8 +1114,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1063,6 +1127,6 @@
     log_printf(TRACE,Decod,"instruction_l_lwz","  * instruction   : l.lwz");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_LOAD_32_Z;
+    inst->_type               = instruction_information(INSTRUCTION_L_LWZ)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1078,8 +1142,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1089,23 +1155,25 @@
     log_printf(TRACE,Decod,"instruction_l_mac","  * instruction   : l.mac");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MAC;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_type               = instruction_information(INSTRUCTION_L_MAC)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 0;
+//  inst->_num_reg_rd         = ;
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
   }
@@ -1115,6 +1183,6 @@
     log_printf(TRACE,Decod,"instruction_l_maci","  * instruction   : l.maci");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MAC;
+    inst->_type               = instruction_information(INSTRUCTION_L_MACI)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -1131,8 +1199,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
   }
@@ -1148,6 +1218,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MACRC;
+    inst->_type               = instruction_information(INSTRUCTION_L_MACRC)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1163,8 +1233,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
       }
@@ -1175,6 +1247,6 @@
     log_printf(TRACE,Decod,"instruction_l_mfspr","  * instruction   : l.mfspr");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MFSPR;
+    inst->_type               = instruction_information(INSTRUCTION_L_MFSPR)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -1190,8 +1262,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
   }
@@ -1201,6 +1275,6 @@
     log_printf(TRACE,Decod,"instruction_l_movhi","  * instruction   : l.movhi");
 
-    inst->_type               = TYPE_MOVE;
-    inst->_operation          = OPERATION_MOVE_L_MOVHI;
+    inst->_type               = instruction_information(INSTRUCTION_L_MOVHI)._type     ; //TYPE_MOVE;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -1216,8 +1290,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1227,23 +1303,25 @@
     log_printf(TRACE,Decod,"instruction_l_msb","  * instruction   : l.msb");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MSB;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_type               = instruction_information(INSTRUCTION_L_MSB)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 0;
+//  inst->_num_reg_rd         = ;
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
   }
@@ -1259,6 +1337,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MSYNC;
+    inst->_type               = instruction_information(INSTRUCTION_L_MSYNC)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1274,8 +1352,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_MSYNC;
       }
@@ -1286,6 +1366,6 @@
     log_printf(TRACE,Decod,"instruction_l_mtspr","  * instruction   : l.mtspr");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_MTSPR;
+    inst->_type               = instruction_information(INSTRUCTION_L_MTSPR)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -1302,8 +1382,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
   }
@@ -1313,6 +1395,6 @@
     log_printf(TRACE,Decod,"instruction_l_mul","  * instruction   : l.mul");
 
-    inst->_type               = TYPE_MUL_DIV;
-    inst->_operation          = OPERATION_MUL_DIV_L_MUL;
+    inst->_type               = instruction_information(INSTRUCTION_L_MUL)._type     ; //TYPE_MUL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1328,8 +1410,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1339,6 +1423,6 @@
     log_printf(TRACE,Decod,"instruction_l_muli","  * instruction   : l.muli");
 
-    inst->_type               = TYPE_MUL_DIV;
-    inst->_operation          = OPERATION_MUL_DIV_L_MUL;
+    inst->_type               = instruction_information(INSTRUCTION_L_MULI)._type     ; //TYPE_MUL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1354,8 +1438,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1365,6 +1451,6 @@
     log_printf(TRACE,Decod,"instruction_l_mulu","  * instruction   : l.mulu");
 
-    inst->_type               = TYPE_MUL_DIV;
-    inst->_operation          = OPERATION_MUL_DIV_L_MULU;
+    inst->_type               = instruction_information(INSTRUCTION_L_MULU)._type     ; //TYPE_MUL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1380,8 +1466,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1391,6 +1479,6 @@
     log_printf(TRACE,Decod,"instruction_l_nop","  * instruction   : l.nop");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_NOP;
+    inst->_type               = instruction_information(INSTRUCTION_L_NOP)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP;
 //  inst->_has_immediat       = 1;
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -1408,8 +1496,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1419,23 +1509,25 @@
     log_printf(TRACE,Decod,"instruction_l_or","  * instruction   : l.or");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_OR;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_OR)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1445,6 +1537,6 @@
     log_printf(TRACE,Decod,"instruction_l_ori","  * instruction   : l.ori");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_OR;
+    inst->_type               = instruction_information(INSTRUCTION_L_ORI)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -1460,8 +1552,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1477,6 +1571,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_PSYNC;
+    inst->_type               = instruction_information(INSTRUCTION_L_PSYNC)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1492,8 +1586,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_PSYNC;
       }
@@ -1504,6 +1600,6 @@
     log_printf(TRACE,Decod,"instruction_l_rfe","  * instruction   : l.rfe");
 
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_RFE;
+    inst->_type               = instruction_information(INSTRUCTION_L_RFE)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1519,8 +1615,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
   }
@@ -1530,23 +1628,25 @@
     log_printf(TRACE,Decod,"instruction_l_ror","  * instruction   : l.ror");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_ROR;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_ROR)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1556,6 +1656,6 @@
     log_printf(TRACE,Decod,"instruction_l_rori","  * instruction   : l.rori");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_ROR;
+    inst->_type               = instruction_information(INSTRUCTION_L_RORI)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR;
     inst->_has_immediat       = 1;
     inst->_immediat           = range<Tgeneral_data_t   >(inst->_instruction, 5, 0);
@@ -1571,8 +1671,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1582,6 +1684,6 @@
     log_printf(TRACE,Decod,"instruction_l_sb","  * instruction   : l.sb");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_STORE_8;
+    inst->_type               = instruction_information(INSTRUCTION_L_SB)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -1598,8 +1700,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1609,6 +1713,6 @@
     log_printf(TRACE,Decod,"instruction_l_sb","  * instruction   : l.sb");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_STORE_64;
+    inst->_type               = instruction_information(INSTRUCTION_L_SD)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -1625,8 +1729,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1636,6 +1742,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfeq","  * instruction   : l.sfeq");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFEQ;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFEQ)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1651,8 +1757,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1662,6 +1770,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfeqi","  * instruction   : l.sfeqi");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFEQ;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFEQI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1677,8 +1785,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1688,6 +1798,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfges","  * instruction   : l.sfges");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGES;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGES)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1703,8 +1813,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1714,6 +1826,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgesi","  * instruction   : l.sfgesi");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGES;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGESI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1729,8 +1841,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1740,6 +1854,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgeu","  * instruction   : l.sfgeu");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGEU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGEU)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1755,8 +1869,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1766,6 +1882,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgeui","  * instruction   : l.sfgeui");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGEU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGEUI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1781,8 +1897,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1792,6 +1910,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgts","  * instruction   : l.sfgts");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGTS;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGTS)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1807,8 +1925,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1818,6 +1938,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgtsi","  * instruction   : l.sfgtsi");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGTS;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGTSI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1833,8 +1953,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1844,6 +1966,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgtu","  * instruction   : l.sfgtu");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGTU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGTU)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1859,8 +1981,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1870,6 +1994,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfgtui","  * instruction   : l.sfgtui");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFGTU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFGTUI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1885,8 +2009,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1896,6 +2022,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfles","  * instruction   : l.sfles");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLES;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLES)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1911,8 +2037,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1922,6 +2050,6 @@
     log_printf(TRACE,Decod,"instruction_l_sflesi","  * instruction   : l.sflesi");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLES;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLESI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1937,8 +2065,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1948,6 +2078,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfleu","  * instruction   : l.sfleu");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLEU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLEU)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -1963,8 +2093,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -1974,6 +2106,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfleui","  * instruction   : l.sfleui");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLEU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLEUI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -1989,8 +2121,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2000,6 +2134,6 @@
     log_printf(TRACE,Decod,"instruction_l_sflts","  * instruction   : l.sflts");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLTS;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLTS)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -2015,8 +2149,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2026,6 +2162,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfltsi","  * instruction   : l.sfltsi");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLTS;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLTSI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -2041,8 +2177,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2052,6 +2190,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfltu","  * instruction   : l.sfltu");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLTU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLTU)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -2067,8 +2205,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2078,6 +2218,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfltui","  * instruction   : l.sfltui");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFLTU;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFLTUI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -2093,8 +2233,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2104,6 +2246,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfne","  * instruction   : l.sfne");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFNE;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFNE)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -2119,8 +2261,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2130,6 +2274,6 @@
     log_printf(TRACE,Decod,"instruction_l_sfnei","  * instruction   : l.sfnei");
 
-    inst->_type               = TYPE_TEST;
-    inst->_operation          = OPERATION_TEST_L_SFNE;
+    inst->_type               = instruction_information(INSTRUCTION_L_SFNEI)._type     ; //TYPE_TEST;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -2145,8 +2289,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2156,6 +2302,6 @@
     log_printf(TRACE,Decod,"instruction_l_sh","  * instruction   : l.sh");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_STORE_16;
+    inst->_type               = instruction_information(INSTRUCTION_L_SH)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -2172,8 +2318,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2183,23 +2331,25 @@
     log_printf(TRACE,Decod,"instruction_l_sll","  * instruction   : l.sll");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SLL;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_SLL)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2209,6 +2359,6 @@
     log_printf(TRACE,Decod,"instruction_l_slli","  * instruction   : l.slli");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SLL;
+    inst->_type               = instruction_information(INSTRUCTION_L_SLLI)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL;
     inst->_has_immediat       = 1;
     inst->_immediat           = range<Tgeneral_data_t   >(inst->_instruction, 5, 0);
@@ -2224,8 +2374,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2235,23 +2387,25 @@
     log_printf(TRACE,Decod,"instruction_l_sra","  * instruction   : l.sra");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SRA;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_SRA)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2261,6 +2415,6 @@
     log_printf(TRACE,Decod,"instruction_l_srai","  * instruction   : l.srai");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SRA;
+    inst->_type               = instruction_information(INSTRUCTION_L_SRAI)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA;
     inst->_has_immediat       = 1;
     inst->_immediat           = range<Tgeneral_data_t   >(inst->_instruction, 5, 0);
@@ -2276,8 +2430,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2287,23 +2443,25 @@
     log_printf(TRACE,Decod,"instruction_l_srl","  * instruction   : l.srl");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SRL;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_SRL)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2313,6 +2471,6 @@
     log_printf(TRACE,Decod,"instruction_l_srli","  * instruction   : l.srli");
 
-    inst->_type               = TYPE_SHIFT;
-    inst->_operation          = OPERATION_SHIFT_L_SRL;
+    inst->_type               = instruction_information(INSTRUCTION_L_SRLI)._type     ; //TYPE_SHIFT;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL;
     inst->_has_immediat       = 1;
     inst->_immediat           = range<Tgeneral_data_t   >(inst->_instruction, 5, 0);
@@ -2328,8 +2486,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2339,6 +2499,6 @@
     log_printf(TRACE,Decod,"instruction_l_sub","  * instruction   : l.sub");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_SUB;
+    inst->_type               = instruction_information(INSTRUCTION_L_SUB)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB;
     inst->_has_immediat       = 0;
 //  inst->_immediat           = ;
@@ -2354,8 +2514,10 @@
     inst->_num_reg_re         = SPR_LOGIC_SR_CY_OV;
     inst->_exception_use      = EXCEPTION_USE_RANGE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2365,6 +2527,6 @@
     log_printf(TRACE,Decod,"instruction_l_sw","  * instruction   : l.sw");
 
-    inst->_type               = TYPE_MEMORY;
-    inst->_operation          = OPERATION_MEMORY_STORE_32;
+    inst->_type               = instruction_information(INSTRUCTION_L_SW)._type     ; //TYPE_MEMORY;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(((range<Tgeneral_data_t   >(inst->_instruction,25,21)<<11)|
@@ -2381,8 +2543,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2398,6 +2562,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_SYS;
+    inst->_type               = instruction_information(INSTRUCTION_L_SYS)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS;
 //  inst->_has_immediat       = 1;
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -2415,4 +2579,5 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_SYSCALL;
+    inst->_exception          = EXCEPTION_SYSCALL;
 //  inst->_branch_condition   = ;
 //  inst->_branch_stack_write = ;
@@ -2426,4 +2591,5 @@
 
 //  inst->_address_next       = ; // don't change
+    inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_EXCEPTION;
       }
@@ -2440,6 +2606,6 @@
     else
       {
-    inst->_type               = TYPE_SPECIAL;
-    inst->_operation          = OPERATION_SPECIAL_L_TRAP;
+    inst->_type               = instruction_information(INSTRUCTION_L_TRAP)._type     ; //TYPE_SPECIAL;
+    inst->_operation          = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
@@ -2455,8 +2621,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_TRAP;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
       }
@@ -2467,23 +2635,25 @@
     log_printf(TRACE,Decod,"instruction_l_xor","  * instruction   : l.xor");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_XOR;
-    inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_type               = instruction_information(INSTRUCTION_L_XOR)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR;
+    inst->_has_immediat       = 0;
+//  inst->_immediat           = ;
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+//  inst->_num_reg_rc         = ;
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+//  inst->_num_reg_re         = ;
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
@@ -2493,6 +2663,6 @@
     log_printf(TRACE,Decod,"instruction_l_xori","  * instruction   : l.xori");
 
-    inst->_type               = TYPE_ALU;
-    inst->_operation          = OPERATION_ALU_L_XOR;
+    inst->_type               = instruction_information(INSTRUCTION_L_XORI)._type     ; //TYPE_ALU;
+    inst->_operation          = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR;
     inst->_has_immediat       = 1;
     inst->_immediat           = EXTENDS(inst->_instruction,16);
@@ -2508,8 +2678,10 @@
 //  inst->_num_reg_re         = ;
     inst->_exception_use      = EXCEPTION_USE_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ;
+    inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
   }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps	(revision 88)
@@ -13,4 +13,7 @@
 include 			$(DIR_MORPHEO)/Behavioural/Makefile.deps
 endif
+ifndef Priority
+include 			$(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps
+endif
 ifndef Custom
 include 			$(DIR_MORPHEO)/Behavioural/Custom/Makefile.deps
@@ -25,8 +28,10 @@
 Decod_LIBRARY			= 	-lDecod	\
 					$(Custom_LIBRARY)		\
+					$(Priority_LIBRARY)		\
 					$(Behavioural_LIBRARY)	
 
-Decod_DIR_LIBRARY		=	-L$(Decod_DIR)/lib	\
+Decod_DIR_LIBRARY		=	-L$(Decod_DIR)/lib		\
 					$(Custom_DIR_LIBRARY)		\
+					$(Priority_DIR_LIBRARY)		\
 					$(Behavioural_DIR_LIBRARY)
 
@@ -36,4 +41,5 @@
 				@\
 				$(MAKE) Behavioural_library;		\
+				$(MAKE) Priority_library;		\
 				$(MAKE) Custom_library;			\
 				$(MAKE) --directory=$(Decod_DIR) --makefile=Makefile;
@@ -42,4 +48,5 @@
 				@\
 				$(MAKE) Behavioural_library_clean;	\
+				$(MAKE) Priority_library_clean;		\
 				$(MAKE) Custom_library_clean;		\
 				$(MAKE) --directory=$(Decod_DIR) --makefile=Makefile clean;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Decod_library_clean
 
+local_clean			:
+
 include                         $(DIR_COMPONENT)/Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg	(revision 88)
@@ -1,8 +1,7 @@
 Decod
 1	1	*4	# nb_context           
-1	1	*4	# nb_inst_fetch        [0] [nb_context]
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
 1	1	*4	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-0	0	+1	# size_branch_update_prediction
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
 1	1	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg	(revision 88)
@@ -1,8 +1,7 @@
 Decod
 1	1	*4	# nb_context           
-4	16	*4	# nb_inst_fetch        [0] [nb_context]
-1	4 	*4	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-0	2	+1	# size_branch_update_prediction
+4	16	*4	# nb_inst_fetch                 [0] [nb_context]
+1	4 	*4	# nb_inst_decod         
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
 1	1	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg	(revision 88)
@@ -1,11 +1,13 @@
 Decod
 4	4	*4	# nb_context           
-1	1	*4	# nb_inst_fetch        [0] [nb_context]
-2	2	*4	# nb_inst_fetch        [1] [nb_context]
-4	4	*4	# nb_inst_fetch        [2] [nb_context]
-8	8	*4	# nb_inst_fetch        [3] [nb_context]
+1	1	*4	# nb_inst_fetch                 [0] [nb_context]
+2	2	*4	# nb_inst_fetch                 [1] [nb_context]
+4	4	*4	# nb_inst_fetch                 [2] [nb_context]
+8	8	*4	# nb_inst_fetch                 [3] [nb_context]
 1	8	*2	# nb_inst_decod        
-1	1	*2	# nb_branch_speculated 
-2	2	*2	# size_branch_update_prediction
+1	1	*2	# nb_branch_speculated          [0] [nb_context]
+0	0	*2	# nb_branch_speculated          [1] [nb_context]
+1	1	*2	# nb_branch_speculated          [2] [nb_context]
+2	2	*2	# nb_branch_speculated          [3] [nb_context]
 1	4	*2	# nb_context_select    
 32	32	*2	# size_general_data    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h	(revision 88)
@@ -32,4 +32,5 @@
   public : Ttype_t             _type                       ;
   public : Toperation_t        _operation                  ;
+  public : Tcontrol_t          _no_execute                 ;
   public : Tcontrol_t          _is_delay_slot              ;
   public : Tcontrol_t          _has_immediat               ;
@@ -46,4 +47,6 @@
   public : Tspecial_address_t  _num_reg_re                 ;
   public : Texception_t        _exception_use              ;
+  public : Texception_t        _exception_ifetch           ;
+  public : Texception_t        _exception_decod            ;
   public : Tevent_type_t       _context_event_type         ;
 
@@ -64,4 +67,5 @@
 		    Ttype_t             type                       ,
 		    Toperation_t        operation                  ,
+// 		    Tcontrol_t          no_execute                 ,
 		    Tcontrol_t          is_delay_slot              ,
 		    Tcontrol_t          has_immediat               ,
@@ -78,4 +82,6 @@
 		    Tspecial_address_t  num_reg_re                 ,
 		    Texception_t        exception_use              ,
+//                     Texception_t        exception_ifetch           ,
+//                     Texception_t        exception_decod            ,
 		    Tevent_type_t       context_event_type         )
     {
@@ -110,4 +116,8 @@
       _exception_use               = exception_use              ;
       _context_event_type          = context_event_type         ;
+
+      _no_execute                  = 0                          ;
+      _exception_ifetch            = EXCEPTION_IFETCH_NONE      ;
+      _exception_decod             = EXCEPTION_DECOD_NONE       ;
     }
   };
@@ -246,5 +256,5 @@
     0xe3caa309,x,y,z,
     BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
-    0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIV,false,
+    0,TYPE_DIV,OPERATION_DIV_L_DIV,false,
     0,0x0,1,10,1,20,0,0                 ,1,30,1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -265,5 +275,5 @@
     0xe3caa30a,x,y,z,
     BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
-    0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIVU,true,
+    0,TYPE_DIV,OPERATION_DIV_L_DIVU,true,
     0,0x0,1,10,1,20,0,0                 ,1,30,1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -622,5 +632,5 @@
     0xe3caa306,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -631,5 +641,5 @@
     0xb3ca03fa,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     1,0x3fa, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -640,5 +650,5 @@
     0xb3cafc06,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
+    TYPE_MUL,OPERATION_MUL_L_MUL,false,
     1,0xfffffc06, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
@@ -649,5 +659,5 @@
     0xe3caa30b,x,y,z,
     0,0,0,0,0,0,
-    TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MULU,false,
+    TYPE_MUL,OPERATION_MUL_L_MULU,false,
     0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
     EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp	(revision 88)
@@ -9,5 +9,5 @@
 #include "Behavioural/Custom/include/Custom_example.h"
 
-#define NB_PARAMS 8
+#define NB_PARAMS 6
 
 void usage (int argc, char * argv[])
@@ -15,13 +15,12 @@
   err (_("<Usage> %s name_instance list_params.\n"),argv[0]);
   err (_("list_params is :\n"));
-  err (_(" * nb_context                                (uint32_t         )\n"));
-  err (_(" * nb_inst_fetch                [nb_context] (uint32_t         )\n"));
-  err (_(" * nb_inst_decod                             (uint32_t         )\n"));
-  err (_(" * nb_branch_speculated                      (uint32_t         )\n"));
-  err (_(" * size_branch_update_prediction             (uint32_t         )\n"));
-  err (_(" * nb_context_select                         (uint32_t         )\n"));
-  err (_(" * size_general_data                         (uint32_t         )\n"));
-  err (_(" * priority                                  (Tpriority_t      )\n"));
-  err (_(" * load_balancing                            (Tload_balancing_t)\n"));
+  err (_(" * nb_context                                 (uint32_t         )\n"));
+  err (_(" * nb_inst_fetch                 [nb_context] (uint32_t         )\n"));
+  err (_(" * nb_inst_decod                              (uint32_t         )\n"));
+  err (_(" * nb_branch_speculated          [nb_context] (uint32_t         )\n"));
+  err (_(" * nb_context_select                          (uint32_t         )\n"));
+  err (_(" * size_general_data                          (uint32_t         )\n"));
+  err (_(" * priority                                   (Tpriority_t      )\n"));
+  err (_(" * load_balancing                             (Tload_balancing_t)\n"));
 
   exit (1);
@@ -42,14 +41,21 @@
   uint32_t            _nb_context           = fromString<uint32_t         >(argv[x++]);
 
-  if (argc != static_cast<int>(2+NB_PARAMS+_nb_context))
+  if (argc != static_cast<int>(2+NB_PARAMS+2*_nb_context))
     usage (argc, argv);
   
-  uint32_t          * _nb_inst_fetch        = new uint32_t [_nb_context];
+  uint32_t          * _nb_inst_fetch                = new uint32_t [_nb_context];
   for (uint32_t i=0;i<_nb_context; i++)
     _nb_inst_fetch [i] = fromString<uint32_t>(argv[x++]);
 
   uint32_t            _nb_inst_decod                = fromString<uint32_t         >(argv[x++]);
-  uint32_t            _nb_branch_speculated         = fromString<uint32_t         >(argv[x++]);
-  uint32_t            _size_branch_update_prediction= fromString<uint32_t         >(argv[x++]);
+
+  uint32_t          * _nb_branch_speculated         = new uint32_t [_nb_context];
+  for (uint32_t i=0;i<_nb_context; i++)
+    _nb_branch_speculated [i] = fromString<uint32_t>(argv[x++]);
+
+//   uint32_t          * _size_branch_update_prediction= new uint32_t [_nb_context];
+//   for (uint32_t i=0;i<_nb_context; i++)
+//     _size_branch_update_prediction[i] = fromString<uint32_t>(argv[x++]);
+
   uint32_t            _nb_context_select            = fromString<uint32_t         >(argv[x++]);
   uint32_t            _size_general_data            = fromString<uint32_t         >(argv[x++]);
@@ -63,5 +69,5 @@
       
       for (uint32_t j=0; j<NB_INSTRUCTION; j++)
-	_instruction_implemeted [i][j] = true;
+        _instruction_implemeted [i][j] = true;
     }
 
@@ -70,16 +76,17 @@
     {
       morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters
-	(_nb_context                   ,
-	 _nb_inst_fetch                ,
-	 _nb_inst_decod                ,
-	 _nb_branch_speculated         ,
-	 _size_branch_update_prediction,
-	 _nb_context_select            ,
-	 _size_general_data            ,
-	 _priority                     ,
-	 _load_balancing               ,
-	 _instruction_implemeted       ,
-	 &(morpheo::behavioural::custom::example_get_custom_information)
-	 );
+        (_nb_context                   ,
+         _nb_inst_fetch                ,
+         _nb_inst_decod                ,
+         _nb_branch_speculated         ,
+//          _size_branch_update_prediction,
+         _nb_context_select            ,
+         _size_general_data            ,
+         _priority                     ,
+         _load_balancing               ,
+         _instruction_implemeted       ,
+         &(morpheo::behavioural::custom::example_get_custom_information),
+         true // is_toplevel
+         );
       
       msg(_("%s"),param->print(1).c_str());
@@ -100,4 +107,7 @@
   delete _nb_inst_fetch;
   delete _instruction_implemeted;
+  delete _nb_branch_speculated;
+//   delete _size_branch_update_prediction;
+
   return (_return);
 }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp	(revision 88)
@@ -22,6 +22,16 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Decod * _Decod = new Decod 
@@ -31,5 +41,5 @@
 #endif
      _param,
-     USE_ALL);
+     _usage);
   
 #ifdef SYSTEMC
@@ -42,7 +52,7 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC2_SC_SIGNAL( in_IFETCH_VAL                         ," in_IFETCH_VAL                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  ALLOC2_SC_SIGNAL(out_IFETCH_ACK                         ,"out_IFETCH_ACK                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION                 ," in_IFETCH_INSTRUCTION                 ",Tinstruction_t     ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
+  ALLOC2_SC_SIGNAL( in_IFETCH_VAL                         ," in_IFETCH_VAL                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  ALLOC2_SC_SIGNAL(out_IFETCH_ACK                         ,"out_IFETCH_ACK                         ",Tcontrol_t         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION                 ," in_IFETCH_INSTRUCTION                 ",Tinstruction_t     ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
   ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID                  ," in_IFETCH_CONTEXT_ID                  ",Tcontext_t         ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS                     ," in_IFETCH_ADDRESS                     ",Tgeneral_address_t ,_param->_nb_context);
@@ -51,4 +61,6 @@
   ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE                ," in_IFETCH_BRANCH_STATE                ",Tbranch_state_t    ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t  ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION                   ," in_IFETCH_EXCEPTION                   ",Texception_t       ,_param->_nb_context);
+
   ALLOC1_SC_SIGNAL(out_DECOD_VAL                          ,"out_DECOD_VAL                          ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_DECOD_ACK                          ," in_DECOD_ACK                          ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -57,4 +69,5 @@
   ALLOC1_SC_SIGNAL(out_DECOD_TYPE                         ,"out_DECOD_TYPE                         ",Ttype_t            ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_OPERATION                    ,"out_DECOD_OPERATION                    ",Toperation_t       ,_param->_nb_inst_decod);
+  ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE                   ,"out_DECOD_NO_EXECUTE                   ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT                ,"out_DECOD_IS_DELAY_SLOT                ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS                      ,"out_DECOD_ADDRESS                      ",Tgeneral_data_t    ,_param->_nb_inst_decod);
@@ -72,4 +85,5 @@
   ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE                   ,"out_DECOD_NUM_REG_RE                   ",Tspecial_address_t ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE                ,"out_DECOD_EXCEPTION_USE                ",Texception_t       ,_param->_nb_inst_decod);
+  ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION                    ,"out_DECOD_EXCEPTION                    ",Texception_t       ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL(out_PREDICT_VAL                        ,"out_PREDICT_VAL                        ",Tcontrol_t         ,_param->_nb_inst_decod);
   ALLOC1_SC_SIGNAL( in_PREDICT_ACK                        ," in_PREDICT_ACK                        ",Tcontrol_t         ,_param->_nb_inst_decod);
@@ -89,4 +103,5 @@
   ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK                  ," in_CONTEXT_EVENT_ACK                  ",Tcontrol_t         );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID           ,"out_CONTEXT_EVENT_CONTEXT_ID           ",Tcontext_t         );
+  ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH                ,"out_CONTEXT_EVENT_DEPTH                ",Tdepth_t           );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE                 ,"out_CONTEXT_EVENT_TYPE                 ",Tevent_type_t      );
   ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT        ,"out_CONTEXT_EVENT_IS_DELAY_SLOT        ",Tcontrol_t         );
@@ -103,16 +118,23 @@
   (*(_Decod->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL                         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK                         ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
-  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION                 ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
+  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL                         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK                         ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
+  INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION                 ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
   if (_param->_have_port_context_id)
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID                  ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS                     ,_param->_nb_context);
 //   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT                ,_param->_nb_context);
-  if (_param->_have_port_inst_ifetch_ptr)
-  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR             ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE                ,_param->_nb_context);
-  if (_param->_have_port_branch_update_prediction_id)
-  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION                   ,_param->_nb_context);
+
+  for (uint32_t i=0; i<_param->_nb_context; i++)
+    {
+      if (_param->_have_port_inst_ifetch_ptr)
+        INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
+//       if (_param->_have_port_branch_update_prediction_id)
+      if (_param->_have_port_depth)
+        INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
+    }
+
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL                          ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK                          ,_param->_nb_inst_decod);
@@ -123,4 +145,5 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE                         ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION                    ,_param->_nb_inst_decod);
+  INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT                ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS                      ,_param->_nb_inst_decod);
@@ -138,4 +161,5 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE                   ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE                ,_param->_nb_inst_decod);
+  INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION                    ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL                        ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK                        ,_param->_nb_inst_decod);
@@ -144,5 +168,6 @@
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR      ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE               ,_param->_nb_inst_decod);
-  if (_param->_have_port_branch_update_prediction_id)
+//   if (_param->_have_port_branch_update_prediction_id)
+  if (_param->_have_port_depth)
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION           ,_param->_nb_inst_decod);
@@ -153,10 +178,13 @@
 //   INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE               ,_param->_nb_inst_decod);
   INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE               ,_param->_nb_context);
-  if (_param->_have_port_depth)
-  INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH                      ,_param->_nb_context);
+  for (uint32_t i=0; i<_param->_nb_context; i++)
+    if (_param->_have_port_depth)
+      INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL                  );
   INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK                  );
   if (_param->_have_port_context_id)
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID           );
+  if (_param->_have_port_depth)
+  INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH                );
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE                 );
   INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT        );
@@ -236,4 +264,5 @@
 		      if (_param->_have_port_inst_ifetch_ptr)
 		      in_IFETCH_INST_IFETCH_PTR [i]->write(0);
+		      in_IFETCH_EXCEPTION       [i]->write(EXCEPTION_IFETCH_NONE);
 
 		      // Alignement
@@ -336,5 +365,6 @@
 		    TEST(Tcontrol_t         , out_PREDICT_MATCH_INST_IFETCH_PTR       [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
 		    TEST(Tbranch_state_t    , out_PREDICT_BRANCH_STATE                [i]->read(), request [context].front()._branch_state               );
-		    if (_param->_have_port_branch_update_prediction_id)
+// 		    if (_param->_have_port_branch_update_prediction_id)
+ 		    if (_param->_have_port_depth)
 		    TEST(Tprediction_ptr_t  , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
 		    TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION            [i]->read(), request [context].front()._branch_condition           );
@@ -358,4 +388,6 @@
 		    if (_param->_have_port_context_id)
 		    TEST(Tcontext_t     ,out_CONTEXT_EVENT_CONTEXT_ID   ->read(), context);
+		    if (_param->_have_port_depth )
+		    TEST(Tcontext_t     ,out_CONTEXT_EVENT_DEPTH        ->read(), request [context].front()._depth        );
 		    TEST(Tevent_type_t  ,out_CONTEXT_EVENT_TYPE         ->read(), request [context].front()._context_event_type);
 		    TEST(Tcontrol_t     ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
@@ -403,4 +435,5 @@
   delete []  in_IFETCH_BRANCH_STATE                ;
   delete []  in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
+  delete []  in_IFETCH_EXCEPTION                   ;
   
   delete [] out_DECOD_VAL                          ;
@@ -410,4 +443,5 @@
   delete [] out_DECOD_TYPE                         ;
   delete [] out_DECOD_OPERATION                    ;
+  delete [] out_DECOD_NO_EXECUTE                   ;
   delete [] out_DECOD_IS_DELAY_SLOT                ;
   delete [] out_DECOD_ADDRESS                      ;
@@ -425,4 +459,5 @@
   delete [] out_DECOD_NUM_REG_RE                   ;
   delete [] out_DECOD_EXCEPTION_USE                ;
+  delete [] out_DECOD_EXCEPTION                    ;
   
   delete [] out_PREDICT_VAL                        ;
@@ -445,4 +480,5 @@
   delete     in_CONTEXT_EVENT_ACK                  ;
   delete    out_CONTEXT_EVENT_CONTEXT_ID           ;
+  delete    out_CONTEXT_EVENT_DEPTH                ;
   delete    out_CONTEXT_EVENT_TYPE                 ;
   delete    out_CONTEXT_EVENT_IS_DELAY_SLOT        ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h	(revision 88)
@@ -13,6 +13,4 @@
 #endif
 
-#include <iostream>
-#include <list>
 #include "Common/include/ToString.h"
 #include "Common/include/Debug.h"
@@ -29,4 +27,9 @@
 #endif
 #include "Behavioural/include/Usage.h"
+
+#include "Behavioural/Generic/Priority/include/Priority.h"
+
+#include <iostream>
+#include <list>
 
 namespace morpheo {
@@ -75,5 +78,5 @@
   public    : SC_IN (Tbranch_state_t    )  **  in_IFETCH_BRANCH_STATE                ;//[nb_context]
   public    : SC_IN (Tprediction_ptr_t  )  **  in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context]
-										     
+  public    : SC_IN (Texception_t       )  **  in_IFETCH_EXCEPTION                   ;//[nb_context]										     
     // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	     
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_VAL                          ;//[nb_inst_decod]
@@ -83,4 +86,5 @@
   public    : SC_OUT(Ttype_t            )  ** out_DECOD_TYPE                         ;//[nb_inst_decod]
   public    : SC_OUT(Toperation_t       )  ** out_DECOD_OPERATION                    ;//[nb_inst_decod]
+  public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_NO_EXECUTE                   ;//[nb_inst_decod]
   public    : SC_OUT(Tcontrol_t         )  ** out_DECOD_IS_DELAY_SLOT                ;//[nb_inst_decod]
   public    : SC_OUT(Tgeneral_data_t    )  ** out_DECOD_ADDRESS                      ;//[nb_inst_decod]
@@ -98,4 +102,5 @@
   public    : SC_OUT(Tspecial_address_t )  ** out_DECOD_NUM_REG_RE                   ;//[nb_inst_decod]
   public    : SC_OUT(Texception_t       )  ** out_DECOD_EXCEPTION_USE                ;//[nb_inst_decod]
+  public    : SC_OUT(Texception_t       )  ** out_DECOD_EXCEPTION                    ;//[nb_inst_decod]
 
     // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -121,4 +126,5 @@
   public    : SC_IN (Tcontrol_t         )   *  in_CONTEXT_EVENT_ACK                  ;
   public    : SC_OUT(Tcontext_t         )   * out_CONTEXT_EVENT_CONTEXT_ID           ;
+  public    : SC_OUT(Tdepth_t           )   * out_CONTEXT_EVENT_DEPTH                ;
   public    : SC_OUT(Tevent_type_t      )   * out_CONTEXT_EVENT_TYPE                 ;
   public    : SC_OUT(Tcontrol_t         )   * out_CONTEXT_EVENT_IS_DELAY_SLOT        ;
@@ -127,7 +133,7 @@
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+  private   : generic::priority::Priority   * _priority;
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-  private   : uint32_t                        reg_CONTEXT_PRIORITY;
   private   : Tgeneral_data_t               * reg_CONTEXT_ADDRESS_PREVIOUS     ; //[nb_context]
   private   : Tcontrol_t                    * reg_CONTEXT_IS_DELAY_SLOT        ; //[nb_context]
@@ -136,4 +142,5 @@
   private   : Tcontrol_t                    * internal_CONTEXT_IS_DELAY_SLOT   ; //[nb_context]
 
+  private   : Tcontrol_t                    * internal_DECOD_VAL               ; //[nb_inst_decod]
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   private   : decod_instruction_t           * _decod_instruction;
@@ -141,5 +148,4 @@
   private   : function_decod_t           **** _function_decod   ; //[nb_context][type][opcod]
   private   : function_decod_t           **** _function_custom  ; //[nb_context][type][opcod]
-  private   : std::list<select_t>             select;
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h	(revision 88)
@@ -29,24 +29,15 @@
   public : uint32_t          * _nb_inst_fetch                ; //[nb_context]
   public : uint32_t            _nb_inst_decod                ;
-  public : uint32_t            _size_general_data            ;
-  public : uint32_t            _nb_branch_speculated         ;
-  public : uint32_t            _size_branch_update_prediction;
+//public : uint32_t            _size_general_data            ;
+  public : uint32_t          * _nb_branch_speculated         ; //[nb_context]
+//public : uint32_t          * _size_branch_update_prediction; //[nb_context]
   public : uint32_t            _nb_context_select            ;
   public : Tpriority_t         _priority                     ;
   public : Tload_balancing_t   _load_balancing               ;
   public : bool             ** _instruction_implemeted       ; //[nb_context][nb_instruction]
-  public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t);
+  public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void);
     
-  public : uint32_t            _max_nb_inst_fetch     ;
-
-  public : uint32_t            _size_address_inst     ;
-  public : uint32_t            _size_context_id       ;
-  public : uint32_t            _size_depth            ;
-  public : uint32_t            _size_inst_ifetch_ptr  ;
-						      
-  public : bool                _have_port_context_id                 ;
-  public : bool                _have_port_depth                      ;
-  public : bool                _have_port_branch_update_prediction_id;
-  public : bool                _have_port_inst_ifetch_ptr            ;
+  public : uint32_t            _max_nb_inst_fetch;
+//public : uint32_t            _size_address_inst;
 
     //-----[ methods ]-----------------------------------------------------------
@@ -55,15 +46,19 @@
 			uint32_t          * nb_inst_fetch                ,
 			uint32_t            nb_inst_decod                ,
+			uint32_t          * nb_branch_speculated         ,
+// 			uint32_t          * size_branch_update_prediction,
+			uint32_t            nb_context_select            ,
 			uint32_t            size_general_data            ,
-			uint32_t            nb_branch_speculated         ,
-			uint32_t            size_branch_update_prediction,
-			uint32_t            nb_context_select            ,
 			Tpriority_t         priority                     ,
 			Tload_balancing_t   load_balancing               ,
 			bool             ** instruction_implemeted       ,
-			morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t));
+			morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void),
+                        bool                is_toplevel=false
+                        );
 
 //   public : Parameters  (Parameters & param) ;
   public : ~Parameters () ;
+
+  public :        void            copy       (void);
 
   public :        Parameters_test msg_error  (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h	(revision 88)
@@ -19,17 +19,4 @@
 namespace decod {
 
-  class select_t
-  {
-  public : uint32_t _context ;
-  public : uint32_t _inst_fetch;
-    
-  public : select_t (uint32_t context,
-		     uint32_t inst_fetch)
-    {
-      _context    = context ;
-      _inst_fetch = inst_fetch;
-    }
-  };
-
 
 }; // end namespace decod
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp	(revision 88)
@@ -38,4 +38,10 @@
     log_printf(FUNC,Decod,FUNCTION,"Begin");
 
+#if DEBUG_Decod == true
+    log_printf(INFO,Decod,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+    std::cout << *param << std::endl;
+#endif    
+
     log_printf(INFO,Decod,FUNCTION,"Allocation");
 
@@ -47,5 +53,5 @@
 
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {	
 	log_printf(INFO,Decod,FUNCTION,"Allocation of statistics");
@@ -56,5 +62,5 @@
 
 #ifdef VHDL
-    if (_usage & USE_VHDL)
+    if (usage_is_set(_usage,USE_VHDL))
       {
 	// generate the vhdl
@@ -66,5 +72,5 @@
 
 #ifdef SYSTEMC
-    if (_usage & USE_SYSTEMC)
+    if (usage_is_set(_usage,USE_SYSTEMC))
       {
 	log_printf(INFO,Decod,FUNCTION,"Method - transition");
@@ -95,5 +101,5 @@
 	    if (_param->_have_port_context_id)
             sensitive << (*(in_IFETCH_CONTEXT_ID                  [i]));
-	    if (_param->_have_port_branch_update_prediction_id)
+	    if (_param->_have_port_depth)
 	    sensitive << (*(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]));
 	    if (_param->_have_port_depth)
@@ -110,4 +116,5 @@
 
 # ifdef SYSTEMCASS_SPECIFIC
+        /*
 	// List dependency information
 
@@ -162,8 +169,9 @@
 	      }
 
-	    if (_param->_have_port_depth)
-	      {
-	    for (uint32_t x=0; x<_param->_nb_context; x++)
-	      {
+	    for (uint32_t x=0; x<_param->_nb_context; x++)
+	      {
+	    if (_param->_have_port_depth[i])
+	      {
+
 		(*(out_DECOD_DEPTH [i])) (*(in_CONTEXT_DECOD_ENABLE [x]));
 		(*(out_DECOD_DEPTH [i])) (*(in_CONTEXT_DEPTH        [x]));
@@ -402,5 +410,5 @@
 		if (_param->_have_port_context_id)
 		(*(out_PREDICT_MATCH_INST_IFETCH_PTR [i])) (*(in_IFETCH_CONTEXT_ID      [x]));
-		if (_param->_have_port_inst_ifetch_ptr)
+		if (_param->_have_port_inst_ifetch_ptr[i])
 		(*(out_PREDICT_MATCH_INST_IFETCH_PTR [i])) (*(in_IFETCH_INST_IFETCH_PTR [x]));
 		for (uint32_t y=0; y<_param->_nb_inst_fetch [x]; y++)
@@ -601,5 +609,5 @@
 	      }
 	  }
-	
+        */
 # endif    
 	
@@ -617,5 +625,5 @@
 
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {
 	statistics_deallocation();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp	(revision 88)
@@ -1,4 +1,4 @@
 /*
- * $Id$
+ * $id: Decod_allocation.cpp 86 2008-05-14 17:08:56Z rosiere $
  *
  * [ Description ]
@@ -58,20 +58,21 @@
     // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     {
-      ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[alloc_interface_it1]);
+      ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[it1]);
 
       
-      _ALLOC2_VALACK_IN ( in_IFETCH_VAL        ,VAL, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]);
-      _ALLOC2_VALACK_OUT(out_IFETCH_ACK        ,ACK, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]);
-      _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]);
+      _ALLOC2_VALACK_IN ( in_IFETCH_VAL        ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]);
+      _ALLOC2_VALACK_OUT(out_IFETCH_ACK        ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]);
+      _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]);
     }
     {
       ALLOC1_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context);
       
-      ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t         ,_param->_size_context_id              );
-      ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS                    ,"address"                    ,Tgeneral_address_t ,_param->_size_address_inst            );
-//    ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT               ,"address_next"               ,Tgeneral_address_t ,_param->_size_address_inst            );
-      ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr         );
-      ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state            );
-      ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_branch_update_prediction);
+      ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t         ,_param->_size_context_id      );
+      ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS                    ,"address"                    ,Tgeneral_address_t ,_param->_size_instruction_address    );
+//    ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT               ,"address_next"               ,Tgeneral_address_t ,_param->_size_instruction_address    );
+      ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr );
+      ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state    );
+      ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth           );
+      ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION                  ,"exception"                  ,Texception_t       ,_param->_size_exception_ifetch);
     }
 
@@ -86,6 +87,7 @@
       ALLOC1_SIGNAL_OUT(out_DECOD_TYPE         ,"type"         ,Ttype_t           ,_param->_size_type                  );
       ALLOC1_SIGNAL_OUT(out_DECOD_OPERATION    ,"operation"    ,Toperation_t      ,_param->_size_operation             );
+      ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE   ,"no_execute"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_address_inst          );
+      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_instruction_address          );
       ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT     ,"immediat"     ,Tgeneral_data_t   ,_param->_size_general_data          );
@@ -101,4 +103,5 @@
       ALLOC1_SIGNAL_OUT(out_DECOD_NUM_REG_RE   ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register_logic);
       ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION_USE,"exception_use",Texception_t      ,_param->_size_exception_use         );
+      ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION    ,"exception"    ,Texception_t      ,_param->_size_exception_decod       );
     }
 
@@ -109,14 +112,14 @@
       ALLOC1_VALACK_OUT(out_PREDICT_VAL                        ,VAL);
       ALLOC1_VALACK_IN ( in_PREDICT_ACK                        ,ACK);
-      ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t         ,_param->_size_context_id              );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR      ,"match_inst_ifetch_ptr"      ,Tcontrol_t         ,1                                     );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state            );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_branch_update_prediction);
-      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION           ,"branch_condition"           ,Tbranch_condition_t,_param->_size_branch_condition        );
-//    ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE         ,"branch_stack_write"         ,Tcontrol_t         ,1                                     );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION           ,"branch_direction"           ,Tcontrol_t         ,1                                     );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC                ,"address_src"                ,Tgeneral_data_t    ,_param->_size_address_inst            );
-      ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST               ,"address_dest"               ,Tgeneral_data_t    ,_param->_size_address_inst            );
-//    ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE               ,"can_continue"               ,Tcontrol_t         ,1                                     );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID                 ,"context_id"                 ,Tcontext_t         ,_param->_size_context_id      );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR      ,"match_inst_ifetch_ptr"      ,Tcontrol_t         ,1                             );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t    ,_param->_size_branch_state    );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t  ,_param->_size_depth           );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION           ,"branch_condition"           ,Tbranch_condition_t,_param->_size_branch_condition);
+//    ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE         ,"branch_stack_write"         ,Tcontrol_t         ,1                             );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION           ,"branch_direction"           ,Tcontrol_t         ,1                             );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC                ,"address_src"                ,Tgeneral_data_t    ,_param->_size_instruction_address    );
+      ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST               ,"address_dest"               ,Tgeneral_data_t    ,_param->_size_instruction_address    );
+//    ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE               ,"can_continue"               ,Tcontrol_t         ,1                             );
     }
     
@@ -136,12 +139,15 @@
       ALLOC_VALACK_IN ( in_CONTEXT_EVENT_ACK          ,ACK);
       ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID   ,"context_id"   ,Tcontext_t     ,_param->_size_context_id  );
+      ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH        ,"depth"        ,Tdepth_t       ,_param->_size_depth       );
       ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE         ,"type"         ,Tevent_type_t  ,_param->_size_event_type  );
       ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t     ,1                         );
-      ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS      ,"address"      ,Tgeneral_data_t,_param->_size_address_inst);
-      ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_address_inst);
-    }
-
-    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-
+      ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS      ,"address"      ,Tgeneral_data_t,_param->_size_instruction_address);
+      ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address);
+    }
+
+
+    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
     reg_CONTEXT_ADDRESS_PREVIOUS      = new Tgeneral_data_t [_param->_nb_context];
     reg_CONTEXT_IS_DELAY_SLOT         = new Tcontrol_t      [_param->_nb_context];
@@ -150,4 +156,17 @@
     internal_CONTEXT_ADDRESS_PREVIOUS = new Tgeneral_data_t [_param->_nb_context];
     internal_CONTEXT_IS_DELAY_SLOT    = new Tcontrol_t      [_param->_nb_context];
+
+#ifdef STATISTICS
+    internal_DECOD_VAL                = new Tcontrol_t      [_param->_nb_inst_decod];
+#endif
+      }
+
+    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+    _priority = new generic::priority::Priority (_name+"_priority"      ,
+						 _param->_priority      ,
+						 _param->_load_balancing,
+						 _param->_nb_context    ,
+						 _param->_nb_inst_fetch ,
+						 _param->_nb_context_select);
 
     const uint32_t nb_opcod_type = 14;
@@ -415,18 +434,18 @@
 // 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4   ]) _function_decod [i][ 2][OPCOD_LV_CUST4   ] = &(instruction_lv_custom);
 
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1    ]) _function_custom[i][ 0][OPCOD_L_CUST1    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_1   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2    ]) _function_custom[i][ 0][OPCOD_L_CUST2    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_2   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3    ]) _function_custom[i][ 0][OPCOD_L_CUST3    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_3   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4    ]) _function_custom[i][ 0][OPCOD_L_CUST4    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_4   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5    ]) _function_custom[i][ 0][OPCOD_L_CUST5    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_5   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6    ]) _function_custom[i][ 0][OPCOD_L_CUST6    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_6   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7    ]) _function_custom[i][ 0][OPCOD_L_CUST7    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_7   );
-	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8    ]) _function_custom[i][ 0][OPCOD_L_CUST8    ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_8   );
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LF_1_D);
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LF_1_S);
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1   ]) _function_custom[i][ 2][OPCOD_LV_CUST1   ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_1  );
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2   ]) _function_custom[i][ 2][OPCOD_LV_CUST2   ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_2  );
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3   ]) _function_custom[i][ 2][OPCOD_LV_CUST3   ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_3  );
-// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4   ]) _function_custom[i][ 2][OPCOD_LV_CUST4   ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_4  );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1    ]) _function_custom[i][ 0][OPCOD_L_CUST1    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_1   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2    ]) _function_custom[i][ 0][OPCOD_L_CUST2    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_2   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3    ]) _function_custom[i][ 0][OPCOD_L_CUST3    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_3   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4    ]) _function_custom[i][ 0][OPCOD_L_CUST4    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_4   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5    ]) _function_custom[i][ 0][OPCOD_L_CUST5    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_5   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6    ]) _function_custom[i][ 0][OPCOD_L_CUST6    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_6   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7    ]) _function_custom[i][ 0][OPCOD_L_CUST7    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_7   );
+	if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8    ]) _function_custom[i][ 0][OPCOD_L_CUST8    ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_8   );
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_D);
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_S);
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1   ]) _function_custom[i][ 2][OPCOD_LV_CUST1   ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_1  );
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2   ]) _function_custom[i][ 2][OPCOD_LV_CUST2   ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_2  );
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3   ]) _function_custom[i][ 2][OPCOD_LV_CUST3   ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_3  );
+// 	if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4   ]) _function_custom[i][ 2][OPCOD_LV_CUST4   ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_4  );
       }
 
@@ -440,5 +459,6 @@
 
 #ifdef POSITION
-    _component->generate_file();
+    if (usage_is_set(_usage,USE_POSITION))
+      _component->generate_file();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp	(revision 88)
@@ -7,4 +7,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo                    {
@@ -27,78 +28,83 @@
 	delete    in_CLOCK ;
 	delete    in_NRESET;
+      
+        DELETE2_SIGNAL( in_IFETCH_VAL        , _param->_nb_context, _param->_nb_inst_fetch[it1],1);
+        DELETE2_SIGNAL(out_IFETCH_ACK        , _param->_nb_context, _param->_nb_inst_fetch[it1],1);
+        DELETE2_SIGNAL( in_IFETCH_INSTRUCTION, _param->_nb_context, _param->_nb_inst_fetch[it1],_param->_size_instruction);
+      
+        DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID                 , _param->_nb_context,_param->_size_context_id      );
+        DELETE1_SIGNAL(in_IFETCH_ADDRESS                    , _param->_nb_context,_param->_size_instruction_address    );
+//      DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT               , _param->_nb_context,_param->_size_instruction_address    );
+        DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR            , _param->_nb_context,_param->_size_inst_ifetch_ptr );
+        DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE               , _param->_nb_context,_param->_size_branch_state    );
+        DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID, _param->_nb_context,_param->_size_depth           );
+        DELETE1_SIGNAL(in_IFETCH_EXCEPTION                  , _param->_nb_context,_param->_size_exception_ifetch);
 
-	delete []  in_IFETCH_VAL                         ;
-	delete [] out_IFETCH_ACK                         ;
-	delete []  in_IFETCH_INSTRUCTION                 ;
-	if (_param->_have_port_context_id)
-	delete []  in_IFETCH_CONTEXT_ID                  ;
-	delete []  in_IFETCH_ADDRESS                     ;
-// 	delete []  in_IFETCH_ADDRESS_NEXT                ;
-	if (_param->_have_port_inst_ifetch_ptr)
-	delete []  in_IFETCH_INST_IFETCH_PTR             ;
-	delete []  in_IFETCH_BRANCH_STATE                ;
-	if (_param->_have_port_branch_update_prediction_id)
-	delete []  in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
+        DELETE1_SIGNAL(out_DECOD_VAL          ,_param->_nb_inst_decod,1);
+        DELETE1_SIGNAL( in_DECOD_ACK          ,_param->_nb_inst_decod,1);
+        DELETE1_SIGNAL(out_DECOD_CONTEXT_ID   ,_param->_nb_inst_decod,_param->_size_context_id            );
+        DELETE1_SIGNAL(out_DECOD_DEPTH        ,_param->_nb_inst_decod,_param->_size_depth                 );
+        DELETE1_SIGNAL(out_DECOD_TYPE         ,_param->_nb_inst_decod,_param->_size_type                  );
+        DELETE1_SIGNAL(out_DECOD_OPERATION    ,_param->_nb_inst_decod,_param->_size_operation             );
+        DELETE1_SIGNAL(out_DECOD_NO_EXECUTE   ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_ADDRESS      ,_param->_nb_inst_decod,_param->_size_instruction_address          );
+        DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_IMMEDIAT     ,_param->_nb_inst_decod,_param->_size_general_data          );
+        DELETE1_SIGNAL(out_DECOD_READ_RA      ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NUM_REG_RA   ,_param->_nb_inst_decod,_param->_size_general_register_logic);
+        DELETE1_SIGNAL(out_DECOD_READ_RB      ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NUM_REG_RB   ,_param->_nb_inst_decod,_param->_size_general_register_logic);
+        DELETE1_SIGNAL(out_DECOD_READ_RC      ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NUM_REG_RC   ,_param->_nb_inst_decod,_param->_size_special_register_logic);
+        DELETE1_SIGNAL(out_DECOD_WRITE_RD     ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NUM_REG_RD   ,_param->_nb_inst_decod,_param->_size_general_register_logic);
+        DELETE1_SIGNAL(out_DECOD_WRITE_RE     ,_param->_nb_inst_decod,1                                   );
+        DELETE1_SIGNAL(out_DECOD_NUM_REG_RE   ,_param->_nb_inst_decod,_param->_size_special_register_logic);
+        DELETE1_SIGNAL(out_DECOD_EXCEPTION_USE,_param->_nb_inst_decod,_param->_size_exception_use         );
+        DELETE1_SIGNAL(out_DECOD_EXCEPTION    ,_param->_nb_inst_decod,_param->_size_exception_decod       );
 
-	delete [] out_DECOD_VAL                          ;
-	delete []  in_DECOD_ACK                          ;
-	if (_param->_have_port_context_id)
-	delete [] out_DECOD_CONTEXT_ID                   ;
-	if (_param->_have_port_depth)
-	delete [] out_DECOD_DEPTH                        ;
-	delete [] out_DECOD_TYPE                         ;
-	delete [] out_DECOD_OPERATION                    ;
-	delete [] out_DECOD_IS_DELAY_SLOT                ;
-	delete [] out_DECOD_ADDRESS                      ;
-	delete [] out_DECOD_HAS_IMMEDIAT                 ;
-	delete [] out_DECOD_IMMEDIAT                     ;
-	delete [] out_DECOD_READ_RA                      ;
-	delete [] out_DECOD_NUM_REG_RA                   ;
-	delete [] out_DECOD_READ_RB                      ;
-	delete [] out_DECOD_NUM_REG_RB                   ;
-	delete [] out_DECOD_READ_RC                      ;
-	delete [] out_DECOD_NUM_REG_RC                   ;
-	delete [] out_DECOD_WRITE_RD                     ;
-	delete [] out_DECOD_NUM_REG_RD                   ;
-	delete [] out_DECOD_WRITE_RE                     ;
-	delete [] out_DECOD_NUM_REG_RE                   ;
-	delete [] out_DECOD_EXCEPTION_USE                ;
+        DELETE1_SIGNAL(out_PREDICT_VAL                        ,_param->_nb_inst_decod,1);
+        DELETE1_SIGNAL( in_PREDICT_ACK                        ,_param->_nb_inst_decod,1);
+        DELETE1_SIGNAL(out_PREDICT_CONTEXT_ID                 ,_param->_nb_inst_decod,_param->_size_context_id      );
+        DELETE1_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR      ,_param->_nb_inst_decod,1                             );
+        DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE               ,_param->_nb_inst_decod,_param->_size_branch_state    );
+        DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth           );
+        DELETE1_SIGNAL(out_PREDICT_BRANCH_CONDITION           ,_param->_nb_inst_decod,_param->_size_branch_condition);
+//      DELETE1_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE         ,_param->_nb_inst_decod,1                             );
+        DELETE1_SIGNAL(out_PREDICT_BRANCH_DIRECTION           ,_param->_nb_inst_decod,1                             );
+        DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC                ,_param->_nb_inst_decod,_param->_size_instruction_address    );
+        DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST               ,_param->_nb_inst_decod,_param->_size_instruction_address    );
+//      DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE               ,_param->_nb_inst_decod,1                             );
 
-	delete [] out_PREDICT_VAL                        ;
-	delete []  in_PREDICT_ACK                        ;
-	if (_param->_have_port_context_id)
-	delete [] out_PREDICT_CONTEXT_ID                 ;
-	delete [] out_PREDICT_BRANCH_STATE               ;
-	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR      ;
-	if (_param->_have_port_branch_update_prediction_id)
-	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
-	delete [] out_PREDICT_BRANCH_CONDITION           ;
-// 	delete [] out_PREDICT_BRANCH_STACK_WRITE         ;
-	delete [] out_PREDICT_BRANCH_DIRECTION           ;
-	delete [] out_PREDICT_ADDRESS_SRC                ;
-	delete [] out_PREDICT_ADDRESS_DEST               ;
-// 	delete []  in_PREDICT_CAN_CONTINUE               ;
+        DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE, _param->_nb_context,1);
+        DELETE1_SIGNAL(in_CONTEXT_DEPTH       , _param->_nb_context,_param->_size_depth);
 
-	delete []  in_CONTEXT_DECOD_ENABLE               ;
-	if (_param->_have_port_depth)
-	delete []  in_CONTEXT_DEPTH                      ;
+        DELETE_SIGNAL (out_CONTEXT_EVENT_VAL          ,1);
+        DELETE_SIGNAL ( in_CONTEXT_EVENT_ACK          ,1);
+        DELETE_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID   ,_param->_size_context_id  );
+        DELETE_SIGNAL (out_CONTEXT_EVENT_DEPTH        ,_param->_size_depth       );
+        DELETE_SIGNAL (out_CONTEXT_EVENT_TYPE         ,_param->_size_event_type  );
+        DELETE_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT,1                         );
+        DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS      ,_param->_size_instruction_address);
+        DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address);
 
-	delete    out_CONTEXT_EVENT_VAL                  ;
-	delete     in_CONTEXT_EVENT_ACK                  ;
-	if (_param->_have_port_context_id)
-	delete    out_CONTEXT_EVENT_CONTEXT_ID           ;
-	delete    out_CONTEXT_EVENT_TYPE                 ;
-	delete    out_CONTEXT_EVENT_IS_DELAY_SLOT        ;
-	delete    out_CONTEXT_EVENT_ADDRESS              ;
-	delete    out_CONTEXT_EVENT_ADDRESS_EPCR         ;
+
+    
+        delete    reg_CONTEXT_ADDRESS_PREVIOUS      ;
+        delete [] reg_CONTEXT_IS_DELAY_SLOT         ;
+        
+        delete [] internal_CONTEXT_HAVE_TRANSACTION ;
+        delete [] internal_CONTEXT_ADDRESS_PREVIOUS ;
+        delete [] internal_CONTEXT_IS_DELAY_SLOT    ;
+        
+#ifdef STATISTICS
+        delete [] internal_DECOD_VAL;
+#endif
       }
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
-    delete    reg_CONTEXT_ADDRESS_PREVIOUS      ;
-    delete    reg_CONTEXT_IS_DELAY_SLOT         ;
+    delete    _priority;
 
-    delete    internal_CONTEXT_HAVE_TRANSACTION ;
-    delete    internal_CONTEXT_ADDRESS_PREVIOUS ;
-    delete    internal_CONTEXT_IS_DELAY_SLOT    ;
 
     const uint32_t nb_opcod_type = 14;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp	(revision 88)
@@ -25,5 +25,6 @@
 
 #ifdef STATISTICS
-    _stat->end_cycle();
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
 #endif    
 
@@ -31,5 +32,6 @@
     // Evaluation before read the ouput signal
 //  sc_start(0);
-    _interfaces->testbench();
+    if (usage_is_set(_usage,VHDL_TESTBENCH))
+      _interfaces->testbench();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp	(revision 88)
@@ -22,5 +22,6 @@
   void Decod::genMealy (void)
   {
-    log_printf(TRACE,Decod,FUNCTION,"Begin");
+    log_begin(Decod,FUNCTION);
+    log_function(Decod,FUNCTION,_name.c_str());
 
     //-----------------------------------
@@ -38,4 +39,5 @@
       {
 	decod_val   [i] = false;
+	predict_val [i] = false;
       }
 
@@ -57,18 +59,16 @@
     //-----------------------------------
     // scan all decod "slot_out"
-    log_printf(TRACE,Decod,FUNCTION,"KANE LIVE");    
-    std::list<select_t>::iterator it=select.begin();
+    std::list<generic::priority::select_t> * select = _priority->select();
+    std::list<generic::priority::select_t>::iterator it=select->begin();
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
       {
-	while ((it != select.end())     and  // have a no scanned "slot_in" ?
+	while ((it != select->end())    and  // have a no scanned "slot_in" ?
 	       (decod_val [i] == false) and  // have not a previous selected entry?
 	       (context_event_val == false)) // Have not a context_event (spr_access, exception, ...)
 	  {
-	    log_printf(TRACE,Decod,FUNCTION,"loop");    
-
 	    predict_val [i] = false;
 
-	    Tcontext_t x = it->_context ;
-	    uint32_t   y = it->_inst_fetch;
+	    Tcontext_t x = it->grp;
+	    uint32_t   y = it->elt;
 
 	    // Test if this instruction is valid
@@ -76,5 +76,7 @@
 		(can_continue [x]                == 1))    // context can decod instruction (have not a previous event)
 	      {
-		can_continue      [x] = can_continue_next [x];
+                log_printf(TRACE,Decod,FUNCTION,"  * IFETCH [%d][%d]",x,y);    
+
+		can_continue [x] = can_continue_next [x];
 
 		decod_val  [i]    = true;                        // fetch_val and decod_enable 
@@ -90,21 +92,47 @@
 		_decod_instruction->_is_delay_slot    = internal_CONTEXT_IS_DELAY_SLOT [x];
 
-		// Decod !
-		log_printf(TRACE,Decod,FUNCTION,"DECOD [%d]",i);
-		log_printf(TRACE,Decod,FUNCTION,"  * context       : %d",x);
-		log_printf(TRACE,Decod,FUNCTION,"  * fetch         : %d",y);
-		log_printf(TRACE,Decod,FUNCTION,"  * address       : %.8x",addr);
-		log_printf(TRACE,Decod,FUNCTION,"  * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
-
-		instruction_decod (_decod_instruction, _decod_param[x]);
-
-		Ttype_t type = _decod_instruction->_type;
+                // Test IFetch exception
+                Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x]);
+
+                if (ifetch_exception == EXCEPTION_IFETCH_NONE)
+                  {
+                    // Decod !
+                    log_printf(TRACE,Decod,FUNCTION,"  * DECOD [%d]",i);
+                    log_printf(TRACE,Decod,FUNCTION,"    * context       : %d",x);
+                    log_printf(TRACE,Decod,FUNCTION,"    * fetch         : %d",y);
+                    log_printf(TRACE,Decod,FUNCTION,"    * address       : %.8x (%.8x)",addr,(addr<<2));
+                    log_printf(TRACE,Decod,FUNCTION,"    * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
+                    
+                    instruction_decod (_decod_instruction, _decod_param[x]);
+                  }
+                else
+                  {
+                    // No decod : nop
+                    instruction_l_nop (_decod_instruction, _decod_param[x]);
+
+                    _decod_instruction->_exception_use = EXCEPTION_USE_NONE;
+                    _decod_instruction->_exception     = exception_ifetch_to_exception_decod(ifetch_exception);
+                    
+                    // INSTRUCTION_TLB  
+                    // INSTRUCTION_PAGE 
+                    // BUS_ERROR        
+                    if (_decod_instruction->_is_delay_slot)
+                      _decod_instruction->_address_next       = _decod_instruction->_address_previous;
+                    else
+                      _decod_instruction->_address_next       = _decod_instruction->_address;
+                    
+                    _decod_instruction->_event_type         = EVENT_TYPE_EXCEPTION;
+                  }
+
+		Ttype_t  type  = _decod_instruction->_type;
+                Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT
 
 		if (_param->_have_port_context_id)
 		PORT_WRITE(out_DECOD_CONTEXT_ID    [i], x);
 		if (_param->_have_port_depth)
-		PORT_WRITE(out_DECOD_DEPTH         [i], PORT_READ(in_CONTEXT_DEPTH [x]));
+                PORT_WRITE(out_DECOD_DEPTH         [i], depth);
 		PORT_WRITE(out_DECOD_TYPE          [i], type);
 		PORT_WRITE(out_DECOD_OPERATION     [i], _decod_instruction->_operation     );
+ 		PORT_WRITE(out_DECOD_NO_EXECUTE    [i], _decod_instruction->_no_execute    );
 		PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
 		PORT_WRITE(out_DECOD_ADDRESS       [i], addr);
@@ -122,8 +150,11 @@
 		PORT_WRITE(out_DECOD_NUM_REG_RE    [i], _decod_instruction->_num_reg_re    );
 		PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use );
+// 		PORT_WRITE(out_DECOD_EXCEPTION     [i], _decod_instruction->_exception     );
 
 		if (type == TYPE_BRANCH)
 		  {
-		    log_printf(TRACE,Decod,FUNCTION,"  * type is branch");
+		    log_printf(TRACE,Decod,FUNCTION,"    * type is branch");
+		    log_printf(TRACE,Decod,FUNCTION,"      * address src  : %.8x (%.8x)",_decod_instruction->_address     ,_decod_instruction->_address     <<2);
+		    log_printf(TRACE,Decod,FUNCTION,"      * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2);
 
 		    predict_val [i]     = ifetch_ack  [x][y] // and decod_val [i]
@@ -136,6 +167,6 @@
 		    PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR       [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0));
 		    PORT_WRITE(out_PREDICT_BRANCH_STATE                [i],PORT_READ(in_IFETCH_BRANCH_STATE                [x]));
-		    if (_param->_have_port_branch_update_prediction_id)
-		    PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x]));
+		    if (_param->_have_port_depth)
+                    PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x]));
 		    PORT_WRITE(out_PREDICT_BRANCH_CONDITION            [i],_decod_instruction->_branch_condition  );
 // 		    PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE          [i],_decod_instruction->_branch_stack_write);
@@ -145,5 +176,5 @@
 		
 		    //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order)
-		    can_continue_next [x] = false; // one branch per context
+		    can_continue_next [x] = false; // one branch per context, the DS don't execute
 		  }
 
@@ -160,4 +191,6 @@
 		    if (_param->_have_port_context_id)
 		    PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID   , x);
+                    if (_param->_have_port_depth)
+		    PORT_WRITE(out_CONTEXT_EVENT_DEPTH        , depth);
 		    PORT_WRITE(out_CONTEXT_EVENT_TYPE         , _decod_instruction->_event_type    );
 		    PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot );
@@ -184,9 +217,9 @@
 	      }
 
-	    log_printf(TRACE,Decod,FUNCTION,"  - num_(decod, context, fetch) : %d %d %d",i, x, y);
-	    log_printf(TRACE,Decod,FUNCTION,"    - ifetch_ack        : %d",ifetch_ack  [x][y]);
-	    log_printf(TRACE,Decod,FUNCTION,"    - context_event_val : %d",context_event_val );
-	    log_printf(TRACE,Decod,FUNCTION,"    - predict_val       : %d",predict_val [i]   );
-	    log_printf(TRACE,Decod,FUNCTION,"    - decod_val         : %d",decod_val   [i]   );
+	    log_printf(TRACE,Decod,FUNCTION,"    - num_(decod, context, fetch) : %d %d %d",i, x, y);
+	    log_printf(TRACE,Decod,FUNCTION,"      - ifetch_ack        : %d",ifetch_ack  [x][y]);
+	    log_printf(TRACE,Decod,FUNCTION,"      - context_event_val : %d",context_event_val );
+	    log_printf(TRACE,Decod,FUNCTION,"      - predict_val       : %d",predict_val [i]   );
+	    log_printf(TRACE,Decod,FUNCTION,"      - decod_val         : %d",decod_val   [i]   );
 	    
 	    it ++;
@@ -207,7 +240,11 @@
 	PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]);
 	PORT_WRITE(out_DECOD_VAL   [i], decod_val   [i]);
-      }
-
-    log_printf(FUNC,Decod,FUNCTION,"End");
+        
+#ifdef STATISTICS
+        internal_DECOD_VAL [i] = decod_val [i];
+#endif
+      }
+
+    log_end(Decod,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp	(revision 88)
@@ -27,11 +27,12 @@
 		      "Decod",
 		      param_statistics);
-   
-    _stat_sum_inst_decod = _stat->create_variable ("sum_inst_decod" // ,"", "Sum of decod instruction"
-						   );
 
+    _stat_sum_inst_decod = _stat->create_variable("sum_inst_decod");
+    
+    
+    _stat->create_expr_average_by_cycle ("average_nb_inst_decod","sum_inst_decod","","Average of decod instruction by cycle");
+    _stat->create_expr_percent          ("percent_nb_inst_decod","average_nb_inst_decod", toString(_param->_nb_inst_decod), "Percent of decod instruction by cycle");
+  
 
-    _stat->create_expr_average_by_cycle ("average_sum_inst_decod","sum_inst_decod","","Average of decod instruction by cycle");
-    _stat->create_expr_percent          ("percent_sum_inst_decod","average_sum_inst_decod", toString(_param->_nb_inst_decod), "Percent of decod instruction by cycle");
  
     log_printf(FUNC,Decod,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp	(revision 88)
@@ -22,9 +22,9 @@
   void Decod::transition (void)
   {
-    log_printf(FUNC,Decod,FUNCTION,"Begin");
+    log_begin(Decod,FUNCTION);
 
     if (PORT_READ(in_NRESET) == 0)
       {
-	reg_CONTEXT_PRIORITY = 0;
+	_priority->reset();
 
 	for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -36,60 +36,5 @@
     else
       {
-	switch (_param->_priority)
-	  {
-// 	  case PRIORITY_STATIC :
-// 	    {
-// 	      reg_CONTEXT_PRIORITY = (reg_CONTEXT_PRIORITY+_param->_nb_context_select)%_param->_nb_context;
-// 	      break;
-// 	    }
-	  case PRIORITY_ROUND_ROBIN :
-	    {
-	      reg_CONTEXT_PRIORITY = (reg_CONTEXT_PRIORITY+1                         )%_param->_nb_context;
-	      break;
-	    }
-	  default:
-	    {
-	      break;
-	    }
-	  }
-
-	// flush list
-	select.clear();
-	
-	// Compute next scan order !!!
-	switch (_param->_load_balancing)
-	  {
-// 	  case LOAD_BALANCING_BALANCE :
-// 	    {
-// 	      for (uint32_t j=0; j<_param->_max_nb_inst_fetch; j++)
-// 		for (uint32_t i=0; i<_param->_nb_context_select; i++)
-// 		  {
-// 		    uint32_t x=(reg_CONTEXT_PRIORITY+i)%_param->_nb_context;
-		    
-// 		    // Test valid inst_fetch
-// 		    if (j < _param->_nb_inst_fetch[x])
-// 		      select.push_back(select_t(x,j));
-// 		  }
-		  
-// 	      break;
-// 	    }
-	  case LOAD_BALANCING_MAXIMUM_FOR_PRIORITY :
-	    {
-
-	      for (uint32_t i=0; i<_param->_nb_context_select; i++)
-		{
-		  uint32_t x=(reg_CONTEXT_PRIORITY+i)%_param->_nb_context;
-		  
-		  for (uint32_t j=0; j<_param->_nb_inst_fetch[x]; j++)
-		    select.push_back(select_t(x,j));
-		}
-
-	      break;
-	    }
-	  default :
-	    {
-	      break;
-	    }
-	  }
+	_priority->transition();
 
 	// Compute "next previous" address
@@ -97,8 +42,4 @@
 	  if (internal_CONTEXT_HAVE_TRANSACTION[i])
 	    {
-#ifdef STATISTICS
-	      (*_stat_sum_inst_decod) ++;
-#endif
-
 	      reg_CONTEXT_ADDRESS_PREVIOUS [i] = internal_CONTEXT_ADDRESS_PREVIOUS [i];
 	      reg_CONTEXT_IS_DELAY_SLOT    [i] = internal_CONTEXT_IS_DELAY_SLOT    [i];
@@ -107,4 +48,11 @@
 // 	for (uint32_t i=0; i<_param->_nb_context; i++)
 // 	  log_printf(TRACE,Decod,FUNCTION,"[%d] %.8x %d",i,reg_CONTEXT_ADDRESS_PREVIOUS [i], reg_CONTEXT_IS_DELAY_SLOT [i]);
+
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
+            if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i]))
+              (*_stat_sum_inst_decod) ++;
+#endif
       }
 
@@ -113,5 +61,5 @@
 #endif
 
-    log_printf(FUNC,Decod,FUNCTION,"End");
+    log_end(Decod,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp	(revision 88)
@@ -1,4 +1,3 @@
 /*
-
  * $Id$
  *
@@ -24,6 +23,6 @@
 			  uint32_t          * nb_inst_fetch                ,
 			  uint32_t            nb_inst_decod                ,
-			  uint32_t            nb_branch_speculated         ,
-			  uint32_t            size_branch_update_prediction,
+			  uint32_t          * nb_branch_speculated         ,
+// 			  uint32_t          * size_branch_update_prediction,
 			  uint32_t            nb_context_select            ,
 			  uint32_t            size_general_data            ,
@@ -31,5 +30,7 @@
 			  Tload_balancing_t   load_balancing               ,
 			  bool             ** instruction_implemeted       ,
-			  morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t))
+			  morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void),
+                          bool                is_toplevel
+                          )
   {
     log_printf(FUNC,Decod,FUNCTION,"Begin");
@@ -40,6 +41,6 @@
     _nb_branch_speculated          = nb_branch_speculated         ;
     _nb_context_select             = nb_context_select            ;
-    _size_branch_update_prediction = size_branch_update_prediction;
-    _size_general_data             = size_general_data            ;
+//  _size_branch_update_prediction = size_branch_update_prediction;
+//  _size_general_data             = size_general_data            ;
     _priority                      = priority                     ;
     _load_balancing                = load_balancing               ;
@@ -52,17 +53,27 @@
 
     
-    _max_nb_inst_fetch                     = max<uint32_t>(nb_inst_fetch,nb_context);
+    _max_nb_inst_fetch                        = max<uint32_t>(nb_inst_fetch,nb_context);
+                                              
+//  _size_address_inst                        = size_general_data-2;
 
-    _size_address_inst                     = size_general_data-2;
-    _size_context_id                       = log2(nb_context          );
-    _size_depth                            = log2(nb_branch_speculated);
-    _size_inst_ifetch_ptr                  = log2(_max_nb_inst_fetch  );
+    test();
 
-    _have_port_context_id                  = _size_context_id > 0;
-    _have_port_depth                       = _size_depth      > 0;
-    _have_port_branch_update_prediction_id = _size_branch_update_prediction > 0;
-    _have_port_inst_ifetch_ptr             = _size_inst_ifetch_ptr > 0;
-    
-    test();
+    if (is_toplevel)
+      {
+        _size_context_id                      = log2(nb_context          );
+        _size_depth                           = log2(max<uint32_t>(_nb_branch_speculated,_nb_context));
+//      _size_branch_update_prediction_id     = max<uint32_t>(_size_branch_update_prediction,_nb_context);
+        _size_inst_ifetch_ptr                 = log2(_max_nb_inst_fetch  );
+        _size_instruction_address             = size_general_data-2;
+        _size_general_data                    = size_general_data;
+
+        _have_port_context_id                 = _size_context_id > 0;
+        _have_port_depth                      = _size_depth                       > 0;
+//      _have_port_branch_update_prediction_id= _size_branch_update_prediction_id > 0;
+        _have_port_inst_ifetch_ptr            = _size_inst_ifetch_ptr             > 0;
+
+        copy ();
+      }
+
     log_printf(FUNC,Decod,FUNCTION,"End");
   };
@@ -82,4 +93,14 @@
   {
     log_printf(FUNC,Decod,FUNCTION,"Begin");
+
+    log_printf(FUNC,Decod,FUNCTION,"End");
+  };
+
+#undef  FUNCTION
+#define FUNCTION "Decod::copy"
+  void Parameters::copy (void) 
+  {
+    log_printf(FUNC,Decod,FUNCTION,"Begin");
+
     log_printf(FUNC,Decod,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp	(revision 88)
@@ -31,11 +31,11 @@
       test.error(_("nb_inst_decod must be > 0.\n"));
 
-    if ((_size_general_data != 32) and
-	(_size_general_data != 64))
-      test.error(_("size_general_data must be equal at 32 or 64 bits.\n"));
+//  if ((_size_general_data != 32) and
+//      (_size_general_data != 64))
+//    test.error(_("size_general_data must be equal at 32 or 64 bits.\n"));
 
-    if ((_nb_branch_speculated == 0) or
-	(_nb_branch_speculated > _nb_context))
-      test.error(_("nb_branch_speculated must be in [1:nb_context].\n"));
+//     if ((_nb_branch_speculated == 0) or
+// 	(_nb_branch_speculated > _nb_context))
+//       test.error(_("nb_branch_speculated must be in [1:nb_context].\n"));
 
     if ((_nb_context_select == 0) or
@@ -48,5 +48,5 @@
 
     if (sum_inst_fetch < _nb_inst_decod)
-      test.error(_("The sum of the _nb_context_select most nb_inst_fetch must be greater that _nb_inst_decod"));
+      test.error(_("The sum of the _nb_context_select most nb_inst_fetch must be greater that _nb_inst_decod\n"));
 
     if ((_priority != PRIORITY_ROUND_ROBIN))
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp	(revision 87)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp	(revision 88)
@@ -30,5 +30,5 @@
     xml.singleton_begin("nb_inst_decod                "); xml.attribut("value",toString(_nb_inst_decod                )); xml.singleton_end();
     xml.singleton_begin("nb_branch_speculated         "); xml.attribut("value",toString(_nb_branch_speculated         )); xml.singleton_end();
-    xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
+//  xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end();
     xml.singleton_begin("nb_context_select            "); xml.attribut("value",toString(_nb_context_select            )); xml.singleton_end();
     xml.singleton_begin("size_general_data            "); xml.attribut("value",toString(_size_general_data            )); xml.singleton_end();
