Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp	(revision 88)
@@ -41,4 +41,14 @@
 #endif
 
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
+
   Ifetch_queue * _Ifetch_queue = new Ifetch_queue 
     (name.c_str(),
@@ -47,5 +57,5 @@
 #endif
      _param,
-     USE_ALL);
+     _usage);
   
 #ifdef SYSTEMC
@@ -93,12 +103,12 @@
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL                        );
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK                        );
-  if (_param->_have_port_queue_ptr)
+  if (_param->_have_port_ifetch_queue_ptr)
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID            );
   INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE         ,_param->_nb_instruction);
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS        );
-  if (_param->_have_port_instruction_ptr)
+  if (_param->_have_port_inst_ifetch_ptr)
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR            );
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE               );
-  if (_param->_have_port_branch_update_prediction_id)
+  if (_param->_have_port_depth)
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
   INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL                          ,_param->_nb_instruction);
@@ -106,13 +116,13 @@
   INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION                  ,_param->_nb_instruction);
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS                      );
-  if (_param->_have_port_instruction_ptr)
+  if (_param->_have_port_inst_ifetch_ptr)
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR              );
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE                 );
-  if (_param->_have_port_branch_update_prediction_id)
+  if (_param->_have_port_depth)
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID  );
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION                    );
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL                     );
   INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK                     );
-  if (_param->_have_port_queue_ptr)
+  if (_param->_have_port_ifetch_queue_ptr)
   INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID               );
   INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION             ,_param->_nb_instruction);
@@ -180,9 +190,9 @@
 	  for (uint32_t i=0; i<_param->_nb_instruction; i++)
 	  in_ADDRESS_INSTRUCTION_ENABLE [i]      ->write(i<=nb_inst_enable);
-	  if (_param->_have_port_instruction_ptr)
+	  if (_param->_have_port_inst_ifetch_ptr)
 	  in_ADDRESS_INST_IFETCH_PTR             ->write(address%_param->_nb_instruction);
 	  in_ADDRESS_BRANCH_STATE                ->write(address%SIZE_BRANCH_STATE);
-	  if (_param->_have_port_branch_update_prediction_id)
-	  in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_branch_update_prediction);
+	  if (_param->_have_port_depth)
+	  in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth);
 
 	  // =====
@@ -241,5 +251,5 @@
 	      
 	      list_wait_decod.push_back(address);
-// 	      list_req_icache.insert(, entry_t((_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
+// 	      list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
 
 	      uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality;
@@ -252,5 +262,5 @@
 
 	      LABEL("  * list_req_icache : %d",list_req_icache.size());
-	      list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
+	      list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
 	      LABEL("  * list_req_icache : %d",list_req_icache.size());	      
 	      address += 4*_param->_nb_instruction;
@@ -292,8 +302,8 @@
 	      TEST(Tgeneral_data_t   ,out_DECOD_ADDRESS                    ->read(), addr);
 	      TEST(Tbranch_state_t   ,out_DECOD_BRANCH_STATE               ->read(),addr%SIZE_BRANCH_STATE);
-	      if (_param->_have_port_instruction_ptr)
+	      if (_param->_have_port_inst_ifetch_ptr)
 	      TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR            ->read(),addr%_param->_nb_instruction);
-	      if (_param->_have_port_branch_update_prediction_id)
-	      TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_branch_update_prediction);
+	      if (_param->_have_port_depth)
+	      TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth);
 	      if ((addr % modulo_iberr) == 0)
 	      TEST(Texception_t      ,out_DECOD_EXCEPTION                  ->read(),EXCEPTION_IFETCH_BUS_ERROR);
