Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (16 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

Location:
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src
Files:
11 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp

    r82 r88  
    3939    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
    4040
     41#if DEBUG_Branch_Target_Buffer_Register == true
     42    log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str());
     43
     44    std::cout << *param << std::endl;
     45#endif   
     46
    4147    log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation");
    4248
    … …  
    4854
    4955#ifdef STATISTICS
    50     if (_usage & USE_STATISTICS)
     56    if (usage_is_set(_usage,USE_STATISTICS))
    5157      {
    5258        log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation of statistics");
    … …  
    5763
    5864#ifdef VHDL
    59     if (_usage & USE_VHDL)
     65    if (usage_is_set(_usage,USE_VHDL))
    6066      {
    6167        // generate the vhdl
    … …  
    6773
    6874#ifdef SYSTEMC
    69     if (_usage & USE_SYSTEMC)
     75    if (usage_is_set(_usage,USE_SYSTEMC))
    7076      {
    7177        // Constant
    … …  
    108114          }
    109115
    110 # ifdef SYSTEMCASS_SPECIFIC
    111         // List dependency information
    112         for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
    113           for (uint32_t j=0; j<_param->_associativity; j++)
    114             {
    115               (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    116               if (_param->_have_port_context_id)
    117               (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    118 
    119               (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    120               if (_param->_have_port_context_id)
    121               (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    122 
    123               (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    124               if (_param->_have_port_context_id)
    125               (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    126 
    127               (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    128               if (_param->_have_port_context_id)
    129               (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    130 
    131               (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    132               if (_param->_have_port_context_id)
    133               (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    134 
    135               (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
    136               if (_param->_have_port_context_id)
    137               (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
    138           }
    139 # endif
     116// # ifdef SYSTEMCASS_SPECIFIC
     117//      // List dependency information
     118//      for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
     119//        for (uint32_t j=0; j<_param->_associativity; j++)
     120//          {
     121//            (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     122//            if (_param->_have_port_context_id)
     123//            (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     124
     125//            (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     126//            if (_param->_have_port_context_id)
     127//            (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     128
     129//            (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     130//            if (_param->_have_port_context_id)
     131//            (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     132
     133//            (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     134//            if (_param->_have_port_context_id)
     135//            (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     136
     137//            (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     138//            if (_param->_have_port_context_id)
     139//            (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     140
     141//            (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
     142//            if (_param->_have_port_context_id)
     143//            (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
     144//        }
     145// # endif
    140146
    141147        if (_param->_have_port_victim)
    … …  
    215221
    216222#ifdef STATISTICS
    217     if (_usage & USE_STATISTICS)
     223    if (usage_is_set(_usage,USE_STATISTICS))
    218224      {
    219225        statistics_deallocation();

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp

    r82 r88  
    6464      ALLOC1_VALACK_OUT(out_PREDICT_ACK         ,ACK);
    6565      ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID  ,"context_id"  ,Tcontext_t         ,_param->_size_context_id);
    66       ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS     ,"address"     ,Tgeneral_data_t    ,_param->_size_address);
     66      ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS     ,"address"     ,Tgeneral_data_t    ,_param->_size_instruction_address);
    6767
    6868      {
    … …  
    7070 
    7171        ALLOC2_SIGNAL_OUT(out_PREDICT_HIT         ,"hit"         ,Tcontrol_t         ,1);
    72         ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t    ,_param->_size_address);
    73         ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t    ,_param->_size_address);
     72        ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t    ,_param->_size_instruction_address);
     73        ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t    ,_param->_size_instruction_address);
    7474        ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION   ,"condition"   ,Tbranch_condition_t,_param->_size_branch_state);
    7575        ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE   ,"last_take"   ,Tcontrol_t         ,1);
    … …  
    9191        }
    9292      ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
    93       ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
    94       ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_address);
     93      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
     94      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
    9595      ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_state);
    9696      ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
    … …  
    112112        }
    113113      ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
    114       ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
    115       ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_address);
     114      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
     115      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
    116116      ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_state);
    117117      ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
    … …  
    119119    }
    120120
     121    if (usage_is_set(_usage,USE_SYSTEMC))
     122      {
    121123    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    122124    reg_BTB = new btb_entry_t * [_param->_size_bank];
    … …  
    133135    internal_UPDATE_NUM_BANK  = new uint32_t   [_param->_nb_inst_update];
    134136    internal_UPDATE_NUM_ENTRY = new uint32_t   [_param->_nb_inst_update];
     137      }
    135138
    136139    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
    137140
    138141#ifdef POSITION
    139     _component->generate_file();
     142    if (usage_is_set(_usage,USE_POSITION))
     143      _component->generate_file();
    140144#endif
    141145

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp

    r82 r88  
    2424    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
    2525
    26     if (_usage & USE_SYSTEMC)
     26    if (usage_is_set(_usage,USE_SYSTEMC))
    2727      {
    2828        delete    in_CLOCK ;
    … …  
    4242        delete []  in_DECOD_VAL             ;
    4343        delete [] out_DECOD_ACK             ;
     44        if (_param->_have_port_victim)
     45          {
    4446        delete [] out_DECOD_HIT             ;
    45         if (_param->_have_port_victim)
    4647        delete [] out_DECOD_HIT_INDEX       ;
    47         if (_param->_have_port_victim)
    4848        delete []  in_DECOD_VICTIM          ;
     49          }
    4950        if (_param->_have_port_context_id)
    5051        delete []  in_DECOD_CONTEXT_ID      ;
    … …  
    5758        delete []  in_UPDATE_VAL            ;
    5859        delete [] out_UPDATE_ACK            ;
     60        if (_param->_have_port_victim)
     61          {
    5962        delete [] out_UPDATE_HIT            ;
    60         if (_param->_have_port_victim)
    6163        delete [] out_UPDATE_HIT_INDEX      ;
    62         if (_param->_have_port_victim)
    6364        delete []  in_UPDATE_VICTIM         ;
     65          }
    6466        if (_param->_have_port_context_id)
    6567        delete []  in_UPDATE_CONTEXT_ID     ;

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp

    r81 r88  
    2626
    2727#ifdef STATISTICS
    28     _stat->end_cycle();
     28    if (usage_is_set(_usage,USE_STATISTICS))
     29      _stat->end_cycle();
    2930#endif   
    3031
    … …  
    3233    // Evaluation before read the ouput signal
    3334//  sc_start(0);
    34     _interfaces->testbench();
     35    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     36      _interfaces->testbench();
    3537#endif
    3638

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp

    r82 r88  
    2222  void Branch_Target_Buffer_Register::genMealy_decod (void)
    2323  {
    24     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
     24    log_begin(Branch_Target_Buffer_Register,FUNCTION);
     25    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
    2526
    2627    for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
    … …  
    5556      }
    5657
    57     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
     58    log_end(Branch_Target_Buffer_Register,FUNCTION);
    5859  };
    5960

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp

    r81 r88  
    2222  void Branch_Target_Buffer_Register::genMealy_predict (void)
    2323  {
    24     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
    25 
     24    log_begin(Branch_Target_Buffer_Register,FUNCTION);
     25    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
     26   
    2627    for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
    2728      {
     29        log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * PREDICT [%d]",i);
    2830        Tcontext_t      context   = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID  [i]):0;
    2931        Tgeneral_data_t address   = PORT_READ(in_PREDICT_ADDRESS [i]);
    … …  
    3335        Tgeneral_data_t address_offset = (address >> _param->_shift_offset)&_param->_mask_offset;
    3436
    35 //      log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_    (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset);
     37        log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * address_    (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset);
    3638
    3739        for (uint32_t j=0; j<_param->_associativity; j++)
    … …  
    4648                              (address_src_offset                >= address_offset));
    4749
    48 //          log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit);
     50            log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit);
    4951
    5052            // Hit :
    … …  
    6264      }
    6365
    64     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
     66    log_end(Branch_Target_Buffer_Register,FUNCTION);
    6567  };
    6668

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp

    r82 r88  
    2222  void Branch_Target_Buffer_Register::genMealy_update (void)
    2323  {
    24     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
     24    log_begin(Branch_Target_Buffer_Register,FUNCTION);
     25    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
    2526
    2627    for (uint32_t i=0; i<_param->_nb_inst_update; i++)
    … …  
    5556      }
    5657
    57     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
     58    log_end(Branch_Target_Buffer_Register,FUNCTION);
    5859  };
    5960

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp

    r82 r88  
    2222  void Branch_Target_Buffer_Register::transition (void)
    2323  {
    24     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
     24    log_begin(Branch_Target_Buffer_Register,FUNCTION);
     25    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
    2526
    2627    if (PORT_READ(in_NRESET) == 0)
    … …  
    8384          if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i])
    8485            {
     86              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * UPDATE [%d]",i);
     87 
    8588              bool     hit       = internal_UPDATE_HIT      [i];
    8689              uint32_t num_bank  = internal_UPDATE_NUM_BANK [i];
    … …  
    8992
    9093              // detect new branch !!! insert in branch target buffer
     94              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * hit       : %d",hit);
     95              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_bank  : %d",num_bank );
     96              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_entry : %d",num_entry);
     97
    9198              Tcounter_t accurate_new = 0;
    9299
    … …  
    123130                  accurate_new =  (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
    124131
    125                   reg_BTB[num_bank][num_entry]._val              = 1;
    126                   reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
    127                   reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
    128                   reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
    129                   reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
    130                 }
     132//                reg_BTB[num_bank][num_entry]._val              = 1;
     133//                reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
     134//                reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
     135//                reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
     136//                reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
     137                  reg_BTB[num_bank][num_entry]._address_dest_val = 0;
     138                }
    131139
    132140              // =====[ All Case ]
    133               if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
    134                 {
    135                   reg_BTB[num_bank][num_entry]._address_dest_val = 1;
    136                   reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
    137                 }
     141//            if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
     142//              {
     143//                reg_BTB[num_bank][num_entry]._address_dest_val = 1;
     144//                reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
     145//              }
     146              reg_BTB[num_bank][num_entry]._val              = 1;
     147              reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
     148              reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
     149              reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
     150              reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
     151              reg_BTB[num_bank][num_entry]._address_dest_val = 1;
     152              reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
    138153              reg_BTB[num_bank][num_entry]._accurate         = accurate_new;
    139154            }
    140155
     156#if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register
     157        log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * Dump BTB");
    141158        for (uint32_t i=0; i<_param->_size_bank; i++)
    142159          for (uint32_t j=0; j<_param->_associativity; j++)
    143             log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"[%.4d][%.4d] %d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d",
     160            log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d",
    144161                       i,j,
    145162                       reg_BTB [i][j]._val             ,
    146163                       reg_BTB [i][j]._context         ,
    147164                       reg_BTB [i][j]._address_src     ,
     165                       reg_BTB [i][j]._address_src <<2,
    148166                       reg_BTB [i][j]._address_dest_val,
    149167                       reg_BTB [i][j]._address_dest    ,
     168                       reg_BTB [i][j]._address_dest<<2 ,
    150169                       reg_BTB [i][j]._condition       ,
    151170                       reg_BTB [i][j]._last_take       ,
    152171                       reg_BTB [i][j]._accurate        );
     172#endif
    153173      }
    154    
     174
    155175#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
    156176    end_cycle ();
    157177#endif
    158178
    159     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
     179    log_end(Branch_Target_Buffer_Register,FUNCTION);
    160180  };
    161181

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp

    r81 r88  
    3030                          uint32_t   nb_inst_predict,
    3131                          uint32_t   nb_inst_decod  ,
    32                           uint32_t   nb_inst_update )
     32                          uint32_t   nb_inst_update ,
     33                          bool       is_toplevel)
    3334  {
    3435    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
    … …  
    3839    _size_buffer     = size_buffer    ;
    3940    _associativity   = associativity  ;
    40     _size_address    = size_address   ;
    4141    _size_counter    = size_counter   ;
    4242    _nb_inst_predict = nb_inst_predict;
    … …  
    4545
    4646    _size_bank       = size_buffer/associativity;
    47     _size_context_id = log2(nb_context);
    4847    _size_victim     = log2(associativity);
    4948
    50     _have_port_context_id   = (_size_context_id > 0);
    5149    _have_port_victim       = (_size_victim     > 0);
    5250
    … …  
    8179    test();
    8280
     81    if (is_toplevel)
     82      {
     83        _size_instruction_address = size_address   ;
     84        _size_context_id          = log2(nb_context);
     85        _have_port_context_id     = (_size_context_id > 0);
     86
     87        copy ();
     88      }
     89
    8390    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
    8491  };
    … …  
    101108  };
    102109
     110#undef  FUNCTION
     111#define FUNCTION "Branch_Target_Buffer_Register::copy"
     112  void Parameters::copy ()
     113  {
     114    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
     115    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
     116  };
     117
    103118}; // end namespace branch_target_buffer_register
    104119}; // end namespace branch_target_buffer

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp

    r81 r88  
    2929
    3030    if (_size_counter < 2 )
    31       test.error("size_counter must be >= 2.");
     31      test.error(_("size_counter must be >= 2.\n"));
    3232
    3333    if ((_associativity == 0) or
    3434        (_associativity > _size_buffer))
    35       test.error("associativity must be > 0 and <= size_buffer.");
     35      test.error(_("associativity must be > 0 and <= size_buffer.\n"));
    3636
    3737    if (_associativity == 1) // special case : full assoc and direct map ... also we print direct map
    38       test.information("Branch Target Buffer is Direct Map");
     38      test.information(_("Branch Target Buffer is Direct Map.\n"));
    3939    else
    4040      if (_associativity == _size_buffer)
    41         test.information("Branch Target Buffer is Full associative");
     41        test.information(_("Branch Target Buffer is Full associative.\n"));
    4242      else
    43         test.information("Branch Target Buffer is Semi associative");
     43        test.information(_("Branch Target Buffer is Semi associative.\n"));
    4444
    4545    for (uint32_t i=0; i<_nb_context; i++)
    4646      if (_associativity < (_nb_instruction[i]/2))
    47         test.error("associativity must be >= nb_instruction["+toString(i)+"]/2.");
     47        test.error(toString(_("associativity must be >= nb_instruction[%d]/2.\n"),i));
    4848
    4949    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp

    r81 r88  
    3131    xml.singleton_begin("size_buffer    "); xml.attribut("value",toString(_size_buffer    )); xml.singleton_end();
    3232    xml.singleton_begin("associativity  "); xml.attribut("value",toString(_associativity  )); xml.singleton_end();
    33     xml.singleton_begin("size_address   "); xml.attribut("value",toString(_size_address   )); xml.singleton_end();
     33//  xml.singleton_begin("size_address   "); xml.attribut("value",toString(_size_address   )); xml.singleton_end();
    3434    xml.singleton_begin("size_counter   "); xml.attribut("value",toString(_size_counter   )); xml.singleton_end();
    3535    xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end();
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