Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps	(revision 88)
@@ -16,13 +16,13 @@
 #-----[ Directory ]----------------------------------------
 
-Branch_Target_Buffer_Register_DIR			=	$(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register
+Branch_Target_Buffer_Register_DIR		=	$(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register
 
 #-----[ Library ]------------------------------------------
 
 Branch_Target_Buffer_Register_LIBRARY		= 	-lBranch_Target_Buffer_Register	\
-					$(Behavioural_LIBRARY)	
+                                                	$(Behavioural_LIBRARY)	
 
-Branch_Target_Buffer_Register_DIR_LIBRARY		=	-L$(Branch_Target_Buffer_Register_DIR)/lib	\
-					$(Behavioural_DIR_LIBRARY)
+Branch_Target_Buffer_Register_DIR_LIBRARY	=	-L$(Branch_Target_Buffer_Register_DIR)/lib	\
+                                                	$(Behavioural_DIR_LIBRARY)
 
 #-----[ Rules ]--------------------------------------------
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile	(revision 88)
@@ -24,4 +24,6 @@
 library_clean			: Branch_Target_Buffer_Register_library_clean
 
+local_clean			:
+
 include                         $(DIR_COMPONENT)/Makefile.deps
 include                         $(DIR_MORPHEO)/Behavioural/Makefile.flags
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg	(revision 88)
@@ -4,5 +4,5 @@
 1 	1	*4	# size_buffer    
 1 	1	*4	# associativity  
-32	32	*2	# size_address   
+30	30	*2	# size_address   
 2	2	+1	# size_counter   
 1	1	*4	# nb_inst_predict
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg	(revision 88)
@@ -4,5 +4,5 @@
 16	16	*4	# size_buffer    
 2 	16	*4	# associativity  
-32	32	*2	# size_address   
+30	30	*2	# size_address   
 2	2	+1	# size_counter   
 1	4	*4	# nb_inst_predict
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg	(revision 88)
@@ -7,5 +7,5 @@
 8 	64	*4	# size_buffer    
 4	8	*2	# associativity  
-32	32	*2	# size_address   
+30	30	*2	# size_address   
 2	2	+1	# size_counter   
 1	4	*4	# nb_inst_predict
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h	(revision 88)
@@ -0,0 +1,67 @@
+#ifndef test_BTB
+#define test_BTB
+
+  class entry_t
+  {
+  public : Tcontrol_t          _val             ;
+  public : Tcontext_t          _context         ;
+  public : Tcontrol_t          _address_dest_val;
+  public : Tgeneral_data_t     _address_src     ;
+  public : Tgeneral_data_t     _address_dest    ;
+  public : Tbranch_condition_t _condition       ;
+  public : Tcontrol_t          _last_take       ;
+  public : Tcounter_t          _accurate        ;
+
+  public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
+		     Tgeneral_data_t addr_test,
+		     Tcontext_t      context)
+    {
+      Tgeneral_data_t addr_src_offset  = (_address_src  >> _param->_shift_offset)&_param->_mask_offset;
+      Tgeneral_data_t addr_src_index   = (_address_src  >> _param->_shift_bank  )&_param->_mask_bank  ;
+      Tgeneral_data_t addr_src_tag     = (_address_src  >> _param->_shift_tag   );
+      
+      Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset;
+      Tgeneral_data_t addr_test_index  = (addr_test >> _param->_shift_bank  )&_param->_mask_bank  ;
+      Tgeneral_data_t addr_test_tag    = (addr_test >> _param->_shift_tag   );
+
+      bool is_hit = ( (_val             == 1               ) and
+		      (_context         == context         ) and
+		      (addr_test_tag    == addr_src_tag    ) and
+		      (addr_test_index  == addr_src_index  ) and
+		      (addr_test_offset <= addr_src_offset ));
+
+      LABEL("address_src  (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset);
+      LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit);
+      return is_hit;
+    }
+    
+  public : void print (void)
+    {
+      LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 
+	    _val             ,
+	    _context         ,
+	    _address_src     ,
+	    _address_dest_val,
+	    _address_dest    ,
+	    _condition       ,
+	    _last_take       ,
+	    _accurate        );
+    }
+    
+  };
+
+Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
+			  Tgeneral_data_t index)
+{
+  Tgeneral_data_t addr_tag     = (rand()%(_param->_associativity)) << _param->_shift_tag   ;
+  Tgeneral_data_t addr_index   = (index &_param->_mask_bank        ) << _param->_shift_bank  ;
+  Tgeneral_data_t addr_offset  = (rand()&_param->_mask_offset      ) << _param->_shift_offset;
+
+  LABEL("gen_addr     (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset);
+
+  return (addr_tag    |
+	  addr_index  |
+	  addr_offset );
+}
+
+#endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp	(revision 88)
@@ -67,5 +67,7 @@
 	 _nb_inst_predict,
 	 _nb_inst_decod  ,
-	 _nb_inst_commit );
+	 _nb_inst_commit ,
+         true // is_toplevel
+         );
       
       msg(_("%s"),param->print(1).c_str());
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp	(revision 88)
@@ -14,71 +14,5 @@
 #include "Common/include/BitManipulation.h"
 #include "Behavioural/include/Allocation.h"
-
-  class entry_t
-  {
-  public : Tcontrol_t          _val             ;
-  public : Tcontext_t          _context         ;
-  public : Tcontrol_t          _address_dest_val;
-  public : Tgeneral_data_t     _address_src     ;
-  public : Tgeneral_data_t     _address_dest    ;
-  public : Tbranch_condition_t _condition       ;
-  public : Tcontrol_t          _last_take       ;
-  public : Tcounter_t          _accurate        ;
-
-  public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
-		     Tgeneral_data_t addr_test,
-		     Tcontext_t      context)
-    {
-      Tgeneral_data_t addr_src_offset  = (_address_src  >> _param->_shift_offset)&_param->_mask_offset;
-      Tgeneral_data_t addr_src_index   = (_address_src  >> _param->_shift_bank  )&_param->_mask_bank  ;
-      Tgeneral_data_t addr_src_tag     = (_address_src  >> _param->_shift_tag   );
-      
-      Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset;
-      Tgeneral_data_t addr_test_index  = (addr_test >> _param->_shift_bank  )&_param->_mask_bank  ;
-      Tgeneral_data_t addr_test_tag    = (addr_test >> _param->_shift_tag   );
-
-      bool is_hit = ( (_val             == 1               ) and
-		      (_context         == context         ) and
-		      (addr_test_tag    == addr_src_tag    ) and
-		      (addr_test_index  == addr_src_index  ) and
-		      (addr_test_offset <= addr_src_offset ));
-
-      LABEL("address_src  (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset);
-      LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit);
-      return is_hit;
-    }
-    
-  public : void print (void)
-    {
-      LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 
-	    _val             ,
-	    _context         ,
-	    _address_src     ,
-	    _address_dest_val,
-	    _address_dest    ,
-	    _condition       ,
-	    _last_take       ,
-	    _accurate        );
-
-    }
-    
-  };
-
-
-
-Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param,
-			  Tgeneral_data_t index)
-{
-  Tgeneral_data_t addr_tag     = (rand()%(2*_param->_associativity)) << _param->_shift_tag   ;
-  Tgeneral_data_t addr_index   = (index &_param->_mask_bank        ) << _param->_shift_bank  ;
-  Tgeneral_data_t addr_offset  = (rand()&_param->_mask_offset      ) << _param->_shift_offset;
-
-  LABEL("gen_addr     (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset);
-
-  return (addr_tag    |
-	  addr_index  |
-	  addr_offset );
-}
-
+#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h"
 
 void test (string name,
@@ -90,4 +24,14 @@
   morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register 
@@ -97,5 +41,5 @@
 #endif
      _param,
-     USE_ALL);
+     _usage);
   
 #ifdef SYSTEMC
@@ -269,5 +213,5 @@
 	  in_DECOD_VICTIM          [i]->write(rand()%_param->_associativity);
 	  in_DECOD_CONTEXT_ID      [i]->write(rand()%_param->_nb_context);
-	  in_DECOD_ADDRESS_SRC     [i]->write(addr);
+	  in_DECOD_ADDRESS_SRC     [i]->write( addr);
 	  in_DECOD_ADDRESS_DEST    [i]->write(~addr);
 	  in_DECOD_CONDITION       [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
@@ -284,5 +228,5 @@
 	  in_UPDATE_VICTIM          [i]->write(rand()%_param->_associativity);
 	  in_UPDATE_CONTEXT_ID      [i]->write(rand()%_param->_nb_context);
-	  in_UPDATE_ADDRESS_SRC     [i]->write(addr);
+	  in_UPDATE_ADDRESS_SRC     [i]->write( addr);
 	  in_UPDATE_ADDRESS_DEST    [i]->write(~addr);
 	  in_UPDATE_CONDITION       [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK);
@@ -334,14 +278,19 @@
 
 	    bool hit = false;
-	    
-	    for (uint32_t j=0; j<_param->_associativity; j++)
-	      hit |= ((tab_old[j]._val         == 1) and
-		      (tab_old[j]._context     == in_DECOD_CONTEXT_ID  [i]->read()) and
-		      (tab_old[j]._address_src == in_DECOD_ADDRESS_SRC [i]->read()));
+
+	    Tptr_t k;
+	    for (k=0; k<_param->_associativity; k++)
+	      {
+		hit |= ((tab_old[k]._val         == 1) and
+			(tab_old[k]._context     == in_DECOD_CONTEXT_ID  [i]->read()) and
+			(tab_old[k]._address_src == in_DECOD_ADDRESS_SRC [i]->read()));
+
+		if (hit)
+		  break;
+	      }
 
 	    if (not hit)
 	      {
-		Tptr_t k = in_DECOD_VICTIM [i]->read();
-
+		k = in_DECOD_VICTIM [i]->read();
 		LABEL("  * miss");
 		LABEL("  * victim      : %d",k);
@@ -354,12 +303,17 @@
 		tab[k]._condition        = in_DECOD_CONDITION   [i]->read();
 		tab[k]._last_take        = in_DECOD_LAST_TAKE   [i]->read();
-		//tab[k]._accurate         = _param->_first_accurate_if_hit;
+		tab[k]._accurate         =(in_DECOD_IS_ACCURATE [i]->read())?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss;
 	      }
 	    else
 	      {
-		LABEL("  * miss");
-	      }
-	    
-	    TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit);
+		LABEL("  * hit");
+	      }
+	  
+	    if (_param->_have_port_victim)
+	      {
+	    TEST(Tcontrol_t, out_DECOD_HIT       [i]->read(), hit);
+	    if (hit)
+	    TEST(Tptr_t    , out_DECOD_HIT_INDEX [i]->read(), k);
+	      }
 	  }
 
@@ -373,15 +327,12 @@
 	    bool hit = false;
 	    
-	    Tptr_t k = 0;
-	    for (uint32_t j=0; j<_param->_associativity; j++)
-	      {
-		hit |= ((tab_old[j]._val         == 1) and
-			(tab_old[j]._context     == in_UPDATE_CONTEXT_ID  [i]->read()) and
-			(tab_old[j]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));
+	    Tptr_t k;
+	    for (k=0; k<_param->_associativity; k++)
+	      {
+		hit |= ((tab_old[k]._val         == 1) and
+			(tab_old[k]._context     == in_UPDATE_CONTEXT_ID  [i]->read()) and
+			(tab_old[k]._address_src == in_UPDATE_ADDRESS_SRC [i]->read()));
 		if (hit)
-		  {
-		    k = j;
-		    break;
-		  }
+		  break;
 	      }
 
@@ -400,5 +351,5 @@
 		tab[k]._condition        = in_UPDATE_CONDITION   [i]->read();
 		tab[k]._last_take        = in_UPDATE_LAST_TAKE   [i]->read();
-		//tab[k]._accurate         = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
+		tab[k]._accurate         = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
 	      }
 	    else
@@ -414,8 +365,26 @@
 		tab[k]._condition        = in_UPDATE_CONDITION   [i]->read();
 		tab[k]._last_take        = in_UPDATE_LAST_TAKE   [i]->read();
-		//tab[k]._accurate         = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
-	      }
-
-	    TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit);
+
+
+		Tcounter_t accurate_old = tab[k]._accurate;
+		// hit  : increase accurate
+		// miss : decrease accurate
+		Tcounter_t accurate_new = (in_UPDATE_MISS_PREDICTION [i]->read())?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old);
+		
+		// test if accurate go to the threshold
+		if ((accurate_old >= _param->_accurate_limit) and
+		    (accurate_new <  _param->_accurate_limit))
+		  accurate_new = 0;
+		
+
+		tab[k]._accurate         = accurate_new;
+	      }
+
+	    if (_param->_have_port_victim)
+	      {
+	    TEST(Tcontrol_t, out_UPDATE_HIT       [i]->read(), hit);
+	    if (hit)
+	    TEST(Tptr_t    , out_UPDATE_HIT_INDEX [i]->read(), k);
+	      }
 	  }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h	(revision 88)
@@ -31,5 +31,5 @@
   public : uint32_t   _size_buffer    ;
   public : uint32_t   _associativity  ;
-  public : uint32_t   _size_address   ;
+//public : uint32_t   _size_address   ;
   public : uint32_t   _size_counter   ;
   public : uint32_t   _nb_inst_predict;
@@ -38,8 +38,8 @@
 
   public : uint32_t   _size_bank      ;
-  public : uint32_t   _size_context_id;
+//public : uint32_t   _size_context_id;
   public : uint32_t   _size_victim    ;
 
-  public : bool       _have_port_context_id;
+//public : bool       _have_port_context_id;
   public : bool       _have_port_victim    ;
 
@@ -65,7 +65,11 @@
 			uint32_t   nb_inst_predict,
 			uint32_t   nb_inst_decod  ,
-			uint32_t   nb_inst_update );
+			uint32_t   nb_inst_update ,
+                        bool       is_toplevel=false
+                        );
 //   public : Parameters  (Parameters & param) ;
   public : ~Parameters () ;
+
+  public :        void            copy       (void);
 
   public :        Parameters_test msg_error  (void);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp	(revision 88)
@@ -39,4 +39,10 @@
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
 
+#if DEBUG_Branch_Target_Buffer_Register == true
+    log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str());
+
+    std::cout << *param << std::endl;
+#endif    
+
     log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation");
 
@@ -48,5 +54,5 @@
 
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {	
 	log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation of statistics");
@@ -57,5 +63,5 @@
 
 #ifdef VHDL
-    if (_usage & USE_VHDL)
+    if (usage_is_set(_usage,USE_VHDL))
       {
 	// generate the vhdl
@@ -67,5 +73,5 @@
 
 #ifdef SYSTEMC
-    if (_usage & USE_SYSTEMC)
+    if (usage_is_set(_usage,USE_SYSTEMC))
       {
 	// Constant
@@ -108,34 +114,34 @@
 	  }
 
-# ifdef SYSTEMCASS_SPECIFIC
-	// List dependency information
-	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
-	  for (uint32_t j=0; j<_param->_associativity; j++)
-	    {
-	      (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-
-	      (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-
-	      (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-
-	      (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-
-	      (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-
-	      (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
-	      if (_param->_have_port_context_id)
-	      (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
-	  }
-# endif
+// # ifdef SYSTEMCASS_SPECIFIC
+// 	// List dependency information
+// 	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+// 	  for (uint32_t j=0; j<_param->_associativity; j++)
+// 	    {
+// 	      (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_HIT          [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+
+// 	      (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_ADDRESS_SRC  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+
+// 	      (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+
+// 	      (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_CONDITION    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+
+// 	      (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_LAST_TAKE    [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+
+// 	      (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_ADDRESS    [i]));
+// 	      if (_param->_have_port_context_id)
+// 	      (*(out_PREDICT_IS_ACCURATE  [i][j])) (*(in_PREDICT_CONTEXT_ID [i]));
+// 	  }
+// # endif
 
 	if (_param->_have_port_victim)
@@ -215,5 +221,5 @@
 
 #ifdef STATISTICS
-    if (_usage & USE_STATISTICS)
+    if (usage_is_set(_usage,USE_STATISTICS))
       {
 	statistics_deallocation();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp	(revision 88)
@@ -64,5 +64,5 @@
       ALLOC1_VALACK_OUT(out_PREDICT_ACK         ,ACK);
       ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID  ,"context_id"  ,Tcontext_t         ,_param->_size_context_id);
-      ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS     ,"address"     ,Tgeneral_data_t    ,_param->_size_address);
+      ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS     ,"address"     ,Tgeneral_data_t    ,_param->_size_instruction_address);
 
       {
@@ -70,6 +70,6 @@
  
 	ALLOC2_SIGNAL_OUT(out_PREDICT_HIT         ,"hit"         ,Tcontrol_t         ,1);
-	ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t    ,_param->_size_address);
-	ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t    ,_param->_size_address);
+	ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t    ,_param->_size_instruction_address);
+	ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t    ,_param->_size_instruction_address);
 	ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION   ,"condition"   ,Tbranch_condition_t,_param->_size_branch_state);
 	ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE   ,"last_take"   ,Tcontrol_t         ,1);
@@ -91,6 +91,6 @@
 	}
       ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
-      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
-      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_address);
+      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
+      ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
       ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_state);
       ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
@@ -112,6 +112,6 @@
 	}
       ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID     ,"context_id"     ,Tcontext_t         ,_param->_size_context_id);
-      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_address);
-      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_address);
+      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC    ,"address_src"    ,Tgeneral_data_t    ,_param->_size_instruction_address);
+      ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST   ,"address_dest"   ,Tgeneral_data_t    ,_param->_size_instruction_address);
       ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION      ,"condition"      ,Tbranch_condition_t,_param->_size_branch_state);
       ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE      ,"last_take"      ,Tcontrol_t         ,1);
@@ -119,4 +119,6 @@
     }
 
+    if (usage_is_set(_usage,USE_SYSTEMC))
+      {
     // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
     reg_BTB = new btb_entry_t * [_param->_size_bank];
@@ -133,9 +135,11 @@
     internal_UPDATE_NUM_BANK  = new uint32_t   [_param->_nb_inst_update];
     internal_UPDATE_NUM_ENTRY = new uint32_t   [_param->_nb_inst_update];
+      }
 
     // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
 
 #ifdef POSITION
-    _component->generate_file();
+    if (usage_is_set(_usage,USE_POSITION))
+      _component->generate_file();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp	(revision 88)
@@ -24,5 +24,5 @@
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
 
-    if (_usage & USE_SYSTEMC)
+    if (usage_is_set(_usage,USE_SYSTEMC))
       {
 	delete    in_CLOCK ;
@@ -42,9 +42,10 @@
 	delete []  in_DECOD_VAL             ;
 	delete [] out_DECOD_ACK             ;
+	if (_param->_have_port_victim)
+          {
 	delete [] out_DECOD_HIT             ;
-	if (_param->_have_port_victim)
 	delete [] out_DECOD_HIT_INDEX       ;
-	if (_param->_have_port_victim)
 	delete []  in_DECOD_VICTIM          ;
+          }
 	if (_param->_have_port_context_id)
 	delete []  in_DECOD_CONTEXT_ID      ;
@@ -57,9 +58,10 @@
 	delete []  in_UPDATE_VAL            ;
 	delete [] out_UPDATE_ACK            ;
+	if (_param->_have_port_victim)
+          {
 	delete [] out_UPDATE_HIT            ;
-	if (_param->_have_port_victim)
 	delete [] out_UPDATE_HIT_INDEX      ;
-	if (_param->_have_port_victim)
 	delete []  in_UPDATE_VICTIM         ;
+          }
 	if (_param->_have_port_context_id)
 	delete []  in_UPDATE_CONTEXT_ID     ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp	(revision 88)
@@ -26,5 +26,6 @@
 
 #ifdef STATISTICS
-    _stat->end_cycle();
+    if (usage_is_set(_usage,USE_STATISTICS))
+      _stat->end_cycle();
 #endif    
 
@@ -32,5 +33,6 @@
     // Evaluation before read the ouput signal
 //  sc_start(0);
-    _interfaces->testbench();
+    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
+      _interfaces->testbench();
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp	(revision 88)
@@ -22,5 +22,6 @@
   void Branch_Target_Buffer_Register::genMealy_decod (void)
   {
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
+    log_begin(Branch_Target_Buffer_Register,FUNCTION);
+    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
 
     for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
@@ -55,5 +56,5 @@
       }
 
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+    log_end(Branch_Target_Buffer_Register,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp	(revision 88)
@@ -22,8 +22,10 @@
   void Branch_Target_Buffer_Register::genMealy_predict (void)
   {
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
-
+    log_begin(Branch_Target_Buffer_Register,FUNCTION);
+    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
+    
     for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
       {
+ 	log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * PREDICT [%d]",i);
 	Tcontext_t      context   = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID  [i]):0;
 	Tgeneral_data_t address   = PORT_READ(in_PREDICT_ADDRESS [i]);
@@ -33,5 +35,5 @@
 	Tgeneral_data_t address_offset = (address >> _param->_shift_offset)&_param->_mask_offset;
 
-// 	log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_    (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset);
+ 	log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * address_    (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset);
 
 	for (uint32_t j=0; j<_param->_associativity; j++)
@@ -46,5 +48,5 @@
 			      (address_src_offset                >= address_offset));
 
-// 	    log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit);
+            log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit);
 
 	    // Hit :
@@ -62,5 +64,5 @@
       }
 
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+    log_end(Branch_Target_Buffer_Register,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp	(revision 88)
@@ -22,5 +22,6 @@
   void Branch_Target_Buffer_Register::genMealy_update (void)
   {
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
+    log_begin(Branch_Target_Buffer_Register,FUNCTION);
+    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
 
     for (uint32_t i=0; i<_param->_nb_inst_update; i++)
@@ -55,5 +56,5 @@
       }
 
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+    log_end(Branch_Target_Buffer_Register,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp	(revision 88)
@@ -22,5 +22,6 @@
   void Branch_Target_Buffer_Register::transition (void)
   {
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
+    log_begin(Branch_Target_Buffer_Register,FUNCTION);
+    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -83,4 +84,6 @@
 	  if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i])
 	    {
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * UPDATE [%d]",i);
+ 
 	      bool     hit       = internal_UPDATE_HIT      [i];
 	      uint32_t num_bank  = internal_UPDATE_NUM_BANK [i];
@@ -89,4 +92,8 @@
 
 	      // detect new branch !!! insert in branch target buffer
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * hit       : %d",hit);
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_bank  : %d",num_bank );
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_entry : %d",num_entry);
+
 	      Tcounter_t accurate_new = 0;
 
@@ -123,39 +130,52 @@
 		  accurate_new =  (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
 
-		  reg_BTB[num_bank][num_entry]._val              = 1;
-		  reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
-		  reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
-		  reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
-		  reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
-		}
+// 		  reg_BTB[num_bank][num_entry]._val              = 1;
+// 		  reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+// 		  reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
+// 		  reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
+// 		  reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
+                  reg_BTB[num_bank][num_entry]._address_dest_val = 0;
+                }
 
 	      // =====[ All Case ]
-	      if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
-		{
-		  reg_BTB[num_bank][num_entry]._address_dest_val = 1;
-		  reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
-		}
+// 	      if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
+// 		{
+// 		  reg_BTB[num_bank][num_entry]._address_dest_val = 1;
+// 		  reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
+// 		}
+              reg_BTB[num_bank][num_entry]._val              = 1;
+              reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+              reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
+              reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
+              reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
+              reg_BTB[num_bank][num_entry]._address_dest_val = 1;
+              reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
 	      reg_BTB[num_bank][num_entry]._accurate         = accurate_new;
 	    }
 
+#if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register
+        log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * Dump BTB");
 	for (uint32_t i=0; i<_param->_size_bank; i++)
 	  for (uint32_t j=0; j<_param->_associativity; j++)
-	    log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"[%.4d][%.4d] %d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 
+	    log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", 
 		       i,j,
 		       reg_BTB [i][j]._val             ,
 		       reg_BTB [i][j]._context         ,
 		       reg_BTB [i][j]._address_src     ,
+		       reg_BTB [i][j]._address_src <<2,
 		       reg_BTB [i][j]._address_dest_val,
 		       reg_BTB [i][j]._address_dest    ,
+		       reg_BTB [i][j]._address_dest<<2 ,
 		       reg_BTB [i][j]._condition       ,
 		       reg_BTB [i][j]._last_take       ,
 		       reg_BTB [i][j]._accurate        );
+#endif
       }
-    
+
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     end_cycle ();
 #endif
 
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+    log_end(Branch_Target_Buffer_Register,FUNCTION);
   };
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp	(revision 88)
@@ -30,5 +30,6 @@
 			  uint32_t   nb_inst_predict,
 			  uint32_t   nb_inst_decod  ,
-			  uint32_t   nb_inst_update )
+			  uint32_t   nb_inst_update ,
+                          bool       is_toplevel)
   {
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
@@ -38,5 +39,4 @@
     _size_buffer     = size_buffer    ;
     _associativity   = associativity  ;
-    _size_address    = size_address   ;
     _size_counter    = size_counter   ;
     _nb_inst_predict = nb_inst_predict;
@@ -45,8 +45,6 @@
 
     _size_bank       = size_buffer/associativity;
-    _size_context_id = log2(nb_context);
     _size_victim     = log2(associativity);
 
-    _have_port_context_id   = (_size_context_id > 0);
     _have_port_victim       = (_size_victim     > 0);
 
@@ -81,4 +79,13 @@
     test();
 
+    if (is_toplevel)
+      {
+        _size_instruction_address = size_address   ;
+        _size_context_id          = log2(nb_context);
+        _have_port_context_id     = (_size_context_id > 0);
+
+        copy ();
+      }
+
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
   };
@@ -101,4 +108,12 @@
   };
 
+#undef  FUNCTION
+#define FUNCTION "Branch_Target_Buffer_Register::copy"
+  void Parameters::copy () 
+  {
+    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
+    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+  };
+
 }; // end namespace branch_target_buffer_register
 }; // end namespace branch_target_buffer
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp	(revision 88)
@@ -29,21 +29,21 @@
 
     if (_size_counter < 2 )
-      test.error("size_counter must be >= 2.");
+      test.error(_("size_counter must be >= 2.\n"));
 
     if ((_associativity == 0) or
 	(_associativity > _size_buffer))
-      test.error("associativity must be > 0 and <= size_buffer.");
+      test.error(_("associativity must be > 0 and <= size_buffer.\n"));
 
     if (_associativity == 1) // special case : full assoc and direct map ... also we print direct map
-      test.information("Branch Target Buffer is Direct Map");
+      test.information(_("Branch Target Buffer is Direct Map.\n"));
     else
       if (_associativity == _size_buffer)
-	test.information("Branch Target Buffer is Full associative");
+	test.information(_("Branch Target Buffer is Full associative.\n"));
       else
-	test.information("Branch Target Buffer is Semi associative");
+	test.information(_("Branch Target Buffer is Semi associative.\n"));
 
     for (uint32_t i=0; i<_nb_context; i++)
       if (_associativity < (_nb_instruction[i]/2))
-	test.error("associativity must be >= nb_instruction["+toString(i)+"]/2.");
+	test.error(toString(_("associativity must be >= nb_instruction[%d]/2.\n"),i));
 
     log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp	(revision 82)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp	(revision 88)
@@ -31,5 +31,5 @@
     xml.singleton_begin("size_buffer    "); xml.attribut("value",toString(_size_buffer    )); xml.singleton_end();
     xml.singleton_begin("associativity  "); xml.attribut("value",toString(_associativity  )); xml.singleton_end();
-    xml.singleton_begin("size_address   "); xml.attribut("value",toString(_size_address   )); xml.singleton_end();
+//  xml.singleton_begin("size_address   "); xml.attribut("value",toString(_size_address   )); xml.singleton_end();
     xml.singleton_begin("size_counter   "); xml.attribut("value",toString(_size_counter   )); xml.singleton_end();
     xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end();
