Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (16 years ago)
- Location:
- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src
- Files:
-
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp
r82 r88 21 21 #define FUNCTION "Update_Prediction_Table::Parameters" 22 22 Parameters::Parameters (uint32_t nb_context , 23 uint32_t * size_queue , 23 uint32_t * size_upt_queue , 24 uint32_t * size_ufpt_queue , 24 25 uint32_t size_address , 25 26 uint32_t nb_inst_predict , … … 28 29 uint32_t nb_inst_update , 29 30 uint32_t size_history , 30 uint32_t * size_ras_index ) 31 uint32_t * size_ras_index , 32 bool is_toplevel): 33 _not_accurate_block_predict (false) 31 34 { 32 35 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 33 36 34 37 _nb_context = nb_context ; 35 _size_queue = size_queue ; 36 _size_address = size_address ; 38 _size_upt_queue = size_upt_queue ; 39 _size_ufpt_queue = size_ufpt_queue ; 40 // _size_address = size_address ; 37 41 _nb_inst_predict = nb_inst_predict ; 38 42 _nb_inst_decod = nb_inst_decod ; … … 42 46 _size_ras_index = size_ras_index ; 43 47 44 _size_context_id = log2(nb_context);45 _size_depth = new uint32_t[_nb_context];46 _have_port_depth = new bool [_nb_context];47 for (uint32_t i=0; i<_nb_context; i++)48 {49 _size_depth [i] = log2(_size_queue[i]);50 _have_port_depth [i] = (_size_depth [i] > 0);51 }52 _max_size_depth = max<uint32_t>(_size_depth,_nb_context);53 48 _max_size_ras_index = max<uint32_t>(_size_ras_index,nb_context); 54 49 55 _have_port_context_id = _size_context_id> 0;56 _have_port_max_depth = _max_size_depth > 0;57 50 _have_port_history = _size_history > 0; 51 52 test(); 53 54 if (is_toplevel) 55 { 56 _size_instruction_address = size_address; 57 _size_context_id = log2(nb_context); 58 _size_depth = log2(max<uint32_t>(_size_upt_queue,_nb_context)); 59 60 _have_port_context_id = _size_context_id> 0; 61 _have_port_depth = _size_depth > 0; 62 63 copy (); 64 } 58 65 59 test();60 66 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 61 67 }; … … 75 81 { 76 82 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 77 delete [] _size_depth ; 78 delete [] _have_port_depth; 83 // delete [] _size_depth ; 84 // delete [] _have_port_depth; 85 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 86 }; 87 88 #undef FUNCTION 89 #define FUNCTION "Update_Prediction_Table::copy" 90 void Parameters::copy (void) 91 { 92 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 79 93 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 80 94 }; -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_msg_error.cpp
r82 r88 8 8 #include "Behavioural/include/Types.h" 9 9 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h" 10 #include "Common/include/Max.h" 10 11 #include <sstream> 11 12 … … 27 28 Parameters_test test ("Update_Prediction_Table"); 28 29 29 if (morpheo::behavioural::test<Tdepth_t>(_max_size_depth) == false) 30 test.error("type \"Tdepth_t\" is too small."); 31 30 for (uint32_t i=0; i<_nb_context; i++) 31 if (_size_ufpt_queue [i] > _size_upt_queue [i]) 32 test.error(toString(_("context \"%d\" : size_upt_queue must be >= at size_ufpt_queue\n"),i)); 33 32 34 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 33 35 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_print.cpp
r81 r88 28 28 xml.balise_open("update_prediction_table"); 29 29 xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); 30 30 // xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); 31 31 xml.singleton_begin("nb_inst_predict "); xml.attribut("value",toString(_nb_inst_predict )); xml.singleton_end(); 32 32 xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); … … 40 40 xml. attribut("id" ,toString(i)); 41 41 xml. balise_open_end(); 42 xml. singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue [i])); xml.singleton_end(); 42 xml. singleton_begin("size_upt_queue "); xml.attribut("value",toString(_size_upt_queue [i])); xml.singleton_end(); 43 xml. singleton_begin("size_ufpt_queue "); xml.attribut("value",toString(_size_ufpt_queue [i])); xml.singleton_end(); 43 44 xml. singleton_begin("size_ras_index "); xml.attribut("value",toString(_size_ras_index [i])); xml.singleton_end(); 44 45 xml. balise_close(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp
r82 r88 40 40 usage_environment(_usage); 41 41 42 #if DEBUG_Update_Prediction_Table == true 43 log_printf(INFO,Update_Prediction_Table,FUNCTION,_("<%s> Parameters"),_name.c_str()); 44 45 std::cout << *param << std::endl; 46 #endif 47 42 48 log_printf(INFO,Update_Prediction_Table,FUNCTION,"Allocation"); 43 49 … … 49 55 50 56 #ifdef STATISTICS 51 if ( _usage & USE_STATISTICS)57 if (usage_is_set(_usage,USE_STATISTICS)) 52 58 { 53 59 log_printf(INFO,Update_Prediction_Table,FUNCTION,"Allocation of statistics"); … … 58 64 59 65 #ifdef VHDL 60 if ( _usage & USE_VHDL)66 if (usage_is_set(_usage,USE_VHDL)) 61 67 { 62 68 // generate the vhdl … … 68 74 69 75 #ifdef SYSTEMC 70 if ( _usage & USE_SYSTEMC)76 if (usage_is_set(_usage,USE_SYSTEMC)) 71 77 { 72 78 … … 91 97 SC_METHOD (genMoore); 92 98 dont_initialize (); 93 sensitive << (*(in_CLOCK)).neg(); 99 sensitive << (*(in_CLOCK)).neg(); // use internal register 94 100 95 101 # ifdef SYSTEMCASS_SPECIFIC … … 106 112 if (_param->_have_port_context_id) 107 113 sensitive << (*(in_PREDICT_CONTEXT_ID [i])); 108 sensitive << (*(in_PREDICT_BTB_IS_ACCURATE [i]));114 // sensitive << (*(in_PREDICT_BTB_IS_ACCURATE [i])); 109 115 } 110 116 … … 128 134 if (_param->_have_port_context_id) 129 135 sensitive << (*(in_DECOD_CONTEXT_ID [i])); 130 sensitive << (*(in_DECOD_MISS_IFETCH [i]))131 << (*(in_DECOD_MISS_DECOD [i]));132 136 } 133 137 … … 136 140 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 137 141 { 138 (*(out_DECOD_ACK [i])) (*(in_DECOD_MISS_IFETCH [i]));139 (*(out_DECOD_ACK [i])) (*(in_DECOD_MISS_DECOD [i]));140 142 if (_param->_have_port_context_id) 141 143 (*(out_DECOD_ACK [i])) (*(in_DECOD_CONTEXT_ID [i])); … … 152 154 if (_param->_have_port_context_id) 153 155 sensitive << (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); 154 if (_param->_have_port_ max_depth)156 if (_param->_have_port_depth) 155 157 sensitive << (*(in_BRANCH_COMPLETE_DEPTH [i])); 156 158 sensitive << (*(in_BRANCH_COMPLETE_FLAG [i])) … … 164 166 if (_param->_have_port_context_id) 165 167 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); 166 if (_param->_have_port_ max_depth)168 if (_param->_have_port_depth) 167 169 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 168 170 (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); … … 171 173 if (_param->_have_port_context_id) 172 174 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); 173 if (_param->_have_port_ max_depth)175 if (_param->_have_port_depth) 174 176 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 175 177 (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); … … 177 179 if (_param->_have_port_context_id) 178 180 (*(out_BRANCH_COMPLETE_ADDRESS_SRC [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); 179 if (_param->_have_port_ max_depth)181 if (_param->_have_port_depth) 180 182 (*(out_BRANCH_COMPLETE_ADDRESS_SRC [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 181 183 182 184 if (_param->_have_port_context_id) 183 185 (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); 184 if (_param->_have_port_ max_depth)186 if (_param->_have_port_depth) 185 187 (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); 186 188 (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); … … 200 202 201 203 #ifdef STATISTICS 202 if ( _usage & USE_STATISTICS)204 if (usage_is_set(_usage,USE_STATISTICS)) 203 205 { 204 206 statistics_deallocation(); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
r82 r88 63 63 ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); 64 64 ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 65 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); 66 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); 65 ALLOC1_SIGNAL_OUT(out_PREDICT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 66 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); 67 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); 67 68 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); 68 69 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); 69 70 ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"btb_is_accurate" ,Tcontrol_t ,1); 70 71 ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_HISTORY ,"dir_history" ,Thistory_t ,_param->_size_history); 71 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_ address);72 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 72 73 ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 73 // ALLOC1_SIGNAL_OUT(out_PREDICT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);74 74 } 75 75 76 76 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 77 77 { 78 ALLOC1_INTERFACE("decod", IN,SOUTH, "decod", _param->_nb_inst_ predict);78 ALLOC1_INTERFACE("decod", IN,SOUTH, "decod", _param->_nb_inst_decod); 79 79 80 80 ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); 81 81 ALLOC1_VALACK_OUT(out_DECOD_ACK ,ACK); 82 82 ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 83 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_ address);84 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_ address);83 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); 84 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); 85 85 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); 86 86 ALLOC1_SIGNAL_IN ( in_DECOD_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); 87 ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_ address);87 ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 88 88 ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 89 89 ALLOC1_SIGNAL_IN ( in_DECOD_MISS_IFETCH ,"miss_ifetch" ,Tcontrol_t ,1); 90 90 ALLOC1_SIGNAL_IN ( in_DECOD_MISS_DECOD ,"miss_decod" ,Tcontrol_t ,1); 91 ALLOC1_SIGNAL_IN ( in_DECOD_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_ max_size_depth);91 ALLOC1_SIGNAL_IN ( in_DECOD_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 92 92 // ALLOC1_SIGNAL_OUT(out_DECOD_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 93 ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); 93 94 } 94 95 … … 100 101 ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_ACK ,ACK); 101 102 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 102 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_ max_size_depth);103 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_ address);103 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 104 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); 104 105 ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t,1); 105 106 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 106 107 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); 107 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_ address);108 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_ address);108 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); 109 ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 109 110 } 110 111 … … 116 117 ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); 117 118 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); 118 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_ max_size_depth);119 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); 119 120 // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); 120 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_ address);121 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_ address);121 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); 122 ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); 122 123 } 123 124 … … 132 133 ALLOC1_SIGNAL_OUT(out_UPDATE_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); 133 134 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); 134 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_ address);135 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_ address);135 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); 136 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); 136 137 ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); 137 138 ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_VAL ,"dir_val" ,Tcontrol_t ,1); … … 139 140 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_VAL ,"ras_val" ,Tcontrol_t ,1); 140 141 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PUSH ,"ras_push" ,Tcontrol_t ,1); 141 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_ address);142 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); 142 143 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); 143 144 ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); … … 147 148 { 148 149 ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); 149 150 ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"TAIL" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]); 151 ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH,"NB_BRANCH",Tdepth_t,_param->_size_depth[alloc_signal_it1]+1); 152 } 153 150 ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t,_param->_size_depth); 151 ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"MIN" ,Tdepth_t,_param->_size_depth); 152 ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t,_param->_size_depth+1); 153 } 154 155 if (usage_is_set(_usage,USE_SYSTEMC)) 156 { 154 157 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 155 internal_PREDICT_ACK = new Tcontrol_t [_param->_nb_inst_predict]; 156 internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod]; 157 internal_BRANCH_COMPLETE_ACK = new Tcontrol_t [_param->_nb_inst_branch_complete]; 158 internal_BRANCH_COMPLETE_MISS_PREDICTION = new Tcontrol_t [_param->_nb_inst_branch_complete]; 159 internal_BRANCH_COMPLETE_TAKE = new Tcontrol_t [_param->_nb_inst_branch_complete]; 160 internal_BRANCH_COMPLETE_ADDRESS_DEST = new Taddress_t [_param->_nb_inst_branch_complete]; 161 internal_BRANCH_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; 162 internal_BRANCH_EVENT_DEPTH = new Tdepth_t [_param->_nb_context]; 163 internal_UPDATE_VAL = new Tcontrol_t [_param->_nb_inst_update]; 164 internal_UPDATE_CONTEXT_ID = new Tcontext_t [_param->_nb_inst_update]; 165 internal_UPDATE_DEPTH = new Tdepth_t [_param->_nb_inst_update]; 158 ALLOC1(internal_PREDICT_ACK ,Tcontrol_t,_param->_nb_inst_predict); 159 ALLOC1(internal_PREDICT_UPDATE_PREDICTION_ID ,Tdepth_t ,_param->_nb_inst_predict); 160 ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod); 161 ALLOC1(internal_DECOD_UPT_PTR_WRITE ,uint32_t ,_param->_nb_inst_decod); 162 ALLOC1(internal_BRANCH_COMPLETE_ACK ,Tcontrol_t,_param->_nb_inst_branch_complete); 163 ALLOC1(internal_BRANCH_COMPLETE_MISS_PREDICTION ,Tcontrol_t,_param->_nb_inst_branch_complete); 164 ALLOC1(internal_BRANCH_COMPLETE_TAKE ,Tcontrol_t,_param->_nb_inst_branch_complete); 165 ALLOC1(internal_BRANCH_COMPLETE_ADDRESS_DEST ,Taddress_t,_param->_nb_inst_branch_complete); 166 ALLOC1(internal_BRANCH_EVENT_VAL ,Tcontrol_t,_param->_nb_context); 167 ALLOC1(internal_BRANCH_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); 168 ALLOC1(internal_UPDATE_VAL ,Tcontrol_t,_param->_nb_inst_update); 169 ALLOC1(internal_UPDATE_VAL_WITHOUT_ACK ,Tcontrol_t,_param->_nb_inst_update); 170 ALLOC1(internal_UPDATE_CONTEXT_ID ,Tcontext_t,_param->_nb_inst_update); 171 ALLOC1(internal_UPDATE_FROM_UFPT ,bool ,_param->_nb_inst_update); 172 ALLOC1(internal_UPDATE_DEPTH ,Tdepth_t ,_param->_nb_inst_update); 173 ALLOC1(internal_UPDATE_RAS ,bool ,_param->_nb_inst_update); 166 174 167 175 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 168 reg_TOP = new uint32_t [_param->_nb_context]; 169 reg_BOTTOM = new uint32_t [_param->_nb_context]; 170 reg_NB_ELT = new uint32_t [_param->_nb_context]; 171 reg_NB_ELT_UPDATE = new uint32_t [_param->_nb_context]; 172 reg_NB_ELT_NEED_UPDATE = new uint32_t [_param->_nb_context]; 173 reg_UPDATE_PREDICTION_TABLE = new entry_t * [_param->_nb_context]; 174 for (uint32_t i=0; i<_param->_nb_context; i++) 175 { 176 #ifndef NO_INIT 177 reg_TOP [i] = 0; 178 #endif 179 reg_UPDATE_PREDICTION_TABLE [i] = new entry_t [_param->_size_queue[i]]; 176 177 ALLOC1(reg_IS_ACCURATE ,bool ,_param->_nb_context); 178 179 ALLOC2(reg_UPDATE_FETCH_PREDICTION_TABLE,ufpt_entry_t ,_param->_nb_context,_param->_size_ufpt_queue[it1]); 180 ALLOC1(reg_UFPT_BOTTOM ,uint32_t ,_param->_nb_context); 181 ALLOC1(reg_UFPT_TOP ,uint32_t ,_param->_nb_context); 182 ALLOC1(reg_UFPT_UPDATE ,uint32_t ,_param->_nb_context); 183 ALLOC1(reg_UFPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); 184 185 ALLOC2(reg_UPDATE_PREDICTION_TABLE ,upt_entry_t ,_param->_nb_context,_param->_size_upt_queue[it1]); 186 ALLOC1(reg_UPT_BOTTOM ,uint32_t ,_param->_nb_context); 187 ALLOC1(reg_UPT_TOP ,uint32_t ,_param->_nb_context); 188 ALLOC1(reg_UPT_UPDATE ,uint32_t ,_param->_nb_context); 189 ALLOC1(reg_UPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); 190 191 ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); 192 ALLOC1(reg_EVENT_RAS_CORRUPTED ,Tcontrol_t ,_param->_nb_context); 193 ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); 194 ALLOC1(reg_EVENT_ADDRESS_SRC_VAL ,Tcontrol_t ,_param->_nb_context); 195 ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); 180 196 } 197 181 198 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 182 199 183 200 #ifdef POSITION 184 _component->generate_file(); 201 if (usage_is_set(_usage,USE_POSITION)) 202 _component->generate_file(); 185 203 #endif 186 204 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
r82 r88 7 7 8 8 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" 9 #include "Behavioural/include/Allocation.h" 9 10 10 11 namespace morpheo { … … 42 43 delete [] in_PREDICT_RAS_ADDRESS ; 43 44 delete [] in_PREDICT_RAS_INDEX ; 44 //if (_param->_have_port_depth)45 //delete [] out_PREDICT_UPDATE_PREDICTION_ID;45 if (_param->_have_port_depth) 46 delete [] out_PREDICT_UPDATE_PREDICTION_ID; 46 47 47 48 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 58 59 delete [] in_DECOD_MISS_IFETCH ; 59 60 delete [] in_DECOD_MISS_DECOD ; 60 if (_param->_have_port_ max_depth)61 if (_param->_have_port_depth) 61 62 delete [] in_DECOD_UPDATE_PREDICTION_ID ; 62 63 // if (_param->_have_port_depth) 63 64 // delete [] out_DECOD_DEPTH ; 65 delete [] in_DECOD_IS_ACCURATE ; 64 66 65 67 // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 68 70 if (_param->_have_port_context_id) 69 71 delete [] in_BRANCH_COMPLETE_CONTEXT_ID ; 70 if (_param->_have_port_ max_depth)72 if (_param->_have_port_depth) 71 73 delete [] in_BRANCH_COMPLETE_DEPTH ; 72 74 delete [] in_BRANCH_COMPLETE_ADDRESS ; … … 82 84 // if (_param->_have_port_context_id) 83 85 // delete [] in_BRANCH_EVENT_CONTEXT_ID ; 84 // if (_param->_have_port_ max_depth)86 // if (_param->_have_port_depth) 85 87 // delete [] in_BRANCH_EVENT_DEPTH ; 86 88 // delete [] out_BRANCH_EVENT_MISS_PREDICTION; … … 109 111 110 112 // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 111 if (_param->_have_port_ max_depth)113 if (_param->_have_port_depth) 112 114 { 113 delete [] out_DEPTH_ NB_BRANCH;114 delete [] out_DEPTH_ TAIL;115 delete [] out_DEPTH_CURRENT; 116 delete [] out_DEPTH_MIN; 115 117 } 116 } 117 118 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 119 delete [] internal_PREDICT_ACK ; 120 delete [] internal_DECOD_ACK ; 121 delete [] internal_BRANCH_COMPLETE_ACK ; 122 delete [] internal_BRANCH_COMPLETE_MISS_PREDICTION ; 123 delete [] internal_BRANCH_COMPLETE_TAKE ; 124 delete [] internal_BRANCH_COMPLETE_ADDRESS_DEST ; 125 delete [] internal_BRANCH_EVENT_VAL ; 126 delete [] internal_BRANCH_EVENT_DEPTH ; 127 delete [] internal_UPDATE_VAL ; 128 delete [] internal_UPDATE_CONTEXT_ID ; 129 delete [] internal_UPDATE_DEPTH ; 130 131 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 132 delete [] reg_TOP; 133 delete [] reg_BOTTOM; 134 delete [] reg_NB_ELT; 135 delete [] reg_NB_ELT_UPDATE; 136 delete [] reg_NB_ELT_NEED_UPDATE; 137 for (uint32_t i=0; i<_param->_nb_context; i++) 138 delete [] reg_UPDATE_PREDICTION_TABLE [i]; 139 delete [] reg_UPDATE_PREDICTION_TABLE; 118 delete [] out_DEPTH_MAX; 119 120 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 121 DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); 122 DELETE1(internal_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict); 123 DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod); 124 DELETE1(internal_DECOD_UPT_PTR_WRITE ,_param->_nb_inst_decod); 125 DELETE1(internal_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); 126 DELETE1(internal_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); 127 DELETE1(internal_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); 128 DELETE1(internal_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); 129 DELETE1(internal_BRANCH_EVENT_VAL ,_param->_nb_context); 130 DELETE1(internal_BRANCH_EVENT_DEPTH ,_param->_nb_context); 131 DELETE1(internal_UPDATE_VAL ,_param->_nb_inst_update); 132 DELETE1(internal_UPDATE_VAL_WITHOUT_ACK ,_param->_nb_inst_update); 133 DELETE1(internal_UPDATE_CONTEXT_ID ,_param->_nb_inst_update); 134 DELETE1(internal_UPDATE_FROM_UFPT ,_param->_nb_inst_update); 135 DELETE1(internal_UPDATE_DEPTH ,_param->_nb_inst_update); 136 DELETE1(internal_UPDATE_RAS ,_param->_nb_inst_update); 137 138 // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 139 DELETE1(reg_IS_ACCURATE ,_param->_nb_context); 140 141 DELETE2(reg_UPDATE_FETCH_PREDICTION_TABLE,_param->_nb_context,_param->_size_ufpt_queue[it1]); 142 DELETE1(reg_UFPT_BOTTOM ,_param->_nb_context); 143 DELETE1(reg_UFPT_TOP ,_param->_nb_context); 144 DELETE1(reg_UFPT_UPDATE ,_param->_nb_context); 145 DELETE1(reg_UFPT_NB_NEED_UPDATE ,_param->_nb_context); 146 147 DELETE2(reg_UPDATE_PREDICTION_TABLE ,_param->_nb_context,_param->_size_upt_queue[it1]); 148 DELETE1(reg_UPT_BOTTOM ,_param->_nb_context); 149 DELETE1(reg_UPT_TOP ,_param->_nb_context); 150 DELETE1(reg_UPT_UPDATE ,_param->_nb_context); 151 DELETE1(reg_UPT_NB_NEED_UPDATE ,_param->_nb_context); 152 153 DELETE1(reg_EVENT_STATE ,_param->_nb_context); 154 DELETE1(reg_EVENT_RAS_CORRUPTED ,_param->_nb_context); 155 DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); 156 DELETE1(reg_EVENT_ADDRESS_SRC_VAL ,_param->_nb_context); 157 DELETE1(reg_EVENT_ADDRESS_DEST ,_param->_nb_context); 158 } 140 159 141 160 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_end_cycle.cpp
r81 r88 25 25 26 26 #ifdef STATISTICS 27 _stat->end_cycle(); 27 if (usage_is_set(_usage,USE_STATISTICS)) 28 _stat->end_cycle(); 28 29 #endif 29 30 … … 31 32 // Evaluation before read the ouput signal 32 33 // sc_start(0); 34 if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) 33 35 _interfaces->testbench(); 34 36 #endif -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
r82 r88 22 22 void Update_Prediction_Table::genMealy_branch_complete (void) 23 23 { 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 24 log_begin(Update_Prediction_Table,FUNCTION); 25 log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); 25 26 26 27 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 28 #ifdef DEBUG_TEST 29 // just to don't have exception in not transaction 30 if (PORT_READ(in_BRANCH_COMPLETE_VAL [i])) 31 #endif 27 32 { 33 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE [%d]",i); 34 28 35 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 29 Tdepth_t depth = (_param->_have_port_ max_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;36 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 30 37 Tcontrol_t miss = false; 31 38 Tcontrol_t take = reg_UPDATE_PREDICTION_TABLE [context][depth]._last_take ; 32 39 Taddress_t addr_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 33 40 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition ; 41 42 Tcontrol_t flag = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]); 43 Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); 44 45 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 46 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); 47 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); 48 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",flag); 49 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_good : %.8x",addr_good); 50 51 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * (before)"); 52 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 53 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); 54 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_dest : %.8x",addr_dest); 34 55 35 56 switch (condition) … … 39 60 { 40 61 //miss : always hit 41 //addr_dest : know in decod stage 62 //addr_dest : compute in decod stage 63 64 #ifdef DEBUG_TEST 65 if (take != 1) 66 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); 67 if (addr_dest != addr_good) 68 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 69 #endif 70 42 71 break; 43 72 } 44 73 case BRANCH_CONDITION_FLAG_UNSET : // l.bnf 45 74 { 46 Tcontrol_t take_good = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]) == 0; 75 //addr_dest : compute in decod stage 76 //miss if the direction is bad 77 Tcontrol_t take_good = not flag; // flag set = not take 78 47 79 miss = (take != take_good); 48 80 take = take_good; 49 //addr_dest : know in decod stage 81 82 #ifdef DEBUG_TEST 83 if (addr_dest != addr_good) 84 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 85 #endif 86 50 87 break; 51 88 } 52 89 case BRANCH_CONDITION_FLAG_SET : // l.bf 53 90 { 54 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG_SET"); 55 56 Tcontrol_t take_good = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]) == 1; 91 //addr_dest : compute in decod stage 92 //miss if the direction is bad 93 Tcontrol_t take_good = flag; // flag set = take 94 57 95 miss = (take != take_good); 58 96 take = take_good; 59 97 60 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",PORT_READ(in_BRANCH_COMPLETE_FLAG [i])); 61 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take_good : %d",take_good); 62 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);63 64 //addr_dest : know in decod stage 98 #ifdef DEBUG_TEST 99 if (addr_dest != addr_good) 100 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); 101 #endif 102 65 103 break; 66 104 } … … 69 107 case BRANCH_CONDITION_READ_STACK : // l.jr (rb==r9) 70 108 { 71 Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); 72 miss = ((take == 1) and 73 (addr_dest = addr_good)); 74 take = 1; 109 // miss if destination address is bad 110 miss = (addr_dest != addr_good); 75 111 addr_dest = addr_good; 112 113 #ifdef DEBUG_TEST 114 if (take != 1) 115 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); 116 #endif 117 76 118 break; 77 119 } 78 120 } 79 121 80 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 81 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); 82 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address : %x",addr_dest); 83 122 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * (after)"); 123 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); 124 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); 125 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_dest : %.8x",addr_dest); 126 84 127 internal_BRANCH_COMPLETE_MISS_PREDICTION [i] = miss ; 85 128 internal_BRANCH_COMPLETE_TAKE [i] = take ; 86 129 internal_BRANCH_COMPLETE_ADDRESS_DEST [i] = addr_dest; 87 130 88 131 PORT_WRITE(out_BRANCH_COMPLETE_MISS_PREDICTION [i], internal_BRANCH_COMPLETE_MISS_PREDICTION [i]); 89 132 PORT_WRITE(out_BRANCH_COMPLETE_TAKE [i], internal_BRANCH_COMPLETE_TAKE [i]); … … 92 135 } 93 136 94 log_ printf(FUNC,Update_Prediction_Table,FUNCTION,"End");137 log_end(Update_Prediction_Table,FUNCTION); 95 138 }; 96 139 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp
r82 r88 22 22 void Update_Prediction_Table::genMealy_decod (void) 23 23 { 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 24 log_begin(Update_Prediction_Table,FUNCTION); 25 log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); 25 26 27 // WARNING : One branch per context per cycle 26 28 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 27 29 { 28 Tcontrol_t miss = PORT_READ(in_DECOD_MISS_DECOD [i]);30 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD [%d]",i); 29 31 30 if (miss) 31 { 32 // miss : need a empty slot. 33 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 34 uint32_t top = reg_TOP[context]; 35 internal_DECOD_ACK [i] = (reg_UPDATE_PREDICTION_TABLE [context][top]._state == UPDATE_PREDICTION_STATE_EMPTY); 36 } 37 else 38 { 39 internal_DECOD_ACK [i] = true; 40 } 32 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 33 bool is_accurate = reg_IS_ACCURATE [context]; 34 event_state_t event_state = reg_EVENT_STATE [context]; 35 uint32_t ptr_write = reg_UPT_TOP [context]; 36 37 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context ); 38 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate); 39 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_state : %s",toString(event_state).c_str()); 40 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ptr_write : %d",ptr_write ); 41 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_state : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state).c_str()); 42 43 // ack : 44 // * in all case (miss or hit), need empty slot 45 // * is_accurate 46 // * event_state : don't update upt 47 internal_DECOD_ACK [i] = ((reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state == UPDATE_PREDICTION_STATE_EMPTY) and 48 is_accurate and 49 // ( 50 (event_state == EVENT_STATE_OK )// or 51 // (event_state == EVENT_STATE_FLUSH_UFPT ) or 52 // (event_state == EVENT_STATE_UPDATE_CONTEXT)) 53 ); 54 internal_DECOD_UPT_PTR_WRITE [i] = ptr_write; 55 56 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ack : %d",internal_DECOD_ACK [i]); 41 57 42 58 PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); 43 59 } 44 60 45 log_ printf(FUNC,Update_Prediction_Table,FUNCTION,"End");61 log_end(Update_Prediction_Table,FUNCTION); 46 62 }; 47 63 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp
r81 r88 22 22 void Update_Prediction_Table::genMealy_predict (void) 23 23 { 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 25 24 log_begin(Update_Prediction_Table,FUNCTION); 25 log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); 26 27 if (PORT_READ(in_NRESET) != 0) 28 { 29 26 30 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 27 31 { 28 32 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 29 uint32_t top = reg_ TOP[context];33 uint32_t top = reg_UFPT_TOP[context]; 30 34 31 //log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT [%d] (genMealy)",i);32 //log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);33 //log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);34 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][top]._state).c_str());35 //log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is accurate : %d",PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]));35 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT [%d] (genMealy)",i); 36 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 37 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 38 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state).c_str()); 39 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is accurate : %d",PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])); 36 40 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * need update : %d",reg_NB_ELT_NEED_UPDATE [context]); 37 41 38 // Not Full, accurate and no previous miss 39 // Optimisation to restart faster : 40 // don't counter nb_elt_ko, but just nb_elt that need a update (change branch structure) 41 internal_PREDICT_ACK [i] = ((reg_UPDATE_PREDICTION_TABLE [context][top]._state == UPDATE_PREDICTION_STATE_EMPTY) and 42 PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and 43 (reg_NB_ELT_NEED_UPDATE [context] == 0)); 42 internal_PREDICT_UPDATE_PREDICTION_ID [i] = top; 44 43 45 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ACK : %d",internal_PREDICT_ACK [i]); 44 if (_param->_have_port_depth) 45 PORT_WRITE(out_PREDICT_UPDATE_PREDICTION_ID [i], internal_PREDICT_UPDATE_PREDICTION_ID [i]); 46 46 47 bool is_accurate = not _param->_not_accurate_block_predict or reg_IS_ACCURATE[context]; 48 49 // Ack if : 50 // * slot is empty 51 // * no previous miss 52 // * is_accurate 53 internal_PREDICT_ACK [i] = ((reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state == UPDATE_FETCH_PREDICTION_STATE_EMPTY) and 54 // PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and 55 (reg_EVENT_STATE [context] == EVENT_STATE_OK) and 56 is_accurate); 57 58 59 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ACK : %d",internal_PREDICT_ACK [i]); 47 60 PORT_WRITE(out_PREDICT_ACK [i], internal_PREDICT_ACK [i]); 48 61 } 49 62 50 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 63 }//don't reset 64 65 log_end(Update_Prediction_Table,FUNCTION); 51 66 }; 52 67 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
r82 r88 22 22 void Update_Prediction_Table::genMoore (void) 23 23 { 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 24 log_begin(Update_Prediction_Table,FUNCTION); 25 log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); 26 log_printf(NONE,Update_Prediction_Table,FUNCTION,FUNCTION); 27 28 if (PORT_READ(in_NRESET) == 1) 29 { 25 30 26 31 // =================================================================== … … 30 35 for (uint32_t i=0; i<_param->_nb_context; i++) 31 36 { 32 if (_param->_have_port_depth [i]) 33 { 34 PORT_WRITE(out_DEPTH_TAIL [i], reg_BOTTOM [i]); 35 } 36 PORT_WRITE(out_DEPTH_NB_BRANCH [i], reg_NB_ELT [i]); 37 } 37 if (_param->_have_port_depth) 38 { 39 PORT_WRITE(out_DEPTH_CURRENT [i], reg_UPT_TOP [i]); 40 PORT_WRITE(out_DEPTH_MIN [i], reg_UPT_BOTTOM [i]); 41 } 42 PORT_WRITE(out_DEPTH_MAX [i], reg_UPT_TOP [i]); 43 } 44 38 45 // =================================================================== 39 46 // =====[ UPDATE ]==================================================== 40 47 // =================================================================== 41 48 42 Tdepth_t tab_depth [_param->_nb_context]; 49 bool retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt 50 bool retire_ras_from_upt [_param->_nb_context]; // event upt -> restore RAS, else restore others structure 51 bool ufpt_update [_param->_nb_context]; 52 bool upt_update [_param->_nb_context]; 53 Tdepth_t tab_ufpt_depth [_param->_nb_context]; 54 Tdepth_t tab_upt_depth [_param->_nb_context]; 55 43 56 for (uint32_t i=0; i<_param->_nb_context; i++) 44 tab_depth [i] = reg_BOTTOM [i]; 57 { 58 event_state_t event_state = reg_EVENT_STATE [i]; 59 60 retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or 61 (event_state == EVENT_STATE_FLUSH_UFPT_AND_UPT)); 62 retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT_RAS); 63 64 ufpt_update [i] = true; 65 upt_update [i] = true; 66 tab_ufpt_depth [i] = reg_UFPT_UPDATE [i]; 67 tab_upt_depth [i] = reg_UPT_UPDATE [i]; 68 } 45 69 46 70 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 47 71 { 48 uint32_t context = (reg_UPDATE_PRIORITY+i)%_param->_nb_context; 49 Tdepth_t depth = tab_depth[context]; 50 state_t state = reg_UPDATE_PREDICTION_TABLE [context][depth]._state; 72 Tcontext_t context = (reg_UPDATE_PRIORITY+i)%_param->_nb_context; 73 74 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE [%d] (genMoore)",i); 75 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 76 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_state : %s",toString(reg_EVENT_STATE [context]).c_str()); 77 78 Tcontrol_t val = false; 79 Tcontrol_t val_without_ack = false; 80 Tcontrol_t miss_prediction ; 81 Tcontrol_t direction_good ; 82 Tcontrol_t btb_val ; 83 Taddress_t btb_address_src ; 84 Taddress_t btb_address_dest ; 85 Tbranch_condition_t btb_condition ; 86 Tcontrol_t dir_val ; 87 Thistory_t dir_history ; 88 Tcontrol_t ras_val ; 89 Tcontrol_t ras_push ; 90 Taddress_t ras_address ; 91 Tptr_t ras_index ; 92 Tcontrol_t ras_prediction_ifetch; 93 94 // Test if update fetch prediction table need update port 95 if (retire_ras_from_ufpt [context]) 96 { 97 if (ufpt_update [context]) 98 { 99 // Update Fetch Prediction Table 100 // An update of ufpt is to previous miss. Just restore Return Address Stack 101 102 Tdepth_t depth = tab_ufpt_depth[context]; 103 ufpt_state_t state = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state; 104 Tbranch_condition_t condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition; 105 106 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); 107 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); 108 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state ).c_str()); 109 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); 110 111 val = (state == UPDATE_FETCH_PREDICTION_STATE_EVENT); 112 miss_prediction = 1; 113 // direction_good = ; 114 btb_val = 0; // don't update btb (is update by the event branch) 115 // btb_address_src = ; 116 // btb_address_dest = ; 117 // btb_condition = ; 118 dir_val = 0; // don't update btb (is update by the event branch (if conditionnal branch)) 119 // dir_history = ; 120 ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras 121 ras_push = push_ras(condition); 122 ras_address = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras; 123 ras_index = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._index_ras; 124 ras_prediction_ifetch = 1; 125 126 internal_UPDATE_FROM_UFPT [i] = true; 127 internal_UPDATE_DEPTH [i] = depth; 128 internal_UPDATE_RAS [i] = false; 129 130 // Warning : don't update same entry 131 if (depth == reg_UFPT_BOTTOM[context]) 132 ufpt_update [context] = false; 133 134 tab_ufpt_depth[context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1); 135 } 136 } 137 else 138 { 139 if (upt_update [context]) 140 { 141 // Update Prediction Table 142 143 Tdepth_t depth = tab_upt_depth[context]; 144 upt_state_t state = reg_UPDATE_PREDICTION_TABLE [context][depth]._state; 145 Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 146 Tcontrol_t ifetch = reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction; 147 148 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 149 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); 150 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state ).c_str()); 151 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); 152 153 Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK) or 154 (state == UPDATE_PREDICTION_STATE_KO)); 155 Tcontrol_t state_is_event = (state == UPDATE_PREDICTION_STATE_EVENT); 156 Tcontrol_t state_is_event_update = state_is_event and need_update(condition); 157 Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); 158 159 if (retire_ras_from_upt [context]) 160 { 161 val = state_is_event_update; 162 val_without_ack = state_is_event_no_update; 163 } 164 else 165 { 166 val = state_is_ok_ko; 167 val_without_ack = false; 168 } 169 170 miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); 171 direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; 172 btb_val = update_btb(condition); 173 btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; 174 btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; 175 btb_condition = condition; 176 dir_val = update_dir(condition) and ifetch; // if not ifetch, then static prediction 177 dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; 178 ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras 179 ras_push = push_ras(condition); 180 ras_address = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; 181 ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; 182 ras_prediction_ifetch = ifetch; 183 184 internal_UPDATE_FROM_UFPT [i] = false; 185 internal_UPDATE_DEPTH [i] = depth; 186 internal_UPDATE_RAS [i] = retire_ras_from_upt [context]; 187 188 // Warning : don't update same entry 189 if (retire_ras_from_upt [context]) 190 { 191 // Restore RAS. 192 if ((depth == reg_UPT_BOTTOM[context]) or not (val or val_without_ack)) 193 upt_update [context] = false; 194 195 tab_upt_depth[context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1); 196 } 197 else 198 { 199 if ((depth == reg_UPT_TOP [context]) or not (val or val_without_ack)) 200 upt_update [context] = false; 201 202 tab_upt_depth[context] = (depth+1)%_param->_size_upt_queue[context]; 203 } 204 } 205 } 206 207 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val ); 208 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val_without_ack : %d",val_without_ack); 209 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * btb_val : %d",btb_val); 210 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * dir_val : %d",dir_val); 211 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ras_val : %d",ras_val); 212 213 internal_UPDATE_VAL [i] = val; 214 internal_UPDATE_VAL_WITHOUT_ACK [i] = val_without_ack; 215 internal_UPDATE_CONTEXT_ID [i] = context; 216 217 PORT_WRITE(out_UPDATE_VAL [i],internal_UPDATE_VAL [i]); 218 if (val) 219 { 220 if (_param->_have_port_context_id) 221 PORT_WRITE(out_UPDATE_CONTEXT_ID [i],context ); 222 PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],miss_prediction ); 223 PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],direction_good ); 224 PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val ); 225 PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],btb_address_src ); 226 227 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_src : %.8x",btb_address_src); 228 229 PORT_WRITE(out_UPDATE_BTB_ADDRESS_DEST [i],btb_address_dest ); 230 PORT_WRITE(out_UPDATE_BTB_CONDITION [i],btb_condition ); 231 PORT_WRITE(out_UPDATE_DIR_VAL [i],dir_val ); 232 if (_param->_have_port_history) 233 PORT_WRITE(out_UPDATE_DIR_HISTORY [i],dir_history ); 234 PORT_WRITE(out_UPDATE_RAS_VAL [i],ras_val ); 235 PORT_WRITE(out_UPDATE_RAS_PUSH [i],ras_push ); 236 PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],ras_address ); 237 PORT_WRITE(out_UPDATE_RAS_INDEX [i],ras_index ); 238 PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ras_prediction_ifetch); 239 } 240 } 241 242 // // =================================================================== 243 // // =====[ BRANCH_EVENT ]============================================== 244 // // =================================================================== 245 // for (uint32_t i=0; i<_param->_nb_context; i++) 246 // { 247 // Tdepth_t depth = (reg_BOTTOM [i] + reg_NB_ELT_UPDATE [i])%_param->_size_queue [i]; 248 // state_t state = reg_UPDATE_PREDICTION_TABLE [i][depth]._state; 51 249 52 Tcontrol_t val = ((state == UPDATE_PREDICTION_STATE_OK) or 53 (state == UPDATE_PREDICTION_STATE_KO)); 54 55 // log_printf(TRACE,Update_Prediction_Table,FUNCTION,"UPDATE [%d] (genMoore)",i); 56 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 57 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 58 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state).c_str()); 59 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val); 60 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * addr_src : %x",reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ); 61 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * addr_dest : %x",reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest); 62 63 if (val) 64 { 65 Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; 66 67 Tcontrol_t ifetch = reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction; 68 Tcontrol_t btb_val = true; 69 Tcontrol_t dir_val = (ifetch and // not ifetch == static prediction 70 ((cond == BRANCH_CONDITION_FLAG_UNSET) or 71 (cond == BRANCH_CONDITION_FLAG_SET))); 72 Tcontrol_t ras_val = ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 73 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 74 (cond == BRANCH_CONDITION_READ_STACK)); 75 76 Tcontrol_t push = ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 77 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK)); 78 79 if (_param->_have_port_context_id) 80 PORT_WRITE(out_UPDATE_CONTEXT_ID [i],context); 81 PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],(state == UPDATE_PREDICTION_STATE_KO)); 82 PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ); 83 PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val); 84 PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ); 85 PORT_WRITE(out_UPDATE_BTB_ADDRESS_DEST [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest); 86 PORT_WRITE(out_UPDATE_BTB_CONDITION [i],cond); 87 PORT_WRITE(out_UPDATE_DIR_VAL [i],dir_val); 88 if (_param->_have_port_history) 89 PORT_WRITE(out_UPDATE_DIR_HISTORY [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._history ); 90 PORT_WRITE(out_UPDATE_RAS_VAL [i],ras_val); 91 PORT_WRITE(out_UPDATE_RAS_PUSH [i],push); 92 PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras ); 93 PORT_WRITE(out_UPDATE_RAS_INDEX [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras ); 94 PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ifetch); 95 96 internal_UPDATE_CONTEXT_ID [i] = context; 97 internal_UPDATE_DEPTH [i] = depth; 98 99 tab_depth[context] = (depth+1)%_param->_size_queue[context]; 100 } 101 102 internal_UPDATE_VAL [i] = val; 103 PORT_WRITE(out_UPDATE_VAL [i], internal_UPDATE_VAL [i]); 104 } 105 106 // =================================================================== 107 // =====[ BRANCH_EVENT ]============================================== 108 // =================================================================== 109 for (uint32_t i=0; i<_param->_nb_context; i++) 110 { 111 Tdepth_t depth = (reg_BOTTOM [i] + reg_NB_ELT_UPDATE [i])%_param->_size_queue [i]; 112 state_t state = reg_UPDATE_PREDICTION_TABLE [i][depth]._state; 113 114 Tcontrol_t val = (state == UPDATE_PREDICTION_STATE_EVENT); 115 116 if (val) 117 { 118 PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_src ); 119 PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_dest); 120 internal_BRANCH_EVENT_DEPTH [i] = depth; 121 } 122 123 internal_BRANCH_EVENT_VAL [i] = val; 124 PORT_WRITE(out_BRANCH_EVENT_VAL [i], internal_BRANCH_EVENT_VAL [i]); 125 } 126 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); 250 // Tcontrol_t val = ((state == UPDATE_PREDICTION_STATE_EVENT) or 251 // (state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT)); 252 253 // if (val) 254 // { 255 // // breakpoint ("UPT : have an branch_event (depth %d)",depth); 256 // PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_src ); 257 // PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_dest); 258 // internal_BRANCH_EVENT_DEPTH [i] = depth; 259 // } 260 261 // internal_BRANCH_EVENT_VAL [i] = val; 262 // PORT_WRITE(out_BRANCH_EVENT_VAL [i], internal_BRANCH_EVENT_VAL [i]); 263 // } 264 265 } 266 log_end(Update_Prediction_Table,FUNCTION); 127 267 }; 128 268 -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp
r81 r88 27 27 "Update_Prediction_Table", 28 28 param_statistics); 29 30 // _stat_nb_branch_hit = new counter_t * [_param->_nb_context]; 31 // _stat_nb_branch_miss = new counter_t * [_param->_nb_context]; 32 // _stat_nb_branch_unused = new counter_t * [_param->_nb_context]; 33 // _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context]; 34 // _stat_queue_nb_cycle_full = new counter_t * [_param->_nb_context]; 35 // _stat_queue_nb_elt = new counter_t * [_param->_nb_context]; 36 37 // for (uint32_t i=0; i<_param->_nb_context; ++i) 38 // { 39 // _stat_nb_branch_hit [i] = _stat->create_counter("nb_branch_hit_" +toString(i),"",toString(_("Branch hit speculation (context %d)"),i)); 40 // _stat_nb_branch_miss [i] = _stat->create_counter("nb_branch_miss_" +toString(i),"",toString(_("Branch miss speculation (context %d)"),i)); 41 // _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i)); 42 // _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i)); 43 // _stat_queue_nb_cycle_full [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i)); 44 // _stat_queue_nb_elt [i] = _stat->create_counter("queue_nb_elt_" +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); 45 // } 29 46 30 47 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
r81 r88 26 26 log_printf(INFO,Update_Prediction_Table,FUNCTION,"Generate Statistics file"); 27 27 28 delete _stat; 28 delete _stat; 29 // delete [] _stat_nb_branch_hit ; 30 // delete [] _stat_nb_branch_miss ; 31 // delete [] _stat_nb_branch_unused ; 32 // delete [] _stat_queue_nb_cycle_empty; 33 // delete [] _stat_queue_nb_cycle_full ; 34 // delete [] _stat_queue_nb_elt ; 29 35 30 36 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); -
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
r82 r88 17 17 namespace update_prediction_table { 18 18 19 20 19 #undef FUNCTION 21 20 #define FUNCTION "Update_Prediction_Table::transition" 22 21 void Update_Prediction_Table::transition (void) 23 22 { 24 log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); 23 log_begin(Update_Prediction_Table,FUNCTION); 24 log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); 25 25 26 26 if (PORT_READ(in_NRESET) == 0) 27 27 { 28 // Initialisation 29 30 reg_UPDATE_PRIORITY = 0; 31 32 // All pointer is set at 0 28 33 for (uint32_t i=0; i<_param->_nb_context; i++) 29 34 { 30 reg_TOP [i] = 0; 31 reg_BOTTOM [i] = 0; 32 reg_NB_ELT [i] = 0; 33 reg_NB_ELT_UPDATE [i] = 0; 34 reg_NB_ELT_NEED_UPDATE [i] = 0; 35 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 36 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; 37 } 38 reg_UPDATE_PRIORITY = 0; 35 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) 36 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 37 reg_UFPT_BOTTOM [i] = 0; 38 reg_UFPT_TOP [i] = 0; 39 reg_UFPT_UPDATE [i] = 0; 40 reg_UFPT_NB_NEED_UPDATE [i] = 0; 41 42 for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) 43 reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; 44 reg_UPT_BOTTOM [i] = 0; 45 reg_UPT_TOP [i] = 0; 46 reg_UPT_UPDATE [i] = 0; 47 reg_UPT_NB_NEED_UPDATE [i] = 0; 48 49 reg_IS_ACCURATE [i] = true; 50 51 reg_EVENT_STATE [i] = EVENT_STATE_OK; 52 } 39 53 } 40 54 else 41 55 { 42 56 // =================================================================== 57 // =====[ GARBAGE COLLECTOR ]========================================= 58 // =================================================================== 59 60 // Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot 61 // * Update state -> new status is "empty" 62 // * Update pointer (bottom and accurate) 63 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR"); 64 for (uint32_t i=0; i<_param->_nb_context; i++) 65 { 66 // UPDATE_FETCH_PREDICTION_TABLE 67 { 68 uint32_t bottom = reg_UFPT_BOTTOM [i]; 69 70 // Test if state is end 71 if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END) 72 { 73 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom); 74 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom); 75 76 // Free slot 77 reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 78 // Update pointer 79 reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i]; 80 } 81 } 82 83 // UPDATE_PREDICTION_TABLE 84 { 85 uint32_t bottom = reg_UPT_BOTTOM [i]; 86 87 // Test if state is end 88 if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) 89 { 90 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); 91 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); 92 93 // Free slot 94 reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; 95 // Update pointer 96 reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; 97 } 98 } 99 } 100 101 // =================================================================== 43 102 // =====[ PREDICT ]=================================================== 44 103 // =================================================================== 104 105 // An ifetch_unit compute next cycle and have an branch : predict_val is set 106 // * Alloc new entry -> new status is "wait decod" 107 // * Save input (to restore in miss or error) 108 // * Update pointer 109 45 110 for (uint32_t i=0; i<_param->_nb_inst_predict; i++) 46 111 if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i]) 47 112 { 48 113 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; 49 uint32_t top = reg_TOP [context]; 50 51 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT[%d] - Accepted",i); 52 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 53 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 54 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); 55 56 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAIT_DECOD; 57 reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = true; 58 reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 59 reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 60 reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 61 reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); 62 //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take 63 reg_UPDATE_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; 64 reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); 65 reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); 66 67 reg_TOP [context] = (top+1)%_param->_size_queue [context]; 68 reg_NB_ELT [context] ++; 114 uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i]; 115 116 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i); 117 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 118 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); 119 120 #ifdef DEBUG_TEST 121 if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) 122 throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state.")); 123 #endif 124 125 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top); 126 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD; 127 128 Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); 129 130 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition; 131 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); 132 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); 133 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); 134 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]); 135 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; 136 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); 137 reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); 138 139 reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context]; 140 // reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; 141 if (need_update(condition)) 142 reg_UFPT_NB_NEED_UPDATE [context] ++; 69 143 } 70 144 … … 72 146 // =====[ DECOD ]===================================================== 73 147 // =================================================================== 148 149 150 // An decod is detected by decod stage 151 // 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch 152 // * Update state, wait_decod -> wait_end 153 // * Pop ufpt -> push upt 154 // * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod 155 // 2) Miss : The instruction bundle have a branch but it is not predicted 156 // * Flush ufpt 157 // * decod information is write in upt 158 74 159 for (uint32_t i=0; i<_param->_nb_inst_decod; i++) 75 160 if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i]) 76 161 { 77 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 78 Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); 79 Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); 80 81 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"DECOD[%d] - Accepted",i); 82 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 83 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); 84 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); 85 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); 162 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; 163 Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); 164 Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); 165 uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i]; 166 Tbranch_condition_t condition ; 167 Tcontrol_t is_accurate; 168 169 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i); 170 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 171 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); 172 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); 173 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); 86 174 87 // Test if miss ifetch 88 // miss ifetch = decod a branch and the predict unit have not predict this branch ... gloup :P 89 if (miss_ifetch or miss_decod) 175 if (miss_ifetch or miss_decod) 90 176 { 91 Tdepth_t depth = (_param->_have_port_max_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; 92 Tdepth_t top = reg_TOP [context]; 93 94 reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAITEND; 95 reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = false; // static prediction 96 reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); 97 reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); 98 reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); 99 reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); 100 //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take 101 //reg_UPDATE_PREDICTION_TABLE [context][top]._history 102 reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); 103 reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); 104 105 // Invalid all previous "ifetch" prediction 106 // (ifetch prediction = prediction make in fetch stage and not again comming in decod stage) 107 uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 108 uint32_t nb_elt_need_update = 0; 109 for (uint32_t j=0; j<nb_elt_miss; j++) 110 { 111 uint32_t k=(depth+j)%_param->_size_queue[context]; 112 113 // Ifetch have make a prediction and it's a miss 114 // When ifetch predict : 115 // * btb is not change -> needn't update 116 // * direction is not change -> needn't update 117 // * ras have change -> need update 118 119 Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; 120 if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 121 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 122 (cond == BRANCH_CONDITION_READ_STACK)) 123 { 124 nb_elt_need_update ++; 125 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 126 } 127 else 128 { 129 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 130 } 131 } 132 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; // rewrite 133 134 reg_TOP [context] = (depth+1)%_param->_size_queue [context]; 135 reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 136 reg_NB_ELT [context] ++; 177 // Have a miss !!! 178 179 // Flush UPFT 180 181 // It's to accelerate miss speculation 182 if (reg_UFPT_NB_NEED_UPDATE [context] == 0) 183 { 184 // No entry need prediction, flush all entry -> Reset 185 for (uint32_t j=0; j<_param->_size_ufpt_queue[context]; ++j) 186 reg_UPDATE_FETCH_PREDICTION_TABLE [context][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; 187 reg_UFPT_BOTTOM [context] = 0; 188 reg_UFPT_TOP [context] = 0; 189 // reg_UFPT_UPDATE [context] = 0; 190 } 191 else 192 { 193 reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; 194 195 #ifdef DEBUG_TEST 196 if (reg_EVENT_STATE [context] == EVENT_STATE_OK) 197 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); 198 #endif 199 200 // Change state 201 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss)",context); 202 203 reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT; 204 } 205 206 // Push upt (from decod interface) 207 condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); 208 is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]); 209 210 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; 211 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); 212 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); 213 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); 214 // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; 215 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; 216 // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction 217 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); 218 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); 219 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction 137 220 } 138 221 else 139 222 { 140 223 // Normal case : branch is previous predicated, change state of branch 141 Tdepth_t depth = (_param->_have_port_max_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; 142 143 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; 224 uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; 225 226 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read); 227 228 #ifdef DEBUG_TEST 229 if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) 230 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state.")); 231 #endif 232 // Change state 233 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read); 234 reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END; 235 236 // Push upt (from Pop ufpt) 237 condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition; 238 is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate; 239 240 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; 241 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ; 242 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest; 243 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ; 244 // reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; 245 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; 246 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ; 247 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ; 248 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ; 249 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true; // prediction from ifetch 250 251 // Update pointer 252 if (need_update(condition)) 253 { 254 reg_UFPT_NB_NEED_UPDATE [context] --; 255 } 144 256 } 257 258 // All case !!! 259 260 #ifdef DEBUG_TEST 261 if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY) 262 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state.")); 263 #endif 264 265 // Change state 266 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write); 267 reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END; 268 269 // Write new accurate 270 #ifdef DEBUG_TEST 271 if (not reg_IS_ACCURATE [context] and not is_accurate) 272 throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag.")); 273 #endif 274 reg_IS_ACCURATE [context] = is_accurate; 275 276 // Update pointer 277 reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; 278 // reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; 279 if (need_update(condition)) 280 { 281 reg_UPT_NB_NEED_UPDATE [context] ++; 282 } 145 283 } 146 284 … … 148 286 // =====[ BRANCH_COMPLETE ]=========================================== 149 287 // =================================================================== 288 289 // The branch is complete 290 // * Hit prediction : 291 // * update status 292 // * Miss prediction : 150 293 for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) 151 294 if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) 152 295 { 153 296 Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; 154 Tdepth_t depth = (_param->_have_port_ max_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;155 156 log_printf(TRACE,Update_Prediction_Table,FUNCTION," BRANCH_COMPLETE[%d] - Accepted",i);157 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);158 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);159 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]);297 Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; 298 299 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); 300 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 301 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 302 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",internal_BRANCH_COMPLETE_MISS_PREDICTION [i]); 160 303 161 304 if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i]) 162 305 { 163 306 // Miss case 164 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 165 166 // Another prediction (prediction with depth higer) 167 Tdepth_t top = reg_TOP [context]; 168 uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 169 uint32_t nb_elt_need_update = 1; 170 for (uint32_t j=1; j<nb_elt_miss; j++) 171 { 172 uint32_t k=(depth+j)%_param->_size_queue[context]; 307 // // breakpoint("Branch_complete and miss ..."); 308 309 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_EVENT (branch_complete)",context,depth); 310 // reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; 311 312 // // Another prediction (prediction with depth higer) 313 // Tdepth_t top = reg_TOP [context]; 314 // uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; 315 // uint32_t nb_elt_need_update = 1; 316 // for (uint32_t j=1; j<nb_elt_miss; j++) 317 // { 318 // uint32_t k=(depth+j)%_param->_size_queue[context]; 173 319 174 // Ifetch have make a prediction and it's a miss 175 // When ifetch predict : 176 // * btb is not change -> needn't update 177 // * direction is not change -> needn't update 178 // * ras have change -> need update 179 180 Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; 181 if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 182 (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 183 (cond == BRANCH_CONDITION_READ_STACK)) 184 { 185 nb_elt_need_update ++; 186 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 187 } 188 else 189 { 190 reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 191 } 192 } 193 reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 194 195 // Update pointer : 196 reg_TOP [context] = depth; 197 reg_NB_ELT [context] -= nb_elt_miss; 320 // // Ifetch have make a prediction and it's a miss 321 // // When ifetch predict : 322 // // * btb is not change -> needn't update 323 // // * direction is not change -> needn't update 324 // // * ras have change -> need update 325 326 // Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; 327 // if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or 328 // (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or 329 // (cond == BRANCH_CONDITION_READ_STACK)) 330 // { 331 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch miss, update ras)",context,k); 332 333 // nb_elt_need_update ++; 334 // reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; 335 // } 336 // else 337 // { 338 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_END (branch_complete, ifetch miss, don't update ras)",context,k); 339 340 // reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; 341 // } 342 // } 343 // reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; 344 345 // // Update pointer : 346 // reg_TOP [context] = depth; 347 // reg_NB_ELT [context] -= nb_elt_miss; 348 // reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 349 198 350 } 199 351 else 200 352 { 201 // Hit case 202 #ifdef DEBUG_TEST 203 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAITEND) 204 ERRORMORPHEO(FUNCTION,"Branche complete : invalid state"); 205 #endif 206 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; 353 // Hit case 354 355 #ifdef DEBUG_TEST 356 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) 357 throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); 358 #endif 359 360 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); 361 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; 207 362 } 208 363 209 // In all case : update good_take and address_destination 210 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i]; 211 reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; 212 } 364 // In all case : update good_take 365 reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i]; 366 } 213 367 214 368 // =================================================================== … … 216 370 // =================================================================== 217 371 for (uint32_t i=0; i<_param->_nb_inst_update; i++) 218 if (internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) 372 if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or 373 (internal_UPDATE_VAL_WITHOUT_ACK [i])) 219 374 { 220 375 Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; 221 376 Tdepth_t depth = internal_UPDATE_DEPTH [i]; 222 223 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"UPDATE[%d] - Accepted",i); 224 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 225 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 226 227 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) 228 reg_NB_ELT_NEED_UPDATE [context] --; 229 230 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; 377 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); 378 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); 379 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); 380 381 if (internal_UPDATE_FROM_UFPT [i]) 382 { 383 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); 384 385 // Change state 386 #ifdef DEBUG_TEST 387 if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) 388 throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); 389 #endif 390 391 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); 392 393 reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; 394 395 // Update pointer 396 reg_UFPT_UPDATE [context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1); 397 398 // Free a register that need update ? 399 if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) 400 reg_UFPT_NB_NEED_UPDATE [context] --; 401 } 402 else 403 { 404 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); 405 406 // Change state 407 #ifdef DEBUG_TEST 408 if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and 409 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) and 410 (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT)) 411 throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); 412 #endif 413 414 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); 415 416 reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; 417 418 // Update pointer 419 if (internal_UPDATE_RAS [i]) 420 reg_UPT_UPDATE [context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1); 421 else 422 reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; 423 424 // Free a register that need update ? 425 if (need_update(reg_UPDATE_PREDICTION_TABLE [context][depth]._condition)) 426 reg_UPT_NB_NEED_UPDATE [context] --; 427 // Free the branch with no accurate ? 428 if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) 429 reg_IS_ACCURATE [i] = true; 430 } 231 431 } 232 432 … … 234 434 reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; 235 435 236 // =================================================================== 237 // =====[ BRANCH_EVENT ]============================================== 238 // =================================================================== 239 for (uint32_t i=0; i<_param->_nb_context; i++) 240 if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) 241 { 242 Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i]; 243 244 reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO; 245 } 246 247 // =================================================================== 248 // =====[ GARBAGE COLLECTOR ]========================================= 249 // =================================================================== 250 251 for (uint32_t i=0; i<_param->_nb_context; i++) 252 { 253 uint32_t bottom = reg_BOTTOM [i]; 254 255 // Test if the tail of queue is finish (ok or ko and update) 256 if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) 257 { 258 log_printf(TRACE,Update_Prediction_Table,FUNCTION,"GARBAGE_COLLECTOR"); 259 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); 260 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); 261 262 reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; 263 reg_BOTTOM [i] = (bottom+1)%_param->_size_queue [i]; 264 if (reg_NB_ELT [i]>0) 265 reg_NB_ELT [i] --; 266 } 267 } 268 } 436 // // =================================================================== 437 // // =====[ BRANCH_EVENT ]============================================== 438 // // =================================================================== 439 // for (uint32_t i=0; i<_param->_nb_context; i++) 440 // if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) 441 // { 442 // Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i]; 443 444 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_EVENT) 445 // { 446 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_event)",i,depth); 447 448 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO; 449 // } 450 // else 451 // { 452 // #ifdef DEBUG_TEST 453 // if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT) 454 // throw ERRORMORPHEO(FUNCTION,_("Branche event : invalid state")); 455 // #endif 456 457 // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_WAITEND (branch_event)",i,depth); 458 459 // reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; 460 // } 461 // } 269 462 270 463 #if (DEBUG >= DEBUG_TRACE) 271 log_printf(TRACE,Update_Prediction_Table,FUNCTION," Dump Update_Prediction_Table");272 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY: %d",reg_UPDATE_PRIORITY);464 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table"); 465 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); 273 466 for (uint32_t i=0; i<_param->_nb_context; i++) 274 467 { 275 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); 276 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_TOP : %d",reg_TOP [i]); 277 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); 278 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); 279 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT_NEED_UPDATE : %d",reg_NB_ELT_NEED_UPDATE [i]); 280 for (uint32_t j=0; j<_param->_size_queue[i]; j++) 281 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %s %x",j,toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str(),reg_UPDATE_PREDICTION_TABLE [i][j]._address_src); 468 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); 469 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); 470 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_RAS_CORRUPTED : %d" ,reg_EVENT_RAS_CORRUPTED [i]); 471 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); 472 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC_VAL : %d" ,reg_EVENT_ADDRESS_SRC_VAL [i]); 473 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]); 474 475 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); 476 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]); 477 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]); 478 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); 479 for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) 480 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s", 481 j, 482 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition, 483 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src, 484 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest, 485 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take, 486 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate, 487 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history, 488 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras, 489 reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras, 490 toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str() 491 ); 492 493 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); 494 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); 495 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); 496 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); 497 log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_NB_NEED_UPDATE : %d",reg_UPT_NB_NEED_UPDATE [i]); 498 for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) 499 log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s", 500 j, 501 reg_UPDATE_PREDICTION_TABLE [i][j]._condition, 502 reg_UPDATE_PREDICTION_TABLE [i][j]._address_src, 503 reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest, 504 reg_UPDATE_PREDICTION_TABLE [i][j]._last_take, 505 reg_UPDATE_PREDICTION_TABLE [i][j]._good_take, 506 reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate, 507 reg_UPDATE_PREDICTION_TABLE [i][j]._history, 508 reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras, 509 reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras, 510 toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str() 511 ); 282 512 } 283 513 #endif 514 } 284 515 285 516 … … 287 518 end_cycle (); 288 519 #endif 289 290 log_ printf(FUNC,Update_Prediction_Table,FUNCTION,"End");520 521 log_end(Update_Prediction_Table,FUNCTION); 291 522 }; 292 523
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