Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 81)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h	(revision 88)
@@ -2,6 +2,33 @@
 #define morpheo_behavioural_Constants_h
 
+/*
+  WARNING : 
+  
+  I Use reserved exception : 
+
+  0x10 - EXCEPTION_MEMORY_MISS_SPECULATION   - Load miss speculation
+  0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE   - The load is speculative : write in register file, but don't commit
+  0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID    - SPR     present in ALU but not compatible privilege
+  0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ  - SPR not present in ALU
+  0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU
+
+  I Use reserved SPR :
+  [0][19] - SPR_CID
+*/
+
 namespace morpheo {
 namespace behavioural {
+
+#  define SET_FLAG(     x,pos)  {(x) |=  (1<<(pos));} while (0)
+#  define UNSET_FLAG(   x,pos)  {(x) &= ~(1<<(pos));} while (0)
+#  define IS_SET_FLAG(  x,pos) (((x) &   (1<<(pos))) != 0)
+#  define IS_UNSET_FLAG(x,pos) (((x) &   (1<<(pos))) == 0)
+#  define CHANGE_FLAG(  x,pos,f) \
+   {                        \
+     if (f)                 \
+       {SET_FLAG(x,pos);}   \
+     else                   \
+       {UNSET_FLAG(x,pos);} \
+   } while (0)
 
   //=========================================================[ Type ]=====
@@ -10,14 +37,30 @@
 #  define TYPE_MOVE                                0x2        // 00000 - unit multiple
 #  define TYPE_TEST                                0x3        // 00000 - unit multiple
-#  define TYPE_MUL_DIV                             0x4        // 00000 - unit multiple
-#  define TYPE_EXTEND                              0x5        // 00000 - unit multiple, type optionnal
-#  define TYPE_FIND                                0x6        // 00000 - unit multiple, type optionnal
-#  define TYPE_SPECIAL                             0x7        // 00000 - unit uniq
-#  define TYPE_CUSTOM                              0x8        // 00000 - unit uniq    , type optionnal
-#  define TYPE_BRANCH                              0x9        // 00000 - unit multiple
-#  define TYPE_MEMORY                              0xa        // 00000 - unit uniq
-
+#  define TYPE_MUL                                 0x4        // 00000 - unit multiple
+#  define TYPE_DIV                                 0x5        // 00000 - unit multiple, type optionnal
+#  define TYPE_EXTEND                              0x6        // 00000 - unit multiple, type optionnal
+#  define TYPE_FIND                                0x7        // 00000 - unit multiple, type optionnal
+#  define TYPE_SPECIAL                             0x8        // 00000 - unit uniq
+#  define TYPE_CUSTOM                              0x9        // 00000 - unit uniq    , type optionnal
+#  define TYPE_BRANCH                              0xa        // 00000 - unit multiple
+#  define TYPE_MEMORY                              0xb        // 00000 - unit uniq
+
+//#define NB_TYPE                                  11
 #  define SIZE_TYPE                                5
 #  define MAX_TYPE                                 (1<<SIZE_TYPE)
+
+#  define is_type_valid(x) \
+  (( x == TYPE_ALU    ) or \
+   ( x == TYPE_SHIFT  ) or \
+   ( x == TYPE_MOVE   ) or \
+   ( x == TYPE_TEST   ) or \
+   ( x == TYPE_MUL    ) or \
+   ( x == TYPE_DIV    ) or \
+   ( x == TYPE_EXTEND ) or \
+   ( x == TYPE_FIND   ) or \
+   ( x == TYPE_SPECIAL) or \
+   ( x == TYPE_CUSTOM ) or \
+   ( x == TYPE_BRANCH ) or \
+   ( x == TYPE_MEMORY ))
 
   //====================================================[ Operation ]=====
@@ -149,8 +192,9 @@
 #  define OPERATION_TEST_L_SFNE                    0x20       // 000_0000 l.sfne  , l.sfnei
 
-#  define OPERATION_MUL_DIV_L_MUL                  0x1        // 000_0000 l.mul   , l.muli
-#  define OPERATION_MUL_DIV_L_MULU                 0x2        // 000_0000 l.mulu
-#  define OPERATION_MUL_DIV_L_DIV                  0x4        // 000_0000 l.div
-#  define OPERATION_MUL_DIV_L_DIVU                 0x8        // 000_0000 l.divu
+#  define OPERATION_MUL_L_MUL                      0x1        // 000_0000 l.mul   , l.muli
+#  define OPERATION_MUL_L_MULU                     0x2        // 000_0000 l.mulu
+
+#  define OPERATION_DIV_L_DIV                      0x1        // 000_0000 l.div
+#  define OPERATION_DIV_L_DIVU                     0x2        // 000_0000 l.divu
 
 #  define OPERATION_EXTEND_L_EXTEND_Z              0x1        // 000_0000 l.extbz , l.exthz, l.extwz
@@ -204,9 +248,9 @@
 #  define SIZE_EXCEPTION                           5
 #  define SIZE_EXCEPTION_USE                       4
-#  define SIZE_EXCEPTION_MEMORY                    3
-#  define SIZE_EXCEPTION_CUSTOM                    3
-#  define SIZE_EXCEPTION_ALU                       2
-#  define SIZE_EXCEPTION_DECOD                     2
-#  define SIZE_EXCEPTION_IFETCH                    2
+#  define SIZE_EXCEPTION_MEMORY                    5
+#  define SIZE_EXCEPTION_CUSTOM                    5
+#  define SIZE_EXCEPTION_ALU                       5
+#  define SIZE_EXCEPTION_DECOD                     5
+#  define SIZE_EXCEPTION_IFETCH                    5
 
 #  define EXCEPTION_NONE                           0x00       // none exception
@@ -243,54 +287,67 @@
 #  define EXCEPTION_CUSTOM_6                       0x1f       // Reserved for custom exceptions
 
-
-#define exception_to_address(x) (x<<8)
+  //SR[14].EPH : Exception Prefix High
+  // EPH = 0 Exceptions vectors are located in memory area starting at 0x0
+  // EPH = 1 Exception vectors are located in memory area starting at 0xF0000000
+
+#define exception_to_address(eph,x) (((eph==0)?0x0:0xF0000000)+(x<<8))
 
   // Exception Execution
-#  define EXCEPTION_MEMORY_NONE                    0x0        // Load/Store generate none exception
-#  define EXCEPTION_MEMORY_ALIGNMENT               0x1        // Load/Store access is not aligned
-#  define EXCEPTION_MEMORY_DATA_TLB                0x2        // DTLB miss
-#  define EXCEPTION_MEMORY_DATA_PAGE               0x3        // No matching or page violation protection in pages tables
-#  define EXCEPTION_MEMORY_BUS_ERROR               0x4        // Access at a invalid physical address
-#  define EXCEPTION_MEMORY_MISS_SPECULATION        0x5        // Load miss speculation
-#  define EXCEPTION_MEMORY_LOAD_SPECULATIVE        0x6        // The load is speculative : write in register file, but don't commit
-
-#  define EXCEPTION_CUSTOM_NONE                    0x1        // Custom unit generate none exception
-#  define EXCEPTION_CUSTOM_CUST_0                  0x1        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_1                  0x2        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_2                  0x3        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_3                  0x4        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_4                  0x5        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_5                  0x6        // Reserved for custom exceptions
-#  define EXCEPTION_CUSTOM_CUST_6                  0x7        // Reserved for custom exceptions
-
-#  define EXCEPTION_ALU_NONE                       0x0        // Functionnal unit generate none exception
-#  define EXCEPTION_ALU_RANGE                      0x1        // 
-#  define EXCEPTION_ALU_SPR_ACCESS_INVALID         0x2        // SPR     present in ALU but not compatible privilege
-#  define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE    0x3        // SPR not present in ALU
-
-#  define EXCEPTION_DECOD_NONE                     0x0        // none exception
-#  define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION      0x1        // Instruction is illegal (no implemented)
-#  define EXCEPTION_DECOD_SYSCALL                  0x2        // System Call
-//#define EXCEPTION_DECOD_TRAP                     0x4        // L.trap or debug unit (note : must read SR !)
-
-#  define EXCEPTION_IFETCH_NONE                    0x0        // Fetch Unit generate none exception
-#  define EXCEPTION_IFETCH_INSTRUCTION_TLB         0x1        // ITLB miss
-#  define EXCEPTION_IFETCH_INSTRUCTION_PAGE        0x2        // No matching or page violation protection in pages tables
-#  define EXCEPTION_IFETCH_BUS_ERROR               0x3        // Access at a invalid physical address
-
-#  define EXCEPTION_USE_NONE                       0x0        // 
-#  define EXCEPTION_USE_ILLEGAL_INSTRUCTION        0x1        // illegal_instruction
-#  define EXCEPTION_USE_RANGE                      0x2        // range
-#  define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT      0x3        // TLB miss, page fault, bus error, alignment
-#  define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT   0x4        // TLB miss, page fault, bus error
-#  define EXCEPTION_USE_SYSCALL                    0x5        // syscall
-#  define EXCEPTION_USE_TRAP                       0x6        // trap
-#  define EXCEPTION_USE_CUSTOM_0                   0x7        // 
-#  define EXCEPTION_USE_CUSTOM_1                   0x8        // 
-#  define EXCEPTION_USE_CUSTOM_2                   0x9        // 
-#  define EXCEPTION_USE_CUSTOM_3                   0xa        // 
-#  define EXCEPTION_USE_CUSTOM_4                   0xb        // 
-#  define EXCEPTION_USE_CUSTOM_5                   0xc        // 
-#  define EXCEPTION_USE_CUSTOM_6                   0xd        // 
+#  define EXCEPTION_IFETCH_NONE                    0x00       // Fetch Unit generate none exception
+#  define EXCEPTION_IFETCH_INSTRUCTION_TLB         0x0a       // ITLB miss
+#  define EXCEPTION_IFETCH_INSTRUCTION_PAGE        0x04       // No matching or page violation protection in pages tables
+#  define EXCEPTION_IFETCH_BUS_ERROR               0x02       // Access at a invalid physical address
+
+#  define EXCEPTION_DECOD_NONE                     0x00       // none exception
+#  define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION      0x01       // Instruction is illegal (no implemented)
+#  define EXCEPTION_DECOD_SYSCALL                  0x02       // System Call
+//#define EXCEPTION_DECOD_TRAP                     0x0e       // L.trap or debug unit (note : must read SR !)
+#  define EXCEPTION_DECOD_INSTRUCTION_TLB          0x0a       // ITLB miss
+#  define EXCEPTION_DECOD_INSTRUCTION_PAGE         0x04       // No matching or page violation protection in pages tables
+#  define EXCEPTION_DECOD_BUS_ERROR                0x02       // Access at a invalid physical address
+
+#  define EXCEPTION_ALU_NONE                       0x00       // Functionnal unit generate none exception
+#  define EXCEPTION_ALU_RANGE                      0x0b       // 
+#  define EXCEPTION_ALU_SPR_ACCESS_INVALID         0x12       // SPR     present in ALU but not compatible privilege
+#  define EXCEPTION_ALU_SPR_ACCESS_MUST_READ       0x13       // SPR not present in ALU
+#  define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE      0x14       // SPR not present in ALU
+
+#  define EXCEPTION_MEMORY_NONE                    0x00       // Load/Store generate none exception
+#  define EXCEPTION_MEMORY_ALIGNMENT               0x06       // Load/Store access is not aligned
+#  define EXCEPTION_MEMORY_DATA_TLB                0x09       // DTLB miss
+#  define EXCEPTION_MEMORY_DATA_PAGE               0x03       // No matching or page violation protection in pages tables
+#  define EXCEPTION_MEMORY_BUS_ERROR               0x02       // Access at a invalid physical address
+#  define EXCEPTION_MEMORY_MISS_SPECULATION        0x10       // Load miss speculation
+#  define EXCEPTION_MEMORY_LOAD_SPECULATIVE        0x11       // The load is speculative : write in register file, but don't commit
+
+#  define EXCEPTION_CUSTOM_NONE                    0x00       // Custom unit generate none exception
+#  define EXCEPTION_CUSTOM_CUST_0                  0x19       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_1                  0x1a       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_2                  0x1b       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_3                  0x1c       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_4                  0x1d       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_5                  0x1e       // Reserved for custom exceptions
+#  define EXCEPTION_CUSTOM_CUST_6                  0x1f       // Reserved for custom exceptions
+
+#  define EXCEPTION_USE_NONE                       0x00       // 
+#  define EXCEPTION_USE_ILLEGAL_INSTRUCTION        0x01       // illegal_instruction
+#  define EXCEPTION_USE_RANGE                      0x02       // range
+#  define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT      0x03       // TLB miss, page fault, bus error, alignment
+#  define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT   0x04       // TLB miss, page fault, bus error
+#  define EXCEPTION_USE_SYSCALL                    0x05       // syscall
+#  define EXCEPTION_USE_TRAP                       0x06       // trap
+#  define EXCEPTION_USE_CUSTOM_0                   0x07       // 
+#  define EXCEPTION_USE_CUSTOM_1                   0x08       // 
+#  define EXCEPTION_USE_CUSTOM_2                   0x09       // 
+#  define EXCEPTION_USE_CUSTOM_3                   0x0a       // 
+#  define EXCEPTION_USE_CUSTOM_4                   0x0b       // 
+#  define EXCEPTION_USE_CUSTOM_5                   0x0c       // 
+#  define EXCEPTION_USE_CUSTOM_6                   0x0d       // 
+
+#  define exception_ifetch_to_exception_decod(x) x
+#  define exception_decod_to_exception(x)        x
+#  define exception_alu_to_exception(x)          x
+#  define exception_memory_to_exception(x)       x
+#  define exception_custom_to_exception(x)       x
 
   //=======================================================[ icache ]=====
@@ -298,10 +355,10 @@
   //--------------------------------------------------[ icache_type ]-----
 
-#  define SIZE_ICACHE_TYPE                              2
-
-#  define ICACHE_TYPE_LOAD                              0x0        // 0000
-#  define ICACHE_TYPE_LOCK                              0x1        // 0001
-#  define ICACHE_TYPE_INVALIDATE                        0x2        // 0010
-#  define ICACHE_TYPE_PREFETCH                          0x3        // 0011
+#  define SIZE_ICACHE_TYPE                         2
+
+#  define ICACHE_TYPE_LOAD                         0x0        // 0000
+#  define ICACHE_TYPE_LOCK                         0x1        // 0001
+#  define ICACHE_TYPE_INVALIDATE                   0x2        // 0010
+#  define ICACHE_TYPE_PREFETCH                     0x3        // 0011
 
 // just take the 2 less significative bits.
@@ -310,8 +367,8 @@
   //-------------------------------------------------[ icache_error ]-----
 
-#  define SIZE_ICACHE_ERROR                             1
-
-#  define ICACHE_ERROR_NONE                             0x0
-#  define ICACHE_ERROR_BUS_ERROR                        0x1
+#  define SIZE_ICACHE_ERROR                        1
+
+#  define ICACHE_ERROR_NONE                        0x0
+#  define ICACHE_ERROR_BUS_ERROR                   0x1
 
   //=======================================================[ dcache ]=====
@@ -319,22 +376,22 @@
   //--------------------------------------------------[ dcache_type ]-----
 
-#  define SIZE_DCACHE_TYPE                              4
-
-//#define DCACHE_TYPE_                                  0x0        // 0000
-#  define DCACHE_TYPE_LOCK                              0x1        // 0001
-#  define DCACHE_TYPE_INVALIDATE                        0x2        // 0010
-#  define DCACHE_TYPE_PREFETCH                          0x3        // 0011
-//#define DCACHE_TYPE_                                  0x4        // 0100
-//#define DCACHE_TYPE_                                  0x5        // 0101
-#  define DCACHE_TYPE_FLUSH                             0x6        // 0110
-#  define DCACHE_TYPE_SYNCHRONIZATION                   0x7        // 0111
-#  define DCACHE_TYPE_LOAD_8                            0x8        // 1000
-#  define DCACHE_TYPE_LOAD_16                           0x9        // 1001
-#  define DCACHE_TYPE_LOAD_32                           0xa        // 1010
-#  define DCACHE_TYPE_LOAD_64                           0xb        // 1011
-#  define DCACHE_TYPE_STORE_8                           0xc        // 1100
-#  define DCACHE_TYPE_STORE_16                          0xd        // 1101
-#  define DCACHE_TYPE_STORE_32                          0xe        // 1110
-#  define DCACHE_TYPE_STORE_64                          0xf        // 1111
+#  define SIZE_DCACHE_TYPE                         4
+
+//#define DCACHE_TYPE_                             0x0        // 0000
+#  define DCACHE_TYPE_LOCK                         0x1        // 0001
+#  define DCACHE_TYPE_INVALIDATE                   0x2        // 0010
+#  define DCACHE_TYPE_PREFETCH                     0x3        // 0011
+//#define DCACHE_TYPE_                             0x4        // 0100
+//#define DCACHE_TYPE_                             0x5        // 0101
+#  define DCACHE_TYPE_FLUSH                        0x6        // 0110
+#  define DCACHE_TYPE_SYNCHRONIZATION              0x7        // 0111
+#  define DCACHE_TYPE_LOAD_8                       0x8        // 1000
+#  define DCACHE_TYPE_LOAD_16                      0x9        // 1001
+#  define DCACHE_TYPE_LOAD_32                      0xa        // 1010
+#  define DCACHE_TYPE_LOAD_64                      0xb        // 1011
+#  define DCACHE_TYPE_STORE_8                      0xc        // 1100
+#  define DCACHE_TYPE_STORE_16                     0xd        // 1101
+#  define DCACHE_TYPE_STORE_32                     0xe        // 1110
+#  define DCACHE_TYPE_STORE_64                     0xf        // 1111
 
 // just take the 4 less significative bits.
@@ -343,21 +400,21 @@
   //-------------------------------------------------[ dcache_error ]-----
 
-#  define SIZE_DCACHE_ERROR                             1
-
-#  define DCACHE_ERROR_NONE                             0x0
-#  define DCACHE_ERROR_BUS_ERROR                        0x1
+#  define SIZE_DCACHE_ERROR                        1
+
+#  define DCACHE_ERROR_NONE                        0x0
+#  define DCACHE_ERROR_BUS_ERROR                   0x1
 
   //=================================================[ special_data ]=====
 
-#  define SIZE_SPECIAL_DATA                             2
+#  define SIZE_SPECIAL_DATA                        2
 
 // Position of flag in "rename register SR" (NOT IN "SR")
-#  define FLAG_POSITION_F                               0x0         // Conditionnal branch flag
-#  define FLAG_POSITION_CY                              0x1         // Carry was produced by last arithmetic operation
-#  define FLAG_POSITION_OV                              0x0         // Overflow occured during last arithmetic operation
-
-#  define FLAG_F                                        (1<<FLAG_POSITION_F ) // Conditionnal branch flag
-#  define FLAG_CY                                       (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation
-#  define FLAG_OV                                       (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation
+#  define FLAG_POSITION_F                          0x0         // Conditionnal branch flag
+#  define FLAG_POSITION_CY                         0x1         // Carry was produced by last arithmetic operation
+#  define FLAG_POSITION_OV                         0x0         // Overflow occured during last arithmetic operation
+
+#  define FLAG_F                                   (1<<FLAG_POSITION_F ) // Conditionnal branch flag
+#  define FLAG_CY                                  (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation
+#  define FLAG_OV                                  (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation
 
   //==========================================================[ spr ]=====
@@ -396,8 +453,8 @@
       GROUP_CUSTOM_6,            // 29     
       GROUP_CUSTOM_7,            // 30     
-      GROUP_CUSTOM_8             // 31     
+      GROUP_CUSTOM_8,            // 31     
+      NB_GROUP
     };
 
-#  define NB_GROUP                                 32
 #  define NB_REG_GROUP_SYSTEM_AND_CONTROL          1536
 #  define NB_REG_GROUP_DMMU                        1536
@@ -432,5 +489,72 @@
 #  define NB_REG_GROUP_CUSTOM_7                    0
 #  define NB_REG_GROUP_CUSTOM_8                    0
-					           
+
+  static const uint32_t NB_REG_GROUP [] =
+    {NB_REG_GROUP_SYSTEM_AND_CONTROL  ,
+     NB_REG_GROUP_DMMU                ,
+     NB_REG_GROUP_IMMU                ,
+     NB_REG_GROUP_DCACHE              ,
+     NB_REG_GROUP_ICACHE              ,
+     NB_REG_GROUP_MAC                 ,
+     NB_REG_GROUP_DEBUG               ,
+     NB_REG_GROUP_PERFORMANCE_COUNTER ,
+     NB_REG_GROUP_POWER_MANAGEMENT    ,
+     NB_REG_GROUP_PIC                 ,
+     NB_REG_GROUP_TICK_TIMER          ,
+     NB_REG_GROUP_FLOATING_POINT      ,
+     NB_REG_GROUP_RESERVED_1          ,
+     NB_REG_GROUP_RESERVED_2          ,
+     NB_REG_GROUP_RESERVED_3          ,
+     NB_REG_GROUP_RESERVED_4          ,
+     NB_REG_GROUP_RESERVED_5          ,
+     NB_REG_GROUP_RESERVED_6          ,
+     NB_REG_GROUP_RESERVED_7          ,
+     NB_REG_GROUP_RESERVED_8          ,
+     NB_REG_GROUP_RESERVED_9          ,
+     NB_REG_GROUP_RESERVED_10         ,
+     NB_REG_GROUP_RESERVED_11         ,
+     NB_REG_GROUP_RESERVED_12         ,
+     NB_REG_GROUP_CUSTOM_1            ,
+     NB_REG_GROUP_CUSTOM_2            ,
+     NB_REG_GROUP_CUSTOM_3            ,
+     NB_REG_GROUP_CUSTOM_4            ,
+     NB_REG_GROUP_CUSTOM_5            ,
+     NB_REG_GROUP_CUSTOM_6            ,
+     NB_REG_GROUP_CUSTOM_7            ,
+     NB_REG_GROUP_CUSTOM_8            };
+  
+  // GROUP_SYSTEM_AND_CONTROL
+#  define SPR_VR                                   0          // Version register
+#  define SPR_UPR                                  1          // Unit Present register
+#  define SPR_CPUCFGR                              2          // CPU Configuration register
+#  define SPR_DMMUCFGR                             3          // Data MMU Configuration register
+#  define SPR_IMMUCFGR                             4          // Instruction MMU Configuration register
+#  define SPR_DCCFGR                               5          // Data Cache Configuration register
+#  define SPR_ICCFGR                               6          // Instruction Cache Configuration register
+#  define SPR_DCFGR                                7          // Debug Configuration register
+#  define SPR_PCCFGR                               8          // Performance Counters Configuration register
+#  define SPR_NPC                                  16         // PC mapped to SPR space (next PC)
+#  define SPR_SR                                   17         // Supervision register
+#  define SPR_PPC                                  18         // PC mapped to SPR space (previous PC)
+#  define SPR_CID                                  19         // Context Id
+#  define SPR_FPCSR                                20         // FP Control Status register
+#  define SPR_EPCR                                 32         // Exception PC register
+#  define SPR_EEAR                                 48         // Exception EA register
+#  define SPR_ESR                                  64         // Exception SR register
+#  define SPR_GPR                                  1024       // GPRs mappted to SPR space
+  
+  // GROUP_DCACHE
+#  define SPR_DCCR                                 0          // DC Control register
+#  define SPR_DCBPR                                1          // DC Block Prefetch register
+#  define SPR_DCBFR                                2          // DC Block Flush register
+#  define SPR_DCBIR                                3          // DC Block Invalidate register
+#  define SPR_DCBWR                                4          // DC Block Write-back register
+#  define SPR_DCBLR                                5          // DC Block Lock register
+
+  // GROUP_ICACHE
+#  define SPR_ICCR                                 0          // IC Control register
+#  define SPR_ICBPR                                1          // IC Block Prefetch register
+#  define SPR_ICBIR                                2          // IC Block Invalidate register
+#  define SPR_ICBLR                                3          // IC Block Lock register
 					           
   // GROUP_MAC				           
@@ -438,4 +562,7 @@
 #  define SPR_MACHI                                2          // MAC High
 
+
+
+  // SR RENAME
 #  define NB_SPR_LOGIC                             2
 #  define LOG2_NB_SPR_LOGIC                        1
@@ -863,197 +990,4 @@
 #  define OPCOD_L_EXTWZ                            0x1           // 0001
 
-  /*
-
-  //--------------------------------------------------[ destination ]-----
-#define                 _size_destination1            4
-
-#define                  cst_DESTINATION1_NONE        0x0
-#define                 mask_DESTINATION1_GPR         0x1
-#define                 mask_DESTINATION1_MEMORY      0x2
-#define                 mask_DESTINATION1_SPR         0x4
-#define                 mask_DESTINATION1_MAC_UNIT    0x8
-  
-#define                 _size_destination2  3
-
-#define                  cst_DESTINATION2_NONE        0x0
-#define                 mask_DESTINATION2_COMMIT      0x1
-#define                 mask_DESTINATION2_MEMORY      0x2
-#define                 mask_DESTINATION2_SPR         0x4
-  
-  //----------------------------------------------------[ exec_flag ]-----
-#define                 _size_exec_flag               2
-
-#define                 mask_EXEC_FLAG_NONE           0x1
-#define                 mask_EXEC_FLAG_CARRY          0x1
-#define                 mask_EXEC_FLAG_FLAG           0x1
-#define                 mask_EXEC_FLAG_OVERFLOW       0x2
-
-  //---------------------------------------------------[ exec_excep ]-----
-#define                  _size_exec_excep             1
-
-#define                 mask_EXEC_EXCEP_NONE          0x0
-#define                 mask_EXEC_EXCEP_RANGE         0x1
-  
-  //----------------------------------------------------[ Condition ]-----
-#define                 _size_condition               3
-    
-#define                  cst_CONDITION_UNCONDITIONAL  0x0           // None condition (jump)
-#define                 mask_CONDITION_CONDITIONAL    0x2           
-#define                 mask_CONDITION_CONDITIONAL_NF 0x0           // Branch if Flag is clear 
-#define                 mask_CONDITION_CONDITIONAL_F  0x1           // Branch if Flag is set   
-#define                 mask_CONDITION_REG            0x4           // Branch if a register is read
-#define                 mask_CONDITION_STACK          0x8           // Branch with pop  in stack pointer
-
-  */
-
-  /*
-#define M_CPU_SIZE_INST       32
-
-//----------------------------------------------------
-// Exception type
-//----------------------------------------------------
-
-#define M_CPU_LOG2_NB_EXCP    5
-#define M_CPU_NB_EXCP         32
-
-#define EXCP_NO               0x00          // none exception
-#define EXCP_RESET            0x01          // software or hardware reset
-#define EXCP_BERR             0x02          // Access at a invalid physical adress
-#define EXCP_D_PAGE           0x03          // No matching or page violation protection in pages tables
-#define EXCP_I_PAGE           0x04          // No matching or page violation protection in pages tables
-#define EXCP_TICK_TIMER       0x05          // Tick timer interruption
-#define EXCP_ALIGNMENT        0x06          // Load/Store access is not aligned
-#define EXCP_ILL_INST         0x07          // Instruction is illegal (no implemented)
-#define EXCP_IRQ              0x08          // External interruption 
-#define EXCP_D_TLB            0x09          // DTLB miss
-#define EXCP_I_TLB            0x0a          // ITLB miss
-#define EXCP_RANGE            0x0b          // Overflow or access at a unimplemented register or context
-#define EXCP_SYSCALL          0x0c          // System Call
-#define EXCP_FP               0x0d          // Caused by a floating instruction
-#define EXCP_TRAP             0x0e          // L.trap or debug unit
-#define EXCP_RES0             0x0f          // Reserved for a futur usage
-#define EXCP_RES1             0x10          // Reserved for a futur usage
-#define EXCP_RES2             0x11          // Reserved for a futur usage
-#define EXCP_RES3             0x12          // Reserved for a futur usage
-#define EXCP_RES4             0x13          // Reserved for a futur usage
-#define EXCP_RES5             0x14          // Reserved for a futur usage
-#define EXCP_RES6             0x15          // Reserved for implemented specific exceptions
-#define EXCP_RES7             0x16          // Reserved for implemented specific exceptions
-#define EXCP_RES8             0x17          // Reserved for implemented specific exceptions
-#define EXCP_RES9             0x18          // Reserved for implemented specific exceptions
-#define EXCP_CUST0            0x19          // Reserved for custom exceptions
-#define EXCP_CUST1            0x1a          // Reserved for custom exceptions
-#define EXCP_CUST2            0x1b          // Reserved for custom exceptions
-#define EXCP_CUST3            0x1c          // Reserved for custom exceptions
-#define EXCP_CUST4            0x1d          // Reserved for custom exceptions
-#define EXCP_CUST5            0x1e          // Reserved for custom exceptions
-#define EXCP_CUST6            0x1f          // Reserved for custom exceptions
-
-//----------------------------------------------------
-// Flags
-//----------------------------------------------------
-
-#define M_CPU_NB_FLAG         3
-
-// Integer flags
-#define FLAG_F                0x1           // Conditionnal branch flag
-#define FLAG_CY               0x2           // Carry was produced by last arithmétic operation
-#define FLAG_OV               0x4           // Overflow occured during last arithmetic operation
-
-// Floating flags
-#define FLAG_OVF              0x004         // Overflow occured during last arithmetic operation
-#define FLAG_UNF              0x008         // Underflow flags
-#define FLAG_SNF              0x010         // Result SNAN
-#define FLAG_QNF              0x020         // Result QNAN
-#define FLAG_ZF               0x040         // Result is nul
-#define FLAG_IXF              0x080         // Result is inexact
-#define FLAG_IVF              0x100         // Result is invalid
-#define FLAG_INF              0x200         // Result is infinite
-#define FLAG_DZF              0x400         // Division by zero
-
-// Position of flag in "rename register SR" (NOT IN "SR")
-#define FLAG_POS_F            0x0           // Conditionnal branch flag
-#define FLAG_POS_CY           0x1           // Carry was produced by last arithmétic operation
-#define FLAG_POS_OV           0x0           // Overflow occured during last arithmetic operation
-
-//----------------------------------------------------
-// Instruction type
-//----------------------------------------------------
-
-#define M_CPU_LOG2_NB_TYPE    4
-
-#define TYPE_NOP              0x0
-#define TYPE_ALU_F            0x1           // Instruction ALU with    flag using (ADD, SUB, ADDC ...)
-#define TYPE_ALU_NF           0x2           // Instruction ALU without flag using (AND, OR ...)
-#define TYPE_MAC              0x3           // Instruction ALU with    utilisation of register HI/LO
-#define TYPE_J                0x4           // Branch instruction
-#define TYPE_SPR_READ         0x5           // Instruction special : l.mfspr
-#define TYPE_SPR_WRITE        0x6           // Instruction special : l.mtspr
-#define TYPE_SPECIAL          0x7           // Instruction execute in decode stage
-#define TYPE_CUSTOM           0x8           // Instruction Custom
-
-#define TYPE_LOAD_Z           0x9           // Load  access (extended by zero)
-#define TYPE_LOAD_S           0xa           // Load  access (sign extended)
-#define TYPE_STORE            0xc           // Store access
-
-//----------------------------------------------------
-// Condition to branch
-//----------------------------------------------------
-
-#define M_CPU_LOG2_NB_COND    4
-
-#define COND_NONE             0x0           // None condition (jump)
-#define COND_F                0x2           // Branch if Flag is set
-#define COND_NF               0x3           // Branch if Flag is clear
-#define COND_REG              0x4           // Branch if a register is read
-#define COND_STACK            0x8           // Branch with pop  in stack pointer
-
-//----------------------------------------------------
-// Event : State and Type
-//----------------------------------------------------
-
-#define EVENT_STATE_NO_EVENT  0             // no event : current case
-#define EVENT_STATE_EVENT     1             // Have a event : make necessary to manage the event
-#define EVENT_STATE_WAITEND   2             // Wait end of manage event (restaure a good context)
-#define EVENT_STATE_END       3             // CPU can continue
-
-#define EVENT_TYPE_MISS       0             // miss of speculation
-#define EVENT_TYPE_EXCP       1             // exception or interruption occure
-
-// SPEC? TAKE?
-#define BRANCH_STATE_NONE         0  // 0     0
-#define BRANCH_STATE_NSPEC_TAKE   1  // 0     1  -> incondionnal
-#define BRANCH_STATE_SPEC_NTAKE   2  // 1     0
-#define BRANCH_STATE_SPEC_TAKE    3  // 1     1
-
-//----------------------------------------------------
-// Name to particular register
-//----------------------------------------------------
-
-//~~~~~~~~~~~~~~~~~~~~~~~~~~
-// GENERAL PURPOSE REGISTER
-//~~~~~~~~~~~~~~~~~~~~~~~~~~
-#define M_CPU_LOG2_NB_GPR_LOG 5
-#define M_CPU_NB_GPR_LOG      (1<<M_CPU_LOG2_NB_GPR_LOG)
-
-#define GPR_LOG_LR            0x09          // Link register
-#define REG_PHY_SR            0x00          // Status register
-
-//~~~~~~~~~~~~~~~~~~~~~~~~~~
-// SPECIAL PURPOSE REGISTER
-//~~~~~~~~~~~~~~~~~~~~~~~~~~
-#define M_CPU_LOG2_NB_SPR_LOG 1
-#define M_CPU_NB_SPR_LOG      (1<<M_CPU_LOG2_NB_SPR_LOG)
-#define M_CPU_SPR_SIZE_DATA   2             // Size of the most great register 
-
-#define SPR_LOG_SR_F          0x00          // Status register bit F                   (size = 1)
-#define SPR_LOG_SR_CY_OV      0x01          // Status register bit overflow and carry  (size = 2)
-//#define SPR_LOG_SR_LO         0x02          // MAC LSB                                 (size = 32)
-//#define SPR_LOG_SR_HI         0x03          // MAC MSB                                 (size = 32)
-  */
-
-  /*
-  */
-
 }; // end namespace behavioural
 }; // end namespace morpheo              
