Index: trunk/Documents/INSTALL =================================================================== --- trunk/Documents/INSTALL (revision 88) +++ trunk/Documents/INSTALL (revision 88) @@ -0,0 +1,45 @@ +-------------------------------------------------- + Table of contents +-------------------------------------------------- + + I - Install + +-------------------------------------------------- + I - Install +-------------------------------------------------- + +Follow this step to install the Morpheo Tools Chain + +1) Install GNU-Toolchain + +cf Tools-source/or1k_toolchain-build-instructions.txt + +2) Install newlib + +Now you can compile a software and use the libc and libm + +3) Install a simulator + +3a) systemC +... + +3b) systemCASS + +4) Install soclib + +... + +5) Link + +This step consist at create all symbolik link + * Morpheo/Tools : + - newlib + - or1k + - soclib + - systemc (or systemcass) + * Morpheo/Software/*/src/sys/ + - crt0.s with $TOOLS/newlib/libgloss/or32/crt0.S + * Morpheo/IPs/systemC/shared/ + - mapping_memory.h + +6) Enjoy Index: trunk/Documents/MORPHEO-Install.txt =================================================================== --- trunk/Documents/MORPHEO-Install.txt (revision 87) +++ (revision ) @@ -1,45 +1,0 @@ --------------------------------------------------- - Table of contents --------------------------------------------------- - - I - Install - --------------------------------------------------- - I - Install --------------------------------------------------- - -Follow this step to install the Morpheo Tools Chain - -1) Install GNU-Toolchain - -cf Tools-source/or1k_toolchain-build-instructions.txt - -2) Install newlib - -Now you can compile a software and use the libc and libm - -3) Install a simulator - -3a) systemC -... - -3b) systemCASS - -4) Install soclib - -... - -5) Link - -This step consist at create all symbolik link - * Morpheo/Tools : - - newlib - - or1k - - soclib - - systemc (or systemcass) - * Morpheo/Software/*/src/sys/ - - crt0.s with $TOOLS/newlib/libgloss/or32/crt0.S - * Morpheo/IPs/systemC/shared/ - - mapping_memory.h - -6) Enjoy Index: trunk/IPs/systemC/Environment/Cache/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Cache/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Cache/Makefile (revision 88) @@ -4,4 +4,6 @@ #-----[ Variable ]----------------------------------------- + +ENTITY ?= Cache OBJECTS_DEPS = $(patsubst $(DIR_QUEUE)/$(DIR_SRC)/%.cpp,$(DIR_QUEUE)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_QUEUE)/$(DIR_SRC)/*.cpp)) @@ -19,4 +21,6 @@ $(MAKE) environment_clean; +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/Common/include/Debug.h =================================================================== --- trunk/IPs/systemC/Environment/Common/include/Debug.h (revision 87) +++ trunk/IPs/systemC/Environment/Common/include/Debug.h (revision 88) @@ -3,13 +3,13 @@ #define DEBUG_ENVIRONMENT true -#define DEBUG_CACHE false -#define DEBUG_DATA false -#define DEBUG_ENDIANNESS false -#define DEBUG_QUEUE false -#define DEBUG_RAMLOCK false -#define DEBUG_SIM2OS false -#define DEBUG_TTY false +#define DEBUG_CACHE true +#define DEBUG_DATA true +#define DEBUG_ENDIANNESS true +#define DEBUG_QUEUE true +#define DEBUG_RAMLOCK true +#define DEBUG_SIM2OS true +#define DEBUG_TTY true -#ifdef DEBUG +// #ifdef DEBUG # define _cout(component, str...) \ do \ @@ -19,11 +19,13 @@ fprintf(stdout,str); \ } \ - } while(0) -#else -# define _cout(component, str...) \ - do \ - { \ - } while(0) -#endif + } \ + while(0) +// #else +// # define _cout(component, str...) +// do +// { +// } +// while(0) +// #endif #endif Index: trunk/IPs/systemC/Environment/Data/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Data/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Data/Makefile (revision 88) @@ -4,4 +4,6 @@ #-----[ Variable ]----------------------------------------- + +ENTITY ?= Data # OBJECTS_DEPS = $(patsubst $(DIR_ENDIANNESS)/$(DIR_SRC)/%.cpp,$(DIR_ENDIANNESS)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_ENDIANNESS)/$(DIR_SRC)/*.cpp)) @@ -21,4 +23,6 @@ # $(MAKE) --directory=$(DIR_ENDIANNESS) clean; \ +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/Data/include/Segment.h =================================================================== --- trunk/IPs/systemC/Environment/Data/include/Segment.h (revision 87) +++ trunk/IPs/systemC/Environment/Data/include/Segment.h (revision 88) @@ -39,4 +39,5 @@ public : void read (uint32_t address, uint32_t size, char * & data_dest); public : void write (uint32_t address, uint32_t size, char * & data_src); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output, Segment & x); }; Index: trunk/IPs/systemC/Environment/Data/src/Segment_init.cpp =================================================================== --- trunk/IPs/systemC/Environment/Data/src/Segment_init.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Data/src/Segment_init.cpp (revision 88) @@ -1,3 +1,4 @@ #include "../include/Segment.h" +#include "../../Common/include/Debug.h" namespace environment { @@ -22,6 +23,31 @@ memcpy(data, ptab, size); - + free (ptab); + + +// { +// _cout(DATA,"Segment Init\n"); +// _cout(DATA," * size : %d\n",size); +// _cout(DATA," * size : %d\n",this->size); +// _cout(DATA,"%s\n",print(0).c_str()); + +// uint32_t addr = base; +// uint32_t step1 = 4; +// uint32_t step2 = step1*8; + +// for (int32_t i=0; i(data[i])); +// } +// _cout(DATA,"\n"); +// } return true; Index: trunk/IPs/systemC/Environment/Data/src/Segment_print.cpp =================================================================== --- trunk/IPs/systemC/Environment/Data/src/Segment_print.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Data/src/Segment_print.cpp (revision 88) @@ -1,16 +1,28 @@ #include "../include/Segment.h" +#include namespace environment { namespace data { + + std::string Segment::print(uint32_t depth) + { + std::ostringstream out(""); + std::string tab = std::string(depth,'\t'); + + + out << tab << "Segment \"" << name << "\"" << std::endl + << std::hex + << tab << " * base : " << std::setw(8) << std::setfill('0') << base << std::endl + << tab << " * size : " << std::setw(8) << std::setfill('0') << size << std::endl + << std::dec + << tab << " * uncached : " << uncached << std::endl + << tab << " * type : " << type; + + return out.str(); + } std::ostream& operator<< (std::ostream& output, Segment & x) { - output << "Segment \"" << x.name << "\"" << std::endl - << std::hex - << " * base : " << std::setw(8) << std::setfill('0') << x.base << std::endl - << " * size : " << std::setw(8) << std::setfill('0') << x.size << std::endl - << std::dec - << " * uncached : " << x.uncached << std::endl - << " * type : " << x.type; + output << x.print(0); return output; Index: trunk/IPs/systemC/Environment/Endianness/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Endianness/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Endianness/Makefile (revision 88) @@ -2,4 +2,6 @@ #-----[ Variable ]----------------------------------------- + +ENTITY ?= Endianness #OBJECTS_DEPS = @@ -15,4 +17,6 @@ $(MAKE) environment_clean; +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Makefile (revision 88) @@ -1,13 +1,18 @@ #-----[ Directory ]---------------------------------------- -DIR_CACHE = Cache -DIR_DATA = Data -DIR_ENDIANNESS = Endianness -DIR_QUEUE = Queue -DIR_RAMLOCK = RamLock -DIR_SIM2OS = Sim2OS -DIR_TTY = TTY +DIR_LIB = ./lib +DIR_CACHE = ./Cache +DIR_DATA = ./Data +DIR_ENDIANNESS = ./Endianness +DIR_QUEUE = ./Queue +DIR_RAMLOCK = ./RamLock +DIR_SIM2OS = ./Sim2OS +DIR_TTY = ./TTY #-----[ Variable ]----------------------------------------- +ENTITY ?= Environment + +LIBRARY_NAME = Environment +LIBRARY_FILE = $(DIR_LIB)/lib$(LIBRARY_NAME).a OBJECTS_DEPS = $(patsubst $(DIR_CACHE)/$(DIR_SRC)/%.cpp,$(DIR_CACHE)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_CACHE)/$(DIR_SRC)/*.cpp)) \ @@ -18,19 +23,64 @@ $(patsubst $(DIR_RAMLOCK)/$(DIR_SRC)/%.cpp,$(DIR_RAMLOCK)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_RAMLOCK)/$(DIR_SRC)/*.cpp)) \ $(patsubst $(DIR_SIM2OS)/$(DIR_SRC)/%.cpp,$(DIR_SIM2OS)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_SIM2OS)/$(DIR_SRC)/*.cpp)) \ - $(patsubst $(DIR_TTY)/$(DIR_SRC)/%.cpp,$(DIR_TTY)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_TTY)/$(DIR_SRC)/*.cpp)) + $(patsubst $(DIR_TTY)/$(DIR_SRC)/%.cpp,$(DIR_TTY)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_TTY)/$(DIR_SRC)/*.cpp)) #-----[ Rules ]-------------------------------------------- -all : +all : a b c d e f g @\ - $(MAKE) --directory=$(DIR_CACHE) all; \ - $(MAKE) --directory=$(DIR_DATA) all; \ - $(MAKE) --directory=$(DIR_ENDIANNESS) all; \ - $(MAKE) --directory=$(DIR_QUEUE) all; \ - $(MAKE) --directory=$(DIR_RAMLOCK) all; \ - $(MAKE) --directory=$(DIR_SIM2OS) all; \ - $(MAKE) --directory=$(DIR_TTY) all; \ - $(MAKE) all_environment; + $(MAKE) all_environment; \ + $(MAKE) $(LIBRARY_FILE); + +a : + @\ + $(MAKE) --directory=$(DIR_CACHE) all; + +b : + @\ + $(MAKE) --directory=$(DIR_DATA) all; + +c : + @\ + $(MAKE) --directory=$(DIR_ENDIANNESS) all; + +d : + @\ + $(MAKE) --directory=$(DIR_QUEUE) all; + +e : + @\ + $(MAKE) --directory=$(DIR_RAMLOCK) all; + +f : + @\ + $(MAKE) --directory=$(DIR_SIM2OS) all; + +g : + @\ + $(MAKE) --directory=$(DIR_TTY) all; + + +$(LIBRARY_FILE) : $(OBJECTS_DEPS) $(OBJECTS) $(DIR_LIB) + @\ + $(ECHO) "Archive : $@";\ + $(AR) -r $@ $(OBJECTS_DEPS) $(OBJECTS);\ + $(RANLIB) $@; + +$(DIR_LIB) : + @\ + $(ECHO) "Create directory : $@";\ + $(MKDIR) $@; + +exe_all : + @\ + $(MAKE) --directory=$(DIR_CACHE) exe; \ + $(MAKE) --directory=$(DIR_DATA) exe; \ + $(MAKE) --directory=$(DIR_ENDIANNESS) exe; \ + $(MAKE) --directory=$(DIR_QUEUE) exe; \ + $(MAKE) --directory=$(DIR_RAMLOCK) exe; \ + $(MAKE) --directory=$(DIR_SIM2OS) exe; \ + $(MAKE) --directory=$(DIR_TTY) exe; \ + $(MAKE) exe; \ clean : @@ -46,4 +96,7 @@ $(RM) tty_*; +clean_all : clean + @\ + $(RM) $(DIR_LIB); help : Index: trunk/IPs/systemC/Environment/Makefile.Environment =================================================================== --- trunk/IPs/systemC/Environment/Makefile.Environment (revision 87) +++ trunk/IPs/systemC/Environment/Makefile.Environment (revision 88) @@ -1,11 +1,18 @@ -include $(MORPHEO_TOPLEVEL)/Makefile.tools -include $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools + include $(MORPHEO_TOPLEVEL)/Makefile.flags +endif #-----[ Directory ]---------------------------------------- -DIR_TST = selftest -DIR_INC = include -DIR_SRC = src -DIR_OBJ = obj -DIR_BIN = bin +ENTITY ?= Environment + +DIR_TMP = $(MORPHEO_TMP)/$(ENTITY) +DIR_TST = ./selftest +DIR_INC = ./include +DIR_SRC = ./src +DIR_OBJ = ./obj +DIR_BIN = $(DIR_TMP)/bin #-----[ Compilation ]-------------------------------------- @@ -16,6 +23,7 @@ LIBDIR = $(SYSTEMC_LIBDIR_$(SIMULATOR)) -LIBNAME = $(SYSTEMC_LIBNAME_$(SIMULATOR)) \ - -lbfd +LIBNAME = -lbfd \ + -liberty \ + $(SYSTEMC_LIBNAME_$(SIMULATOR)) FLAGS = $(SYSTEMC_CFLAGS_$(SIMULATOR)) @@ -26,6 +34,4 @@ #-----[ Variable ]----------------------------------------- - -ENTITY = `$(BASENAME) $$PWD` OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) \ @@ -42,4 +48,9 @@ #-----[ Rules ]-------------------------------------------- +vpath %.h $(DIR_INC) +vpath %.c $(DIR_SRC) +vpath %.cpp $(DIR_SRC):$(DIR_TST) +vpath %.o $(DIR_OBJ) + .PRECIOUS : $(DIR_OBJ)/%.o $(DIR_BIN)/%.x @@ -48,18 +59,13 @@ $(ECHO) "-------------------| $(ENTITY)" -$(DIR_OBJ)/%.o : $(DIR_SRC)/%.cpp $(HEADERS) +$(DIR_OBJ)/%.o : %.cpp $(HEADERS) @\ $(ECHO) "Compilation : $*";\ $(CXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; -$(DIR_OBJ)/%.o : $(DIR_SRC)/%.c $(HEADERS) +$(DIR_OBJ)/%.o : %.c $(HEADERS) @\ $(ECHO) "Compilation : $*";\ $(CC) $(MORPHEO_CC_FLAGS) -c -o $@ $<; - -$(DIR_OBJ)/%.o : $(DIR_TST)/%.cpp $(HEADERS) - @\ - $(ECHO) "Compilation : $*";\ - $(CXX) $(MORPHEO_CXX_FLAGS) -c -o $@ $<; $(DIR_BIN)/%.x : $(OBJECTS_DEPS) $(OBJECTS) $(OBJECTS_BIN) @@ -79,12 +85,13 @@ -exe : all +exe : all $(DIR_BIN) @\ - export SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(EXEC_PREFIX) ./$(EXE) $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR)) + $(MAKE) $(EXE); \ + export SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(EXEC_PREFIX) $(EXE) $(SYSTEMC_EXEC_PARAMS_$(SIMULATOR)) -all_environment : test_env $(DIR_OBJ) $(DIR_BIN) +all_environment : test_env $(DIR_OBJ) @\ - $(MAKE) $(EXE) + $(MAKE) $(OBJECTS_DEPS) $(OBJECTS) $(OBJECTS_BIN) environment_clean : @@ -104,5 +111,6 @@ $(ECHO) " -----[ Environment ]------------------------------";\ $(ECHO) "";\ - $(ECHO) " * test_env : test if environnment's variable is set";\ - $(ECHO) " * all_environment : generate object";\ + $(ECHO) " * exe : execute testbench";\ + $(ECHO) " * test_env : test if environnment's variable is set";\ + $(ECHO) " * all_environment : generate object";\ $(ECHO) ""; Index: trunk/IPs/systemC/Environment/Makefile.deps =================================================================== --- trunk/IPs/systemC/Environment/Makefile.deps (revision 88) +++ trunk/IPs/systemC/Environment/Makefile.deps (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# + +#-----[ Test ]--------------------------------------------- + +# Test Environment variables +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif + +#-----[ Variables ]---------------------------------------- + +ENVIRONMENT_DIR = $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment +ENVIRONMENT_INCDIR = -I$(ENVIRONMENT_DIR)/include +ENVIRONMENT_LIBDIR = -L$(ENVIRONMENT_DIR)/lib +ENVIRONMENT_LIBNAME = -lEnvironment -lbfd -liberty Index: trunk/IPs/systemC/Environment/Queue/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Queue/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Queue/Makefile (revision 88) @@ -1,2 +1,6 @@ +#-----[ Variables ]---------------------------------------- + +ENTITY ?= Queue + #-----[ Rules ]-------------------------------------------- @@ -7,4 +11,6 @@ @$(MAKE) environment_clean +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/RamLock/Makefile =================================================================== --- trunk/IPs/systemC/Environment/RamLock/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/RamLock/Makefile (revision 88) @@ -1,2 +1,6 @@ +#-----[ Variables ]---------------------------------------- + +ENTITY ?= RamLock + #-----[ Rules ]-------------------------------------------- @@ -7,4 +11,6 @@ @$(MAKE) environment_clean +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/Sim2OS/Makefile =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/Makefile (revision 88) @@ -4,4 +4,6 @@ #-----[ Variable ]----------------------------------------- + +ENTITY ?= Sim2OS OBJECTS_DEPS = $(patsubst $(DIR_ENDIANNESS)/$(DIR_SRC)/%.cpp,$(DIR_ENDIANNESS)/$(DIR_OBJ)/%.o,$(wildcard $(DIR_ENDIANNESS)/$(DIR_SRC)/*.cpp)) @@ -19,4 +21,6 @@ $(MAKE) environment_clean +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_convert_address.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_convert_address.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_convert_address.cpp (revision 88) @@ -9,9 +9,9 @@ void * Sim2OS::convert_address (void * address) { - void * result = param->segment_table->getAddrAlloc((uint32_t)address); + void * result = param->segment_table->getAddrAlloc(static_cast(reinterpret_cast(address))); if (result == NULL) { - std::cerr << "<" << name << "> address don't match : " << std::hex << (uint32_t)(address) << std::dec << std::endl; + std::cerr << "<" << name << "> address don't match : " << std::hex << static_cast(reinterpret_cast(address)) << std::dec << std::endl; exit(0); } Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_parameter.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_parameter.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_parameter.cpp (revision 88) @@ -13,5 +13,5 @@ { if (num_reg == 0) - num_service = int2service((int)(val)); + num_service = int2service(static_cast(reinterpret_cast(val))); else arguments[num_reg] = val; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_clock.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_clock.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_clock.cpp (revision 88) @@ -16,6 +16,6 @@ std::cout << "\n\t***** service : clock *****" << std::endl; - std::cout << "\tresult : " << (unsigned int) result << std::endl; - std::cout << "\terrno : " << (unsigned int) error << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; + std::cout << "\terrno : " << error << std::endl; return result; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_close.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_close.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_close.cpp (revision 88) @@ -12,5 +12,5 @@ } - int fd = (int) arguments[1]; + int fd = static_cast(reinterpret_cast(arguments[1])); void * result = (void *) close(fd); error = errno; @@ -18,5 +18,5 @@ std::cout << "\n\t***** service : close *****" << std::endl; std::cout << "\tfd : " << (unsigned int) fd << std::endl; - std::cout << "\tresult : " << (unsigned int) result << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_lseek.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_lseek.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_lseek.cpp (revision 88) @@ -12,7 +12,7 @@ } - int flides = (int) arguments[1]; - off_t offset = (off_t) arguments[2]; - int whence = (int) arguments[3]; + int flides = static_cast(reinterpret_cast(arguments[1])); + off_t offset = static_cast(reinterpret_cast(arguments[2])); + int whence = static_cast(reinterpret_cast(arguments[3])); void * result = (void *) lseek(flides,offset,whence); error = errno; @@ -24,5 +24,5 @@ std::cout << "\toffset : " << (unsigned int) offset << std::endl; std::cout << "\twhence : " << (unsigned int) whence << std::endl; - std::cout << "\tresult : " << (unsigned int) result << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_open.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_open.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_open.cpp (revision 88) @@ -13,6 +13,6 @@ const char *pathname = (const char *) convert_address(arguments[1]); - int flags = (int) arguments[2]; - mode_t mode = (mode_t) arguments[3]; + int flags = static_cast(reinterpret_cast(arguments[2])); + mode_t mode = static_cast(reinterpret_cast(arguments[3])); void * result = (void *) open(pathname,flags,mode); error = errno; @@ -26,5 +26,5 @@ std::cout << "\tmode /10 : " << std::dec << (unsigned int) mode << std::endl; std::cout << "\tmode /16 : " << std::hex << (unsigned int) mode << std::endl; - std::cout << "\tresult : " << std::dec << (unsigned int) result << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_read.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_read.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_read.cpp (revision 88) @@ -12,5 +12,5 @@ } - int fd = (int) arguments[1]; + int fd = static_cast(reinterpret_cast(arguments[1])); void * buf = (void *) convert_address(arguments[2]); ssize_t count = (ssize_t) arguments[3]; @@ -19,8 +19,8 @@ std::cout << "\n\t***** service : read *****" << std::endl; std::cout << "\tfd : " << (unsigned int) fd << std::endl; - std::cout << "\tbuf : " << std::hex << (unsigned int) buf << std::endl; + std::cout << "\tbuf : " << std::hex << static_cast(reinterpret_cast(buf)) << std::endl; //std::cout << "\tbuf : " << std::dec << (char *) buf << std::endl; std::cout << "\tcount : " << std::dec << (unsigned int) count << std::endl; - std::cout << "\tresult : " << (unsigned int) result << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_time.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_time.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_time.cpp (revision 88) @@ -17,6 +17,6 @@ std::cout << "\n\t***** service : time *****" << std::endl; - std::cout << "\tt : " << std::hex << (unsigned int) t << std::endl; - std::cout << "\tresult : " << std::dec << (unsigned int) result << " - " << ctime((time_t *) t) << std::endl; + std::cout << "\tt : " << std::hex << static_cast(reinterpret_cast(t)) << std::endl; + std::cout << "\tresult : " << std::dec << static_cast(reinterpret_cast(result)) << " - " << ctime((time_t *) t) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_write.cpp =================================================================== --- trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_write.cpp (revision 87) +++ trunk/IPs/systemC/Environment/Sim2OS/src/Sim2OS_service_write.cpp (revision 88) @@ -12,5 +12,5 @@ } - int fd = (int) arguments[1]; + int fd = static_cast(reinterpret_cast(arguments[1])); const void *buf = (const void *) convert_address(arguments[2]); ssize_t count = (ssize_t) arguments[3]; @@ -22,8 +22,8 @@ std::cout << "\n\t***** service : write *****" << std::endl; std::cout << "\tfd : " << (unsigned int) fd << std::endl; - std::cout << "\tbuf : " << std::hex << (unsigned int) buf << std::endl; + std::cout << "\tbuf : " << std::hex << static_cast(reinterpret_cast(buf)) << std::endl; //std::cout << "\tbuf : " << std::dec << (char *) buf << std::endl; std::cout << "\tcount : " << std::dec << (unsigned int) count << std::endl; - std::cout << "\tresult : " << (unsigned int) result << std::endl; + std::cout << "\tresult : " << static_cast(reinterpret_cast(result)) << std::endl; std::cout << "\terrno : " << (unsigned int) error << std::endl; Index: trunk/IPs/systemC/Environment/TTY/Makefile =================================================================== --- trunk/IPs/systemC/Environment/TTY/Makefile (revision 87) +++ trunk/IPs/systemC/Environment/TTY/Makefile (revision 88) @@ -2,4 +2,6 @@ #-----[ Variable ]----------------------------------------- + +ENTITY ?= TTY #OBJECTS_DEPS = @@ -16,4 +18,6 @@ $(RM) tty_*; +clean_all : clean + help : @$(MAKE) environment_help Index: trunk/IPs/systemC/Environment/include/Cache_Access.h =================================================================== --- trunk/IPs/systemC/Environment/include/Cache_Access.h (revision 87) +++ trunk/IPs/systemC/Environment/include/Cache_Access.h (revision 88) @@ -22,6 +22,6 @@ }; - Cache_Access ireq_type2cache_type (Ticache_type_t ireq_type, bool uncached); - Cache_Access dreq_type2cache_type (Tdcache_type_t dreq_type, bool uncached); + Cache_Access ireq_type2cache_type (morpheo::Ticache_type_t ireq_type, bool uncached); + Cache_Access dreq_type2cache_type (morpheo::Tdcache_type_t dreq_type, bool uncached); }; #endif Index: trunk/IPs/systemC/Environment/include/Environment.h =================================================================== --- trunk/IPs/systemC/Environment/include/Environment.h (revision 87) +++ trunk/IPs/systemC/Environment/include/Environment.h (revision 88) @@ -20,6 +20,6 @@ namespace environment { - typedef Respons irsp_t; - typedef Respons drsp_t; + typedef Respons irsp_t; + typedef Respons drsp_t; class Environment : public sc_module @@ -29,38 +29,38 @@ public : sc_in * NRESET ; - public : sc_in *** ICACHE_REQ_VAL ; - public : sc_out *** ICACHE_REQ_ACK ; - public : sc_in *** ICACHE_REQ_CONTEXT_ID ; - public : sc_in *** ICACHE_REQ_PACKET_ID ; - public : sc_in *** ICACHE_REQ_ADDRESS ; - public : sc_in *** ICACHE_REQ_TYPE ; + public : sc_in *** ICACHE_REQ_VAL ;//[nb_entity][icache_dedicated_nb_port] + public : sc_out *** ICACHE_REQ_ACK ;//[nb_entity][icache_dedicated_nb_port] + public : sc_in *** ICACHE_REQ_CONTEXT_ID ;//[nb_entity][icache_dedicated_nb_port] + public : sc_in *** ICACHE_REQ_PACKET_ID ;//[nb_entity][icache_dedicated_nb_port] + public : sc_in *** ICACHE_REQ_ADDRESS ;//[nb_entity][icache_dedicated_nb_port] + public : sc_in *** ICACHE_REQ_TYPE ;//[nb_entity][icache_dedicated_nb_port] - public : sc_out *** ICACHE_RSP_VAL ; - public : sc_in *** ICACHE_RSP_ACK ; - public : sc_out *** ICACHE_RSP_CONTEXT_ID ; - public : sc_out *** ICACHE_RSP_PACKET_ID ; - public : sc_out **** ICACHE_RSP_INSTRUCTION;//[nb_instruction] - public : sc_out *** ICACHE_RSP_ERROR ; + public : sc_out *** ICACHE_RSP_VAL ;//[nb_entity][icache_dedicated_nb_port] + public : sc_in *** ICACHE_RSP_ACK ;//[nb_entity][icache_dedicated_nb_port] + public : sc_out *** ICACHE_RSP_CONTEXT_ID ;//[nb_entity][icache_dedicated_nb_port] + public : sc_out *** ICACHE_RSP_PACKET_ID ;//[nb_entity][icache_dedicated_nb_port] + public : sc_out **** ICACHE_RSP_INSTRUCTION;//[nb_entity][icache_dedicated_nb_port][iaccess_nb_instruction] + public : sc_out *** ICACHE_RSP_ERROR ;//[nb_entity][icache_dedicated_nb_port] - public : sc_in *** DCACHE_REQ_VAL ; - public : sc_out *** DCACHE_REQ_ACK ; - public : sc_in *** DCACHE_REQ_CONTEXT_ID ; - public : sc_in *** DCACHE_REQ_PACKET_ID ; - public : sc_in *** DCACHE_REQ_ADDRESS ; - public : sc_in *** DCACHE_REQ_TYPE ; - public : sc_in *** DCACHE_REQ_WDATA ; + public : sc_in *** DCACHE_REQ_VAL ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_out *** DCACHE_REQ_ACK ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_REQ_CONTEXT_ID ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_REQ_PACKET_ID ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_REQ_ADDRESS ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_REQ_TYPE ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_REQ_WDATA ;//[nb_entity][dcache_dedicated_nb_port] - public : sc_out *** DCACHE_RSP_VAL ; - public : sc_in *** DCACHE_RSP_ACK ; - public : sc_out *** DCACHE_RSP_CONTEXT_ID ; - public : sc_out *** DCACHE_RSP_PACKET_ID ; - public : sc_out *** DCACHE_RSP_RDATA ; - public : sc_out *** DCACHE_RSP_ERROR ; + public : sc_out *** DCACHE_RSP_VAL ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_in *** DCACHE_RSP_ACK ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_out *** DCACHE_RSP_CONTEXT_ID ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_out *** DCACHE_RSP_PACKET_ID ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_out *** DCACHE_RSP_RDATA ;//[nb_entity][dcache_dedicated_nb_port] + public : sc_out *** DCACHE_RSP_ERROR ;//[nb_entity][dcache_dedicated_nb_port] // ===== [ Internal ]==================================================== - public : Tcontrol_t ** icache_req_ack ; - public : Tcontrol_t ** icache_rsp_val ; - public : Tcontrol_t ** dcache_req_ack ; - public : Tcontrol_t ** dcache_rsp_val ; + public : morpheo::Tcontrol_t ** icache_req_ack ; + public : morpheo::Tcontrol_t ** icache_rsp_val ; + public : morpheo::Tcontrol_t ** dcache_req_ack ; + public : morpheo::Tcontrol_t ** dcache_rsp_val ; // ===== [ Variables ]=================================================== @@ -68,7 +68,11 @@ private : Parameters * param; - private: char ** read_iram; - private: char ** read_dram; - private: char * write_dram; + private : char ** read_iram; + private : char ** read_dram; + private : char * write_dram; + + private : bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal) + private : uint32_t nb_context_stop; // stop the simulation when all context have send the stop signal + // ===== [ Components ]================================================== @@ -88,9 +92,11 @@ public : ~Environment (void); - public : bool init (std::string section, const char * filename, const char ** list_section); - public : void reset (void); + public : bool init (std::string section, const char * filename, const char ** list_section); + public : void reset (void); + public : void stop (uint32_t num_context); + public : bool simulation_end (void); - public : void transition (void); - public : void genMoore (void); + public : void transition (void); + public : void genMoore (void); public : friend std::ostream& operator<< (std::ostream& output, Environment &x); @@ -137,17 +143,4 @@ } }; - - -// private: bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal) -// private: uint3 nb_context_stop; // stop the simulation when all context have send the stop signal - -// //--------------------------------------------------------------------------------------------- -// //-----[ stop ]-------------------------------------------------------------------------------- -// //--------------------------------------------------------------------------------------------- -// public : bool stop () -// { -// return (nb_context_stop >= nb_context); -// } - }; Index: trunk/IPs/systemC/Environment/include/Environment_Parameters.h =================================================================== --- trunk/IPs/systemC/Environment/include/Environment_Parameters.h (revision 87) +++ trunk/IPs/systemC/Environment/include/Environment_Parameters.h (revision 88) @@ -8,4 +8,5 @@ #include "../RamLock/include/RamLock_Parameters.h" #include "../Sim2OS/include/Sim2OS_Parameters.h" +#include "../../processor/Morpheo/Common/include/ToString.h" namespace environment { @@ -13,41 +14,41 @@ class Parameters { - public : uint32_t nb_iport; - public : uint32_t nb_dport; - public : uint32_t nb_entity; - public : uint32_t * icache_dedicated_nb_port; - public : uint32_t * dcache_dedicated_nb_port; - - public : uint32_t * iaccess_nb_context ; - public : uint32_t * iaccess_nb_packet ; - public : uint32_t * iaccess_size_address ; - public : uint32_t * iaccess_nb_instruction; - public : uint32_t * iaccess_size_instruction; - - public : uint32_t * daccess_nb_context ; - public : uint32_t * daccess_nb_packet ; - public : uint32_t * daccess_size_address ; - public : uint32_t * daccess_size_data ; + public : uint32_t nb_iport ; + public : uint32_t nb_dport ; + public : uint32_t nb_entity ; + public : uint32_t * icache_dedicated_nb_port; //[nb_entity] + public : uint32_t * dcache_dedicated_nb_port; //[nb_entity] + + public : uint32_t * iaccess_nb_context ; //[nb_entity] + public : uint32_t * iaccess_nb_packet ; //[nb_entity] + public : uint32_t * iaccess_size_address ; //[nb_entity] + public : uint32_t * iaccess_nb_instruction ; //[nb_entity] + public : uint32_t * iaccess_size_instruction; //[nb_entity] + + public : uint32_t * daccess_nb_context ; //[nb_entity] + public : uint32_t * daccess_nb_packet ; //[nb_entity] + public : uint32_t * daccess_size_address ; //[nb_entity] + public : uint32_t * daccess_size_data ; //[nb_entity] // Parameters cache - public : cache::Parameters * param_cache; + public : cache::Parameters * param_cache ; // Parameters tty - public : uint32_t nb_component_tty; - public : uint32_t * tty_address; - public : tty::Parameters ** param_tty; + public : uint32_t nb_component_tty ; + public : uint32_t * tty_address ; //[nb_component_tty] + public : tty::Parameters ** param_tty ; //[nb_component_tty] // Parameters ramlock - public : uint32_t nb_component_ramlock; - public : uint32_t * ramlock_address; - public : ramlock::Parameters ** param_ramlock; + public : uint32_t nb_component_ramlock ; + public : uint32_t * ramlock_address ; //[nb_component_ramlock] + public : ramlock::Parameters ** param_ramlock ; //[nb_component_ramlock] // Parameters sim2OS - public : uint32_t sim2os_address; - public : uint32_t sim2os_size; - public : sim2os::Parameters * param_sim2os; + public : uint32_t sim2os_address ; + public : uint32_t sim2os_size ; + public : sim2os::Parameters * param_sim2os ; // Parameters data - public : data::Parameters * param_data; + public : data::Parameters * param_data ; // Parameters buffer_respons - public : queue::Parameters ** param_buffer_irsp; - public : queue::Parameters ** param_buffer_drsp; + public : queue::Parameters ** param_buffer_irsp ; //[nb_entity] + public : queue::Parameters ** param_buffer_drsp ; //[nb_entity] public : Parameters (// General @@ -232,4 +233,76 @@ delete param_cache; } + + public : std::string print (uint32_t depth) + { + std::string tab = std::string(depth,'\t'); + std::string str = ""; + + str+=tab+"nb_entity : "+morpheo::toString(nb_entity)+"\n"; + str+=tab+"nb_iport : "+morpheo::toString(nb_iport )+"\n"; + str+=tab+"nb_dport : "+morpheo::toString(nb_dport )+"\n"; + for (uint32_t i=0; iprint(depth+1); + +// str+=tab+"nb_component_tty : "+morpheo::toString(nb_component_tty )+"\n"; +// for (uint32_t i=0; iprint(depth+1); +// } + +// str+=tab+"nb_component_ramlock : "+morpheo::toString(nb_component_ramlock )+"\n"; +// for (uint32_t i=0; iprint(depth+1); +// } + +// str+=tab+"SIM2OS\n"; +// str+=tab+"sim2os_address : "+morpheo::toString(sim2os_address)+"\n"; +// str+=tab+"sim2os_size : "+morpheo::toString(sim2os_size )+"\n"; +// str+=param_sim2os->print(depth+1); + +// str+=tab+"DATA\n"; +// str+=param_data->print(depth+1); + +// for (uint32_t i=0; iprint(depth+1); +// } + +// for (uint32_t i=0; iprint(depth+1); +// } + + return str; + } + +// public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x) +// { +// x.print(0); +// return output; +// } }; Index: trunk/IPs/systemC/Environment/include/Types.h =================================================================== --- trunk/IPs/systemC/Environment/include/Types.h (revision 87) +++ trunk/IPs/systemC/Environment/include/Types.h (revision 88) @@ -2,5 +2,5 @@ #define ENVIRONMENT_TYPES_H -#include "../../processor/Morpheo/Behavioural/include/Types.h" +#include "../../processor/Morpheo/TopLevel/include/Types.h" #include "../../processor/Morpheo/Behavioural/include/Constants.h" #include "../Cache/include/Types.h" @@ -9,19 +9,20 @@ { - typedef morpheo::behavioural::Tcontrol_t Tcontrol_t ; +// typedef morpheo::behavioural::Tcontrol_t Tcontrol_t ; - typedef morpheo::behavioural::Tcontext_t Ticache_context_t ; - typedef morpheo::behavioural::Tpacket_t Ticache_packet_t ; - typedef morpheo::behavioural::Ticache_address_t Ticache_address_t ; - typedef morpheo::behavioural::Ticache_type_t Ticache_type_t ; - typedef morpheo::behavioural::Ticache_instruction_t Ticache_instruction_t; - typedef morpheo::behavioural::Ticache_error_t Ticache_error_t ; +// typedef morpheo::behavioural::Tcontext_t Ticache_context_t ; +// typedef morpheo::behavioural::Tpacket_t Ticache_packet_t ; +// typedef morpheo::behavioural::Ticache_address_t Ticache_address_t ; +// typedef morpheo::behavioural::Ticache_type_t Ticache_type_t ; +// typedef morpheo::behavioural::Ticache_instruction_t Ticache_instruction_t; +// typedef morpheo::behavioural::Ticache_error_t Ticache_error_t ; - typedef morpheo::behavioural::Tcontext_t Tdcache_context_t ; - typedef morpheo::behavioural::Tpacket_t Tdcache_packet_t ; - typedef morpheo::behavioural::Tdcache_address_t Tdcache_address_t ; - typedef morpheo::behavioural::Tdcache_type_t Tdcache_type_t ; - typedef morpheo::behavioural::Tdcache_data_t Tdcache_data_t ; - typedef morpheo::behavioural::Tdcache_error_t Tdcache_error_t ; +// typedef morpheo::behavioural::Tcontext_t Tdcache_context_t ; +// typedef morpheo::behavioural::Tpacket_t Tdcache_packet_t ; +// typedef morpheo::behavioural::Tdcache_address_t Tdcache_address_t ; +// typedef morpheo::behavioural::Tdcache_type_t Tdcache_type_t ; +// typedef morpheo::behavioural::Tdcache_data_t Tdcache_data_t ; +// typedef morpheo::behavioural::Tdcache_error_t Tdcache_error_t ; + }; #endif Index: trunk/IPs/systemC/Environment/selftest/main.cpp =================================================================== --- trunk/IPs/systemC/Environment/selftest/main.cpp (revision 87) +++ trunk/IPs/systemC/Environment/selftest/main.cpp (revision 88) @@ -4,4 +4,5 @@ using namespace std; using namespace environment; +using namespace morpheo; #define _TEST_IMEMORY_ true @@ -206,5 +207,5 @@ dcache_miss_penality, 1 , -// cache_shared_nb_port , +// cache_shared_nb_port , cache_shared_nb_line , cache_shared_size_line , @@ -218,5 +219,5 @@ nb_tty, name_tty, - false, + false, // don't execute xtty nb_component_ramlock, @@ -458,5 +459,5 @@ ICACHE_REQ_VAL [i][j]->write((addr < addr_max) and ((rand()%100)write(0); - ICACHE_REQ_ADDRESS [i][j]->write(addr); + ICACHE_REQ_ADDRESS [i][j]->write(addr>>2); ICACHE_REQ_PACKET_ID [i][j]->write(addr>>2); ICACHE_REQ_TYPE [i][j]->write(ICACHE_TYPE_LOAD); @@ -535,5 +536,5 @@ ICACHE_REQ_VAL [0][0]->write(1); ICACHE_REQ_CONTEXT_ID [0][0]->write(0); - ICACHE_REQ_ADDRESS [0][0]->write(0xe0000000); + ICACHE_REQ_ADDRESS [0][0]->write(0xe0000000>>2); ICACHE_REQ_PACKET_ID [0][0]->write(21); ICACHE_REQ_TYPE [0][0]->write(ICACHE_TYPE_LOAD); @@ -561,5 +562,5 @@ ICACHE_REQ_VAL [0][0]->write(1); ICACHE_REQ_CONTEXT_ID [0][0]->write(0); - ICACHE_REQ_ADDRESS [0][0]->write(0xa0000000); + ICACHE_REQ_ADDRESS [0][0]->write(0xa0000000>>2); ICACHE_REQ_PACKET_ID [0][0]->write(21); ICACHE_REQ_TYPE [0][0]->write(ICACHE_TYPE_LOAD); Index: trunk/IPs/systemC/Environment/src/Environment.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment.cpp (revision 87) +++ trunk/IPs/systemC/Environment/src/Environment.cpp (revision 88) @@ -1,3 +1,5 @@ #include "../include/Environment.h" + +using namespace morpheo; namespace environment { @@ -60,6 +62,4 @@ - - for (uint32_t i=0; inb_entity; i++) { @@ -79,4 +79,8 @@ read_dram[0] = new char [max_data_size/8]; write_dram = new char [max_data_size/8]; + context_stop = new bool [param->nb_entity]; + for (uint32_t i=0; inb_entity; ++i) + context_stop [i] = false; + nb_context_stop = 0; // Port Index: trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp (revision 88) @@ -1,3 +1,5 @@ #include "../include/Environment.h" + +using namespace morpheo; namespace environment { Index: trunk/IPs/systemC/Environment/src/Environment_simulation_end.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_simulation_end.cpp (revision 88) +++ trunk/IPs/systemC/Environment/src/Environment_simulation_end.cpp (revision 88) @@ -0,0 +1,10 @@ +#include "../include/Environment.h" + +namespace environment { + + bool Environment::simulation_end(void) + { + return (nb_context_stop >= param->nb_entity); + } + +}; Index: trunk/IPs/systemC/Environment/src/Environment_stop.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_stop.cpp (revision 88) +++ trunk/IPs/systemC/Environment/src/Environment_stop.cpp (revision 88) @@ -0,0 +1,17 @@ +#include "../include/Environment.h" + +namespace environment { + + void Environment::stop(uint32_t num_context) + { + if (context_stop [num_context] == false) + { + context_stop [num_context] = true; + nb_context_stop ++; + + if (nb_context_stop >= param->nb_entity) + sc_stop(); + } + } + +}; Index: trunk/IPs/systemC/Environment/src/Environment_transition.cpp =================================================================== --- trunk/IPs/systemC/Environment/src/Environment_transition.cpp (revision 87) +++ trunk/IPs/systemC/Environment/src/Environment_transition.cpp (revision 88) @@ -1,3 +1,5 @@ #include "../include/Environment.h" + +using namespace morpheo; namespace environment { @@ -43,7 +45,7 @@ Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence - Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read(); + Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2; Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read(); - uint32_t size = param->iaccess_size_address [i]/8; + uint32_t size = (param->iaccess_size_address [i]+2)/8; _cout(ENVIRONMENT," * information\n"); @@ -67,5 +69,5 @@ (entity.segment->getType() == data::TYPE_TARGET_MEMORY)) { - _cout(ENVIRONMENT, " * OK !\n"); + _cout(ENVIRONMENT," * OK !\n"); bus_error = false; uncached = entity.segment->getUncached(); @@ -73,10 +75,10 @@ if (must_read == true) // Test if must read the ram { - _cout(ENVIRONMENT, " * must read\n"); + _cout(ENVIRONMENT," * must read\n"); // Read all instruction for (unsigned int k=0; kiaccess_nb_instruction[i]; k++) { uint32_t addr = address+k*(size); - _cout(ENVIRONMENT, " * addr : %.8x\n",addr); + _cout(ENVIRONMENT," * addr : %.8x\n",addr); bus_error |= !component_data->read(addr,size,read_iram[k]); @@ -84,5 +86,12 @@ // Swap if endienness is different if (endianness::isSameEndianness(context) == false) - read_iram[k] = endianness::swapBytes(read_iram[k],size,size); + { + read_iram[k] = endianness::swapBytes(read_iram[k],size,size); + } + + _cout(ENVIRONMENT," * inst :"); + for (int32_t cpt=(param->iaccess_size_instruction[context]/8)-1; cpt>=0; --cpt) + _cout(ENVIRONMENT, "%.2x",0xff&static_cast(read_iram[k][cpt])); + _cout(ENVIRONMENT, "\n"); } } @@ -241,14 +250,7 @@ ,static_cast((wdata>> 0)&0xff) ); + + stop (context); -// if (context_stop [context] == false) -// { -// context_stop [context] = true; -// nb_context_stop ++; - -// if (nb_context_stop >= nb_context) -// sc_stop(); -// } - break; } @@ -387,5 +389,5 @@ { // Decomposition en groupe octect - Tdcache_data_t result = (Tdcache_data_t)(component_sim2os->result); + Tdcache_data_t result = static_cast(reinterpret_cast(component_sim2os->result)); _cout(ENVIRONMENT," result : %x\n",result); @@ -494,5 +496,4 @@ component_buffer_drsp [i]->push(latence,rsp); } - } //============================================================================= Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libConfiguration.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/Makefile.deps (revision 88) @@ -0,0 +1,46 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Configuration = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Custom +include $(DIR_MORPHEO)/Behavioural/Custom/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Configuration_DIR = $(DIR_MORPHEO)/Behavioural/Configuration + +#-----[ Library ]------------------------------------------ + +Configuration_LIBRARY = $(Behavioural_LIBRARY) \ + -lConfiguration \ + $(Custom_LIBRARY) \ + $(Behavioural_LIBRARY) + +Configuration_DIR_LIBRARY = -L$(Configuration_DIR)/lib \ + $(Custom_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Configuration_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Custom_library; \ + $(MAKE) --directory=$(Configuration_DIR) --makefile=Makefile; + +Configuration_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Custom_library_clean; \ + $(MAKE) --directory=$(Configuration_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/Makefile (revision 88) @@ -0,0 +1,34 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Configuration_LIBRARY) + +DIR_LIBRARY = $(Configuration_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Configuration_library + +library_clean : Configuration_library_clean + +local_clean : + @$(RM) data_in/*~ \ + data_out/* + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/include/test.h (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Configuration/include/Configuration.h" + +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::configuration; + +void test (string name); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,59 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/SelfTest/include/test.h" + +#define NB_PARAMS 0 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance.\n"),argv[0]); + err ("argc : %d\n",argc); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + int _return = EXIT_SUCCESS; + + try + { + test (name); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Configuration : no error"); + else + TEST_KO("Configuration : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,85 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Configuration/SelfTest/include/test.h" +#include "Behavioural/Custom/include/Custom_default.h" +#include "Behavioural/Custom/include/Custom_example.h" + +void test (string name) +{ + morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information); + + cout << "------------------------------------------------------" << endl; + + Simulator * simulator1 = new Simulator ("../../../Files/Morpheo.sim"); + +//cout << *simulator1 << endl; + + simulator1->toFile("data_out"); + + cout << "------------------------------------------------------" << endl; + + Generator * generator1 = new Generator ("../../../Files/Morpheo.gen"); + +//cout << *generator1 << endl; + + generator1->toFile("data_out"); + + cout << "------------------------------------------------------" << endl; + + Instance * instance1 = new Instance ("../../../Files/Instance_min.cfg", + generator1, + _get_custom_information + ); + +// cout << *instance1 << endl; + + instance1->toFile("data_out"); + + cout << "------------------------------------------------------" << endl; + + Configuration * configuration1 = new Configuration("../../../Files/Morpheo.sim", + "../../../Files/Morpheo.gen", + "../../../Files/Instance_min.cfg", + _get_custom_information); + +//cout << *configuration1 << endl; + + configuration1->toFile("data_out"); + + { + cout << "------------------------------------------------------" << endl; + + Instance * instance = new Instance ("../../../Files/Instance_scalar_1.cfg", + generator1, + _get_custom_information + ); + instance->toFile("data_out"); + + delete instance; + } + + { + cout << "------------------------------------------------------" << endl; + + Instance * instance = new Instance ("../../../Files/Instance_scalar_2.cfg", + generator1, + _get_custom_information + ); + instance->toFile("data_out"); + + delete instance; + } + + delete configuration1; + delete instance1; + delete generator1; + delete simulator1; + + +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h (revision 88) @@ -0,0 +1,62 @@ +#ifndef morpheo_behavioural_configuration_Configuration_h +#define morpheo_behavioural_configuration_Configuration_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" +#include "Behavioural/Configuration/include/Generator.h" +#include "Behavioural/Configuration/include/Instance.h" +#include "Behavioural/Custom/include/Custom.h" + +#include "Behavioural/include/Usage.h" +#include "Behavioural/include/Parameters_Statistics.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Configuration + { + // -----[ fields ]---------------------------------------------------- + private : std::string _name; + private : Simulator * _simulator; + private : Generator * _generator; + private : Instance * _instance ; + + private : Parameters * _param; + private : morpheo::behavioural::Parameters_Statistics * _param_statistics; + + private : Tusage_t _usage; + + // -----[ methods ]--------------------------------------------------- + public : Configuration (std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + behavioural::custom::custom_information_t (*get_custom_information) (void)); + public : ~Configuration (); + + public : std::string getName (void); + public : Tusage_t getUsage (void); + public : Parameters * getParam (void); + public : morpheo::behavioural::Parameters_Statistics * getParamStatistics (void); + + public : void toFile (std::string dirname="."); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Configuration & x); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Generator.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Generator.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Generator.h (revision 88) @@ -0,0 +1,57 @@ +#ifndef morpheo_behavioural_configuration_Generator_h +#define morpheo_behavioural_configuration_Generator_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_definition.h" +#include "Behavioural/Configuration/include/Link_definition.h" +#include "Behavioural/Configuration/include/XMLUtils.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Generator + { + // -----[ fields ]---------------------------------------------------- + private : std::string _filename; + private : std::map * _array_param; + private : std::map * _array_link; + + // -----[ methods ]--------------------------------------------------- + public : Generator (std::string filename); + public : ~Generator (); + + public : Parameter_definition * getParam (std::string name); + public : Link_definition * getLink (std::string name); + + + public : void test (std::string param, + std::string x); + public : void test (std::string link, + std::string father_name, + bool father_is_src, + bool father_is_dest); + + private : void insert (Parameter_definition * param); + private : void insert (Link_definition * param); + private : void fromFile (std::string filename); + + public : void toFile (std::string dirname="."); + private : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Generator & x); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Instance.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Instance.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Instance.h (revision 88) @@ -0,0 +1,205 @@ +#ifndef morpheo_behavioural_configuration_Instance_h +#define morpheo_behavioural_configuration_Instance_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_affectation.h" +#include "Behavioural/Configuration/include/Link_affectation.h" +#include "Behavioural/Configuration/include/Generator.h" +#include "Behavioural/Configuration/include/Parameters.h" +#include "Behavioural/Custom/include/Custom.h" + +#include +#include +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Instance_component; + + typedef std::map list_parameters_t; + typedef std::map list_link_t; + typedef std::map list_links_t; + typedef std::map list_instances_t; + typedef std::map list_components_t; + + class Instance_component + { + public : const std::string _name; + public : const std::string _id; + public : list_parameters_t * _list_parameters; +//public : list_links_t * _list_links; + public : list_components_t * _list_components; + + public : Instance_component (std::string name, + std::string id): + _name (name), + _id (id) + { + _list_parameters = new list_parameters_t; +// _list_links = new list_links_t ; + _list_components = new list_components_t; + } + + public : ~Instance_component (void) + { + for (list_parameters_t::iterator it = _list_parameters->begin(); + it != _list_parameters->end(); + ++it) + delete it->second; + delete _list_parameters; + +// for (list_links_t::iterator it1 = _list_links->begin(); +// it1 != _list_links->end(); +// ++it1) +// for (list_link_t::iterator it2 = it1->second.begin(); +// it2 != it1->second.end(); +// ++it2) +// delete it2->second; +// delete _list_links; + + for (list_components_t::iterator it1 = _list_components->begin(); + it1 != _list_components->end(); + ++it1) + for (list_instances_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + delete it2->second; + delete _list_components; + } + +#undef FUNCTION +#define FUNCTION "Instance_component::toXML" + public : XML toXML (void) + { + log_begin(Configuration,FUNCTION); + + XML xml (_name); + + xml.balise_open_begin(_name); + xml. attribut("id" ,_id); + xml.balise_open_end(); + + for (list_parameters_t::iterator it = _list_parameters->begin(); + it != _list_parameters->end(); + ++it) + xml.insert_XML(it->second->toXML(),1); + +// for (list_links_t::iterator it1 = _list_links->begin(); +// it1 != _list_links->end(); +// ++it1) +// for (list_link_t::iterator it2 = it1->second.begin(); +// it2 != it1->second.end(); +// ++it2) +// xml.insert_XML(it2->second->toXML(),1); + + for (list_components_t::iterator it1 = _list_components->begin(); + it1 != _list_components->end(); + ++it1) + for (list_instances_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + xml.insert_XML(it2->second->toXML(),1); + + xml.balise_close(); + + log_end(Configuration,FUNCTION); + return xml; + } + +#undef FUNCTION +#define FUNCTION "Instance_component::print" + private : std::string print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Instance_component::operator<<" + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Instance_component & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + }; + + + class Instance + { + // -----[ fields ]---------------------------------------------------- + private : std::string _name; + private : std::string _filename; +//private : list_parameters_t * _array; + + public : list_parameters_t * _list_parameters; + public : list_links_t * _list_links; + public : list_components_t * _list_components; + + private : Generator * _generator; + public : Parameters * _param; + + // -----[ methods ]--------------------------------------------------- + public : Instance (std::string filename, + Generator * generator, + behavioural::custom::custom_information_t (*get_custom_information) (void)); + public : ~Instance (); + + public : std::string getName (void); + private : std::string getParam (const char * name, ...); + private : std::vector getLink (const char * name, ...); + private : std::vector link2array (std::string str); + + // Test : parameter, link, component + public : void test (std::string type, + std::string value); + public : void test (std::string type, + std::string father_name, + bool father_is_src, + bool father_is_dest); + private : void test (std::string link, + std::vector & vect, + uint32_t nb_elt); + private : void test_use (void); + private : void test_use (std::string name, + list_parameters_t * list_parameters, + list_components_t * list_components, + std::vector & list_not_use); + + private : void fromInternalStructure(void); + + private : void fromXMLLight(XML_t * xml, + attribute_t id, + list_parameters_t * list_parameters, + list_links_t * list_links, + list_components_t * list_component); + + private : void fromFile (std::string filename); + + public : void toFile (std::string dirname="."); + private : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Instance & x); + + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_affectation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_affectation.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_affectation.h (revision 88) @@ -0,0 +1,48 @@ +#ifndef morpheo_behavioural_configuration_Link_affectation_h +#define morpheo_behavioural_configuration_Link_affectation_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/XML.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Link_affectation + { + // -----[ fields ]---------------------------------------------------- + // Constant + public : const std::string _name; + public : const std::string _src ; + public : const std::string _dest; + public : bool _use ; + + // -----[ methods ]--------------------------------------------------- + public : Link_affectation (std::string name, + std::string src , + std::string dest + ); + public : ~Link_affectation (); + + public : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Link_affectation & x); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_definition.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_definition.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Link_definition.h (revision 88) @@ -0,0 +1,52 @@ +#ifndef morpheo_behavioural_configuration_Link_definition_h +#define morpheo_behavioural_configuration_Link_definition_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/XML.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + + class Link_definition + { + // -----[ fields ]---------------------------------------------------- + // Constant + public : const std::string _name ; + public : const std::string _src ; + public : const std::string _dest ; + public : const std::string _description; + + // -----[ methods ]--------------------------------------------------- + public : Link_definition (std::string name , + std::string src , + std::string dest , + std::string description ); + public : ~Link_definition (); + +//public : bool test (uint32_t x); + + public : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Link_definition & x); + + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_affectation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_affectation.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_affectation.h (revision 88) @@ -0,0 +1,46 @@ +#ifndef morpheo_behavioural_configuration_Parameter_affectation_h +#define morpheo_behavioural_configuration_Parameter_affectation_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/XML.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Parameter_affectation + { + // -----[ fields ]---------------------------------------------------- + // Constant + public : const std::string _name ; + public : const std::string _value; + public : bool _use ; + + // -----[ methods ]--------------------------------------------------- + public : Parameter_affectation (std::string name, + std::string value + ); + public : ~Parameter_affectation (); + + public : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Parameter_affectation & x); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_definition.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_definition.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameter_definition.h (revision 88) @@ -0,0 +1,58 @@ +#ifndef morpheo_behavioural_configuration_Parameter_definition_h +#define morpheo_behavioural_configuration_Parameter_definition_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/XML.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + + class Parameter_definition + { + // -----[ fields ]---------------------------------------------------- + // Constant + public : const std::string _name ; + public : const std::string _min ; + public : const std::string _max ; + public : const std::string _step ; + public : const std::string _default ; + public : const std::string _level ; + public : const std::string _description; + + // -----[ methods ]--------------------------------------------------- + public : Parameter_definition (std::string name , + std::string min , + std::string max , + std::string step , + std::string value_default, + std::string level , + std::string description ); + public : ~Parameter_definition (); + + public : void test (std::string x); + + public : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Parameter_definition & x); + + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 88) @@ -0,0 +1,177 @@ +#ifndef morpheo_behavioural_configuration_Parameters_h +#define morpheo_behavioural_configuration_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Parameters + { + // -----[ parameters ]------------------------------------------------ + // Common + public : uint32_t _size_general_data ; + public : uint32_t _size_special_data ; + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); + + // Thread + public : uint32_t _nb_thread ; + public : uint32_t * _size_ifetch_queue ;//[nb_thread] + public : uint32_t * _nb_inst_fetch ;//[nb_thread] + public : bool ** _implement_group ;//[nb_thread][NB_GROUP] + public : uint32_t * _ras_size_queue ;//[nb_thread] + public : uint32_t * _upt_size_queue ;//[nb_thread] + + // Decod bloc + public : uint32_t _nb_decod_bloc ; + public : uint32_t * _size_decod_queue ;//[nb_decod_bloc] + public : uint32_t * _nb_inst_decod ;//[nb_decod_bloc] + public : uint32_t * _nb_context_select ;//[nb_decod_bloc] + public : Tpriority_t * _context_select_priority ;//[nb_decod_bloc] + public : Tload_balancing_t * _context_select_load_balancing ;//[nb_decod_bloc] + + // Rename bloc + public : uint32_t _nb_rename_bloc ; + public : uint32_t * _nb_inst_insert ;//[nb_rename_bloc] + public : uint32_t * _nb_inst_retire ;//[nb_rename_bloc] + public : Tpriority_t * _rename_select_priority ;//[nb_rename_bloc] + public : Tload_balancing_t * _rename_select_load_balancing ;//[nb_rename_bloc] + public : uint32_t * _rename_select_nb_front_end_select ;//[nb_rename_bloc] + public : uint32_t * _nb_general_register ;//[nb_rename_bloc] + public : uint32_t * _nb_special_register ;//[nb_rename_bloc] + public : uint32_t * _nb_reg_free ;//[nb_rename_bloc] + public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] + public : uint32_t * _size_read_counter ;//[nb_rename_bloc] + + // Read bloc + public : uint32_t _nb_read_bloc ;// + public : uint32_t * _size_read_queue ;//[nb_read_bloc] + public : uint32_t * _size_reservation_station ;//[nb_read_bloc] + public : uint32_t * _nb_inst_retire_reservation_station ;//[nb_read_bloc] + + // Write bloc + public : uint32_t _nb_write_bloc ;// + public : uint32_t * _size_write_queue ;//[nb_write_bloc] + public : uint32_t * _size_execute_queue ;//[nb_write_bloc] + public : uint32_t * _nb_bypass_write ;//[nb_write_bloc] + + // Load_store_unit + public : uint32_t _nb_load_store_unit ; + public : uint32_t * _size_store_queue ;//[nb_load_store_unit] + public : uint32_t * _size_load_queue ;//[nb_load_store_unit] + public : uint32_t * _size_speculative_access_queue ;//[nb_load_store_unit] + public : uint32_t * _nb_port_check ;//[nb_load_store_unit] + public : core::multi_execute_loop::execute_loop::Tspeculative_load_t + * _speculative_load ;//[nb_load_store_unit] + public : uint32_t * _nb_bypass_memory ;//[nb_load_store_unit] + public : uint32_t * _nb_cache_port ;//[nb_load_store_unit] + public : uint32_t * _nb_inst_memory ;//[nb_load_store_unit] + + // Functionnal_unit + public : uint32_t _nb_functionnal_unit ; + public : uint32_t * _nb_inst_functionnal_unit ;//[nb_functionnal_unit] + public : core::multi_execute_loop::execute_loop::execute_timing_t + *** _timing ;//[nb_functionnal_unit][nb_type][nb_operation] + + // Icache_port + public : uint32_t _nb_icache_port ; + public : Tpriority_t _icache_port_priority ; + public : Tload_balancing_t _icache_port_load_balancing ; + + // Dcache_port + public : uint32_t _nb_dcache_port ; + public : Tpriority_t _dcache_port_priority ; + public : Tload_balancing_t _dcache_port_load_balancing ; + + // Front_end + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t * _nb_decod_unit ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_predict ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_decod ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_update ;//[nb_front_end] + public : uint32_t * _btb_size_queue ;//[nb_front_end] + public : uint32_t * _btb_associativity ;//[nb_front_end] + public : uint32_t * _btb_size_counter ;//[nb_front_end] + public : Tvictim_t * _btb_victim_scheme ;//[nb_front_end] + public : Tpredictor_t * _dir_predictor_scheme ;//[nb_front_end] + public : bool ** _dir_have_bht ;//[nb_front_end][3] + public : uint32_t ** _dir_bht_size_shifter ;//[nb_front_end][3] + public : uint32_t ** _dir_bht_nb_shifter ;//[nb_front_end][3] + public : bool ** _dir_have_pht ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_size_counter ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_nb_counter ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_size_address_share ;//[nb_front_end][3] + + // OOO_Engine + public : uint32_t _nb_ooo_engine ; + public : uint32_t * _nb_rename_unit ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_issue ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_reexecute ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_commit ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_branch_complete ;//[nb_ooo_engine] + public : uint32_t * _nb_rename_unit_select ;//[nb_ooo_engine] + public : uint32_t * _nb_execute_loop_select ;//[nb_ooo_engine] + public : uint32_t * _size_re_order_buffer ;//[nb_ooo_engine] + public : uint32_t * _nb_re_order_buffer_bank ;//[nb_ooo_engine] + public : Tpriority_t * _commit_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _commit_load_balancing ;//[nb_ooo_engine] + public : uint32_t * _size_issue_queue ;//[nb_ooo_engine] + public : uint32_t * _nb_issue_queue_bank ;//[nb_ooo_engine] + public : Tpriority_t * _issue_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _issue_load_balancing ;//[nb_ooo_engine] + public : uint32_t * _size_reexecute_queue ;//[nb_ooo_engine] + public : Tpriority_t * _reexecute_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _reexecute_load_balancing ;//[nb_ooo_engine] + + // Execute_loop + public : uint32_t _nb_execute_loop ; + public : uint32_t * _nb_read_unit ;//[nb_execute_loop] + public : uint32_t * _nb_execute_unit ;//[nb_execute_loop] + public : uint32_t * _nb_write_unit ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_bank ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_port_read_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_port_write_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_port_read_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_port_write_by_bank ;//[nb_execute_loop] + public : Tpriority_t * _execution_unit_to_write_unit_priority ;//[nb_execute_loop] + public : Tpriority_t * _read_unit_to_execution_unit_priority ;//[nb_execute_loop] + + // Link + public : pair_dual * _link_context_with_thread ;//[nb_thread] + public : pair_dual * _link_decod_unit_with_decod_bloc ;//[nb_decod_bloc] + public : pair_dual * _link_rename_unit_with_rename_bloc ;//[nb_rename_bloc] + public : pair_dual * _link_read_unit_with_read_bloc ;//[nb_read_bloc] + public : pair_dual * _link_write_unit_with_write_bloc ;//[nb_write_bloc] + public : pair_dual * _link_execute_unit_with_functionnal_unit ;//[nb_functionnal_unit] + public : pair_dual * _link_execute_unit_with_load_store_unit ;//[nb_load_store_unit] + public : uint32_t * _link_decod_bloc_with_thread ;//[nb_thread] + public : uint32_t * _link_rename_bloc_with_front_end ;//[nb_front_end] + public : bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + public : bool ** _link_read_bloc_and_load_store_unit ;//[nb_read_bloc][nb_load_store_unit] + public : bool ** _link_read_bloc_and_functionnal_unit ;//[nb_read_bloc][nb_functionnal_unit] + public : bool ** _link_write_bloc_and_load_store_unit ;//[nb_write_bloc][nb_load_store_unit] + public : bool ** _link_write_bloc_and_functionnal_unit ;//[nb_write_bloc][nb_functionnal_unit] + public : uint32_t * _link_load_store_unit_with_thread ;//[nb_thread] + public : bool ** _link_thread_and_functionnal_unit ;//[nb_thread][nb_functionnal_unit] + public : uint32_t * _link_icache_port_with_thread ;//[nb_thread] + public : uint32_t ** _link_dcache_port_with_load_store_unit ;//[nb_load_store_unit][nb_cache_port] + + public : Tpriority_t _dispatch_priority ; + public : Tload_balancing_t _dispatch_load_balancing ; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Simulator.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Simulator.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Simulator.h (revision 88) @@ -0,0 +1,44 @@ +#ifndef morpheo_behavioural_configuration_Simulator_h +#define morpheo_behavioural_configuration_Simulator_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_affectation.h" +#include "Behavioural/Configuration/include/XMLUtils.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + class Simulator + { + // -----[ fields ]---------------------------------------------------- + private : std::string _filename; + private : std::map * _array; + + // -----[ methods ]--------------------------------------------------- + public : Simulator (std::string filename); + public : ~Simulator (); + + public : std::string getParam (std::string name); + private : void insert (Parameter_affectation * param); + private : void fromFile (std::string filename); + + public : void toFile (std::string dirname="."); + private : XML toXML (void); + private : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Simulator & x); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/XMLUtils.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/XMLUtils.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/XMLUtils.h (revision 88) @@ -0,0 +1,41 @@ +#ifndef morpheo_behavioural_configuration_XMLUtils_h +#define morpheo_behavioural_configuration_XMLUtils_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/FileXMLLight.h" +#include "Behavioural/include/XMLLightFunctors.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/Debug.h" +#include +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + typedef XMLUtils::IXMLLightASCII XML_t; + typedef std::basic_string attribute_t; + typedef std::map, std::basic_string > attributes_t; + + attribute_t getAttribute (XML_t * xml, + attributes_t & attributes, + const attribute_t & name); + + void testAttributesEmpty (XML_t * xml, + attributes_t attributes); + + void testNoAttribute (XML_t * xml); + void testNodeName (XML_t * xml, std::string name); + void testSingleton (XML_t * xml, bool must_be_singleton); + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 88) @@ -0,0 +1,104 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" +#include "Behavioural/include/Simulation.h" +#include "Common/include/Environment.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::Configuration" + Configuration::Configuration (std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + behavioural::custom::custom_information_t (*get_custom_information) (void)) + { + log_begin(Configuration,FUNCTION); + + _simulator = new Simulator (filename_simulator); + _generator = new Generator (filename_generator); + _instance = new Instance (filename_instance , + _generator, + get_custom_information); + + //-------------------------------------------------- + // Name + //-------------------------------------------------- + _name = _instance->getName(); + + //-------------------------------------------------- + // Parameters + //-------------------------------------------------- + _param = _instance->_param; + + //-------------------------------------------------- + // Usage + //-------------------------------------------------- + _usage = USE_NONE; + + if (fromString(_simulator->getParam("use_systemc"))) + _usage = usage_set(_usage, USE_SYSTEMC); + if (fromString(_simulator->getParam("use_vhdl"))) + _usage = usage_set(_usage, USE_VHDL); + if (fromString(_simulator->getParam("use_vhdl_testbench"))) + _usage = usage_set(_usage, USE_VHDL_TESTBENCH); + if (fromString(_simulator->getParam("use_vhdl_testbench_assert"))) + _usage = usage_set(_usage, USE_VHDL_TESTBENCH_ASSERT); + if (fromString(_simulator->getParam("use_position"))) + _usage = usage_set(_usage, USE_POSITION); + if (fromString(_simulator->getParam("use_statistics"))) + _usage = usage_set(_usage, USE_STATISTICS); + if (fromString(_simulator->getParam("use_information"))) + _usage = usage_set(_usage, USE_INFORMATION); + if (fromString(_simulator->getParam("use_header"))) + _usage = usage_set(_usage, USE_HEADER); + + usage_environment (_usage); + + //-------------------------------------------------- + // Parameters_Statistics + //-------------------------------------------------- + _param_statistics = new Parameters_Statistics (fromString(_simulator->getParam("nb_cycle_before_begin")), + fromString(_simulator->getParam("period_save"))); + + //-------------------------------------------------- + // Simulation condition stop + //-------------------------------------------------- + simulation_init (fromString(_simulator->getParam("simulation_nb_cycle")), + fromString(_simulator->getParam("simulation_nb_instruction"))); + + //-------------------------------------------------- + // Directory + //-------------------------------------------------- + directory_init (_simulator->getParam("directory_statistics"), + _simulator->getParam("directory_vhdl" ), + _simulator->getParam("directory_position" ), + _simulator->getParam("directory_log" )); + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Configuration::~Configuration" + Configuration::~Configuration () + { + log_begin(Configuration,FUNCTION); + + delete _simulator; + delete _generator; + delete _instance; + delete _param_statistics; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getName.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getName.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getName.cpp (revision 88) @@ -0,0 +1,23 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::toFile" + std::string Configuration::getName (void) + { + return _name; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParam.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParam.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParam.cpp (revision 88) @@ -0,0 +1,23 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::toFile" + Parameters * Configuration::getParam (void) + { + return _param; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParamStatistics.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParamStatistics.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getParamStatistics.cpp (revision 88) @@ -0,0 +1,23 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::toFile" + morpheo::behavioural::Parameters_Statistics * Configuration::getParamStatistics (void) + { + return _param_statistics; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getUsage.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getUsage.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_getUsage.cpp (revision 88) @@ -0,0 +1,23 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::toFile" + Tusage_t Configuration::getUsage (void) + { + return _usage; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_print.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Configuration & x) + { + log_begin(Configuration,FUNCTION); + output << *(x._simulator); + output << *(x._generator); + output << *(x._instance); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_toFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_toFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_toFile.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::toFile" + void Configuration::toFile (std::string dirname) + { + log_begin(Configuration,FUNCTION); + + _simulator->toFile(dirname); + _generator->toFile(dirname); + _instance ->toFile(dirname); + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator.cpp (revision 88) @@ -0,0 +1,59 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::Generator" + Generator::Generator (std::string filename) + { + log_begin(Configuration,FUNCTION); + + _filename = filename; + _array_param = new std::map; + _array_link = new std::map; + + fromFile (filename); + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Generator::~Generator" + Generator::~Generator () + { + log_begin(Configuration,FUNCTION); + + for (std::map::iterator it = _array_param->begin(); + it != _array_param->end(); + ++it) + { + delete it->second; + } + + delete _array_param; + + for (std::map::iterator it = _array_link->begin(); + it != _array_link->end(); + ++it) + { + delete it->second; + } + + delete _array_link; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_fromFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_fromFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_fromFile.cpp (revision 88) @@ -0,0 +1,133 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" +#include "Common/include/FromString.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + using namespace XMLUtils; + +#undef FUNCTION +#define FUNCTION "Generator::fromFile" + void Generator::fromFile (std::string filename) + { + log_begin(Configuration,FUNCTION); + + msg_printf(INFORMATION,_("Read file \"%s\"."),filename.c_str()); + + std::ifstream file (filename.c_str()); + + // Test the file open + if (!file) + throw ERRORMORPHEO(FUNCTION,toString(_("Error opening \"%s\" file.\n"),filename.c_str())); + + XML_t * _xml = new FileXMLLight(file); + + // Test root node : Root name, must not a singleton, have none attribute + testNodeName (_xml,"parameters"); + testSingleton (_xml,false); + testNoAttribute(_xml); + + XMLLightVector vect = _xml->getNodes(); + +// std::cout << vect << std::endl; + + for (uint32_t i=0; igetName(); + + //-------------------------------------- + // Node : Parameter + //-------------------------------------- + if (node_name == "parameter") + { + testSingleton (xml,true); + + // Take attributes of this tag + + attributes_t attributes = xml->getAttributes(); + +// std::cout << "Node [" << name << "]" << std::endl; +// std::cout << " * nb attributes : " << xml->getAttributes().size() << std::endl; + + attribute_t value_name = getAttribute(xml,attributes,"name" ); + attribute_t value_default = getAttribute(xml,attributes,"default"); + attribute_t value_level = (xml->containsAttribute("level" ))?getAttribute(xml,attributes,"level" ):"3"; + attribute_t value_description = (xml->containsAttribute("description"))?getAttribute(xml,attributes,"description"):""; + + bool is_binary = not (xml->containsAttribute("min" ) or + xml->containsAttribute("max" ) or + xml->containsAttribute("step")); + + attribute_t value_min = (not is_binary)?getAttribute(xml,attributes,"min" ):"0"; + attribute_t value_max = (not is_binary)?getAttribute(xml,attributes,"max" ):"1"; + attribute_t value_step = (not is_binary)?getAttribute(xml,attributes,"step"):"+ 1"; + + testAttributesEmpty(xml,attributes); + + // Insert in array + Parameter_definition * param = new Parameter_definition(value_name , + value_min , + value_max , + value_step , + value_default , + value_level , + value_description); + + insert(param); + } + else + //-------------------------------------- + // Node : Link + //-------------------------------------- + if (node_name == "link") + { + testSingleton (xml,true); + + // Take attributes of this tag + + attributes_t attributes = xml->getAttributes(); + +// std::cout << "Node [" << name << "]" << std::endl; +// std::cout << " * nb attributes : " << xml->getAttributes().size() << std::endl; + + attribute_t value_name = getAttribute(xml,attributes,"name"); + attribute_t value_src = getAttribute(xml,attributes,"src" ); + attribute_t value_dest = (xml->containsAttribute("dest" ))?getAttribute(xml,attributes,"dest" ):""; + attribute_t value_description = (xml->containsAttribute("description"))?getAttribute(xml,attributes,"description"):""; + + testAttributesEmpty(xml,attributes); + + // Insert in array + Link_definition * param = new Link_definition(value_name , + value_src , + value_dest , + value_description); + + insert(param); + } + //-------------------------------------- + // Node : Unknow + //-------------------------------------- + else + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"%s\" is unknow.\n"),node_name.c_str())); + } + + delete _xml; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getLink.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getLink.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getLink.cpp (revision 88) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::getLink" + Link_definition * Generator::getLink (std::string name) + { + log_begin(Configuration,FUNCTION); + + std::map::iterator it_link = _array_link->find(name); + + if (it_link == _array_link->end()) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Link \"%s\" is unknow.\n"),name.c_str()))); + } + + log_end(Configuration,FUNCTION); + + return it_link->second; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getParam.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getParam.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_getParam.cpp (revision 88) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::getParam" + Parameter_definition * Generator::getParam (std::string name) + { + log_begin(Configuration,FUNCTION); + + std::map::iterator it_param = _array_param->find(name); + + if (it_param == _array_param->end()) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Parameter \"%s\" is unknow.\n"),name.c_str()))); + } + + log_end(Configuration,FUNCTION); + + return it_param->second; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_insert.cpp (revision 88) @@ -0,0 +1,36 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::insert" + void Generator::insert (Parameter_definition * param) + { + log_begin(Configuration,FUNCTION); + + (*_array_param)[param->_name] = param; + + log_end(Configuration,FUNCTION); + }; + + void Generator::insert (Link_definition * link) + { + log_begin(Configuration,FUNCTION); + + (*_array_link)[link->_name] = link; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::print" + std::string Generator::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Generator::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Generator & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_test.cpp (revision 88) @@ -0,0 +1,68 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::test" + void Generator::test (std::string param, std::string x) + { + log_begin(Configuration,FUNCTION); + + std::map::iterator it_param = _array_param->find(param); + + if (it_param == _array_param->end()) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Parameter \"%s\" is unknow.\n"),param.c_str()))); + } + else + { + it_param->second->test(x); + } + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Generator::test" + void Generator::test (std::string link, + std::string father_name, + bool father_is_src, + bool father_is_dest) + { + log_begin(Configuration,FUNCTION); + + // Link ? + std::map::iterator it_link = _array_link->find(link); + + if (it_link == _array_link->end()) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Link \"%s\" is unknow.\n"),link.c_str()))); + } + + if ((father_is_src ) and + (father_name != it_link->second->_src )) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Link \"%s\", must be instance as source in component \"%s\", but find in component \"%s\".\n"),link.c_str(),it_link->second->_src.c_str(),father_name.c_str()))); + } + + if ((father_is_dest ) and + (father_name != it_link->second->_dest )) + { + throw (ERRORMORPHEO(FUNCTION,toString(_("Link \"%s\", must be instance as destination in component \"%s\", but find in component \"%s\".\n"),link.c_str(),it_link->second->_dest.c_str(),father_name.c_str()))); + } + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toFile.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::toFile" + void Generator::toFile (std::string dirname) + { + log_begin(Configuration,FUNCTION); + + (toXML()).generate_file(dirname); + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Generator_toXML.cpp (revision 88) @@ -0,0 +1,41 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Generator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Generator::toXML" + XML Generator::toXML (void) + { + XML xml (basename(_filename.c_str())); + xml.filename_extension(""); + + xml.balise_open("parameters"); + for (std::map::iterator it = _array_param->begin(); + it != _array_param->end(); + ++it) + { + xml.insert_XML(it->second->toXML(),1); + } + for (std::map::iterator it = _array_link->begin(); + it != _array_link->end(); + ++it) + { + xml.insert_XML(it->second->toXML(),1); + } + xml.balise_close(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 88) @@ -0,0 +1,179 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::Instance" + Instance::Instance (std::string filename, + Generator * generator, + behavioural::custom::custom_information_t (*get_custom_information) (void)) + { + log_begin(Configuration,FUNCTION); + + _name = ""; + _filename = filename; + + _list_parameters = new list_parameters_t; + _list_links = new list_links_t; + _list_components = new list_components_t; + + _generator = generator; + _param = new Parameters; + _param->_get_custom_information = get_custom_information; + + fromFile (filename); + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Instance::~Instance" + Instance::~Instance () + { + log_begin(Configuration,FUNCTION); + + for (list_parameters_t::iterator it = _list_parameters->begin(); + it != _list_parameters->end(); + ++it) + delete it->second; + delete _list_parameters; + + for (list_links_t::iterator it1 = _list_links->begin(); + it1 != _list_links->end(); + ++it1) + for (list_link_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + delete it2->second; + delete _list_links; + + for (list_components_t::iterator it1 = _list_components->begin(); + it1 != _list_components->end(); + ++it1) + for (list_instances_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + delete it2->second; + delete _list_components; + + if (_param != NULL) // TEST A ENLEVER + { + DELETE2(_param->_link_dcache_port_with_load_store_unit ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE1(_param->_link_icache_port_with_thread ,_param->_nb_thread); + DELETE2(_param->_link_thread_and_functionnal_unit ,_param->_nb_thread,_param->_nb_functionnal_unit); + DELETE1(_param->_link_load_store_unit_with_thread ,_param->_nb_thread); + DELETE2(_param->_link_write_bloc_and_functionnal_unit ,_param->_nb_write_bloc,_param->_nb_functionnal_unit); + DELETE2(_param->_link_write_bloc_and_load_store_unit ,_param->_nb_write_bloc,_param->_nb_load_store_unit); + DELETE2(_param->_link_read_bloc_and_functionnal_unit ,_param->_nb_read_bloc,_param->_nb_functionnal_unit); + DELETE2(_param->_link_read_bloc_and_load_store_unit ,_param->_nb_read_bloc,_param->_nb_load_store_unit); + DELETE3(_param->_table_dispatch ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_nb_read_bloc); + DELETE1(_param->_link_rename_bloc_with_front_end ,_param->_nb_front_end); + DELETE1(_param->_link_decod_bloc_with_thread ,_param->_nb_thread); + DELETE1(_param->_link_execute_unit_with_load_store_unit ,_param->_nb_load_store_unit); + DELETE1(_param->_link_execute_unit_with_functionnal_unit,_param->_nb_functionnal_unit); + DELETE1(_param->_link_write_unit_with_write_bloc ,_param->_nb_write_bloc); + DELETE1(_param->_link_read_unit_with_read_bloc ,_param->_nb_read_bloc); + DELETE1(_param->_link_rename_unit_with_rename_bloc ,_param->_nb_rename_bloc); + DELETE1(_param->_link_decod_unit_with_decod_bloc ,_param->_nb_decod_bloc); + DELETE1(_param->_link_context_with_thread ,_param->_nb_thread); + DELETE1(_param->_read_unit_to_execution_unit_priority ,_param->_nb_execute_loop); + DELETE1(_param->_execution_unit_to_write_unit_priority ,_param->_nb_execute_loop); + DELETE1(_param->_nb_spr_port_write_by_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_spr_port_read_by_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_spr_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_gpr_port_write_by_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_gpr_port_read_by_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_gpr_bank ,_param->_nb_execute_loop); + DELETE1(_param->_nb_write_unit ,_param->_nb_execute_loop); + DELETE1(_param->_nb_execute_unit ,_param->_nb_execute_loop); + DELETE1(_param->_nb_read_unit ,_param->_nb_execute_loop); + DELETE1(_param->_reexecute_load_balancing ,_param->_nb_ooo_engine); + DELETE1(_param->_reexecute_priority ,_param->_nb_ooo_engine); + DELETE1(_param->_size_reexecute_queue ,_param->_nb_ooo_engine); + DELETE1(_param->_issue_load_balancing ,_param->_nb_ooo_engine); + DELETE1(_param->_issue_priority ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_issue_queue_bank ,_param->_nb_ooo_engine); + DELETE1(_param->_size_issue_queue ,_param->_nb_ooo_engine); + DELETE1(_param->_commit_load_balancing ,_param->_nb_ooo_engine); + DELETE1(_param->_commit_priority ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_re_order_buffer_bank ,_param->_nb_ooo_engine); + DELETE1(_param->_size_re_order_buffer ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_execute_loop_select ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_rename_unit_select ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_inst_branch_complete ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_inst_commit ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_inst_reexecute ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_inst_issue ,_param->_nb_ooo_engine); + DELETE1(_param->_nb_rename_unit ,_param->_nb_ooo_engine); + DELETE2(_param->_dir_pht_size_address_share ,_param->_nb_front_end,3); + DELETE2(_param->_dir_pht_nb_counter ,_param->_nb_front_end,3); + DELETE2(_param->_dir_pht_size_counter ,_param->_nb_front_end,3); + DELETE2(_param->_dir_have_pht ,_param->_nb_front_end,3); + DELETE2(_param->_dir_bht_nb_shifter ,_param->_nb_front_end,3); + DELETE2(_param->_dir_bht_size_shifter ,_param->_nb_front_end,3); + DELETE2(_param->_dir_have_bht ,_param->_nb_front_end,3); + DELETE1(_param->_dir_predictor_scheme ,_param->_nb_front_end); + DELETE1(_param->_btb_victim_scheme ,_param->_nb_front_end); + DELETE1(_param->_btb_size_counter ,_param->_nb_front_end); + DELETE1(_param->_btb_associativity ,_param->_nb_front_end); + DELETE1(_param->_btb_size_queue ,_param->_nb_front_end); + DELETE1(_param->_nb_inst_branch_update ,_param->_nb_front_end); + DELETE1(_param->_nb_inst_branch_decod ,_param->_nb_front_end); + DELETE1(_param->_nb_inst_branch_predict ,_param->_nb_front_end); + DELETE1(_param->_nb_decod_unit ,_param->_nb_front_end); + DELETE1(_param->_nb_context ,_param->_nb_front_end); + DELETE3(_param->_timing ,_param->_nb_functionnal_unit,MAX_TYPE,MAX_OPERATION); + DELETE1(_param->_nb_inst_functionnal_unit ,_param->_nb_functionnal_unit); + DELETE1(_param->_speculative_load ,_param->_nb_load_store_unit); + DELETE1(_param->_nb_inst_memory ,_param->_nb_load_store_unit); + DELETE1(_param->_nb_cache_port ,_param->_nb_load_store_unit); + DELETE1(_param->_nb_bypass_memory ,_param->_nb_load_store_unit); + DELETE1(_param->_nb_port_check ,_param->_nb_load_store_unit); + DELETE1(_param->_size_speculative_access_queue ,_param->_nb_load_store_unit); + DELETE1(_param->_size_load_queue ,_param->_nb_load_store_unit); + DELETE1(_param->_size_store_queue ,_param->_nb_load_store_unit); + DELETE1(_param->_nb_bypass_write ,_param->_nb_write_bloc); + DELETE1(_param->_size_execute_queue ,_param->_nb_write_bloc); + DELETE1(_param->_size_write_queue ,_param->_nb_write_bloc); + DELETE1(_param->_nb_inst_retire_reservation_station ,_param->_nb_read_bloc); + DELETE1(_param->_size_reservation_station ,_param->_nb_read_bloc); + DELETE1(_param->_size_read_queue ,_param->_nb_read_bloc); + DELETE1(_param->_size_read_counter ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_rename_unit_bank ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_reg_free ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_special_register ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_general_register ,_param->_nb_rename_bloc); + DELETE1(_param->_rename_select_nb_front_end_select ,_param->_nb_rename_bloc); + DELETE1(_param->_rename_select_load_balancing ,_param->_nb_rename_bloc); + DELETE1(_param->_rename_select_priority ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_inst_retire ,_param->_nb_rename_bloc); + DELETE1(_param->_nb_inst_insert ,_param->_nb_rename_bloc); + DELETE1(_param->_context_select_load_balancing ,_param->_nb_decod_bloc); + DELETE1(_param->_context_select_priority ,_param->_nb_decod_bloc); + DELETE1(_param->_nb_context_select ,_param->_nb_decod_bloc); + DELETE1(_param->_nb_inst_decod ,_param->_nb_decod_bloc); + DELETE1(_param->_size_decod_queue ,_param->_nb_decod_bloc); + DELETE1(_param->_upt_size_queue ,_param->_nb_thread); + DELETE1(_param->_ras_size_queue ,_param->_nb_thread); + DELETE2(_param->_implement_group ,_param->_nb_thread,NB_GROUP); + DELETE1(_param->_nb_inst_fetch ,_param->_nb_thread); + DELETE1(_param->_size_ifetch_queue ,_param->_nb_thread); + + delete _param; + } + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromFile.cpp (revision 88) @@ -0,0 +1,58 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" +#include "Common/include/FromString.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + using namespace XMLUtils; + +#undef FUNCTION +#define FUNCTION "Instance::fromFile" + void Instance::fromFile (std::string filename) + { + log_begin(Configuration,FUNCTION); + + msg_printf(INFORMATION,_("Read file \"%s\"."),filename.c_str()); + + std::ifstream file (filename.c_str()); + + // Test the file open + if (!file) + throw ERRORMORPHEO(FUNCTION,toString(_("Error opening \"%s\" file.\n"),filename.c_str())); + + // 1) FILL _array + XML_t * _xml = new FileXMLLight(file); + + // Test root node : Root name, must not a singleton, have none attribute + testNodeName (_xml,"core"); + testSingleton (_xml,false); + + attributes_t attributes = _xml->getAttributes(); + _name = getAttribute(_xml,attributes,"name" ); + + fromXMLLight (_xml, + "", + _list_parameters, + _list_links, + _list_components); + + delete _xml; + + // 2) TEST/CREATE Parameters + fromInternalStructure(); + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 88) @@ -0,0 +1,547 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/FromString.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::fromInternalStructure" + void Instance::fromInternalStructure (void) + { + //----------------------------------------------------- + // Common + //----------------------------------------------------- + log_printf(INFO,Configuration,FUNCTION,_("COMMON")); + + _param->_size_general_data = fromString(getParam("size_data" , "")); + _param->_size_special_data = SIZE_SPECIAL_DATA; // Constant + + _param->_nb_thread = fromString(getParam("nb_thread" , "")); + _param->_nb_decod_bloc = fromString(getParam("nb_decod_bloc" , "")); + _param->_nb_rename_bloc = fromString(getParam("nb_rename_bloc" , "")); + _param->_nb_read_bloc = fromString(getParam("nb_read_bloc" , "")); + _param->_nb_write_bloc = fromString(getParam("nb_write_bloc" , "")); + _param->_nb_load_store_unit = fromString(getParam("nb_load_store_unit" , "")); + _param->_nb_functionnal_unit = fromString(getParam("nb_functionnal_unit", "")); + _param->_nb_front_end = fromString(getParam("nb_front_end" , "")); + _param->_nb_ooo_engine = fromString(getParam("nb_ooo_engine" , "")); + _param->_nb_execute_loop = fromString(getParam("nb_execute_loop" , "")); + + //----------------------------------------------------- + // Thread + //----------------------------------------------------- + + ALLOC1(_param->_size_ifetch_queue,uint32_t,_param->_nb_thread); + ALLOC1(_param->_nb_inst_fetch ,uint32_t,_param->_nb_thread); + ALLOC2(_param->_implement_group ,bool ,_param->_nb_thread,NB_GROUP); + ALLOC1(_param->_ras_size_queue ,uint32_t,_param->_nb_thread); + ALLOC1(_param->_upt_size_queue ,uint32_t,_param->_nb_thread); + + for (uint32_t i=0; i<_param->_nb_thread; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("THREAD [%d]"),i); + + _param->_size_ifetch_queue [i] = fromString(getParam("size_ifetch_queue", "thread",toString(i).c_str(),"")); + _param->_nb_inst_fetch [i] = fromString(getParam("nb_inst_fetch" , "thread",toString(i).c_str(),"")); + _param->_ras_size_queue [i] = fromString(getParam("ras_size_queue" , "thread",toString(i).c_str(),"")); + _param->_upt_size_queue [i] = fromString(getParam("upt_size_queue" , "thread",toString(i).c_str(),"")); + + // just read !!! + try + { + getParam("nb_group","thread",toString(i).c_str(), ""); + } + catch (morpheo::ErrorMorpheo & error) + { + } + + for (uint32_t j=0; j_implement_group [i][j] = fromString(getParam("implement_group", + "thread",toString(i).c_str(), + "group" ,toString(j).c_str(),"")); + } + } + + //----------------------------------------------------- + // Decod_bloc + //----------------------------------------------------- + + ALLOC1(_param->_size_decod_queue ,uint32_t ,_param->_nb_decod_bloc); + ALLOC1(_param->_nb_inst_decod ,uint32_t ,_param->_nb_decod_bloc); + ALLOC1(_param->_nb_context_select ,uint32_t ,_param->_nb_decod_bloc); + ALLOC1(_param->_context_select_priority ,Tpriority_t ,_param->_nb_decod_bloc); + ALLOC1(_param->_context_select_load_balancing,Tload_balancing_t,_param->_nb_decod_bloc); + + for (uint32_t i=0; i<_param->_nb_decod_bloc; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("DECOD_BLOC [%d]"),i); + + _param->_size_decod_queue [i] = fromString (getParam("size_decod_queue" , "decod_bloc",toString(i).c_str(),"")); + _param->_nb_inst_decod [i] = fromString (getParam("nb_inst_decod" , "decod_bloc",toString(i).c_str(),"")); + _param->_nb_context_select [i] = fromString (getParam("nb_context_select" , "decod_bloc",toString(i).c_str(),"")); + _param->_context_select_priority [i] = fromString (getParam("context_select_priority" , "decod_bloc",toString(i).c_str(),"")); + _param->_context_select_load_balancing [i] = fromString (getParam("context_select_load_balancing", "decod_bloc",toString(i).c_str(),"")); + } + + //----------------------------------------------------- + // Rename_bloc + //----------------------------------------------------- + + ALLOC1(_param->_nb_inst_insert ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_nb_inst_retire ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_rename_select_priority ,Tpriority_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_rename_select_load_balancing ,Tload_balancing_t,_param->_nb_rename_bloc); + ALLOC1(_param->_rename_select_nb_front_end_select,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_nb_general_register ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_nb_special_register ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_nb_reg_free ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_nb_rename_unit_bank ,uint32_t ,_param->_nb_rename_bloc); + ALLOC1(_param->_size_read_counter ,uint32_t ,_param->_nb_rename_bloc); + + for (uint32_t i=0; i<_param->_nb_rename_bloc; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("RENAME_BLOC [%d]"),i); + + _param->_nb_inst_insert [i] = fromString (getParam("nb_inst_insert" , "rename_bloc",toString(i).c_str(),"")); + _param->_nb_inst_retire [i] = fromString (getParam("nb_inst_retire" , "rename_bloc",toString(i).c_str(),"")); + _param->_rename_select_priority [i] = fromString (getParam("rename_select_priority" , "rename_bloc",toString(i).c_str(),"")); + _param->_rename_select_load_balancing [i] = fromString (getParam("rename_select_load_balancing" , "rename_bloc",toString(i).c_str(),"")); + _param->_rename_select_nb_front_end_select [i] = fromString (getParam("rename_select_nb_front_end_select", "rename_bloc",toString(i).c_str(),"")); + _param->_nb_general_register [i] = fromString (getParam("nb_general_register" , "rename_bloc",toString(i).c_str(),"")); + _param->_nb_special_register [i] = fromString (getParam("nb_special_register" , "rename_bloc",toString(i).c_str(),"")); + _param->_nb_reg_free [i] = fromString (getParam("nb_reg_free" , "rename_bloc",toString(i).c_str(),"")); + _param->_nb_rename_unit_bank [i] = fromString (getParam("nb_rename_unit_bank" , "rename_bloc",toString(i).c_str(),"")); + _param->_size_read_counter [i] = fromString (getParam("size_read_counter" , "rename_bloc",toString(i).c_str(),"")); + } + + //----------------------------------------------------- + // Read_bloc + //----------------------------------------------------- + ALLOC1(_param->_size_read_queue ,uint32_t,_param->_nb_read_bloc); + ALLOC1(_param->_size_reservation_station ,uint32_t,_param->_nb_read_bloc); + ALLOC1(_param->_nb_inst_retire_reservation_station,uint32_t,_param->_nb_read_bloc); + + for (uint32_t i=0; i<_param->_nb_read_bloc; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("READ_BLOC [%d]"),i); + + _param->_size_read_queue [i] = fromString (getParam("size_read_queue" ,"read_bloc",toString(i).c_str(),"")); + _param->_size_reservation_station [i] = fromString (getParam("size_reservation_station" ,"read_bloc",toString(i).c_str(),"")); + _param->_nb_inst_retire_reservation_station [i] = fromString (getParam("nb_inst_retire_reservation_station","read_bloc",toString(i).c_str(),"")); + } + + //----------------------------------------------------- + // Write_bloc + //----------------------------------------------------- + ALLOC1(_param->_size_write_queue ,uint32_t,_param->_nb_write_bloc); + ALLOC1(_param->_size_execute_queue,uint32_t,_param->_nb_write_bloc); + ALLOC1(_param->_nb_bypass_write ,uint32_t,_param->_nb_write_bloc); + + for (uint32_t i=0; i<_param->_nb_write_bloc; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("WRITE_BLOC [%d]"),i); + + _param->_size_write_queue [i] = fromString (getParam("size_write_queue" ,"write_bloc",toString(i).c_str(),"")); + _param->_size_execute_queue [i] = fromString (getParam("size_execute_queue","write_bloc",toString(i).c_str(),"")); + _param->_nb_bypass_write [i] = fromString (getParam("nb_bypass_write" ,"write_bloc",toString(i).c_str(),"")); + } + + //----------------------------------------------------- + // load_store_unit + //----------------------------------------------------- + ALLOC1(_param->_size_store_queue ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_size_load_queue ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_size_speculative_access_queue,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_nb_port_check ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_nb_bypass_memory ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_nb_cache_port ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_nb_inst_memory ,uint32_t,_param->_nb_load_store_unit); + ALLOC1(_param->_speculative_load ,core::multi_execute_loop::execute_loop::Tspeculative_load_t,_param->_nb_load_store_unit); + + for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("LOAD_STORE_UNIT [%d]"),i); + + _param->_size_store_queue [i] = fromString (getParam("size_store_queue" ,"load_store_unit",toString(i).c_str(),"")); + _param->_size_load_queue [i] = fromString (getParam("size_load_queue" ,"load_store_unit",toString(i).c_str(),"")); + _param->_size_speculative_access_queue [i] = fromString (getParam("size_speculative_access_queue","load_store_unit",toString(i).c_str(),"")); + _param->_nb_port_check [i] = fromString (getParam("nb_port_check" ,"load_store_unit",toString(i).c_str(),"")); + _param->_nb_bypass_memory [i] = fromString (getParam("nb_bypass_memory" ,"load_store_unit",toString(i).c_str(),"")); + _param->_nb_cache_port [i] = fromString (getParam("nb_cache_port" ,"load_store_unit",toString(i).c_str(),"")); + _param->_nb_inst_memory [i] = fromString (getParam("nb_inst_memory" ,"load_store_unit",toString(i).c_str(),"")); + + _param->_speculative_load [i] = fromString (getParam("speculative_load","load_store_unit",toString(i).c_str(),"")); + } + + //----------------------------------------------------- + // functionnal_unit + //----------------------------------------------------- + ALLOC1(_param->_nb_inst_functionnal_unit,uint32_t,_param->_nb_functionnal_unit); + ALLOC3(_param->_timing,core::multi_execute_loop::execute_loop::execute_timing_t,_param->_nb_functionnal_unit,MAX_TYPE,MAX_OPERATION); + + for (uint32_t i=0; i<_param->_nb_functionnal_unit; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("FUNCTIONNAL_UNIT [%d]"),i); + + _param->_nb_inst_functionnal_unit [i] = fromString (getParam("nb_inst_functionnal_unit","functionnal_unit",toString(i).c_str(),"")); + + // just read !!! + try + { + getParam("nb_type","functionnal_unit",toString(i).c_str(), ""); + } + catch (morpheo::ErrorMorpheo & error) + { + } + + for (uint32_t j=0; j_timing [i][j][k]._latence = fromString (getParam("latence", + "functionnal_unit",toString(i).c_str(), + "type" ,toString(j).c_str(), + "operation" ,toString(k).c_str(), + "")); + _param->_timing [i][j][k]._delay = fromString (getParam("delay", + "functionnal_unit",toString(i).c_str(), + "type" ,toString(j).c_str(), + "operation" ,toString(k).c_str(), + "")); + } + else + { + _param->_timing [i][j][k]._latence = 0; + _param->_timing [i][j][k]._delay = 0; + } + } + } + + //----------------------------------------------------- + // icache_port + //----------------------------------------------------- + + log_printf(INFO,Configuration,FUNCTION,_("ICACHE_PORT")); + + _param->_nb_icache_port = fromString(getParam("nb_icache_port" , "")); + _param->_icache_port_priority = fromString(getParam("icache_port_priority" , "")); + _param->_icache_port_load_balancing = fromString(getParam("icache_port_load_balancing", "")); + + //----------------------------------------------------- + // dcache_port + //----------------------------------------------------- + log_printf(INFO,Configuration,FUNCTION,_("DCACHE_PORT")); + + _param->_nb_dcache_port = fromString(getParam("nb_dcache_port" , "")); + _param->_dcache_port_priority = fromString(getParam("dcache_port_priority" , "")); + _param->_dcache_port_load_balancing = fromString(getParam("dcache_port_load_balancing", "")); + + + //----------------------------------------------------- + // front_end + //----------------------------------------------------- + ALLOC1(_param->_nb_context ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_nb_decod_unit ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_nb_inst_branch_predict ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_nb_inst_branch_decod ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_nb_inst_branch_update ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_btb_size_queue ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_btb_associativity ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_btb_size_counter ,uint32_t ,_param->_nb_front_end); + ALLOC1(_param->_btb_victim_scheme ,Tvictim_t ,_param->_nb_front_end); + ALLOC1(_param->_dir_predictor_scheme ,Tpredictor_t,_param->_nb_front_end); + ALLOC2(_param->_dir_have_bht ,bool ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_bht_size_shifter ,uint32_t ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_bht_nb_shifter ,uint32_t ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_have_pht ,bool ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_pht_size_counter ,uint32_t ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_pht_nb_counter ,uint32_t ,_param->_nb_front_end,3); + ALLOC2(_param->_dir_pht_size_address_share ,uint32_t ,_param->_nb_front_end,3); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("FRONT_END [%d]"),i); + + _param->_nb_context [i] = fromString(getParam("nb_context" ,"front_end",toString(i).c_str(), "")); + _param->_nb_decod_unit [i] = fromString(getParam("nb_decod_unit" ,"front_end",toString(i).c_str(), "")); + _param->_nb_inst_branch_predict [i] = fromString(getParam("nb_inst_branch_predict" ,"front_end",toString(i).c_str(), "")); + _param->_nb_inst_branch_decod [i] = fromString(getParam("nb_inst_branch_decod" ,"front_end",toString(i).c_str(), "")); + _param->_nb_inst_branch_update [i] = fromString(getParam("nb_inst_branch_update" ,"front_end",toString(i).c_str(), "")); + _param->_btb_size_queue [i] = fromString(getParam("btb_size_queue" ,"front_end",toString(i).c_str(), "")); + _param->_btb_associativity [i] = fromString(getParam("btb_associativity" ,"front_end",toString(i).c_str(), "")); + _param->_btb_size_counter [i] = fromString(getParam("btb_size_counter" ,"front_end",toString(i).c_str(), "")); + _param->_btb_victim_scheme [i] = fromString(getParam("btb_victim_scheme" ,"front_end",toString(i).c_str(), "")); + _param->_dir_predictor_scheme [i] = fromString(getParam("dir_predictor_scheme" ,"front_end",toString(i).c_str(), "")); + + // just read !!! + try + { + getParam("nb_predictor","front_end",toString(i).c_str(), ""); + } + catch (morpheo::ErrorMorpheo & error) + { + } + + for (uint32_t j=0; j<3; ++j) + { + log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j); + + _param->_dir_have_bht [i][j] = fromString(getParam("dir_have_bht" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_bht_size_shifter [i][j] = fromString(getParam("dir_bht_size_shifter" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_bht_nb_shifter [i][j] = fromString(getParam("dir_bht_nb_shifter" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_have_pht [i][j] = fromString(getParam("dir_have_pht" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_pht_size_counter [i][j] = fromString(getParam("dir_pht_size_counter" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_pht_nb_counter [i][j] = fromString(getParam("dir_pht_nb_counter" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + _param->_dir_pht_size_address_share [i][j] = fromString(getParam("dir_pht_size_address_share","front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); + } + } + + //----------------------------------------------------- + // ooo_engine + //----------------------------------------------------- + + ALLOC1(_param->_nb_rename_unit ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_inst_issue ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_inst_reexecute ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_inst_commit ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_inst_branch_complete ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_rename_unit_select ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_execute_loop_select ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_size_re_order_buffer ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_re_order_buffer_bank ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_commit_priority ,Tpriority_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_commit_load_balancing ,Tload_balancing_t,_param->_nb_ooo_engine); + ALLOC1(_param->_size_issue_queue ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_nb_issue_queue_bank ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_issue_priority ,Tpriority_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_issue_load_balancing ,Tload_balancing_t,_param->_nb_ooo_engine); + ALLOC1(_param->_size_reexecute_queue ,uint32_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_reexecute_priority ,Tpriority_t ,_param->_nb_ooo_engine); + ALLOC1(_param->_reexecute_load_balancing,Tload_balancing_t,_param->_nb_ooo_engine); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("OOO_ENGINE [%d]"),i); + + _param->_nb_rename_unit [i] = fromString(getParam("nb_rename_unit" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_inst_issue [i] = fromString(getParam("nb_inst_issue" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_inst_reexecute [i] = fromString(getParam("nb_inst_reexecute" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_inst_commit [i] = fromString(getParam("nb_inst_commit" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_inst_branch_complete [i] = fromString(getParam("nb_inst_branch_complete" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_rename_unit_select [i] = fromString(getParam("nb_rename_unit_select" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_execute_loop_select [i] = fromString(getParam("nb_execute_loop_select" ,"ooo_engine",toString(i).c_str(), "")); + _param->_size_re_order_buffer [i] = fromString(getParam("size_re_order_buffer" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_re_order_buffer_bank [i] = fromString(getParam("nb_re_order_buffer_bank" ,"ooo_engine",toString(i).c_str(), "")); + _param->_commit_priority [i] = fromString(getParam("commit_priority" ,"ooo_engine",toString(i).c_str(), "")); + _param->_commit_load_balancing [i] = fromString(getParam("commit_load_balancing" ,"ooo_engine",toString(i).c_str(), "")); + _param->_size_issue_queue [i] = fromString(getParam("size_issue_queue" ,"ooo_engine",toString(i).c_str(), "")); + _param->_nb_issue_queue_bank [i] = fromString(getParam("nb_issue_queue_bank" ,"ooo_engine",toString(i).c_str(), "")); + _param->_issue_priority [i] = fromString(getParam("issue_priority" ,"ooo_engine",toString(i).c_str(), "")); + _param->_issue_load_balancing [i] = fromString(getParam("issue_load_balancing" ,"ooo_engine",toString(i).c_str(), "")); + _param->_size_reexecute_queue [i] = fromString(getParam("size_reexecute_queue" ,"ooo_engine",toString(i).c_str(), "")); + _param->_reexecute_priority [i] = fromString(getParam("reexecute_priority" ,"ooo_engine",toString(i).c_str(), "")); + _param->_reexecute_load_balancing[i] = fromString(getParam("reexecute_load_balancing","ooo_engine",toString(i).c_str(), "")); + } + + //----------------------------------------------------- + // execute_loop + //----------------------------------------------------- + + ALLOC1(_param->_nb_read_unit ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_execute_unit ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_write_unit ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_gpr_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_gpr_port_read_by_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_gpr_port_write_by_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_spr_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_spr_port_read_by_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_nb_spr_port_write_by_bank ,uint32_t ,_param->_nb_execute_loop); + ALLOC1(_param->_execution_unit_to_write_unit_priority,Tpriority_t,_param->_nb_execute_loop); + ALLOC1(_param->_read_unit_to_execution_unit_priority ,Tpriority_t,_param->_nb_execute_loop); + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + { + log_printf(INFO,Configuration,FUNCTION,_("EXECUTE_LOOP [%d]"),i); + + _param->_nb_read_unit [i] = fromString(getParam("nb_read_unit" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_execute_unit [i] = fromString(getParam("nb_execute_unit" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_write_unit [i] = fromString(getParam("nb_write_unit" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_gpr_bank [i] = fromString(getParam("nb_gpr_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_gpr_port_read_by_bank [i] = fromString(getParam("nb_gpr_port_read_by_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_gpr_port_write_by_bank [i] = fromString(getParam("nb_gpr_port_write_by_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_spr_bank [i] = fromString(getParam("nb_spr_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_spr_port_read_by_bank [i] = fromString(getParam("nb_spr_port_read_by_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_nb_spr_port_write_by_bank [i] = fromString(getParam("nb_spr_port_write_by_bank" ,"execute_loop",toString(i).c_str(), "")); + _param->_execution_unit_to_write_unit_priority[i] = fromString(getParam("execution_unit_to_write_unit_priority","execute_loop",toString(i).c_str(), "")); + _param->_read_unit_to_execution_unit_priority [i] = fromString(getParam("read_unit_to_execution_unit_priority" ,"execute_loop",toString(i).c_str(), "")); + } + + //----------------------------------------------------- + // Link + //----------------------------------------------------- + + log_printf(INFO,Configuration,FUNCTION,_("LINK")); + + _param->_dispatch_priority = fromString(getParam("dispatch_priority" , "")); + _param->_dispatch_load_balancing = fromString(getParam("dispatch_load_balancing", "")); + + ALLOC1(_param->_link_context_with_thread ,pair_dual,_param->_nb_thread); + ALLOC1(_param->_link_decod_unit_with_decod_bloc ,pair_dual,_param->_nb_decod_bloc); + ALLOC1(_param->_link_rename_unit_with_rename_bloc ,pair_dual,_param->_nb_rename_bloc); + ALLOC1(_param->_link_read_unit_with_read_bloc ,pair_dual,_param->_nb_read_bloc); + ALLOC1(_param->_link_write_unit_with_write_bloc ,pair_dual,_param->_nb_write_bloc); + ALLOC1(_param->_link_execute_unit_with_functionnal_unit,pair_dual,_param->_nb_functionnal_unit); + ALLOC1(_param->_link_execute_unit_with_load_store_unit ,pair_dual,_param->_nb_load_store_unit); + ALLOC1(_param->_link_decod_bloc_with_thread ,uint32_t ,_param->_nb_thread); + ALLOC1(_param->_link_rename_bloc_with_front_end ,uint32_t ,_param->_nb_front_end); + ALLOC3(_param->_table_dispatch ,bool ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_nb_read_bloc); + ALLOC2(_param->_link_read_bloc_and_load_store_unit ,bool ,_param->_nb_read_bloc,_param->_nb_load_store_unit); + ALLOC2(_param->_link_read_bloc_and_functionnal_unit ,bool ,_param->_nb_read_bloc,_param->_nb_functionnal_unit); + ALLOC2(_param->_link_write_bloc_and_load_store_unit ,bool ,_param->_nb_write_bloc,_param->_nb_load_store_unit); + ALLOC2(_param->_link_write_bloc_and_functionnal_unit ,bool ,_param->_nb_write_bloc,_param->_nb_functionnal_unit); + ALLOC1(_param->_link_load_store_unit_with_thread ,uint32_t ,_param->_nb_thread); + ALLOC2(_param->_link_thread_and_functionnal_unit ,bool ,_param->_nb_thread,_param->_nb_functionnal_unit); + ALLOC1(_param->_link_icache_port_with_thread ,uint32_t ,_param->_nb_thread); + ALLOC2(_param->_link_dcache_port_with_load_store_unit ,uint32_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + + std::vector dest; + +#define getLink_n(x,nb_dest,src...) {dest = getLink(x, src); test(x,dest,nb_dest);} +#define getLink_2(x,src...) {getLink_n(x,2,src);} +#define getLink_1(x,src...) {getLink_n(x,1,src);} + + for (uint32_t i=0; i<_param->_nb_thread; ++i) + { + getLink_2("link_context_with_thread",toString(i).c_str(), ""); + _param->_link_context_with_thread [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + + getLink_1("link_decod_bloc_with_thread",toString(i).c_str(), ""); + _param->_link_decod_bloc_with_thread [i] = fromString(dest[0]); + + getLink_1("link_load_store_unit_with_thread",toString(i).c_str(), ""); + _param->_link_load_store_unit_with_thread [i] = fromString(dest[0]); + + getLink_1("link_icache_port_with_thread",toString(i).c_str(), ""); + _param->_link_icache_port_with_thread [i] = fromString(dest[0]); + + for (uint32_t j=0; j<_param->_nb_functionnal_unit; ++j) + { + getLink_1("link_thread_and_functionnal_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_thread_and_functionnal_unit [i][j] = fromString(dest[0]); + } + } + + for (uint32_t i=0; i<_param->_nb_decod_bloc; ++i) + { + getLink_2("link_decod_unit_with_decod_bloc",toString(i).c_str(), ""); + _param->_link_decod_unit_with_decod_bloc [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + } + + for (uint32_t i=0; i<_param->_nb_rename_bloc; ++i) + { + getLink_2("link_rename_unit_with_rename_bloc",toString(i).c_str(), ""); + _param->_link_rename_unit_with_rename_bloc [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + } + + for (uint32_t i=0; i<_param->_nb_read_bloc; ++i) + { + getLink_2("link_read_unit_with_read_bloc",toString(i).c_str(), ""); + _param->_link_read_unit_with_read_bloc [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + + for (uint32_t j=0; j<_param->_nb_functionnal_unit; ++j) + { + getLink_1("link_read_bloc_and_functionnal_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_read_bloc_and_functionnal_unit [i][j] = fromString(dest[0]); + } + + for (uint32_t j=0; j<_param->_nb_load_store_unit; ++j) + { + getLink_1("link_read_bloc_and_load_store_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_read_bloc_and_load_store_unit [i][j] = fromString(dest[0]); + } + } + + for (uint32_t i=0; i<_param->_nb_write_bloc; ++i) + { + getLink_2("link_write_unit_with_write_bloc",toString(i).c_str(), ""); + _param->_link_write_unit_with_write_bloc [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + + for (uint32_t j=0; j<_param->_nb_functionnal_unit; ++j) + { + getLink_1("link_write_bloc_and_functionnal_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_write_bloc_and_functionnal_unit [i][j] = fromString(dest[0]); + } + + for (uint32_t j=0; j<_param->_nb_load_store_unit; ++j) + { + getLink_1("link_write_bloc_and_load_store_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_write_bloc_and_load_store_unit [i][j] = fromString(dest[0]); + } + } + + for (uint32_t i=0; i<_param->_nb_functionnal_unit; ++i) + { + getLink_2("link_execute_unit_with_functionnal_unit",toString(i).c_str(), ""); + _param->_link_execute_unit_with_functionnal_unit [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + } + + for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i) + { + getLink_2("link_execute_unit_with_load_store_unit",toString(i).c_str(), ""); + _param->_link_execute_unit_with_load_store_unit [i] = pair_dual(fromString(dest[0]), + fromString(dest[1])); + + for (uint32_t j=0; j<_param->_nb_cache_port[i]; ++j) + { + getLink_1("link_dcache_port_with_load_store_unit",toString(i).c_str(),toString(j).c_str(), ""); + _param->_link_dcache_port_with_load_store_unit [i][j] = fromString(dest[0]); + } + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + { + getLink_1("link_rename_bloc_with_front_end",toString(i).c_str(), ""); + _param->_link_rename_bloc_with_front_end [i] = fromString(dest[0]); + } + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) + for (uint32_t k=0; k<_param->_nb_read_bloc; ++k) + { + getLink_1("table_dispatch",toString(i).c_str(),toString(j).c_str(),toString(k).c_str(),""); + _param->_table_dispatch [i][j][k] = fromString(dest[0]); + } + + test_use (); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromXMLLight.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromXMLLight.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromXMLLight.cpp (revision 88) @@ -0,0 +1,245 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" +#include "Common/include/FromString.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + using namespace XMLUtils; + +#undef FUNCTION +#define FUNCTION "Instance::fromXMLLight" + void Instance::fromXMLLight (XML_t * xml, + attribute_t id, + list_parameters_t * list_parameters, + list_links_t * list_links, + list_components_t * list_components) + { + + XMLLightVector vect = xml->getNodes(); + + for (uint32_t i=0; igetName(); + + //-------------------------------------------- + // Child : Parameter + //-------------------------------------------- + if (child_name == "parameter") + { + // Is a parameter + testSingleton (child,true); + + attributes_t attributes = child->getAttributes(); + attribute_t value_name = getAttribute(child,attributes,"name" ); + attribute_t value = getAttribute(child,attributes,"value"); + + testAttributesEmpty(child,attributes); + + // Test the parameter : + // * name is correct + // * value is correct + test (value_name, value); + + // Insert in array + Parameter_affectation * param = new Parameter_affectation(value_name, // type + value); + + // insert parameter + (*list_parameters)[param->_name] = param; + } + //-------------------------------------------- + // Child : Link + //-------------------------------------------- + else + if (child_name == "link") + { + // Is a parameter + testSingleton (child,true); + + attributes_t attributes = child->getAttributes(); + attribute_t value_name = getAttribute(child,attributes,"name"); + + // Test, must have src or dest (or twice) + bool have_src = child->containsAttribute("src" ); + bool have_dest = child->containsAttribute("dest"); + if (not have_src and + not have_dest) + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"link\" must have one or twince of this attributes : src, dest\n"))); + + attribute_t value_src = (have_src )?getAttribute(child,attributes,"src" ):id; + attribute_t value_dest = (have_dest)?getAttribute(child,attributes,"dest"):id; + + testAttributesEmpty(child,attributes); + + // Test the link : + // * name is correct + // * if not have_src , test if src is correct + // * if not have_dest, test if dest is correct + test (value_name, + xml->getName(), + not have_src, + not have_dest); + + // Create a new link + { + Link_affectation * link = new Link_affectation(value_name, // type + value_src, + value_dest); + + // Test if this id is previously used + if (((*list_links)[value_name]).find(value_src) != ((*list_links)[value_name]).end()) + throw ERRORMORPHEO(FUNCTION,toString(_("A Link \"%s\" with the source \"%s\" is previously declared.\n"),value_name.c_str(),value_src.c_str())); + + ((*list_links)[value_name])[value_src] = link; + } + } + //-------------------------------------------- + // Child : Timing + //-------------------------------------------- + else + if (child_name == "timing") + { + // Notation : + // + // + // is equivalent at : + // + // + // + // + // + // + + // Is a parameter + testSingleton (child,true); + + attributes_t attributes = child->getAttributes(); + attribute_t value_type = getAttribute(child,attributes,"type"); + bool have_operation = (child->containsAttribute("operation")); + attribute_t value_operation ; + attribute_t value_latence = (child->containsAttribute("latence" ))?getAttribute(child,attributes,"latence" ):"1"; + attribute_t value_delay = (child->containsAttribute("delay" ))?getAttribute(child,attributes,"delay" ):"1"; + + { + // Find component "type", if don't exist : create + if (((*list_components)["type"]).find(value_type) == ((*list_components)["type"]).end()) + { + // Create instance + Instance_component * param = new Instance_component("type", // type + value_type); + ((*list_components)["type"])[value_type] = param; + } + + list_components_t * list_type = ((*list_components)["type"])[value_type]->_list_components; + + // Find component "operation", if exist : error, else create + + bool stop = false; + Toperation_t operation = 0; + attribute_t value_operation = (have_operation)?getAttribute(child,attributes,"operation"):toString(operation); + + while (not stop) + { + if (((*list_type)["operation"]).find(value_operation) != ((*list_type)["operation"]).end()) + throw ERRORMORPHEO(FUNCTION,toString(_("A Component \"%s\" with id \"%s\" is previously declared.\n"),"operation",value_operation.c_str())); + else + { + // Create instance + Instance_component * param = new Instance_component("operation", // type + value_operation); + ((*list_type)["operation"])[value_operation] = param; + } + + list_parameters_t * list_operation = ((*list_type)["operation"])[value_operation]->_list_parameters; + + // insert parameter "latence" and "delay" + Parameter_affectation * param_latence = new Parameter_affectation("latence", + value_latence); + Parameter_affectation * param_delay = new Parameter_affectation("delay", + value_delay); + + (*list_operation)["latence"] = param_latence; + (*list_operation)["delay" ] = param_delay ; + + operation ++; + value_operation = toString(operation); + stop = have_operation or (operation == MAX_OPERATION); + }; + + } + + testAttributesEmpty(child,attributes); + } + //-------------------------------------------- + // Child : Other (node) + //-------------------------------------------- + else + { + testSingleton (child,false); + + attributes_t attributes = child->getAttributes(); + attribute_t value_id = getAttribute(child,attributes,"id"); + attribute_t value_type = child->getName(); + + testAttributesEmpty(child,attributes); + + // Create a new component + { + Instance_component * param = new Instance_component(value_type, // type + value_id); + +// log_printf(TRACE,Configuration,FUNCTION,"%s.%s",value_type.c_str(),value_id.c_str()); +// log_printf(TRACE,Configuration,FUNCTION," * %d",((*list_components)[value_type]).size()); + + // Test if this id is previously used + if (((*list_components)[value_type]).find(value_id) != ((*list_components)[value_type]).end()) + throw ERRORMORPHEO(FUNCTION,toString(_("A Component \"%s\" with id \"%s\" is previously declared.\n"),value_type.c_str(),value_id.c_str())); + + ((*list_components)[value_type])[value_id] = param; + } + + // Test if counter is an parameters + { + std::string name_counter = "nb_"+value_type; +// std::cout << name_counter << std::endl; + + if (list_parameters->find(name_counter) == list_parameters->end()) + { + // Scearch all occurante of this type + uint32_t nb_counter = xml->getNodes(value_type).size(); +// std::cout << " * " << nb_counter << std::endl; + + // Insert in array + Parameter_affectation * param = new Parameter_affectation(name_counter, // type + toString(nb_counter)); + + // insert parameter + (*list_parameters)[name_counter] = param; + } + } + + // Recursive function + fromXMLLight (child, + ((id=="")?value_id:(id+"."+value_id)), // construction of identificator + ((*list_components)[value_type])[value_id]->_list_parameters, +// ((*list_components)[value_type])[value_id]->_list_links, + list_links, + ((*list_components)[value_type])[value_id]->_list_components); + } + } + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp (revision 88) @@ -0,0 +1,91 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::getLink" + std::vector Instance::getLink (const char * name, ...) + { + log_begin(Configuration,FUNCTION); + + std::string src = ""; + std::string dest; + + // Create src id + { + va_list args; + va_start(args, name); + + std::string tmp; + while ((tmp = va_arg(args,const char *)) != "") + { + if (src == "") + src = tmp; + else + src += "." + tmp; + } + va_end(args); + } + + // Find link + bool find = true; + + { + // find link + list_links_t::iterator it1=_list_links->find(name); + + if (it1 == _list_links->end()) + { +// log_printf(INFO,Configuration,FUNCTION,_("Link \"%s\" is not define, don't link."),name); + find = false; + } + else + { + // Find src + list_link_t::iterator it2=it1->second.find(src); + + if (it2 == it1->second.end()) + { +// log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\" is not define, don't link."),name,src.c_str()); + find = false; + } + else + { + if (it2->second->_use) + throw ERRORMORPHEO(FUNCTION,toString(_("Link \"%s[%s]\" is already used.\n"),name,src.c_str())); + + dest = it2->second->_dest; + it2->second->_use = true; // now, this parameters is use + } + } + } + + std::vector _return; + if (find) + { + _return = link2array(dest); + log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\"= %s."),name,src.c_str(),dest.c_str()); + } + else + { + _return.clear(); + log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\" not find."),name,src.c_str()); + } + + log_end(Configuration,FUNCTION); + + return _return; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getName.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getName.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getName.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::getName" + std::string Instance::getName (void) + { + log_begin(Configuration,FUNCTION); + + std::string _return = _name; + + log_end(Configuration,FUNCTION); + + return _return; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp (revision 88) @@ -0,0 +1,96 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::getParam" + std::string Instance::getParam (const char * name, ...) + { + log_begin(Configuration,FUNCTION); + + std::string value = ""; + + // Go to the good component + list_parameters_t * list_parameters = _list_parameters; + list_components_t * list_components = _list_components; + + { + va_list args; + va_start(args, name); + + std::string component = ""; + std::string id = ""; + std::string tmp; + while (((tmp = va_arg(args,const char *)) != "") and + (value == "")) + { + // 2 string : + // * first : component + // * second : id + + component = tmp; + + if ((tmp = va_arg(args,const char *)) == "") + throw ERRORMORPHEO(FUNCTION,_("Must have two name : first is the component's name, second is the identification\n")); + id = tmp; + + list_instances_t::iterator it=((*list_components)[component]).find(id); + + if (it == ((*list_components)[component]).end()) + { + log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is not define, take default value for parameter \"%s\"."),component.c_str(),id.c_str(),name); + + value = _generator->getParam(name)->_default; + } + else + { + list_parameters = it->second->_list_parameters; + list_components = it->second->_list_components; + } + } + + if (value == "") + { + // no default value : component is find + + // Test if parameters exist +// std::map + list_parameters_t::iterator it=(*list_parameters).find(name); + if (it == (*list_parameters).end()) + { + log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is define, but parameter \"%s\" is not define. Take default value."),component.c_str(),id.c_str(),name); + + value = _generator->getParam(name)->_default; + } + else + { + if (it->second->_use) + throw ERRORMORPHEO(FUNCTION,toString(_("Parameter \"%s\" is already used.\n"),name)); + + value = it->second->_value; + it->second->_use = true; // now, this parameters is use + } + } + + va_end(args); + } + + log_printf(INFO,Configuration,FUNCTION,_("Parameters \"%s\" = %s."),name,value.c_str()); + + log_end(Configuration,FUNCTION); + + return value; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_link2array.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_link2array.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_link2array.cpp (revision 88) @@ -0,0 +1,42 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::link2array" + std::vector Instance::link2array (std::string str) + { + log_begin(Configuration,FUNCTION); + + std::vector _return; + + size_t begin=0; + size_t end =0; + + do + { + end = str.find_first_of(".",begin); // "." is the separator + + _return.push_back(str.substr(begin, end-begin)); + + begin = end+1; // next index + } + while (end!=std::string::npos); + + log_end(Configuration,FUNCTION); + + return _return; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::print" + std::string Instance::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Instance::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Instance & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test.cpp (revision 88) @@ -0,0 +1,107 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::test" + void Instance::test (std::string type, + std::string value) + { + log_begin(Configuration,FUNCTION); + + // Test the parameter : + // * name is correct + // * value is correct + + _generator->test(type, value); + + log_end(Configuration,FUNCTION); + } + +#undef FUNCTION +#define FUNCTION "Instance::test" + void Instance::test (std::string type, + std::string father_name, + bool father_is_src, + bool father_is_dest) + { + log_begin(Configuration,FUNCTION); + + // * name is correct + // * if not have_src , test if src is correct + // * if not have_dest, test if dest is correct + _generator->test(type, + father_name, + father_is_src, + father_is_dest); + + log_end(Configuration,FUNCTION); + } + +#undef FUNCTION +#define FUNCTION "Instance::test" + + void Instance::test (std::string link, + std::vector & vect, + uint32_t nb_elt) + { + log_begin(Configuration,FUNCTION); + + if (vect.size() == 0) + for (uint32_t i=0; ibegin(); + it1!=list_components->end(); + ++it1) + for (list_instances_t::iterator it2=it1->second.begin(); + it2!=it1->second.end(); + ++it2) + test (component,nb_component,it2->second->_list_components); + + log_end(Configuration,FUNCTION); + } + */ + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test_use.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test_use.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_test_use.cpp (revision 88) @@ -0,0 +1,99 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::test_use" + void Instance::test_use (void) + { + log_begin(Configuration,FUNCTION); + + std::vector list_not_use; + + for (list_links_t::iterator it1 = _list_links->begin(); + it1 != _list_links->end(); + ++it1) + for (list_link_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + { + Link_affectation * link = it2->second; + if (link->_use == false) + { + std::string str = link->_name; + + list_not_use.push_back(toString(_("Link \"%s[%s]\""),str.c_str(),link->_src.c_str())); + } + } + + test_use("", + _list_parameters, + _list_components, + list_not_use); + + if (list_not_use.size() != 0) + { + std::string str = ""; + for (uint32_t i=0; i & list_not_use) + { + log_begin(Configuration,FUNCTION); + + for (list_parameters_t::iterator it = list_parameters->begin(); + it != list_parameters->end(); + ++it) + { + Parameter_affectation * param = it->second; + if (param->_use == false) + { + std::string str = ((name == "")?"":(name+".")) + param->_name; + + list_not_use.push_back(toString(_("Parameter \"%s\""),str.c_str())); + } + } + + for (list_components_t::iterator it1 = list_components->begin(); + it1 != list_components->end(); + ++it1) + for (list_instances_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + { + Instance_component * instance = it2->second; + + test_use(((name == "")?"":(name+"."))+instance->_name+"["+instance->_id+"]", + instance->_list_parameters, + instance->_list_components, + list_not_use); + } + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toFile.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::toFile" + void Instance::toFile (std::string dirname) + { + log_begin(Configuration,FUNCTION); + + (toXML()).generate_file(dirname); + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_toXML.cpp (revision 88) @@ -0,0 +1,53 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Instance.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Instance::toXML" + XML Instance::toXML (void) + { + XML xml (basename(_filename.c_str())); + xml.filename_extension(""); + + xml.balise_open_begin("core"); + xml.attribut("name",_name); + xml.balise_open_end (); + + for (list_parameters_t::iterator it = _list_parameters->begin(); + it != _list_parameters->end(); + ++it) + xml.insert_XML(it->second->toXML(),1); + + for (list_links_t::iterator it1 = _list_links->begin(); + it1 != _list_links->end(); + ++it1) + for (list_link_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + xml.insert_XML(it2->second->toXML(),1); + + for (list_components_t::iterator it1 = _list_components->begin(); + it1 != _list_components->end(); + ++it1) + for (list_instances_t::iterator it2 = it1->second.begin(); + it2 != it1->second.end(); + ++it2) + xml.insert_XML(it2->second->toXML(),1); + + xml.balise_close(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation.cpp (revision 88) @@ -0,0 +1,41 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_affectation.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_affectation::Link_affectation" + Link_affectation::Link_affectation (std::string name, + std::string src , + std::string dest): + _name (name), + _src (src ), + _dest (dest) + { + log_begin(Configuration,FUNCTION); + + _use = false; + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Link_affectation::~Link_affectation" + Link_affectation::~Link_affectation () + { + log_begin(Configuration,FUNCTION); + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_affectation.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_affectation::print" + std::string Link_affectation::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Link_affectation::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Link_affectation & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_affectation_toXML.cpp (revision 88) @@ -0,0 +1,31 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_affectation.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_affectation::toXML" + XML Link_affectation::toXML (void) + { + XML xml (_name); + + xml.singleton_begin("link"); + xml. attribut("name",_name); + xml. attribut("src" ,_src ); + xml. attribut("dest",_dest); + xml.singleton_end(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition.cpp (revision 88) @@ -0,0 +1,40 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_definition.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_definition::Link_definition" + Link_definition::Link_definition (std::string name , + std::string src , + std::string dest , + std::string description): + _name (name ), + _src (src ), + _dest (dest ), + _description (description ) + { + log_begin(Configuration,FUNCTION); + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Link_definition::~Link_definition" + Link_definition::~Link_definition () + { + log_begin(Configuration,FUNCTION); + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_definition.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_definition::print" + std::string Link_definition::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Link_definition::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Link_definition & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Link_definition_toXML.cpp (revision 88) @@ -0,0 +1,32 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Link_definition.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Link_definition::toXML" + XML Link_definition::toXML (void) + { + XML xml (_name); + + xml.singleton_begin("link"); + xml. attribut("name" ,_name ); + xml. attribut("src" ,_src ); + xml. attribut("dest" ,_dest ); + xml. attribut("description",_description); + xml.singleton_end(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_affectation.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_affectation::Parameter_affectation" + Parameter_affectation::Parameter_affectation (std::string name , + std::string value ): + _name (name ), + _value (value ) + { + log_begin(Configuration,FUNCTION); + + _use = false; + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Parameter_affectation::~Parameter_affectation" + Parameter_affectation::~Parameter_affectation () + { + log_begin(Configuration,FUNCTION); + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_affectation.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_affectation::print" + std::string Parameter_affectation::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Parameter_affectation::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Parameter_affectation & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_affectation_toXML.cpp (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_affectation.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_affectation::toXML" + XML Parameter_affectation::toXML (void) + { + XML xml (_name); + + xml.singleton_begin("parameter"); + xml. attribut("name" ,_name ); + xml. attribut("value",_value); + xml.singleton_end(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition.cpp (revision 88) @@ -0,0 +1,50 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_definition.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_definition::Parameter_definition" + Parameter_definition::Parameter_definition (std::string name , + std::string min , + std::string max , + std::string step , + std::string value_default, + std::string level , + std::string description): + _name (name ), + _min (min ), + _max (max ), + _step (step ), + _default (value_default), + _level (level ), + _description (description ) + { + log_begin(Configuration,FUNCTION); + + test(_max); + test(_default); + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Parameter_definition::~Parameter_definition" + Parameter_definition::~Parameter_definition () + { + log_begin(Configuration,FUNCTION); + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_definition.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_definition::print" + std::string Parameter_definition::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Parameter_definition::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Parameter_definition & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_test.cpp (revision 88) @@ -0,0 +1,64 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_definition.h" +#include "Behavioural/include/Stat_binary_tree.h" +#include "Common/include/FromString.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_definition::test" + void Parameter_definition::test (std::string x) + { + log_begin(Configuration,FUNCTION); + + std::map * operand = new std::map; + + std::string expr = _step+" "+_name; + std::string expr_str = _name + "(n+1) = "+_step+" "+_name+"(n)"; + + counter_t value; + (*operand)[_name] = &value; + + Stat_binary_tree * tree; + try + { + tree = new Stat_binary_tree(expr,operand); + } + catch (morpheo::ErrorMorpheo & error) + { + throw (ERRORMORPHEO (FUNCTION,toString(_("step make an invalid infix expression : \"%s\"\n"),expr_str.c_str()))); + } + + counter_t min = fromString(_min); + counter_t max = fromString(_max); + + value = min; + while ((value != fromString(x)) and (value <= max)) + { + counter_t tmp = tree->eval(); + + // warning, can have infinite loop + value = (tmp == value)?(max+1):tmp; + } + + if (value > max) + { + throw (ERRORMORPHEO (FUNCTION,toString(_("With the expression \"%s\" and \"%s(0) = %s\" and value between [%s:%s], \"%s(n) = %s\" is not a valid value.\n"),expr_str.c_str(),_name.c_str(),_min.c_str(),_min.c_str(),_max.c_str(),_name.c_str(),x.c_str()))); + } + + delete tree; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Parameter_definition_toXML.cpp (revision 88) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Parameter_definition.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Parameter_definition::toXML" + XML Parameter_definition::toXML (void) + { + XML xml (_name); + + xml.singleton_begin("parameter"); + xml. attribut("name" , _name ); + xml. attribut("min" ,toString(_min )); + xml. attribut("max" ,toString(_max )); + xml. attribut("step" , _step ); + xml. attribut("default" ,toString(_default)); + xml. attribut("level" ,toString(_level)); + xml. attribut("description", _description); + xml.singleton_end(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator.cpp (revision 88) @@ -0,0 +1,49 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::Simulator" + Simulator::Simulator (std::string filename) + { + log_begin(Configuration,FUNCTION); + + _filename = filename; + _array = new std::map; + + fromFile (filename); + + log_end(Configuration,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Simulator::~Simulator" + Simulator::~Simulator () + { + log_begin(Configuration,FUNCTION); + + for (std::map::iterator it = _array->begin(); + it != _array->end(); + ++it) + { + delete it->second; + } + + delete _array; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_fromFile.cpp (revision 88) @@ -0,0 +1,77 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" +#include "Common/include/FromString.h" +#include + +namespace morpheo { +namespace behavioural { +namespace configuration { + + using namespace XMLUtils; + +#undef FUNCTION +#define FUNCTION "Simulator::fromFile" + void Simulator::fromFile (std::string filename) + { + log_begin(Configuration,FUNCTION); + + msg_printf(INFORMATION,_("Read file \"%s\"."),filename.c_str()); + + std::ifstream file (filename.c_str()); + + // Test the file open + if (!file) + throw ERRORMORPHEO(FUNCTION,toString(_("Error opening \"%s\" file.\n"),filename.c_str())); + + XML_t * _xml = new FileXMLLight(file); + + // Test root node : Root name, must not a singleton, have none attribute + testNodeName (_xml,"parameters"); + testSingleton (_xml,false); + testNoAttribute(_xml); + + XMLLightVector vect = _xml->getNodes(); + +// std::cout << vect << std::endl; + + for (uint32_t i=0; igetAttributes(); + +// std::cout << "Node [" << name << "]" << std::endl; +// std::cout << " * nb attributes : " << xml->getAttributes().size() << std::endl; + + attribute_t value_name = getAttribute(xml,attributes,"name" ); + attribute_t value = getAttribute(xml,attributes,"value"); + + testAttributesEmpty(xml,attributes); + + // Insert in array + Parameter_affectation * param = new Parameter_affectation(value_name, + value ); + + insert(param); + } + + delete _xml; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_getParam.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_getParam.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_getParam.cpp (revision 88) @@ -0,0 +1,32 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::getParam" + std::string Simulator::getParam (std::string name) + { + log_begin(Configuration,FUNCTION); + + if (_array->find(name) == _array->end()) + throw ERRORMORPHEO(FUNCTION,toString(_("Simulator file \"%s\" does't have the parameters \"%s\".\n"),_filename.c_str(),name.c_str())); + + std::string res = ((*_array)[name])->_value; + + log_end(Configuration,FUNCTION); + + return res; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_insert.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::insert" + void Simulator::insert (Parameter_affectation * param) + { + log_begin(Configuration,FUNCTION); + + (*_array)[param->_name] = param; + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_print.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::print" + std::string Simulator::print (uint32_t depth) + { + log_begin(Configuration,FUNCTION); + + std::string _return = (toXML()).get_body(depth); + + log_end(Configuration,FUNCTION); + return _return; + }; + +#undef FUNCTION +#define FUNCTION "Simulator::operator<<" + std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::configuration::Simulator & x) + { + log_begin(Configuration,FUNCTION); + output << x.print(0); + log_end(Configuration,FUNCTION); + return output; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toFile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toFile.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toFile.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::toFile" + void Simulator::toFile (std::string dirname) + { + log_begin(Configuration,FUNCTION); + + (toXML()).generate_file(dirname); + + log_end(Configuration,FUNCTION); + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toXML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toXML.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Simulator_toXML.cpp (revision 88) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Simulator.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Simulator::toXML" + XML Simulator::toXML (void) + { + XML xml (basename(_filename.c_str())); + xml.filename_extension(""); + + xml.balise_open("parameters"); + for (std::map::iterator it = _array->begin(); + it != _array->end(); + ++it) + { + xml.insert_XML(it->second->toXML(),1); + } + xml.balise_close(); + + return xml; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_getAttribute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_getAttribute.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_getAttribute.cpp (revision 88) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/XMLUtils.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "getAttribute" + attribute_t getAttribute(XML_t * xml, + attributes_t & attributes, + const attribute_t & name) + { + // List attribute + attributes_t::iterator it = attributes.find(name); + + if (it == attributes.end()) + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"%s\" must have attribute \"%s\"\n"),xml->getName().c_str(),name.c_str())); + + attribute_t str = it->second; + + attributes.erase(it); + + return str; + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testAttributesEmpty.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testAttributesEmpty.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testAttributesEmpty.cpp (revision 88) @@ -0,0 +1,37 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/XMLUtils.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "testAttributesEmpty" + void testAttributesEmpty (XML_t * xml, + attributes_t attributes) + { + // Test if attributes is empty + if (not attributes.empty()) + { + std::string msg = ""; + for (attributes_t::iterator it=attributes.begin(); + it!=attributes.end(); + ++it) + { + if (it!=attributes.begin()) + msg+= ", "; + msg+=it->first; + } + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"%s\" must have not this attributes : %s\n"),xml->getName().c_str(),msg.c_str())); + } + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNoAttribute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNoAttribute.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNoAttribute.cpp (revision 88) @@ -0,0 +1,25 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/XMLUtils.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "testNoAttribute" + + void testNoAttribute (XML_t * xml) + { + if (xml->getAttributes().size() != 0) + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"%s\" have none attribute\n"),xml->getName().c_str())); + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNodeName.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNodeName.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testNodeName.cpp (revision 88) @@ -0,0 +1,25 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/XMLUtils.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "testNodeName" + + void testNodeName (XML_t * xml, std::string name) + { + if (xml->getName() != name) + throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node is \"%s\", but must be \"%s\"\n"),xml->getName().c_str(),name.c_str())); + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testSingleton.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testSingleton.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/XMLUtils_testSingleton.cpp (revision 88) @@ -0,0 +1,33 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/XMLUtils.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "testSingleton" + + void testSingleton (XML_t * xml, bool must_be_singleton) + { + std::string name = xml->getName (); + + if (must_be_singleton) + { +// if (xml->getNodes().size() != 0) // isSingleton +// throw ERRORMORPHEO(FUNCTION,toString(_("Syntax error, node \"%s\" must be a singleton\n"),name.c_str())); + } + else + { + } + } + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libCore_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Core_Glue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Core_Glue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Core_Glue + +#-----[ Library ]------------------------------------------ + +Core_Glue_LIBRARY = -lCore_Glue \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Core_Glue_DIR_LIBRARY = -L$(Core_Glue_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Core_Glue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Core_Glue_DIR) --makefile=Makefile; + +Core_Glue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Core_Glue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Core_Glue_LIBRARY) + +DIR_LIBRARY = $(Core_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Core_Glue_library + +library_clean : Core_Glue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-1_front_end-1_ooo_engine-1_execute_loop.cfg (revision 88) @@ -0,0 +1,45 @@ +Core_Glue +1 1 +1 # nb_front_end +1 4 *4 # nb_context [0] [nb_front_end] +1 1 +1 # nb_ooo_engine +1 1 +1 # nb_execute_loop +1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] +1 1 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] +4 4 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] +4 4 +1 # nb_inst_insert [0] [nb_ooo_engine] +4 4 +1 # nb_inst_issue [0] [nb_ooo_engine] +4 4 +1 # nb_inst_execute [0] [nb_ooo_engine] +4 4 +1 # nb_read_unit [0] [nb_execute_loop] +4 4 +1 # nb_write_unit [0] [nb_execute_loop] +3 3 +1 # size_depth +5 5 +1 # size_rob_ptr +8 8 +1 # size_load_queue_ptr +8 8 +1 # size_store_queue_ptr +32 32 +1 # size_general_data +2 2 +1 # size_special_data +6 6 +1 # size_general_register +2 2 +1 # size_special_register +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing +1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [3][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [3][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [3][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [3][0][0][3] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] +0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-1_ooo_engine-1_execute_loop.cfg (revision 88) @@ -0,0 +1,50 @@ +Core_Glue +4 4 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +2 2 +1 # nb_context [1] [nb_front_end] +4 4 +1 # nb_context [2] [nb_front_end] +3 3 +1 # nb_context [3] [nb_front_end] +1 1 +1 # nb_ooo_engine +1 1 +1 # nb_execute_loop +4 4 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] +1 1 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +2 2 +1 # nb_inst_decod [1] [nb_front_end] +1 1 +1 # nb_inst_decod [2] [nb_front_end] +3 3 +1 # nb_inst_decod [3] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [1] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [2] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [3] [nb_front_end] +4 4 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] +3 3 +1 # nb_inst_insert [0] [nb_ooo_engine] +3 3 +1 # nb_inst_issue [0] [nb_ooo_engine] +4 4 +1 # nb_inst_execute [0] [nb_ooo_engine] +3 3 +1 # nb_read_unit [0] [nb_execute_loop] +4 4 +1 # nb_write_unit [0] [nb_execute_loop] +3 3 +1 # size_depth +5 5 +1 # size_rob_ptr +8 8 +1 # size_load_queue_ptr +8 8 +1 # size_store_queue_ptr +32 32 +1 # size_general_data +2 2 +1 # size_special_data +6 6 +1 # size_general_register +2 2 +1 # size_special_register +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing +1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] +1 1 +1 # translate_ooo_engine_num_front_end [0][1] [nb_ooo_engine][ooo_engine_nb_front_end] +2 2 +1 # translate_ooo_engine_num_front_end [0][2] [nb_ooo_engine][ooo_engine_nb_front_end] +3 3 +1 # translate_ooo_engine_num_front_end [0][3] [nb_ooo_engine][ooo_engine_nb_front_end] +0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-1_execute_loop.cfg (revision 88) @@ -0,0 +1,75 @@ +Core_Glue +4 4 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +2 2 +1 # nb_context [1] [nb_front_end] +4 4 +1 # nb_context [2] [nb_front_end] +3 3 +1 # nb_context [3] [nb_front_end] +3 3 +1 # nb_ooo_engine +1 1 +1 # nb_execute_loop +1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] +2 2 +1 # ooo_engine_nb_front_end [1] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_front_end [2] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [1] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [2] [nb_ooo_engine] +3 3 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +2 2 +1 # nb_inst_decod [1] [nb_front_end] +1 1 +1 # nb_inst_decod [2] [nb_front_end] +3 3 +1 # nb_inst_decod [3] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] +2 2 +1 # front_end_nb_inst_branch_complete [1] [nb_front_end] +2 2 +1 # front_end_nb_inst_branch_complete [2] [nb_front_end] +3 3 +1 # front_end_nb_inst_branch_complete [3] [nb_front_end] +4 4 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] +2 2 +1 # ooo_engine_nb_inst_branch_complete [1] [nb_ooo_engine] +3 3 +1 # ooo_engine_nb_inst_branch_complete [2] [nb_ooo_engine] +3 3 +1 # nb_inst_insert [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert [1] [nb_ooo_engine] +2 2 +1 # nb_inst_insert [2] [nb_ooo_engine] +3 3 +1 # nb_inst_issue [0] [nb_ooo_engine] +1 1 +1 # nb_inst_issue [1] [nb_ooo_engine] +2 2 +1 # nb_inst_issue [2] [nb_ooo_engine] +4 4 +1 # nb_inst_execute [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +4 4 +1 # nb_inst_execute [1][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +4 4 +1 # nb_inst_execute [2][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +3 3 +1 # nb_read_unit [0] [nb_execute_loop] +4 4 +1 # nb_write_unit [0] [nb_execute_loop] +3 3 +1 # size_depth +5 5 +1 # size_rob_ptr +8 8 +1 # size_load_queue_ptr +8 8 +1 # size_store_queue_ptr +32 32 +1 # size_general_data +2 2 +1 # size_special_data +6 6 +1 # size_general_register +2 2 +1 # size_special_register +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing +1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] +1 1 +1 # translate_ooo_engine_num_front_end [1][0] [nb_ooo_engine][ooo_engine_nb_front_end] +2 2 +1 # translate_ooo_engine_num_front_end [1][1] [nb_ooo_engine][ooo_engine_nb_front_end] +3 3 +1 # translate_ooo_engine_num_front_end [2][0] [nb_ooo_engine][ooo_engine_nb_front_end] +0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_ooo_engine_num_execute_loop [1][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_ooo_engine_num_execute_loop [2][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] +1 1 +1 # translate_execute_loop_num_ooo_engine [0][1] [nb_execute_loop][execute_loop_nb_ooo_engine] +2 2 +1 # translate_execute_loop_num_ooo_engine [0][2] [nb_execute_loop][execute_loop_nb_ooo_engine] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-4_front_end-3_ooo_engine-2_execute_loop.cfg (revision 88) @@ -0,0 +1,98 @@ +Core_Glue +4 4 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +2 2 +1 # nb_context [1] [nb_front_end] +4 4 +1 # nb_context [2] [nb_front_end] +3 3 +1 # nb_context [3] [nb_front_end] +3 3 +1 # nb_ooo_engine +2 2 +1 # nb_execute_loop +1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] +2 2 +1 # ooo_engine_nb_front_end [1] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_front_end [2] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] +2 2 +1 # ooo_engine_nb_execute_loop [1] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [2] [nb_ooo_engine] +2 2 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] +1 1 +1 # execute_loop_nb_ooo_engine [1] [nb_execute_loop] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +2 2 +1 # nb_inst_decod [1] [nb_front_end] +1 1 +1 # nb_inst_decod [2] [nb_front_end] +3 3 +1 # nb_inst_decod [3] [nb_front_end] +4 4 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] +2 2 +1 # front_end_nb_inst_branch_complete [1] [nb_front_end] +2 2 +1 # front_end_nb_inst_branch_complete [2] [nb_front_end] +3 3 +1 # front_end_nb_inst_branch_complete [3] [nb_front_end] +4 4 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] +2 2 +1 # ooo_engine_nb_inst_branch_complete [1] [nb_ooo_engine] +3 3 +1 # ooo_engine_nb_inst_branch_complete [2] [nb_ooo_engine] +3 3 +1 # nb_inst_insert [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert [1] [nb_ooo_engine] +2 2 +1 # nb_inst_insert [2] [nb_ooo_engine] +3 3 +1 # nb_inst_issue [0] [nb_ooo_engine] +1 1 +1 # nb_inst_issue [1] [nb_ooo_engine] +2 2 +1 # nb_inst_issue [2] [nb_ooo_engine] +4 4 +1 # nb_inst_execute [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +3 3 +1 # nb_inst_execute [1][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +4 4 +1 # nb_inst_execute [1][1] [nb_ooo_engine][ooo_engine_nb_execute_loop] +4 4 +1 # nb_inst_execute [2][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +3 3 +1 # nb_read_unit [0] [nb_execute_loop] +3 3 +1 # nb_read_unit [1] [nb_execute_loop] +4 4 +1 # nb_write_unit [0] [nb_execute_loop] +3 3 +1 # nb_write_unit [1] [nb_execute_loop] +3 3 +1 # size_depth +5 5 +1 # size_rob_ptr +8 8 +1 # size_load_queue_ptr +8 8 +1 # size_store_queue_ptr +32 32 +1 # size_general_data +2 2 +1 # size_special_data +6 6 +1 # size_general_register +2 2 +1 # size_special_register +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing +1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [0][2][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [1][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][0][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][0][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][1][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][1][1] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +1 1 +1 # table_dispatch [2][1][1][2] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] +1 1 +1 # translate_ooo_engine_num_front_end [1][0] [nb_ooo_engine][ooo_engine_nb_front_end] +2 2 +1 # translate_ooo_engine_num_front_end [1][1] [nb_ooo_engine][ooo_engine_nb_front_end] +3 3 +1 # translate_ooo_engine_num_front_end [2][0] [nb_ooo_engine][ooo_engine_nb_front_end] +0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +1 1 +1 # translate_ooo_engine_num_execute_loop [1][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_ooo_engine_num_execute_loop [1][1] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_ooo_engine_num_execute_loop [2][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] +2 2 +1 # translate_execute_loop_num_ooo_engine [0][1] [nb_execute_loop][execute_loop_nb_ooo_engine] +1 1 +1 # translate_execute_loop_num_ooo_engine [1][0] [nb_execute_loop][execute_loop_nb_ooo_engine] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,30 @@ +Core_Glue +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_ooo_engine +1 1 +1 # nb_execute_loop +1 1 +1 # ooo_engine_nb_front_end [0] [nb_ooo_engine] +1 1 +1 # ooo_engine_nb_execute_loop [0] [nb_ooo_engine] +1 1 +1 # execute_loop_nb_ooo_engine [0] [nb_execute_loop] +1 1 +1 # nb_inst_decod [0] [nb_front_end] +1 1 +1 # front_end_nb_inst_branch_complete [0] [nb_front_end] +1 1 +1 # ooo_engine_nb_inst_branch_complete [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert [0] [nb_ooo_engine] +1 1 +1 # nb_inst_issue [0] [nb_ooo_engine] +1 1 +1 # nb_inst_execute [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +1 1 +1 # nb_read_unit [0] [nb_execute_loop] +1 1 +1 # nb_write_unit [0] [nb_execute_loop] +1 1 +1 # size_depth +1 1 +1 # size_rob_ptr +1 1 +1 # size_load_queue_ptr +2 2 +1 # size_store_queue_ptr +32 32 +1 # size_general_data +2 2 +1 # size_special_data +6 6 +1 # size_general_register +2 2 +1 # size_special_register +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing +1 1 +1 # table_dispatch [0][0][0][0] [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] +0 0 +1 # translate_ooo_engine_num_front_end [0][0] [nb_ooo_engine][ooo_engine_nb_front_end] +0 0 +1 # translate_ooo_engine_num_execute_loop [0][0] [nb_ooo_engine][ooo_engine_nb_execute_loop] +0 0 +1 # translate_execute_loop_num_ooo_engine [0][0] [nb_execute_loop][execute_loop_nb_ooo_engine] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Behavioural/include/Selftest.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; + +using namespace morpheo::behavioural::core::core_glue; + +void test (string name, + morpheo::behavioural::core::core_glue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,261 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 13 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_ooo_engine (uint32_t )\n")); + err (_(" * nb_execute_loop (uint32_t )\n")); + err (_(" * ooo_engine_nb_front_end [nb_ooo_engine] (uint32_t )\n")); + err (_(" * ooo_engine_nb_execute_loop [nb_ooo_engine] (uint32_t )\n")); + err (_(" * execute_loop_nb_ooo_engine [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_inst_decod [nb_front_end] (uint32_t )\n")); + err (_(" * front_end_nb_inst_branch_complete [nb_front_end] (uint32_t )\n")); + err (_(" * ooo_engine_nb_inst_branch_complete [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_insert [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_issue [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_execute [nb_ooo_engine][ooo_engine_nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_read_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_write_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * size_depth (uint32_t )\n")); + err (_(" * size_rob_ptr (uint32_t )\n")); + err (_(" * size_load_queue_ptr (uint32_t )\n")); + err (_(" * size_store_queue_ptr (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); + err (_(" * size_general_register (uint32_t )\n")); + err (_(" * size_special_register (uint32_t )\n")); + err (_(" * dispatch_priority (Tpriority_t )\n")); + err (_(" * dispatch_load_balancing (Tload_balancing_t)\n")); + err (_(" * table_dispatch [nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] (bool )\n")); + err (_(" * translate_ooo_engine_num_front_end [nb_ooo_engine][ooo_engine_nb_front_end] (uint32_t )\n")); + err (_(" * translate_ooo_engine_num_execute_loop [nb_ooo_engine][ooo_engine_nb_execute_loop] (uint32_t )\n")); + err (_(" * translate_execute_loop_num_ooo_engine [nb_execute_loop][execute_loop_nb_ooo_engine] (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + int nb_params; + + nb_params = static_cast (2+NB_PARAMS); + if (argc < nb_params) + usage (argc, argv); + + uint32_t x = 1; + + uint32_t nb_front_end ; + uint32_t * nb_context ;//[nb_front_end] + uint32_t nb_ooo_engine ; + uint32_t nb_execute_loop ; + uint32_t * ooo_engine_nb_front_end ;//[nb_ooo_engine] + uint32_t * ooo_engine_nb_execute_loop ;//[nb_ooo_engine] + uint32_t * execute_loop_nb_ooo_engine ;//[nb_execute_loop] + uint32_t * nb_inst_decod ;//[nb_front_end] -> [sum_inst_decod] + uint32_t * front_end_nb_inst_branch_complete ;//[nb_front_end] + uint32_t * ooo_engine_nb_inst_branch_complete ;//[nb_ooo_engine] + uint32_t * nb_inst_insert ;//[nb_ooo_engine] + uint32_t * nb_inst_issue ;//[nb_ooo_engine] + uint32_t ** nb_inst_execute ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t * nb_read_unit ;//[nb_execute_loop] + uint32_t * nb_write_unit ;//[nb_execute_loop] + uint32_t size_depth ; + uint32_t size_rob_ptr ; + uint32_t size_load_queue_ptr ; + uint32_t size_store_queue_ptr ; + uint32_t size_general_data ; + uint32_t size_special_data ; + uint32_t size_general_register ; + uint32_t size_special_register ; + Tpriority_t dispatch_priority ; + Tload_balancing_t dispatch_load_balancing ; + bool **** table_dispatch ;//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] + uint32_t ** translate_ooo_engine_num_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] + uint32_t ** translate_ooo_engine_num_execute_loop;//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t ** translate_execute_loop_num_ooo_engine;//[nb_execute_loop][execute_loop_nb_ooo_engine] + + string name = argv[x++]; + + SELFTEST0(nb_front_end ,uint32_t ,argv,x); + + nb_params = static_cast (2+NB_PARAMS+ + 1*nb_front_end); + if (argc < nb_params) + usage (argc, argv); + + SELFTEST1(nb_context ,uint32_t ,argv,x,nb_front_end); + SELFTEST0(nb_ooo_engine ,uint32_t ,argv,x); + SELFTEST0(nb_execute_loop ,uint32_t ,argv,x); + + nb_params = static_cast (2+NB_PARAMS+ + 3*nb_front_end+ + 5*nb_ooo_engine+ + 3*nb_execute_loop + ); + if (argc < nb_params) + usage (argc, argv); + + SELFTEST1(ooo_engine_nb_front_end ,uint32_t ,argv,x,nb_ooo_engine); + SELFTEST1(ooo_engine_nb_execute_loop ,uint32_t ,argv,x,nb_ooo_engine); + SELFTEST1(execute_loop_nb_ooo_engine ,uint32_t ,argv,x,nb_execute_loop); + SELFTEST1(nb_inst_decod ,uint32_t ,argv,x,nb_front_end); + SELFTEST1(front_end_nb_inst_branch_complete ,uint32_t ,argv,x,nb_front_end); + SELFTEST1(ooo_engine_nb_inst_branch_complete ,uint32_t ,argv,x,nb_ooo_engine); + SELFTEST1(nb_inst_insert ,uint32_t ,argv,x,nb_ooo_engine); + SELFTEST1(nb_inst_issue ,uint32_t ,argv,x,nb_ooo_engine); + + uint32_t sum_ooo_engine_nb_front_end = 0; + uint32_t sum_ooo_engine_nb_execute_loop = 0; + uint32_t sum_nb_inst_issue = 0; + + for (uint32_t i=0; i (2+NB_PARAMS+ + 3*nb_front_end+ + 5*nb_ooo_engine+ + 3*nb_execute_loop+ + 1*sum_ooo_engine_nb_execute_loop + ); + if (argc < nb_params) + usage (argc, argv); + + SELFTEST2(nb_inst_execute ,uint32_t ,argv,x,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); + SELFTEST1(nb_read_unit ,uint32_t ,argv,x,nb_execute_loop); + SELFTEST1(nb_write_unit ,uint32_t ,argv,x,nb_execute_loop); + SELFTEST0(size_depth ,uint32_t ,argv,x); + SELFTEST0(size_rob_ptr ,uint32_t ,argv,x); + SELFTEST0(size_load_queue_ptr ,uint32_t ,argv,x); + SELFTEST0(size_store_queue_ptr ,uint32_t ,argv,x); + SELFTEST0(size_general_data ,uint32_t ,argv,x); + SELFTEST0(size_special_data ,uint32_t ,argv,x); + SELFTEST0(size_general_register ,uint32_t ,argv,x); + SELFTEST0(size_special_register ,uint32_t ,argv,x); + + uint32_t sum_execute_loop_nb_ooo_engine = 0; + uint32_t sum_nb_read_unit = 0; + + for (uint32_t i=0; i (2+NB_PARAMS+ + 3*nb_front_end+ + 5*nb_ooo_engine+ + 3*nb_execute_loop+ + sum_nb_inst_issue*sum_nb_read_unit+ + sum_ooo_engine_nb_front_end+ + 2*sum_ooo_engine_nb_execute_loop+ + sum_execute_loop_nb_ooo_engine + ); + if (argc != nb_params) + usage (argc, argv); + + SELFTEST0(dispatch_priority ,Tpriority_t ,argv,x); + SELFTEST0(dispatch_load_balancing ,Tload_balancing_t,argv,x); + + SELFTEST4(table_dispatch ,bool ,argv,x,nb_ooo_engine,nb_inst_issue[it1],nb_execute_loop,nb_read_unit[it3]); + SELFTEST2(translate_ooo_engine_num_front_end ,uint32_t ,argv,x,nb_ooo_engine,ooo_engine_nb_front_end[it1]); + SELFTEST2(translate_ooo_engine_num_execute_loop,uint32_t ,argv,x,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); + SELFTEST2(translate_execute_loop_num_ooo_engine,uint32_t ,argv,x,nb_execute_loop,execute_loop_nb_ooo_engine[it1]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::core_glue::Parameters * param = new morpheo::behavioural::core::core_glue::Parameters + ( + nb_front_end , + nb_context ,//[nb_front_end] + nb_ooo_engine , + nb_execute_loop , + ooo_engine_nb_front_end ,//[nb_ooo_engine] + ooo_engine_nb_execute_loop ,//[nb_ooo_engine] + execute_loop_nb_ooo_engine ,//[nb_execute_loop] + nb_inst_decod ,//[nb_front_end] + front_end_nb_inst_branch_complete ,//[nb_front_end] + ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] + nb_inst_insert ,//[nb_ooo_engine] + nb_inst_issue ,//[nb_ooo_engine] + nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + nb_read_unit ,//[nb_execute_loop] + nb_write_unit ,//[nb_execute_loop] + size_depth , + size_rob_ptr , + size_load_queue_ptr , + size_store_queue_ptr , + size_general_data , + size_special_data , + size_general_register , + size_special_register , + dispatch_priority , + dispatch_load_balancing , + table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] + translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] + translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + translate_execute_loop_num_ooo_engine,//[nb_execute_loop][execute_loop_nb_ooo_engine] + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Core_Glue : no error"); + else + TEST_KO("Core_Glue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + DELETE2(translate_execute_loop_num_ooo_engine,nb_execute_loop,execute_loop_nb_ooo_engine[it1]); + DELETE2(translate_ooo_engine_num_execute_loop,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); + DELETE2(translate_ooo_engine_num_front_end ,nb_ooo_engine,ooo_engine_nb_front_end[it1]); + DELETE4(table_dispatch ,nb_ooo_engine,nb_inst_issue[it1],nb_execute_loop,nb_read_unit[it2]); + DELETE1(nb_write_unit ,nb_execute_loop); + DELETE1(nb_read_unit ,nb_execute_loop); + DELETE2(nb_inst_execute ,nb_ooo_engine,ooo_engine_nb_execute_loop[it1]); + DELETE1(nb_inst_issue ,nb_ooo_engine); + DELETE1(ooo_engine_nb_inst_branch_complete ,nb_ooo_engine); + DELETE1(front_end_nb_inst_branch_complete ,nb_front_end); + DELETE1(nb_inst_decod ,nb_front_end); + DELETE1(execute_loop_nb_ooo_engine ,nb_execute_loop); + DELETE1(ooo_engine_nb_execute_loop ,nb_ooo_engine); + DELETE1(ooo_engine_nb_front_end ,nb_ooo_engine); + DELETE1(nb_context ,nb_front_end); + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,794 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Core_Glue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/BitManipulation.h" + +void test (string name, + morpheo::behavioural::core::core_glue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Core_Glue * _Core_Glue = new Core_Glue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL(out_RENAME_FRONT_END_ID ,"out_RENAME_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_VAL ,"out_BRANCH_COMPLETE_FRONT_END_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_ACK ," in_BRANCH_COMPLETE_FRONT_END_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ,"out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,"out_BRANCH_COMPLETE_FRONT_END_DEPTH ",Tdepth_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,"out_BRANCH_COMPLETE_FRONT_END_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,"out_BRANCH_COMPLETE_FRONT_END_FLAG ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ," in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ," in_BRANCH_COMPLETE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_ACK ,"out_BRANCH_COMPLETE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ," in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ," in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ," in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ," in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ," in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL ,"out_COMMIT_EVENT_FRONT_END_VAL ",Tcontrol_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_FRONT_END_ACK ," in_COMMIT_EVENT_FRONT_END_ACK ",Tcontrol_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ,"out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_DEPTH ,"out_COMMIT_EVENT_FRONT_END_DEPTH ",Tdepth_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_TYPE ,"out_COMMIT_EVENT_FRONT_END_TYPE ",Tevent_type_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"out_COMMIT_EVENT_FRONT_END_ADDRESS ",Taddress_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ",Taddress_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ",Taddress_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_VAL ," in_COMMIT_EVENT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_OOO_ENGINE_ACK ,"out_COMMIT_EVENT_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ," in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ," in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_DEPTH ," in_COMMIT_EVENT_OOO_ENGINE_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_TYPE ," in_COMMIT_EVENT_OOO_ENGINE_TYPE ",Tevent_type_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ," in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",Taddress_t ,_param->_nb_ooo_engine); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ," in_ISSUE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,"out_ISSUE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ," in_ISSUE_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ," in_ISSUE_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ," in_ISSUE_OOO_ENGINE_PACKET_ID ",Tpacket_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ," in_ISSUE_OOO_ENGINE_TYPE ",Ttype_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ," in_ISSUE_OOO_ENGINE_OPERATION ",Toperation_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ," in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ," in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ," in_ISSUE_OOO_ENGINE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ," in_ISSUE_OOO_ENGINE_READ_RA ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ," in_ISSUE_OOO_ENGINE_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ," in_ISSUE_OOO_ENGINE_READ_RB ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ," in_ISSUE_OOO_ENGINE_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ," in_ISSUE_OOO_ENGINE_READ_RC ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ," in_ISSUE_OOO_ENGINE_NUM_REG_RC ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ," in_ISSUE_OOO_ENGINE_WRITE_RD ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ," in_ISSUE_OOO_ENGINE_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ," in_ISSUE_OOO_ENGINE_WRITE_RE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ," in_ISSUE_OOO_ENGINE_NUM_REG_RE ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,"out_ISSUE_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_EXECUTE_LOOP_ACK ," in_ISSUE_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ,"out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ,"out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ,"out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_PACKET_ID ,"out_ISSUE_EXECUTE_LOOP_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_OPERATION ,"out_ISSUE_EXECUTE_LOOP_OPERATION ",Toperation_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE ,"out_ISSUE_EXECUTE_LOOP_TYPE ",Ttype_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ,"out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ,"out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ,"out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_IMMEDIAT ,"out_ISSUE_EXECUTE_LOOP_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RA ,"out_ISSUE_EXECUTE_LOOP_READ_RA ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ,"out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RB ,"out_ISSUE_EXECUTE_LOOP_READ_RB ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ,"out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RC ,"out_ISSUE_EXECUTE_LOOP_READ_RC ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ,"out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ",Tspecial_address_t,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RD ,"out_ISSUE_EXECUTE_LOOP_WRITE_RD ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ,"out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RE ,"out_ISSUE_EXECUTE_LOOP_WRITE_RE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,"out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ",Tspecial_address_t,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_VAL ,"out_EXECUTE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL( in_EXECUTE_OOO_ENGINE_ACK ," in_EXECUTE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_FRONT_END_ID ,"out_EXECUTE_OOO_ENGINE_FRONT_END_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_CONTEXT_ID ,"out_EXECUTE_OOO_ENGINE_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_PACKET_ID ,"out_EXECUTE_OOO_ENGINE_PACKET_ID ",Tpacket_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_TYPE ,"out_EXECUTE_OOO_ENGINE_TYPE ",Ttype_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_OPERATION ,"out_EXECUTE_OOO_ENGINE_OPERATION ",Toperation_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_FLAGS ,"out_EXECUTE_OOO_ENGINE_FLAGS ",Tspecial_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"out_EXECUTE_OOO_ENGINE_EXCEPTION ",Texception_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,"out_EXECUTE_OOO_ENGINE_ADDRESS ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_DATA ,"out_EXECUTE_OOO_ENGINE_DATA ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_VAL ," in_EXECUTE_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_EXECUTE_LOOP_ACK ,"out_EXECUTE_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ," in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ," in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ," in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_PACKET_ID ," in_EXECUTE_EXECUTE_LOOP_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OPERATION ," in_EXECUTE_EXECUTE_LOOP_OPERATION ",Toperation_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_TYPE ," in_EXECUTE_EXECUTE_LOOP_TYPE ",Ttype_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FLAGS ," in_EXECUTE_EXECUTE_LOOP_FLAGS ",Tspecial_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_EXECUTE_LOOP_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_DATA ," in_EXECUTE_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_VAL ," in_INSERT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_OOO_ENGINE_ACK ,"out_INSERT_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RD_USE ," in_INSERT_OOO_ENGINE_RD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RD_NUM_REG ," in_INSERT_OOO_ENGINE_RD_NUM_REG ",Tgeneral_address_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RE_USE ," in_INSERT_OOO_ENGINE_RE_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RE_NUM_REG ," in_INSERT_OOO_ENGINE_RE_NUM_REG ",Tspecial_address_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_VAL ,"out_INSERT_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + ALLOC3_SC_SIGNAL( in_INSERT_EXECUTE_LOOP_ACK ," in_INSERT_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_USE ,"out_INSERT_EXECUTE_LOOP_RD_USE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_NUM_REG ,"out_INSERT_EXECUTE_LOOP_RD_NUM_REG ",Tgeneral_address_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_USE ,"out_INSERT_EXECUTE_LOOP_RE_USE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + ALLOC3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_NUM_REG ,"out_INSERT_EXECUTE_LOOP_RE_NUM_REG ",Tspecial_address_t ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Core_Glue.\n"),name.c_str()); + + (*(_Core_Glue->in_CLOCK)) (*(in_CLOCK)); + (*(_Core_Glue->in_NRESET)) (*(in_NRESET)); + + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_VAL ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_FRONT_END_ACK ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_VAL ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_FRONT_END_ACK ,_param->_nb_front_end); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ,_param->_nb_front_end); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_DEPTH ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_TYPE ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,_param->_nb_front_end); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Core_Glue, in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + if (_param->_have_port_rob_ptr) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_ISSUE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + if (_param->_have_port_ooo_engine_id) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + if (_param->_have_port_rob_ptr) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_READ_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_READ_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_READ_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_WRITE_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_WRITE_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue, in_EXECUTE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + if (_param->_have_port_front_end_id) + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + if (_param->_have_port_context_id) + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + if (_param->_have_port_rob_ptr) + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_FLAGS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_EXCEPTION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_EXECUTE_OOO_ENGINE_DATA ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_EXECUTE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + if (_param->_have_port_ooo_engine_id) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + if (_param->_have_port_rob_ptr) + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_EXECUTE_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_INSERT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_INSERT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_INSERT_OOO_ENGINE_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_INSERT_OOO_ENGINE_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_INSERT_OOO_ENGINE_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_INSERT_OOO_ENGINE_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_INSERT_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue, in_INSERT_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_INSERT_EXECUTE_LOOP_RD_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_INSERT_EXECUTE_LOOP_RD_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_INSERT_EXECUTE_LOOP_RE_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + INSTANCE3_SC_SIGNAL(_Core_Glue,out_INSERT_EXECUTE_LOOP_RE_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Test RENAME_FRONT_END_ID"); + if (_param->_have_port_front_end_id) + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod [i]; ++j) + { + Tcontext_t id = out_RENAME_FRONT_END_ID [i][j]->read(); + bool find = false; + + for (uint32_t x=0; x<_param->_nb_ooo_engine; ++x) + if ((id < _param->_ooo_engine_nb_front_end [x]) and // Valid value + (_param->_translate_ooo_engine_num_front_end [x][id] == i)) // Correctness of translation + find = true; + TEST(bool,find,true); + } + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_front_end_nb_inst_branch_complete[i]; ++j) + { + in_BRANCH_COMPLETE_FRONT_END_ACK [i][j]->write(rand()%2); + in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [i][j]->write(rand()%2); + } + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + { + Tcontext_t front_end_id = rand() % _param->_ooo_engine_nb_front_end [i]; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end[i][front_end_id]; + Tcontext_t context_id = rand() % _param->_nb_context[num_front_end]; + + LABEL("BRANCH_COMPLETE_OOO_ENGINE [%d][%d]",i,j); + LABEL(" * front_end : id %d, num %d",front_end_id,num_front_end); + LABEL(" * context : id %d" ,context_id); + + in_BRANCH_COMPLETE_OOO_ENGINE_VAL [i][j]->write(rand()%2); + in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID [i][j]->write(range(front_end_id,_param->_size_front_end_id)); + in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID [i][j]->write(range(context_id ,_param->_size_context_id )); + in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j]->write(range(rand(),_param->_size_depth )); + in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j]->write(range(rand(),_param->_size_instruction_address)); + in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j]->write(rand()%2); + } + + //--------------------------------------------------------------------------------- + // COMMIT_EVENT : random input + //--------------------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + { + in_COMMIT_EVENT_FRONT_END_ACK [i]->write(rand()%2); + } + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + Tcontext_t front_end_id = rand() % _param->_ooo_engine_nb_front_end [i]; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end[i][front_end_id]; + Tcontext_t context_id = rand() % _param->_nb_context[num_front_end]; + + LABEL("COMMIT_EVENT_OOO_ENGINE [%d]",i); + LABEL(" * front_end : id %d, num %d",front_end_id,num_front_end); + LABEL(" * context : id %d" ,context_id); + + in_COMMIT_EVENT_OOO_ENGINE_VAL [i]->write(rand()%2); + in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID [i]->write(range(front_end_id,_param->_size_front_end_id)); + in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID [i]->write(range(context_id ,_param->_size_context_id )); + in_COMMIT_EVENT_OOO_ENGINE_DEPTH [i]->write(range(rand(),_param->_size_depth )); + in_COMMIT_EVENT_OOO_ENGINE_TYPE [i]->write(range(rand(),_param->_size_event_type)); + in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i]->write(rand()%2); + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i]->write(range(rand(),_param->_size_instruction_address)); + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i]->write(range(rand(),_param->_size_instruction_address)); + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL[i]->write(rand()%2); + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR [i]->write(range(rand(),_param->_size_instruction_address)); + } + + //--------------------------------------------------------------------------------- + // EXECUTE : random input + //--------------------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_execute_loop[i]; ++j) + for (uint32_t k=0; k<_param->_nb_inst_execute [i][j]; ++j) + in_EXECUTE_OOO_ENGINE_ACK [i][j][k]->write(rand()%2); + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + { + in_EXECUTE_EXECUTE_LOOP_VAL [i][j]->write(rand()%2); + + Tcontext_t ooo_engine_id = rand() % _param->_execute_loop_nb_ooo_engine [i]; + Tcontext_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine[i][ooo_engine_id]; + Tcontext_t front_end_id = rand() % _param->_ooo_engine_nb_front_end [num_ooo_engine]; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end[num_ooo_engine][front_end_id]; + Tcontext_t context_id = rand() % _param->_nb_context[num_front_end]; + + LABEL("EXECUTE_EXECUTE_LOOP [%d][%d]",i,j); + LABEL(" * ooo_engine : id %d, num %d",ooo_engine_id,num_ooo_engine); + LABEL(" * front_end : id %d, num %d",front_end_id,num_front_end); + LABEL(" * context : id %d" ,context_id); + + in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID [i][j]->write(range(front_end_id ,_param->_size_front_end_id )); + in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID [i][j]->write(range(context_id ,_param->_size_context_id )); + in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j]->write(range(ooo_engine_id,_param->_size_ooo_engine_id )); + in_EXECUTE_EXECUTE_LOOP_PACKET_ID [i][j]->write(range(rand(),_param->_size_rob_ptr )); +// in_EXECUTE_EXECUTE_LOOP_OPERATION [i][j]->write(range(rand(),_param->_size_operation )); +// in_EXECUTE_EXECUTE_LOOP_TYPE [i][j]->write(range(rand(),_param->_size_type )); + in_EXECUTE_EXECUTE_LOOP_FLAGS [i][j]->write(range(rand(),_param->_size_special_data )); + in_EXECUTE_EXECUTE_LOOP_EXCEPTION [i][j]->write(range(rand(),_param->_size_exception )); + in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE [i][j]->write(rand()%2); + in_EXECUTE_EXECUTE_LOOP_ADDRESS [i][j]->write(range(rand(),_param->_size_general_data )); + in_EXECUTE_EXECUTE_LOOP_DATA [i][j]->write(range(rand(),_param->_size_general_data )); + } + + //--------------------------------------------------------------------------------- + // ISSUE : random input + //--------------------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + in_ISSUE_EXECUTE_LOOP_ACK [i][j]->write(rand()%2); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) + { + Tcontext_t front_end_id = rand() % _param->_ooo_engine_nb_front_end [i]; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end[i][front_end_id]; + Tcontext_t context_id = rand() % _param->_nb_context[num_front_end]; + + LABEL("ISSUE_OOO_ENGINE [%d][%d]",i,j); + LABEL(" * front_end : id %d, num %d",front_end_id,num_front_end); + LABEL(" * context : id %d" ,context_id); + + in_ISSUE_OOO_ENGINE_VAL [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_FRONT_END_ID [i][j]->write(range(front_end_id ,_param->_size_front_end_id )); + in_ISSUE_OOO_ENGINE_CONTEXT_ID [i][j]->write(range(context_id ,_param->_size_context_id )); + in_ISSUE_OOO_ENGINE_PACKET_ID [i][j]->write(range(rand(),_param->_size_rob_ptr )); + in_ISSUE_OOO_ENGINE_TYPE [i][j]->write(range(rand(),_param->_size_operation )); + in_ISSUE_OOO_ENGINE_OPERATION [i][j]->write(range(rand(),_param->_size_type )); + in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [i][j]->write(range(rand(),_param->_size_store_queue_ptr )); + in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [i][j]->write(range(rand(),_param->_size_load_queue_ptr )); + in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_IMMEDIAT [i][j]->write(i|(j<<_param->_size_ooo_engine_id)); + in_ISSUE_OOO_ENGINE_READ_RA [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_NUM_REG_RA [i][j]->write(range(rand(),_param->_size_general_register)); + in_ISSUE_OOO_ENGINE_READ_RB [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_NUM_REG_RB [i][j]->write(range(rand(),_param->_size_general_register)); + in_ISSUE_OOO_ENGINE_READ_RC [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_NUM_REG_RC [i][j]->write(range(rand(),_param->_size_special_register)); + in_ISSUE_OOO_ENGINE_WRITE_RD [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_NUM_REG_RD [i][j]->write(range(rand(),_param->_size_general_register)); + in_ISSUE_OOO_ENGINE_WRITE_RE [i][j]->write(rand()%2); + in_ISSUE_OOO_ENGINE_NUM_REG_RE [i][j]->write(range(rand(),_param->_size_special_register)); + } + + //================================================================================= + // TEST + //================================================================================= + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + { + uint32_t id= in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID [i][j]->read(); + uint32_t x = _param->_translate_ooo_engine_num_front_end[i][id]; + + TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_VAL [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_VAL [i][j]->read()); + TEST(Tcontext_t,out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID [i][j]->read()); + TEST(Tdepth_t ,out_BRANCH_COMPLETE_FRONT_END_DEPTH [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j]->read()); + TEST(Taddress_t,out_BRANCH_COMPLETE_FRONT_END_ADDRESS [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j]->read()); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_FLAG [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j]->read()); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j]->read(), + in_BRANCH_COMPLETE_FRONT_END_ACK [x][j]->read()); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION [i][j]->read(), + in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [x][j]->read()); + } + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + uint32_t id= in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID [i]->read(); + uint32_t x = _param->_translate_ooo_engine_num_front_end[i][id]; + + + TEST(Tcontrol_t,out_COMMIT_EVENT_FRONT_END_VAL [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_VAL [i]->read()); + TEST(Tcontext_t,out_COMMIT_EVENT_FRONT_END_CONTEXT_ID [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID [i]->read()); + TEST(Tdepth_t ,out_COMMIT_EVENT_FRONT_END_DEPTH [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_DEPTH [i]->read()); + TEST(Tcontrol_t,out_COMMIT_EVENT_OOO_ENGINE_ACK [i]->read(), + in_COMMIT_EVENT_FRONT_END_ACK [x]->read()); + + TEST(Tevent_type_t,out_COMMIT_EVENT_FRONT_END_TYPE [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_TYPE [i]->read()); + TEST(Tcontrol_t ,out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i]->read()); + TEST(Taddress_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i]->read()); + TEST(Taddress_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i]->read()); + TEST(Tcontrol_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL[i]->read()); + TEST(Taddress_t ,out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR [x]->read(), + in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR [i]->read()); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + { + Tcontext_t id = in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j]->read(); + Tcontext_t x = _param->_translate_execute_loop_num_ooo_engine[i][id]; + Tcontext_t y = _param->_translate_num_execute_loop_to_ooo_engine_execute_loop_id[i][id]; + + TEST(Tcontrol_t ,out_EXECUTE_OOO_ENGINE_VAL [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_VAL [i][j]->read()); + TEST(Tcontext_t ,out_EXECUTE_OOO_ENGINE_FRONT_END_ID [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID [i][j]->read()); + TEST(Tcontext_t ,out_EXECUTE_OOO_ENGINE_CONTEXT_ID [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID [i][j]->read()); + TEST(Tpacket_t ,out_EXECUTE_OOO_ENGINE_PACKET_ID [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_PACKET_ID [i][j]->read()); +// TEST(Ttype_t ,out_EXECUTE_OOO_ENGINE_TYPE [x][y][j]->read(), +// in_EXECUTE_EXECUTE_LOOP_TYPE [i][j]->read()); +// TEST(Toperation_t ,out_EXECUTE_OOO_ENGINE_OPERATION [x][y][j]->read(), +// in_EXECUTE_EXECUTE_LOOP_OPERATION [i][j]->read()); + TEST(Tspecial_data_t,out_EXECUTE_OOO_ENGINE_FLAGS [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_FLAGS [i][j]->read()); + TEST(Texception_t ,out_EXECUTE_OOO_ENGINE_EXCEPTION [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_EXCEPTION [i][j]->read()); + TEST(Tcontrol_t ,out_EXECUTE_OOO_ENGINE_NO_SEQUENCE [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE [i][j]->read()); + TEST(Tgeneral_data_t,out_EXECUTE_OOO_ENGINE_ADDRESS [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_ADDRESS [i][j]->read()); + TEST(Tgeneral_data_t,out_EXECUTE_OOO_ENGINE_DATA [x][y][j]->read(), + in_EXECUTE_EXECUTE_LOOP_DATA [i][j]->read()); + TEST(Tcontrol_t ,out_EXECUTE_EXECUTE_LOOP_ACK [i][j]->read() , + in_EXECUTE_OOO_ENGINE_ACK [x][y][j]->read()); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + // Test transaction + if (out_ISSUE_EXECUTE_LOOP_VAL [i][j]->read() and + in_ISSUE_EXECUTE_LOOP_ACK [i][j]->read()) + { + Tgeneral_data_t imm = out_ISSUE_EXECUTE_LOOP_IMMEDIAT [i][j]->read(); + Tcontext_t x = range(imm,_param->_size_ooo_engine_id); + Tcontext_t y = imm>>_param->_size_ooo_engine_id; // port_issue + + LABEL("ISSUE - transaction"); + LABEL(" * execute_loop : %d",i); + LABEL(" * read_unit : %d",j); + LABEL(" * ooo_engine : %d",x); + LABEL(" * port_issue : %d",y); + + TEST(Tcontext_t,x,_param->_translate_execute_loop_num_ooo_engine[i][out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j]->read()]); + + TEST(bool,_param->_table_dispatch [x][y][i][j],true); + + TEST(Tcontrol_t , in_ISSUE_OOO_ENGINE_VAL [x][y]->read(),1); + TEST(Tcontrol_t ,out_ISSUE_OOO_ENGINE_ACK [x][y]->read(),1); + + TEST(Tcontext_t ,out_ISSUE_EXECUTE_LOOP_FRONT_END_ID [i][j]->read(), + in_ISSUE_OOO_ENGINE_FRONT_END_ID [x][y]->read()); + TEST(Tcontext_t ,out_ISSUE_EXECUTE_LOOP_CONTEXT_ID [i][j]->read(), + in_ISSUE_OOO_ENGINE_CONTEXT_ID [x][y]->read()); + TEST(Tpacket_t ,out_ISSUE_EXECUTE_LOOP_PACKET_ID [i][j]->read(), + in_ISSUE_OOO_ENGINE_PACKET_ID [x][y]->read()); + TEST(Ttype_t ,out_ISSUE_EXECUTE_LOOP_TYPE [i][j]->read(), + in_ISSUE_OOO_ENGINE_TYPE [x][y]->read()); + TEST(Toperation_t ,out_ISSUE_EXECUTE_LOOP_OPERATION [i][j]->read(), + in_ISSUE_OOO_ENGINE_OPERATION [x][y]->read()); + TEST(Tlsq_ptr_t ,out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [i][j]->read(), + in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [x][y]->read()); + TEST(Tlsq_ptr_t ,out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE [i][j]->read(), + in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT [i][j]->read(), + in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [x][y]->read()); + TEST(Tgeneral_data_t ,out_ISSUE_EXECUTE_LOOP_IMMEDIAT [i][j]->read(), + in_ISSUE_OOO_ENGINE_IMMEDIAT [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_READ_RA [i][j]->read(), + in_ISSUE_OOO_ENGINE_READ_RA [x][y]->read()); + TEST(Tgeneral_address_t,out_ISSUE_EXECUTE_LOOP_NUM_REG_RA [i][j]->read(), + in_ISSUE_OOO_ENGINE_NUM_REG_RA [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_READ_RB [i][j]->read(), + in_ISSUE_OOO_ENGINE_READ_RB [x][y]->read()); + TEST(Tgeneral_address_t,out_ISSUE_EXECUTE_LOOP_NUM_REG_RB [i][j]->read(), + in_ISSUE_OOO_ENGINE_NUM_REG_RB [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_READ_RC [i][j]->read(), + in_ISSUE_OOO_ENGINE_READ_RC [x][y]->read()); + TEST(Tspecial_address_t,out_ISSUE_EXECUTE_LOOP_NUM_REG_RC [i][j]->read(), + in_ISSUE_OOO_ENGINE_NUM_REG_RC [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_WRITE_RD [i][j]->read(), + in_ISSUE_OOO_ENGINE_WRITE_RD [x][y]->read()); + TEST(Tgeneral_address_t,out_ISSUE_EXECUTE_LOOP_NUM_REG_RD [i][j]->read(), + in_ISSUE_OOO_ENGINE_NUM_REG_RD [x][y]->read()); + TEST(Tcontrol_t ,out_ISSUE_EXECUTE_LOOP_WRITE_RE [i][j]->read(), + in_ISSUE_OOO_ENGINE_WRITE_RE [x][y]->read()); + TEST(Tspecial_address_t,out_ISSUE_EXECUTE_LOOP_NUM_REG_RE [i][j]->read(), + in_ISSUE_OOO_ENGINE_NUM_REG_RE [x][y]->read()); + } + + SC_START(1); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL(out_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_VAL ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_ACK ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL ,_param->_nb_front_end); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_FRONT_END_ACK ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_DEPTH ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_TYPE ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,_param->_nb_front_end); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL(out_COMMIT_EVENT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL( in_EXECUTE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +//DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_FLAGS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_EXCEPTION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_DATA ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OOO_ENGINE_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + DELETE3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + DELETE3_SC_SIGNAL( in_INSERT_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + DELETE3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + DELETE3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + DELETE3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + DELETE3_SC_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + } +#endif + + delete _Core_Glue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Core_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Core_Glue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Core_Glue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Core_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 88) @@ -0,0 +1,271 @@ +#ifndef morpheo_behavioural_core_core_glue_Core_Glue_h +#define morpheo_behavioural_core_core_glue_Core_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Core_Glue/include/Parameters.h" +#include "Behavioural/Core/Core_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +#include "Behavioural/Generic/Priority/include/Priority.h" + + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace core_glue { + + + class Core_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontext_t ) *** out_RENAME_FRONT_END_ID ;//[nb_front_end][nb_inst_decod] + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_FRONT_END_VAL ;//[nb_front_end][nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_FRONT_END_ACK ;//[nb_front_end][nb_inst_branch_complete] + public : SC_OUT(Tcontext_t ) *** out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ;//[nb_front_end][nb_inst_branch_complete] + public : SC_OUT(Tdepth_t ) *** out_BRANCH_COMPLETE_FRONT_END_DEPTH ;//[nb_front_end][nb_inst_branch_complete] + public : SC_OUT(Taddress_t ) *** out_BRANCH_COMPLETE_FRONT_END_ADDRESS ;//[nb_front_end][nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_FRONT_END_FLAG ;//[nb_front_end][nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ;//[nb_front_end][nb_inst_branch_complete] + + public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_VAL ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_OOO_ENGINE_ACK ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Tcontext_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Tcontext_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Tdepth_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Taddress_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION;//[nb_ooo_engine][nb_inst_branch_complete] + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_VAL ;//[nb_front_end] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_FRONT_END_ACK ;//[nb_front_end] + public : SC_OUT(Tcontext_t ) ** out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ;//[nb_front_end] + public : SC_OUT(Tdepth_t ) ** out_COMMIT_EVENT_FRONT_END_DEPTH ;//[nb_front_end] + public : SC_OUT(Tevent_type_t ) ** out_COMMIT_EVENT_FRONT_END_TYPE ;//[nb_front_end] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ;//[nb_front_end] + public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS ;//[nb_front_end] + public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ;//[nb_front_end] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ;//[nb_front_end] + public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ;//[nb_front_end] + + public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_VAL ;//[nb_ooo_engine] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_OOO_ENGINE_ACK ;//[nb_ooo_engine] + public : SC_IN (Tcontext_t ) ** in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ;//[nb_ooo_engine] + public : SC_IN (Tcontext_t ) ** in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ;//[nb_ooo_engine] + public : SC_IN (Tdepth_t ) ** in_COMMIT_EVENT_OOO_ENGINE_DEPTH ;//[nb_ooo_engine] + public : SC_IN (Tevent_type_t ) ** in_COMMIT_EVENT_OOO_ENGINE_TYPE ;//[nb_ooo_engine] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ;//[nb_ooo_engine] + public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine] + public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ;//[nb_ooo_engine] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ;//[nb_ooo_engine] + public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ;//[nb_ooo_engine] + + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_VAL ;//[nb_ooo_engine][nb_inst_issue] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_OOO_ENGINE_ACK ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontext_t ) *** in_ISSUE_OOO_ENGINE_FRONT_END_ID ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontext_t ) *** in_ISSUE_OOO_ENGINE_CONTEXT_ID ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tpacket_t ) *** in_ISSUE_OOO_ENGINE_PACKET_ID ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Ttype_t ) *** in_ISSUE_OOO_ENGINE_TYPE ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Toperation_t ) *** in_ISSUE_OOO_ENGINE_OPERATION ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tlsq_ptr_t ) *** in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tlsq_ptr_t ) *** in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tgeneral_data_t ) *** in_ISSUE_OOO_ENGINE_IMMEDIAT ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_READ_RA ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_OOO_ENGINE_NUM_REG_RA ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_READ_RB ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_OOO_ENGINE_NUM_REG_RB ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_READ_RC ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tspecial_address_t) *** in_ISSUE_OOO_ENGINE_NUM_REG_RC ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_WRITE_RD ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_OOO_ENGINE_NUM_REG_RD ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_OOO_ENGINE_WRITE_RE ;//[nb_ooo_engine][nb_inst_issue] + public : SC_IN (Tspecial_address_t) *** in_ISSUE_OOO_ENGINE_NUM_REG_RE ;//[nb_ooo_engine][nb_inst_issue] + + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_VAL ;//[nb_execute_loop][nb_read_unit] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_EXECUTE_LOOP_ACK ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontext_t ) *** out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontext_t ) *** out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontext_t ) *** out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tpacket_t ) *** out_ISSUE_EXECUTE_LOOP_PACKET_ID ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Toperation_t ) *** out_ISSUE_EXECUTE_LOOP_OPERATION ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Ttype_t ) *** out_ISSUE_EXECUTE_LOOP_TYPE ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tlsq_ptr_t ) *** out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tlsq_ptr_t ) *** out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tgeneral_data_t ) *** out_ISSUE_EXECUTE_LOOP_IMMEDIAT ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_READ_RA ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tgeneral_address_t) *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_READ_RB ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tgeneral_address_t) *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_READ_RC ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tspecial_address_t) *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_WRITE_RD ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tgeneral_address_t) *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_EXECUTE_LOOP_WRITE_RE ;//[nb_execute_loop][nb_read_unit] + public : SC_OUT(Tspecial_address_t) *** out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ;//[nb_execute_loop][nb_read_unit] + + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) **** out_EXECUTE_OOO_ENGINE_VAL ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontrol_t ) **** in_EXECUTE_OOO_ENGINE_ACK ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tcontext_t ) **** out_EXECUTE_OOO_ENGINE_FRONT_END_ID ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tcontext_t ) **** out_EXECUTE_OOO_ENGINE_CONTEXT_ID ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tpacket_t ) **** out_EXECUTE_OOO_ENGINE_PACKET_ID ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] +//public : SC_OUT(Ttype_t ) **** out_EXECUTE_OOO_ENGINE_TYPE ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] +//public : SC_OUT(Toperation_t ) **** out_EXECUTE_OOO_ENGINE_OPERATION ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tspecial_data_t ) **** out_EXECUTE_OOO_ENGINE_FLAGS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Texception_t ) **** out_EXECUTE_OOO_ENGINE_EXCEPTION ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tcontrol_t ) **** out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tgeneral_data_t ) **** out_EXECUTE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tgeneral_data_t ) **** out_EXECUTE_OOO_ENGINE_DATA ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_EXECUTE_LOOP_VAL ;//[nb_execute_loop][nb_write_unit] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_EXECUTE_LOOP_ACK ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tpacket_t ) *** in_EXECUTE_EXECUTE_LOOP_PACKET_ID ;//[nb_execute_loop][nb_write_unit] +//public : SC_IN (Toperation_t ) *** in_EXECUTE_EXECUTE_LOOP_OPERATION ;//[nb_execute_loop][nb_write_unit] +//public : SC_IN (Ttype_t ) *** in_EXECUTE_EXECUTE_LOOP_TYPE ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tspecial_data_t ) *** in_EXECUTE_EXECUTE_LOOP_FLAGS ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Texception_t ) *** in_EXECUTE_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_write_unit] + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_INSERT_OOO_ENGINE_VAL ;//[nb_ooo_engine][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_OOO_ENGINE_ACK ;//[nb_ooo_engine][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_OOO_ENGINE_RD_USE ;//[nb_ooo_engine][nb_inst_insert] + public : SC_IN (Tgeneral_address_t) *** in_INSERT_OOO_ENGINE_RD_NUM_REG ;//[nb_ooo_engine][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_OOO_ENGINE_RE_USE ;//[nb_ooo_engine][nb_inst_insert] + public : SC_IN (Tspecial_address_t) *** in_INSERT_OOO_ENGINE_RE_NUM_REG ;//[nb_ooo_engine][nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) **** out_INSERT_EXECUTE_LOOP_VAL ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + public : SC_IN (Tcontrol_t ) **** in_INSERT_EXECUTE_LOOP_ACK ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + public : SC_OUT(Tcontrol_t ) **** out_INSERT_EXECUTE_LOOP_RD_USE ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) **** out_INSERT_EXECUTE_LOOP_RD_NUM_REG ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + public : SC_OUT(Tcontrol_t ) **** out_INSERT_EXECUTE_LOOP_RE_USE ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + public : SC_OUT(Tspecial_address_t) **** out_INSERT_EXECUTE_LOOP_RE_NUM_REG ;//[nb_execute_loop][execute_loop_nb_ooo_engine][execute_loop_nb_inst_insert] + + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority ** _priority; //[nb_execute_loop] + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Core_Glue); +#endif + public : Core_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Core_Glue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_branch_complete (void); + public : void genMealy_commit_event (void); + public : void genMealy_issue (void); + public : void genMealy_execute (void); + public : void genMealy_insert (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Parameters.h (revision 88) @@ -0,0 +1,126 @@ +#ifndef morpheo_behavioural_core_core_glue_Parameters_h +#define morpheo_behavioural_core_core_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_execute_loop ; + public : uint32_t * _ooo_engine_nb_front_end ;//[nb_ooo_engine] + public : uint32_t * _ooo_engine_nb_execute_loop ;//[nb_ooo_engine] + public : uint32_t * _execute_loop_nb_ooo_engine ;//[nb_execute_loop] + public : uint32_t * _nb_inst_decod ;//[nb_front_end] -> [sum_inst_decod] + public : uint32_t * _front_end_nb_inst_branch_complete ;//[nb_front_end] + public : uint32_t * _ooo_engine_nb_inst_branch_complete ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_insert ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_issue ;//[nb_ooo_engine] + public : uint32_t ** _nb_inst_execute ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] + public : uint32_t * _nb_read_unit ;//[nb_execute_loop] + public : uint32_t * _nb_write_unit ;//[nb_execute_loop] +//public : uint32_t _size_depth ; +//public : uint32_t _size_rob_ptr ; +//public : uint32_t _size_load_queue_ptr ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_ooo_engine_id ; + public : Tpriority_t _dispatch_priority ; + public : Tload_balancing_t _dispatch_load_balancing ; + public : bool **** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] + public : uint32_t ** _translate_ooo_engine_num_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] + public : uint32_t ** _translate_ooo_engine_num_execute_loop;//[nb_ooo_engine][ooo_engine_nb_execute_loop] + public : uint32_t ** _translate_execute_loop_num_ooo_engine;//[nb_execute_loop][execute_loop_nb_ooo_engine] + + public : uint32_t * _link_ooo_engine_with_front_end ;//[nb_front_end] + public : uint32_t * _translate_num_front_end_to_ooo_engine_front_end_id ;//[nb_front_end] + + public : uint32_t ** _translate_num_execute_loop_to_ooo_engine_execute_loop_id;//[nb_execute_loop][execute_loop_nb_ooo_engine] + + public : uint32_t ** _execute_loop_nb_inst_insert ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + public : uint32_t ** _execute_loop_nb_inst_issue ;//[nb_execute_loop][execute_loop_nb_ooo_engine] +//public : uint32_t * _link_execute_loop_with_ooo_engine ;//[nb_ooo_engine] + + public : uint32_t _max_ooo_engine_nb_inst_branch_complete; + public : uint32_t _max_front_end_nb_inst_branch_complete ; + public : uint32_t _max_ooo_engine_nb_execute_loop ; + public : uint32_t _max_nb_inst_execute ; + public : uint32_t _max_nb_write_unit ; + public : uint32_t _max_nb_inst_insert ; + public : uint32_t _max_nb_inst_issue ; + public : uint32_t _max_nb_read_unit ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters + (uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t nb_ooo_engine , + uint32_t nb_execute_loop , + uint32_t * ooo_engine_nb_front_end ,//[nb_ooo_engine] + uint32_t * ooo_engine_nb_execute_loop ,//[nb_ooo_engine] + uint32_t * execute_loop_nb_ooo_engine ,//[nb_execute_loop] + uint32_t * nb_inst_decod ,//[nb_front_end] -> [sum_inst_decod] + uint32_t * front_end_nb_inst_branch_complete ,//[nb_front_end] + uint32_t * ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] + uint32_t * nb_inst_insert ,//[nb_ooo_engine] + uint32_t * nb_inst_issue ,//[nb_ooo_engine] + uint32_t ** nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t * nb_read_unit ,//[nb_execute_loop] + uint32_t * nb_write_unit ,//[nb_execute_loop] + uint32_t size_depth , + uint32_t size_rob_ptr , + uint32_t size_load_queue_ptr , + uint32_t size_store_queue_ptr , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_general_register , + uint32_t size_special_register , + Tpriority_t dispatch_priority , + Tload_balancing_t dispatch_load_balancing , + bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] + uint32_t ** translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] + uint32_t ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t ** translate_execute_loop_num_ooo_engine,//[nb_execute_loop][execute_loop_nb_ooo_engine] + bool is_toplevel=false); + +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::core_glue::Parameters & x); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Types.h (revision 88) @@ -0,0 +1,25 @@ +#ifndef morpheo_behavioural_core_core_glue_Types_h +#define morpheo_behavioural_core_core_glue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp (revision 88) @@ -0,0 +1,281 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::Core_Glue" + Core_Glue::Core_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::core_glue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Core_Glue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Core_Glue == true + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Constant + if (_param->_have_port_front_end_id) + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod [i]; ++j) + PORT_WRITE(out_RENAME_FRONT_END_ID [i][j],_param->_translate_num_front_end_to_ooo_engine_front_end_id[i]); + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMealy_branch_complete"),_name.c_str()); + SC_METHOD (genMealy_branch_complete); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_front_end_nb_inst_branch_complete[i]; ++j) + sensitive << (*(in_BRANCH_COMPLETE_FRONT_END_ACK [i][j])) + << (*(in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [i][j])); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + { + sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_VAL [i][j])) + << (*(in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j])) + << (*(in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID [i][j])); + if (_param->_have_port_context_id) + sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID [i][j])); + if (_param->_have_port_depth) + sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j])); + } + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMealy_commit_event"),_name.c_str()); + SC_METHOD (genMealy_commit_event); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + sensitive << (*(in_COMMIT_EVENT_FRONT_END_ACK [i])); + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + sensitive << (*(in_COMMIT_EVENT_OOO_ENGINE_VAL [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_TYPE [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL [i])) + << (*(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR [i])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID [i])); + if (_param->_have_port_context_id) + sensitive << (*(in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID [i])); + if (_param->_have_port_depth) + sensitive << (*(in_COMMIT_EVENT_OOO_ENGINE_DEPTH [i])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMealy_issue"),_name.c_str()); + SC_METHOD (genMealy_issue); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_issue [i]; ++j) + { + sensitive << (*(in_ISSUE_OOO_ENGINE_VAL [i][j])) + << (*(in_ISSUE_OOO_ENGINE_TYPE [i][j])) + << (*(in_ISSUE_OOO_ENGINE_OPERATION [i][j])) + << (*(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [i][j])) + << (*(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [i][j])) + << (*(in_ISSUE_OOO_ENGINE_IMMEDIAT [i][j])) + << (*(in_ISSUE_OOO_ENGINE_READ_RA [i][j])) + << (*(in_ISSUE_OOO_ENGINE_NUM_REG_RA [i][j])) + << (*(in_ISSUE_OOO_ENGINE_READ_RB [i][j])) + << (*(in_ISSUE_OOO_ENGINE_NUM_REG_RB [i][j])) + << (*(in_ISSUE_OOO_ENGINE_READ_RC [i][j])) + << (*(in_ISSUE_OOO_ENGINE_NUM_REG_RC [i][j])) + << (*(in_ISSUE_OOO_ENGINE_WRITE_RD [i][j])) + << (*(in_ISSUE_OOO_ENGINE_NUM_REG_RD [i][j])) + << (*(in_ISSUE_OOO_ENGINE_WRITE_RE [i][j])) + << (*(in_ISSUE_OOO_ENGINE_NUM_REG_RE [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_ISSUE_OOO_ENGINE_FRONT_END_ID [i][j])); + if (_param->_have_port_context_id) + sensitive << (*(in_ISSUE_OOO_ENGINE_CONTEXT_ID [i][j])); + if (_param->_have_port_rob_ptr) + sensitive << (*(in_ISSUE_OOO_ENGINE_PACKET_ID [i][j])); + if (_param->_have_port_load_queue_ptr) + sensitive << (*(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [i][j])); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_read_unit [i]; ++j) + sensitive << (*(in_ISSUE_EXECUTE_LOOP_ACK [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMealy_execute"),_name.c_str()); + SC_METHOD (genMealy_execute); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_execute_loop[i]; ++j) + for (uint32_t k=0; k<_param->_nb_inst_execute[i][j]; ++k) + sensitive << (*(in_EXECUTE_OOO_ENGINE_ACK [i][j][k])); + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + { + sensitive << (*(in_EXECUTE_EXECUTE_LOOP_VAL [i][j])) +// << (*(in_EXECUTE_EXECUTE_LOOP_OPERATION [i][j])) +// << (*(in_EXECUTE_EXECUTE_LOOP_TYPE [i][j])) + << (*(in_EXECUTE_EXECUTE_LOOP_FLAGS [i][j])) + << (*(in_EXECUTE_EXECUTE_LOOP_EXCEPTION [i][j])) + << (*(in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE [i][j])) + << (*(in_EXECUTE_EXECUTE_LOOP_ADDRESS [i][j])) + << (*(in_EXECUTE_EXECUTE_LOOP_DATA [i][j])); + if (_param->_have_port_context_id) + sensitive << (*(in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID [i][j])); + if (_param->_have_port_ooo_engine_id) + sensitive << (*(in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j])); + if (_param->_have_port_rob_ptr) + sensitive << (*(in_EXECUTE_EXECUTE_LOOP_PACKET_ID [i][j])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Method - genMealy_insert"),_name.c_str()); + SC_METHOD (genMealy_insert); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) + sensitive << (*(in_INSERT_OOO_ENGINE_VAL [i][j])) + << (*(in_INSERT_OOO_ENGINE_RD_USE [i][j])) + << (*(in_INSERT_OOO_ENGINE_RD_NUM_REG [i][j])) + << (*(in_INSERT_OOO_ENGINE_RE_USE [i][j])) + << (*(in_INSERT_OOO_ENGINE_RE_NUM_REG [i][j])); + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_execute_loop_nb_ooo_engine[i]; ++j) + for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert[i][j]; ++k) + sensitive << (*(in_INSERT_EXECUTE_LOOP_ACK [i][j][k])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Core_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Core_Glue::~Core_Glue" + Core_Glue::~Core_Glue (void) + { + log_begin(Core_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 88) @@ -0,0 +1,258 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + + +#undef FUNCTION +#define FUNCTION "Core_Glue::allocation" + void Core_Glue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Core_Glue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Core_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("rename",SOUTH,OUT,_("Request between the decod unit and the rename unit"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + _ALLOC2_SIGNAL_OUT(out_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("branch_complete_front_end",SOUTH,OUT,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_FRONT_END_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_FLAG ,"FLAG" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + } + { + ALLOC2_INTERFACE("branch_complete_ooo_engine",SOUTH,IN ,_("Branch complete : request between commit unit and prediction unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,"FLAG" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + } + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("commit_event_front_end",SOUTH,OUT,_("Commit event : request between commit unit and context state"),_param->_nb_front_end); + + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_VAL ,"VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_FRONT_END_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_spr); + } + + { + ALLOC1_INTERFACE("commit_event_ooo_engine",SOUTH,IN ,_("Commit event : request between commit unit and context state"),_param->_nb_ooo_engine); + + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_spr); + } + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("issue_ooo_engine",SOUTH,IN ,_("Issue : request between rename unit and execute loop"),_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); + } + + { + ALLOC2_INTERFACE("issue_execute_loop",SOUTH,OUT,_("Issue : request between rename unit and execute loop"),_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_EXECUTE_LOOP_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_execute_loop,_param->_nb_read_unit[it1]); + } + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC3_INTERFACE("execute_ooo_engine",SOUTH,OUT,_("Execute : request between execute loop and commit unit"),_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_EXECUTE_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +// _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); +// _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_FLAGS ,"FLAGS" ,Tspecial_data_t ,_param->_size_special_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + } + + { + ALLOC2_INTERFACE("execute_execute_loop",SOUTH,IN ,_("Execute : request between execute loop and commit unit"),_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_EXECUTE_LOOP_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_FLAGS ,"FLAGS" ,Tspecial_data_t ,_param->_size_special_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("insert_ooo_engine",SOUTH,IN ,_("Insert"),_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + + _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_OOO_ENGINE_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RD_USE ,"RD_USE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RD_NUM_REG,"RD_NUM_REG",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_OOO_ENGINE_RE_NUM_REG,"RE_NUM_REG",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); + } + + { + ALLOC3_INTERFACE("insert_execute_loop",SOUTH,IN ,_("Insert"),_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + + _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_VAL ,"VAL" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_INSERT_EXECUTE_LOOP_ACK ,"ACK" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RD_USE ,"RD_USE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RD_NUM_REG,"RD_NUM_REG",Tgeneral_address_t,_param->_size_general_register,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_INSERT_EXECUTE_LOOP_RE_NUM_REG,"RE_NUM_REG",Tspecial_address_t,_param->_size_special_register,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority = new generic::priority::Priority * [_param->_nb_execute_loop]; + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + _priority [i] = new generic::priority::Priority (_name+"_priority_"+toString(i), + _param->_dispatch_priority , + _param->_dispatch_load_balancing, + _param->_execute_loop_nb_ooo_engine [i], + _param->_execute_loop_nb_inst_issue [i], + _param->_execute_loop_nb_ooo_engine [i] + ); + + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp (revision 88) @@ -0,0 +1,171 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::deallocation" + void Core_Glue::deallocation (void) + { + log_begin(Core_Glue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL(out_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_front_end_id); + + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_VAL ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_ACK ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],_param->_size_context_id); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],_param->_size_depth); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],_param->_size_instruction_address); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); + + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_front_end_id); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_context_id); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_depth); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_instruction_address); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); + + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL ,_param->_nb_front_end,1); + DELETE1_SIGNAL( in_COMMIT_EVENT_FRONT_END_ACK ,_param->_nb_front_end,1); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_CONTEXT_ID ,_param->_nb_front_end,_param->_size_context_id); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_size_depth); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_TYPE ,_param->_nb_front_end,_param->_size_event_type); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,_param->_nb_front_end,1); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_size_instruction_address); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,_param->_nb_front_end,_param->_size_spr); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,_param->_nb_front_end,1); + DELETE1_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,_param->_nb_front_end,_param->_size_spr); + + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,1); + DELETE1_SIGNAL(out_COMMIT_EVENT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,1); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_size_front_end_id); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_size_context_id); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_size_depth); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_size_event_type); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,_param->_nb_ooo_engine,1); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_size_instruction_address); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,_param->_nb_ooo_engine,_param->_size_spr); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine,1); + DELETE1_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,_param->_nb_ooo_engine,_param->_size_spr); + + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_front_end_id); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_context_id); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_rob_ptr); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_type); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_operation); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_store_queue_ptr); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_load_queue_ptr); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_IMMEDIAT ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_general_data); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RA ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RB ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_READ_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RC ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_special_register); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RD ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_WRITE_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],1); + DELETE2_SIGNAL( in_ISSUE_OOO_ENGINE_NUM_REG_RE ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1],_param->_size_special_register); + + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL( in_ISSUE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_context_id); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_front_end_id); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_ooo_engine_id); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_rob_ptr); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_operation); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_type); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_store_queue_ptr); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_load_queue_ptr); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_IMMEDIAT ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_general_data); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_READ_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_special_register); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_WRITE_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],1); + DELETE2_SIGNAL(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE ,_param->_nb_execute_loop,_param->_nb_read_unit[it1],_param->_size_special_register); + + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],1); + DELETE3_SIGNAL( in_EXECUTE_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],1); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_FRONT_END_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_front_end_id); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_context_id); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_PACKET_ID ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_rob_ptr); +// DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_TYPE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_type); +// DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_OPERATION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_operation); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_FLAGS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_special_data); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_EXCEPTION ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_exception); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],1); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_general_data); + DELETE3_SIGNAL(out_EXECUTE_OOO_ENGINE_DATA ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2],_param->_size_general_data); + + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],1); + DELETE2_SIGNAL(out_EXECUTE_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],1); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_context_id); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_front_end_id); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_ooo_engine_id); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_rob_ptr); +// DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_type); +// DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_operation); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_special_data); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_exception); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],1); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_general_data); + DELETE2_SIGNAL( in_EXECUTE_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_write_unit[it1],_param->_size_general_data); + + DELETE2_SIGNAL( in_INSERT_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_OOO_ENGINE_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_OOO_ENGINE_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_OOO_ENGINE_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_OOO_ENGINE_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_OOO_ENGINE_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1],_param->_size_special_register); + + DELETE3_SIGNAL(out_INSERT_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],1 ); + DELETE3_SIGNAL( in_INSERT_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],1 ); + DELETE3_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],1 ); + DELETE3_SIGNAL(out_INSERT_EXECUTE_LOOP_RD_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],_param->_size_general_register); + DELETE3_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_USE ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],1 ); + DELETE3_SIGNAL(out_INSERT_EXECUTE_LOOP_RE_NUM_REG ,_param->_nb_execute_loop,_param->_execute_loop_nb_ooo_engine[it1],_param->_execute_loop_nb_inst_insert[it1][it2],_param->_size_special_register); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + delete _priority [i]; + delete [] _priority; + + delete _component; + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_end_cycle.cpp (revision 88) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::end_cycle" +void Core_Glue::end_cycle () + { + log_begin(Core_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp (revision 88) @@ -0,0 +1,73 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::genMealy_branch_complete" + void Core_Glue::genMealy_branch_complete (void) + { + log_begin(Core_Glue,FUNCTION); + log_function(Core_Glue,FUNCTION,_name.c_str()); + + Tcontrol_t BRANCH_COMPLETE_FRONT_END_VAL [_param->_nb_front_end ][_param->_max_front_end_nb_inst_branch_complete ]; + Tcontrol_t BRANCH_COMPLETE_OOO_ENGINE_ACK [_param->_nb_ooo_engine][_param->_max_ooo_engine_nb_inst_branch_complete]; + + // init val/ack at 0 + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_front_end_nb_inst_branch_complete[i]; ++j) + BRANCH_COMPLETE_FRONT_END_VAL [i][j] = 0; + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j] = 0; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + { + // Take the ooo_engine.num_front_end and translate in core.num_front_end + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID [i][j]):0; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end [i][front_end_id]; + + // Warning : ooo_engine.nb_inst_branch_complete[i] = front_end.nb_inst_branch_complete[num_front_end] +// log_printf(TRACE,Core_Glue,FUNCTION," * [%d][%d] front_end_id %d, num_front_end %d",i,j,front_end_id,num_front_end); + + BRANCH_COMPLETE_FRONT_END_VAL [num_front_end][j] = PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_VAL [i][j]); + BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j] = PORT_READ(in_BRANCH_COMPLETE_FRONT_END_ACK [num_front_end][j]); + + if (_param->_have_port_context_id) + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID [i][j])); + if (_param->_have_port_depth) + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_DEPTH [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j])); + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ADDRESS [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j])); + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_FLAG [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j])); + PORT_WRITE(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION [i][j], PORT_READ(in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [num_front_end][j])); + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_front_end_nb_inst_branch_complete[i]; ++j) + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_VAL [i][j], BRANCH_COMPLETE_FRONT_END_VAL [i][j]); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_branch_complete[i]; ++j) + PORT_WRITE(out_BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j], BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j]); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_commit_event.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_commit_event.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_commit_event.cpp (revision 88) @@ -0,0 +1,72 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::genMealy_commit_event" + void Core_Glue::genMealy_commit_event (void) + { + log_begin(Core_Glue,FUNCTION); + log_function(Core_Glue,FUNCTION,_name.c_str()); + + Tcontrol_t COMMIT_EVENT_FRONT_END_VAL [_param->_nb_front_end ]; + Tcontrol_t COMMIT_EVENT_OOO_ENGINE_ACK [_param->_nb_ooo_engine]; + + // init val/ack at 0 + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + COMMIT_EVENT_FRONT_END_VAL [i] = 0; + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + COMMIT_EVENT_OOO_ENGINE_ACK [i] = 0; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + // Take the ooo_engine.num_front_end and translate in core.num_front_end + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID [i]):0; + Tcontext_t num_front_end = _param->_translate_ooo_engine_num_front_end [i][front_end_id]; + + // Warning : ooo_engine.nb_inst_commit_event[i] = front_end.nb_inst_commit_event[num_front_end] +// log_printf(TRACE,Core_Glue,FUNCTION," * [%d][%d] front_end_id %d, num_front_end %d",i,j,front_end_id,num_front_end); + + COMMIT_EVENT_FRONT_END_VAL [num_front_end] = PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_VAL [i]); + COMMIT_EVENT_OOO_ENGINE_ACK [i] = PORT_READ(in_COMMIT_EVENT_FRONT_END_ACK [num_front_end]); + + if (_param->_have_port_context_id) + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_CONTEXT_ID [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID [i])); + if (_param->_have_port_depth) + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_DEPTH [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_DEPTH [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_TYPE [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_TYPE [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL [i])); + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR [num_front_end], PORT_READ(in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR [i])); + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + PORT_WRITE(out_COMMIT_EVENT_FRONT_END_VAL [i], COMMIT_EVENT_FRONT_END_VAL [i]); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + PORT_WRITE(out_COMMIT_EVENT_OOO_ENGINE_ACK [i], COMMIT_EVENT_OOO_ENGINE_ACK [i]); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_execute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_execute.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_execute.cpp (revision 88) @@ -0,0 +1,79 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::genMealy_execute" + void Core_Glue::genMealy_execute (void) + { + log_begin(Core_Glue,FUNCTION); + log_function(Core_Glue,FUNCTION,_name.c_str()); + + Tcontrol_t EXECUTE_OOO_ENGINE_VAL [_param->_nb_ooo_engine][_param->_max_ooo_engine_nb_execute_loop][_param->_max_nb_inst_execute]; + Tcontrol_t EXECUTE_EXECUTE_LOOP_ACK [_param->_nb_execute_loop][_param->_max_nb_write_unit]; + + // init + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_execute_loop[i]; ++j) + for (uint32_t k=0; k<_param->_nb_inst_execute[i][j];++k) + EXECUTE_OOO_ENGINE_VAL [i][j][k] = 0; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + EXECUTE_EXECUTE_LOOP_ACK [i][j] = 0; + + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + { + // Take the execute_loop.num_front_end and translate in core.num_ooo_engine + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j]):0; + Tcontext_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine [i][ooo_engine_id]; + Tcontext_t num_execute_loop = _param->_translate_num_execute_loop_to_ooo_engine_execute_loop_id [i][ooo_engine_id]; + + EXECUTE_OOO_ENGINE_VAL [num_ooo_engine][num_execute_loop][j] = PORT_READ(in_EXECUTE_EXECUTE_LOOP_VAL [i][j]); + EXECUTE_EXECUTE_LOOP_ACK [i][j] = PORT_READ(in_EXECUTE_OOO_ENGINE_ACK [num_ooo_engine][num_execute_loop][j]); + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_EXECUTE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID [i][j])); + if (_param->_have_port_context_id) + PORT_WRITE(out_EXECUTE_OOO_ENGINE_CONTEXT_ID [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID [i][j])); + if (_param->_have_port_rob_ptr) + PORT_WRITE(out_EXECUTE_OOO_ENGINE_PACKET_ID [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_PACKET_ID [i][j])); +// PORT_WRITE(out_EXECUTE_OOO_ENGINE_TYPE [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_TYPE [i][j])); +// PORT_WRITE(out_EXECUTE_OOO_ENGINE_OPERATION [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_OPERATION [i][j])); + PORT_WRITE(out_EXECUTE_OOO_ENGINE_FLAGS [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_FLAGS [i][j])); + PORT_WRITE(out_EXECUTE_OOO_ENGINE_EXCEPTION [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_EXCEPTION [i][j])); + PORT_WRITE(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE [i][j])); + PORT_WRITE(out_EXECUTE_OOO_ENGINE_ADDRESS [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_ADDRESS [i][j])); + PORT_WRITE(out_EXECUTE_OOO_ENGINE_DATA [num_ooo_engine][num_execute_loop][j], PORT_READ(in_EXECUTE_EXECUTE_LOOP_DATA [i][j])); + } + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_ooo_engine_nb_execute_loop[i]; ++j) + for (uint32_t k=0; k<_param->_nb_inst_execute[i][j];++k) + PORT_WRITE(out_EXECUTE_OOO_ENGINE_VAL [i][j][k], EXECUTE_OOO_ENGINE_VAL [i][j][k]); + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + PORT_WRITE(out_EXECUTE_EXECUTE_LOOP_ACK [i][j], EXECUTE_EXECUTE_LOOP_ACK [i][j]); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_insert.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::genMealy_insert" + void Core_Glue::genMealy_insert (void) + { + log_begin(Core_Glue,FUNCTION); + log_function(Core_Glue,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_execute_loop_nb_ooo_engine[i]; ++j) + { + Tcontext_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine [i][j]; + + for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert[i][j]; ++k) + { + PORT_WRITE(out_INSERT_EXECUTE_LOOP_VAL [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_VAL [num_ooo_engine][k])); + PORT_WRITE(out_INSERT_OOO_ENGINE_ACK [i][j] ,PORT_READ(in_INSERT_EXECUTE_LOOP_ACK [i][j][k])); + PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_USE [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_USE [num_ooo_engine][k])); + PORT_WRITE(out_INSERT_EXECUTE_LOOP_RD_NUM_REG [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RD_NUM_REG [num_ooo_engine][k])); + PORT_WRITE(out_INSERT_EXECUTE_LOOP_RE_USE [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RE_USE [num_ooo_engine][k])); + PORT_WRITE(out_INSERT_EXECUTE_LOOP_RE_NUM_REG [i][j][k],PORT_READ(in_INSERT_OOO_ENGINE_RE_NUM_REG [num_ooo_engine][k])); + } + } + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_issue.cpp (revision 88) @@ -0,0 +1,124 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::genMealy_issue" + void Core_Glue::genMealy_issue (void) + { + log_begin(Core_Glue,FUNCTION); + log_function(Core_Glue,FUNCTION,_name.c_str()); + + Tcontrol_t ISSUE_OOO_ENGINE_ACK [_param->_nb_ooo_engine ][_param->_max_nb_inst_issue]; + Tcontrol_t ISSUE_EXECUTE_LOOP_VAL [_param->_nb_execute_loop][_param->_max_nb_read_unit ]; + bool READ_UNIT_ENABLE [_param->_nb_execute_loop][_param->_max_nb_read_unit ]; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) + ISSUE_OOO_ENGINE_ACK [i][j] = 0; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + { + ISSUE_EXECUTE_LOOP_VAL [i][j] = 0; + // Read unit is enable is signal ack is set + READ_UNIT_ENABLE [i][j] = (PORT_READ(in_ISSUE_EXECUTE_LOOP_ACK [i][j]) == 1); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + { + log_printf(TRACE,Core_Glue,FUNCTION," * execute_loop [%d]",i); + + std::list * select = _priority[i] ->select(); + for (std::list::iterator it=select ->begin(); + it!=select->end(); + ++it) + { + const uint32_t ooo_engine_id = it->grp; + const uint32_t num_ooo_engine = _param->_translate_execute_loop_num_ooo_engine [i][ooo_engine_id]; + const uint32_t num_inst_issue = it->elt; + + log_printf(TRACE,Core_Glue,FUNCTION," * num_ooo_engine [%d] (id : %d)",num_ooo_engine, ooo_engine_id); + log_printf(TRACE,Core_Glue,FUNCTION," * num_inst_issue : %d",num_inst_issue); + log_printf(TRACE,Core_Glue,FUNCTION," * ISSUE_OOO_ENGINE_VAL : %d",PORT_READ(in_ISSUE_OOO_ENGINE_VAL [num_ooo_engine][num_inst_issue])); + + // have request ? + if (PORT_READ(in_ISSUE_OOO_ENGINE_VAL [num_ooo_engine][num_inst_issue])) + { +// // If ooo_engine can issue instruction on multiple execute_loop +// if (not ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue]) + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + // Test if have an link and read unit is enable + { + log_printf(TRACE,Core_Glue,FUNCTION," * read_unit : %d",j); + log_printf(TRACE,Core_Glue,FUNCTION," * READ_UNIT_ENABLE : %d",READ_UNIT_ENABLE [i][j]); + log_printf(TRACE,Core_Glue,FUNCTION," * table_dispatch : %d",_param->_table_dispatch [num_ooo_engine][num_inst_issue][i][j]); + + if (READ_UNIT_ENABLE [i][j] and + _param->_table_dispatch [num_ooo_engine][num_inst_issue][i][j]) + { + // Transaction + ISSUE_EXECUTE_LOOP_VAL [i][j] = 1; + ISSUE_OOO_ENGINE_ACK [num_ooo_engine][num_inst_issue] = 1; + READ_UNIT_ENABLE [i][j] = false; // now, this read_unit is busy + + if (_param->_have_port_context_id) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_CONTEXT_ID [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_CONTEXT_ID [num_ooo_engine][num_inst_issue])); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_FRONT_END_ID [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_FRONT_END_ID [num_ooo_engine][num_inst_issue])); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID [i][j],ooo_engine_id); + if (_param->_have_port_rob_ptr) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_PACKET_ID [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_PACKET_ID [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_OPERATION [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_OPERATION [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_TYPE [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_TYPE [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue])); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_IMMEDIAT [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_IMMEDIAT [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RA [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RA [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RA [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RA [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RB [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RB [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RB [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RB [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_READ_RC [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_READ_RC [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RC [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RC [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RD [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RD [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RD [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RD [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_WRITE_RE [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_WRITE_RE [num_ooo_engine][num_inst_issue])); + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_NUM_REG_RE [i][j],PORT_READ(in_ISSUE_OOO_ENGINE_NUM_REG_RE [num_ooo_engine][num_inst_issue])); + } + } + } + } + } + + // Write output + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_param->_nb_inst_issue[i]; ++j) + PORT_WRITE(out_ISSUE_OOO_ENGINE_ACK [i][j], ISSUE_OOO_ENGINE_ACK [i][j]); + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + PORT_WRITE(out_ISSUE_EXECUTE_LOOP_VAL [i][j], ISSUE_EXECUTE_LOOP_VAL [i][j]); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::statistics_allocation" + void Core_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Core_Glue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Core_Glue", + param_statistics); + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::statistics_deallocation" + void Core_Glue::statistics_deallocation (void) + { + log_begin(Core_Glue,FUNCTION); + + log_printf(INFO,Core_Glue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_transition.cpp (revision 88) @@ -0,0 +1,47 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::transition" + void Core_Glue::transition (void) + { + log_begin(Core_Glue,FUNCTION); + + if (PORT_READ(in_NRESET) == 0) + { + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + _priority [i]->reset(); + } + else + { + // next priority + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + _priority [i]->transition(); + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl.cpp (revision 88) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::vhdl" + void Core_Glue::vhdl (void) + { + log_begin(Core_Glue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_body.cpp (revision 88) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::vhdl_body" + void Core_Glue::vhdl_body (Vhdl * & vhdl) + { + log_begin(Core_Glue,FUNCTION); + vhdl->set_body (""); + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::vhdl_declaration" + void Core_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Core_Glue,FUNCTION); + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters.cpp (revision 88) @@ -0,0 +1,194 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Parameters.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::Parameters" + Parameters::Parameters + (uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t nb_ooo_engine , + uint32_t nb_execute_loop , + uint32_t * ooo_engine_nb_front_end ,//[nb_ooo_engine] + uint32_t * ooo_engine_nb_execute_loop ,//[nb_ooo_engine] + uint32_t * execute_loop_nb_ooo_engine ,//[nb_execute_loop] + uint32_t * nb_inst_decod ,//[nb_front_end] -> [sum_inst_decod] + uint32_t * front_end_nb_inst_branch_complete ,//[nb_front_end] + uint32_t * ooo_engine_nb_inst_branch_complete ,//[nb_ooo_engine] + uint32_t * nb_inst_insert ,//[nb_ooo_engine] + uint32_t * nb_inst_issue ,//[nb_ooo_engine] + uint32_t ** nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t * nb_read_unit ,//[nb_execute_loop] + uint32_t * nb_write_unit ,//[nb_execute_loop] + uint32_t size_depth , + uint32_t size_rob_ptr , + uint32_t size_load_queue_ptr , + uint32_t size_store_queue_ptr , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_general_register , + uint32_t size_special_register , + Tpriority_t dispatch_priority , + Tload_balancing_t dispatch_load_balancing , + bool **** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][execute_loop][nb_read_unit] + uint32_t ** translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] + uint32_t ** translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + uint32_t ** translate_execute_loop_num_ooo_engine,//[nb_execute_loop][execute_loop_nb_ooo_engine] + bool is_toplevel) + { + log_begin(Core_Glue,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_execute_loop = nb_execute_loop ; + _ooo_engine_nb_front_end = ooo_engine_nb_front_end ; + _ooo_engine_nb_execute_loop = ooo_engine_nb_execute_loop ; + _execute_loop_nb_ooo_engine = execute_loop_nb_ooo_engine ; + _nb_inst_decod = nb_inst_decod ; + _front_end_nb_inst_branch_complete = front_end_nb_inst_branch_complete ; + _ooo_engine_nb_inst_branch_complete = ooo_engine_nb_inst_branch_complete ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_issue = nb_inst_issue ; + _nb_inst_execute = nb_inst_execute ; + _nb_read_unit = nb_read_unit ; + _nb_write_unit = nb_write_unit ; + _dispatch_priority = dispatch_priority ; + _dispatch_load_balancing = dispatch_load_balancing ; + _table_dispatch = table_dispatch ; + _translate_ooo_engine_num_front_end = translate_ooo_engine_num_front_end ; + _translate_ooo_engine_num_execute_loop = translate_ooo_engine_num_execute_loop; + _translate_execute_loop_num_ooo_engine = translate_execute_loop_num_ooo_engine; + + test(); + + ALLOC1(_link_ooo_engine_with_front_end,uint32_t,_nb_front_end); + ALLOC1(_translate_num_front_end_to_ooo_engine_front_end_id,uint32_t,_nb_front_end); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; + + _link_ooo_engine_with_front_end [num_front_end] = i; + _translate_num_front_end_to_ooo_engine_front_end_id [num_front_end] = j; + } + + ALLOC2(_translate_num_execute_loop_to_ooo_engine_execute_loop_id, uint32_t, _nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + { + uint32_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j]; + uint32_t execute_loop_id; + for (execute_loop_id = 0; execute_loop_id<_ooo_engine_nb_execute_loop[num_ooo_engine]; ++execute_loop_id) + if (_translate_ooo_engine_num_execute_loop [num_ooo_engine][execute_loop_id] == i) + break; + + _translate_num_execute_loop_to_ooo_engine_execute_loop_id [i][j] = execute_loop_id; + } + + ALLOC2(_execute_loop_nb_inst_insert,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + ALLOC2(_execute_loop_nb_inst_issue ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + { + uint32_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j]; + _execute_loop_nb_inst_issue [i][j] = _nb_inst_issue [num_ooo_engine]; + _execute_loop_nb_inst_insert [i][j] = _nb_inst_insert [num_ooo_engine]; + } + + _max_ooo_engine_nb_inst_branch_complete = max(_ooo_engine_nb_inst_branch_complete,_nb_ooo_engine); + _max_front_end_nb_inst_branch_complete = max(_front_end_nb_inst_branch_complete,_nb_front_end); + _max_ooo_engine_nb_execute_loop = max(_ooo_engine_nb_execute_loop,_nb_ooo_engine); + _max_nb_inst_execute = max(_nb_inst_execute ,_nb_ooo_engine, _ooo_engine_nb_execute_loop); + _max_nb_write_unit = max(_nb_write_unit ,_nb_execute_loop); + _max_nb_inst_insert = max(_nb_inst_insert ,_nb_ooo_engine); + _max_nb_inst_issue = max(_nb_inst_issue ,_nb_ooo_engine); + _max_nb_read_unit = max(_nb_read_unit ,_nb_execute_loop); + + if (is_toplevel) + { + _size_context_id = log2(max(nb_context,nb_front_end)); + _size_front_end_id = log2(nb_front_end ); + _size_ooo_engine_id = log2(nb_ooo_engine); + _size_instruction_address = size_general_data-2 ; + _size_data_address = size_general_data ; + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_general_register = size_general_register; + _size_special_register = size_special_register; + _size_depth = size_depth ; + _size_rob_ptr = size_rob_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + _size_store_queue_ptr = size_store_queue_ptr ; +// _size_nb_inst_decod = size_nb_inst_decod ; +// _size_nb_inst_commit = size_nb_inst_commit ; +// _size_ifetch_queue_ptr = size_ifetch_queue_ptr; +// _size_inst_ifetch_ptr = size_inst_ifetch_ptr ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_depth = _size_depth > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; +// _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0; +// _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + + copy(); + } + + log_end(Core_Glue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Core_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Core_Glue,FUNCTION); +// test(); +// log_end(Core_Glue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Core_Glue::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Core_Glue,FUNCTION); + + DELETE2(_execute_loop_nb_inst_issue,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_execute_loop_nb_inst_insert,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_translate_num_execute_loop_to_ooo_engine_execute_loop_id, _nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE1(_translate_num_front_end_to_ooo_engine_front_end_id,_nb_front_end); + DELETE1(_link_ooo_engine_with_front_end,_nb_front_end); + + log_end(Core_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Core_Glue::copy" + void Parameters::copy (void) + { + log_begin(Core_Glue,FUNCTION); + log_end(Core_Glue,FUNCTION); + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,68 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Core_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Core_Glue,FUNCTION); + + Parameters_test test ("Core_Glue"); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + if (_translate_ooo_engine_num_front_end [i][j] > _nb_front_end) + test.error(_("Translation in ooo_engine of front_end id is an invalid id.\n")); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_execute_loop[i]; ++j) + if (_translate_ooo_engine_num_execute_loop [i][j] > _nb_execute_loop) + test.error(_("Translation in ooo_engine of execute_loop id is an invalid id.\n")); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + if (_translate_execute_loop_num_ooo_engine [i][j] > _nb_ooo_engine) + test.error(_("Translation in execute_loop of ooo_engine id is an invalid id.\n")); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; + + if (_front_end_nb_inst_branch_complete [num_front_end] != _ooo_engine_nb_inst_branch_complete [i]) + test.error(toString(_("front_end[%d].nb_inst_branch_complete must be equal at ooo_engine[%d].nb_inst_branch_complete.\n"),num_front_end,i)); + } + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + { + Tcontext_t num_ooo_engine = _translate_execute_loop_num_ooo_engine [i][j]; + for (uint32_t k=0; k<_ooo_engine_nb_execute_loop[num_ooo_engine]; ++k) + if (_translate_ooo_engine_num_execute_loop [num_ooo_engine][k] == i) + if (_nb_inst_execute[num_ooo_engine][k] != _nb_write_unit [i]) + test.error(toString(_("ooo_engine[%d][%d].nb_inst_execute must be equal at execute_loop[%d].nb_write_unit.\n"),num_ooo_engine,k,i)); + } + log_end(Core_Glue,FUNCTION); + + return test; + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,52 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Core_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace core_glue { + + +#undef FUNCTION +#define FUNCTION "Core_Glue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Core_Glue,FUNCTION); + + XML xml ("core_glue"); + + xml.balise_open("core_glue"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Core_Glue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Core_Glue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::core_glue::Parameters & x) + { + log_begin(Core_Glue,FUNCTION); + + output_stream << x.print(0); + + log_end(Core_Glue,FUNCTION); + + return output_stream; + }; + +}; // end namespace core_glue +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libDcache_Access.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Dcache_Access = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Dcache_Access_DIR = $(DIR_MORPHEO)/Behavioural/Core/Dcache_Access + +#-----[ Library ]------------------------------------------ + +Dcache_Access_LIBRARY = -lDcache_Access \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Dcache_Access_DIR_LIBRARY = -L$(Dcache_Access_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Dcache_Access_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Dcache_Access_DIR) --makefile=Makefile; + +Dcache_Access_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Dcache_Access_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Dcache_Access_LIBRARY) + +DIR_LIBRARY = $(Dcache_Access_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Dcache_Access_library + +library_clean : Dcache_Access_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_min.cfg (revision 88) @@ -0,0 +1,12 @@ +Dcache_Access +1 1 +1 # nb_execute_loop +1 1 +1 # nb_load_store_unit [0] [nb_execute_loop] +1 1 +1 # nb_cache_access [0][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_dcache_port +32 32 +1 # size_address +32 32 +1 # size_data +0 0 +1 # size_thread_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # table_routing [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop1.cfg (revision 88) @@ -0,0 +1,24 @@ +Dcache_Access +1 1 +1 # nb_execute_loop +4 4 +1 # nb_load_store_unit [0] [nb_execute_loop] +1 1 +1 # nb_cache_access [0][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [0][1] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [0][2] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [0][3] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_dcache_port +32 32 +1 # size_address +32 32 +1 # size_data +0 0 +1 # size_thread_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][3] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][3] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # table_routing [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop2.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_mono_execute_loop2.cfg (revision 88) @@ -0,0 +1,27 @@ +Dcache_Access +1 1 +1 # nb_execute_loop +4 4 +1 # nb_load_store_unit [0] [nb_execute_loop] +1 1 +1 # nb_cache_access [0][0] [nb_execute_loop][nb_load_store_unit] +2 2 +1 # nb_cache_access [0][1] [nb_execute_loop][nb_load_store_unit] +3 3 +1 # nb_cache_access [0][2] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [0][3] [nb_execute_loop][nb_load_store_unit] +4 4 +1 # nb_dcache_port +32 32 +1 # size_address +32 32 +1 # size_data +0 0 +1 # size_thread_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [0][3] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][3] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # table_routing [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [0][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +2 2 +1 # table_routing [0][1][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +2 2 +1 # table_routing [0][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [0][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [0][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [0][3][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop1.cfg (revision 88) @@ -0,0 +1,40 @@ +Dcache_Access +3 3 +1 # nb_execute_loop +1 1 +1 # nb_load_store_unit [0] [nb_execute_loop] +2 2 +1 # nb_load_store_unit [1] [nb_execute_loop] +3 3 +1 # nb_load_store_unit [2] [nb_execute_loop] +1 1 +1 # nb_cache_access [0][0] [nb_execute_loop][nb_load_store_unit] +2 2 +1 # nb_cache_access [1][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [1][1] [nb_execute_loop][nb_load_store_unit] +3 3 +1 # nb_cache_access [2][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [2][1] [nb_execute_loop][nb_load_store_unit] +4 4 +1 # nb_cache_access [2][2] [nb_execute_loop][nb_load_store_unit] +4 4 +1 # nb_dcache_port +32 32 +1 # size_address +32 32 +1 # size_data +0 0 +1 # size_thread_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [1][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [1][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [1][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [1][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # table_routing [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +2 2 +1 # table_routing [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop2.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/config_multi_execute_loop2.cfg (revision 88) @@ -0,0 +1,40 @@ +Dcache_Access +3 3 +1 # nb_execute_loop +1 1 +1 # nb_load_store_unit [0] [nb_execute_loop] +2 2 +1 # nb_load_store_unit [1] [nb_execute_loop] +3 3 +1 # nb_load_store_unit [2] [nb_execute_loop] +1 1 +1 # nb_cache_access [0][0] [nb_execute_loop][nb_load_store_unit] +2 2 +1 # nb_cache_access [1][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [1][1] [nb_execute_loop][nb_load_store_unit] +3 3 +1 # nb_cache_access [2][0] [nb_execute_loop][nb_load_store_unit] +1 1 +1 # nb_cache_access [2][1] [nb_execute_loop][nb_load_store_unit] +4 4 +1 # nb_cache_access [2][2] [nb_execute_loop][nb_load_store_unit] +8 8 +1 # nb_dcache_port +32 32 +1 # size_address +32 32 +1 # size_data +0 0 +1 # size_thread_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [1][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [1][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_thread_id [2][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [0][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [1][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [1][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][0] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][1] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # size_packet_id [2][2] [nb_execute_loop][nb_load_store_unit] +0 0 +1 # table_routing [0][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [1][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +2 2 +1 # table_routing [1][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [1][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +4 4 +1 # table_routing [2][0][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +5 5 +1 # table_routing [2][0][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +6 6 +1 # table_routing [2][0][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +7 7 +1 # table_routing [2][1][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 0 +1 # table_routing [2][2][0] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +1 1 +1 # table_routing [2][2][1] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +2 2 +1 # table_routing [2][2][2] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +3 3 +1 # table_routing [2][2][3] [nb_execute_loop][nb_load_store_unit][nb_cache_access] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/include/test.h (revision 88) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; + +using namespace morpheo::behavioural::core::dcache_access; + +void test (string name, + morpheo::behavioural::core::dcache_access::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,210 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/SelfTest/include/test.h" +#include "Common/include/Max.h" + +#define NB_PARAMS 6 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_execute_loop (uint32_t )\n")); + err (_(" * nb_load_store_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_cache_access [nb_execute_loop][nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_dcache_port (uint32_t )\n")); + err (_(" * size_address (uint32_t )\n")); + err (_(" * size_data (uint32_t )\n")); + err (_(" * size_thread_id [nb_execute_loop][nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_packet_id [nb_execute_loop][nb_load_store_unit] (uint32_t )\n")); + err (_(" * table_routing [nb_execute_loop][nb_load_store_unit][nb_cache_access] (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + for (int32_t i=0; i(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t sum_load_store_unit = 0; + uint32_t sum_nb_cache_access = 0; + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_execute_loop = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+_nb_execute_loop)) + usage (argc, argv); + + uint32_t * _nb_load_store_unit = new uint32_t [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + _nb_load_store_unit [i] = fromString(argv[x++]); + sum_load_store_unit += _nb_load_store_unit [i]; + } + + if (argc <= static_cast(2+NB_PARAMS+_nb_execute_loop+3*sum_load_store_unit)) + usage (argc, argv); + + uint32_t ** _nb_cache_access = new uint32_t * [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + _nb_cache_access [i] = new uint32_t [_nb_load_store_unit[i]]; + for (uint32_t j=0; j<_nb_load_store_unit[i]; ++j) + { + _nb_cache_access [i][j] = fromString(argv[x++]); + sum_nb_cache_access += _nb_cache_access [i][j]; + } + } + + if (argc != static_cast(2+NB_PARAMS+_nb_execute_loop+3*sum_load_store_unit+sum_nb_cache_access)) + usage (argc, argv); + + uint32_t _nb_dcache_port = fromString(argv[x++]); + uint32_t _size_address = fromString(argv[x++]); + uint32_t _size_data = fromString(argv[x++]); + + + uint32_t ** _size_thread_id = new uint32_t * [_nb_execute_loop]; + uint32_t ** _size_packet_id = new uint32_t * [_nb_execute_loop]; + uint32_t *** _table_routing = new uint32_t ** [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; i++) + { + _size_thread_id [i] = new uint32_t [_nb_load_store_unit [i]]; + _size_packet_id [i] = new uint32_t [_nb_load_store_unit [i]]; + _table_routing [i] = new uint32_t * [_nb_load_store_unit [i]]; + + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + _table_routing [i][j] = new uint32_t [_nb_cache_access [i][j]]; + } + + for (uint32_t i=0; i<_nb_execute_loop; i++) + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + _size_thread_id [i][j] = fromString(argv[x++]); + + for (uint32_t i=0; i<_nb_execute_loop; i++) + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + _size_packet_id [i][j] = fromString(argv[x++]); + + for (uint32_t i=0; i<_nb_execute_loop; i++) + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + for (uint32_t k=0; k<_nb_cache_access [i][j]; ++k) + _table_routing [i][j][k] = fromString(argv[x++]); + + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + + uint32_t * _nb_context = new uint32_t [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; ++i) + _nb_context [i] = 1<(_size_thread_id[i],_nb_load_store_unit[i]); + + uint32_t _nb_thread = 0; + uint32_t *** _translate_load_store_unit_to_thread = new uint32_t ** [_nb_execute_loop]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + _translate_load_store_unit_to_thread[i] = new uint32_t * [_nb_load_store_unit[i]]; + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + { + _translate_load_store_unit_to_thread[i][j] = new uint32_t [_nb_context[i]]; + for (uint32_t k=0; k<_nb_context[i]; ++k) + _translate_load_store_unit_to_thread[i][j][k] = _nb_thread ++; + } + } + + uint32_t _size_dcache_thread_id = log2(_nb_thread); + uint32_t _size_dcache_packet_id = (log2(max(_nb_cache_access,_nb_execute_loop,_nb_load_store_unit)) + + max(_size_packet_id,_nb_execute_loop,_nb_load_store_unit)); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::dcache_access::Parameters * param = new morpheo::behavioural::core::dcache_access::Parameters + (_nb_thread , + _nb_execute_loop , + _nb_load_store_unit , + _nb_context , + _nb_cache_access , + _nb_dcache_port , + _size_address , + _size_data , + _size_dcache_thread_id , + _size_dcache_packet_id , + _size_thread_id , + _size_packet_id , + _table_routing , + _priority , + _load_balancing , + _translate_load_store_unit_to_thread + ); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("%s\n"), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Dcache_Access : no error"); + else + TEST_KO("Dcache_Access : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_context; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + delete [] _translate_load_store_unit_to_thread[i][j]; + delete [] _translate_load_store_unit_to_thread[i]; + } + delete [] _translate_load_store_unit_to_thread; + + for (uint32_t i=0; i<_nb_execute_loop; i++) + { + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + delete [] _table_routing [i][j]; + + delete [] _size_thread_id [i]; + delete [] _size_packet_id [i]; + delete [] _table_routing [i]; + } + delete [] _size_thread_id; + delete [] _size_packet_id; + delete [] _table_routing ; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + delete [] _nb_cache_access [i]; + delete [] _nb_cache_access; + + delete [] _nb_load_store_unit; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,331 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Dcache_Access/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +typedef struct +{ + uint32_t execute_loop ; + uint32_t load_store_unit; + uint32_t cache_access ; +} thread_id_t; + +void test (string name, + morpheo::behavioural::core::dcache_access::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Dcache_Access * _Dcache_Access = new Dcache_Access + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,"out_DCACHE_REQ_THREAD_ID",Tcontext_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID",Tpacket_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_dcache_port); + + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ," in_DCACHE_RSP_THREAD_ID",Tcontext_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID",Tpacket_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_dcache_port); + + ALLOC3_SC_SIGNAL( in_LSQ_REQ_VAL ," in_LSQ_REQ_VAL ",Tcontrol_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL(out_LSQ_REQ_ACK ,"out_LSQ_REQ_ACK ",Tcontrol_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_REQ_THREAD_ID ," in_LSQ_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_REQ_PACKET_ID ," in_LSQ_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_REQ_ADDRESS ," in_LSQ_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_REQ_WDATA ," in_LSQ_REQ_WDATA ",Tdcache_data_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_REQ_TYPE ," in_LSQ_REQ_TYPE ",Tdcache_type_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + ALLOC3_SC_SIGNAL(out_LSQ_RSP_VAL ,"out_LSQ_RSP_VAL ",Tcontrol_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL( in_LSQ_RSP_ACK ," in_LSQ_RSP_ACK ",Tcontrol_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL(out_LSQ_RSP_THREAD_ID ,"out_LSQ_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL(out_LSQ_RSP_PACKET_ID ,"out_LSQ_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL(out_LSQ_RSP_RDATA ,"out_LSQ_RSP_RDATA ",Tdcache_data_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + ALLOC3_SC_SIGNAL(out_LSQ_RSP_ERROR ,"out_LSQ_RSP_ERROR ",Tdcache_error_t ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Dcache_Access.\n"),name.c_str()); + + (*(_Dcache_Access->in_CLOCK)) (*(in_CLOCK)); + (*(_Dcache_Access->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_VAL ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_REQ_ACK ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port); + + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_RSP_VAL ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_DCACHE_RSP_ACK ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port); + + INSTANCE3_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access,out_LSQ_REQ_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_ADDRESS ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_WDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_TYPE ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + INSTANCE3_SC_SIGNAL(_Dcache_Access,out_LSQ_RSP_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access, in_LSQ_RSP_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access,out_LSQ_RSP_RDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + INSTANCE3_SC_SIGNAL(_Dcache_Access,out_LSQ_RSP_ERROR ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + for (uint32_t i=0; i<_param->_nb_execute_loop; i++) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; j++) + { + if (_param->_have_port_lsq_thread_id [i][j]) + { + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_THREAD_ID [i][j], _param->_nb_cache_access[i][j]); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_LSQ_RSP_THREAD_ID [i][j], _param->_nb_cache_access[i][j]); + } + if (_param->_have_port_lsq_packet_id [i][j]) + { + INSTANCE1_SC_SIGNAL(_Dcache_Access, in_LSQ_REQ_PACKET_ID [i][j], _param->_nb_cache_access[i][j]); + INSTANCE1_SC_SIGNAL(_Dcache_Access,out_LSQ_RSP_PACKET_ID [i][j], _param->_nb_cache_access[i][j]); + } + } + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const int32_t percent_transaction_req = 75; + const int32_t percent_transaction_rsp = 75; + + thread_id_t link_cache_rsp [_param->_nb_dcache_port][_param->_nb_execute_loop*_param->_max_nb_load_store_unit*_param->_max_nb_cache_access]; + uint32_t nb_link_cache_rsp [_param->_nb_dcache_port]; + + for (uint32_t i=0; i<_param->_nb_dcache_port; i++) + nb_link_cache_rsp [i] = 0; + + for (uint32_t i=0; i<_param->_nb_execute_loop; i++) + for (uint32_t j=0; j<_param->_nb_load_store_unit [i]; j++) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + { + uint32_t x = _param->_table_routing [i][j][k]; + + link_cache_rsp [x][nb_link_cache_rsp[x]].execute_loop = i; + link_cache_rsp [x][nb_link_cache_rsp[x]].load_store_unit = j; + link_cache_rsp [x][nb_link_cache_rsp[x]].cache_access = k; + nb_link_cache_rsp[x] ++; + } + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_dcache_port; i++) + { + in_DCACHE_REQ_ACK [i]->write((rand()%100)write((rand()%100)write(_param->_translate_load_store_unit_to_thread[a][b][0]); + in_DCACHE_RSP_PACKET_ID [i]->write((c << _param->_shift_num_cache_access)); + in_DCACHE_RSP_RDATA [i]->write(0); + in_DCACHE_RSP_ERROR [i]->write(0); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; i++) + for (uint32_t j=0; j<_param->_nb_load_store_unit [i]; j++) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + { + in_LSQ_REQ_VAL [i][j][k]->write((rand()%100)write(0); + in_LSQ_REQ_THREAD_ID [i][j][k]->write(0); + in_LSQ_REQ_PACKET_ID [i][j][k]->write(0); + in_LSQ_REQ_ADDRESS [i][j][k]->write(0); + in_LSQ_REQ_WDATA [i][j][k]->write(0); + in_LSQ_REQ_TYPE [i][j][k]->write(0); + + in_LSQ_RSP_ACK [i][j][k]->write((rand()%100)_nb_dcache_port; i++) + { + if (out_DCACHE_REQ_VAL [i]->read() and in_DCACHE_REQ_ACK [i]->read()) + { + LABEL("DCACHE_REQ [%d] - Transaction Accepted.",i); + + nb_request ++; + } + if ( in_DCACHE_RSP_VAL [i]->read() and out_DCACHE_RSP_ACK [i]->read()) + { + LABEL("DCACHE_RSP [%d] - Transaction Accepted.",i); + + nb_respons ++; + } + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; i++) + for (uint32_t j=0; j<_param->_nb_load_store_unit [i]; j++) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + { + if (in_LSQ_REQ_VAL [i][j][k]->read() and out_LSQ_REQ_ACK [i][j][k]->read()) + { + LABEL("LSQ_REQ [%d][%d][%d] - Transaction Accepted.",i,j,k); + + uint32_t x=_param->_table_routing[i][j][k]; + + TEST(Tcontrol_t,out_DCACHE_REQ_VAL[x]->read(), 1); + TEST(Tcontrol_t, in_DCACHE_REQ_ACK[x]->read(), 1); + + TEST(Tcontext_t ,out_DCACHE_REQ_THREAD_ID [x]->read(), _param->_translate_load_store_unit_to_thread [i][j][0]); + TEST(Tpacket_t ,out_DCACHE_REQ_PACKET_ID [x]->read(), (k << _param->_shift_num_cache_access)); + TEST(Tdcache_address_t,out_DCACHE_REQ_ADDRESS [x]->read(), 0); + TEST(Tdcache_address_t,out_DCACHE_REQ_WDATA [x]->read(), 0); + TEST(Tdcache_type_t ,out_DCACHE_REQ_TYPE [x]->read(), 0); + + nb_request --; + } + + if (out_LSQ_RSP_VAL [i][j][k]->read() and in_LSQ_RSP_ACK [i][j][k]->read()) + { + LABEL("LSQ_RSP [%d][%d][%d] - Transaction Accepted.",i,j,k); + +// public : SC_OUT(Tcontext_t ) **** out_LSQ_RSP_THREAD_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] +// public : SC_OUT(Tpacket_t ) **** out_LSQ_RSP_PACKET_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] +// public : SC_OUT(Tdcache_data_t ) **** out_LSQ_RSP_RDATA ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] +// public : SC_OUT(Tdcache_error_t ) **** out_LSQ_RSP_ERROR ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + nb_respons --; + } + } + + TEST(int32_t, nb_request, 0); + TEST(int32_t, nb_respons, 0); + + SC_START(1); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port); + + DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port); + + DELETE3_SC_SIGNAL( in_LSQ_REQ_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL(out_LSQ_REQ_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_REQ_THREAD_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_REQ_PACKET_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_REQ_ADDRESS ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_REQ_WDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_REQ_TYPE ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + DELETE3_SC_SIGNAL(out_LSQ_RSP_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL( in_LSQ_RSP_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL(out_LSQ_RSP_THREAD_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL(out_LSQ_RSP_PACKET_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL(out_LSQ_RSP_RDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + DELETE3_SC_SIGNAL(out_LSQ_RSP_ERROR ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + } +#endif + + delete _Dcache_Access; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Dcache_Access.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Dcache_Access.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Dcache_Access.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Dcache_Access} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Dcache_Access.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Dcache_Access.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Dcache_Access.h (revision 88) @@ -0,0 +1,174 @@ +#ifndef morpheo_behavioural_core_dcache_access_Dcache_Access_h +#define morpheo_behavioural_core_dcache_access_Dcache_Access_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Dcache_Access/include/Parameters.h" +#include "Behavioural/Core/Dcache_Access/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace dcache_access { + + + class Dcache_Access +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; + + private : counter_t ** _stat_nb_access; + private : counter_t ** _stat_nb_access_conflit; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_dcache_port] + public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_dcache_port] + public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_THREAD_ID ;//[nb_dcache_port] + public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_dcache_port] + public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_dcache_port] + public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_dcache_port] + public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_dcache_port] + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_dcache_port] + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_dcache_port] + public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_THREAD_ID ;//[nb_dcache_port] + public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_dcache_port] + public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_dcache_port] + public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_dcache_port] + + // ~~~~~[ Interface "lsq_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) **** in_LSQ_REQ_VAL ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_OUT(Tcontrol_t ) **** out_LSQ_REQ_ACK ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tcontext_t ) **** in_LSQ_REQ_THREAD_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tpacket_t ) **** in_LSQ_REQ_PACKET_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tdcache_address_t ) **** in_LSQ_REQ_ADDRESS ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tdcache_data_t ) **** in_LSQ_REQ_WDATA ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tdcache_type_t ) **** in_LSQ_REQ_TYPE ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + + // ~~~~~[ Interface "lsq_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) **** out_LSQ_RSP_VAL ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_IN (Tcontrol_t ) **** in_LSQ_RSP_ACK ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_OUT(Tcontext_t ) **** out_LSQ_RSP_THREAD_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_OUT(Tpacket_t ) **** out_LSQ_RSP_PACKET_ID ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_OUT(Tdcache_data_t ) **** out_LSQ_RSP_RDATA ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : SC_OUT(Tdcache_error_t ) **** out_LSQ_RSP_ERROR ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef STATISTICS + private : uint32_t * _internal_DCACHE_REQ_NB_ACCESS ; //[nb_dcache_port] + private : uint32_t * _internal_DCACHE_REQ_NB_ACCESS_CONFLIT; //[nb_dcache_port] +#endif + +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Dcache_Access); +#endif + public : Dcache_Access + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Dcache_Access (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_req (void); + public : void genMealy_rsp (void); + +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Parameters.h (revision 88) @@ -0,0 +1,92 @@ +#ifndef morpheo_behavioural_core_dcache_access_Parameters_h +#define morpheo_behavioural_core_dcache_access_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_thread ; + public : uint32_t _nb_execute_loop ; + public : uint32_t * _nb_load_store_unit ;//[nb_execute_loop] + public : uint32_t * _nb_context ;//[nb_execute_loop]//{nb_front_end + nb_context} + public : uint32_t ** _nb_cache_access ;//[nb_execute_loop][nb_load_store_unit] + public : uint32_t _nb_dcache_port ; + public : uint32_t _size_address ; + public : uint32_t _size_data ; + public : uint32_t _size_dcache_thread_id ; + public : uint32_t _size_dcache_packet_id ; + public : uint32_t ** _size_thread_id ;//[nb_execute_loop][nb_load_store_unit] + public : uint32_t ** _size_packet_id ;//[nb_execute_loop][nb_load_store_unit] + public : uint32_t *** _table_routing ;//[nb_execute_loop][nb_load_store_unit][nb_cache_access] + public : Tpriority_t _priority ; + public : Tload_balancing_t _load_balancing ; + public : uint32_t *** _translate_load_store_unit_to_thread; //[nb_execute_loop][nb_load_store_unit][nb_context] + + public : uint32_t _max_nb_load_store_unit ; + public : uint32_t _max_nb_cache_access ; + public : Tcontext_t _shift_num_cache_access ; + public : Tcontext_t _mask_num_cache_access ; + public : Tcontext_t _mask_num_lsq_packet ; + public : uint32_t * _translate_thread_to_execute_loop ; //[nb_thread] + public : uint32_t * _translate_thread_to_load_store_unit; //[nb_thread] + public : uint32_t * _translate_thread_to_context ; //[nb_thread] + + public : bool ** _have_port_lsq_thread_id ;//[nb_execute_loop][nb_load_store_unit] + public : bool ** _have_port_lsq_packet_id ;//[nb_execute_loop][nb_load_store_unit] + public : bool _have_port_dcache_thread_id; + public : bool _have_port_dcache_packet_id; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_thread , + uint32_t nb_execute_loop , + uint32_t * nb_load_store_unit , + uint32_t * nb_context , + uint32_t ** nb_cache_access , + uint32_t nb_dcache_port , + uint32_t size_address , + uint32_t size_data , + uint32_t size_dcache_thread_id , + uint32_t size_dcache_packet_id , + uint32_t ** size_thread_id , + uint32_t ** size_packet_id , + uint32_t *** table_routing , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t *** translate_load_store_unit_to_thread, + bool is_toplevel=false ); + +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::dcache_access::Parameters & x); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/include/Types.h (revision 88) @@ -0,0 +1,25 @@ +#ifndef morpheo_behavioural_core_dcache_access_Types_h +#define morpheo_behavioural_core_dcache_access_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access.cpp (revision 88) @@ -0,0 +1,178 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::Dcache_Access" + Dcache_Access::Dcache_Access + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::dcache_access::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Dcache_Access,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Dcache_Access == true + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Method - genMealy_req"),_name.c_str()); + + SC_METHOD (genMealy_req); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + sensitive << (*(in_DCACHE_REQ_ACK [i])); + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + { + sensitive << (*(in_LSQ_REQ_VAL [i][j][k])) + << (*(in_LSQ_REQ_ADDRESS [i][j][k])) + << (*(in_LSQ_REQ_WDATA [i][j][k])) + << (*(in_LSQ_REQ_TYPE [i][j][k])); + + if (_param->_have_port_lsq_thread_id [i][j]) + sensitive << (*(in_LSQ_REQ_THREAD_ID [i][j][k])); + if (_param->_have_port_lsq_packet_id [i][j]) + sensitive << (*(in_LSQ_REQ_PACKET_ID [i][j][k])); + } + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Method - genMealy_rsp"),_name.c_str()); + + SC_METHOD (genMealy_rsp); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + { + sensitive << (*(in_DCACHE_RSP_VAL [i])) + << (*(in_DCACHE_RSP_RDATA [i])) + << (*(in_DCACHE_RSP_ERROR [i])); + if (_param->_have_port_dcache_thread_id) + sensitive << (*(in_DCACHE_RSP_THREAD_ID [i])); + if (_param->_have_port_dcache_packet_id) + sensitive << (*(in_DCACHE_RSP_PACKET_ID [i])); + + } + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + sensitive << (*(in_LSQ_RSP_ACK [i][j][k])); + + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Dcache_Access,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Dcache_Access::~Dcache_Access" + Dcache_Access::~Dcache_Access (void) + { + log_begin(Dcache_Access,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_allocation.cpp (revision 88) @@ -0,0 +1,135 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::allocation" + void Dcache_Access::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Dcache_Access,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Dcache_Access" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); + + ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_dcache_thread_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_dcache_packet_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_data); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type); + } + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); + + ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_dcache_thread_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_dcache_packet_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_data); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error); + } + + // ~~~~~[ Interface "lsq_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC3_INTERFACE("lsq_req", IN, SOUTH, _("Request from load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + _ALLOC3_VALACK_IN ( in_LSQ_REQ_VAL ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_VALACK_OUT(out_LSQ_REQ_ACK ,ACK, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_thread_id [it1][it2], _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_packet_id [it1][it2], _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_param->_size_address , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_data , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_IN ( in_LSQ_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + } + + // ~~~~~[ Interface "lsq_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC3_INTERFACE("lsq_rsp",OUT, SOUTH, _("Respons to load_store queue"), _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + + _ALLOC3_VALACK_OUT(out_LSQ_RSP_VAL ,VAL, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_VALACK_IN ( in_LSQ_RSP_ACK ,ACK, _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_thread_id [it1][it2], _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_packet_id [it1][it2], _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_data , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_LSQ_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error , _param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2]); + } + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef STATISTICS + if (usage_is_set(_usage,USE_SYSTEMC)) + { + _internal_DCACHE_REQ_NB_ACCESS = new uint32_t [_param->_nb_dcache_port]; + _internal_DCACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_dcache_port]; + } +#endif + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority = new generic::priority::Priority (_name+"_priority", + _param->_priority , + _param->_load_balancing , + _param->_nb_execute_loop , + _param->_nb_load_store_unit, + _param->_nb_execute_loop ); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_deallocation.cpp (revision 88) @@ -0,0 +1,77 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::deallocation" + void Dcache_Access::deallocation (void) + { + log_begin(Dcache_Access,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port,_param->_size_dcache_thread_id); + DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port,_param->_size_dcache_packet_id); + DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port,_param->_size_address); + DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port,_param->_size_data); + DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port,_param->_size_dcache_type); + + DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port,_param->_size_dcache_thread_id); + DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port,_param->_size_dcache_packet_id); + DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port,_param->_size_data); + DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port,_param->_size_dcache_error); + + DELETE3_SIGNAL( in_LSQ_REQ_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],1); + DELETE3_SIGNAL(out_LSQ_REQ_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],1); + DELETE3_SIGNAL( in_LSQ_REQ_THREAD_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_thread_id [it1][it2]); + DELETE3_SIGNAL( in_LSQ_REQ_PACKET_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_packet_id [it1][it2]); + DELETE3_SIGNAL( in_LSQ_REQ_ADDRESS ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_address ); + DELETE3_SIGNAL( in_LSQ_REQ_WDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_data ); + DELETE3_SIGNAL( in_LSQ_REQ_TYPE ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_dcache_type ); + + DELETE3_SIGNAL(out_LSQ_RSP_VAL ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],1); + DELETE3_SIGNAL( in_LSQ_RSP_ACK ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],1); + DELETE3_SIGNAL(out_LSQ_RSP_THREAD_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_thread_id [it1][it2]); + DELETE3_SIGNAL(out_LSQ_RSP_PACKET_ID ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_packet_id [it1][it2]); + DELETE3_SIGNAL(out_LSQ_RSP_RDATA ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_data ); + DELETE3_SIGNAL(out_LSQ_RSP_ERROR ,_param->_nb_execute_loop, _param->_nb_load_store_unit[it1], _param->_nb_cache_access[it1][it2],_param->_size_dcache_error ); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef STATISTICS + delete [] _internal_DCACHE_REQ_NB_ACCESS ; + delete [] _internal_DCACHE_REQ_NB_ACCESS_CONFLIT; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _priority; + + delete _component; + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_end_cycle.cpp (revision 88) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::end_cycle" +void Dcache_Access::end_cycle () + { + log_begin(Dcache_Access,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_req.cpp (revision 88) @@ -0,0 +1,107 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::genMealy_req" + void Dcache_Access::genMealy_req (void) + { + log_begin(Dcache_Access,FUNCTION); + + Tcontrol_t dcache_req_val [_param->_nb_dcache_port]; + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + { + dcache_req_val [i] = 0; + +#ifdef STATISTICS + _internal_DCACHE_REQ_NB_ACCESS [i] = 0; + _internal_DCACHE_REQ_NB_ACCESS_CONFLIT [i] = 0; +#endif + } + + Tcontrol_t lsq_req_ack [_param->_nb_execute_loop][_param->_max_nb_load_store_unit][_param->_max_nb_cache_access]; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + lsq_req_ack [i][j][k] = 0; + + std::list * select = _priority ->select(); + for (std::list::iterator it=select ->begin(); + it!=select->end(); + ++it) + { + uint32_t num_execute_loop = it->grp; + uint32_t num_load_store_unit = it->elt; + + for (uint32_t num_cache_access = 0; num_cache_access<_param->_nb_cache_access [num_execute_loop][num_load_store_unit]; ++num_cache_access) + { + if (PORT_READ(in_LSQ_REQ_VAL [num_execute_loop][num_load_store_unit][num_cache_access])) + { + uint32_t num_port = _param->_table_routing[num_execute_loop][num_load_store_unit][num_cache_access]; + Tcontrol_t dcache_req_ack = PORT_READ(in_DCACHE_REQ_ACK [num_port]); + +#ifdef STATISTICS + if (dcache_req_ack) + { + _internal_DCACHE_REQ_NB_ACCESS [num_port] ++; + if (dcache_req_val [num_port]) + _internal_DCACHE_REQ_NB_ACCESS_CONFLIT [num_port] ++; + } +#endif + if (not dcache_req_val [num_port]) + { + dcache_req_val [num_port] = 1; + lsq_req_ack [num_execute_loop][num_load_store_unit][num_cache_access] = dcache_req_ack; + + if (_param->_have_port_dcache_thread_id) + { + Tcontext_t num_context = (_param->_have_port_lsq_thread_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_THREAD_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0; + PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], _param->_translate_load_store_unit_to_thread[num_execute_loop][num_load_store_unit][num_context]); + } +// PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], ((num_execute_loop << _param->_shift_num_execute_loop )+ +// (num_load_store_unit << _param->_shift_num_load_store_unit)+ +// (num_cache_access << _param->_shift_num_cache_access )+ +// num_context)); + if (_param->_have_port_dcache_packet_id) + { + Tpacket_t packet_id = (_param->_have_port_lsq_packet_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_PACKET_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0; + PORT_WRITE(out_DCACHE_REQ_PACKET_ID [num_port], ((num_cache_access << _param->_shift_num_cache_access )+ + packet_id)); + } + PORT_WRITE(out_DCACHE_REQ_ADDRESS [num_port], PORT_READ(in_LSQ_REQ_ADDRESS [num_execute_loop][num_load_store_unit][num_cache_access])); + PORT_WRITE(out_DCACHE_REQ_WDATA [num_port], PORT_READ(in_LSQ_REQ_WDATA [num_execute_loop][num_load_store_unit][num_cache_access])); + PORT_WRITE(out_DCACHE_REQ_TYPE [num_port], PORT_READ(in_LSQ_REQ_TYPE [num_execute_loop][num_load_store_unit][num_cache_access])); + } + } + } + } + + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + PORT_WRITE(out_DCACHE_REQ_VAL [i], dcache_req_val [i]); + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], lsq_req_ack [i][j][k]); + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp (revision 88) @@ -0,0 +1,98 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::genMealy_rsp" + void Dcache_Access::genMealy_rsp (void) + { + log_begin(Dcache_Access,FUNCTION); + + Tcontrol_t lsq_rsp_val [_param->_nb_execute_loop][_param->_max_nb_load_store_unit][_param->_max_nb_cache_access]; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + lsq_rsp_val [i][j][k] = 0; + + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + { + Tcontrol_t val = PORT_READ(in_DCACHE_RSP_VAL [i]); + Tcontrol_t ack; + + if (val) + { + Tcontext_t thread_id = (_param->_have_port_dcache_thread_id)?PORT_READ(in_DCACHE_RSP_THREAD_ID [i]):0; + Tcontext_t packet_id = (_param->_have_port_dcache_packet_id)?PORT_READ(in_DCACHE_RSP_PACKET_ID [i]):0; + + Tcontext_t execute_loop_id = _param->_translate_thread_to_execute_loop [thread_id]; + Tcontext_t load_store_unit_id = _param->_translate_thread_to_load_store_unit [thread_id]; + Tcontext_t context_id = _param->_translate_thread_to_context [thread_id]; + + Tpacket_t cache_access_id = (packet_id >> _param->_shift_num_cache_access ) & _param->_mask_num_cache_access; + Tpacket_t lsq_packet_id = packet_id & _param->_mask_num_lsq_packet; + +// log_printf(TRACE,Dcache_Access,FUNCTION,"thread_id : %d",thread_id); +// log_printf(TRACE,Dcache_Access,FUNCTION,"execute_loop_id : %d",execute_loop_id); +// log_printf(TRACE,Dcache_Access,FUNCTION,"load_store_unit_id : %d",load_store_unit_id); +// log_printf(TRACE,Dcache_Access,FUNCTION,"cache_access_id : %d",cache_access_id); + +#ifdef DEBUG_TEST + if (execute_loop_id > _param->_nb_execute_loop) + throw ERRORMORPHEO(FUNCTION,_("invalid execute_loop_id.\n")); + + if (load_store_unit_id > _param->_nb_load_store_unit[execute_loop_id]) + throw ERRORMORPHEO(FUNCTION,_("invalid load_store_unit_id.\n")); + + if (context_id > _param->_nb_context[execute_loop_id][load_store_unit_id]) + throw ERRORMORPHEO(FUNCTION,_("invalid context_id.\n")); + + if (cache_access_id > _param->_nb_cache_access[execute_loop_id][load_store_unit_id]) + throw ERRORMORPHEO(FUNCTION,_("invalid cache_access_id.\n")); + + if (_param->_table_routing [execute_loop_id][load_store_unit_id][cache_access_id] != i) + throw ERRORMORPHEO(FUNCTION,_("invalid route.\n")); +#endif + + ack = PORT_READ(in_LSQ_RSP_ACK [execute_loop_id][load_store_unit_id][cache_access_id]); + + lsq_rsp_val [execute_loop_id][load_store_unit_id][cache_access_id] = 1; + + if (_param->_have_port_lsq_thread_id [execute_loop_id][load_store_unit_id]) + PORT_WRITE(out_LSQ_RSP_THREAD_ID [execute_loop_id][load_store_unit_id][cache_access_id], context_id); + if (_param->_have_port_lsq_packet_id [execute_loop_id][load_store_unit_id]) + PORT_WRITE(out_LSQ_RSP_PACKET_ID [execute_loop_id][load_store_unit_id][cache_access_id], lsq_packet_id); + PORT_WRITE(out_LSQ_RSP_RDATA [execute_loop_id][load_store_unit_id][cache_access_id], PORT_READ(in_DCACHE_RSP_RDATA [i])); + PORT_WRITE(out_LSQ_RSP_ERROR [execute_loop_id][load_store_unit_id][cache_access_id], PORT_READ(in_DCACHE_RSP_ERROR [i])); + } + else + ack = 0; + + PORT_WRITE(out_DCACHE_RSP_ACK [i],ack); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) + PORT_WRITE(out_LSQ_RSP_VAL [i][j][k], lsq_rsp_val [i][j][k]); + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_allocation.cpp (revision 88) @@ -0,0 +1,70 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::statistics_allocation" + void Dcache_Access::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Dcache_Access,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Dcache_Access", + param_statistics); + + _stat_nb_access = new counter_t * [_param->_nb_dcache_port]; + _stat_nb_access_conflit = new counter_t * [_param->_nb_dcache_port]; + + std::string _sum_nb_access = ""; + std::string _sum_nb_access_conflit = ""; + + for (uint32_t i=0; i<_param->_nb_dcache_port; i++) + { + _stat_nb_access [i] = _stat->create_counter("nb_access_" +toString(i),"",toString(_("Total access achieved by all contexts (port %d)"),i)); + _stat_nb_access_conflit [i] = _stat->create_counter("nb_access_conflit_"+toString(i),"",toString(_("Total access conducting a conflict (port %d)"),i)); + + if (i == 0) + { + _sum_nb_access = "nb_access_0"; + _sum_nb_access_conflit = "nb_access_conflit_0"; + } + else + { + _sum_nb_access = "+ nb_access_" +toString(i)+" "+ _sum_nb_access ; + _sum_nb_access_conflit = "+ nb_access_conflit_" +toString(i)+" "+ _sum_nb_access_conflit; + } + + _stat->create_expr_percent ("percent_access_conflit_"+toString(i), "nb_access_conflit_"+toString(i), "nb_access_"+toString(i),toString(_("Percent for total access conducting a conflict (port %d)"),i)); + + + _stat->create_expr_average_by_cycle ("average_nb_dcache_access_"+toString(i),"- nb_access_"+toString(i)+" nb_access_conflit_"+toString(i),"",toString(_("Average of dcache access (port %d)"),i)); + } + + _stat->create_expr ("nb_access" , _sum_nb_access , TYPE_COUNTER, "", _("Total access achieved by all contexts (all port)")); + _stat->create_expr ("nb_access_conflit", _sum_nb_access_conflit, TYPE_COUNTER, "", _("Total access conducting a conflict (all port)")); + + _stat->create_expr_percent ("percent_access_conflit", _sum_nb_access_conflit, _sum_nb_access,_("Percent for total access conducting a conflict")); + + _stat->create_expr_average_by_cycle ("average_nb_dcache_access","- nb_access nb_access_conflit","",_("Average of dcache access (all port)")); + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::statistics_deallocation" + void Dcache_Access::statistics_deallocation (void) + { + log_begin(Dcache_Access,FUNCTION); + + log_printf(INFO,Dcache_Access,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + delete [] _stat_nb_access; + delete [] _stat_nb_access_conflit; + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_transition.cpp (revision 88) @@ -0,0 +1,54 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::transition" + void Dcache_Access::transition (void) + { + log_begin(Dcache_Access,FUNCTION); + + if (PORT_READ(in_NRESET) == 0) + { + _priority->reset(); + } + else + { + // next priority + _priority->transition(); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_dcache_port;i++) + { + (*_stat_nb_access [i]) += _internal_DCACHE_REQ_NB_ACCESS [i]; + (*_stat_nb_access_conflit [i]) += _internal_DCACHE_REQ_NB_ACCESS_CONFLIT [i]; + } +#endif + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl.cpp (revision 88) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::vhdl" + void Dcache_Access::vhdl (void) + { + log_begin(Dcache_Access,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_body.cpp (revision 88) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::vhdl_body" + void Dcache_Access::vhdl_body (Vhdl * & vhdl) + { + log_begin(Dcache_Access,FUNCTION); + vhdl->set_body (""); + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::vhdl_declaration" + void Dcache_Access::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Dcache_Access,FUNCTION); + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters.cpp (revision 88) @@ -0,0 +1,156 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Parameters.h" +#include "Common/include/Max.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::Parameters" + Parameters::Parameters (uint32_t nb_thread , + uint32_t nb_execute_loop , + uint32_t * nb_load_store_unit , + uint32_t * nb_context , + uint32_t ** nb_cache_access , + uint32_t nb_dcache_port , + uint32_t size_address , + uint32_t size_data , + uint32_t size_dcache_thread_id , + uint32_t size_dcache_packet_id , + uint32_t ** size_thread_id , + uint32_t ** size_packet_id , + uint32_t *** table_routing , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t *** translate_load_store_unit_to_thread, + bool is_toplevel ) + { + log_begin(Dcache_Access,FUNCTION); + + _nb_thread = nb_thread ; + _nb_execute_loop = nb_execute_loop ; + _nb_load_store_unit = nb_load_store_unit; + _nb_context = nb_context ; + _nb_cache_access = nb_cache_access ; + _nb_dcache_port = nb_dcache_port ; + _size_address = size_address ; + _size_data = size_data ; + _size_dcache_thread_id = size_dcache_thread_id; + _size_dcache_packet_id = size_dcache_packet_id; + _size_thread_id = size_thread_id ; + _size_packet_id = size_packet_id ; + _table_routing = table_routing ; + _priority = priority ; + _load_balancing = load_balancing ; + _translate_load_store_unit_to_thread = translate_load_store_unit_to_thread; + + test(); + + _max_nb_load_store_unit = max(_nb_load_store_unit, nb_execute_loop); + _max_nb_cache_access = max(_nb_cache_access , _nb_execute_loop, _nb_load_store_unit); + +// _size_dcache_thread_id = (log2(_nb_execute_loop) + +// log2(_max_nb_load_store_unit) + +// log2(_max_nb_cache_access) + +// _max_size_thread_id); + + uint32_t max_size_packet_id= max(_size_packet_id , _nb_execute_loop, _nb_load_store_unit); + + _shift_num_cache_access = max_size_packet_id; + _mask_num_cache_access = gen_mask(log2(_max_nb_cache_access)); + _mask_num_lsq_packet = gen_mask(max_size_packet_id); + + _have_port_dcache_thread_id= _size_dcache_thread_id > 0; + _have_port_dcache_packet_id= _size_dcache_packet_id > 0; + + _have_port_lsq_thread_id = new bool * [_nb_execute_loop]; + _have_port_lsq_packet_id = new bool * [_nb_execute_loop]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + _have_port_lsq_thread_id [i] = new bool [_nb_load_store_unit [i]]; + _have_port_lsq_packet_id [i] = new bool [_nb_load_store_unit [i]]; + + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + { + _have_port_lsq_thread_id [i][j] = _size_thread_id[i][j] > 0; + _have_port_lsq_packet_id [i][j] = _size_packet_id[i][j] > 0; + } + } + + _translate_thread_to_execute_loop = new uint32_t [nb_thread]; + _translate_thread_to_load_store_unit = new uint32_t [nb_thread]; + _translate_thread_to_context = new uint32_t [nb_thread]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + for (uint32_t k=0; k<_nb_context[i]; ++k) + { + uint32_t num_thread = _translate_load_store_unit_to_thread [i][j][k]; + + _translate_thread_to_execute_loop [num_thread] = i; + _translate_thread_to_load_store_unit [num_thread] = j; + _translate_thread_to_context [num_thread] = k; + } + + if (is_toplevel) + { + copy(); + } + + log_end(Dcache_Access,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Dcache_Access::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Dcache_Access,FUNCTION); +// test(); +// log_end(Dcache_Access,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Dcache_Access::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Dcache_Access,FUNCTION); + + delete [] _translate_thread_to_context ; + delete [] _translate_thread_to_load_store_unit; + delete [] _translate_thread_to_execute_loop ; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + delete [] _have_port_lsq_thread_id [i]; + delete [] _have_port_lsq_packet_id [i]; + } + delete [] _have_port_lsq_thread_id; + delete [] _have_port_lsq_packet_id; + + log_end(Dcache_Access,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Dcache_Access::copy" + void Parameters::copy (void) + { + log_begin(Dcache_Access,FUNCTION); + log_end(Dcache_Access,FUNCTION); + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,73 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Dcache_Access/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Dcache_Access,FUNCTION); + + Parameters_test test ("Dcache_Access"); + + bool have_link [_nb_dcache_port]; + for (uint32_t i=0; i<_nb_dcache_port; i++) + have_link [i] = 0; + + for (uint32_t i=0; i<_nb_execute_loop; i++) + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + for (uint32_t k=0; k<_nb_cache_access [i][j]; ++k) + if (_table_routing [i][j][k] >= _nb_dcache_port) + test.error(toString(_("table_routing [%d][%d][%d] : invalid value, must be < nb_dcache_port.\n"),i,j,k)); + else + have_link [_table_routing [i][j][k]] = true; + + for (uint32_t i=0; i<_nb_dcache_port; i++) + if (not have_link [i]) + test.error(toString(_("Port[%d] is not linked.\n"),i)); + + bool thread_link [_nb_thread]; + for (uint32_t i=0; i<_nb_thread; ++i) + thread_link [i] = false; + + for (uint32_t i=0; i<_nb_execute_loop; i++) + for (uint32_t j=0; j<_nb_load_store_unit [i]; j++) + for (uint32_t k=0; k<_nb_context[i]; k++) + { + uint32_t num_thread = _translate_load_store_unit_to_thread [i][j][k]; + if (num_thread >= _nb_thread) + test.error(toString(_("Context [%d][%d][%d] is linked with an invalid thread id.\n"),i,j,k)); + else + if (thread_link [num_thread] == true) + test.error(toString(_("Context [%d][%d][%d] is linked with an already used thread id.\n"),i,j,k)); + else + thread_link [num_thread] = true; + } + + for (uint32_t i=0; i<_nb_thread; ++i) + if (not thread_link [i]) + test.error(toString(_("Thread [%d] is not linked.\n"),i)); + + log_end(Dcache_Access,FUNCTION); + + return test; + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,91 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Dcache_Access/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace dcache_access { + + +#undef FUNCTION +#define FUNCTION "Dcache_Access::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Dcache_Access,FUNCTION); + + XML xml ("dcache_access"); + + xml.balise_open("dcache_access"); + xml.singleton_begin("nb_execute_loop "); xml.attribut("value",toString(_nb_execute_loop )); xml.singleton_end(); + xml.singleton_begin("nb_dcache_port "); xml.attribut("value",toString(_nb_dcache_port )); xml.singleton_end(); + xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); + xml.singleton_begin("size_data "); xml.attribut("value",toString(_size_data )); xml.singleton_end(); + xml.singleton_begin("priority "); xml.attribut("value",toString(_priority )); xml.singleton_end(); + xml.singleton_begin("load_balancing "); xml.attribut("value",toString(_load_balancing )); xml.singleton_end(); + + for (uint32_t i=0;i<_nb_execute_loop; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","execute_loop"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_load_store_unit "); xml.attribut("value",toString(_nb_load_store_unit [i])); xml.singleton_end(); + + for (uint32_t j=0; j<_nb_load_store_unit [i]; ++j) + { + xml. balise_open_begin("component"); + xml. attribut("type","load_store_unit"); + xml. attribut("id" ,toString(j)); + xml. balise_open_end(); + xml.singleton_begin("nb_cache_access "); xml.attribut("value",toString(_nb_cache_access [i][j])); xml.singleton_end(); + xml.singleton_begin("size_thread_id "); xml.attribut("value",toString(_size_thread_id [i][j])); xml.singleton_end(); + xml.singleton_begin("size_packet_id "); xml.attribut("value",toString(_size_packet_id [i][j])); xml.singleton_end(); + + for (uint32_t k=0; k<_nb_cache_access [i][j]; ++k) + { + xml. balise_open_begin("component"); + xml. attribut("type","cache_access"); + xml. attribut("id" ,toString(k)); + xml. balise_open_end(); + xml.singleton_begin("table_routing "); xml.attribut("value",toString(_table_routing [i][j][k])); xml.singleton_end(); + + xml. balise_close(); + } + xml. balise_close(); + } + xml. balise_close(); + } + + xml.balise_close(); + + log_end(Dcache_Access,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Dcache_Access::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::dcache_access::Parameters & x) + { + log_begin(Dcache_Access,FUNCTION); + + output_stream << x.print(0); + + log_end(Dcache_Access,FUNCTION); + + return output_stream; + }; + +}; // end namespace dcache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libIcache_Access.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Icache_Access = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Icache_Access_DIR = $(DIR_MORPHEO)/Behavioural/Core/Icache_Access + +#-----[ Library ]------------------------------------------ + +Icache_Access_LIBRARY = -lIcache_Access \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Icache_Access_DIR_LIBRARY = -L$(Icache_Access_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Icache_Access_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Icache_Access_DIR) --makefile=Makefile; + +Icache_Access_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Icache_Access_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Icache_Access_LIBRARY) + +DIR_LIBRARY = $(Icache_Access_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Icache_Access_library + +library_clean : Icache_Access_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_min.cfg (revision 88) @@ -0,0 +1,10 @@ +Icache_Access +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end1.cfg (revision 88) @@ -0,0 +1,19 @@ +Icache_Access +1 1 +1 # nb_front_end +4 4 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [0][1] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [0][2] [nb_front_end][nb_context] +8 8 +1 # nb_instruction [0][3] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [0][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [0][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [0][3] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][2] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][3] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end2.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_mono_front_end2.cfg (revision 88) @@ -0,0 +1,19 @@ +Icache_Access +1 1 +1 # nb_front_end +4 4 +1 # nb_context [0] [nb_front_end] +2 2 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [0][1] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [0][2] [nb_front_end][nb_context] +8 8 +1 # nb_instruction [0][3] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [0][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [0][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [0][3] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +1 1 +1 # table_routing [0][1] [nb_front_end][nb_context] +1 1 +1 # table_routing [0][2] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][3] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end1.cfg (revision 88) @@ -0,0 +1,27 @@ +Icache_Access +3 3 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +3 3 +1 # nb_context [1] [nb_front_end] +2 2 +1 # nb_context [2] [nb_front_end] +1 1 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][0] [nb_front_end][nb_context] +3 3 +1 # nb_instruction [1][1] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][2] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][0] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][1] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [1][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][0] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][2] [nb_front_end][nb_context] +0 0 +1 # table_routing [2][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [2][1] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end2.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end2.cfg (revision 88) @@ -0,0 +1,27 @@ +Icache_Access +3 3 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +3 3 +1 # nb_context [1] [nb_front_end] +2 2 +1 # nb_context [2] [nb_front_end] +2 2 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][0] [nb_front_end][nb_context] +3 3 +1 # nb_instruction [1][1] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][2] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][0] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][1] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [1][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][0] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +1 1 +1 # table_routing [1][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][1] [nb_front_end][nb_context] +1 1 +1 # table_routing [1][2] [nb_front_end][nb_context] +1 1 +1 # table_routing [2][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [2][1] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end3.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end3.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end3.cfg (revision 88) @@ -0,0 +1,27 @@ +Icache_Access +3 3 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +3 3 +1 # nb_context [1] [nb_front_end] +2 2 +1 # nb_context [2] [nb_front_end] +3 3 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][0] [nb_front_end][nb_context] +3 3 +1 # nb_instruction [1][1] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][2] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][0] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][1] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [1][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][0] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][1] [nb_front_end][nb_context] +2 2 +1 # table_routing [0][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][0] [nb_front_end][nb_context] +1 1 +1 # table_routing [1][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [1][2] [nb_front_end][nb_context] +1 1 +1 # table_routing [2][0] [nb_front_end][nb_context] +2 2 +1 # table_routing [2][1] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end4.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/config_multi_front_end4.cfg (revision 88) @@ -0,0 +1,27 @@ +Icache_Access +3 3 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +3 3 +1 # nb_context [1] [nb_front_end] +2 2 +1 # nb_context [2] [nb_front_end] +4 4 +1 # nb_icache_port +30 30 +1 # size_address +1 1 +1 # nb_instruction [0][0] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][0] [nb_front_end][nb_context] +3 3 +1 # nb_instruction [1][1] [nb_front_end][nb_context] +2 2 +1 # nb_instruction [1][2] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][0] [nb_front_end][nb_context] +4 4 +1 # nb_instruction [2][1] [nb_front_end][nb_context] +2 2 +1 # size_packet_id [0][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][0] [nb_front_end][nb_context] +3 3 +1 # size_packet_id [1][1] [nb_front_end][nb_context] +0 0 +1 # size_packet_id [1][2] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][0] [nb_front_end][nb_context] +1 1 +1 # size_packet_id [2][1] [nb_front_end][nb_context] +0 0 +1 # table_routing [0][0] [nb_front_end][nb_context] +1 1 +1 # table_routing [1][0] [nb_front_end][nb_context] +2 2 +1 # table_routing [1][1] [nb_front_end][nb_context] +3 3 +1 # table_routing [1][2] [nb_front_end][nb_context] +1 1 +1 # table_routing [2][0] [nb_front_end][nb_context] +0 0 +1 # table_routing [2][1] [nb_front_end][nb_context] +0 1 +1 # priority +0 1 +1 # load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/include/test.h (revision 88) @@ -0,0 +1,28 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; + +using namespace morpheo::behavioural::core::icache_access; + +void test (string name, + morpheo::behavioural::core::icache_access::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,157 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/SelfTest/include/test.h" +#include "Common/include/Max.h" + +#define NB_PARAMS 5 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_icache_port (uint32_t )\n")); + err (_(" * size_address (uint32_t )\n")); + err (_(" * nb_instruction [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * size_packet_id [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * table_routing [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+_nb_front_end)) + usage (argc, argv); + + uint32_t _sum_nb_context = 0; + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_context [i] = fromString(argv[x++]); + _sum_nb_context += _nb_context [i]; + } + + if (argc != static_cast(2+NB_PARAMS+_nb_front_end+3*_sum_nb_context)) + usage (argc, argv); + + uint32_t _nb_icache_port = fromString(argv[x++]); + uint32_t _size_address = fromString(argv[x++]); + + uint32_t ** _nb_instruction = new uint32_t * [_nb_front_end]; + uint32_t ** _size_packet_id = new uint32_t * [_nb_front_end]; + uint32_t ** _table_routing = new uint32_t * [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_instruction [i] = new uint32_t [_nb_context[i]]; + _size_packet_id [i] = new uint32_t [_nb_context[i]]; + _table_routing [i] = new uint32_t [_nb_context[i]]; + } + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context [i]; j++) + _nb_instruction [i][j] = fromString(argv[x++]); + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context [i]; j++) + _size_packet_id [i][j] = fromString(argv[x++]); + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context [i]; j++) + _table_routing [i][j] = fromString(argv[x++]); + + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + + uint32_t _size_icache_thread_id = log2(_nb_front_end) + log2(max(_nb_context,_nb_front_end));; + uint32_t _size_icache_packet_id = max(_size_packet_id,_nb_front_end, _nb_context); + + uint32_t _nb_thread = 0; + uint32_t ** _translate_context_to_thread = new uint32_t * [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + _translate_context_to_thread [i] = new uint32_t [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; ++j) + _translate_context_to_thread [i][j] = _nb_thread ++; + } + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::icache_access::Parameters * param = new morpheo::behavioural::core::icache_access::Parameters + (_nb_thread , + _nb_front_end , + _nb_context , + _nb_icache_port , + _size_address , + _size_icache_thread_id , + _size_icache_packet_id , + _nb_instruction , + _size_packet_id , + _table_routing , + _priority , + _load_balancing , + _translate_context_to_thread + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Icache_Access : no error"); + else + TEST_KO("Icache_Access : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_context; + for (uint32_t i=0; i<_nb_front_end; i++) + { + delete [] _nb_instruction [i]; + delete [] _size_packet_id [i]; + delete [] _table_routing [i]; + delete [] _translate_context_to_thread [i]; + } + delete [] _nb_instruction; + delete [] _size_packet_id; + delete [] _table_routing ; + delete [] _translate_context_to_thread; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,306 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Icache_Access/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +typedef struct +{ + uint32_t front_end; + uint32_t context; +} thread_id_t; + +void test (string name, + morpheo::behavioural::core::icache_access::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Icache_Access * _Icache_Access = new Icache_Access + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_address_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_icache_port); + ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_icache_port); + ALLOC2_SC_SIGNAL( in_CONTEXT_REQ_VAL ," in_CONTEXT_REQ_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_CONTEXT_REQ_ACK ,"out_CONTEXT_REQ_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); +//ALLOC2_SC_SIGNAL( in_CONTEXT_REQ_THREAD_ID ," in_CONTEXT_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_CONTEXT_REQ_PACKET_ID ," in_CONTEXT_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_CONTEXT_REQ_ADDRESS ," in_CONTEXT_REQ_ADDRESS ",Ticache_address_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_CONTEXT_REQ_TYPE ," in_CONTEXT_REQ_TYPE ",Ticache_type_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_CONTEXT_RSP_VAL ,"out_CONTEXT_RSP_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_CONTEXT_RSP_ACK ," in_CONTEXT_RSP_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); +//ALLOC2_SC_SIGNAL(out_CONTEXT_RSP_THREAD_ID ,"out_CONTEXT_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_CONTEXT_RSP_PACKET_ID ,"out_CONTEXT_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC3_SC_SIGNAL(out_CONTEXT_RSP_INSTRUCTION,"out_CONTEXT_RSP_INSTRUCTION",Ticache_instruction_t,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + ALLOC2_SC_SIGNAL(out_CONTEXT_RSP_ERROR ,"out_CONTEXT_RSP_ERROR ",Ticache_error_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Icache_Access.\n"),name.c_str()); + + (*(_Icache_Access->in_CLOCK)) (*(in_CLOCK)); + (*(_Icache_Access->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_REQ_VAL ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Icache_Access, in_ICACHE_REQ_ACK ,_param->_nb_icache_port); + if (_param->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port); + if (_param->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_REQ_TYPE ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Icache_Access, in_ICACHE_RSP_VAL ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Icache_Access,out_ICACHE_RSP_ACK ,_param->_nb_icache_port); + if (_param->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Icache_Access, in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port); + if (_param->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Icache_Access, in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port); + INSTANCE2_SC_SIGNAL(_Icache_Access, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + INSTANCE1_SC_SIGNAL(_Icache_Access, in_ICACHE_RSP_ERROR ,_param->_nb_icache_port); + INSTANCE2_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Icache_Access,out_CONTEXT_REQ_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); +//INSTANCE2_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_THREAD_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_TYPE ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Icache_Access, in_CONTEXT_RSP_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); +//INSTANCE2_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_THREAD_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE3_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_INSTRUCTION,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + INSTANCE2_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_ERROR ,_param->_nb_front_end,_param->_nb_context[it1]); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + if (_param->_have_port_packet_id [i][j]) + { + INSTANCE_SC_SIGNAL(_Icache_Access, in_CONTEXT_REQ_PACKET_ID [i][j]); + INSTANCE_SC_SIGNAL(_Icache_Access,out_CONTEXT_RSP_PACKET_ID [i][j]); + } + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const int32_t percent_transaction_req = 75; + const int32_t percent_transaction_rsp = 75; + + thread_id_t link_cache_rsp [_param->_nb_icache_port][_param->_nb_front_end*_param->_max_nb_context]; + uint32_t nb_link_cache_rsp [_param->_nb_icache_port]; + + for (uint32_t i=0; i<_param->_nb_icache_port; i++) + nb_link_cache_rsp [i] = 0; + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + uint32_t x = _param->_table_routing [i][j]; + + link_cache_rsp [x][nb_link_cache_rsp[x]].front_end = i; + link_cache_rsp [x][nb_link_cache_rsp[x]].context = j; + nb_link_cache_rsp[x] ++; + } + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_icache_port; i++) + { + in_ICACHE_REQ_ACK [i]->write((rand()%100)write((rand()%100)write(_param->_translate_context_to_thread[x][y]); + in_ICACHE_RSP_PACKET_ID [i]->write(0); + in_ICACHE_RSP_ERROR [i]->write(0); + + for (uint32_t j=0; j<_param->_icache_nb_instruction[i]; j++) + in_ICACHE_RSP_INSTRUCTION [i][j]->write(0); + } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + in_CONTEXT_REQ_VAL [i][j]->write((rand()%100)write(0); + in_CONTEXT_REQ_PACKET_ID [i][j]->write(0); + in_CONTEXT_REQ_TYPE [i][j]->write(0); + + in_CONTEXT_RSP_ACK [i][j]->write((rand()%100)_nb_icache_port; i++) + { + if (out_ICACHE_REQ_VAL [i]->read() and in_ICACHE_REQ_ACK [i]->read()) + { + LABEL("ICACHE_REQ [%d] - Transaction Accepted.",i); + + nb_request ++; + } + if ( in_ICACHE_RSP_VAL [i]->read() and out_ICACHE_RSP_ACK [i]->read()) + { + LABEL("ICACHE_RSP [%d] - Transaction Accepted.",i); + + nb_respons ++; + } + } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + if (in_CONTEXT_REQ_VAL [i][j]->read() and out_CONTEXT_REQ_ACK [i][j]->read()) + { + LABEL("CONTEXT_REQ [%d][%d] - Transaction Accepted.",i,j); + + uint32_t x=_param->_table_routing[i][j]; + + TEST(Tcontrol_t,out_ICACHE_REQ_VAL[x]->read(), 1); + TEST(Tcontrol_t, in_ICACHE_REQ_ACK[x]->read(), 1); + + TEST(Tcontext_t ,out_ICACHE_REQ_THREAD_ID [x]->read(), _param->_translate_context_to_thread[i][j]); + TEST(Tpacket_t ,out_ICACHE_REQ_PACKET_ID [x]->read(), 0); + TEST(Ticache_address_t,out_ICACHE_REQ_ADDRESS [x]->read(), 0); + TEST(Ticache_type_t ,out_ICACHE_REQ_TYPE [x]->read(), 0); + + nb_request --; + } + + if (out_CONTEXT_RSP_VAL [i][j]->read() and in_CONTEXT_RSP_ACK [i][j]->read()) + { + LABEL("CONTEXT_RSP [%d][%d] - Transaction Accepted.",i,j); + +// public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_RSP_VAL ;//[nb_front_end][nb_context] +// //public : SC_OUT(Tcontext_t ) *** out_CONTEXT_RSP_THREAD_ID ;//[nb_front_end][nb_context] +// public : SC_OUT(Tpacket_t ) *** out_CONTEXT_RSP_PACKET_ID ;//[nb_front_end][nb_context] +// public : SC_OUT(Ticache_instruction_t) **** out_CONTEXT_RSP_INSTRUCTION;//[nb_front_end][nb_context][nb_instruction] +// public : SC_OUT(Ticache_error_t ) *** out_CONTEXT_RSP_ERROR ;//[nb_front_end][nb_context] + + nb_respons --; + } + } + + TEST(int32_t, nb_request, 0); + TEST(int32_t, nb_respons, 0); + + SC_START(1); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port); + DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_icache_port); + DELETE2_SC_SIGNAL( in_CONTEXT_REQ_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_CONTEXT_REQ_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); +//DELETE2_SC_SIGNAL( in_CONTEXT_REQ_THREAD_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_CONTEXT_REQ_PACKET_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_CONTEXT_REQ_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_CONTEXT_REQ_TYPE ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_CONTEXT_RSP_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_CONTEXT_RSP_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); +//DELETE2_SC_SIGNAL(out_CONTEXT_RSP_THREAD_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_CONTEXT_RSP_PACKET_ID ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE3_SC_SIGNAL(out_CONTEXT_RSP_INSTRUCTION,_param->_nb_front_end,_param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + DELETE2_SC_SIGNAL(out_CONTEXT_RSP_ERROR ,_param->_nb_front_end,_param->_nb_context[it1]); + + } +#endif + + delete _Icache_Access; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Icache_Access.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Icache_Access.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Icache_Access.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Icache_Access} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Icache_Access.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Icache_Access.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Icache_Access.h (revision 88) @@ -0,0 +1,171 @@ +#ifndef morpheo_behavioural_core_icache_access_Icache_Access_h +#define morpheo_behavioural_core_icache_access_Icache_Access_h + +/* + * $Id$ + * + * [ Description ] + * + * TODO : + * To implement icache special instruction (prefetch, invalidate, lock), add port here + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Icache_Access/include/Parameters.h" +#include "Behavioural/Core/Icache_Access/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + class Icache_Access +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; + + private : counter_t ** _stat_nb_access; + private : counter_t ** _stat_nb_access_conflit; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET; + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_REQ_VAL ;//[nb_icache_port] + public : SC_IN (Tcontrol_t ) ** in_ICACHE_REQ_ACK ;//[nb_icache_port] + public : SC_OUT(Tcontext_t ) ** out_ICACHE_REQ_THREAD_ID ;//[nb_icache_port] + public : SC_OUT(Tpacket_t ) ** out_ICACHE_REQ_PACKET_ID ;//[nb_icache_port] + public : SC_OUT(Ticache_address_t ) ** out_ICACHE_REQ_ADDRESS ;//[nb_icache_port] + public : SC_OUT(Ticache_type_t ) ** out_ICACHE_REQ_TYPE ;//[nb_icache_port] + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_ICACHE_RSP_VAL ;//[nb_icache_port] + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_RSP_ACK ;//[nb_icache_port] + public : SC_IN (Tcontext_t ) ** in_ICACHE_RSP_THREAD_ID ;//[nb_icache_port] + public : SC_IN (Tpacket_t ) ** in_ICACHE_RSP_PACKET_ID ;//[nb_icache_port] + public : SC_IN (Ticache_instruction_t) *** in_ICACHE_RSP_INSTRUCTION ;//[nb_icache_port][icache_nb_instruction] + public : SC_IN (Ticache_error_t ) ** in_ICACHE_RSP_ERROR ;//[nb_icache_port] + + // ~~~~~[ Interface "context_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_CONTEXT_REQ_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_REQ_ACK ;//[nb_front_end][nb_context] +//public : SC_IN (Tcontext_t ) *** in_CONTEXT_REQ_THREAD_ID ;//[nb_front_end][nb_context] + public : SC_IN (Tpacket_t ) *** in_CONTEXT_REQ_PACKET_ID ;//[nb_front_end][nb_context] + public : SC_IN (Ticache_address_t ) *** in_CONTEXT_REQ_ADDRESS ;//[nb_front_end][nb_context] + public : SC_IN (Ticache_type_t ) *** in_CONTEXT_REQ_TYPE ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface "context_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_CONTEXT_RSP_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_CONTEXT_RSP_ACK ;//[nb_front_end][nb_context] +//public : SC_OUT(Tcontext_t ) *** out_CONTEXT_RSP_THREAD_ID ;//[nb_front_end][nb_context] + public : SC_OUT(Tpacket_t ) *** out_CONTEXT_RSP_PACKET_ID ;//[nb_front_end][nb_context] + public : SC_OUT(Ticache_instruction_t) **** out_CONTEXT_RSP_INSTRUCTION;//[nb_front_end][nb_context][nb_instruction] + public : SC_OUT(Ticache_error_t ) *** out_CONTEXT_RSP_ERROR ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef STATISTICS + private : uint32_t * _internal_ICACHE_REQ_NB_ACCESS ; //[nb_icache_port] + private : uint32_t * _internal_ICACHE_REQ_NB_ACCESS_CONFLIT; //[nb_icache_port] +#endif + +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Icache_Access); +#endif + public : Icache_Access + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Icache_Access (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_req (void); + public : void genMealy_rsp (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Parameters.h (revision 88) @@ -0,0 +1,87 @@ +#ifndef morpheo_behavioural_core_icache_access_Parameters_h +#define morpheo_behavioural_core_icache_access_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_thread ; + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_icache_port ; + public : uint32_t _size_address ; + public : uint32_t _size_icache_thread_id ; + public : uint32_t _size_icache_packet_id ; + public : uint32_t ** _nb_instruction ;//[nb_front_end][nb_context] + public : uint32_t ** _size_packet_id ;//[nb_front_end][nb_context] + public : uint32_t ** _table_routing ;//[nb_front_end][nb_context] + public : Tpriority_t _priority ; + public : Tload_balancing_t _load_balancing ; + public : uint32_t ** _translate_context_to_thread ;//[nb_front_end][nb_context] + + public : uint32_t _max_nb_context ; + public : uint32_t _max_nb_instruction ; + public : uint32_t _size_thread_id ; + public : uint32_t _max_size_packet_id ; + public : Tcontext_t _shift_num_front_end ; + public : Tcontext_t _mask_size_context ; + public : uint32_t * _icache_nb_instruction ;//[nb_icache_port] + public : Tcontext_t * _translate_thread_to_context ;//[nb_thread] + public : Tcontext_t * _translate_thread_to_front_end;//[nb_thread] + + public : bool _have_port_icache_thread_id ; + public : bool _have_port_icache_packet_id ; + public : bool ** _have_port_packet_id ;//[nb_front_end][nb_context] + + //-----[ methods ]----------------------------------------------------------- + public : Parameters + (uint32_t nb_thread , + uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_icache_port , + uint32_t size_address , + uint32_t size_icache_thread_id , + uint32_t size_icache_packet_id , + uint32_t ** nb_instruction , + uint32_t ** size_packet_id , + uint32_t ** table_routing , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t ** translate_context_to_thread, + bool is_toplevel=false); + +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::icache_access::Parameters & x); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/include/Types.h (revision 88) @@ -0,0 +1,25 @@ +#ifndef morpheo_behavioural_core_icache_access_Types_h +#define morpheo_behavioural_core_icache_access_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access.cpp (revision 88) @@ -0,0 +1,240 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::Icache_Access" + Icache_Access::Icache_Access + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::icache_access::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Icache_Access,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Method - genMealy_req"),_name.c_str()); + + SC_METHOD (genMealy_req); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + sensitive << (*(in_ICACHE_REQ_ACK [i])); + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + sensitive << (*(in_CONTEXT_REQ_VAL [i][j])) + << (*(in_CONTEXT_REQ_ADDRESS [i][j])) + << (*(in_CONTEXT_REQ_TYPE [i][j])); + if (_param->_have_port_packet_id [i][j]) + sensitive << (*(in_CONTEXT_REQ_PACKET_ID [i][j])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + for (uint32_t x=0; x<_param->_nb_icache_port; ++x) + { + (*(out_ICACHE_REQ_VAL [i])) (*(in_ICACHE_REQ_ACK [x])); + if (_param->_have_port_icache_thread_id) + (*(out_ICACHE_REQ_THREAD_ID [i])) (*(in_ICACHE_REQ_ACK [x])); + if (_param->_have_port_icache_packet_id) + (*(out_ICACHE_REQ_PACKET_ID [i])) (*(in_ICACHE_REQ_ACK [x])); + (*(out_ICACHE_REQ_ADDRESS [i])) (*(in_ICACHE_REQ_ACK [x])); + (*(out_ICACHE_REQ_TYPE [i])) (*(in_ICACHE_REQ_ACK [x])); + } + for (uint32_t x=0; x<_param->_nb_front_end; ++x) + for (uint32_t y=0; y<_param->_nb_context[x]; ++y) + { + (*(out_ICACHE_REQ_VAL [i])) (*(in_CONTEXT_REQ_VAL [x][y])); + if (_param->_have_port_packet_id [x][y]) + (*(out_ICACHE_REQ_PACKET_ID [i])) (*(in_CONTEXT_REQ_PACKET_ID [x][y])); + (*(out_ICACHE_REQ_ADDRESS [i])) (*(in_CONTEXT_REQ_ADDRESS [x][y])); + (*(out_ICACHE_REQ_TYPE [i])) (*(in_CONTEXT_REQ_TYPE [x][y])); + } + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + for (uint32_t x=0; x<_param->_nb_front_end; ++x) + for (uint32_t y=0; y<_param->_nb_context[x]; ++y) + (*(out_CONTEXT_REQ_ACK [i][j])) (*(in_CONTEXT_REQ_VAL [x][y])); + + for (uint32_t x=0; x<_param->_nb_icache_port; ++x) + (*(out_CONTEXT_REQ_ACK [i][j])) (*(in_ICACHE_REQ_ACK [x])); + } +# endif + + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Method - genMealy_rsp"),_name.c_str()); + + SC_METHOD (genMealy_rsp); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + sensitive << (*(in_ICACHE_RSP_VAL [i])) + << (*(in_ICACHE_RSP_ERROR [i])); + if (_param->_have_port_icache_thread_id) + sensitive << (*(in_ICACHE_RSP_THREAD_ID [i])); + if (_param->_have_port_icache_packet_id) + sensitive << (*(in_ICACHE_RSP_PACKET_ID [i])); + + for (uint32_t j=0; j<_param->_icache_nb_instruction[i]; ++j) + sensitive << (*(in_ICACHE_RSP_INSTRUCTION [i][j])); + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + sensitive << (*(in_CONTEXT_RSP_ACK [i][j])); + + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + if (_param->_have_port_icache_thread_id) + (*(out_ICACHE_RSP_ACK [i])) (*(in_ICACHE_RSP_THREAD_ID [i])); + + for (uint32_t x=0; x<_param->_nb_front_end; ++x) + for (uint32_t y=0; y<_param->_nb_context[x]; ++y) + (*(out_ICACHE_RSP_ACK [i])) (*(in_CONTEXT_RSP_ACK [x][y])); + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + for (uint32_t x=0; x<_param->_nb_icache_port; ++x) + { + if (_param->_have_port_icache_thread_id) + { + (*(out_CONTEXT_RSP_VAL [i][j])) (*(in_ICACHE_RSP_THREAD_ID [x])); + if (_param->_have_port_packet_id [i][j]) + (*(out_CONTEXT_RSP_PACKET_ID [i][j])) (*(in_ICACHE_RSP_THREAD_ID [x])); + (*(out_CONTEXT_RSP_ERROR [i][j])) (*(in_ICACHE_RSP_THREAD_ID [x])); + for (uint32_t k=0; k<_param->_nb_instruction [i][j]; ++k) + (*(out_CONTEXT_RSP_INSTRUCTION [i][j][k])) (*(in_ICACHE_RSP_THREAD_ID [x])); + } + + (*(out_CONTEXT_RSP_VAL [i][j])) (*(in_ICACHE_RSP_VAL [x])); + if (_param->_have_port_packet_id [i][j]) + (*(out_CONTEXT_RSP_PACKET_ID [i][j])) (*(in_ICACHE_RSP_PACKET_ID [x])); + (*(out_CONTEXT_RSP_ERROR [i][j])) (*(in_ICACHE_RSP_ERROR [x])); + for (uint32_t k=0; k<_param->_nb_instruction [i][j]; ++k) + for (uint32_t y=0; y<_param->_icache_nb_instruction[x]; ++y) + (*(out_CONTEXT_RSP_INSTRUCTION [i][j][k])) (*(in_ICACHE_RSP_INSTRUCTION [x][y])); + } +# endif + +#endif + } + log_end(Icache_Access,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Icache_Access::~Icache_Access" + Icache_Access::~Icache_Access (void) + { + log_begin(Icache_Access,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_allocation.cpp (revision 88) @@ -0,0 +1,142 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + + +#undef FUNCTION +#define FUNCTION "Icache_Access::allocation" + void Icache_Access::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Icache_Access,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Icache_Access" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); + + ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_icache_thread_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_icache_packet_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_address ); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); + + ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_icache_thread_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_icache_packet_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ); + } + { + // NOTE : max_nb_instruction is too wide ... + ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + + _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + } + + // ~~~~~[ Interface "context_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("context_req",EAST,IN ,_("Request from context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_CONTEXT_REQ_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_CONTEXT_REQ_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); +// _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_); + _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id[it1][it2],_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_address ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_CONTEXT_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface "context_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_OUT(out_CONTEXT_RSP_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_IN ( in_CONTEXT_RSP_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); +// _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_ ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id[it1][it2],_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_CONTEXT_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ,_param->_nb_front_end, _param->_nb_context[it1]); + } + { + ALLOC3_INTERFACE("context_rsp",EAST,OUT,_("Respons to context_unit."),_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + + _ALLOC3_SIGNAL_OUT(out_CONTEXT_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2]); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef STATISTICS + _internal_ICACHE_REQ_NB_ACCESS = new uint32_t [_param->_nb_icache_port]; + _internal_ICACHE_REQ_NB_ACCESS_CONFLIT = new uint32_t [_param->_nb_icache_port]; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority = new generic::priority::Priority (_name+"_priority", + _param->_priority , + _param->_load_balancing, + _param->_nb_front_end , + _param->_nb_context , + _param->_nb_front_end ); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_deallocation.cpp (revision 88) @@ -0,0 +1,75 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::deallocation" + void Icache_Access::deallocation (void) + { + log_begin(Icache_Access,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port,_param->_size_icache_thread_id); + DELETE1_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port,_param->_size_icache_packet_id); + DELETE1_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port,_param->_size_address); + DELETE1_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_icache_port,_param->_size_icache_type); + + DELETE1_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port,_param->_size_icache_thread_id); + DELETE1_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port,_param->_size_icache_packet_id); + DELETE1_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_icache_port,_param->_size_icache_error); + DELETE2_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1],_param->_size_instruction); + + DELETE2_SIGNAL( in_CONTEXT_REQ_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_CONTEXT_REQ_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1 ); +// DELETE2_SIGNAL( in_CONTEXT_REQ_THREAD_ID ,_param->_size_); + DELETE2_SIGNAL( in_CONTEXT_REQ_PACKET_ID ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_packet_id[it1][it2]); + DELETE2_SIGNAL( in_CONTEXT_REQ_ADDRESS ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_address ); + DELETE2_SIGNAL( in_CONTEXT_REQ_TYPE ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_icache_type ); + + DELETE2_SIGNAL(out_CONTEXT_RSP_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_CONTEXT_RSP_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1 ); +// DELETE2_SIGNAL(out_CONTEXT_RSP_THREAD_ID ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_ ); + DELETE2_SIGNAL(out_CONTEXT_RSP_PACKET_ID ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_packet_id[it1][it2]); + DELETE2_SIGNAL(out_CONTEXT_RSP_ERROR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_icache_error ); + DELETE3_SIGNAL(out_CONTEXT_RSP_INSTRUCTION,_param->_nb_front_end, _param->_nb_context[it1],_param->_nb_instruction[it1][it2],_param->_size_instruction ); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#ifdef STATISTICS + delete [] _internal_ICACHE_REQ_NB_ACCESS ; + delete [] _internal_ICACHE_REQ_NB_ACCESS_CONFLIT; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _priority; + + delete _component; + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_end_cycle.cpp (revision 88) @@ -0,0 +1,43 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::end_cycle" +void Icache_Access::end_cycle () + { + log_begin(Icache_Access,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_req.cpp (revision 88) @@ -0,0 +1,91 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::genMealy_req" + void Icache_Access::genMealy_req (void) + { + log_begin(Icache_Access,FUNCTION); + + Tcontrol_t icache_req_val [_param->_nb_icache_port]; + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + icache_req_val [i] = 0; + +#ifdef STATISTICS + _internal_ICACHE_REQ_NB_ACCESS [i] = 0; + _internal_ICACHE_REQ_NB_ACCESS_CONFLIT [i] = 0; +#endif + } + + Tcontrol_t context_req_ack [_param->_nb_front_end][_param->_max_nb_context]; + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + context_req_ack [i][j] = 0; + + std::list * select = _priority ->select(); + for (std::list::iterator it=select ->begin(); + it!=select->end(); + ++it) + { + uint32_t num_front_end = it->grp; + uint32_t num_context = it->elt; + + if (PORT_READ(in_CONTEXT_REQ_VAL [num_front_end][num_context])) + { + uint32_t num_port = _param->_table_routing[num_front_end][num_context]; + Tcontrol_t icache_req_ack = PORT_READ(in_ICACHE_REQ_ACK [num_port]); + +#ifdef STATISTICS + if (icache_req_ack) + { + _internal_ICACHE_REQ_NB_ACCESS [num_port] ++; + if (icache_req_val [num_port]) + _internal_ICACHE_REQ_NB_ACCESS_CONFLIT [num_port] ++; + } +#endif + if (not icache_req_val [num_port]) + { + icache_req_val [num_port] = 1; + context_req_ack [num_front_end][num_context] = icache_req_ack; + + if (_param->_have_port_icache_thread_id) + PORT_WRITE(out_ICACHE_REQ_THREAD_ID [num_port], _param->_translate_context_to_thread[num_front_end][num_context]); +// if (_param->_have_port_icache_packet_id) + if (_param->_have_port_packet_id [num_front_end][num_context]) + PORT_WRITE(out_ICACHE_REQ_PACKET_ID [num_port], PORT_READ(in_CONTEXT_REQ_PACKET_ID [num_front_end][num_context])); + PORT_WRITE(out_ICACHE_REQ_ADDRESS [num_port], PORT_READ(in_CONTEXT_REQ_ADDRESS [num_front_end][num_context])); + PORT_WRITE(out_ICACHE_REQ_TYPE [num_port], PORT_READ(in_CONTEXT_REQ_TYPE [num_front_end][num_context])); + } + } + } + + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + PORT_WRITE(out_ICACHE_REQ_VAL [i], icache_req_val [i]); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + PORT_WRITE(out_CONTEXT_REQ_ACK [i][j], context_req_ack [i][j]); + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_rsp.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_rsp.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_genMealy_rsp.cpp (revision 88) @@ -0,0 +1,89 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::genMealy_rsp" + void Icache_Access::genMealy_rsp (void) + { + log_begin(Icache_Access,FUNCTION); + + Tcontrol_t context_rsp_val [_param->_nb_front_end][_param->_max_nb_context]; + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + context_rsp_val [i][j] = 0; + + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + Tcontrol_t val = PORT_READ(in_ICACHE_RSP_VAL [i]); + Tcontrol_t ack; + + Tcontext_t thread_id = (_param->_have_port_icache_thread_id)?PORT_READ(in_ICACHE_RSP_THREAD_ID [i]):0; + +#ifdef DEBUG_TEST + if (thread_id > _param->_nb_thread) + throw ERRORMORPHEO(FUNCTION,_("invalid thread_id.\n")); +#endif + + if (val) + { + Tcontext_t front_end_id = _param->_translate_thread_to_context [thread_id]; + Tcontext_t context_id = _param->_translate_thread_to_front_end[thread_id]; + +// log_printf(TRACE,Icache_Access,FUNCTION,"thread_id : %d",thread_id); +// log_printf(TRACE,Icache_Access,FUNCTION,"front_end_id : %d",front_end_id); +// log_printf(TRACE,Icache_Access,FUNCTION,"context_id : %d",context_id); + +#ifdef DEBUG_TEST + if (front_end_id > _param->_nb_front_end) + throw ERRORMORPHEO(FUNCTION,_("invalid front_end_id.\n")); + + if (context_id > _param->_nb_context[front_end_id]) + throw ERRORMORPHEO(FUNCTION,_("invalid context_id.\n")); + + if (_param->_table_routing [front_end_id][context_id] != i) + throw ERRORMORPHEO(FUNCTION,_("invalid route.\n")); +#endif + + ack = PORT_READ(in_CONTEXT_RSP_ACK [front_end_id][context_id]); + + context_rsp_val [front_end_id][context_id] = 1; +// if (_param->_have_port_icache_packet_id) + if (_param->_have_port_packet_id [front_end_id][context_id]) + PORT_WRITE(out_CONTEXT_RSP_PACKET_ID [front_end_id][context_id], PORT_READ(in_ICACHE_RSP_PACKET_ID [i])); + PORT_WRITE(out_CONTEXT_RSP_ERROR [front_end_id][context_id], PORT_READ(in_ICACHE_RSP_ERROR [i])); + + for (uint32_t j=0; j<_param->_nb_instruction [front_end_id][context_id]; ++j) + PORT_WRITE(out_CONTEXT_RSP_INSTRUCTION [front_end_id][context_id][j], PORT_READ(in_ICACHE_RSP_INSTRUCTION [i][j])); + } + else + ack = 0; + + PORT_WRITE(out_ICACHE_RSP_ACK [i],ack); + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + PORT_WRITE(out_CONTEXT_RSP_VAL [i][j], context_rsp_val [i][j]); + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_allocation.cpp (revision 88) @@ -0,0 +1,69 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::statistics_allocation" + void Icache_Access::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Icache_Access,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Icache_Access", + param_statistics); + + _stat_nb_access = new counter_t * [_param->_nb_icache_port]; + _stat_nb_access_conflit = new counter_t * [_param->_nb_icache_port]; + + std::string _sum_nb_access = ""; + std::string _sum_nb_access_conflit = ""; + + for (uint32_t i=0; i<_param->_nb_icache_port; i++) + { + _stat_nb_access [i] = _stat->create_counter("nb_access_" +toString(i),"",toString(_("Total access achieved by all contexts (port %d)"),i)); + _stat_nb_access_conflit [i] = _stat->create_counter("nb_access_conflit_"+toString(i),"",toString(_("Total access conducting a conflict (port %d)"),i)); + + if (i == 0) + { + _sum_nb_access = "nb_access_0"; + _sum_nb_access_conflit = "nb_access_conflit_0"; + } + else + { + _sum_nb_access = "+ nb_access_" +toString(i)+" "+ _sum_nb_access ; + _sum_nb_access_conflit = "+ nb_access_conflit_" +toString(i)+" "+ _sum_nb_access_conflit; + } + + _stat->create_expr_percent ("percent_access_conflit_"+toString(i), "nb_access_conflit_"+toString(i), "nb_access_"+toString(i),toString(_("Percent for total access conducting a conflict (port %d)"),i)); + + + _stat->create_expr_average_by_cycle ("average_nb_icache_access_"+toString(i),"- nb_access_"+toString(i)+" nb_access_conflit_"+toString(i),"",toString(_("Average of icache access (port %d)"),i)); + } + + _stat->create_expr ("nb_access" , _sum_nb_access , TYPE_COUNTER, "", _("Total access achieved by all contexts (all port)")); + _stat->create_expr ("nb_access_conflit", _sum_nb_access_conflit, TYPE_COUNTER, "", _("Total access conducting a conflict (all port)")); + + _stat->create_expr_percent ("percent_access_conflit", _sum_nb_access_conflit, _sum_nb_access,_("Percent for total access conducting a conflict")); + + _stat->create_expr_average_by_cycle ("average_nb_icache_access","- nb_access nb_access_conflit","",_("Average of icache access (all port)")); + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::statistics_deallocation" + void Icache_Access::statistics_deallocation (void) + { + log_begin(Icache_Access,FUNCTION); + + log_printf(INFO,Icache_Access,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + delete [] _stat_nb_access; + delete [] _stat_nb_access_conflit; + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_transition.cpp (revision 88) @@ -0,0 +1,54 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::transition" + void Icache_Access::transition (void) + { + log_begin(Icache_Access,FUNCTION); + + if (PORT_READ(in_NRESET) == 0) + { + _priority->reset(); + } + else + { + // next priority + _priority->transition(); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_icache_port;i++) + { + (*_stat_nb_access [i]) += _internal_ICACHE_REQ_NB_ACCESS [i]; + (*_stat_nb_access_conflit [i]) += _internal_ICACHE_REQ_NB_ACCESS_CONFLIT [i]; + } +#endif + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl.cpp (revision 88) @@ -0,0 +1,44 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::vhdl" + void Icache_Access::vhdl (void) + { + log_begin(Icache_Access,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_body.cpp (revision 88) @@ -0,0 +1,31 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::vhdl_body" + void Icache_Access::vhdl_body (Vhdl * & vhdl) + { + log_begin(Icache_Access,FUNCTION); + vhdl->set_body (""); + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Icache_Access_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,30 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::vhdl_declaration" + void Icache_Access::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Icache_Access,FUNCTION); + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters.cpp (revision 88) @@ -0,0 +1,145 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Parameters.h" +#include "Common/include/Max.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::Parameters" + Parameters::Parameters (uint32_t nb_thread , + uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_icache_port , + uint32_t size_address , + uint32_t size_icache_thread_id , + uint32_t size_icache_packet_id , + uint32_t ** nb_instruction , + uint32_t ** size_packet_id , + uint32_t ** table_routing , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t ** translate_context_to_thread, + bool is_toplevel ) + { + log_begin(Icache_Access,FUNCTION); + + _nb_thread = nb_thread ; + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_icache_port = nb_icache_port; + _size_address = size_address ; + _size_icache_thread_id = size_icache_thread_id; + _size_icache_packet_id = size_icache_packet_id; + _nb_instruction = nb_instruction; + _size_packet_id = size_packet_id; + _table_routing = table_routing ; + _priority = priority ; + _load_balancing = load_balancing; + _translate_context_to_thread = translate_context_to_thread; + + test(); + + _have_port_icache_thread_id = _size_icache_thread_id>0; + _have_port_icache_packet_id = _size_icache_packet_id>0; + + + _translate_thread_to_context = new Tcontext_t [_nb_thread]; + _translate_thread_to_front_end = new Tcontext_t [_nb_thread]; + + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + { + uint32_t num_thread = translate_context_to_thread[i][j]; + + _translate_thread_to_context [num_thread] = i; + _translate_thread_to_front_end [num_thread] = j; + } + + _icache_nb_instruction = new uint32_t [_nb_icache_port]; + for (uint32_t i=0; i<_nb_icache_port; ++i) + _icache_nb_instruction [i] = 0; + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context[i]; j++) + { + uint32_t port = _table_routing [i][j]; + + // Take the greater + if (_icache_nb_instruction[port] < _nb_instruction [i][j]) + _icache_nb_instruction[port] = _nb_instruction [i][j]; + } + + _have_port_packet_id = new bool * [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _have_port_packet_id [i] = new bool [_nb_context [i]]; + + for (uint32_t j=0; j<_nb_context[i]; j++) + _have_port_packet_id [i][j] = _size_packet_id [i][j] > 0; + } + + _max_nb_context = max(_nb_context,_nb_front_end); + _max_nb_instruction = max(_nb_instruction,_nb_front_end,_nb_context); + _size_thread_id = log2(_nb_front_end) + log2(_max_nb_context); + _max_size_packet_id = max(_size_packet_id,_nb_front_end, _nb_context); + + _shift_num_front_end = log2(_max_nb_context); + _mask_size_context = gen_mask(log2(_max_nb_context)); + + if (is_toplevel) + { + copy (); + } + + log_end(Icache_Access,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Icache_Access::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Icache_Access,FUNCTION); +// test(); +// log_end(Icache_Access,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Icache_Access::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Icache_Access,FUNCTION); + + for (uint32_t i=0; i<_nb_front_end; i++) + delete [] _have_port_packet_id [i]; + delete [] _have_port_packet_id; + delete [] _icache_nb_instruction; + + delete [] _translate_thread_to_front_end; + delete [] _translate_thread_to_context ; + + log_end(Icache_Access,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Icache_Access::copy" + void Parameters::copy (void) + { + log_begin(Icache_Access,FUNCTION); + log_end(Icache_Access,FUNCTION); + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,71 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Icache_Access/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Icache_Access,FUNCTION); + + Parameters_test test ("Icache_Access"); + + bool have_link [_nb_icache_port]; + for (uint32_t i=0; i<_nb_icache_port; i++) + have_link [i] = 0; + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context [i]; j++) + if (_table_routing [i][j] >= _nb_icache_port) + test.error(toString(_("table_routing [%d][%d] : invalid value, must be < nb_icache_port.\n"),i,j)); + else + have_link [_table_routing [i][j]] = true; + + for (uint32_t i=0; i<_nb_icache_port; i++) + if (not have_link [i]) + test.error(toString(_("Port[%d] is not linked.\n"),i)); + + bool thread_link [_nb_thread]; + for (uint32_t i=0; i<_nb_thread; ++i) + thread_link [i] = false; + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context [i]; j++) + { + uint32_t num_thread = _translate_context_to_thread [i][j]; + if (num_thread >= _nb_thread) + test.error(toString(_("Context [%d][%d] is linked with an invalid thread id.\n"),i,j)); + else + if (thread_link [num_thread] == true) + test.error(toString(_("Context [%d][%d] is linked with an already used thread id.\n"),i,j)); + else + thread_link [num_thread] = true; + } + + for (uint32_t i=0; i<_nb_thread; ++i) + if (not thread_link [i]) + test.error(toString(_("Thread [%d] is not linked.\n"),i)); + + log_end(Icache_Access,FUNCTION); + + return test; + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Icache_Access/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,78 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Icache_Access/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace icache_access { + + +#undef FUNCTION +#define FUNCTION "Icache_Access::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Icache_Access,FUNCTION); + + XML xml ("icache_access"); + + xml.balise_open("icache_access"); + xml.singleton_begin("nb_front_end "); xml.attribut("value",toString(_nb_front_end )); xml.singleton_end(); + xml.singleton_begin("nb_icache_port "); xml.attribut("value",toString(_nb_icache_port )); xml.singleton_end(); + xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); + xml.singleton_begin("priority "); xml.attribut("value",toString(_priority )); xml.singleton_end(); + xml.singleton_begin("load_balancing "); xml.attribut("value",toString(_load_balancing )); xml.singleton_end(); + for (uint32_t i=0;i<_nb_front_end; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","front_end"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context [i])); xml.singleton_end(); + + for (uint32_t j=0;j<_nb_context [i]; j++) + { + xml. balise_open_begin("component"); + xml. attribut("type","context"); + xml. attribut("id" ,toString(j)); + xml. balise_open_end(); + xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction [i][j])); xml.singleton_end(); + xml.singleton_begin("size_packet_id "); xml.attribut("value",toString(_size_packet_id [i][j])); xml.singleton_end(); + xml.singleton_begin("table_routing "); xml.attribut("value",toString(_table_routing [i][j])); xml.singleton_end(); + xml. balise_close(); + } + xml. balise_close(); + } + + xml.balise_close(); + + log_end(Icache_Access,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Icache_Access::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::icache_access::Parameters & x) + { + log_begin(Icache_Access,FUNCTION); + + output_stream << x.print(0); + + log_end(Icache_Access,FUNCTION); + + return output_stream; + }; + +}; // end namespace icache_access +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libCore.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Makefile.deps (revision 88) @@ -0,0 +1,80 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Core = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Icache_Access +include $(DIR_MORPHEO)/Behavioural/Core/Icache_Access/Makefile.deps +endif +ifndef Dcache_Access +include $(DIR_MORPHEO)/Behavioural/Core/Dcache_Access/Makefile.deps +endif +ifndef Multi_Front_end +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Makefile.deps +endif +ifndef Multi_OOO_Engine +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.deps +endif +ifndef Multi_Execute_loop +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Makefile.deps +endif +ifndef Core_Glue +include $(DIR_MORPHEO)/Behavioural/Core/Core_Glue/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Core_DIR = $(DIR_MORPHEO)/Behavioural/Core + +#-----[ Library ]------------------------------------------ + +Core_LIBRARY = -lCore \ + $(Icache_Access_LIBRARY) \ + $(Dcache_Access_LIBRARY) \ + $(Front_end_LIBRARY) \ + $(OOO_Engine_LIBRARY) \ + $(Execute_loop_LIBRARY) \ + $(Core_Glue_LIBRARY) \ + $(Behavioural_LIBRARY) + +Core_DIR_LIBRARY = -L$(Core_DIR)/lib \ + $(Icache_Access_DIR_LIBRARY) \ + $(Dcache_Access_DIR_LIBRARY) \ + $(Front_end_DIR_LIBRARY) \ + $(OOO_Engine_DIR_LIBRARY) \ + $(Execute_loop_DIR_LIBRARY) \ + $(Core_Glue_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Core_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Icache_Access_library; \ + $(MAKE) Dcache_Access_library; \ + $(MAKE) Front_end_library; \ + $(MAKE) OOO_Engine_library; \ + $(MAKE) Execute_loop_library; \ + $(MAKE) Core_Glue_library; \ + $(MAKE) --directory=$(Core_DIR) --makefile=Makefile; + +Core_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Icache_Access_library_clean; \ + $(MAKE) Dcache_Access_library_clean; \ + $(MAKE) Front_end_library_clean; \ + $(MAKE) OOO_Engine_library_clean; \ + $(MAKE) Execute_loop_library_clean; \ + $(MAKE) Core_Glue_library_clean; \ + $(MAKE) --directory=$(Core_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libExecute_loop_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.deps (revision 88) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Execute_loop_Glue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Execute_loop_Glue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue + +#-----[ Library ]------------------------------------------ + +Execute_loop_Glue_LIBRARY = -lExecute_loop_Glue \ + $(Behavioural_LIBRARY) + +Execute_loop_Glue_DIR_LIBRARY = -L$(Execute_loop_Glue_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Execute_loop_Glue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Execute_loop_Glue_DIR) --makefile=Makefile; + +Execute_loop_Glue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Execute_loop_Glue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Execute_loop_Glue_LIBRARY) + +DIR_LIBRARY = $(Execute_loop_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Execute_loop_Glue_library + +library_clean : Execute_loop_Glue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/configuration.cfg (revision 88) @@ -0,0 +1,8 @@ +Execute_loop_Glue +1 4 *4 # nb_gpr_write +1 4 *4 # nb_spr_write +0 2 +1 # size_ooo_engine_id +6 6 *2 # size_general_register +4 4 *2 # size_special_register +32 32 *2 # size_general_data +2 2 *2 # size_special_data Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_execute_loop; +using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop; + +using namespace morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue; + +void test (string name, + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,86 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 7 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_gpr_write (uint32_t)\n")); + err (_(" * nb_spr_write (uint32_t)\n")); + err (_(" * size_ooo_engine_id (uint32_t)\n")); + err (_(" * size_general_register (uint32_t)\n")); + err (_(" * size_special_register (uint32_t)\n")); + err (_(" * size_general_data (uint32_t)\n")); + err (_(" * size_special_data (uint32_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc != static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + uint32_t _nb_gpr_write = fromString(argv[x++]); + uint32_t _nb_spr_write = fromString(argv[x++]); + uint32_t _size_ooo_engine_id = fromString(argv[x++]); + uint32_t _size_general_register = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters + ( + _nb_gpr_write , + _nb_spr_write , + _size_ooo_engine_id , + _size_general_register , + _size_special_register , + _size_general_data , + _size_special_data , + true // is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Execute_loop_Glue : no error"); + else + TEST_KO("Execute_loop_Glue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,213 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Execute_loop_Glue * _Execute_loop_Glue = new Execute_loop_Glue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_VAL ," in_GPR_WRITE_WRITE_UNIT_VAL ",Tcontrol_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_WRITE_UNIT_ACK ,"out_GPR_WRITE_WRITE_UNIT_ACK ",Tcontrol_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ," in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_NUM_REG ," in_GPR_WRITE_WRITE_UNIT_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_DATA ," in_GPR_WRITE_WRITE_UNIT_DATA ",Tgeneral_data_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_VAL ,"out_GPR_WRITE_REGISTER_FILE_VAL ",Tcontrol_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL( in_GPR_WRITE_REGISTER_FILE_ACK ," in_GPR_WRITE_REGISTER_FILE_ACK ",Tcontrol_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,"out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID",Tcontext_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_NUM_REG ,"out_GPR_WRITE_REGISTER_FILE_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_DATA ,"out_GPR_WRITE_REGISTER_FILE_DATA ",Tgeneral_data_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_VAL ,"out_GPR_WRITE_READ_UNIT_VAL ",Tcontrol_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,"out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_NUM_REG ,"out_GPR_WRITE_READ_UNIT_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_DATA ,"out_GPR_WRITE_READ_UNIT_DATA ",Tgeneral_data_t ,_param->_nb_gpr_write); + ALLOC1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_VAL ," in_SPR_WRITE_WRITE_UNIT_VAL ",Tcontrol_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_WRITE_UNIT_ACK ,"out_SPR_WRITE_WRITE_UNIT_ACK ",Tcontrol_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ," in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_NUM_REG ," in_SPR_WRITE_WRITE_UNIT_NUM_REG ",Tspecial_address_t,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_DATA ," in_SPR_WRITE_WRITE_UNIT_DATA ",Tspecial_data_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_VAL ,"out_SPR_WRITE_REGISTER_FILE_VAL ",Tcontrol_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL( in_SPR_WRITE_REGISTER_FILE_ACK ," in_SPR_WRITE_REGISTER_FILE_ACK ",Tcontrol_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,"out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID",Tcontext_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_NUM_REG ,"out_SPR_WRITE_REGISTER_FILE_NUM_REG ",Tspecial_address_t,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_DATA ,"out_SPR_WRITE_REGISTER_FILE_DATA ",Tspecial_data_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_VAL ,"out_SPR_WRITE_READ_UNIT_VAL ",Tcontrol_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,"out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_NUM_REG ,"out_SPR_WRITE_READ_UNIT_NUM_REG ",Tspecial_address_t,_param->_nb_spr_write); + ALLOC1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_DATA ,"out_SPR_WRITE_READ_UNIT_DATA ",Tspecial_data_t ,_param->_nb_spr_write); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Execute_loop_Glue.\n"),name.c_str()); + + (*(_Execute_loop_Glue->in_CLOCK)) (*(in_CLOCK)); + (*(_Execute_loop_Glue->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_GPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_gpr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_GPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_GPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_gpr_write); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_GPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_gpr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_gpr_write); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_READ_UNIT_VAL ,_param->_nb_gpr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_gpr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_GPR_WRITE_READ_UNIT_DATA ,_param->_nb_gpr_write); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_SPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_spr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_SPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_SPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_spr_write); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue, in_SPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_spr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_spr_write); + + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_READ_UNIT_VAL ,_param->_nb_spr_write); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_spr_write); + INSTANCE1_SC_SIGNAL(_Execute_loop_Glue,out_SPR_WRITE_READ_UNIT_DATA ,_param->_nb_spr_write); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL( in_GPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_gpr_write); + + DELETE1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL( in_GPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_gpr_write); + + DELETE1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_VAL ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_gpr_write); + DELETE1_SC_SIGNAL(out_GPR_WRITE_READ_UNIT_DATA ,_param->_nb_gpr_write); + + DELETE1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL( in_SPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_spr_write); + + DELETE1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL( in_SPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_spr_write); + + DELETE1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_VAL ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_spr_write); + DELETE1_SC_SIGNAL(out_SPR_WRITE_READ_UNIT_DATA ,_param->_nb_spr_write); + } +#endif + + delete _Execute_loop_Glue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Execute_loop_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Execute_loop_Glue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Execute_loop_Glue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Execute_loop_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h (revision 88) @@ -0,0 +1,171 @@ +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Execute_loop_Glue_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Execute_loop_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + + class Execute_loop_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // -----[ Interface "gpr_write_write_unit" ]-------------------------- + public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_WRITE_UNIT_VAL ; + public : SC_OUT(Tcontrol_t ) ** out_GPR_WRITE_WRITE_UNIT_ACK ; + public : SC_IN (Tcontext_t ) ** in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ; + public : SC_IN (Tgeneral_address_t) ** in_GPR_WRITE_WRITE_UNIT_NUM_REG ; + public : SC_IN (Tgeneral_data_t ) ** in_GPR_WRITE_WRITE_UNIT_DATA ; + + // -----[ Interface "gpr_write_register_file" ]----------------------- + public : SC_OUT(Tcontrol_t ) ** out_GPR_WRITE_REGISTER_FILE_VAL ; + public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_REGISTER_FILE_ACK ; + public : SC_OUT(Tcontext_t ) ** out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ; + public : SC_OUT(Tgeneral_address_t) ** out_GPR_WRITE_REGISTER_FILE_NUM_REG ; + public : SC_OUT(Tgeneral_data_t ) ** out_GPR_WRITE_REGISTER_FILE_DATA ; + + // -----[ Interface "gpr_write_read_unit" ]--------------------------- + public : SC_OUT(Tcontrol_t ) ** out_GPR_WRITE_READ_UNIT_VAL ; + public : SC_OUT(Tcontext_t ) ** out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ; + public : SC_OUT(Tgeneral_address_t) ** out_GPR_WRITE_READ_UNIT_NUM_REG ; + public : SC_OUT(Tgeneral_data_t ) ** out_GPR_WRITE_READ_UNIT_DATA ; + + // -----[ Interface "spr_write_write_unit" ]-------------------------- + public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_WRITE_UNIT_VAL ; + public : SC_OUT(Tcontrol_t ) ** out_SPR_WRITE_WRITE_UNIT_ACK ; + public : SC_IN (Tcontext_t ) ** in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ; + public : SC_IN (Tspecial_address_t) ** in_SPR_WRITE_WRITE_UNIT_NUM_REG ; + public : SC_IN (Tspecial_data_t ) ** in_SPR_WRITE_WRITE_UNIT_DATA ; + + // -----[ Interface "spr_write_register_file" ]----------------------- + public : SC_OUT(Tcontrol_t ) ** out_SPR_WRITE_REGISTER_FILE_VAL ; + public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_REGISTER_FILE_ACK ; + public : SC_OUT(Tcontext_t ) ** out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ; + public : SC_OUT(Tspecial_address_t) ** out_SPR_WRITE_REGISTER_FILE_NUM_REG ; + public : SC_OUT(Tspecial_data_t ) ** out_SPR_WRITE_REGISTER_FILE_DATA ; + + // -----[ Interface "spr_write_read_unit" ]--------------------------- + public : SC_OUT(Tcontrol_t ) ** out_SPR_WRITE_READ_UNIT_VAL ; + public : SC_OUT(Tcontext_t ) ** out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ; + public : SC_OUT(Tspecial_address_t) ** out_SPR_WRITE_READ_UNIT_NUM_REG ; + public : SC_OUT(Tspecial_data_t ) ** out_SPR_WRITE_READ_UNIT_DATA ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Execute_loop_Glue); +#endif + public : Execute_loop_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Execute_loop_Glue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_gpr_write (void); + public : void genMealy_spr_write (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h (revision 88) @@ -0,0 +1,64 @@ +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Parameters_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + +//public : bool _have_port_ooo_engine_id; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_gpr_write , + uint32_t nb_spr_write , + uint32_t size_ooo_engine_id , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_general_data , + uint32_t size_special_data , + bool is_toplevel=false ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters & x); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Types.h (revision 88) @@ -0,0 +1,29 @@ +#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Types_h +#define morpheo_behavioural_core_multi_execute_loop_execute_loop_execute_loop_glue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue.cpp (revision 88) @@ -0,0 +1,197 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::Execute_loop_Glue" + Execute_loop_Glue::Execute_loop_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Execute_loop_Glue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Execute_loop_Glue == true + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Method - genMealy_gpr_write"),_name.c_str()); + + SC_METHOD (genMealy_gpr_write); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't internal register + + for (uint32_t i=0; i<_param->_nb_gpr_write; i++) + { + sensitive <<(*(in_GPR_WRITE_WRITE_UNIT_VAL [i])) + <<(*(in_GPR_WRITE_WRITE_UNIT_NUM_REG [i])) + <<(*(in_GPR_WRITE_WRITE_UNIT_DATA [i])) + <<(*(in_GPR_WRITE_REGISTER_FILE_ACK [i])); + if (_param->_have_port_ooo_engine_id) + sensitive <<(*(in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_gpr_write; i++) + { + (*(out_GPR_WRITE_WRITE_UNIT_ACK [i])) (*( in_GPR_WRITE_REGISTER_FILE_ACK [i])); + (*(out_GPR_WRITE_REGISTER_FILE_VAL [i])) (*( in_GPR_WRITE_WRITE_UNIT_VAL [i])); + if (_param->_have_port_ooo_engine_id) + (*(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + (*(out_GPR_WRITE_REGISTER_FILE_NUM_REG [i])) (*( in_GPR_WRITE_WRITE_UNIT_NUM_REG [i])); + (*(out_GPR_WRITE_REGISTER_FILE_DATA [i])) (*( in_GPR_WRITE_WRITE_UNIT_DATA [i])); + (*(out_GPR_WRITE_READ_UNIT_VAL [i])) (*( in_GPR_WRITE_WRITE_UNIT_VAL [i])); + (*(out_GPR_WRITE_READ_UNIT_VAL [i])) (*( in_GPR_WRITE_REGISTER_FILE_ACK [i])); + if (_param->_have_port_ooo_engine_id) + (*(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + (*(out_GPR_WRITE_READ_UNIT_NUM_REG [i])) (*( in_GPR_WRITE_WRITE_UNIT_NUM_REG [i])); + (*(out_GPR_WRITE_READ_UNIT_DATA [i])) (*( in_GPR_WRITE_WRITE_UNIT_DATA [i])); + } +# endif + + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Method - genMealy_spr_write"),_name.c_str()); + + SC_METHOD (genMealy_spr_write); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't internal register + + for (uint32_t i=0; i<_param->_nb_spr_write; i++) + { + sensitive <<(*(in_SPR_WRITE_WRITE_UNIT_VAL [i])) + <<(*(in_SPR_WRITE_WRITE_UNIT_NUM_REG [i])) + <<(*(in_SPR_WRITE_WRITE_UNIT_DATA [i])) + <<(*(in_SPR_WRITE_REGISTER_FILE_ACK [i])); + if (_param->_have_port_ooo_engine_id) + sensitive <<(*(in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_spr_write; i++) + { + (*(out_SPR_WRITE_WRITE_UNIT_ACK [i])) (*( in_SPR_WRITE_REGISTER_FILE_ACK [i])); + (*(out_SPR_WRITE_REGISTER_FILE_VAL [i])) (*( in_SPR_WRITE_WRITE_UNIT_VAL [i])); + if (_param->_have_port_ooo_engine_id) + (*(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + (*(out_SPR_WRITE_REGISTER_FILE_NUM_REG [i])) (*( in_SPR_WRITE_WRITE_UNIT_NUM_REG [i])); + (*(out_SPR_WRITE_REGISTER_FILE_DATA [i])) (*( in_SPR_WRITE_WRITE_UNIT_DATA [i])); + (*(out_SPR_WRITE_READ_UNIT_VAL [i])) (*( in_SPR_WRITE_WRITE_UNIT_VAL [i])); + (*(out_SPR_WRITE_READ_UNIT_VAL [i])) (*( in_SPR_WRITE_REGISTER_FILE_ACK [i])); + if (_param->_have_port_ooo_engine_id) + (*(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i])); + (*(out_SPR_WRITE_READ_UNIT_NUM_REG [i])) (*( in_SPR_WRITE_WRITE_UNIT_NUM_REG [i])); + (*(out_SPR_WRITE_READ_UNIT_DATA [i])) (*( in_SPR_WRITE_WRITE_UNIT_DATA [i])); + } +# endif + +#endif + } + log_end(Execute_loop_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::~Execute_loop_Glue" + Execute_loop_Glue::~Execute_loop_Glue (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_allocation.cpp (revision 88) @@ -0,0 +1,138 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::allocation" + void Execute_loop_Glue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Execute_loop_Glue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Execute_loop_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // -----[ Interface "gpr_write_write_unit" ]-------------------------- + { + ALLOC1_INTERFACE("gpr_write_write_unit", IN, EAST, _("General register write (from write_unit)"), _param->_nb_gpr_write); + + ALLOC1_VALACK_IN ( in_GPR_WRITE_WRITE_UNIT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_GPR_WRITE_WRITE_UNIT_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_WRITE_UNIT_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_WRITE_UNIT_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + } + + // -----[ Interface "gpr_write_register_file" ]----------------------- + { + ALLOC1_INTERFACE("gpr_write_register_file",OUT,SOUTH, _("General register write (to register file)"), _param->_nb_gpr_write); + + ALLOC1_VALACK_OUT(out_GPR_WRITE_REGISTER_FILE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_GPR_WRITE_REGISTER_FILE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_REGISTER_FILE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_REGISTER_FILE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + } + + // -----[ Interface "gpr_write_read_unit" ]--------------------------- + { + ALLOC1_INTERFACE("gpr_write_read_unit",OUT,SOUTH, _("General register write (to read unit)"), _param->_nb_gpr_write); + + ALLOC1_VALACK_OUT(out_GPR_WRITE_READ_UNIT_VAL ,VAL); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_READ_UNIT_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_GPR_WRITE_READ_UNIT_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); + } + + // -----[ Interface "spr_write_write_unit" ]-------------------------- + { + ALLOC1_INTERFACE("spr_write_write_unit", IN, EAST, _("Special register write (from write_unit)"), _param->_nb_spr_write); + + ALLOC1_VALACK_IN ( in_SPR_WRITE_WRITE_UNIT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_WRITE_WRITE_UNIT_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_WRITE_UNIT_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_WRITE_UNIT_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + } + + // -----[ Interface "spr_write_register_file" ]----------------------- + { + ALLOC1_INTERFACE("spr_write_register_file",OUT,SOUTH, _("Special register write (to register file)"), _param->_nb_spr_write); + + ALLOC1_VALACK_OUT(out_SPR_WRITE_REGISTER_FILE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_SPR_WRITE_REGISTER_FILE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_REGISTER_FILE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_REGISTER_FILE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + } + + // -----[ Interface "spr_write_read_unit" ]--------------------------- + { + ALLOC1_INTERFACE("spr_write_read_unit",OUT,SOUTH, _("Special register write (to read unit)"), _param->_nb_spr_write); + + ALLOC1_VALACK_OUT(out_SPR_WRITE_READ_UNIT_VAL ,VAL); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_READ_UNIT_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_SPR_WRITE_READ_UNIT_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_deallocation.cpp (revision 88) @@ -0,0 +1,77 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::deallocation" + void Execute_loop_Glue::deallocation (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL( in_GPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_GPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL( in_GPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_gpr_write,_param->_size_general_data); + + DELETE1_SIGNAL(out_GPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL( in_GPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_GPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL(out_GPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_gpr_write,_param->_size_general_data); + + DELETE1_SIGNAL(out_GPR_WRITE_READ_UNIT_VAL ,_param->_nb_gpr_write,1); + DELETE1_SIGNAL(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_gpr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_GPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_gpr_write,_param->_size_general_register); + DELETE1_SIGNAL(out_GPR_WRITE_READ_UNIT_DATA ,_param->_nb_gpr_write,_param->_size_general_data); + + DELETE1_SIGNAL( in_SPR_WRITE_WRITE_UNIT_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_WRITE_UNIT_ACK ,_param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_SPR_WRITE_WRITE_UNIT_NUM_REG ,_param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL( in_SPR_WRITE_WRITE_UNIT_DATA ,_param->_nb_spr_write,_param->_size_special_data); + + DELETE1_SIGNAL(out_SPR_WRITE_REGISTER_FILE_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL( in_SPR_WRITE_REGISTER_FILE_ACK ,_param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID ,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_SPR_WRITE_REGISTER_FILE_NUM_REG ,_param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL(out_SPR_WRITE_REGISTER_FILE_DATA ,_param->_nb_spr_write,_param->_size_special_data); + + DELETE1_SIGNAL(out_SPR_WRITE_READ_UNIT_VAL ,_param->_nb_spr_write,1); + DELETE1_SIGNAL(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID ,_param->_nb_spr_write,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_SPR_WRITE_READ_UNIT_NUM_REG ,_param->_nb_spr_write,_param->_size_special_register); + DELETE1_SIGNAL(out_SPR_WRITE_READ_UNIT_DATA ,_param->_nb_spr_write,_param->_size_special_data); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::end_cycle" +void Execute_loop_Glue::end_cycle () + { + log_begin(Execute_loop_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_gpr_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_gpr_write.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_gpr_write.cpp (revision 88) @@ -0,0 +1,58 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::genMealy_gpr_write" + void Execute_loop_Glue::genMealy_gpr_write (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_gpr_write; i++) + { + Tcontrol_t val = PORT_READ(in_GPR_WRITE_WRITE_UNIT_VAL [i]); + Tcontrol_t ack = PORT_READ(in_GPR_WRITE_REGISTER_FILE_ACK [i]); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i]):0; + Tgeneral_address_t num_reg = PORT_READ(in_GPR_WRITE_WRITE_UNIT_NUM_REG [i]); + Tgeneral_data_t data = PORT_READ(in_GPR_WRITE_WRITE_UNIT_DATA [i]); + + PORT_WRITE(out_GPR_WRITE_WRITE_UNIT_ACK [i],ack ); + + PORT_WRITE(out_GPR_WRITE_REGISTER_FILE_VAL [i],val ); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID [i],ooo_engine_id); + PORT_WRITE(out_GPR_WRITE_REGISTER_FILE_NUM_REG [i],num_reg ); + PORT_WRITE(out_GPR_WRITE_REGISTER_FILE_DATA [i],data ); + + PORT_WRITE(out_GPR_WRITE_READ_UNIT_VAL [i],val and ack ); // Transaction + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID [i],ooo_engine_id); + PORT_WRITE(out_GPR_WRITE_READ_UNIT_NUM_REG [i],num_reg ); + PORT_WRITE(out_GPR_WRITE_READ_UNIT_DATA [i],data ); + } + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_spr_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_spr_write.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_genMealy_spr_write.cpp (revision 88) @@ -0,0 +1,58 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::genMealy_spr_write" + void Execute_loop_Glue::genMealy_spr_write (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_spr_write; i++) + { + Tcontrol_t val = PORT_READ(in_SPR_WRITE_WRITE_UNIT_VAL [i]); + Tcontrol_t ack = PORT_READ(in_SPR_WRITE_REGISTER_FILE_ACK [i]); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID [i]):0; + Tspecial_address_t num_reg = PORT_READ(in_SPR_WRITE_WRITE_UNIT_NUM_REG [i]); + Tspecial_data_t data = PORT_READ(in_SPR_WRITE_WRITE_UNIT_DATA [i]); + + PORT_WRITE(out_SPR_WRITE_WRITE_UNIT_ACK [i],ack ); + + PORT_WRITE(out_SPR_WRITE_REGISTER_FILE_VAL [i],val ); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID [i],ooo_engine_id); + PORT_WRITE(out_SPR_WRITE_REGISTER_FILE_NUM_REG [i],num_reg ); + PORT_WRITE(out_SPR_WRITE_REGISTER_FILE_DATA [i],data ); + + PORT_WRITE(out_SPR_WRITE_READ_UNIT_VAL [i],val and ack ); // Transaction + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID [i],ooo_engine_id); + PORT_WRITE(out_SPR_WRITE_READ_UNIT_NUM_REG [i],num_reg ); + PORT_WRITE(out_SPR_WRITE_READ_UNIT_DATA [i],data ); + } + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::statistics_allocation" + void Execute_loop_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Execute_loop_Glue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Execute_loop_Glue", + param_statistics); + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::statistics_deallocation" + void Execute_loop_Glue::statistics_deallocation (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + log_printf(INFO,Execute_loop_Glue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_transition.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::transition" + void Execute_loop_Glue::transition (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::vhdl" + void Execute_loop_Glue::vhdl (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::vhdl_body" + void Execute_loop_Glue::vhdl_body (Vhdl * & vhdl) + { + log_begin(Execute_loop_Glue,FUNCTION); + vhdl->set_body (""); + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Execute_loop_Glue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::vhdl_declaration" + void Execute_loop_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Execute_loop_Glue,FUNCTION); + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters.cpp (revision 88) @@ -0,0 +1,90 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::Parameters" + Parameters::Parameters (uint32_t nb_gpr_write , + uint32_t nb_spr_write , + uint32_t size_ooo_engine_id , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_general_data , + uint32_t size_special_data , + bool is_toplevel) + { + log_begin(Execute_loop_Glue,FUNCTION); + + _nb_gpr_write = nb_gpr_write ; + _nb_spr_write = nb_spr_write ; +// _size_ooo_engine_id = size_ooo_engine_id ; +// _size_general_register = size_general_register ; +// _size_special_register = size_special_register ; +// _size_general_data = size_general_data ; +// _size_special_data = size_special_data ; + +// _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + + test(); + + if (is_toplevel) + { + _size_ooo_engine_id = size_ooo_engine_id ; + _size_general_register = size_general_register ; + _size_special_register = size_special_register ; + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + + copy(); + } + + log_end(Execute_loop_Glue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Execute_loop_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Execute_loop_Glue,FUNCTION); +// test(); +// log_end(Execute_loop_Glue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + log_end(Execute_loop_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::copy" + void Parameters::copy (void) + { + log_begin(Execute_loop_Glue,FUNCTION); + log_end(Execute_loop_Glue,FUNCTION); + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Execute_loop_Glue,FUNCTION); + + Parameters_test test ("Execute_loop_Glue"); + + log_end(Execute_loop_Glue,FUNCTION); + + return test; + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,62 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_execute_loop { +namespace execute_loop { +namespace execute_loop_glue { + + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Execute_loop_Glue,FUNCTION); + + XML xml ("execute_loop_glue"); + + xml.balise_open("execute_loop_glue"); + xml.singleton_begin("nb_gpr_write "); xml.attribut("value",toString(_nb_gpr_write )); xml.singleton_end(); + xml.singleton_begin("nb_spr_write "); xml.attribut("value",toString(_nb_spr_write )); xml.singleton_end(); + xml.singleton_begin("size_ooo_engine_id "); xml.attribut("value",toString(_size_ooo_engine_id )); xml.singleton_end(); + xml.singleton_begin("size_general_register"); xml.attribut("value",toString(_size_general_register)); xml.singleton_end(); + xml.singleton_begin("size_special_register"); xml.attribut("value",toString(_size_special_register)); xml.singleton_end(); + xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); + xml.singleton_begin("size_special_data "); xml.attribut("value",toString(_size_special_data )); xml.singleton_end(); + xml.balise_close(); + + log_end(Execute_loop_Glue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Execute_loop_Glue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters & x) + { + log_begin(Execute_loop_Glue,FUNCTION); + + output_stream << x.print(0); + + log_end(Execute_loop_Glue,FUNCTION); + + return output_stream; + }; + +}; // end namespace execute_loop_glue +}; // end namespace execute_loop +}; // end namespace multi_execute_loop +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Makefile.deps (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Makefile.deps (revision 88) @@ -12,4 +12,7 @@ ifndef Behavioural include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Execute_loop_Glue +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/Makefile.deps endif ifndef Read_unit @@ -43,4 +46,5 @@ Execute_loop_LIBRARY = -lExecute_loop \ $(Behavioural_LIBRARY) \ + $(Execute_loop_Glue_LIBRARY) \ $(Read_unit_LIBRARY) \ $(Functionnal_unit_LIBRARY) \ @@ -54,5 +58,5 @@ Execute_loop_DIR_LIBRARY = -L$(Execute_loop_DIR)/lib \ $(Behavioural_DIR_LIBRARY) \ - $(Behavioural_DIR_LIBRARY) \ + $(Execute_loop_Glue_DIR_LIBRARY) \ $(Read_unit_DIR_LIBRARY) \ $(Functionnal_unit_DIR_LIBRARY) \ @@ -69,4 +73,5 @@ @\ $(MAKE) Behavioural_library; \ + $(MAKE) Execute_loop_Glue_library; \ $(MAKE) Read_unit_library; \ $(MAKE) Functionnal_unit_library; \ @@ -81,4 +86,5 @@ @\ $(MAKE) Behavioural_library_clean; \ + $(MAKE) Execute_loop_Glue_library_clean; \ $(MAKE) Read_unit_library_clean; \ $(MAKE) Functionnal_unit_library_clean; \ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 88) @@ -8,14 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Operation.h" - -#define neg(data) (~(data)+1) -#define sign(data) ((data)>>(param->_size_data-1)) -#define unsigned(data) (data) -#define signed(data) ((sign(data)==0)?(data):neg(data)) -#define ovf(op1, op2, res) ((sign(op1) == sign(op2))?(sign(op1) xor sign(res)):0) -#define carry(op1, op2, res) (((res)<(op1)) or ((res)<(op2))) -#define set_flag(data,flag,is_set) (((is_set)==1)?((data)|(flag)):((data)&~(flag))) -#define get_flag(data,flag) (((data)&(flag))!=0) -#define concatenation_bool(a,b) (((a)<<1) | (b)) +#include "Behavioural/include/Operation.h" namespace morpheo { @@ -43,11 +34,11 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_add"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = param->_mask_data & (gpr1 + gpr2); - bool overflow = ovf (gpr1,gpr2,gpr3); - bool carry_out = carry(gpr1,gpr2,gpr3); + bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); + bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); // Result @@ -70,10 +61,10 @@ Tgeneral_data_t carry_in = get_flag(op->_data_rc,FLAG_CY); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = param->_mask_data & (gpr1 + gpr2 + carry_in); - bool overflow = ovf (gpr1,gpr2,gpr3); - bool carry_out = carry(gpr1,gpr2,gpr3); + bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); + bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); // Result @@ -94,10 +85,10 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sub"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = neg(unsigned(op->_data_rb)); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = neg(param->_size_data,unsigned(param->_size_data,op->_data_rb)); Tgeneral_data_t gpr3 = param->_mask_data & (gpr1 + gpr2); - bool overflow = ovf (gpr1,gpr2,gpr3); - bool carry_out = carry(gpr1,gpr2,gpr3); + bool overflow = ovf (param->_size_data,gpr1,gpr2,gpr3); + bool carry_out = carry(param->_size_data,gpr1,gpr2,gpr3); // Result @@ -118,6 +109,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_and"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = (gpr1 & gpr2); @@ -137,6 +128,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_or"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = (gpr1 | gpr2); @@ -156,6 +147,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_xor"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = (gpr1 ^ gpr2); @@ -175,5 +166,5 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_movhi"); - Tgeneral_data_t gpr1 = unsigned(op->_immediat); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_immediat); Tgeneral_data_t gpr2 = param->_mask_data & (gpr1<<16); @@ -195,6 +186,6 @@ Tgeneral_data_t f_in = get_flag(op->_data_rc,FLAG_F); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned(op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); Tgeneral_data_t gpr3 = ((f_in==0)?gpr2:gpr1); @@ -215,5 +206,5 @@ Tgeneral_data_t f_in = get_flag(op->_data_rc,FLAG_F); - Tgeneral_data_t imm = unsigned(op->_immediat); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); // Result @@ -233,5 +224,5 @@ Tgeneral_data_t f_in = get_flag(op->_data_rc,FLAG_F); - Tgeneral_data_t imm = unsigned(op->_immediat); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); // Result @@ -254,6 +245,6 @@ - Tgeneral_data_t gpr = unsigned(op->_data_rb); - Tgeneral_data_t imm = unsigned(op->_immediat); + Tgeneral_data_t gpr = unsigned(param->_size_data,op->_data_rb); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); // Result @@ -272,6 +263,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_extend_s"); - Tgeneral_data_t imm = unsigned(op->_immediat); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); Tgeneral_data_t gpr2 = extend(param->_size_data, gpr1, true , imm); @@ -291,6 +282,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_extend_z"); - Tgeneral_data_t imm = unsigned(op->_immediat); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); Tgeneral_data_t gpr2 = extend(param->_size_data, gpr1, false , imm); @@ -310,6 +301,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sll"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = shift_logic_left(param->_size_data, gpr1, gpr2); @@ -329,6 +320,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_srl"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = shift_logic_right(param->_size_data, gpr1, gpr2); @@ -348,6 +339,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sra"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = shift_arithmetic_right(param->_size_data, gpr1, gpr2); @@ -367,6 +358,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_ror"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = param->_mask_shift & unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = param->_mask_shift & unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); Tgeneral_data_t gpr3 = rotate_right(param->_size_data, gpr1, gpr2); @@ -386,5 +377,5 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_ff1"); - Tgeneral_data_t gpr = unsigned(op->_data_ra); + Tgeneral_data_t gpr = unsigned(param->_size_data,op->_data_ra); Tgeneral_data_t index; @@ -406,5 +397,5 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_fl1"); - Tgeneral_data_t gpr = unsigned(op->_data_ra); + Tgeneral_data_t gpr = unsigned(param->_size_data,op->_data_ra); Tgeneral_data_t index; @@ -426,6 +417,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfeq"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 == gpr2); @@ -446,6 +437,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfne"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 != gpr2); @@ -466,6 +457,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfgeu"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 >= gpr2); @@ -486,6 +477,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfgtu"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 > gpr2); @@ -506,6 +497,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfleu"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 <= gpr2); @@ -526,6 +517,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_sfltu"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); bool f_out = (gpr1 < gpr2); @@ -549,16 +540,16 @@ Tgeneral_data_t gpr2 = (op->_has_immediat==1)?op->_immediat:op->_data_rb; - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra : %.8x",unsigned(op->_data_ra)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x", signed(op->_data_ra)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb : %.8x",unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb)); - log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x", signed((op->_has_immediat==1)?op->_immediat:op->_data_rb)); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra : %.8x",unsigned(param->_size_data,op->_data_ra)); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ras : %.8x", signed(param->_size_data,op->_data_ra)); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb : %.8x",unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rbs : %.8x", signed(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb)); bool f_out; - switch (concatenation_bool(sign(gpr1),sign(gpr2))) + switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) { case 1 /*b01*/ : f_out = 1 ; break; case 2 /*b10*/ : f_out = 0 ; break; - default : f_out = signed(gpr1) >= signed(gpr2); break; + default : f_out = signed(param->_size_data,gpr1) >= signed(param->_size_data,gpr2); break; } @@ -585,9 +576,9 @@ bool f_out; - switch (concatenation_bool(sign(gpr1),sign(gpr2))) + switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) { case 1 /*b01*/ : f_out = 1; break; case 2 /*b10*/ : f_out = 0; break; - default : f_out = signed(gpr1) > signed(gpr2); break; + default : f_out = signed(param->_size_data,gpr1) > signed(param->_size_data,gpr2); break; } @@ -612,9 +603,9 @@ bool f_out; - switch (concatenation_bool(sign(gpr1),sign(gpr2))) + switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) { case 1 /*b01*/ : f_out = 0; break; case 2 /*b10*/ : f_out = 1; break; - default : f_out = signed(gpr1) <= signed(gpr2); break; + default : f_out = signed(param->_size_data,gpr1) <= signed(param->_size_data,gpr2); break; } @@ -639,9 +630,9 @@ bool f_out; - switch (concatenation_bool(sign(gpr1),sign(gpr2))) + switch (concatenation_bool(sign(param->_size_data,gpr1),sign(param->_size_data,gpr2))) { case 1 /*b01*/ : f_out = 0; break; case 2 /*b10*/ : f_out = 1; break; - default : f_out = signed(gpr1) < signed(gpr2); break; + default : f_out = signed(param->_size_data,gpr1) < signed(param->_size_data,gpr2); break; } @@ -661,7 +652,7 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mtspr"); - Tgeneral_data_t imm = unsigned(op->_immediat); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned(op->_data_rb); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,op->_data_rb); Tgeneral_data_t addr = range(gpr1|imm,16); @@ -694,5 +685,5 @@ else { - exception = EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE; + exception = EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE; } @@ -712,6 +703,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mfspr"); - Tgeneral_data_t imm = unsigned(op->_immediat); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); + Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); Tgeneral_data_t gpr2 = 0; Tgeneral_data_t addr = range(gpr1|imm,16); @@ -745,5 +736,5 @@ else { - exception = EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE; + exception = EXCEPTION_ALU_SPR_ACCESS_MUST_READ; } @@ -784,6 +775,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_mac"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); uint64_t temp = range(gpr1 * gpr2, 32); @@ -808,6 +799,6 @@ log_printf(TRACE,Functionnal_unit,FUNCTION,"Operation : l_msb"); - Tgeneral_data_t gpr1 = unsigned(op->_data_ra); - Tgeneral_data_t gpr2 = unsigned((op->_has_immediat==1)?op->_immediat:op->_data_rb); + Tgeneral_data_t gpr1 = unsigned(param->_size_data,op->_data_ra); + Tgeneral_data_t gpr2 = unsigned(param->_size_data,(op->_has_immediat==1)?op->_immediat:op->_data_rb); uint64_t temp = range(gpr1 * gpr2, 32); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Functionnal_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/main.cpp (revision 88) @@ -75,5 +75,6 @@ size_load_queue , timing , - &(morpheo::behavioural::custom::example_get_custom_information) + &(morpheo::behavioural::custom::example_get_custom_information), + true // is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 88) @@ -69,8 +69,8 @@ _data_rc (data_rc & gen_mask(param->_size_special_data)), _write_rd (write_rd ), - _num_reg_rd (num_reg_rd % param->_nb_special_register), + _num_reg_rd (num_reg_rd % (1<_size_general_register)), _data_rd (data_rd & gen_mask(param->_size_general_data)), _write_re (write_re ), - _num_reg_re (num_reg_re % param->_nb_special_register), + _num_reg_re (num_reg_re % (1<_size_special_register)), _data_re (data_re & gen_mask(param->_size_special_data)), _exception (exception ), @@ -88,6 +88,16 @@ #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Functionnal_unit * _Functionnal_unit = new Functionnal_unit (name.c_str(), @@ -96,5 +106,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -162,5 +172,5 @@ if (_param->_have_port_ooo_engine_id) (*(_Functionnal_unit-> in_EXECUTE_IN_OOO_ENGINE_ID )) ( in_EXECUTE_IN_OOO_ENGINE_ID ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) (*(_Functionnal_unit-> in_EXECUTE_IN_PACKET_ID )) ( in_EXECUTE_IN_PACKET_ID ); (*(_Functionnal_unit-> in_EXECUTE_IN_OPERATION )) ( in_EXECUTE_IN_OPERATION ); @@ -187,5 +197,5 @@ if (_param->_have_port_ooo_engine_id) (*(_Functionnal_unit->out_EXECUTE_OUT_OOO_ENGINE_ID)) (out_EXECUTE_OUT_OOO_ENGINE_ID); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) (*(_Functionnal_unit->out_EXECUTE_OUT_PACKET_ID )) (out_EXECUTE_OUT_PACKET_ID ); //(*(_Functionnal_unit->out_EXECUTE_OUT_OPERATION )) (out_EXECUTE_OUT_OPERATION ); @@ -475,6 +485,6 @@ transaction_in.push_back(execute_transaction(_param,0,0,0,301,OPERATION_TEST_L_SFLTS ,TYPE_TEST,0,0 ,0x11111111,0xdeadbeef,0 ,0,63,0x0 ,1,15,0 ,EXCEPTION_NONE ,0)); // + < - (in unsigned) - transaction_in.push_back(execute_transaction(_param,0,0,0,400,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 3,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE,0,(GROUP_ICACHE<<11)| 3)); - transaction_in.push_back(execute_transaction(_param,0,0,0,401,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 5,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE,0,(GROUP_ICACHE<<11)| 5)); + transaction_in.push_back(execute_transaction(_param,0,0,0,400,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 3,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE ,0,(GROUP_ICACHE<<11)| 3)); + transaction_in.push_back(execute_transaction(_param,0,0,0,401,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_ICACHE<<11, 5,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE ,0,(GROUP_ICACHE<<11)| 5)); transaction_in.push_back(execute_transaction(_param,0,0,0,402,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_MAC <<11, 0,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_SPR_ACCESS_INVALID ,0,(GROUP_MAC <<11)| 0)); transaction_in.push_back(execute_transaction(_param,0,0,0,403,OPERATION_SPECIAL_L_MTSPR ,TYPE_SPECIAL,1,GROUP_MAC <<11, 1,0xdeadbeef,0 ,0,63,0xdeadbeef,0, 0,0 ,EXCEPTION_ALU_NONE ,0,(GROUP_MAC <<11)| 1)); @@ -590,5 +600,5 @@ if (_param->_have_port_ooo_engine_id) in_EXECUTE_IN_OOO_ENGINE_ID .write(transaction_in.front()._ooo_engine_id); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) in_EXECUTE_IN_PACKET_ID .write(transaction_in.front()._packet_id ); in_EXECUTE_IN_OPERATION .write(transaction_in.front()._operation ); @@ -613,5 +623,5 @@ { // TEST - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) TEST(Tpacket_t , out_EXECUTE_OUT_PACKET_ID .read(), transaction_out.front()._packet_id ); if (_param->_have_port_context_id) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 88) @@ -124,7 +124,9 @@ private : Tcontrol_t internal_EXECUTE_IN_ACK; private : Tcontrol_t internal_EXECUTE_OUT_VAL; - private : bool reg_BUSY; + private : bool reg_BUSY_IN ; + private : bool reg_BUSY_OUT; - private : execute_operation_t * _execute_operation; + private : execute_operation_t * _execute_operation_in ; + private : execute_operation_t * _execute_operation_out; private : execute_register_t **** _execute_register; private : execute_param_t * _execute_param; @@ -158,6 +160,4 @@ public : void transition (void); public : void genMoore (void); - public : void genMealy (void); - #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h (revision 88) @@ -25,36 +25,35 @@ namespace functionnal_unit { - class Parameters : public morpheo::behavioural::Parameters { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _size_store_queue ; - public : const uint32_t _size_load_queue ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; +//public : uint32_t _nb_general_register ; +//public : uint32_t _nb_special_register ; +//public : uint32_t _size_store_queue ; +//public : uint32_t _size_load_queue ; - public : execute_timing_t ** _timing ; - public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t); + public : execute_timing_t ** _timing ; + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; - public : const bool _have_port_load_queue_ptr ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr ; - public : const bool _have_groupe_MAC ; + public : bool _have_groupe_MAC ; //-----[ methods ]----------------------------------------------------------- @@ -70,7 +69,11 @@ uint32_t size_load_queue , execute_timing_t** timing , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)); - public : Parameters (Parameters & param) ; + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel=true + ); +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit.cpp (revision 88) @@ -42,6 +42,12 @@ allocation (); +#if DEBUG_Functionnal_unit == true + log_printf(INFO,Functionnal_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Functionnal_unit,FUNCTION,"Allocation of statistics"); @@ -52,5 +58,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -62,5 +68,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Functionnal_unit,FUNCTION,"Method - transition"); @@ -84,16 +90,4 @@ # endif - log_printf(INFO,Functionnal_unit,FUNCTION,"Method - genMealy"); - - SC_METHOD (genMealy); - dont_initialize (); - sensitive << (*(in_CLOCK)).neg() - << (*(in_EXECUTE_OUT_ACK)); - -# ifdef SYSTEMCASS_SPECIFIC - // List dependency information - (*(out_EXECUTE_IN_ACK)) (*(in_EXECUTE_OUT_ACK)); -# endif - #endif } @@ -108,5 +102,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Functionnal_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 88) @@ -67,11 +67,11 @@ if (_param->_have_port_ooo_engine_id) in_EXECUTE_IN_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); - if (_param->_have_port_packet_id) - in_EXECUTE_IN_PACKET_ID = interface->set_signal_in ("packet_id" , _param->_size_packet_id ); + if (_param->_have_port_rob_ptr) + in_EXECUTE_IN_PACKET_ID = interface->set_signal_in ("packet_id" , _param->_size_rob_ptr ); in_EXECUTE_IN_OPERATION = interface->set_signal_in ("operation" , _param->_size_operation ); in_EXECUTE_IN_TYPE = interface->set_signal_in ("type" , _param->_size_type ); - in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write",log2(_param->_size_store_queue)); + in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write",_param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,log2(_param->_size_load_queue)); + in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,_param->_size_load_queue_ptr); in_EXECUTE_IN_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat" , 1); in_EXECUTE_IN_IMMEDIAT = interface->set_signal_in ("immediat" , _param->_size_general_data); @@ -102,6 +102,6 @@ if (_param->_have_port_ooo_engine_id) out_EXECUTE_OUT_OOO_ENGINE_ID = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - if (_param->_have_port_packet_id) - out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_packet_id ); + if (_param->_have_port_rob_ptr) + out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_rob_ptr ); //out_EXECUTE_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); out_EXECUTE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); @@ -117,8 +117,11 @@ } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _execute_operation = new execute_operation_t; - _execute_param = new execute_param_t(_param->_size_general_data, - _param->_timing); + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + _execute_operation_in = new execute_operation_t; + _execute_operation_out = new execute_operation_t; + _execute_param = new execute_param_t(_param->_size_general_data, + _param->_timing); _execute_register = new execute_register_t *** [_param->_nb_context]; @@ -134,7 +137,7 @@ for (uint32_t k=0; k<_param->_nb_ooo_engine; k++) { - uint32_t num_thread = get_num_thread(i,_param->_size_context_id, - j,_param->_size_front_end_id, - k,_param->_size_ooo_engine_id); +// uint32_t num_thread = get_num_thread(i,_param->_size_context_id, +// j,_param->_size_front_end_id, +// k,_param->_size_ooo_engine_id); _execute_register [i][j][k] = new execute_register_t; @@ -144,11 +147,11 @@ for (uint32_t x=GROUP_CUSTOM_1; x_get_custom_information(num_thread))._get_valid_group(x) == true) + if ((_param->_get_custom_information())._get_valid_group(x) == true) { - uint32_t nb_reg = (_param->_get_custom_information(num_thread))._get_nb_register(x); + uint32_t nb_reg = (_param->_get_custom_information())._get_nb_register(x); _execute_register[i][j][k]->implement_group(x,nb_reg); for (uint32_t y=0; y_spr_access_mode->change_mode(x,y,(_param->_get_custom_information(num_thread))._get_access_mode(x,y)); + _execute_register[i][j][k]->_spr_access_mode->change_mode(x,y,(_param->_get_custom_information())._get_access_mode(x,y)); } } @@ -211,12 +214,12 @@ if (_param->_timing[TYPE_TEST ][OPERATION_TEST_L_SFNE ]._latence > 0) _function_execute[TYPE_TEST ][OPERATION_TEST_L_SFNE ] = &(operation_l_sfne ); -// if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MUL ]._latence > 0) -// _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MUL ] = &(operation_l_mul ); -// if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MULU ]._latence > 0) -// _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_MULU ] = &(operation_l_mulu ); -// if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIV ]._latence > 0) -// _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIV ] = &(operation_l_div ); -// if (_param->_timing[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIVU ]._latence > 0) -// _function_execute[TYPE_MUL_DIV][OPERATION_MUL_DIV_L_DIVU ] = &(operation_l_divu ); +// if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MUL ]._latence > 0) +// _function_execute[TYPE_MUL ][OPERATION_MUL_L_MUL ] = &(operation_l_mul ); +// if (_param->_timing[TYPE_MUL ][OPERATION_MUL_L_MULU ]._latence > 0) +// _function_execute[TYPE_DIV ][OPERATION_MUL_L_MULU ] = &(operation_l_mulu ); +// if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIV ]._latence > 0) +// _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIV ] = &(operation_l_div ); +// if (_param->_timing[TYPE_DIV ][OPERATION_DIV_L_DIVU ]._latence > 0) +// _function_execute[TYPE_DIV ][OPERATION_DIV_L_DIVU ] = &(operation_l_divu ); if (_param->_timing[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ]._latence > 0) _function_execute[TYPE_EXTEND ][OPERATION_EXTEND_L_EXTEND_S ] = &(operation_l_extend_s); @@ -243,9 +246,9 @@ if (_param->_timing[TYPE_BRANCH ][OPERATION_BRANCH_L_JALR ]._latence > 0) _function_execute[TYPE_BRANCH ][OPERATION_BRANCH_L_JALR ] = &(operation_l_jalr ); - - - -#ifdef POSITION - _component->generate_file(); + } + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -37,5 +37,5 @@ if (_param->_have_port_ooo_engine_id) delete in_EXECUTE_IN_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete in_EXECUTE_IN_PACKET_ID ; delete in_EXECUTE_IN_OPERATION ; @@ -62,5 +62,5 @@ if (_param->_have_port_ooo_engine_id) delete out_EXECUTE_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete out_EXECUTE_OUT_PACKET_ID ; //delete out_EXECUTE_OUT_OPERATION ; @@ -75,11 +75,13 @@ delete out_EXECUTE_OUT_NO_SEQUENCE ; delete out_EXECUTE_OUT_ADDRESS ; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete [] _execute_register; + delete _execute_param; + delete _execute_operation_in; + delete _execute_operation_out; + delete [] _function_execute; } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] _execute_register; - delete _execute_param; - delete _execute_operation; - delete [] _function_execute; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMealy.cpp (revision 87) +++ (revision ) @@ -1,46 +1,0 @@ -#ifdef SYSTEMC -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" - -namespace morpheo { -namespace behavioural { -namespace core { -namespace multi_execute_loop { -namespace execute_loop { -namespace multi_execute_unit { -namespace execute_unit { -namespace functionnal_unit { - - -#undef FUNCTION -#define FUNCTION "Functionnal_unit::genMealy" - void Functionnal_unit::genMealy (void) - { - log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); - - bool execute_out_transaction = (PORT_READ(in_EXECUTE_OUT_ACK) and - (reg_BUSY and (_execute_operation->_timing._latence == 0))); - - internal_EXECUTE_IN_ACK = not reg_BUSY or (reg_BUSY and execute_out_transaction); - - PORT_WRITE(out_EXECUTE_IN_ACK, internal_EXECUTE_IN_ACK); - - log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); - }; - -}; // end namespace functionnal_unit -}; // end namespace execute_unit -}; // end namespace multi_execute_unit -}; // end namespace execute_loop -}; // end namespace multi_execute_loop -}; // end namespace core - -}; // end namespace behavioural -}; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 88) @@ -23,30 +23,39 @@ void Functionnal_unit::genMoore (void) { - log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); + log_begin(Functionnal_unit,FUNCTION); + log_function(Functionnal_unit,FUNCTION,_name.c_str()); - internal_EXECUTE_OUT_VAL = reg_BUSY and (_execute_operation->_timing._latence == 0); + { + internal_EXECUTE_IN_ACK = not reg_BUSY_IN; + + PORT_WRITE(out_EXECUTE_IN_ACK , internal_EXECUTE_IN_ACK); + } - PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); - if (_param->_have_port_context_id) - PORT_WRITE(out_EXECUTE_OUT_CONTEXT_ID ,_execute_operation->_context_id ); - if (_param->_have_port_front_end_id) - PORT_WRITE(out_EXECUTE_OUT_FRONT_END_ID ,_execute_operation->_front_end_id ); - if (_param->_have_port_ooo_engine_id) - PORT_WRITE(out_EXECUTE_OUT_OOO_ENGINE_ID,_execute_operation->_ooo_engine_id); - if (_param->_have_port_packet_id) - PORT_WRITE(out_EXECUTE_OUT_PACKET_ID ,_execute_operation->_packet_id ); - //PORT_WRITE(out_EXECUTE_OUT_OPERATION ,_execute_operation->_operation ); - PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation->_type ); - PORT_WRITE(out_EXECUTE_OUT_WRITE_RD ,_execute_operation->_write_rd ); - PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD ,_execute_operation->_num_reg_rd ); - PORT_WRITE(out_EXECUTE_OUT_DATA_RD ,_execute_operation->_data_rd ); - PORT_WRITE(out_EXECUTE_OUT_WRITE_RE ,_execute_operation->_write_re ); - PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RE ,_execute_operation->_num_reg_re ); - PORT_WRITE(out_EXECUTE_OUT_DATA_RE ,_execute_operation->_data_re ); - PORT_WRITE(out_EXECUTE_OUT_EXCEPTION ,_execute_operation->_exception ); - PORT_WRITE(out_EXECUTE_OUT_NO_SEQUENCE ,_execute_operation->_no_sequence ); - PORT_WRITE(out_EXECUTE_OUT_ADDRESS ,_execute_operation->_address ); + { + internal_EXECUTE_OUT_VAL = reg_BUSY_OUT and (_execute_operation_out->_timing._latence == 0); + + PORT_WRITE(out_EXECUTE_OUT_VAL , internal_EXECUTE_OUT_VAL); + if (_param->_have_port_context_id) + PORT_WRITE(out_EXECUTE_OUT_CONTEXT_ID ,_execute_operation_out->_context_id ); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_EXECUTE_OUT_FRONT_END_ID ,_execute_operation_out->_front_end_id ); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_EXECUTE_OUT_OOO_ENGINE_ID,_execute_operation_out->_ooo_engine_id); + if (_param->_have_port_rob_ptr) + PORT_WRITE(out_EXECUTE_OUT_PACKET_ID ,_execute_operation_out->_packet_id ); + // PORT_WRITE(out_EXECUTE_OUT_OPERATION ,_execute_operation_out->_operation ); + PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation_out->_type ); + PORT_WRITE(out_EXECUTE_OUT_WRITE_RD ,_execute_operation_out->_write_rd ); + PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD ,_execute_operation_out->_num_reg_rd ); + PORT_WRITE(out_EXECUTE_OUT_DATA_RD ,_execute_operation_out->_data_rd ); + PORT_WRITE(out_EXECUTE_OUT_WRITE_RE ,_execute_operation_out->_write_re ); + PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RE ,_execute_operation_out->_num_reg_re ); + PORT_WRITE(out_EXECUTE_OUT_DATA_RE ,_execute_operation_out->_data_re ); + PORT_WRITE(out_EXECUTE_OUT_EXCEPTION ,_execute_operation_out->_exception ); + PORT_WRITE(out_EXECUTE_OUT_NO_SEQUENCE ,_execute_operation_out->_no_sequence ); + PORT_WRITE(out_EXECUTE_OUT_ADDRESS ,_execute_operation_out->_address ); + } - log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); + log_end(Functionnal_unit,FUNCTION); }; @@ -57,5 +66,4 @@ }; // end namespace multi_execute_loop }; // end namespace core - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 88) @@ -23,9 +23,11 @@ void Functionnal_unit::transition (void) { - log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); + log_begin(Functionnal_unit,FUNCTION); + log_function(Functionnal_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) { - reg_BUSY = false; + reg_BUSY_IN = false; + reg_BUSY_OUT = false; for (uint32_t i=0; i<_param->_nb_context; i++) @@ -33,11 +35,11 @@ for (uint32_t k=0; k<_param->_nb_ooo_engine; k++) { - uint32_t num_thread = get_num_thread(i,_param->_size_context_id, - j,_param->_size_front_end_id, - k,_param->_size_ooo_engine_id); +// uint32_t num_thread = get_num_thread(i,_param->_size_context_id, +// j,_param->_size_front_end_id, +// k,_param->_size_ooo_engine_id); for (uint32_t x=GROUP_CUSTOM_1; x_get_custom_information(num_thread)._get_custom_execute_reset(x)); + function_execute_end_cycle_t * fct = (_param->_get_custom_information()._get_custom_execute_reset(x)); if (fct != NULL) @@ -51,6 +53,7 @@ if (internal_EXECUTE_OUT_VAL and PORT_READ(in_EXECUTE_OUT_ACK)) { + log_printf(TRACE,Functionnal_unit,FUNCTION," * EXECUTE_OUT : Transaction Accepted"); // transaction - reg_BUSY = false; + reg_BUSY_OUT = false; } @@ -60,29 +63,47 @@ if (PORT_READ(in_EXECUTE_IN_VAL) and internal_EXECUTE_IN_ACK) { - reg_BUSY = true; + log_printf(TRACE,Functionnal_unit,FUNCTION," * EXECUTE_IN : Transaction Accepted"); + + reg_BUSY_IN = true; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_IN_CONTEXT_ID ):0; Tcontext_t front_end_id = (_param->_have_port_front_end_id )?PORT_READ(in_EXECUTE_IN_FRONT_END_ID ):0; Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_IN_OOO_ENGINE_ID):0; - Tcontext_t packet_id = (_param->_have_port_packet_id )?PORT_READ(in_EXECUTE_IN_PACKET_ID ):0; + Tcontext_t packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_EXECUTE_IN_PACKET_ID ):0; Toperation_t operation = PORT_READ(in_EXECUTE_IN_OPERATION); Ttype_t type = PORT_READ(in_EXECUTE_IN_TYPE); - _execute_operation->_context_id = context_id ; - _execute_operation->_front_end_id = front_end_id ; - _execute_operation->_ooo_engine_id = ooo_engine_id; - _execute_operation->_packet_id = packet_id ; - _execute_operation->_operation = operation ; - _execute_operation->_type = type ; - _execute_operation->_has_immediat = PORT_READ(in_EXECUTE_IN_HAS_IMMEDIAT); - _execute_operation->_immediat = PORT_READ(in_EXECUTE_IN_IMMEDIAT ); - _execute_operation->_data_ra = PORT_READ(in_EXECUTE_IN_DATA_RA ); - _execute_operation->_data_rb = PORT_READ(in_EXECUTE_IN_DATA_RB ); - _execute_operation->_data_rc = PORT_READ(in_EXECUTE_IN_DATA_RC ); - _execute_operation->_write_rd = PORT_READ(in_EXECUTE_IN_WRITE_RD ); - _execute_operation->_num_reg_rd = PORT_READ(in_EXECUTE_IN_NUM_REG_RD ); - _execute_operation->_write_re = PORT_READ(in_EXECUTE_IN_WRITE_RE ); - _execute_operation->_num_reg_re = PORT_READ(in_EXECUTE_IN_NUM_REG_RE ); - + _execute_operation_in->_context_id = context_id ; + _execute_operation_in->_front_end_id = front_end_id ; + _execute_operation_in->_ooo_engine_id = ooo_engine_id; + _execute_operation_in->_packet_id = packet_id ; + _execute_operation_in->_operation = operation ; + _execute_operation_in->_type = type ; + _execute_operation_in->_has_immediat = PORT_READ(in_EXECUTE_IN_HAS_IMMEDIAT); + _execute_operation_in->_immediat = PORT_READ(in_EXECUTE_IN_IMMEDIAT ); + _execute_operation_in->_data_ra = PORT_READ(in_EXECUTE_IN_DATA_RA ); + _execute_operation_in->_data_rb = PORT_READ(in_EXECUTE_IN_DATA_RB ); + _execute_operation_in->_data_rc = PORT_READ(in_EXECUTE_IN_DATA_RC ); + _execute_operation_in->_write_rd = PORT_READ(in_EXECUTE_IN_WRITE_RD ); + _execute_operation_in->_num_reg_rd = PORT_READ(in_EXECUTE_IN_NUM_REG_RD ); + _execute_operation_in->_write_re = PORT_READ(in_EXECUTE_IN_WRITE_RE ); + _execute_operation_in->_num_reg_re = PORT_READ(in_EXECUTE_IN_NUM_REG_RE ); + + log_printf(TRACE,Functionnal_unit,FUNCTION," * context_id : %d",_execute_operation_in->_context_id ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * front_end_id : %d",_execute_operation_in->_front_end_id ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * ooo_engine_id : %d",_execute_operation_in->_ooo_engine_id); + log_printf(TRACE,Functionnal_unit,FUNCTION," * packet_id : %d",_execute_operation_in->_packet_id ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * operation : %d",_execute_operation_in->_operation ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * type : %s",toString_type(_execute_operation_in->_type).c_str()); + log_printf(TRACE,Functionnal_unit,FUNCTION," * has_immediat : %d",_execute_operation_in->_has_immediat ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * immediat : %.8x",_execute_operation_in->_immediat ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_ra : %.8x",_execute_operation_in->_data_ra ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rb : %.8x",_execute_operation_in->_data_rb ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rc : %.8x",_execute_operation_in->_data_rc ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * write_rd : %d" ,_execute_operation_in->_write_rd ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * num_reg_rd : %d" ,_execute_operation_in->_num_reg_rd ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * write_re : %d" ,_execute_operation_in->_write_re ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * num_reg_re : %d" ,_execute_operation_in->_num_reg_re ); + #ifdef DEBUG_TEST if (type >= _param->_nb_type) @@ -98,18 +119,30 @@ if (type == TYPE_CUSTOM) { - uint32_t num_thread = get_num_thread(context_id ,_param->_size_context_id, - front_end_id ,_param->_size_front_end_id, - ooo_engine_id,_param->_size_ooo_engine_id); - - (*(_param->_get_custom_information(num_thread)._get_custom_execute_genMoore(operation))) (_execute_operation, execute_register, _execute_param); +// uint32_t num_thread = get_num_thread(context_id ,_param->_size_context_id, +// front_end_id ,_param->_size_front_end_id, +// ooo_engine_id,_param->_size_ooo_engine_id); + + (*(_param->_get_custom_information()._get_custom_execute_genMoore(operation))) (_execute_operation_in, execute_register, _execute_param); } else - (*(_function_execute[type][operation])) (_execute_operation, execute_register, _execute_param); - + (*(_function_execute[type][operation])) (_execute_operation_in, execute_register, _execute_param); + + + log_printf(TRACE,Functionnal_unit,FUNCTION," -----------------"); + log_printf(TRACE,Functionnal_unit,FUNCTION," * latence : %.8x",_execute_operation_in->_timing._latence); + log_printf(TRACE,Functionnal_unit,FUNCTION," * delay : %.8x",_execute_operation_in->_timing._delay); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rd : %.8x",_execute_operation_in->_data_rd ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_re : %.8x",_execute_operation_in->_data_re ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * exception : %d" ,_execute_operation_in->_exception ); + log_printf(TRACE,Functionnal_unit,FUNCTION," * no_sequence : %d" ,_execute_operation_in->_no_sequence); + log_printf(TRACE,Functionnal_unit,FUNCTION," * address : %.8x",_execute_operation_in->_address ); #ifdef STATISTICS - (*_stat_use_functionnal_unit) ++; - (*_stat_sum_delay) += _execute_operation->_timing._delay; - (*_stat_sum_latence) += _execute_operation->_timing._latence; + if (usage_is_set(_usage,USE_STATISTICS)) + { + (*_stat_use_functionnal_unit) ++; + (*_stat_sum_delay) += _execute_operation_in->_timing._delay; + (*_stat_sum_latence) += _execute_operation_in->_timing._latence; + } #endif } @@ -121,11 +154,11 @@ for (uint32_t k=0; k<_param->_nb_ooo_engine; k++) { - uint32_t num_thread = get_num_thread(i,_param->_size_context_id, - j,_param->_size_front_end_id, - k,_param->_size_ooo_engine_id); +// uint32_t num_thread = get_num_thread(i,_param->_size_context_id, +// j,_param->_size_front_end_id, +// k,_param->_size_ooo_engine_id); for (uint32_t x=GROUP_CUSTOM_1; x_get_custom_information(num_thread)._get_custom_execute_transition(x)); + function_execute_end_cycle_t * fct = (_param->_get_custom_information()._get_custom_execute_transition(x)); if (fct != NULL) @@ -142,9 +175,37 @@ } } + + if (reg_BUSY_IN and not reg_BUSY_OUT) + { + reg_BUSY_OUT = reg_BUSY_IN; + reg_BUSY_IN = false; + + _execute_operation_out->_timing = _execute_operation_in->_timing ; + _execute_operation_out->_context_id = _execute_operation_in->_context_id ; + _execute_operation_out->_front_end_id = _execute_operation_in->_front_end_id ; + _execute_operation_out->_ooo_engine_id = _execute_operation_in->_ooo_engine_id; + _execute_operation_out->_packet_id = _execute_operation_in->_packet_id ; + _execute_operation_out->_operation = _execute_operation_in->_operation ; + _execute_operation_out->_type = _execute_operation_in->_type ; + _execute_operation_out->_has_immediat = _execute_operation_in->_has_immediat ; + _execute_operation_out->_immediat = _execute_operation_in->_immediat ; + _execute_operation_out->_data_ra = _execute_operation_in->_data_ra ; + _execute_operation_out->_data_rb = _execute_operation_in->_data_rb ; + _execute_operation_out->_data_rc = _execute_operation_in->_data_rc ; + _execute_operation_out->_data_rd = _execute_operation_in->_data_rd ; + _execute_operation_out->_data_re = _execute_operation_in->_data_re ; + _execute_operation_out->_write_rd = _execute_operation_in->_write_rd ; + _execute_operation_out->_num_reg_rd = _execute_operation_in->_num_reg_rd ; + _execute_operation_out->_write_re = _execute_operation_in->_write_re ; + _execute_operation_out->_num_reg_re = _execute_operation_in->_num_reg_re ; + _execute_operation_out->_exception = _execute_operation_in->_exception ; + _execute_operation_out->_no_sequence = _execute_operation_in->_no_sequence ; + _execute_operation_out->_address = _execute_operation_in->_address ; + } + + // each cycle : decrease the latence + if (reg_BUSY_OUT and (_execute_operation_out->_timing._latence > 0)) + _execute_operation_out->_timing._latence --; } - - // each cycle : decrease the latence - if (reg_BUSY and (_execute_operation->_timing._latence > 0)) - _execute_operation->_timing._latence --; #if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -152,5 +213,5 @@ #endif - log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); + log_end(Functionnal_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 88) @@ -31,36 +31,38 @@ uint32_t size_load_queue , execute_timing_t** timing , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)) : - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _nb_general_register (nb_general_register ), - _size_special_data (size_special_data ), - _nb_special_register (nb_special_register ), - _size_store_queue (size_store_queue ), - _size_load_queue (size_load_queue ), - - _size_context_id (log2(nb_context )), - _size_front_end_id (log2(nb_front_end )), - _size_ooo_engine_id (log2(nb_ooo_engine )), - _size_packet_id (log2(nb_packet )), - _size_general_register (log2(nb_general_register)), - _size_special_register (log2(nb_special_register)), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0), - _have_port_load_queue_ptr(_size_load_queue > 1), - - _have_groupe_MAC ( (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence > 0) or - (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence > 0) or - (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB ]._latence > 0)) + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel) { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); - _timing = timing; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; +// _size_general_data = size_general_data ; +// _size_special_data = size_special_data ; +// _nb_general_register = nb_general_register ; +// _nb_special_register = nb_special_register ; +// _size_store_queue = size_store_queue ; +// _size_load_queue = size_load_queue ; + +// _size_context_id = log2(nb_context ); +// _size_front_end_id = log2(nb_front_end ); +// _size_ooo_engine_id = log2(nb_ooo_engine ); +// _size_packet_id = log2(nb_packet ); +// _size_general_register = log2(nb_general_register); +// _size_special_register = log2(nb_special_register); + +// _have_port_context_id = _size_context_id > 0; +// _have_port_front_end_id = _size_front_end_id > 0; +// _have_port_ooo_engine_id = _size_ooo_engine_id > 0; +// _have_port_packet_id = _size_packet_id > 0; +// _have_port_load_queue_ptr= _size_load_queue > 1; + + _have_groupe_MAC = ( (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence > 0) or + (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence > 0) or + (timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB ]._latence > 0)); + + _timing = timing; if (get_custom_information == NULL) @@ -71,48 +73,82 @@ test(); + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_front_end_id = log2(nb_front_end ); + _size_ooo_engine_id = log2(nb_ooo_engine ); + _size_rob_ptr = log2(nb_packet ); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + + _size_load_queue_ptr = log2(size_load_queue ); + _size_store_queue_ptr = log2(size_store_queue); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr= _size_load_queue_ptr> 0; + + copy(); + } + log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Functionnal_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _nb_general_register (param._nb_general_register ), +// _size_special_data (param._size_special_data ), +// _nb_special_register (param._nb_special_register ), +// _size_store_queue (param._size_store_queue ), +// _size_load_queue (param._size_load_queue ), + +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_packet_id (param._have_port_packet_id ), +// _have_port_load_queue_ptr(param._have_port_load_queue_ptr), + +// _have_groupe_MAC (param._have_groupe_MAC ) +// { +// log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); + +// _timing = param._timing; +// _get_custom_information = param._get_custom_information; + +// test(); +// log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Functionnal_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _nb_general_register (param._nb_general_register ), - _size_special_data (param._size_special_data ), - _nb_special_register (param._nb_special_register ), - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ), - _have_port_load_queue_ptr(param._have_port_load_queue_ptr), - - _have_groupe_MAC (param._have_groupe_MAC ) +#define FUNCTION "Functionnal_unit::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); - - _timing = param._timing; - _get_custom_information = param._get_custom_information; - - test(); log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Functionnal_unit::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Functionnal_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_msg_error.cpp (revision 88) @@ -31,10 +31,10 @@ for (uint32_t j=0; j<_nb_operation; j++) if (_timing[i][j]._delay != _timing[i][j]._latence) - test.error("For the type '"+toString(i)+"', and the operation '"+toString(j)+"', the delay and the latence must be equal."); + test.error(toString(_("For the type '%d', and the operation '%d', the delay and the latence must be equal.\n"),i,j)); if (_have_groupe_MAC and ((_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MAC ]._latence == 0) or (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MACRC]._latence == 0) or (_timing[TYPE_SPECIAL][OPERATION_SPECIAL_L_MSB ]._latence == 0))) - test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0."); + test.error("The functionnal unit implement a MAC unit, the latence to operation OPERATION_ALU_L_MAC, OPERATION_ALU_L_MACRC and OPERATION_ALU_L_MSB must be higher than 0.\n"); log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters_print.cpp (revision 88) @@ -32,7 +32,7 @@ xml.singleton_begin("nb_packet "); xml.attribut("value",toString(_nb_packet )); xml.singleton_end(); xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); - xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end(); +// xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end(); xml.singleton_begin("size_special_data "); xml.attribut("value",toString(_size_special_data )); xml.singleton_end(); - xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end(); +// xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Load_store_unit_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/configuration.cfg (revision 88) @@ -6,4 +6,6 @@ 2 2 +1 # speculative_load {none,access,commit,bypass} 0 0 +1 # bypass_memory +1 1 +1 # nb_cache_port +1 1 +1 # nb_inst_memory 2 2 *2 # nb_context 1 1 *2 2 2 *2 # nb_front_end 1 1 *2 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/Memory.h (revision 88) @@ -287,5 +287,5 @@ << i->_data_old << " -> " << i->_data_new << std::endl - << std::hex; + << std::dec; } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/main.cpp (revision 88) @@ -22,4 +22,6 @@ << " - speculative_load (uint32_t)" << endl << " - nb_bypass_memory (uint32_t)" << endl + << " - nb_cache_port (uint32_t)" << endl + << " - nb_inst_memory (uint32_t)" << endl << " - nb_context (uint32_t)" << endl << " - nb_front_end (uint32_t)" << endl @@ -62,4 +64,6 @@ const Tspeculative_load_t _speculative_load = fromString(argv[x++]); const uint32_t _nb_bypass_memory = atoi(argv[x++]); + const uint32_t _nb_cache_port = atoi(argv[x++]); + const uint32_t _nb_inst_memory = atoi(argv[x++]); const uint32_t _nb_context = atoi(argv[x++]); const uint32_t _nb_front_end = atoi(argv[x++]); @@ -81,4 +85,6 @@ _speculative_load , _nb_bypass_memory , + _nb_cache_port , + _nb_inst_memory , _nb_context , _nb_front_end , @@ -88,5 +94,7 @@ _size_special_data , _nb_general_register , - _nb_special_register ); + _nb_special_register , + true //is_toplevel + ); cout << param->print(1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 88) @@ -9,4 +9,5 @@ #include #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" //===================================================================={test} @@ -26,4 +27,6 @@ SPECULATIVE_LOAD_COMMIT, //_speculative_load 0, //_nb_bypass_memory + 1, //_nb_cache_port + 1, //_nb_inst_memory 1, //_nb_context 1, //_nb_front_end @@ -33,5 +36,6 @@ 2 , //_size_special_data 64, //_nb_general_register - 16 //_nb_special_register + 16, //_nb_special_register + true //is_toplevel ); @@ -39,4 +43,14 @@ morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(), @@ -45,5 +59,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -56,69 +70,58 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - sc_signal * in_MEMORY_IN_VAL = new sc_signal (rename.c_str()); - sc_signal * out_MEMORY_IN_ACK = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_CONTEXT_ID = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_FRONT_END_ID = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_PACKET_ID = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_OPERATION = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_TYPE = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_IMMEDIAT = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_DATA_RA = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_DATA_RB = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_DATA_RC = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_WRITE_RD = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_NUM_REG_RD = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_WRITE_RE = new sc_signal (rename.c_str()); - sc_signal * in_MEMORY_IN_NUM_REG_RE = new sc_signal (rename.c_str()); - - sc_signal * out_MEMORY_OUT_VAL = new sc_signal(rename.c_str()); - sc_signal * in_MEMORY_OUT_ACK = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_CONTEXT_ID = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_FRONT_END_ID = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_PACKET_ID = new sc_signal(rename.c_str()); -// sc_signal * out_MEMORY_OUT_OPERATION = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_TYPE = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_WRITE_RD = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_NUM_REG_RD = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_DATA_RD = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_WRITE_RE = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_NUM_REG_RE = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_DATA_RE = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_EXCEPTION = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal(rename.c_str()); - sc_signal * out_MEMORY_OUT_ADDRESS = new sc_signal(rename.c_str()); - - sc_signal * out_DCACHE_REQ_VAL = new sc_signal(rename.c_str()); - sc_signal * in_DCACHE_REQ_ACK = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_REQ_CONTEXT_ID = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_REQ_PACKET_ID = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_REQ_ADDRESS = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_REQ_TYPE = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_REQ_WDATA = new sc_signal(rename.c_str()); - - sc_signal * in_DCACHE_RSP_VAL = new sc_signal(rename.c_str()); - sc_signal * out_DCACHE_RSP_ACK = new sc_signal(rename.c_str()); - sc_signal * in_DCACHE_RSP_CONTEXT_ID = new sc_signal(rename.c_str()); - sc_signal * in_DCACHE_RSP_PACKET_ID = new sc_signal(rename.c_str()); - sc_signal * in_DCACHE_RSP_RDATA = new sc_signal(rename.c_str()); - sc_signal * in_DCACHE_RSP_ERROR = new sc_signal(rename.c_str()); - - sc_signal ** out_BYPASS_MEMORY_VAL = new sc_signal * [_param->_nb_bypass_memory]; - sc_signal ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal * [_param->_nb_bypass_memory]; - sc_signal ** out_BYPASS_MEMORY_NUM_REG = new sc_signal * [_param->_nb_bypass_memory]; - sc_signal ** out_BYPASS_MEMORY_DATA = new sc_signal * [_param->_nb_bypass_memory]; - - for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) - { - out_BYPASS_MEMORY_VAL [i] = new sc_signal(rename.c_str()); - out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal(rename.c_str()); - out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal(rename.c_str()); - out_BYPASS_MEMORY_DATA [i] = new sc_signal(rename.c_str()); - } + // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC1_SC_SIGNAL( in_MEMORY_IN_VAL ," in_MEMORY_IN_VAL ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_IN_ACK ,"out_MEMORY_IN_ACK ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ," in_MEMORY_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ," in_MEMORY_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ," in_MEMORY_IN_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ," in_MEMORY_IN_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_OPERATION ," in_MEMORY_IN_OPERATION ",Toperation_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_TYPE ," in_MEMORY_IN_TYPE ",Ttype_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE," in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ," in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ," in_MEMORY_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ," in_MEMORY_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address + ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ," in_MEMORY_IN_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_memory); // memory address + ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ," in_MEMORY_IN_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (store) + ALLOC1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ," in_MEMORY_IN_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ," in_MEMORY_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) + ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ," in_MEMORY_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) + ALLOC1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ," in_MEMORY_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ," in_MEMORY_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_VAL ,"out_MEMORY_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL( in_MEMORY_OUT_ACK ," in_MEMORY_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,"out_MEMORY_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,"out_MEMORY_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID ,"out_MEMORY_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); +//ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,"out_MEMORY_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_inst_memory); // data (load) + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,"out_MEMORY_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,"out_MEMORY_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,"out_MEMORY_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_cache_port); + ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,"out_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory); + ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"out_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory); + ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,"out_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory); + ALLOC1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,"out_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory); /******************************************************** @@ -131,78 +134,74 @@ (*(_Load_store_unit->in_NRESET)) (*(in_NRESET)); - (*(_Load_store_unit-> in_MEMORY_IN_VAL ))(*( in_MEMORY_IN_VAL )); - (*(_Load_store_unit->out_MEMORY_IN_ACK ))(*(out_MEMORY_IN_ACK )); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_VAL ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_IN_ACK ,_param->_nb_inst_memory); if (_param->_have_port_context_id) - (*(_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(*( in_MEMORY_IN_CONTEXT_ID )); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); if (_param->_have_port_front_end_id) - (*(_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(*( in_MEMORY_IN_FRONT_END_ID )); - if (_param->_have_port_ooo_engine_id) - (*(_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(*( in_MEMORY_IN_OOO_ENGINE_ID )); - if (_param->_have_port_packet_id) - (*(_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(*( in_MEMORY_IN_PACKET_ID )); - (*(_Load_store_unit-> in_MEMORY_IN_OPERATION ))(*( in_MEMORY_IN_OPERATION )); - (*(_Load_store_unit-> in_MEMORY_IN_TYPE ))(*( in_MEMORY_IN_TYPE )); - (*(_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(*( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE)); - if (_param->_have_port_load_queue_ptr) - (*(_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(*( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE )); - (*(_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(*( in_MEMORY_IN_HAS_IMMEDIAT )); - (*(_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(*( in_MEMORY_IN_IMMEDIAT )); - (*(_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(*( in_MEMORY_IN_DATA_RA )); - (*(_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(*( in_MEMORY_IN_DATA_RB )); - (*(_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(*( in_MEMORY_IN_DATA_RC )); - (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(*( in_MEMORY_IN_WRITE_RD )); - (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(*( in_MEMORY_IN_NUM_REG_RD )); - (*(_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(*( in_MEMORY_IN_WRITE_RE )); - (*(_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(*( in_MEMORY_IN_NUM_REG_RE )); - - (*(_Load_store_unit->out_MEMORY_OUT_VAL ))(*(out_MEMORY_OUT_VAL )); - (*(_Load_store_unit-> in_MEMORY_OUT_ACK ))(*( in_MEMORY_OUT_ACK )); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); + if (_param->_have_port_rob_ptr) + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); + + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); if (_param->_have_port_context_id) - (*(_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))(*(out_MEMORY_OUT_CONTEXT_ID )); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); if (_param->_have_port_front_end_id) - (*(_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))(*(out_MEMORY_OUT_FRONT_END_ID )); - if (_param->_have_port_ooo_engine_id) - (*(_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))(*(out_MEMORY_OUT_OOO_ENGINE_ID )); - if (_param->_have_port_packet_id) - (*(_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))(*(out_MEMORY_OUT_PACKET_ID )); -// (*(_Load_store_unit->out_MEMORY_OUT_OPERATION ))(*(out_MEMORY_OUT_OPERATION )); - (*(_Load_store_unit->out_MEMORY_OUT_TYPE ))(*(out_MEMORY_OUT_TYPE )); - (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))(*(out_MEMORY_OUT_WRITE_RD )); - (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))(*(out_MEMORY_OUT_NUM_REG_RD )); - (*(_Load_store_unit->out_MEMORY_OUT_DATA_RD ))(*(out_MEMORY_OUT_DATA_RD )); - (*(_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))(*(out_MEMORY_OUT_WRITE_RE )); - (*(_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))(*(out_MEMORY_OUT_NUM_REG_RE )); - (*(_Load_store_unit->out_MEMORY_OUT_DATA_RE ))(*(out_MEMORY_OUT_DATA_RE )); - (*(_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))(*(out_MEMORY_OUT_EXCEPTION )); - (*(_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))(*(out_MEMORY_OUT_NO_SEQUENCE )); - (*(_Load_store_unit->out_MEMORY_OUT_ADDRESS ))(*(out_MEMORY_OUT_ADDRESS )); - - (*(_Load_store_unit->out_DCACHE_REQ_VAL ))(*(out_DCACHE_REQ_VAL )); - (*(_Load_store_unit-> in_DCACHE_REQ_ACK ))(*( in_DCACHE_REQ_ACK )); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); + if (_param->_have_port_rob_ptr) + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); +//INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); + + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_VAL ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_REQ_ACK ,_param->_nb_cache_port); if (_param->_have_port_dcache_context_id) - (*(_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))(*(out_DCACHE_REQ_CONTEXT_ID)); - (*(_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))(*(out_DCACHE_REQ_PACKET_ID )); - (*(_Load_store_unit->out_DCACHE_REQ_ADDRESS ))(*(out_DCACHE_REQ_ADDRESS )); - (*(_Load_store_unit->out_DCACHE_REQ_TYPE ))(*(out_DCACHE_REQ_TYPE )); - (*(_Load_store_unit->out_DCACHE_REQ_WDATA ))(*(out_DCACHE_REQ_WDATA )); - - (*(_Load_store_unit-> in_DCACHE_RSP_VAL ))(*( in_DCACHE_RSP_VAL )); - (*(_Load_store_unit->out_DCACHE_RSP_ACK ))(*(out_DCACHE_RSP_ACK )); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); + + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_VAL ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_DCACHE_RSP_ACK ,_param->_nb_cache_port); if (_param->_have_port_dcache_context_id) - (*(_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(*( in_DCACHE_RSP_CONTEXT_ID)); - (*(_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(*( in_DCACHE_RSP_PACKET_ID )); - (*(_Load_store_unit-> in_DCACHE_RSP_RDATA ))(*( in_DCACHE_RSP_RDATA )); - (*(_Load_store_unit-> in_DCACHE_RSP_ERROR ))(*( in_DCACHE_RSP_ERROR )); - - { - for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) - { - (*(_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))(*(out_BYPASS_MEMORY_VAL [i])); - if (_param->_have_port_ooo_engine_id) - (*(_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))(*(out_BYPASS_MEMORY_OOO_ENGINE_ID [i])); - (*(_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))(*(out_BYPASS_MEMORY_NUM_REG [i])); - (*(_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))(*(out_BYPASS_MEMORY_DATA [i])); - } - } + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); + INSTANCE1_SC_SIGNAL(_Load_store_unit, in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); + + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); + if (_param->_have_port_ooo_engine_id) + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); + INSTANCE1_SC_SIGNAL(_Load_store_unit,out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); + + cout << "<" << name << "> Start Simulation ............" << endl; Time * _time = new Time(); @@ -238,8 +237,8 @@ LABEL("Initialisation"); - in_MEMORY_IN_VAL ->write(0); - in_MEMORY_OUT_ACK->write(0); - in_DCACHE_REQ_ACK->write(0); - in_DCACHE_RSP_VAL->write(0); + in_MEMORY_IN_VAL [0]->write(0); + in_MEMORY_OUT_ACK[0]->write(0); + in_DCACHE_REQ_ACK[0]->write(0); + in_DCACHE_RSP_VAL[0]->write(0); in_NRESET ->write(0); @@ -419,50 +418,50 @@ can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write]; } - in_MEMORY_IN_VAL ->write(can_execute); + in_MEMORY_IN_VAL [0]->write(can_execute); if (not fifo_request.empty()) { if (_param->_have_port_context_id) - in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id ); + in_MEMORY_IN_CONTEXT_ID [0]->write (fifo_request.top()._context_id ); if (_param->_have_port_front_end_id) - in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id ); + in_MEMORY_IN_FRONT_END_ID [0]->write (fifo_request.top()._front_end_id ); if (_param->_have_port_ooo_engine_id) - in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id ); - if (_param->_have_port_packet_id) - in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id ); - in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation ); - in_MEMORY_IN_TYPE ->write (fifo_request.top()._type ); - in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write); + in_MEMORY_IN_OOO_ENGINE_ID [0]->write (fifo_request.top()._ooo_engine_id ); + if (_param->_have_port_rob_ptr) + in_MEMORY_IN_PACKET_ID [0]->write (fifo_request.top()._packet_id ); + in_MEMORY_IN_OPERATION [0]->write (fifo_request.top()._operation ); + in_MEMORY_IN_TYPE [0]->write (fifo_request.top()._type ); + in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[0]->write (fifo_request.top()._store_queue_ptr_write); if (_param->_have_port_load_queue_ptr) - in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write ); - in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat ); - in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra ); - in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb ); -// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd ); - in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd ); + in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE [0]->write (fifo_request.top()._load_queue_ptr_write ); + in_MEMORY_IN_IMMEDIAT [0]->write (fifo_request.top()._immediat ); + in_MEMORY_IN_DATA_RA [0]->write (fifo_request.top()._data_ra ); + in_MEMORY_IN_DATA_RB [0]->write (fifo_request.top()._data_rb ); +// in_MEMORY_IN_WRITE_RD [0]->write (fifo_request.top()._write_rd ); + in_MEMORY_IN_NUM_REG_RD [0]->write (fifo_request.top()._num_reg_rd ); } - in_MEMORY_OUT_ACK->write((rand()%100)write((rand()%100)write((rand()%100)write((rand()%100)have_rsp (); - in_DCACHE_RSP_VAL->write(have_rsp); + in_DCACHE_RSP_VAL[0]->write(have_rsp); if (have_rsp) { - in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id); - in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id ); - in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata ); - in_DCACHE_RSP_ERROR ->write(_cache->front()._error ); + in_DCACHE_RSP_CONTEXT_ID[0]->write(_cache->front()._context_id); + in_DCACHE_RSP_PACKET_ID [0]->write(_cache->front()._packet_id ); + in_DCACHE_RSP_RDATA [0]->write(_cache->front()._rdata ); + in_DCACHE_RSP_ERROR [0]->write(_cache->front()._error ); } SC_START(0); - LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL ->read(),out_MEMORY_IN_ACK ->read()); - if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read()) + LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL [0]->read(),out_MEMORY_IN_ACK [0]->read()); + if ( in_MEMORY_IN_VAL [0]->read() and out_MEMORY_IN_ACK [0]->read()) { - Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read(); + Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID[0]->read(); LABEL(" * Accepted MEMORY_IN : %d",packet_id); @@ -483,8 +482,8 @@ } - LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL->read(),in_MEMORY_OUT_ACK ->read()); - if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read()) + LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL[0]->read(),in_MEMORY_OUT_ACK [0]->read()); + if (out_MEMORY_OUT_VAL[0]->read() and in_MEMORY_OUT_ACK[0]->read()) { - Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read(); + Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID[0]->read(); LABEL(" * Accepted MEMORY_OUT : %d",packet_id); @@ -499,5 +498,5 @@ else { - if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) + if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) { nb_request_memory_out ++; @@ -508,5 +507,5 @@ { std::cout << "seth - have a load_speculative." << std::endl; - tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait); + tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD[0]->read() != tab_request[packet_id]._data_wait); tab_request[packet_id]._previous_load_speculative = 1; } @@ -516,14 +515,14 @@ // a lot of test - TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id ); - TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id ); - TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id ); - TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id); -// TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation ); - TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY ); + TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID [0]->read(), tab_request[packet_id]._packet_id ); + TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID [0]->read(), tab_request[packet_id]._context_id ); + TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID [0]->read(), tab_request[packet_id]._front_end_id ); + TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); +// TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); + TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); if (is_operation_memory_load (tab_request[packet_id]._operation)) { - TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd ); + TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD [0]->read(), tab_request[packet_id]._num_reg_rd ); } @@ -532,9 +531,9 @@ bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation)))); bool berr = (address >= size_memory); - Texception_t exception = out_MEMORY_OUT_EXCEPTION->read(); + Texception_t exception = out_MEMORY_OUT_EXCEPTION[0]->read(); if (is_operation_memory_store(tab_request[packet_id]._operation)) { - TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0); + TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 0); // store. @@ -568,5 +567,5 @@ if (test_result_ko) { - TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address); + TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); } } @@ -578,5 +577,5 @@ bool is_load = is_operation_memory_load(tab_request[packet_id]._operation); - if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) + if (not (out_MEMORY_OUT_EXCEPTION[0]->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) { bool test_result_ko = false; @@ -586,5 +585,5 @@ // IS A LOAD :D TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION); - TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1); + TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), 1); } else @@ -592,5 +591,5 @@ { TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT); - TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load); + TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); test_result_ko = true; } @@ -599,5 +598,5 @@ { TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR); - TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load); + TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load); test_result_ko = true; } @@ -605,37 +604,37 @@ { TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE); - TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative); + TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD[0]->read(), is_load and not tab_request[packet_id]._previous_load_speculative); } // In all case : test data if (test_result_ko) { - TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address); + TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), address); } else { - TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait); + TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD[0]->read(), tab_request[packet_id]._data_wait); } } else { - TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1); + TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD [0]->read(), 1); } } } - LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL->read(),in_DCACHE_REQ_ACK ->read()); - if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read()) + LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL[0]->read(),in_DCACHE_REQ_ACK [0]->read()); + if (out_DCACHE_REQ_VAL[0]->read() and in_DCACHE_REQ_ACK[0]->read()) { Tcontext_t context_id; Tpacket_t packet_id ; - Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read(); + Tdcache_address_t address = out_DCACHE_REQ_ADDRESS[0]->read(); Tdcache_data_t rdata; Tdcache_error_t error = 0; if (_param->_have_port_dcache_context_id) - context_id = out_DCACHE_REQ_CONTEXT_ID->read(); + context_id = out_DCACHE_REQ_CONTEXT_ID[0]->read(); else context_id = 0; - packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1; + packet_id = (out_DCACHE_REQ_PACKET_ID [0]->read())>>1; LABEL(" * Accepted DCACHE_REQ : %d",packet_id); @@ -649,23 +648,23 @@ else { - rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read()); + rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE[0]->read(), out_DCACHE_REQ_WDATA[0]->read()); LABEL(" * rdata : 0x%x",rdata); } // test type : send or not a respons ! - if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64) or - ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or - (out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) ))) + if ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_SYNCHRONIZATION) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_8 ) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_16) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_32) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_LOAD_64) or + ((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_8 ) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_16) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_32) or + (out_DCACHE_REQ_TYPE[0]->read() == DCACHE_TYPE_STORE_64) ))) { LABEL(" * have_dcache_rsp"); _cache->push (context_id, - out_DCACHE_REQ_PACKET_ID ->read(), + out_DCACHE_REQ_PACKET_ID [0]->read(), rdata, error); @@ -673,6 +672,6 @@ } - LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL->read(),out_DCACHE_RSP_ACK ->read()); - if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read()) + LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL[0]->read(),out_DCACHE_RSP_ACK [0]->read()); + if (in_DCACHE_RSP_VAL[0]->read() and out_DCACHE_RSP_ACK[0]->read()) { _cache->pop(); @@ -704,62 +703,61 @@ delete in_NRESET; - delete in_MEMORY_IN_VAL ; - delete out_MEMORY_IN_ACK ; - delete in_MEMORY_IN_CONTEXT_ID ; - delete in_MEMORY_IN_FRONT_END_ID ; - delete in_MEMORY_IN_OOO_ENGINE_ID ; - delete in_MEMORY_IN_PACKET_ID ; - delete in_MEMORY_IN_OPERATION ; - delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; - delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; - delete in_MEMORY_IN_HAS_IMMEDIAT; - delete in_MEMORY_IN_IMMEDIAT ; - delete in_MEMORY_IN_DATA_RA ; - delete in_MEMORY_IN_DATA_RB ; - delete in_MEMORY_IN_DATA_RC ; - delete in_MEMORY_IN_WRITE_RD ; - delete in_MEMORY_IN_NUM_REG_RD ; - delete in_MEMORY_IN_WRITE_RE ; - delete in_MEMORY_IN_NUM_REG_RE ; - - delete out_MEMORY_OUT_VAL ; - delete in_MEMORY_OUT_ACK ; - delete out_MEMORY_OUT_CONTEXT_ID; - delete out_MEMORY_OUT_FRONT_END_ID; - delete out_MEMORY_OUT_OOO_ENGINE_ID; - delete out_MEMORY_OUT_PACKET_ID ; -// delete out_MEMORY_OUT_OPERATION ; - delete out_MEMORY_OUT_TYPE ; - delete out_MEMORY_OUT_WRITE_RD ; - delete out_MEMORY_OUT_NUM_REG_RD; - delete out_MEMORY_OUT_DATA_RD ; - delete out_MEMORY_OUT_WRITE_RE ; - delete out_MEMORY_OUT_NUM_REG_RE; - delete out_MEMORY_OUT_DATA_RE ; - delete out_MEMORY_OUT_EXCEPTION ; - delete out_MEMORY_OUT_NO_SEQUENCE; - delete out_MEMORY_OUT_ADDRESS ; - - delete out_DCACHE_REQ_VAL ; - delete in_DCACHE_REQ_ACK ; - delete out_DCACHE_REQ_CONTEXT_ID; - delete out_DCACHE_REQ_PACKET_ID ; - delete out_DCACHE_REQ_ADDRESS ; - delete out_DCACHE_REQ_TYPE ; - delete out_DCACHE_REQ_WDATA ; - - delete in_DCACHE_RSP_VAL ; - delete out_DCACHE_RSP_ACK ; - delete in_DCACHE_RSP_CONTEXT_ID; - delete in_DCACHE_RSP_PACKET_ID ; - delete in_DCACHE_RSP_RDATA ; - delete in_DCACHE_RSP_ERROR ; - - { - delete [] out_BYPASS_MEMORY_VAL ; - delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; - delete [] out_BYPASS_MEMORY_NUM_REG ; - delete [] out_BYPASS_MEMORY_DATA ; - } + DELETE1_SC_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory); + + DELETE1_SC_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); +//DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory); + DELETE1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory); + + DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port); + + DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port); + + DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); + DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); + DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); + DELETE1_SC_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (revision 88) @@ -90,66 +90,65 @@ // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ; - public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ; - public : SC_IN (Tcontext_t ) * in_MEMORY_IN_CONTEXT_ID ; - public : SC_IN (Tcontext_t ) * in_MEMORY_IN_FRONT_END_ID; - public : SC_IN (Tcontext_t ) * in_MEMORY_IN_OOO_ENGINE_ID; - public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ; - public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ; - public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ; - public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; - public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; - public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT; - public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ; // memory address - public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ; // memory address - public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ; // data (store) - public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ; - public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ; // = (operation==load) - public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ; // destination (load) - public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ; - public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ; + public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_VAL ;//[nb_inst_memory] + public : SC_OUT(Tcontrol_t ) ** out_MEMORY_IN_ACK ;//[nb_inst_memory] + public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_CONTEXT_ID ;//[nb_inst_memory] + public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_FRONT_END_ID ;//[nb_inst_memory] + public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_OOO_ENGINE_ID ;//[nb_inst_memory] + public : SC_IN (Tpacket_t ) ** in_MEMORY_IN_PACKET_ID ;//[nb_inst_memory] + public : SC_IN (Toperation_t ) ** in_MEMORY_IN_OPERATION ;//[nb_inst_memory] + public : SC_IN (Ttype_t ) ** in_MEMORY_IN_TYPE ;//[nb_inst_memory] + public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory] + public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory] + public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_HAS_IMMEDIAT ;//[nb_inst_memory] + public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_IMMEDIAT ;//[nb_inst_memory] // memory address + public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RA ;//[nb_inst_memory] // memory address + public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RB ;//[nb_inst_memory] // data (store) + public : SC_IN (Tspecial_data_t ) ** in_MEMORY_IN_DATA_RC ;//[nb_inst_memory] + public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RD ;//[nb_inst_memory] // = (operation==load) + public : SC_IN (Tgeneral_address_t) ** in_MEMORY_IN_NUM_REG_RD ;//[nb_inst_memory] // destination (load) + public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RE ;//[nb_inst_memory] + public : SC_IN (Tspecial_address_t) ** in_MEMORY_IN_NUM_REG_RE ;//[nb_inst_memory] // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ; - public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ; - public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID; - public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_FRONT_END_ID; - public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID; - public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ; -//public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ; - public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ; - public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ; // = (operation==load) - public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD; // destination (load) - public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ; // data (load) - public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ; - public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE; - public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ; - public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ; - public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_NO_SEQUENCE; - public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_ADDRESS ; + public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_VAL ;//[nb_inst_memory] + public : SC_IN (Tcontrol_t ) ** in_MEMORY_OUT_ACK ;//[nb_inst_memory] + public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_CONTEXT_ID ;//[nb_inst_memory] + public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_FRONT_END_ID ;//[nb_inst_memory] + public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_OOO_ENGINE_ID ;//[nb_inst_memory] + public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] +//public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] + public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] + public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) + public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) + public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_DATA_RD ;//[nb_inst_memory] // data (load) + public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RE ;//[nb_inst_memory] + public : SC_OUT(Tspecial_address_t) ** out_MEMORY_OUT_NUM_REG_RE ;//[nb_inst_memory] + public : SC_OUT(Tspecial_data_t ) ** out_MEMORY_OUT_DATA_RE ;//[nb_inst_memory] + public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] + public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] + public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] - // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ; - public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ; - public : SC_OUT(Tcontext_t ) * out_DCACHE_REQ_CONTEXT_ID; - public : SC_OUT(Tpacket_t ) * out_DCACHE_REQ_PACKET_ID ; - public : SC_OUT(Tdcache_address_t ) * out_DCACHE_REQ_ADDRESS ; - public : SC_OUT(Tdcache_type_t ) * out_DCACHE_REQ_TYPE ; - public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ; + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_cache_port] + public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_cache_port] + public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_CONTEXT_ID ;//[nb_cache_port] + public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_cache_port] + public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_cache_port] + public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_cache_port] + public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_cache_port] // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ; - public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ; - public : SC_IN (Tcontext_t ) * in_DCACHE_RSP_CONTEXT_ID; - public : SC_IN (Tpacket_t ) * in_DCACHE_RSP_PACKET_ID ; - public : SC_IN (Tdcache_data_t ) * in_DCACHE_RSP_RDATA ; - public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ; + public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_cache_port] + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_cache_port] + public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_CONTEXT_ID ;//[nb_cache_port] + public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_cache_port] + public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_cache_port] + public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_cache_port] // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; - public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; - public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; - public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; + public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; //[nb_bypass_memory] + public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; //[nb_bypass_memory] + public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; //[nb_bypass_memory] + public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; //[nb_bypass_memory] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -177,12 +176,14 @@ // signal public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ; - - private : Tcontrol_t internal_MEMORY_IN_ACK; - private : Tcontrol_t internal_MEMORY_OUT_VAL; + + private : Tcontrol_t internal_MEMORY_IN_ACK ; + private : uint32_t internal_MEMORY_IN_PORT ; + + private : Tcontrol_t internal_MEMORY_OUT_VAL ; private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; - public : Tlsq_ptr_t internal_MEMORY_OUT_PTR; - - private : Tcontrol_t internal_DCACHE_RSP_ACK; - private : Tcontrol_t internal_DCACHE_REQ_VAL; + private : Tlsq_ptr_t internal_MEMORY_OUT_PTR ; + + private : Tcontrol_t internal_DCACHE_RSP_ACK ; + private : Tcontrol_t internal_DCACHE_REQ_VAL ; private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Parameters.h (revision 88) @@ -27,41 +27,42 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_store_queue ; - public : const uint32_t _size_load_queue ; - public : const uint32_t _size_speculative_access_queue; - public : const uint32_t _nb_port_check ; - public : const Tspeculative_load_t _speculative_load ; - public : const uint32_t _nb_bypass_memory ; -//public : const uint32_t _nb_cache_port ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _nb_special_register ; + public : uint32_t _size_store_queue ; + public : uint32_t _size_load_queue ; + public : uint32_t _size_speculative_access_queue; + public : uint32_t _nb_port_check ; + public : Tspeculative_load_t _speculative_load ; + public : uint32_t _nb_bypass_memory ; + public : uint32_t _nb_cache_port ; + public : uint32_t _nb_inst_memory ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; - public : const uint32_t _size_address_store_queue ; - public : const uint32_t _size_address_load_queue ; - public : const uint32_t _size_address_speculative_access_queue; - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; - public : const uint32_t _size_dcache_context_id ; - public : const uint32_t _size_dcache_packet_id ; +//public : uint32_t _size_address_store_queue ; +//public : uint32_t _size_address_load_queue ; + public : uint32_t _size_speculative_access_queue_ptr ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; + public : uint32_t _size_dcache_context_id ; + public : uint32_t _size_dcache_packet_id ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; - public : const bool _have_port_dcache_context_id ; - public : const bool _have_port_load_queue_ptr ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; + public : bool _have_port_dcache_context_id ; +//public : bool _have_port_load_queue_ptr ; - public : const Tdcache_address_t _mask_address_lsb ; - public : const Tdcache_address_t _mask_address_msb ; + public : Tdcache_address_t _mask_address_lsb ; + public : Tdcache_address_t _mask_address_msb ; //-----[ methods ]----------------------------------------------------------- @@ -72,4 +73,6 @@ Tspeculative_load_t speculative_load , uint32_t nb_bypass_memory , + uint32_t nb_cache_port , + uint32_t nb_inst_memory , uint32_t nb_context , uint32_t nb_front_end , @@ -79,8 +82,12 @@ uint32_t size_special_data , uint32_t nb_general_register , - uint32_t nb_special_register ); + uint32_t nb_special_register , + bool is_toplevel=false); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); +#if DEBUG_Load_store_unit == true + log_printf(INFO,Load_store_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + #ifdef SYSTEMC log_printf(INFO,Load_store_unit,FUNCTION,"Allocation"); @@ -46,17 +52,25 @@ #ifdef STATISTICS - log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); - - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Load_store_unit,FUNCTION,"Allocation of statistics"); + + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); - - vhdl(); -#endif - -#ifdef SYSTEMC + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Load_store_unit,FUNCTION,"Generate the vhdl"); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { // Function pointer @@ -84,5 +98,15 @@ internal_DCACHE_RSP_ACK = 1; - PORT_WRITE(out_DCACHE_RSP_ACK, 1); + PORT_WRITE(out_DCACHE_RSP_ACK [0], internal_DCACHE_RSP_ACK); + for (uint32_t i=1; i<_param->_nb_cache_port; ++i) + { + PORT_WRITE(out_DCACHE_RSP_ACK [i], 0); + PORT_WRITE(out_DCACHE_REQ_VAL [i], 0); + } + + for (uint32_t i=1; i<_param->_nb_inst_memory; i++) + { + PORT_WRITE(out_MEMORY_OUT_VAL [i], 0); + } log_printf(INFO,Load_store_unit,FUNCTION,"Method - transition"); @@ -111,9 +135,16 @@ dont_initialize (); sensitive_neg << *(in_CLOCK); - sensitive << *(in_MEMORY_IN_OPERATION); - -#ifdef SYSTEMCASS_SPECIFIC - // List dependency information - (*(out_MEMORY_IN_ACK)) (*(in_MEMORY_IN_OPERATION)); + for (uint32_t i=0; i<_param->_nb_inst_memory; i++) + sensitive << (*(in_MEMORY_IN_VAL [i])) + << (*(in_MEMORY_IN_OPERATION [i])); + +#ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_inst_memory; i++) +// for (uint32_t x=0; x<_param->_nb_inst_memory; x++) + { + (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_VAL [i])); + (*(out_MEMORY_IN_ACK [i])) (*(in_MEMORY_IN_OPERATION [i])); + } #endif @@ -137,5 +168,5 @@ // List dependency information #endif - + } #endif log_printf(FUNC,Load_store_unit,FUNCTION,"End"); @@ -149,7 +180,10 @@ #ifdef STATISTICS - log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); - - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Load_store_unit,FUNCTION,"Generate Statistics file"); + + delete _stat; + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 88) @@ -3,9 +3,10 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -37,5 +38,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface * interface = _interfaces->set_interface("" @@ -43,5 +44,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -50,142 +51,106 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } - // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("memory_in" -#ifdef POSITION - ,IN - ,WEST - ,"Instruction from Reservations station" -#endif - ); + ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); - in_MEMORY_IN_VAL = interface->set_signal_valack_in (VAL); - out_MEMORY_IN_ACK = interface->set_signal_valack_out (ACK); - - if (_param->_have_port_context_id) - in_MEMORY_IN_CONTEXT_ID = interface->set_signal_in ("context_id" ,_param->_size_context_id ); - if (_param->_have_port_front_end_id) - in_MEMORY_IN_FRONT_END_ID = interface->set_signal_in ("front_end_id" ,_param->_size_front_end_id ); - if (_param->_have_port_ooo_engine_id) - in_MEMORY_IN_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id ); - if (_param->_have_port_packet_id) - in_MEMORY_IN_PACKET_ID = interface->set_signal_in ("packet_id" ,_param->_size_packet_id ); - in_MEMORY_IN_OPERATION = interface->set_signal_in ("operation" ,_param->_size_operation ); - in_MEMORY_IN_TYPE = interface->set_signal_in ("type" ,_param->_size_type ); - in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage - if (_param->_have_port_load_queue_ptr) - in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,_param->_size_address_load_queue ); - in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat",1 ); - in_MEMORY_IN_IMMEDIAT = interface->set_signal_in ("immediat" ,_param->_size_general_data ); - in_MEMORY_IN_DATA_RA = interface->set_signal_in ("data_ra" ,_param->_size_general_data ); - in_MEMORY_IN_DATA_RB = interface->set_signal_in ("data_rb" ,_param->_size_general_data ); - in_MEMORY_IN_DATA_RC = interface->set_signal_in ("data_rc" ,_param->_size_special_data ); - in_MEMORY_IN_WRITE_RD = interface->set_signal_in ("write_rd" ,1 ); - in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in ("num_reg_rd" ,1 ); - in_MEMORY_IN_WRITE_RE = interface->set_signal_in ("write_re" ,1 ); - in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in ("num_reg_re" ,1 ); + ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); + ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,1 ); } - // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("memory_out" -#ifdef POSITION - ,OUT - ,EAST - ,"Instruction to write queue" -#endif - ); + ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); - out_MEMORY_OUT_VAL = interface->set_signal_valack_out(VAL); - in_MEMORY_OUT_ACK = interface->set_signal_valack_in (ACK); - if (_param->_have_port_context_id) - out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out ("context_id" ,_param->_size_context_id ); - if (_param->_have_port_front_end_id) - out_MEMORY_OUT_FRONT_END_ID = interface->set_signal_out ("front_end_id" ,_param->_size_front_end_id ); - if (_param->_have_port_ooo_engine_id) - out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out ("ooo_engine_id" ,_param->_size_ooo_engine_id ); - if (_param->_have_port_packet_id) - out_MEMORY_OUT_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_packet_id ); -// out_MEMORY_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); - out_MEMORY_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); - out_MEMORY_OUT_WRITE_RD = interface->set_signal_out ("write_rd" ,1 ); - out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out ("num_reg_rd" ,_param->_size_general_register ); - out_MEMORY_OUT_DATA_RD = interface->set_signal_out ("data_rd" ,_param->_size_general_data ); - out_MEMORY_OUT_WRITE_RE = interface->set_signal_out ("write_re" ,1 ); - out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out ("num_reg_re" ,_param->_size_general_register ); - out_MEMORY_OUT_DATA_RE = interface->set_signal_out ("data_re" ,_param->_size_general_data ); - out_MEMORY_OUT_EXCEPTION = interface->set_signal_out ("exception" ,_param->_size_exception ); - out_MEMORY_OUT_NO_SEQUENCE = interface->set_signal_out ("no_sequence" ,1 ); - out_MEMORY_OUT_ADDRESS = interface->set_signal_out ("address" ,_param->_size_general_data ); + ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); } - // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("dcache_req" -#ifdef POSITION - ,OUT - ,NORTH - ,"Request port to dcache" -#endif - ); + ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); - out_DCACHE_REQ_VAL = interface->set_signal_valack_out(VAL); - in_DCACHE_REQ_ACK = interface->set_signal_valack_in (ACK); - if (_param->_have_port_dcache_context_id) - out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out ("context_id",_param->_size_dcache_context_id ); - out_DCACHE_REQ_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_dcache_packet_id ); - out_DCACHE_REQ_ADDRESS = interface->set_signal_out ("address" ,_param->_size_general_data); - out_DCACHE_REQ_TYPE = interface->set_signal_out ("type" ,_param->_size_dcache_type ); - out_DCACHE_REQ_WDATA = interface->set_signal_out ("wdata" ,_param->_size_general_data); + ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); } - // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - Interface_fifo * interface = _interfaces->set_interface("dcache_rsp" -#ifdef POSITION - ,IN - ,NORTH - ,"Respons port from dcache" -#endif - ); + ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); - in_DCACHE_RSP_VAL = interface->set_signal_valack_in (VAL); - out_DCACHE_RSP_ACK = interface->set_signal_valack_out(ACK); - if (_param->_have_port_dcache_context_id) - in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in ("context_id",_param->_size_dcache_context_id ); - in_DCACHE_RSP_PACKET_ID = interface->set_signal_in ("packet_id" ,_param->_size_dcache_packet_id ); - in_DCACHE_RSP_RDATA = interface->set_signal_in ("rdata" ,_param->_size_general_data); - in_DCACHE_RSP_ERROR = interface->set_signal_in ("error" ,_param->_size_dcache_error); + ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); } - // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -// if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) - { - out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_bypass_memory]; - if (_param->_have_port_ooo_engine_id) - out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_bypass_memory]; - out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory]; - out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_bypass_memory]; - - for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) - { - Interface_fifo * interface = _interfaces->set_interface("memory_out" -#ifdef POSITION - ,OUT - ,NORTH - ,"Bypass between the load queue and the reservation station" -#endif - ); + { + ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); - out_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_out(VAL); - if (_param->_have_port_ooo_engine_id) - out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out ("ooo_engine_id", _param->_size_ooo_engine_id); - out_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_out ("num_reg" , _param->_size_general_register); - out_BYPASS_MEMORY_DATA [i] = interface->set_signal_out ("data" , _param->_size_general_data); - } - } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); + ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id ); + ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); + } + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +// internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; + +// internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; +// internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; +// internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; +// internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; + +// internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; +// internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; +// internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (revision 88) @@ -6,9 +6,10 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -28,4 +29,6 @@ log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); + if (usage_is_set(_usage,USE_SYSTEMC)) + { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) delete in_CLOCK ; @@ -33,74 +36,77 @@ delete in_NRESET; - delete in_MEMORY_IN_VAL ; - delete out_MEMORY_IN_ACK ; - if (_param->_have_port_context_id) - delete in_MEMORY_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete in_MEMORY_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete in_MEMORY_IN_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) - delete in_MEMORY_IN_PACKET_ID ; - delete in_MEMORY_IN_OPERATION ; - delete in_MEMORY_IN_TYPE ; - delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ; - delete in_MEMORY_IN_HAS_IMMEDIAT; - delete in_MEMORY_IN_IMMEDIAT ; - delete in_MEMORY_IN_DATA_RA ; - delete in_MEMORY_IN_DATA_RB ; - delete in_MEMORY_IN_DATA_RC ; - delete in_MEMORY_IN_WRITE_RD ; - delete in_MEMORY_IN_NUM_REG_RD ; - delete in_MEMORY_IN_WRITE_RE ; - delete in_MEMORY_IN_NUM_REG_RE ; + DELETE1_SIGNAL( in_MEMORY_IN_VAL ,_param->_nb_inst_memory,1); + DELETE1_SIGNAL(out_MEMORY_IN_ACK ,_param->_nb_inst_memory,1); + DELETE1_SIGNAL( in_MEMORY_IN_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); + DELETE1_SIGNAL( in_MEMORY_IN_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_MEMORY_IN_OOO_ENGINE_ID ,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL( in_MEMORY_IN_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); + DELETE1_SIGNAL( in_MEMORY_IN_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); + DELETE1_SIGNAL( in_MEMORY_IN_TYPE ,_param->_nb_inst_memory,_param->_size_type ); + DELETE1_SIGNAL( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_memory,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_memory,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL( in_MEMORY_IN_HAS_IMMEDIAT ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL( in_MEMORY_IN_IMMEDIAT ,_param->_nb_inst_memory,_param->_size_general_data ); + DELETE1_SIGNAL( in_MEMORY_IN_DATA_RA ,_param->_nb_inst_memory,_param->_size_general_data ); + DELETE1_SIGNAL( in_MEMORY_IN_DATA_RB ,_param->_nb_inst_memory,_param->_size_general_data ); + DELETE1_SIGNAL( in_MEMORY_IN_DATA_RC ,_param->_nb_inst_memory,_param->_size_special_data ); + DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RD ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RD ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL( in_MEMORY_IN_WRITE_RE ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL( in_MEMORY_IN_NUM_REG_RE ,_param->_nb_inst_memory,1 ); + + DELETE1_SIGNAL(out_MEMORY_OUT_VAL ,_param->_nb_inst_memory,1); + DELETE1_SIGNAL( in_MEMORY_OUT_ACK ,_param->_nb_inst_memory,1); + DELETE1_SIGNAL(out_MEMORY_OUT_CONTEXT_ID ,_param->_nb_inst_memory,_param->_size_context_id ); + DELETE1_SIGNAL(out_MEMORY_OUT_FRONT_END_ID ,_param->_nb_inst_memory,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_MEMORY_OUT_OOO_ENGINE_ID,_param->_nb_inst_memory,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); +// DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); + DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); + DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); + DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RD ,_param->_nb_inst_memory,_param->_size_general_data ); + DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RE ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RE ,_param->_nb_inst_memory,_param->_size_general_register ); + DELETE1_SIGNAL(out_MEMORY_OUT_DATA_RE ,_param->_nb_inst_memory,_param->_size_general_data ); + DELETE1_SIGNAL(out_MEMORY_OUT_EXCEPTION ,_param->_nb_inst_memory,_param->_size_exception ); + DELETE1_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,_param->_nb_inst_memory,1 ); + DELETE1_SIGNAL(out_MEMORY_OUT_ADDRESS ,_param->_nb_inst_memory,_param->_size_general_data ); + + DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_cache_port,1); + DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_cache_port,1); + DELETE1_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); + DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); + DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_cache_port,_param->_size_general_data); + DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_cache_port,_param->_size_dcache_type ); + DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_cache_port,_param->_size_general_data); + + DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_cache_port,1); + DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_cache_port,1); + DELETE1_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_cache_port,_param->_size_dcache_context_id ); + DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_cache_port,_param->_size_dcache_packet_id ); + DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_cache_port,_param->_size_general_data); + DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_cache_port,_param->_size_dcache_error); + + DELETE1_SIGNAL(out_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory,1); + DELETE1_SIGNAL(out_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory,_param->_size_general_register); + DELETE1_SIGNAL(out_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory,_param->_size_general_data ); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete out_MEMORY_OUT_VAL ; - delete in_MEMORY_OUT_ACK ; - if (_param->_have_port_context_id) - delete out_MEMORY_OUT_CONTEXT_ID; - if (_param->_have_port_front_end_id) - delete out_MEMORY_OUT_FRONT_END_ID; - if (_param->_have_port_ooo_engine_id) - delete out_MEMORY_OUT_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) - delete out_MEMORY_OUT_PACKET_ID ; -// delete out_MEMORY_OUT_OPERATION ; - delete out_MEMORY_OUT_TYPE ; - delete out_MEMORY_OUT_WRITE_RD ; - delete out_MEMORY_OUT_NUM_REG_RD; - delete out_MEMORY_OUT_DATA_RD ; - delete out_MEMORY_OUT_WRITE_RE ; - delete out_MEMORY_OUT_NUM_REG_RE; - delete out_MEMORY_OUT_DATA_RE ; - delete out_MEMORY_OUT_EXCEPTION ; - delete out_MEMORY_OUT_NO_SEQUENCE; - delete out_MEMORY_OUT_ADDRESS ; +// delete [] internal_MEMORY_IN_ACK ; +// delete [] internal_MEMORY_OUT_VAL ; +// delete [] internal_MEMORY_OUT_SELECT_QUEUE; +// delete [] internal_MEMORY_OUT_PTR ; - delete out_DCACHE_REQ_VAL ; - delete in_DCACHE_REQ_ACK ; - if (_param->_have_port_dcache_context_id) - delete out_DCACHE_REQ_CONTEXT_ID; - delete out_DCACHE_REQ_PACKET_ID ; - delete out_DCACHE_REQ_ADDRESS ; - delete out_DCACHE_REQ_TYPE ; - delete out_DCACHE_REQ_WDATA ; - - delete in_DCACHE_RSP_VAL ; - delete out_DCACHE_RSP_ACK ; - if (_param->_have_port_dcache_context_id) - delete in_DCACHE_RSP_CONTEXT_ID; - delete in_DCACHE_RSP_PACKET_ID ; - delete in_DCACHE_RSP_RDATA ; - delete in_DCACHE_RSP_ERROR ; - - delete [] out_BYPASS_MEMORY_VAL ; - if (_param->_have_port_ooo_engine_id) - delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID; - delete [] out_BYPASS_MEMORY_NUM_REG ; - delete [] out_BYPASS_MEMORY_DATA ; - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// delete [] internal_DCACHE_RSP_ACK ; +// delete [] internal_DCACHE_REQ_VAL ; +// delete [] internal_DCACHE_REQ_SELECT_QUEUE; + +// delete [] internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMealy_insert.cpp (revision 88) @@ -27,9 +27,28 @@ // ~~~~~[ Output "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // Initialisation + internal_MEMORY_IN_PORT = 0; + Tcontrol_t ack [_param->_nb_inst_memory]; + for (uint32_t i=0; i<_param->_nb_inst_memory; i++) + ack [i] = 0; + // find first valid entry // store queue is never full (pointer is manage by rename stage) - internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION)) or not _speculative_access_queue_control->full(); + for (uint32_t i=0; i<_param->_nb_inst_memory; i++) + if (PORT_READ(in_MEMORY_IN_VAL [i])) + { + internal_MEMORY_IN_ACK = is_operation_memory_store(PORT_READ(in_MEMORY_IN_OPERATION [i])) or not _speculative_access_queue_control->full(); - PORT_WRITE(out_MEMORY_IN_ACK, internal_MEMORY_IN_ACK); + if (internal_MEMORY_IN_ACK) + { + ack [i] = 1; + internal_MEMORY_IN_PORT = i; + break; // end + } + } + + for (uint32_t i=0; i<_param->_nb_inst_memory; i++) + PORT_WRITE(out_MEMORY_IN_ACK [i], ack [i]); log_printf(FUNC,Load_store_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 88) @@ -4,5 +4,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -26,5 +26,5 @@ log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); - // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Tcontext_t memory_out_context_id = 0; @@ -110,29 +110,30 @@ } // write output - PORT_WRITE(out_MEMORY_OUT_VAL , internal_MEMORY_OUT_VAL); + PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL); if (_param->_have_port_context_id) - PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID , memory_out_context_id ); + PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID [0], memory_out_context_id ); if (_param->_have_port_front_end_id) - PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID , memory_out_front_end_id ); + PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id ); if (_param->_have_port_ooo_engine_id) - PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID, memory_out_ooo_engine_id); - if (_param->_have_port_packet_id) - PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); -// PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation ); - PORT_WRITE(out_MEMORY_OUT_TYPE , TYPE_MEMORY ); - PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); - PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD , memory_out_num_reg_rd ); - PORT_WRITE(out_MEMORY_OUT_DATA_RD , memory_out_data_rd ); -// PORT_WRITE(out_MEMORY_OUT_WRITE_RE , memory_out_write_re ); -// PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , memory_out_num_reg_re ); -// PORT_WRITE(out_MEMORY_OUT_DATA_RE , memory_out_data_re ); - PORT_WRITE(out_MEMORY_OUT_WRITE_RE , 0); - PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE , 0); - PORT_WRITE(out_MEMORY_OUT_DATA_RE , 0); - PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); - PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE , 0); - PORT_WRITE(out_MEMORY_OUT_ADDRESS , 0); - // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id); + if (_param->_have_port_rob_ptr) + PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); +// PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); + PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); + PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); + PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); + PORT_WRITE(out_MEMORY_OUT_DATA_RD [0], memory_out_data_rd ); +// PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], memory_out_write_re ); +// PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], memory_out_num_reg_re ); +// PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], memory_out_data_re ); + PORT_WRITE(out_MEMORY_OUT_WRITE_RE [0], 0); + PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE [0], 0); + PORT_WRITE(out_MEMORY_OUT_DATA_RE [0], 0); + PORT_WRITE(out_MEMORY_OUT_EXCEPTION [0], memory_out_exception ); + PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE [0], 0); + PORT_WRITE(out_MEMORY_OUT_ADDRESS [0], 0); + + // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Tcontext_t dcache_req_context_id; @@ -201,11 +202,11 @@ } - PORT_WRITE(out_DCACHE_REQ_VAL , internal_DCACHE_REQ_VAL); + PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL); if (_param->_have_port_dcache_context_id) - PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id); - PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id ); - PORT_WRITE(out_DCACHE_REQ_ADDRESS , dcache_req_address ); - PORT_WRITE(out_DCACHE_REQ_TYPE , dcache_req_type ); - PORT_WRITE(out_DCACHE_REQ_WDATA , dcache_req_wdata ); + PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id); + PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id ); + PORT_WRITE(out_DCACHE_REQ_ADDRESS [0], dcache_req_address ); + PORT_WRITE(out_DCACHE_REQ_TYPE [0], dcache_req_type ); + PORT_WRITE(out_DCACHE_REQ_WDATA [0], dcache_req_wdata ); log_printf(FUNC,Load_store_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 88) @@ -255,6 +255,6 @@ // Interface "MEMORY_IN" //================================================================ - - if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and + + if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and ( internal_MEMORY_IN_ACK == 1)) { @@ -266,10 +266,10 @@ #ifdef DEBUG_TEST - if (PORT_READ(in_MEMORY_IN_TYPE) != TYPE_MEMORY) + if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); #endif - Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); - Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + - PORT_READ(in_MEMORY_IN_DATA_RA )); + Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); + Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + + PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); bool exception_alignement = (mask_memory_access(operation) & address) != 0; @@ -287,5 +287,5 @@ // Write pointer is define in rename stage : - Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); + Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); @@ -375,15 +375,15 @@ log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); - _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID); - _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID); - _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID); - _store_queue [index]._packet_id = (not _param->_have_port_packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID ); + _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); + _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); + _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); + _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); _store_queue [index]._operation = operation; - _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); + _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); _store_queue [index]._address = address; // reordering data - _store_queue [index]._wdata = duplicate(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB), memory_size(operation), 0); -// _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD ); + _store_queue [index]._wdata = duplicate(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); +// _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); } } @@ -413,16 +413,16 @@ // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; - _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID); - _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID); - _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID); - _speculative_access_queue [index]._packet_id = (not _param->_have_port_packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID); + _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); + _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); + _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); + _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); _speculative_access_queue [index]._operation = operation; - _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); - _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); + _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); + _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); _speculative_access_queue [index]._address = address; // NOTE : is operation is a load, then they are a result and must write in the register file _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); - _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD ); + _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); _speculative_access_queue [index]._exception = exception; @@ -437,5 +437,5 @@ if (( internal_MEMORY_OUT_VAL == 1) and - (PORT_READ(in_MEMORY_OUT_ACK) == 1)) + (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) { log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); @@ -495,5 +495,5 @@ if (( internal_DCACHE_REQ_VAL == 1) and - (PORT_READ(in_DCACHE_REQ_ACK) == 1)) + (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) { log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); @@ -598,5 +598,5 @@ // Interface "DCACHE_RSP" //================================================================ - if ((PORT_READ(in_DCACHE_RSP_VAL)== 1) and + if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and ( internal_DCACHE_RSP_ACK == 1)) { @@ -604,8 +604,8 @@ // don't use context_id : because there are one queue for all thread - //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID); - Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID ); - Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA ); - Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR ); + //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); + Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); + Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); + Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); @@ -662,5 +662,5 @@ -#if DEBUG>=DEBUG_TRACE +#if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) // ***** dump store queue std::cout << "Dump STORE_QUEUE :" << std::endl @@ -694,17 +694,19 @@ << _load_queue[j] << std::endl; } - #endif #ifdef STATISTICS - for (uint32_t i=0; i<_param->_size_store_queue; i++) - if (_store_queue[i]._state != STORE_QUEUE_EMPTY) - (*_stat_use_store_queue) ++; - for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) - if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) - (*_stat_use_speculative_access_queue) ++; - for (uint32_t i=0; i<_param->_size_load_queue; i++) - if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) - (*_stat_use_load_queue) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + { + for (uint32_t i=0; i<_param->_size_store_queue; i++) + if (_store_queue[i]._state != STORE_QUEUE_EMPTY) + (*_stat_use_store_queue) ++; + for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) + if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) + (*_stat_use_speculative_access_queue) ++; + for (uint32_t i=0; i<_param->_size_load_queue; i++) + if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) + (*_stat_use_load_queue) ++; + } #endif } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 88) @@ -26,4 +26,6 @@ Tspeculative_load_t speculative_load , uint32_t nb_bypass_memory , + uint32_t nb_cache_port , + uint32_t nb_inst_memory , uint32_t nb_context , uint32_t nb_front_end , @@ -33,97 +35,120 @@ uint32_t size_special_data , uint32_t nb_general_register , - uint32_t nb_special_register ): - _size_store_queue (size_store_queue ), - _size_load_queue (size_load_queue ), - _size_speculative_access_queue (size_speculative_access_queue), - _nb_port_check (nb_port_check ), - _speculative_load (speculative_load ), - _nb_bypass_memory (nb_bypass_memory ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_general_register (nb_general_register ), - _nb_special_register (nb_special_register ), - - _size_address_store_queue (log2(size_store_queue )), - _size_address_load_queue (log2(size_load_queue )), - _size_address_speculative_access_queue (log2(size_speculative_access_queue)), - - _size_context_id (log2(nb_context )), - _size_front_end_id (log2(nb_front_end )), - _size_ooo_engine_id (log2(nb_ooo_engine )), - _size_packet_id (log2(nb_packet )), - _size_general_register (log2(nb_general_register)), - _size_special_register (log2(nb_special_register)), - _size_dcache_context_id (_size_context_id + _size_front_end_id + _size_ooo_engine_id), - _size_dcache_packet_id ((log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1), - - _have_port_context_id (_size_context_id >0), - _have_port_front_end_id (_size_front_end_id >0), - _have_port_ooo_engine_id (_size_ooo_engine_id>0), - _have_port_packet_id (_size_packet_id >0), - _have_port_dcache_context_id (_size_dcache_context_id>0), - _have_port_load_queue_ptr (_size_load_queue>1), - - _mask_address_lsb (gen_mask(log2(size_general_data/8))), - _mask_address_msb (gen_mask(size_general_data) << log2(size_general_data/8)) + uint32_t nb_special_register , + bool is_toplevel) { log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); + + _size_store_queue = size_store_queue ; + _size_load_queue = size_load_queue ; + _size_speculative_access_queue = size_speculative_access_queue; + _nb_port_check = nb_port_check ; + _speculative_load = speculative_load ; + _nb_bypass_memory = nb_bypass_memory ; + _nb_cache_port = nb_cache_port ; + _nb_inst_memory = nb_inst_memory ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + + _size_speculative_access_queue_ptr = log2(size_speculative_access_queue); + + _size_dcache_context_id = log2(nb_context) + log2(nb_front_end) + log2(nb_ooo_engine); + _size_dcache_packet_id = (log2((size_store_queue>size_load_queue)?size_store_queue:size_load_queue))+1; + + _have_port_dcache_context_id = _size_dcache_context_id>0; + + _mask_address_lsb = gen_mask(log2(size_general_data/8)); + _mask_address_msb = gen_mask(size_general_data) << log2(size_general_data/8); + test(); + + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_front_end_id = log2(nb_front_end ); + _size_ooo_engine_id = log2(nb_ooo_engine ); + _size_rob_ptr = log2(nb_packet ); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + _size_store_queue_ptr = log2(size_store_queue ); + _size_load_queue_ptr = log2(size_load_queue ); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_context_id = _size_context_id >0; + _have_port_front_end_id = _size_front_end_id >0; + _have_port_ooo_engine_id = _size_ooo_engine_id >0; + _have_port_rob_ptr = _size_rob_ptr >0; + _have_port_load_queue_ptr = _size_load_queue_ptr>0; + + copy(); + } + log_printf(FUNC,Load_store_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Load_store_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_store_queue (param._size_store_queue ), +// _size_load_queue (param._size_load_queue ), +// _size_speculative_access_queue (param._size_speculative_access_queue), +// _nb_port_check (param._nb_port_check ), +// _speculative_load (param._speculative_load ), +// _nb_bypass_memory (param._nb_bypass_memory ), +// _nb_cache_port (param._nb_cache_port ), +// _nb_inst_memory (param._nb_inst_memory ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), +// _nb_general_register (param._nb_general_register ), +// _nb_special_register (param._nb_special_register ), + +// _size_address_store_queue (param._size_address_store_queue ), +// _size_address_load_queue (param._size_address_load_queue ), +// _size_address_speculative_access_queue (param._size_address_speculative_access_queue), + +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), +// _size_dcache_context_id (param._size_dcache_context_id ), +// _size_dcache_packet_id (param._size_dcache_packet_id ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_packet_id (param._have_port_packet_id ), +// _have_port_dcache_context_id(param._have_port_dcache_context_id), +// _have_port_load_queue_ptr(param._have_port_load_queue_ptr), + +// _mask_address_lsb (param._mask_address_lsb), +// _mask_address_msb (param._mask_address_msb) +// { +// log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Load_store_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Load_store_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), - _size_speculative_access_queue (param._size_speculative_access_queue), - _nb_port_check (param._nb_port_check ), - _speculative_load (param._speculative_load ), - _nb_bypass_memory (param._nb_bypass_memory ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - - _size_address_store_queue (param._size_address_store_queue ), - _size_address_load_queue (param._size_address_load_queue ), - _size_address_speculative_access_queue (param._size_address_speculative_access_queue), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - _size_dcache_context_id (param._size_dcache_context_id ), - _size_dcache_packet_id (param._size_dcache_packet_id ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ), - _have_port_dcache_context_id(param._have_port_dcache_context_id), - _have_port_load_queue_ptr(param._have_port_load_queue_ptr), - - _mask_address_lsb (param._mask_address_lsb), - _mask_address_msb (param._mask_address_msb) +#define FUNCTION "Load_store_unit::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); - test(); log_printf(FUNC,Load_store_unit,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Load_store_unit::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Load_store_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters_msg_error.cpp (revision 88) @@ -32,5 +32,5 @@ { if (not (_nb_bypass_memory == 0)) - test.error("Bypass memory is not supported. Please wait a next revision."); + test.error(_("Bypass memory is not supported. Please wait a next revision.\n")); break; @@ -42,7 +42,7 @@ { if (not (_nb_bypass_memory == 0)) - test.error("In the load scheme '"+toString(_speculative_load)+"', they have none bypass."); + test.error(toString(_("In the load scheme '%s', they have none bypass.\n"),toString(_speculative_load).c_str())); - test.error("Speculative load scheme '"+toString(_speculative_load)+"' is not supported. Please wait a next revision."); + test.error(toString(_("Speculative load scheme '%s' is not supported. Please wait a next revision.\n"),toString(_speculative_load).c_str())); break; } @@ -50,8 +50,14 @@ if (not (_size_store_queue >= 2)) - test.error("Store queue must have at less two slot."); + test.error(_("Store queue must have at less two slot.\n")); if (not (_nb_bypass_memory <= _size_load_queue)) - test.error("Bypass number must be less than load_queue's size."); + test.error(_("Bypass number must be less than load_queue's size.\n")); + + if (_nb_cache_port > 1) + test.warning(_("nb_cache_port > 1 is unsupported (Coming Soon).\n")); + + if (_nb_inst_memory > 1) + test.warning(_("nb_inst_memory > 1 is unsupported (Coming Soon).\n")); log_printf(FUNC,Load_store_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Read_queue_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/include/test.h (revision 88) @@ -16,4 +16,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h" +#include "Common/include/Time.h" using namespace std; @@ -30,33 +31,2 @@ morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Parameters * param); -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/main.cpp (revision 88) @@ -77,4 +77,5 @@ ,size_store_queue ,size_load_queue + ,true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Read_queue * _Read_queue = new Read_queue (name.c_str(), #ifdef STATISTICS @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -200,5 +210,5 @@ if(_param->_have_port_ooo_engine_id) (*(_Read_queue-> in_READ_QUEUE_IN_OOO_ENGINE_ID )) (*(READ_QUEUE_IN_OOO_ENGINE_ID )); - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) (*(_Read_queue-> in_READ_QUEUE_IN_ROB_ID )) (*(READ_QUEUE_IN_ROB_ID )); (*(_Read_queue-> in_READ_QUEUE_IN_OPERATION )) (*(READ_QUEUE_IN_OPERATION )); @@ -228,5 +238,5 @@ if(_param->_have_port_ooo_engine_id) (*(_Read_queue->out_READ_QUEUE_OUT_OOO_ENGINE_ID )) (*(READ_QUEUE_OUT_OOO_ENGINE_ID )); - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) (*(_Read_queue->out_READ_QUEUE_OUT_ROB_ID )) (*(READ_QUEUE_OUT_ROB_ID )); (*(_Read_queue->out_READ_QUEUE_OUT_OPERATION )) (*(READ_QUEUE_OUT_OPERATION )); @@ -388,5 +398,5 @@ if(_param->_have_port_front_end_id ) READ_QUEUE_IN_FRONT_END_ID ->write((3*_ooo_engine_id [request_in])%_param->_nb_front_end); - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) READ_QUEUE_IN_ROB_ID ->write(request_in); READ_QUEUE_IN_OPERATION ->write(0); @@ -504,5 +514,5 @@ { Tpacket_t rob_id; - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) rob_id = READ_QUEUE_OUT_ROB_ID->read(); else @@ -551,4 +561,5 @@ TEST_OK ("End of Simulation"); delete _time; + cout << "<" << name << "> ............ Stop Simulation" << endl; @@ -564,5 +575,5 @@ if(_param->_have_port_ooo_engine_id ) delete READ_QUEUE_IN_OOO_ENGINE_ID; - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) delete READ_QUEUE_IN_ROB_ID ; delete READ_QUEUE_IN_OPERATION ; @@ -592,5 +603,5 @@ if(_param->_have_port_ooo_engine_id ) delete READ_QUEUE_OUT_OOO_ENGINE_ID; - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) delete READ_QUEUE_OUT_ROB_ID ; delete READ_QUEUE_OUT_OPERATION ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Parameters.h (revision 88) @@ -28,34 +28,34 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_spr_write ; - public : const uint32_t _size_store_queue ; - public : const uint32_t _size_load_queue ; + public : uint32_t _size_queue ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; +//public : uint32_t _size_store_queue ; +//public : uint32_t _size_load_queue ; - public : const uint32_t _nb_gpr_read ; - public : const uint32_t _nb_spr_read ; - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_rob_id ; - public : const uint32_t _size_general_register; - public : const uint32_t _size_special_register; + public : uint32_t _nb_gpr_read ; + public : uint32_t _nb_spr_read ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_rob_id ; +//public : uint32_t _size_general_register; +//public : uint32_t _size_special_register; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id; - public : const bool _have_port_rob_id ; - public : const bool _have_port_load_queue_ptr; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id; +//public : bool _have_port_rob_id ; +//public : bool _have_port_load_queue_ptr; - public : const uint32_t _size_internal_queue; + public : uint32_t _size_internal_queue; //-----[ methods ]----------------------------------------------------------- @@ -72,8 +72,11 @@ uint32_t nb_spr_write , uint32_t size_store_queue , - uint32_t size_load_queue ); + uint32_t size_load_queue , + bool is_toplevel=false ); - public : Parameters (Parameters & param) ; - public : ~Parameters () ; +//public : Parameters (Parameters & param) ; + public : ~Parameters (void) ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Read_queue.h (revision 88) @@ -14,5 +14,5 @@ #include -#include +#include #include "Common/include/ToString.h" #include "Common/include/Debug.h" @@ -154,5 +154,5 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ protected : Tread_queue_head_entry_t * _queue_head; - protected : std::queue * _queue; + protected : std::list * _queue; // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters.cpp (revision 88) @@ -30,104 +30,118 @@ uint32_t nb_spr_write , uint32_t size_store_queue , - uint32_t size_load_queue ): - _size_queue (size_queue ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_general_register (nb_general_register ), - _nb_special_register (nb_special_register ), - _nb_gpr_write (nb_gpr_write ), - _nb_spr_write (nb_spr_write ), - _size_store_queue (size_store_queue ), - _size_load_queue (size_load_queue ), - - _nb_gpr_read (2 ), - _nb_spr_read (1 ), - _size_context_id (static_cast(log2(_nb_context ))), - _size_front_end_id (static_cast(log2(_nb_front_end ))), - _size_ooo_engine_id (static_cast(log2(_nb_ooo_engine ))), - _size_rob_id (static_cast(log2(_nb_packet ))), - _size_general_register (static_cast(log2(_nb_general_register))), - _size_special_register (static_cast(log2(_nb_special_register))), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_rob_id (_size_rob_id > 0), - _have_port_load_queue_ptr(_size_load_queue > 1), - - _size_internal_queue ( _size_context_id //_context_id - + _size_front_end_id //_front_end_id - + _size_ooo_engine_id //_ooo_engine_id - + _size_rob_id //_rob_id - + _size_operation //_operation - + _size_type //_type - + log2(_size_store_queue)//_store_queue_ptr_write - + log2(_size_load_queue )//_load_queue_ptr_write - + 1 //_has_immediat - + _size_general_data //_immediat - + 1 //_read_ra - + _size_general_register //_num_reg_ra - + 1 //_read_rb - + _size_general_register //_num_reg_rb - + 1 //_read_rc - + _size_special_register //_num_reg_rc - + 1 //_write_rd - + _size_general_register //_num_reg_rd - + 1 //_write_re - + _size_special_register //_num_reg_re - ) - - + uint32_t size_load_queue , + bool is_toplevel) { log_printf(FUNC,Read_queue,"Parameters","Begin"); + + _size_queue = size_queue ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_gpr_write = nb_gpr_write ; + _nb_spr_write = nb_spr_write ; + + _nb_gpr_read = 2 ; + _nb_spr_read = 1 ; + + _size_internal_queue = ( log2(nb_context ) //_context_id + + log2(nb_front_end ) //_front_end_id + + log2(nb_ooo_engine ) //_ooo_engine_id + + log2(nb_packet ) //_rob_id + + _size_operation //_operation + + _size_type //_type + + log2(size_store_queue ) //_store_queue_ptr_write + + log2(size_load_queue ) //_load_queue_ptr_write + + 1 //_has_immediat + + size_general_data //_immediat + + 1 //_read_ra + + log2(nb_general_register) //_num_reg_ra + + 1 //_read_rb + + log2(nb_general_register) //_num_reg_rb + + 1 //_read_rc + + log2(nb_special_register) //_num_reg_rc + + 1 //_write_rd + + log2(nb_general_register) //_num_reg_rd + + 1 //_write_re + + log2(nb_special_register) //_num_reg_re + ); + test(); + + if (is_toplevel) + { + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_store_queue_ptr = log2(size_store_queue); + _size_load_queue_ptr = log2(size_load_queue ); + _size_context_id = log2(_nb_context ); + _size_front_end_id = log2(_nb_front_end ); + _size_ooo_engine_id = log2(_nb_ooo_engine ); + _size_rob_ptr = log2(_nb_packet ); + _size_general_register = log2(_nb_general_register); + _size_special_register = log2(_nb_special_register); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr= _size_load_queue_ptr> 0; + + copy(); + } + log_printf(FUNC,Read_queue,"Parameters","End"); }; - Parameters::Parameters (Parameters & param): - _size_queue (param._size_queue ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), +// Parameters::Parameters (Parameters & param): +// _size_queue (param._size_queue ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), +// _nb_general_register (param._nb_general_register ), +// _nb_special_register (param._nb_special_register ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), +// _size_store_queue (param._size_store_queue ), +// _size_load_queue (param._size_load_queue ), - _nb_gpr_read (param._nb_gpr_read ), - _nb_spr_read (param._nb_spr_read ), - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_rob_id (param._size_rob_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), +// _nb_gpr_read (param._nb_gpr_read ), +// _nb_spr_read (param._nb_spr_read ), +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_rob_id (param._size_rob_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_rob_id (param._have_port_rob_id ), - _have_port_load_queue_ptr(param._have_port_load_queue_ptr), +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_rob_id (param._have_port_rob_id ), +// _have_port_load_queue_ptr(param._have_port_load_queue_ptr), - _size_internal_queue (param._size_internal_queue ) - { - log_printf(FUNC,Read_queue,"Parameters (copy)","Begin"); - test(); - log_printf(FUNC,Read_queue,"Parameters (copy)","End"); - }; +// _size_internal_queue (param._size_internal_queue ) +// { +// log_printf(FUNC,Read_queue,"Parameters (copy)","Begin"); +// test(); +// log_printf(FUNC,Read_queue,"Parameters (copy)","End"); +// }; - Parameters::~Parameters () + Parameters::~Parameters (void) { log_printf(FUNC,Read_queue,"~Parameters","Begin"); log_printf(FUNC,Read_queue,"~Parameters","End"); + }; + + void Parameters::copy (void) + { + log_printf(FUNC,Read_queue,"copy","Begin"); + log_printf(FUNC,Read_queue,"copy","End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Parameters_print.cpp (revision 88) @@ -31,12 +31,12 @@ xml.singleton_begin("nb_ooo_engine "); xml.attribut("value",toString(_nb_ooo_engine )); xml.singleton_end(); xml.singleton_begin("nb_packet "); xml.attribut("value",toString(_nb_packet )); xml.singleton_end(); - xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); - xml.singleton_begin("size_special_data "); xml.attribut("value",toString(_size_special_data )); xml.singleton_end(); +// xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); +// xml.singleton_begin("size_special_data "); xml.attribut("value",toString(_size_special_data )); xml.singleton_end(); xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end(); xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end(); xml.singleton_begin("nb_gpr_write "); xml.attribut("value",toString(_nb_gpr_write )); xml.singleton_end(); xml.singleton_begin("nb_spr_write "); xml.attribut("value",toString(_nb_spr_write )); xml.singleton_end(); - xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); - xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); +// xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); +// xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue.cpp (revision 88) @@ -36,4 +36,10 @@ log_printf(FUNC,Read_queue,"Read_queue","Begin"); +#if DEBUG_Read_queue == true + log_printf(INFO,Read_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + #ifdef SYSTEMC log_printf(INFO,Read_queue,"Read_queue","Allocation"); @@ -43,17 +49,25 @@ #ifdef STATISTICS - log_printf(INFO,Read_queue,FUNCTION,"Allocation of statistics"); - - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Read_queue,FUNCTION,"Allocation of statistics"); + + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,Read_queue,"Read_queue","Generate the vhdl"); - - vhdl(); -#endif - -#ifdef SYSTEMC + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Read_queue,"Read_queue","Generate the vhdl"); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { log_printf(INFO,Read_queue,"Read_queue","Method - transition"); @@ -206,5 +220,5 @@ } #endif - + } #endif log_printf(FUNC,Read_queue,"Read_queue","End"); @@ -216,7 +230,10 @@ #ifdef STATISTICS - log_printf(INFO,Read_queue,"~Read_queue","Generate Statistics file"); - - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Read_queue,"~Read_queue","Generate Statistics file"); + + delete _stat; + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_allocation.cpp (revision 88) @@ -3,5 +3,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -34,5 +34,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { @@ -48,5 +48,5 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } - // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface_fifo * interface = _interfaces->set_interface("read_queue_in" @@ -66,11 +66,11 @@ if(_param->_have_port_ooo_engine_id) in_READ_QUEUE_IN_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id",_param->_size_ooo_engine_id ); - if(_param->_have_port_rob_id ) - in_READ_QUEUE_IN_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_id ); + if(_param->_have_port_rob_ptr ) + in_READ_QUEUE_IN_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_ptr ); in_READ_QUEUE_IN_OPERATION = interface->set_signal_in ("operation" ,_param->_size_operation ); in_READ_QUEUE_IN_TYPE = interface->set_signal_in ("type" ,_param->_size_type ); - in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write", log2(_param->_size_store_queue)); + in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write", _param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" , log2(_param->_size_load_queue )); + in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" , _param->_size_load_queue_ptr); in_READ_QUEUE_IN_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat",1 ); in_READ_QUEUE_IN_IMMEDIAT = interface->set_signal_in ("immediat" ,_param->_size_general_data ); @@ -87,5 +87,5 @@ } - // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface_fifo * interface = _interfaces->set_interface("read_queue_out" @@ -106,11 +106,11 @@ if(_param->_have_port_ooo_engine_id) out_READ_QUEUE_OUT_OOO_ENGINE_ID = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id ); - if(_param->_have_port_rob_id ) - out_READ_QUEUE_OUT_ROB_ID = interface->set_signal_out ("rob_id" ,_param->_size_rob_id ); + if(_param->_have_port_rob_ptr ) + out_READ_QUEUE_OUT_ROB_ID = interface->set_signal_out ("rob_id" ,_param->_size_rob_ptr ); out_READ_QUEUE_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); out_READ_QUEUE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); - out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE = interface->set_signal_out ("store_queue_ptr_write", log2(_param->_size_store_queue)); + out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE = interface->set_signal_out ("store_queue_ptr_write", _param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_out ("load_queue_ptr_write" , log2(_param->_size_load_queue )); + out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_out ("load_queue_ptr_write" , _param->_size_load_queue_ptr); out_READ_QUEUE_OUT_HAS_IMMEDIAT = interface->set_signal_out ("has_immediat",1 ); out_READ_QUEUE_OUT_IMMEDIAT = interface->set_signal_out ("immediat" ,_param->_size_general_data ); @@ -133,5 +133,5 @@ } - // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ out_GPR_READ_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; @@ -162,5 +162,5 @@ } - // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ out_SPR_READ_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; @@ -191,5 +191,5 @@ } - // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; @@ -216,5 +216,5 @@ } - // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; @@ -241,10 +241,11 @@ } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _queue = new std::queue; + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _queue = new std::list; _queue_head = new Tread_queue_head_entry_t; #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_deallocation.cpp (revision 88) @@ -3,5 +3,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -23,9 +23,11 @@ log_printf(FUNC,Read_queue,"deallocation","Begin"); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete in_CLOCK ; delete in_NRESET; - // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete in_READ_QUEUE_IN_VAL ; delete out_READ_QUEUE_IN_ACK ; @@ -37,5 +39,5 @@ if(_param->_have_port_ooo_engine_id) delete in_READ_QUEUE_IN_OOO_ENGINE_ID ; - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) delete in_READ_QUEUE_IN_ROB_ID ; delete in_READ_QUEUE_IN_OPERATION ; @@ -57,5 +59,5 @@ delete in_READ_QUEUE_IN_NUM_REG_RE ; - // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete out_READ_QUEUE_OUT_VAL ; delete in_READ_QUEUE_OUT_ACK ; @@ -67,5 +69,5 @@ if(_param->_have_port_ooo_engine_id) delete out_READ_QUEUE_OUT_OOO_ENGINE_ID ; - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) delete out_READ_QUEUE_OUT_ROB_ID ; delete out_READ_QUEUE_OUT_OPERATION ; @@ -93,5 +95,5 @@ delete out_READ_QUEUE_OUT_NUM_REG_RE ; - // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] out_GPR_READ_VAL ; @@ -103,5 +105,5 @@ delete [] in_GPR_READ_DATA_VAL ; - // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] out_SPR_READ_VAL ; @@ -113,5 +115,5 @@ delete [] in_SPR_READ_DATA_VAL ; - // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] in_GPR_WRITE_VAL ; @@ -121,5 +123,5 @@ delete [] in_GPR_WRITE_DATA ; - // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] in_SPR_WRITE_VAL ; @@ -128,11 +130,12 @@ delete [] in_SPR_WRITE_NUM_REG ; delete [] in_SPR_WRITE_DATA ; + } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ while (_queue->empty() == false) { delete _queue->front(); - _queue->pop(); + _queue->pop_front(); } delete _queue; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_end_cycle.cpp (revision 88) @@ -24,5 +24,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -30,5 +31,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_gpr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_gpr.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_gpr.cpp (revision 88) @@ -22,5 +22,6 @@ void Read_queue::genMealy_read_queue_out_gpr (void) { - log_printf(FUNC,Read_queue,FUNCTION,"Begin"); + log_begin(Read_queue,FUNCTION); + log_function(Read_queue,FUNCTION,_name.c_str()); internal_READ_QUEUE_OUT_DATA_RA_VAL = (// Previous value @@ -32,9 +33,9 @@ ); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RA_VAL : %d",internal_READ_QUEUE_OUT_DATA_RA_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_ra_val : %d",_queue_head->_data_ra_val); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_ra_val : %d",_queue_head->_read_ra_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [0] : %d",PORT_READ(in_GPR_READ_ACK [0])); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_DATA_VAL [0] : %d",PORT_READ(in_GPR_READ_DATA_VAL [0])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RA_VAL : %d",internal_READ_QUEUE_OUT_DATA_RA_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_ra_val : %d",_queue_head->_data_ra_val); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_ra_val : %d",_queue_head->_read_ra_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [0] : %d",PORT_READ(in_GPR_READ_ACK [0])); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_DATA_VAL [0] : %d",PORT_READ(in_GPR_READ_DATA_VAL [0])); internal_READ_QUEUE_OUT_DATA_RB_VAL = (_queue_head->_data_rb_val or @@ -44,9 +45,9 @@ ); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RB_VAL : %d",internal_READ_QUEUE_OUT_DATA_RB_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_rb_val : %d",_queue_head->_data_rb_val); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rb_val : %d",_queue_head->_read_rb_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [1] : %d",PORT_READ(in_GPR_READ_ACK [1])); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_DATA_VAL [1] : %d",PORT_READ(in_GPR_READ_DATA_VAL [1])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RB_VAL : %d",internal_READ_QUEUE_OUT_DATA_RB_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_rb_val : %d",_queue_head->_data_rb_val); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rb_val : %d",_queue_head->_read_rb_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [1] : %d",PORT_READ(in_GPR_READ_ACK [1])); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_DATA_VAL [1] : %d",PORT_READ(in_GPR_READ_DATA_VAL [1])); @@ -80,5 +81,5 @@ if (_queue_head->_num_reg_ra == gpr_write_num_reg) { - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RA_VAL - bypass hit (%d)",i); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RA_VAL - bypass hit (%d)",i); internal_READ_QUEUE_OUT_DATA_RA_VAL = 1; @@ -90,5 +91,5 @@ if (_queue_head->_num_reg_rb == gpr_write_num_reg) { - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RB_VAL - bypass hit (%d)",i); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RB_VAL - bypass hit (%d)",i); internal_READ_QUEUE_OUT_DATA_RB_VAL = 1; #ifdef SYSTEMC_VHDL_COMPATIBILITY @@ -106,5 +107,5 @@ PORT_WRITE(out_READ_QUEUE_OUT_DATA_RB ,internal_READ_QUEUE_OUT_DATA_RB ); - log_printf(FUNC,Read_queue,FUNCTION,"End"); + log_end(Read_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_spr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_spr.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_spr.cpp (revision 88) @@ -22,5 +22,6 @@ void Read_queue::genMealy_read_queue_out_spr (void) { - log_printf(FUNC,Read_queue,FUNCTION,"Begin"); + log_begin(Read_queue,FUNCTION); + log_function(Read_queue,FUNCTION,_name.c_str()); internal_READ_QUEUE_OUT_DATA_RC_VAL = (// Previous value @@ -32,9 +33,9 @@ ); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RC_VAL : %d",internal_READ_QUEUE_OUT_DATA_RC_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_rc_val : %d",_queue_head->_data_rc_val); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rc_val : %d",_queue_head->_read_rc_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_ACK [0] : %d",PORT_READ(in_SPR_READ_ACK [0])); - log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_DATA_VAL [0] : %d",PORT_READ(in_SPR_READ_DATA_VAL [0])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RC_VAL : %d",internal_READ_QUEUE_OUT_DATA_RC_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_data_rc_val : %d",_queue_head->_data_rc_val); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rc_val : %d",_queue_head->_read_rc_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_ACK [0] : %d",PORT_READ(in_SPR_READ_ACK [0])); + log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_DATA_VAL [0] : %d",PORT_READ(in_SPR_READ_DATA_VAL [0])); internal_READ_QUEUE_OUT_DATA_RC = (// Test if have an previous access @@ -60,5 +61,5 @@ if (_queue_head->_num_reg_rc == PORT_READ(in_SPR_WRITE_NUM_REG [i])) { - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RC_VAL - bypass hit (%d)",i); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_DATA_RC_VAL - bypass hit (%d)",i); internal_READ_QUEUE_OUT_DATA_RC_VAL = 1; #ifdef SYSTEMC_VHDL_COMPATIBILITY @@ -74,5 +75,5 @@ PORT_WRITE(out_READ_QUEUE_OUT_DATA_RC ,internal_READ_QUEUE_OUT_DATA_RC ); - log_printf(FUNC,Read_queue,FUNCTION,"End"); + log_end(Read_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_val.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_val.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMealy_read_queue_out_val.cpp (revision 88) @@ -22,5 +22,6 @@ void Read_queue::genMealy_read_queue_out_val (void) { - log_printf(FUNC,Read_queue,FUNCTION,"Begin"); + log_begin(Read_queue,FUNCTION); + log_function(Read_queue,FUNCTION,_name.c_str()); internal_READ_QUEUE_OUT_READ_RA_VAL = (// Previous value @@ -99,17 +100,17 @@ PORT_WRITE(out_READ_QUEUE_OUT_VAL, internal_READ_QUEUE_OUT_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_VAL : %d",internal_READ_QUEUE_OUT_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue->empty() : %d",_queue->empty()); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RA_VAL : %d",internal_READ_QUEUE_OUT_READ_RA_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_ra_val : %d",_queue_head->_read_ra_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [0] : %d",PORT_READ(in_GPR_READ_ACK [0])); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RB_VAL : %d",internal_READ_QUEUE_OUT_READ_RB_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rb_val : %d",_queue_head->_read_rb_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [1] : %d",PORT_READ(in_GPR_READ_ACK [1])); - log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RC_VAL : %d",internal_READ_QUEUE_OUT_READ_RC_VAL); - log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rc_val : %d",_queue_head->_read_rc_val); - log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_ACK [0] : %d",PORT_READ(in_SPR_READ_ACK [0])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_VAL : %d",internal_READ_QUEUE_OUT_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue->empty() : %d",_queue->empty()); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RA_VAL : %d",internal_READ_QUEUE_OUT_READ_RA_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_ra_val : %d",_queue_head->_read_ra_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [0] : %d",PORT_READ(in_GPR_READ_ACK [0])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RB_VAL : %d",internal_READ_QUEUE_OUT_READ_RB_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rb_val : %d",_queue_head->_read_rb_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_GPR_READ_ACK [1] : %d",PORT_READ(in_GPR_READ_ACK [1])); + log_printf(TRACE,Read_queue,FUNCTION," * internal_READ_QUEUE_OUT_READ_RC_VAL : %d",internal_READ_QUEUE_OUT_READ_RC_VAL); + log_printf(TRACE,Read_queue,FUNCTION," * _queue_head->_read_rc_val : %d",_queue_head->_read_rc_val); + log_printf(TRACE,Read_queue,FUNCTION," * in_SPR_READ_ACK [0] : %d",PORT_READ(in_SPR_READ_ACK [0])); - log_printf(FUNC,Read_queue,FUNCTION,"End"); + log_end(Read_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_genMoore.cpp (revision 88) @@ -22,5 +22,6 @@ void Read_queue::genMoore (void) { - log_printf(FUNC,Read_queue,FUNCTION,"Begin"); + log_begin(Read_queue,FUNCTION); + log_function(Read_queue,FUNCTION,_name.c_str()); bool not_full = not (_queue->size() == _param->_size_queue); @@ -39,5 +40,5 @@ if(_param->_have_port_ooo_engine_id) PORT_WRITE (out_READ_QUEUE_OUT_OOO_ENGINE_ID, _queue_head->_ooo_engine_id); - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) PORT_WRITE (out_READ_QUEUE_OUT_ROB_ID , _queue_head->_rob_id ); PORT_WRITE (out_READ_QUEUE_OUT_OPERATION , _queue_head->_operation ); @@ -79,8 +80,8 @@ PORT_WRITE (out_SPR_READ_VAL [0], not_empty and _queue_head->_read_rc_val); if(_param->_have_port_ooo_engine_id) - PORT_WRITE (out_SPR_READ_OOO_ENGINE_ID [0], _queue_head->_ooo_engine_id); + PORT_WRITE (out_SPR_READ_OOO_ENGINE_ID [0], _queue_head->_ooo_engine_id); PORT_WRITE (out_SPR_READ_NUM_REG [0], _queue_head->_num_reg_rc); - log_printf(FUNC,Read_queue,FUNCTION,"End"); + log_end(Read_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 88) @@ -24,5 +24,6 @@ void Read_queue::transition (void) { - log_printf(FUNC,Read_queue,FUNCTION,"Begin"); + log_begin(Read_queue,FUNCTION); + log_function(Read_queue,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -33,6 +34,8 @@ // > 2) flush all slot in one cycle - while (_queue->empty() == false) - _queue->pop(); + _queue->clear(); + + // Init, else error in registerfile + _queue_head->_ooo_engine_id = 0; } else @@ -44,5 +47,5 @@ // cout << (*_queue_head) << endl; - log_printf(TRACE,Read_queue,FUNCTION,"Read_queue size (begin) : %d",_queue->size()); + log_printf(TRACE,Read_queue,FUNCTION," * Read_queue size (begin) : %d",(int)_queue->size()); // Write to read_queue @@ -51,5 +54,5 @@ bool need_new_head = false; - log_printf(TRACE,Read_queue,FUNCTION," * test transaction READ_QUEUE_IN : %d,%d",PORT_READ(in_READ_QUEUE_IN_VAL), not_full); + log_printf(TRACE,Read_queue,FUNCTION," * test transaction READ_QUEUE_IN : %d,%d",PORT_READ(in_READ_QUEUE_IN_VAL), not_full); if ((PORT_READ(in_READ_QUEUE_IN_VAL) == 1) and not_full) { @@ -62,5 +65,5 @@ if(_param->_have_port_ooo_engine_id) entry->_ooo_engine_id= PORT_READ(in_READ_QUEUE_IN_OOO_ENGINE_ID); - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr ) entry->_rob_id = PORT_READ(in_READ_QUEUE_IN_ROB_ID ); entry->_operation = PORT_READ(in_READ_QUEUE_IN_OPERATION ); @@ -82,12 +85,11 @@ entry->_num_reg_re = PORT_READ(in_READ_QUEUE_IN_NUM_REG_RE ); - log_printf(TRACE,Read_queue,FUNCTION," * push (id : %d-%d)",entry->_context_id, entry->_rob_id); - _queue->push(entry); - + log_printf(TRACE,Read_queue,FUNCTION," * push (id : %d-%d)",entry->_context_id, entry->_rob_id); + _queue->push_back(entry); // read next new head if (empty) { - log_printf(TRACE,Read_queue,FUNCTION," * queue was empty"); + log_printf(TRACE,Read_queue,FUNCTION," * queue was empty"); need_new_head = true; } @@ -95,16 +97,16 @@ // Read from read_queue - log_printf(TRACE,Read_queue,FUNCTION," * test transaction READ_QUEUE_OUT : %d,%d",internal_READ_QUEUE_OUT_VAL, PORT_READ(in_READ_QUEUE_OUT_ACK)); + log_printf(TRACE,Read_queue,FUNCTION," * test transaction READ_QUEUE_OUT : %d,%d",internal_READ_QUEUE_OUT_VAL, PORT_READ(in_READ_QUEUE_OUT_ACK)); if (( internal_READ_QUEUE_OUT_VAL == 1) and (PORT_READ(in_READ_QUEUE_OUT_ACK) == 1)) { // Pop the entry - log_printf(TRACE,Read_queue,FUNCTION," * pop (id : %d-%d)",_queue->front()->_context_id, _queue->front()->_rob_id); - _queue->pop(); + log_printf(TRACE,Read_queue,FUNCTION," * pop (id : %d-%d)",_queue->front()->_context_id, _queue->front()->_rob_id); + _queue->pop_front(); // read next new head if (_queue->empty() == false) { - log_printf(TRACE,Read_queue,FUNCTION," * queue was not empty"); + log_printf(TRACE,Read_queue,FUNCTION," * queue was not empty"); need_new_head = true; } @@ -128,5 +130,5 @@ if (need_new_head == true) { - log_printf(TRACE,Read_queue,FUNCTION," * new head"); + log_printf(TRACE,Read_queue,FUNCTION," * new head"); (*_queue_head) = (*_queue->front()); } @@ -138,12 +140,119 @@ // cout << (*_queue_head) << endl; - log_printf(TRACE,Read_queue,FUNCTION,"Read_queue size (end ) : %d",_queue->size()); +#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Read_queue == true) + log_printf(TRACE,Read_queue,FUNCTION," * Dump Read_queue"); + log_printf(TRACE,Read_queue,FUNCTION," * size : %d",(int)_queue->size()); + + if (_queue->size()>0) + { +// protected : Tread_queue_head_entry_t * _queue_head; +// protected : std::queue * _queue; + + log_printf(TRACE,Read_queue,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", + 0, + + _queue_head->_context_id , + _queue_head->_front_end_id , + _queue_head->_ooo_engine_id , + _queue_head->_rob_id , + + _queue_head->_type , + _queue_head->_operation , + + _queue_head->_store_queue_ptr_write, + _queue_head->_load_queue_ptr_write , + + _queue_head->_has_immediat , + _queue_head->_immediat , + + _queue_head->_read_ra , + _queue_head->_read_ra_val , + _queue_head->_num_reg_ra , + _queue_head->_data_ra_val , + _queue_head->_data_ra , + + _queue_head->_read_rb , + _queue_head->_read_rb_val , + _queue_head->_num_reg_rb , + _queue_head->_data_rb_val , + _queue_head->_data_rb , + + _queue_head->_read_rc , + _queue_head->_read_rc_val , + _queue_head->_num_reg_rc , + _queue_head->_data_rc_val , + _queue_head->_data_rc , + + _queue_head->_write_rd , + _queue_head->_num_reg_rd , + + _queue_head->_write_re , + _queue_head->_num_reg_re , + + toString_type(_queue_head->_type).c_str()); + + + std::list::iterator it=_queue->begin(); + ++it; // first is already printed + uint32_t i=1; + + for (;it!=_queue->end(); ++it) + { + log_printf(TRACE,Read_queue,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.4d , %.1d %.4d , %.1d %.4d , %.1d %.4d, %.1d %.4d (%s)", + i, + + (*it)->_context_id , + (*it)->_front_end_id , + (*it)->_ooo_engine_id , + (*it)->_rob_id , + + (*it)->_type , + (*it)->_operation , + + (*it)->_store_queue_ptr_write, + (*it)->_load_queue_ptr_write , + + (*it)->_has_immediat , + (*it)->_immediat , + + (*it)->_read_ra , +// (*it)->_read_ra_val , + (*it)->_num_reg_ra , +// (*it)->_data_ra_val , +// (*it)->_data_ra , + + (*it)->_read_rb , +// (*it)->_read_rb_val , + (*it)->_num_reg_rb , +// (*it)->_data_rb_val , +// (*it)->_data_rb , + + (*it)->_read_rc , +// (*it)->_read_rc_val , + (*it)->_num_reg_rc , +// (*it)->_data_rc_val , +// (*it)->_data_rc , + + (*it)->_write_rd , + (*it)->_num_reg_rd , + + (*it)->_write_re , + (*it)->_num_reg_re , + + toString_type((*it)->_type).c_str()); + + ++i; + } + } +#endif + + } #if defined(STATISTICS) or defined(VHDL_TESTBENCH) - end_cycle (); + end_cycle (); #endif - log_printf(FUNC,Read_queue,FUNCTION,"End"); + log_end(Read_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Reservation_station_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h (revision 88) @@ -15,4 +15,5 @@ #include +#include "Common/include/Time.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" @@ -31,33 +32,2 @@ morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters * param); -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/main.cpp (revision 88) @@ -86,4 +86,5 @@ ,size_store_queue ,size_load_queue + ,true //is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 88) @@ -22,4 +22,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Reservation_station * _Reservation_station = new Reservation_station (name.c_str(), @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -185,5 +195,5 @@ if (_param->_have_port_ooo_engine_id) (*(_Reservation_station-> in_INSERT_OOO_ENGINE_ID )) (*( in_INSERT_OOO_ENGINE_ID )); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) (*(_Reservation_station-> in_INSERT_ROB_ID )) (*( in_INSERT_ROB_ID )); (*(_Reservation_station-> in_INSERT_OPERATION )) (*( in_INSERT_OPERATION )); @@ -221,5 +231,5 @@ if (_param->_have_port_ooo_engine_id) (*(_Reservation_station->out_RETIRE_OOO_ENGINE_ID [i])) (*(out_RETIRE_OOO_ENGINE_ID [i])); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) (*(_Reservation_station->out_RETIRE_ROB_ID [i])) (*(out_RETIRE_ROB_ID [i])); (*(_Reservation_station->out_RETIRE_OPERATION [i])) (*(out_RETIRE_OPERATION [i])); @@ -417,5 +427,5 @@ if (_param->_have_port_ooo_engine_id) in_INSERT_OOO_ENGINE_ID ->write(insert_ooo_engine_id); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) in_INSERT_ROB_ID ->write(request_in); in_INSERT_OPERATION ->write(0); @@ -610,5 +620,5 @@ { Tpacket_t rob_id; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) rob_id = out_RETIRE_ROB_ID [i]->read(); else @@ -667,5 +677,5 @@ if (_param->_have_port_ooo_engine_id) delete in_INSERT_OOO_ENGINE_ID ; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) delete in_INSERT_ROB_ID ; delete in_INSERT_OPERATION ; @@ -701,5 +711,5 @@ if (_param->_have_port_ooo_engine_id) delete [] out_RETIRE_OOO_ENGINE_ID ; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) delete [] out_RETIRE_ROB_ID ; delete [] out_RETIRE_OPERATION ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h (revision 88) @@ -26,41 +26,40 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue ; - public : const uint32_t _nb_inst_retire ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_spr_write ; - public : const uint32_t _nb_bypass_write ;//if nb_bypass=0, then bypass is desactivated - public : const uint32_t _nb_bypass_memory ;//if nb_bypass=0, then bypass is desactivated - public : const uint32_t _size_store_queue ; - public : const uint32_t _size_load_queue ; + public : uint32_t _size_queue ; + public : uint32_t _nb_inst_retire ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; + public : uint32_t _nb_bypass_write ;//if nb_bypass=0, then bypass is desactivated + public : uint32_t _nb_bypass_memory ;//if nb_bypass=0, then bypass is desactivated +//public : uint32_t _size_store_queue ; +//public : uint32_t _size_load_queue ; + /* + public : bool _have_immediat ; + public : bool _have_gpr_ra ; + public : bool _have_gpr_rb ; + public : bool _have_spr_rc ; + public : bool _have_gpr_rd ; + public : bool _have_spr_re ; + */ +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_rob_ptr ; +//public : uint32_t _size_general_register; +//public : uint32_t _size_special_register; - /* - public : const bool _have_immediat ; - public : const bool _have_gpr_ra ; - public : const bool _have_gpr_rb ; - public : const bool _have_spr_rc ; - public : const bool _have_gpr_rd ; - public : const bool _have_spr_re ; - */ - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_rob_id ; - public : const uint32_t _size_general_register; - public : const uint32_t _size_special_register; - - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id; - public : const bool _have_port_rob_id ; - public : const bool _have_port_load_queue_ptr; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id; +//public : bool _have_port_rob_ptr ; +//public : bool _have_port_load_queue_ptr; //-----[ methods ]----------------------------------------------------------- @@ -80,8 +79,11 @@ uint32_t nb_bypass_memory , uint32_t size_store_queue , - uint32_t size_load_queue ); + uint32_t size_load_queue , + bool is_toplevel=false); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters.cpp (revision 88) @@ -35,81 +35,98 @@ uint32_t nb_bypass_memory , uint32_t size_store_queue , - uint32_t size_load_queue ): - _size_queue (size_queue ), - _nb_inst_retire (nb_inst_retire ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_general_register (nb_general_register ), - _nb_special_register (nb_special_register ), - _nb_gpr_write (nb_gpr_write ), - _nb_spr_write (nb_spr_write ), - _nb_bypass_write (nb_bypass_write ), - _nb_bypass_memory (nb_bypass_memory ), - _size_store_queue (size_store_queue ), - _size_load_queue (size_load_queue ), - - _size_context_id (static_cast(log2(_nb_context ))), - _size_front_end_id (static_cast(log2(_nb_front_end ))), - _size_ooo_engine_id (static_cast(log2(_nb_ooo_engine ))), - _size_rob_id (static_cast(log2(_nb_packet ))), - _size_general_register (static_cast(log2(_nb_general_register))), - _size_special_register (static_cast(log2(_nb_special_register))), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_rob_id (_size_rob_id > 0), - _have_port_load_queue_ptr(_size_load_queue > 1) + uint32_t size_load_queue , + bool is_toplevel) { log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); + + _size_queue = size_queue ; + _nb_inst_retire = nb_inst_retire ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_gpr_write = nb_gpr_write ; + _nb_spr_write = nb_spr_write ; + _nb_bypass_write = nb_bypass_write ; + _nb_bypass_memory = nb_bypass_memory ; + test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context ); + _size_front_end_id = log2(_nb_front_end ); + _size_ooo_engine_id = log2(_nb_ooo_engine ); + _size_rob_ptr = log2(_nb_packet ); + _size_general_register = log2(_nb_general_register); + _size_special_register = log2(_nb_special_register); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_store_queue_ptr = log2(size_store_queue ); + _size_load_queue_ptr = log2(size_load_queue ); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr= _size_load_queue_ptr > 0; + + copy(); + } + log_printf(FUNC,Reservation_station,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Reservation_station::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_queue (param._size_queue ), +// _nb_inst_retire (param._nb_inst_retire ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), +// _nb_general_register (param._nb_general_register ), +// _nb_special_register (param._nb_special_register ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), +// _nb_bypass_write (param._nb_bypass_write ), +// _nb_bypass_memory (param._nb_bypass_memory ), +// _size_store_queue (param._size_store_queue ), +// _size_load_queue (param._size_load_queue ), + +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_rob_id (param._size_rob_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_rob_id (param._have_port_rob_id ), +// _have_port_load_queue_ptr(param._have_port_load_queue_ptr) +// { +// log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Reservation_station,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Reservation_station::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_queue (param._size_queue ), - _nb_inst_retire (param._nb_inst_retire ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), - _nb_bypass_write (param._nb_bypass_write ), - _nb_bypass_memory (param._nb_bypass_memory ), - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_rob_id (param._size_rob_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_rob_id (param._have_port_rob_id ), - _have_port_load_queue_ptr(param._have_port_load_queue_ptr) +#define FUNCTION "Reservation_station::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); - test(); log_printf(FUNC,Reservation_station,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Reservation_station::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Reservation_station::copy" + void Parameters::copy (void) { log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Parameters_print.cpp (revision 88) @@ -42,6 +42,6 @@ xml.singleton_begin("nb_bypass_write "); xml.attribut("value",toString(_nb_bypass_write )); xml.singleton_end(); xml.singleton_begin("nb_bypass_memory "); xml.attribut("value",toString(_nb_bypass_memory )); xml.singleton_end(); - xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); - xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); +// xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); +// xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); +#if DEBUG_Reservation_station == true + log_printf(INFO,Reservation_station,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + #ifdef SYSTEMC log_printf(INFO,Reservation_station,FUNCTION,"Allocation"); @@ -46,17 +52,25 @@ #ifdef STATISTICS - log_printf(INFO,Reservation_station,FUNCTION,"Allocation of statistics"); - - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Reservation_station,FUNCTION,"Allocation of statistics"); + + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,Reservation_station,FUNCTION,"Generate the vhdl"); - - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Reservation_station,FUNCTION,"Generate the vhdl"); + + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) log_printf(INFO,Reservation_station,FUNCTION,"Method - transition"); @@ -80,5 +94,5 @@ // List dependency information #endif - + } #endif log_printf(FUNC,Reservation_station,FUNCTION,"End"); @@ -92,7 +106,10 @@ #ifdef STATISTICS - log_printf(INFO,Reservation_station,FUNCTION,"Generate Statistics file"); - - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Reservation_station,FUNCTION,"Generate Statistics file"); + + delete _stat; + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 88) @@ -3,5 +3,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -37,5 +37,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Interface * interface = _interfaces->set_interface("" @@ -50,5 +50,5 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); - // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface_fifo * interface = _interfaces->set_interface("insert" @@ -68,11 +68,11 @@ if (_param->_have_port_ooo_engine_id) in_INSERT_OOO_ENGINE_ID = interface->set_signal_in ("ooo_engine_id" ,_param->_size_ooo_engine_id ); - if (_param->_have_port_rob_id) - in_INSERT_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_id ); + if (_param->_have_port_rob_ptr) + in_INSERT_ROB_ID = interface->set_signal_in ("rob_id" ,_param->_size_rob_ptr ); in_INSERT_OPERATION = interface->set_signal_in ("operation" ,_param->_size_operation ); in_INSERT_TYPE = interface->set_signal_in ("type" ,_param->_size_type ); - in_INSERT_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write" ,log2(_param->_size_store_queue)); + in_INSERT_STORE_QUEUE_PTR_WRITE = interface->set_signal_in ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - in_INSERT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,log2(_param->_size_load_queue) ); + in_INSERT_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); in_INSERT_HAS_IMMEDIAT = interface->set_signal_in ("has_immediat" ,1 ); in_INSERT_IMMEDIAT = interface->set_signal_in ("immediat" ,_param->_size_general_data ); @@ -95,5 +95,5 @@ } - // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ out_RETIRE_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_inst_retire]; in_RETIRE_ACK = new SC_IN (Tcontrol_t ) * [_param->_nb_inst_retire]; @@ -104,5 +104,5 @@ if (_param->_have_port_ooo_engine_id) out_RETIRE_OOO_ENGINE_ID = new SC_OUT(Tcontext_t ) * [_param->_nb_inst_retire]; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) out_RETIRE_ROB_ID = new SC_OUT(Tpacket_t ) * [_param->_nb_inst_retire]; out_RETIRE_OPERATION = new SC_OUT(Toperation_t ) * [_param->_nb_inst_retire]; @@ -138,11 +138,11 @@ if (_param->_have_port_ooo_engine_id) out_RETIRE_OOO_ENGINE_ID[i] = interface->set_signal_out ("ooo_engine_id",_param->_size_ooo_engine_id); - if (_param->_have_port_rob_id) - out_RETIRE_ROB_ID [i] = interface->set_signal_out ("rob_id" ,_param->_size_rob_id); + if (_param->_have_port_rob_ptr) + out_RETIRE_ROB_ID [i] = interface->set_signal_out ("rob_id" ,_param->_size_rob_ptr); out_RETIRE_OPERATION [i] = interface->set_signal_out ("operation" ,_param->_size_operation); out_RETIRE_TYPE [i] = interface->set_signal_out ("type" ,_param->_size_type); - out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("store_queue_ptr_write" ,log2(_param->_size_store_queue)); + out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("store_queue_ptr_write" ,_param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("load_queue_ptr_write" ,log2(_param->_size_load_queue) ); + out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = interface->set_signal_out ("load_queue_ptr_write" ,_param->_size_load_queue_ptr ); out_RETIRE_HAS_IMMEDIAT [i] = interface->set_signal_out ("has_immediat" ,1); @@ -157,5 +157,5 @@ } - // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; if (_param->_have_port_ooo_engine_id) @@ -181,5 +181,5 @@ } - // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; if (_param->_have_port_ooo_engine_id) @@ -205,5 +205,5 @@ } - // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ if (_param->_have_port_ooo_engine_id) in_BYPASS_WRITE_OOO_ENGINE_ID = new SC_IN (Tcontext_t ) * [_param->_nb_bypass_write]; @@ -235,5 +235,5 @@ } - // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_BYPASS_MEMORY_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_bypass_memory]; if (_param->_have_port_ooo_engine_id) @@ -260,12 +260,16 @@ - // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ internal_RETIRE_VAL = new Tcontrol_t [_param->_nb_inst_retire]; internal_RETIRE_SLOT = new uint32_t [_param->_nb_inst_retire]; - - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -#ifdef POSITION - _component->generate_file(); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif #ifdef SYSTEMC_VHDL_COMPATIBILITY Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_deallocation.cpp (revision 88) @@ -28,4 +28,6 @@ log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); + if (usage_is_set(_usage,USE_SYSTEMC)) + { delete in_CLOCK ; delete in_NRESET; @@ -39,5 +41,5 @@ if (_param->_have_port_ooo_engine_id) delete in_INSERT_OOO_ENGINE_ID ; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) delete in_INSERT_ROB_ID ; delete in_INSERT_OPERATION ; @@ -73,5 +75,5 @@ if (_param->_have_port_ooo_engine_id) delete [] out_RETIRE_OOO_ENGINE_ID ; - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) delete [] out_RETIRE_ROB_ID ; delete [] out_RETIRE_OPERATION ; @@ -119,5 +121,6 @@ // ~~~~~[ internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] internal_RETIRE_VAL; - + delete [] internal_RETIRE_SLOT; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -139,5 +142,4 @@ }; // end namespace multi_execute_loop }; // end namespace core - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif log_printf(FUNC,Reservation_station,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_genMoore.cpp (revision 88) @@ -24,5 +24,6 @@ void Reservation_station::genMoore (void) { - log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); + log_begin(Reservation_station,FUNCTION); + log_function(Reservation_station,FUNCTION,_name.c_str()); // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~ @@ -97,5 +98,5 @@ if (_param->_have_port_ooo_engine_id) PORT_WRITE(out_RETIRE_OOO_ENGINE_ID [i],_queue[index_find]._ooo_engine_id); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) PORT_WRITE(out_RETIRE_ROB_ID [i],_queue[index_find]._rob_id); PORT_WRITE(out_RETIRE_OPERATION [i],_queue[index_find]._operation); @@ -116,5 +117,5 @@ } - log_printf(FUNC,Reservation_station,FUNCTION,"End"); + log_end(Reservation_station,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 88) @@ -20,43 +20,70 @@ #ifdef SYSTEMC_VHDL_COMPATIBILITY -#define dump_queue() \ - do\ - {\ - log_printf(TRACE,Reservation_station,FUNCTION," * dump queue");\ - log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_nb_elt);\ - for (uint32_t j=0;j<_param->_size_queue; j++)\ - {\ - cout << "\t"\ - << "[" << j << "] "\ - << "{" << _queue[j]._rob_id << " - "<< _queue[j]._context_id << "} " << " - "<< _queue[j]._front_end_id << "} " << " - "<< _queue[j]._ooo_engine_id << "} "\ - << _queue[j]._data_ra_val << ", "\ - << _queue[j]._num_reg_ra << " - "\ - << _queue[j]._data_rb_val << ","\ - << _queue[j]._num_reg_rb << " - "\ - << _queue[j]._data_rc_val << ","\ - << _queue[j]._num_reg_rc \ - << endl;\ - }\ - } while (0) -#else -#define dump_queue() \ - do\ - {\ - log_printf(TRACE,Reservation_station,FUNCTION," * dump queue");\ - log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_nb_elt);\ - for (uint32_t j=0;j<_param->_size_queue; j++)\ - {\ - cout << "\t"\ - << "[" << (*_queue_control)[j] << "] "\ - << "{" << _queue[(*_queue_control)[j]]._rob_id << " - "<< _queue[(*_queue_control)[j]]._context_id << "} " << " - "<< _queue[(*_queue_control)[j]]._front_end_id << "} " << " - "<< _queue[(*_queue_control)[j]]._ooo_engine_id << "} "\ - << _queue[(*_queue_control)[j]]._data_ra_val << ", "\ - << _queue[(*_queue_control)[j]]._num_reg_ra << " - "\ - << _queue[(*_queue_control)[j]]._data_rb_val << ","\ - << _queue[(*_queue_control)[j]]._num_reg_rb << " - "\ - << _queue[(*_queue_control)[j]]._data_rc_val << ","\ - << _queue[(*_queue_control)[j]]._num_reg_rc \ - << endl;\ - }\ - } while (0) +#define dump_queue() \ + do \ + { \ + log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \ + for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \ + log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ + it_dump, \ + _queue[it_dump]._context_id , \ + _queue[it_dump]._front_end_id , \ + _queue[it_dump]._ooo_engine_id , \ + _queue[it_dump]._rob_id , \ + _queue[it_dump]._type , \ + _queue[it_dump]._operation , \ + _queue[it_dump]._store_queue_ptr_write, \ + _queue[it_dump]._load_queue_ptr_write , \ + _queue[it_dump]._has_immediat , \ + _queue[it_dump]._immediat , \ + _queue[it_dump]._num_reg_ra , \ + _queue[it_dump]._data_ra_val , \ + _queue[it_dump]._data_ra , \ + _queue[it_dump]._num_reg_rb , \ + _queue[it_dump]._data_rb_val , \ + _queue[it_dump]._data_rb , \ + _queue[it_dump]._num_reg_rc , \ + _queue[it_dump]._data_rc_val , \ + _queue[it_dump]._data_rc , \ + _queue[it_dump]._write_rd , \ + _queue[it_dump]._num_reg_rd , \ + _queue[it_dump]._write_re , \ + _queue[it_dump]._num_reg_re , \ + toString_type(_queue[it_dump]._type).c_str()); \ + } while (0) +#else +#define dump_queue() \ + do \ + { \ + log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \ + log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_control->nb_elt()); \ + for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \ + log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ + (*_queue_control)[it_dump], \ + _queue[(*_queue_control)[it_dump]]._context_id , \ + _queue[(*_queue_control)[it_dump]]._front_end_id , \ + _queue[(*_queue_control)[it_dump]]._ooo_engine_id , \ + _queue[(*_queue_control)[it_dump]]._rob_id , \ + _queue[(*_queue_control)[it_dump]]._type , \ + _queue[(*_queue_control)[it_dump]]._operation , \ + _queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \ + _queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \ + _queue[(*_queue_control)[it_dump]]._has_immediat , \ + _queue[(*_queue_control)[it_dump]]._immediat , \ + _queue[(*_queue_control)[it_dump]]._num_reg_ra , \ + _queue[(*_queue_control)[it_dump]]._data_ra_val , \ + _queue[(*_queue_control)[it_dump]]._data_ra , \ + _queue[(*_queue_control)[it_dump]]._num_reg_rb , \ + _queue[(*_queue_control)[it_dump]]._data_rb_val , \ + _queue[(*_queue_control)[it_dump]]._data_rb , \ + _queue[(*_queue_control)[it_dump]]._num_reg_rc , \ + _queue[(*_queue_control)[it_dump]]._data_rc_val , \ + _queue[(*_queue_control)[it_dump]]._data_rc , \ + _queue[(*_queue_control)[it_dump]]._write_rd , \ + _queue[(*_queue_control)[it_dump]]._num_reg_rd , \ + _queue[(*_queue_control)[it_dump]]._write_re , \ + _queue[(*_queue_control)[it_dump]]._num_reg_re , \ + toString_type(_queue[(*_queue_control)[it_dump]]._type).c_str()); \ + } while (0) #endif @@ -65,5 +92,6 @@ void Reservation_station::transition (void) { - log_printf(FUNC,Reservation_station,FUNCTION,"Begin"); + log_begin(Reservation_station,FUNCTION); + log_function(Reservation_station,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -89,5 +117,5 @@ //uint32_t index = (*_queue_control)[i]; - log_printf(NONE,Reservation_station,FUNCTION,"POP [%d]",i); + log_printf(NONE,Reservation_station,FUNCTION," * POP [%d]",i); uint32_t index = internal_RETIRE_SLOT[i]; @@ -102,5 +130,5 @@ // << " * index : " << index << endl; - log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index); + log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index); } } @@ -140,5 +168,5 @@ if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_ra) { - log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); + log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); _queue[index]._data_ra_val = 1; _queue[index]._data_ra = PORT_READ(in_GPR_WRITE_DATA [j]); @@ -146,5 +174,5 @@ if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rb) { - log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); + log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); _queue[index]._data_rb_val = 1; _queue[index]._data_rb = PORT_READ(in_GPR_WRITE_DATA [j]); @@ -165,5 +193,5 @@ (PORT_READ(in_SPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rc)) { - log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); + log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); _queue[index]._data_rc_val = 1; _queue[index]._data_rc = PORT_READ(in_SPR_WRITE_DATA [j]); @@ -185,5 +213,5 @@ if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG[j]) == _queue[index]._num_reg_ra) { - log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); + log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); _queue[index]._data_ra_val = 1; _queue[index]._data_ra = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]); @@ -191,5 +219,5 @@ if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG [j]) == _queue[index]._num_reg_rb) { - log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); + log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); _queue[index]._data_rb_val = 1; _queue[index]._data_rb = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]); @@ -199,5 +227,5 @@ (PORT_READ(in_BYPASS_WRITE_SPR_NUM_REG[j]) == _queue[index]._num_reg_rc)) { - log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); + log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); _queue[index]._data_rc_val = 1; _queue[index]._data_rc = PORT_READ(in_BYPASS_WRITE_SPR_DATA [j]); @@ -218,5 +246,5 @@ if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_ra) { - log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); + log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); _queue[index]._data_ra_val = 1; _queue[index]._data_ra = PORT_READ(in_BYPASS_MEMORY_DATA [j]); @@ -224,5 +252,5 @@ if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_rb) { - log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); + log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); _queue[index]._data_rb_val = 1; _queue[index]._data_rb = PORT_READ(in_BYPASS_MEMORY_DATA [j]); @@ -235,5 +263,5 @@ ( internal_INSERT_ACK == 1)) { - log_printf(TRACE,Reservation_station,FUNCTION,"PUSH"); + log_printf(TRACE,Reservation_station,FUNCTION," * PUSH"); // Write in reservation station @@ -246,5 +274,5 @@ index = _queue_control->push(); #endif - log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index); + log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index); if (_param->_have_port_context_id) @@ -254,5 +282,5 @@ if (_param->_have_port_ooo_engine_id) _queue[index]._ooo_engine_id = PORT_READ(in_INSERT_OOO_ENGINE_ID ); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) _queue[index]._rob_id = PORT_READ(in_INSERT_ROB_ID ); _queue[index]._operation = PORT_READ(in_INSERT_OPERATION ); @@ -283,7 +311,9 @@ } + dump_queue(); + end_cycle (); - log_printf(FUNC,Reservation_station,FUNCTION,"End"); + log_end(Reservation_station,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Read_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/configuration.cfg (revision 88) @@ -1,8 +1,8 @@ Read_unit -4 4 *2 # size_read_queue -4 4 *2 # size_reservation_station +4 8 *2 # size_read_queue +4 8 *2 # size_reservation_station 1 1 *2 # nb_context 1 1 *2 # nb_front_end -1 4 *2 # nb_ooo_engine +1 4 *4 # nb_ooo_engine 64 64 *2 # nb_packet 32 32 *2 # size_general_data @@ -10,9 +10,9 @@ 64 64 *2 # nb_general_register 16 16 *2 # nb_special_register -2 2 *2 # nb_gpr_write -2 2 *2 # nb_spr_write -4 4 *2 # size_store_queue -1 4 *4 # size_load_queue -2 2 *2 # nb_inst_retire -2 2 *2 # nb_bypass_write -2 2 *2 # nb_bypass_memory +4 4 *4 # nb_gpr_write +4 4 *4 # nb_spr_write +4 4 *2 # size_store_queue +4 4 *4 # size_load_queue +4 4 *4 # nb_inst_retire +4 4 *4 # nb_bypass_write +4 4 *4 # nb_bypass_memory Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/main.cpp (revision 88) @@ -85,5 +85,7 @@ _nb_inst_retire , _nb_bypass_write , - _nb_bypass_memory ); + _nb_bypass_memory , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/src/test.cpp (revision 88) @@ -7,10 +7,24 @@ */ -#define NB_ITERATION 1 -#define CYCLE_MAX (128*NB_ITERATION) +#define NB_ITERATION 16 +#define CYCLE_MAX (1024*NB_ITERATION) #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/include/test.h" #include "Common/include/Test.h" +#include "Common/include/BitManipulation.h" #include "Behavioural/include/Allocation.h" + +class write_req_t +{ + public : uint32_t ooo; + public : uint32_t reg; + + write_req_t (uint32_t ooo, + uint32_t reg) + { + this->ooo = ooo; + this->reg = reg; + } +}; void test (string name, @@ -22,4 +36,14 @@ morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Read_unit * _Read_unit = new Read_unit @@ -29,5 +53,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -130,5 +154,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_PACKET_ID ); INSTANCE_SC_SIGNAL (_Read_unit, in_READ_UNIT_IN_OPERATION ); @@ -157,5 +181,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_inst_retire); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_PACKET_ID ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OPERATION ,_param->_nb_inst_retire); @@ -213,4 +237,12 @@ msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + // Initialisation + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + Time * _time = new Time(); @@ -218,19 +250,42 @@ * Simulation - Begin ********************************************************/ - + { // Initialisation - const uint32_t seed = 0; -//const uint32_t seed = static_cast(time(NULL)); - - srand(seed); - - SC_START(0); + const uint32_t nb_request = _param->_nb_packet; + + Tcontext_t _ooo_engine_id [nb_request]; + Tcontrol_t _read_ra [nb_request]; + Tgeneral_address_t _num_reg_ra [nb_request]; + Tcontrol_t _read_rb [nb_request]; + Tgeneral_address_t _num_reg_rb [nb_request]; + Tcontrol_t _read_rc [nb_request]; + Tspecial_address_t _num_reg_rc [nb_request]; + + // emulation of registerFile + Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; + Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; + Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; + Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; + LABEL("Initialisation"); - - LABEL("Reset"); + in_READ_UNIT_IN_VAL ->write(0); + for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) + in_READ_UNIT_OUT_ACK [i]->write(0); + for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) + in_GPR_WRITE_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_spr_write ; i++) + in_SPR_WRITE_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) + { + in_BYPASS_WRITE_GPR_VAL [i]->write(0); + in_BYPASS_WRITE_SPR_VAL [i]->write(0); + } + for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) + in_BYPASS_MEMORY_VAL [i]->write(0); + in_NRESET->write(0); SC_START(5); - in_NRESET->write(1); + in_NRESET->write(1); LABEL("Loop of Test"); @@ -240,6 +295,422 @@ LABEL("Iteration %d",iteration); - SC_START(1); + int32_t percent_transaction_queue_in = (rand()%50)+25; + int32_t percent_transaction_queue_out = (rand()%50)+25; + int32_t percent_registerfile_valid = (rand()%50)+25; + int32_t percent_transaction_registerfile = (rand()%50)+25; + int32_t percent_transaction_bypass = (rand()%50)+25; + + LABEL("Initialisation"); + + for (uint32_t i=0; i_nb_ooo_engine ; + _read_ra [i] = rand()% 2 ; + _num_reg_ra [i] = rand()% _param->_nb_general_register ; + _read_rb [i] = rand()% 2 ; + _num_reg_rb [i] = rand()% _param->_nb_general_register ; + _read_rc [i] = rand()% 2 ; + _num_reg_rc [i] = rand()% _param->_nb_special_register ; + } + + // emulation of registerFile + for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) + { + for (uint32_t i=0; i<_param->_nb_general_register; i++) + { + _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); + _gpr [i][j] = range(rand(),_param->_size_general_data); + } + for (uint32_t i=0; i<_param->_nb_special_register; i++) + { + _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); + _spr [i][j] = range(rand(),_param->_size_special_data); + } + } + // End initialisation ....... + + uint32_t request_in = 0; + uint32_t request_out = 0; + bool request_out_wait [nb_request]; + + for (uint32_t i=0; i_nb_ooo_engine][_param->_nb_general_register]; +// bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; + + list write_req_gpr; + list write_req_spr; + + while (request_out < nb_request) + { + LABEL("request_in : %d",request_in ); + LABEL("request_out : %d",request_out); + for (uint32_t i=0; i_nb_ooo_engine; j++) +// { +// for (uint32_t i=0; i<_param->_nb_general_register; i++) +// can_gpr_use [j][i] = true; +// for (uint32_t i=0; i<_param->_nb_special_register; i++) +// can_spr_use [j][i] = true; +// } + + Tcontrol_t read_unit_in_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); + Tcontext_t read_unit_in_ooo_engine_id; + Tgeneral_address_t read_unit_in_num_reg_ra; + Tgeneral_address_t read_unit_in_num_reg_rb; + Tspecial_address_t read_unit_in_num_reg_rc; + + in_READ_UNIT_IN_VAL ->write(read_unit_in_val); + if (read_unit_in_val) + { + bool data_val; + read_unit_in_ooo_engine_id = _ooo_engine_id [request_in]; + read_unit_in_num_reg_ra = _num_reg_ra [request_in]; + read_unit_in_num_reg_rb = _num_reg_rb [request_in]; + read_unit_in_num_reg_rc = _num_reg_rc [request_in]; + + if (_param->_have_port_context_id) + in_READ_UNIT_IN_CONTEXT_ID ->write((2*read_unit_in_ooo_engine_id)%_param->_nb_context ); + if (_param->_have_port_front_end_id) + in_READ_UNIT_IN_FRONT_END_ID ->write((3*read_unit_in_ooo_engine_id)%_param->_nb_front_end); + if (_param->_have_port_ooo_engine_id) + in_READ_UNIT_IN_OOO_ENGINE_ID ->write(read_unit_in_ooo_engine_id); + if (_param->_have_port_rob_ptr) + in_READ_UNIT_IN_PACKET_ID ->write(request_in); + in_READ_UNIT_IN_OPERATION ->write(0); + in_READ_UNIT_IN_TYPE ->write(0); + in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE->write(0); + if (_param->_have_port_load_queue_ptr) + in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ->write(0); + in_READ_UNIT_IN_HAS_IMMEDIAT->write(0); + in_READ_UNIT_IN_IMMEDIAT ->write(0); + in_READ_UNIT_IN_READ_RA ->write(_read_ra[request_in]); + data_val = not(_read_ra[request_in]) or _gpr_val[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]; + + if (not data_val) + if (rand ()%2) + write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra)); + else + write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra)); + + + in_READ_UNIT_IN_NUM_REG_RA ->write(read_unit_in_num_reg_ra); +// in_READ_UNIT_IN_DATA_RA_VAL ->write(data_val); +// in_READ_UNIT_IN_DATA_RA ->write((data_val)?_gpr[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]:0); + in_READ_UNIT_IN_READ_RB ->write(_read_rb[request_in]); + data_val = not(_read_rb[request_in]) or _gpr_val[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]; + + if (not data_val) + if (rand ()%2) + write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb)); + else + write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb)); + + + in_READ_UNIT_IN_NUM_REG_RB ->write(read_unit_in_num_reg_rb); +// in_READ_UNIT_IN_DATA_RB_VAL ->write(data_val); +// in_READ_UNIT_IN_DATA_RB ->write((data_val)?_gpr[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]:0); + in_READ_UNIT_IN_READ_RC ->write(_read_rc[request_in]); + data_val = not(_read_rc[request_in]) or _spr_val[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]; + + if (not data_val) + if (rand ()%2) + write_req_spr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc)); + else + write_req_spr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc)); + + in_READ_UNIT_IN_NUM_REG_RC ->write(read_unit_in_num_reg_rc); +// in_READ_UNIT_IN_DATA_RC_VAL ->write(data_val); +// in_READ_UNIT_IN_DATA_RC ->write((data_val)?_spr[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]:0); + in_READ_UNIT_IN_WRITE_RD ->write(0); + in_READ_UNIT_IN_NUM_REG_RD ->write(0); + in_READ_UNIT_IN_WRITE_RE ->write(0); + in_READ_UNIT_IN_NUM_REG_RE ->write(0); + +// can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_ra] = false; +// can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rb] = false; +// can_spr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rc] = false; + } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + in_READ_UNIT_OUT_ACK[i]->write((rand()%100)_nb_gpr_read ; i++) + { + Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile; + in_GPR_READ_ACK [i]->write(ack); + + SC_START(0); + + if (out_GPR_READ_VAL [i]->read()) + { + Tgeneral_address_t num_reg = out_GPR_READ_NUM_REG [i]->read(); + Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_GPR_READ_OOO_ENGINE_ID [i]->read():0; + Tgeneral_data_t data = _gpr [num_reg][ooo_engine]; + Tcontrol_t data_val = _gpr_val[num_reg][ooo_engine]; + + if (ack) + LABEL(" * GPR_READ [%d] - gpr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data); + + in_GPR_READ_DATA [i]->write(data); + in_GPR_READ_DATA_VAL [i]->write(data_val); + } + } + + for (uint32_t i=0; i<_param->_nb_spr_read ; i++) + { + Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile; + in_SPR_READ_ACK [i]->write(ack); + + SC_START(0); + + if (out_SPR_READ_VAL [i]->read()) + { + Tspecial_address_t num_reg = out_SPR_READ_NUM_REG [i]->read(); + Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_SPR_READ_OOO_ENGINE_ID [i]->read():0; + Tspecial_data_t data = _spr [num_reg][ooo_engine]; + Tcontrol_t data_val = _spr_val[num_reg][ooo_engine]; + + if (ack) + LABEL(" * SPR_READ [%d] - spr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data); + + in_SPR_READ_DATA [i]->write(data); + in_SPR_READ_DATA_VAL [i]->write(data_val); + } + } + + list::iterator it_gpr = write_req_gpr.begin(); + list::iterator it_spr = write_req_spr.begin(); + + LABEL("Bypass Network :"); + for (uint32_t i=0; i<_param->_nb_gpr_write; i++) + { + Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; + Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; + Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; + Tgeneral_data_t data = range(rand(),_param->_size_general_data); + + val = (val// and can_spr_use [ooo_engine][num_reg] + and (it_gpr != write_req_gpr.end())); + + in_GPR_WRITE_VAL [i]->write(val); + if (_param->_have_port_ooo_engine_id) + in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); + in_GPR_WRITE_NUM_REG [i]->write(num_reg); + in_GPR_WRITE_DATA [i]->write(data); + + if (val) + { + LABEL(" * GPR_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); + +// can_gpr_use [ooo_engine][num_reg] = false; + + _gpr [num_reg][ooo_engine] = data; + _gpr_val [num_reg][ooo_engine] = 1; + } + + if (it_gpr != write_req_gpr.end()) + it_gpr ++; + } + for (uint32_t i=0; i<_param->_nb_spr_write; i++) + { + Tcontext_t ooo_engine = (it_spr != write_req_spr.end())?(*it_spr).ooo:0; + Tgeneral_address_t num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0; + + Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; + Tspecial_data_t data = range(rand(),_param->_size_special_data); + + val = (val // and can_spr_use [ooo_engine][num_reg] + and (it_spr != write_req_spr.end())); + + in_SPR_WRITE_VAL [i]->write(val); + if (_param->_have_port_ooo_engine_id) + in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); + in_SPR_WRITE_NUM_REG [i]->write(num_reg); + in_SPR_WRITE_DATA [i]->write(data); + + if (val == 1) + { + LABEL(" * SPR_WRITE [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); + +// can_spr_use [ooo_engine][num_reg] = false; + + _spr [num_reg][ooo_engine] = data; + _spr_val [num_reg][ooo_engine] = 1; + } + + if (it_spr != write_req_spr.end()) + it_spr ++; + + } + + for (uint32_t i=0; i<_param->_nb_bypass_write; i++) + { + Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; + Tgeneral_address_t gpr_num_reg= (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; + + if (_param->_have_port_ooo_engine_id) + in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); + + Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; + Tgeneral_data_t gpr_data = range(rand(),_param->_size_general_data); + + gpr_val = (gpr_val // and can_gpr_use [ooo_engine][gpr_num_reg] + and (it_gpr != write_req_gpr.end())); + + in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); + in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); + in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); + + if (gpr_val) + { + LABEL(" * BYPASS_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,gpr_num_reg,ooo_engine,gpr_data); +// can_gpr_use [ooo_engine][gpr_num_reg] = false; + + _gpr [gpr_num_reg][ooo_engine] = gpr_data; + _gpr_val [gpr_num_reg][ooo_engine] = 1; + } + + if (it_gpr != write_req_gpr.end()) + it_gpr ++; + + Tspecial_address_t spr_num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0; + Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; + Tspecial_data_t spr_data = range(rand(),_param->_size_special_data); + + spr_val = (spr_val // and can_spr_use [ooo_engine][spr_num_reg] + and (it_spr != write_req_spr.end()) and ((*it_spr).ooo == ooo_engine)); + + in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); + in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); + in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); + + if (spr_val) + { + LABEL(" * BYPASS_WRITE [%d] - spr[%d][%d] <- 0x%x",i,spr_num_reg,ooo_engine,spr_data); + +// can_spr_use [ooo_engine][spr_num_reg] = false; + + _spr [spr_num_reg][ooo_engine] = spr_data; + _spr_val [spr_num_reg][ooo_engine] = 1; + } + + if (it_spr != write_req_spr.end()) + it_spr ++; + } + + for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) + { + Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; + Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; + + if (_param->_have_port_ooo_engine_id) + in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); + + Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; + Tgeneral_data_t data = range(rand(),_param->_size_general_data); + + val = (val // and can_gpr_use [ooo_engine][num_reg] + and (it_gpr != write_req_gpr.end())); + + in_BYPASS_MEMORY_VAL [i]->write(val); + in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); + in_BYPASS_MEMORY_DATA [i]->write(data); + + if (val) + { + LABEL(" * BYPASS_MEMORY [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); + +// can_gpr_use [ooo_engine][num_reg] = false; + + _gpr [num_reg][ooo_engine] = data; + _gpr_val [num_reg][ooo_engine] = 1; + } + + if (it_gpr != write_req_gpr.end()) + it_gpr ++; + } + + SC_START(0); // to mealy function + +// LABEL("Test READ_UNIT_IN : "+toString(in_READ_UNIT_IN_VAL->read())+","+toString(out_READ_UNIT_IN_ACK->read())); + if (( in_READ_UNIT_IN_VAL->read() == 1) and + (out_READ_UNIT_IN_ACK->read() == 1)) + { + LABEL("Accepted READ_UNIT_IN number : %d",request_in); + request_in ++; + } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + LABEL("Test READ_UNIT_OUT %d : %d,%d",i,out_READ_UNIT_OUT_VAL[i]->read(),in_READ_UNIT_OUT_ACK[i]->read()); + if ((out_READ_UNIT_OUT_VAL [i]->read() == 1) and + ( in_READ_UNIT_OUT_ACK [i]->read() == 1)) + { + Tpacket_t packet_id; + if (_param->_have_port_rob_ptr) + packet_id = out_READ_UNIT_OUT_PACKET_ID [i]->read(); + else + packet_id = 0; + LABEL("Accepted READ_UNIT_OUT [%d] number : %d, request number : %d",i,packet_id,request_out); + TEST(bool, request_out_wait [packet_id] , true); + + request_out ++; + request_out_wait [packet_id] = false; + + Tcontext_t ooo_engine_id = _ooo_engine_id [packet_id]; + + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_READ_UNIT_OUT_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); + if (_param->_have_port_front_end_id) + TEST(Tcontext_t ,out_READ_UNIT_OUT_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); + if (_param->_have_port_ooo_engine_id) + TEST(Tcontext_t ,out_READ_UNIT_OUT_OOO_ENGINE_ID[i]->read(),ooo_engine_id); + + if (_read_ra [packet_id]) + TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RA [i]->read(),_gpr[_num_reg_ra[packet_id]][ooo_engine_id]); + + if (_read_rb [packet_id]) + TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RB [i]->read(),_gpr[_num_reg_rb[packet_id]][ooo_engine_id]); + + if (_read_rc [packet_id]) + TEST(Tspecial_data_t ,out_READ_UNIT_OUT_DATA_RC [i]->read(),_spr[_num_reg_rc[packet_id]][ooo_engine_id]); + } + } + + SC_START(1); + + for (list::iterator it = write_req_gpr.begin(); + it != write_req_gpr.end(); + ) + { + if (_gpr_val [(*it).reg][(*it).ooo] == 1) + it = write_req_gpr.erase(it); + else + it ++; + } + + for (list::iterator it = write_req_spr.begin(); + it != write_req_spr.end(); + ) + { + if (_spr_val [(*it).reg][(*it).ooo] == 1) + it = write_req_spr.erase(it); + else + it ++; + } + } + + for (uint32_t i=0; i0), - _have_port_front_end_id (_size_front_end_id >0), - _have_port_ooo_engine_id (_size_ooo_engine_id>0), - _have_port_packet_id (_size_packet_id >0), - _have_port_load_queue_ptr (_size_load_queue >1) + uint32_t size_reservation_station, + uint32_t nb_context , + uint32_t nb_front_end , + uint32_t nb_ooo_engine , + uint32_t nb_packet , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t nb_general_register , + uint32_t nb_special_register , + uint32_t nb_gpr_write , + uint32_t nb_spr_write , + uint32_t size_store_queue , + uint32_t size_load_queue , + uint32_t nb_inst_retire , + uint32_t nb_bypass_write , + uint32_t nb_bypass_memory , + bool is_toplevel) { log_printf(FUNC,Read_unit,FUNCTION,"Begin"); + _size_read_queue = size_read_queue ; + _size_reservation_station = size_reservation_station; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_gpr_write = nb_gpr_write ; + _nb_spr_write = nb_spr_write ; + _nb_inst_retire = nb_inst_retire ; + _nb_bypass_write = nb_bypass_write ; + _nb_bypass_memory = nb_bypass_memory ; + + _nb_gpr_read = 2; + _nb_spr_read = 1; + _param_read_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Parameters - ( _size_read_queue - ,_nb_context - ,_nb_front_end - ,_nb_ooo_engine - ,_nb_packet - ,_size_general_data - ,_size_special_data - ,_nb_general_register - ,_nb_special_register - ,_nb_gpr_write - ,_nb_spr_write - ,_size_store_queue - ,_size_load_queue - ); + (_size_read_queue + ,_nb_context + ,_nb_front_end + ,_nb_ooo_engine + ,_nb_packet + , size_general_data + , size_special_data + ,_nb_general_register + ,_nb_special_register + ,_nb_gpr_write + ,_nb_spr_write + , size_store_queue + , size_load_queue + ); _param_reservation_station = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters - (size_reservation_station - ,nb_inst_retire - ,nb_context - ,nb_front_end - ,nb_ooo_engine - ,nb_packet - ,size_general_data - ,size_special_data - ,nb_general_register - ,nb_special_register - ,nb_gpr_write - ,nb_spr_write - ,nb_bypass_write - ,nb_bypass_memory - ,size_store_queue - ,size_load_queue - ); - + (_size_reservation_station + ,_nb_inst_retire + ,_nb_context + ,_nb_front_end + ,_nb_ooo_engine + ,_nb_packet + , size_general_data + , size_special_data + ,_nb_general_register + ,_nb_special_register + ,_nb_gpr_write + ,_nb_spr_write + ,_nb_bypass_write + ,_nb_bypass_memory + , size_store_queue + , size_load_queue + ); test(); + + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_front_end_id = log2(nb_front_end ); + _size_ooo_engine_id = log2(nb_ooo_engine ); + _size_rob_ptr = log2(nb_packet ); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_store_queue_ptr = log2(size_store_queue ); + _size_load_queue_ptr = log2(size_load_queue ); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + + copy(); + } log_printf(FUNC,Read_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Read_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_read_queue (param._size_read_queue ), +// _size_reservation_station (param._size_reservation_station), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), +// _nb_general_register (param._nb_general_register ), +// _nb_special_register (param._nb_special_register ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), +// _size_store_queue (param._size_store_queue ), +// _size_load_queue (param._size_load_queue ), +// _nb_inst_retire (param._nb_inst_retire ), +// _nb_bypass_write (param._nb_bypass_write ), +// _nb_bypass_memory (param._nb_bypass_memory ), + +// _nb_gpr_read (param._nb_gpr_read ), +// _nb_spr_read (param._nb_spr_read ), +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id ), +// _have_port_packet_id (param._have_port_packet_id ), +// _have_port_load_queue_ptr (param._have_port_load_queue_ptr) +// { +// log_printf(FUNC,Read_unit,FUNCTION,"Begin"); + +// _param_read_queue = param._param_read_queue ; +// _param_reservation_station = param._param_reservation_station; + +// test(); + +// log_printf(FUNC,Read_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Read_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_read_queue (param._size_read_queue ), - _size_reservation_station (param._size_reservation_station), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), - _nb_inst_retire (param._nb_inst_retire ), - _nb_bypass_write (param._nb_bypass_write ), - _nb_bypass_memory (param._nb_bypass_memory ), - - _nb_gpr_read (param._nb_gpr_read ), - _nb_spr_read (param._nb_spr_read ), - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id ), - _have_port_packet_id (param._have_port_packet_id ), - _have_port_load_queue_ptr (param._have_port_load_queue_ptr) +#define FUNCTION "Read_unit::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Read_unit,FUNCTION,"Begin"); - _param_read_queue = param._param_read_queue ; - _param_reservation_station = param._param_reservation_station; - - test(); + delete _param_read_queue; + delete _param_reservation_station; log_printf(FUNC,Read_unit,FUNCTION,"End"); @@ -159,11 +178,11 @@ #undef FUNCTION -#define FUNCTION "Read_unit::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Read_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Read_unit,FUNCTION,"Begin"); - delete _param_read_queue; - delete _param_reservation_station; + COPY(_param_read_queue); + COPY(_param_reservation_station); log_printf(FUNC,Read_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Parameters_print.cpp (revision 88) @@ -39,6 +39,6 @@ xml.singleton_begin("nb_gpr_write "); xml.attribut("value",toString(_nb_gpr_write )); xml.singleton_end(); xml.singleton_begin("nb_spr_write "); xml.attribut("value",toString(_nb_spr_write )); xml.singleton_end(); - xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); - xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); +// xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); +// xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); xml.singleton_begin("nb_inst_retire "); xml.attribut("value",toString(_nb_inst_retire )); xml.singleton_end(); xml.singleton_begin("nb_bypass_write "); xml.attribut("value",toString(_nb_bypass_write )); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Read_unit,FUNCTION,"Begin"); +#if DEBUG_Read_unit == true + log_printf(INFO,Read_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Read_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Read_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Read_unit,FUNCTION,"Method - transition"); @@ -90,5 +96,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Read_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 88) @@ -48,5 +48,5 @@ ,IN ,SOUTH, - "Generalist interface" + _("Generalist interface") #endif ); @@ -57,5 +57,5 @@ // ~~~~~[ Interface "read_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("read_unit_in", IN, WEST, "Enter of new operation"); + ALLOC_INTERFACE("read_unit_in", IN, WEST, _("Enter of new operation")); ALLOC_VALACK_IN ( in_READ_UNIT_IN_VAL,VAL); @@ -64,9 +64,9 @@ ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,log2(_param->_size_store_queue)); - ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,log2(_param->_size_load_queue)); + ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); @@ -85,5 +85,5 @@ // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("read_unit_out", OUT, EAST, "Output of operation. All operand is valid.", _param->_nb_inst_retire); + ALLOC1_INTERFACE("read_unit_out", OUT, EAST, _("Output of operation. All operand is valid."), _param->_nb_inst_retire); ALLOC1_VALACK_OUT (out_READ_UNIT_OUT_VAL,VAL); @@ -92,9 +92,9 @@ ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,log2(_param->_size_store_queue)); - ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,log2(_param->_size_load_queue )); + ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -110,5 +110,5 @@ // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("gpr_read", OUT, SOUTH, "Read port.", _param->_nb_gpr_read); + ALLOC1_INTERFACE("gpr_read", OUT, SOUTH, _("Read port."), _param->_nb_gpr_read); ALLOC1_VALACK_OUT (out_GPR_READ_VAL,VAL); @@ -122,5 +122,5 @@ // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_read", OUT, SOUTH, "Read port.", _param->_nb_spr_read); + ALLOC1_INTERFACE("spr_read", OUT, SOUTH, _("Read port."), _param->_nb_spr_read); ALLOC1_VALACK_OUT (out_SPR_READ_VAL,VAL); @@ -134,5 +134,5 @@ // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("gpr_write", IN , SOUTH, "Write port.", _param->_nb_gpr_write); + ALLOC1_INTERFACE("gpr_write", IN , SOUTH, _("Write port."), _param->_nb_gpr_write); ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL,VAL); @@ -144,5 +144,5 @@ // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("spr_write", IN , SOUTH, "Write port.", _param->_nb_spr_write); + ALLOC1_INTERFACE("spr_write", IN , SOUTH, _("Write port."), _param->_nb_spr_write); ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL,VAL); @@ -154,5 +154,5 @@ // ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("bypass_write", IN , NORTH, "Output of write_queue.", _param->_nb_bypass_write); + ALLOC1_INTERFACE("bypass_write", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_write); ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); @@ -167,5 +167,5 @@ // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("bypass_memory", IN , NORTH, "Output of write_queue.", _param->_nb_bypass_memory); + ALLOC1_INTERFACE("bypass_memory", IN , NORTH, _("Output of write_queue."), _param->_nb_bypass_memory); ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_VAL ,"val" ,Tcontrol_t ,1); @@ -177,10 +177,9 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - std::string name; { name = _name+"_read_queue"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_read_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Read_queue @@ -200,5 +199,6 @@ { name = _name+"_reservation_station"; - + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + _component_reservation_station = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Reservation_station (name.c_str() @@ -219,5 +219,6 @@ { name = _name+"_read_queue"; - std::cout << "Instance : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str()); + { #ifdef POSITION @@ -246,5 +247,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name, "in_READ_QUEUE_IN_OOO_ENGINE_ID" ,dest, "in_READ_UNIT_IN_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name, "in_READ_QUEUE_IN_ROB_ID" ,dest, "in_READ_UNIT_IN_PACKET_ID" ); _component->port_map(name, "in_READ_QUEUE_IN_OPERATION" ,dest, "in_READ_UNIT_IN_OPERATION" ); @@ -283,5 +284,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name,"out_READ_QUEUE_OUT_OOO_ENGINE_ID" ,dest, "in_INSERT_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name,"out_READ_QUEUE_OUT_ROB_ID" ,dest, "in_INSERT_ROB_ID" ); _component->port_map(name,"out_READ_QUEUE_OUT_OPERATION" ,dest, "in_INSERT_OPERATION" ); @@ -379,5 +380,5 @@ { name = _name+"_reservation_station"; - std::cout << "Instance : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str()); { #ifdef POSITION @@ -407,5 +408,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name, "in_INSERT_OOO_ENGINE_ID" ,dest,"out_READ_QUEUE_OUT_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name, "in_INSERT_ROB_ID" ,dest,"out_READ_QUEUE_OUT_ROB_ID" ); _component->port_map(name, "in_INSERT_OPERATION" ,dest,"out_READ_QUEUE_OUT_OPERATION" ); @@ -452,5 +453,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name,"out_RETIRE_"+toString(i)+"_OOO_ENGINE_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name,"out_RETIRE_"+toString(i)+"_ROB_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_PACKET_ID" ); _component->port_map(name,"out_RETIRE_"+toString(i)+"_OPERATION" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_OPERATION" ); @@ -535,7 +536,11 @@ } - -#ifdef POSITION - _component->generate_file(); +#if DEBUG_Read_unit == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Read_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -37,5 +37,5 @@ if (_param->_have_port_ooo_engine_id) delete in_READ_UNIT_IN_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete in_READ_UNIT_IN_PACKET_ID ; delete in_READ_UNIT_IN_OPERATION ; @@ -66,5 +66,5 @@ if (_param->_have_port_ooo_engine_id) delete [] out_READ_UNIT_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete [] out_READ_UNIT_OUT_PACKET_ID ; delete [] out_READ_UNIT_OUT_OPERATION ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Execute_queue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/configuration.cfg (revision 88) @@ -1,8 +1,8 @@ Execute_queue -8 8 *2 # uint32_t size_queue +8 16 *2 # uint32_t size_queue 1 1 *2 # uint32_t nb_context 1 1 *2 # uint32_t nb_front_end 1 4 *2 # uint32_t nb_ooo_engine -32 32 *2 # uint32_t nb_packet +64 64 *2 # uint32_t nb_packet 32 32 *2 # uint32_t size_general_data 2 2 *2 # uint32_t size_special_data Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/main.cpp (revision 88) @@ -54,5 +54,7 @@ nb_packet , size_general_data , - size_special_data ); + size_special_data , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 88) @@ -7,5 +7,5 @@ */ -#define NB_ITERATION 1 +#define NB_ITERATION 16 #define CYCLE_MAX (128*NB_ITERATION) @@ -27,4 +27,5 @@ public : Tcontrol_t _no_sequence ; public : Tgeneral_data_t _address ; + public : Tgeneral_data_t _data ; public : entry_t (Tcontext_t context_id , @@ -37,5 +38,6 @@ Texception_t exception , Tcontrol_t no_sequence , - Tgeneral_data_t address ) + Tgeneral_data_t address , + Tgeneral_data_t data ) { _context_id = context_id ; @@ -49,4 +51,5 @@ _no_sequence = no_sequence ; _address = address ; + _data = data ; }; @@ -63,5 +66,6 @@ << " * _exception : " << toString(x._exception ) << std::endl << " * _no_sequence : " << toString(x._no_sequence ) << std::endl - << " * _address : " << toString(x._address ) << std::endl; + << " * _address : " << toString(x._address ) << std::endl + << " * _data : " << toString(x._data ) << std::endl; return output_stream; @@ -80,4 +84,14 @@ morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Execute_queue * _Execute_queue = new Execute_queue @@ -87,5 +101,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -110,4 +124,5 @@ ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ," in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_DATA ," in_EXECUTE_QUEUE_IN_DATA" , Tgeneral_data_t ); ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_VAL ,"out_EXECUTE_QUEUE_OUT_VAL" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_OUT_ACK ," in_EXECUTE_QUEUE_OUT_ACK" , Tcontrol_t ); @@ -122,4 +137,5 @@ ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_DATA ,"out_EXECUTE_QUEUE_OUT_DATA" , Tgeneral_data_t ); @@ -141,5 +157,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_OPERATION ); @@ -149,4 +165,5 @@ INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_NO_SEQUENCE ); INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_ADDRESS ); + INSTANCE_SC_SIGNAL (_Execute_queue, in_EXECUTE_QUEUE_IN_DATA ); INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_VAL ); @@ -158,5 +175,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_OPERATION ); @@ -166,4 +183,5 @@ INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ); INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Execute_queue, out_EXECUTE_QUEUE_OUT_DATA ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -212,4 +230,5 @@ range(rand(),_param->_size_exception ), range(rand(),1 ), + range(rand(),_param->_size_general_data ), range(rand(),_param->_size_general_data )); } @@ -236,4 +255,5 @@ in_EXECUTE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence ); in_EXECUTE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address ); + in_EXECUTE_QUEUE_IN_DATA ->write(request [nb_request_in]->_data ); } in_EXECUTE_QUEUE_OUT_ACK ->write((rand()%100)_have_port_packet_id) + if (_param->_have_port_rob_ptr) packet = out_EXECUTE_QUEUE_OUT_PACKET_ID->read(); else @@ -281,4 +301,5 @@ TEST(Tcontrol_t , out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence ); TEST(Tgeneral_data_t, out_EXECUTE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address ); + TEST(Tgeneral_data_t, out_EXECUTE_QUEUE_OUT_DATA ->read(), request [packet]->_data ); nb_request_out ++; @@ -313,4 +334,5 @@ delete in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; delete in_EXECUTE_QUEUE_IN_ADDRESS ; + delete in_EXECUTE_QUEUE_IN_DATA ; delete out_EXECUTE_QUEUE_OUT_VAL ; @@ -326,4 +348,5 @@ delete out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; delete out_EXECUTE_QUEUE_OUT_ADDRESS ; + delete out_EXECUTE_QUEUE_OUT_DATA ; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 88) @@ -79,4 +79,5 @@ public : SC_IN (Tcontrol_t ) * in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_QUEUE_IN_ADDRESS ; + public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_QUEUE_IN_DATA ; // -----[ Interface "Execute_queue_out" ]----------------------------- @@ -93,4 +94,5 @@ public : SC_OUT(Tcontrol_t ) * out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_QUEUE_OUT_ADDRESS ; + public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_QUEUE_OUT_DATA ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h (revision 88) @@ -26,21 +26,21 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; + public : uint32_t _size_queue ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; //-----[ methods ]----------------------------------------------------------- @@ -51,7 +51,10 @@ uint32_t nb_packet , uint32_t size_general_data , - uint32_t size_special_data ); - public : Parameters (Parameters & param) ; + uint32_t size_special_data , + bool is_toplevel=true); +//public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Types.h (revision 88) @@ -32,4 +32,5 @@ public : Tcontrol_t _no_sequence ; public : Tgeneral_data_t _address ; + public : Tgeneral_data_t _data ; public : execute_queue_entry_t (Tcontext_t context_id , @@ -42,5 +43,6 @@ Texception_t exception , Tcontrol_t no_sequence , - Tgeneral_data_t address ) + Tgeneral_data_t address , + Tgeneral_data_t data ) { _context_id = context_id ; @@ -54,4 +56,5 @@ _no_sequence = no_sequence ; _address = address ; + _data = data ; }; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue.cpp (revision 88) @@ -39,9 +39,15 @@ log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); +#if DEBUG_Execute_queue == true + log_printf(INFO,Execute_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Execute_queue,FUNCTION,"Allocation"); allocation (); #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execute_queue,FUNCTION,"Allocation of statistics"); @@ -52,5 +58,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -62,5 +68,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Execute_queue,FUNCTION,"Method - transition"); @@ -96,5 +102,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execute_queue,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 88) @@ -17,6 +17,4 @@ namespace write_unit { namespace execute_queue { - - #undef FUNCTION @@ -62,6 +60,6 @@ if(_param->_have_port_ooo_engine_id) ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - if(_param->_have_port_packet_id) - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + if(_param->_have_port_rob_ptr) + ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); // ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -70,4 +68,5 @@ ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); } @@ -84,6 +83,6 @@ if(_param->_have_port_ooo_engine_id) ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - if(_param->_have_port_packet_id) - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + if(_param->_have_port_rob_ptr) + ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); // ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -92,4 +91,5 @@ ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } @@ -99,5 +99,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -38,5 +38,5 @@ if (_param->_have_port_ooo_engine_id) delete in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete in_EXECUTE_QUEUE_IN_PACKET_ID ; // delete in_EXECUTE_QUEUE_IN_OPERATION ; @@ -46,4 +46,5 @@ delete in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; delete in_EXECUTE_QUEUE_IN_ADDRESS ; + delete in_EXECUTE_QUEUE_IN_DATA ; // -----[ Interface "execute_queue_out" ]------------------------------- @@ -56,5 +57,5 @@ if (_param->_have_port_ooo_engine_id) delete out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete out_EXECUTE_QUEUE_OUT_PACKET_ID ; // delete out_EXECUTE_QUEUE_OUT_OPERATION ; @@ -64,4 +65,5 @@ delete out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; delete out_EXECUTE_QUEUE_OUT_ADDRESS ; + delete out_EXECUTE_QUEUE_OUT_DATA ; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_genMoore.cpp (revision 88) @@ -47,5 +47,5 @@ if (_param->_have_port_ooo_engine_id) PORT_WRITE(out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) PORT_WRITE(out_EXECUTE_QUEUE_OUT_PACKET_ID , _queue->front()->_packet_id ); // PORT_WRITE(out_EXECUTE_QUEUE_OUT_OPERATION , _queue->front()->_operation ); @@ -55,4 +55,5 @@ PORT_WRITE(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE , _queue->front()->_no_sequence ); PORT_WRITE(out_EXECUTE_QUEUE_OUT_ADDRESS , _queue->front()->_address ); + PORT_WRITE(out_EXECUTE_QUEUE_OUT_DATA , _queue->front()->_data ); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_transition.cpp (revision 88) @@ -44,5 +44,5 @@ (_param->_have_port_front_end_id )?PORT_READ(in_EXECUTE_QUEUE_IN_FRONT_END_ID ):0, (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID):0, - (_param->_have_port_packet_id )?PORT_READ(in_EXECUTE_QUEUE_IN_PACKET_ID ):0, + (_param->_have_port_rob_ptr )?PORT_READ(in_EXECUTE_QUEUE_IN_PACKET_ID ):0, //PORT_READ(in_EXECUTE_QUEUE_IN_OPERATION ), //PORT_READ(in_EXECUTE_QUEUE_IN_TYPE ), @@ -50,5 +50,6 @@ PORT_READ(in_EXECUTE_QUEUE_IN_EXCEPTION ), PORT_READ(in_EXECUTE_QUEUE_IN_NO_SEQUENCE ), - PORT_READ(in_EXECUTE_QUEUE_IN_ADDRESS )); + PORT_READ(in_EXECUTE_QUEUE_IN_ADDRESS ), + PORT_READ(in_EXECUTE_QUEUE_IN_DATA )); _queue->push(entry); @@ -64,5 +65,6 @@ #ifdef STATISTICS - *(_stat_use_queue) += _queue->size(); + if (usage_is_set(_usage,USE_STATISTICS)) + *(_stat_use_queue) += _queue->size(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp (revision 88) @@ -26,57 +26,74 @@ uint32_t nb_packet , uint32_t size_general_data , - uint32_t size_special_data ): - _size_queue (size_queue ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - - _size_context_id (log2(_nb_context )), - _size_front_end_id (log2(_nb_front_end )), - _size_ooo_engine_id (log2(_nb_ooo_engine )), - _size_packet_id (log2(_nb_packet )), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0) + uint32_t size_special_data , + bool is_toplevel ) { log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); + + _size_queue = size_queue ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context ); + _size_front_end_id = log2(_nb_front_end ); + _size_ooo_engine_id = log2(_nb_ooo_engine); + _size_rob_ptr = log2(_nb_packet ); + _size_general_data = size_general_data; + _size_special_data = size_special_data; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + + copy(); + } + log_printf(FUNC,Execute_queue,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Execute_queue::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_queue (param._size_queue ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), + +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_packet_id (param._have_port_packet_id ) +// { +// log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Execute_queue,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Execute_queue::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_queue (param._size_queue ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ) +#define FUNCTION "Execute_queue::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); - test(); log_printf(FUNC,Execute_queue,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Execute_queue::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Execute_queue::copy" + void Parameters::copy (void) { log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Write_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/main.cpp (revision 88) @@ -66,5 +66,7 @@ size_special_data , nb_special_register, - nb_bypass_write ); + nb_bypass_write , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 88) @@ -99,4 +99,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Write_unit * _Write_unit = new Write_unit (name.c_str(), @@ -105,5 +115,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -145,4 +155,5 @@ ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t ); ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); @@ -181,5 +192,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OOO_ENGINE_ID ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION ); @@ -202,5 +213,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OOO_ENGINE_ID); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_OPERATION ); @@ -210,4 +221,5 @@ INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_NO_SEQUENCE ); INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Write_unit, out_WRITE_UNIT_OUT_DATA ); INSTANCE1_SC_SIGNAL(_Write_unit, out_GPR_WRITE_VAL , _param->_nb_gpr_write); INSTANCE1_SC_SIGNAL(_Write_unit, in_GPR_WRITE_ACK , _param->_nb_gpr_write); @@ -445,5 +457,5 @@ { Tcontext_t packet; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) packet = out_WRITE_UNIT_OUT_PACKET_ID->read(); else @@ -479,4 +491,5 @@ TEST(Tcontrol_t , out_WRITE_UNIT_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence ); TEST(Tgeneral_data_t, out_WRITE_UNIT_OUT_ADDRESS ->read(), request [packet]->_address ); + TEST(Tgeneral_data_t, out_WRITE_UNIT_OUT_DATA ->read(), request [packet]->_data_rd ); nb_request_out ++; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Write_queue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/configuration.cfg (revision 88) @@ -9,3 +9,3 @@ 2 2 *2 # uint32_t size_special_data 16 16 *2 # uint32_t nb_special_register -1 8 *2 # uint32_t nb_bypass_write +1 8 *4 # uint32_t nb_bypass_write Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/main.cpp (revision 88) @@ -63,5 +63,7 @@ size_special_data , nb_special_register, - nb_bypass_write ); + nb_bypass_write , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 88) @@ -8,5 +8,5 @@ #define NB_ITERATION 1 -#define CYCLE_MAX (128*NB_ITERATION) +#define CYCLE_MAX (1024*NB_ITERATION) #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/test.h" @@ -98,4 +98,13 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Write_queue * _Write_queue = new Write_queue @@ -105,5 +114,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -145,4 +154,5 @@ ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Tgeneral_data_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); @@ -180,5 +190,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); @@ -201,5 +211,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OPERATION ); @@ -209,4 +219,5 @@ INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_DATA ); INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write); INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write); @@ -444,5 +455,5 @@ { Tcontext_t packet; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) packet = out_WRITE_QUEUE_OUT_PACKET_ID->read(); else @@ -478,4 +489,5 @@ TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence ); TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address ); + TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_DATA ->read(), request [packet]->_data_rd ); nb_request_out ++; @@ -531,4 +543,5 @@ delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ; delete out_WRITE_QUEUE_OUT_ADDRESS ; + delete out_WRITE_QUEUE_OUT_DATA ; delete [] out_GPR_WRITE_VAL ; delete [] in_GPR_WRITE_ACK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h (revision 88) @@ -26,29 +26,29 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_queue ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _nb_bypass_write ; + public : uint32_t _size_queue ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; + public : uint32_t _nb_general_register ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_special_register ; + public : uint32_t _nb_bypass_write ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_spr_write ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; //-----[ methods ]----------------------------------------------------------- @@ -62,13 +62,16 @@ uint32_t size_special_data , uint32_t nb_special_register, - uint32_t nb_bypass_write ); - public : Parameters (Parameters & param) ; + uint32_t nb_bypass_write , + bool is_toplevel=false ); +//public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); - public : std::string print (uint32_t depth); - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters & x); + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h (revision 88) @@ -100,4 +100,5 @@ public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_NO_SEQUENCE ; public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; + public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_DATA ; // -----[ Interface "gpr_write" ]------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp (revision 88) @@ -29,73 +29,90 @@ uint32_t size_special_data , uint32_t nb_special_register, - uint32_t nb_bypass_write ): - _size_queue (size_queue ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _nb_general_register (nb_general_register), - _size_special_data (size_special_data ), - _nb_special_register (nb_special_register), - _nb_bypass_write (nb_bypass_write ), - - _nb_gpr_write (1), - _nb_spr_write (1), - - _size_context_id (log2(_nb_context )), - _size_front_end_id (log2(_nb_front_end )), - _size_ooo_engine_id (log2(_nb_ooo_engine )), - _size_packet_id (log2(_nb_packet )), - _size_general_register (log2(_nb_general_register)), - _size_special_register (log2(_nb_special_register)), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0) + uint32_t nb_bypass_write , + bool is_toplevel) { log_printf(FUNC,Write_queue,FUNCTION,"Begin"); + + _size_queue = size_queue ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register; + _nb_special_register = nb_special_register; + _nb_bypass_write = nb_bypass_write ; + + _nb_gpr_write = 1; + _nb_spr_write = 1; + test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context ); + _size_front_end_id = log2(_nb_front_end ); + _size_ooo_engine_id = log2(_nb_ooo_engine ); + _size_rob_ptr = log2(_nb_packet ); + _size_general_register = log2(_nb_general_register); + _size_special_register = log2(_nb_special_register); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + + copy(); + } + log_printf(FUNC,Write_queue,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Write_queue::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_queue (param._size_queue ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _nb_general_register (param._nb_general_register ), +// _size_special_data (param._size_special_data ), +// _nb_special_register (param._nb_special_register ), +// _nb_bypass_write (param._nb_bypass_write ), + +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), + +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), + +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id), +// _have_port_packet_id (param._have_port_packet_id ) +// { +// log_printf(FUNC,Write_queue,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Write_queue,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Write_queue::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_queue (param._size_queue ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _nb_general_register (param._nb_general_register ), - _size_special_data (param._size_special_data ), - _nb_special_register (param._nb_special_register ), - _nb_bypass_write (param._nb_bypass_write ), - - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ) +#define FUNCTION "Write_queue::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Write_queue,FUNCTION,"Begin"); - test(); log_printf(FUNC,Write_queue,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Write_queue::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Write_queue::copy" + void Parameters::copy (void) { log_printf(FUNC,Write_queue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue.cpp (revision 88) @@ -39,9 +39,15 @@ log_printf(FUNC,Write_queue,FUNCTION,"Begin"); +#if DEBUG_Write_queue == true + log_printf(INFO,Write_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Write_queue,FUNCTION,"Allocation"); allocation (); #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Write_queue,FUNCTION,"Allocation of statistics"); @@ -52,5 +58,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -62,5 +68,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Write_queue,FUNCTION,"Method - transition"); @@ -96,5 +102,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Write_queue,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 88) @@ -58,5 +58,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -81,5 +81,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); // ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -88,4 +88,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } @@ -129,5 +130,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Write_queue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -38,5 +38,5 @@ if (_param->_have_port_ooo_engine_id) delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) delete in_WRITE_QUEUE_IN_PACKET_ID ; // delete in_WRITE_QUEUE_IN_OPERATION ; @@ -61,5 +61,5 @@ if (_param->_have_port_ooo_engine_id) delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) delete out_WRITE_QUEUE_OUT_PACKET_ID ; // delete out_WRITE_QUEUE_OUT_OPERATION ; @@ -69,4 +69,5 @@ delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ; delete out_WRITE_QUEUE_OUT_ADDRESS ; + delete out_WRITE_QUEUE_OUT_DATA ; // -----[ Interface "gpr_write" ]------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_genMoore.cpp (revision 88) @@ -49,5 +49,5 @@ if (_param->_have_port_ooo_engine_id) PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID , _queue->front()->_packet_id ); // PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION , _queue->front()->_operation ); @@ -57,4 +57,5 @@ PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE , _queue->front()->_no_sequence ); PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS , _queue->front()->_address ); + PORT_WRITE(out_WRITE_QUEUE_OUT_DATA , _queue->front()->_data_rd ); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 88) @@ -51,5 +51,5 @@ (_param->_have_port_front_end_id )?PORT_READ(in_WRITE_QUEUE_IN_FRONT_END_ID ):0, (_param->_have_port_ooo_engine_id)?PORT_READ(in_WRITE_QUEUE_IN_OOO_ENGINE_ID):0, - (_param->_have_port_packet_id )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, + (_param->_have_port_rob_ptr )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, //PORT_READ(in_WRITE_QUEUE_IN_OPERATION ), PORT_READ(in_WRITE_QUEUE_IN_TYPE ), @@ -83,5 +83,6 @@ #ifdef STATISTICS - *(_stat_use_queue) += _queue->size(); + if (usage_is_set(_usage,USE_STATISTICS)) + *(_stat_use_queue) += _queue->size(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Parameters.h (revision 88) @@ -28,31 +28,31 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _size_write_queue ; - public : const uint32_t _size_execute_queue ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _nb_bypass_write ; + public : uint32_t _size_write_queue ; + public : uint32_t _size_execute_queue ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; + public : uint32_t _nb_general_register ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_special_register ; + public : uint32_t _nb_bypass_write ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_spr_write ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : const bool _have_component_execute_queue ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; + public : bool _have_component_execute_queue ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue ::Parameters * _param_write_queue; @@ -70,7 +70,10 @@ uint32_t size_special_data , uint32_t nb_special_register, - uint32_t nb_bypass_write ); - public : Parameters (Parameters & param) ; + uint32_t nb_bypass_write , + bool is_toplevel=false); +//public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h (revision 88) @@ -95,4 +95,5 @@ public : SC_OUT(Tcontrol_t ) * out_WRITE_UNIT_OUT_NO_SEQUENCE ; public : SC_OUT(Tgeneral_data_t ) * out_WRITE_UNIT_OUT_ADDRESS ; + public : SC_OUT(Tgeneral_data_t ) * out_WRITE_UNIT_OUT_DATA ; // -----[ Interface "gpr_write" ]------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp (revision 88) @@ -29,103 +29,111 @@ uint32_t size_special_data , uint32_t nb_special_register, - uint32_t nb_bypass_write ): - _size_write_queue (size_write_queue ), - _size_execute_queue (size_execute_queue ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _nb_general_register (nb_general_register), - _size_special_data (size_special_data ), - _nb_special_register (nb_special_register), - _nb_bypass_write (nb_bypass_write ), - - _nb_gpr_write (1), - _nb_spr_write (1), - - _size_context_id (log2(_nb_context )), - _size_front_end_id (log2(_nb_front_end )), - _size_ooo_engine_id (log2(_nb_ooo_engine )), - _size_packet_id (log2(_nb_packet )), - _size_general_register (log2(_nb_general_register)), - _size_special_register (log2(_nb_special_register)), - - _have_component_execute_queue (_size_execute_queue > 0), - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0) + uint32_t nb_bypass_write , + bool is_toplevel ) { log_printf(FUNC,Write_unit,FUNCTION,"Begin"); - _param_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue ::Parameters(size_write_queue , - nb_context , - nb_front_end , - nb_ooo_engine , - nb_packet , - size_general_data , - nb_general_register, - size_special_data , - nb_special_register, - nb_bypass_write ); + _size_write_queue = size_write_queue ; + _size_execute_queue = size_execute_queue ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register; + _nb_special_register = nb_special_register; + _nb_bypass_write = nb_bypass_write ; + + _nb_gpr_write = 1; + _nb_spr_write = 1; + + _have_component_execute_queue = _size_execute_queue > 0; + + _param_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue ::Parameters(_size_write_queue , + _nb_context , + _nb_front_end , + _nb_ooo_engine , + _nb_packet , + size_general_data , + _nb_general_register, + size_special_data , + _nb_special_register, + _nb_bypass_write ); if (_have_component_execute_queue) - _param_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Parameters(size_execute_queue , - nb_context , - nb_front_end , - nb_ooo_engine , - nb_packet , - size_general_data , - size_special_data ); + _param_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Parameters(_size_execute_queue , + _nb_context , + _nb_front_end , + _nb_ooo_engine , + _nb_packet , + size_general_data , + size_special_data ); test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context ); + _size_front_end_id = log2(_nb_front_end ); + _size_ooo_engine_id = log2(_nb_ooo_engine ); + _size_rob_ptr = log2(_nb_packet ); + _size_general_register = log2(_nb_general_register); + _size_special_register = log2(_nb_special_register); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + + copy(); + } log_printf(FUNC,Write_unit,FUNCTION,"End"); }; -#undef FUNCTION -#define FUNCTION "Write_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_write_queue (param._size_write_queue ), - _size_execute_queue (param._size_execute_queue ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _nb_general_register (param._nb_general_register ), - _size_special_data (param._size_special_data ), - _nb_special_register (param._nb_special_register ), - _nb_bypass_write (param._nb_bypass_write ), +// #undef FUNCTION +// #define FUNCTION "Write_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_write_queue (param._size_write_queue ), +// _size_execute_queue (param._size_execute_queue ), +// _nb_context (param._nb_context ), +// _nb_front_end (param._nb_front_end ), +// _nb_ooo_engine (param._nb_ooo_engine ), +// _nb_packet (param._nb_packet ), +// _size_general_data (param._size_general_data ), +// _nb_general_register (param._nb_general_register ), +// _size_special_data (param._size_special_data ), +// _nb_special_register (param._nb_special_register ), +// _nb_bypass_write (param._nb_bypass_write ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), +// _size_context_id (param._size_context_id ), +// _size_front_end_id (param._size_front_end_id ), +// _size_ooo_engine_id (param._size_ooo_engine_id ), +// _size_packet_id (param._size_packet_id ), +// _size_general_register (param._size_general_register ), +// _size_special_register (param._size_special_register ), - _have_component_execute_queue (param._have_component_execute_queue), - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id ), - _have_port_packet_id (param._have_port_packet_id ) - { - log_printf(FUNC,Write_unit,FUNCTION,"Begin"); +// _have_component_execute_queue (param._have_component_execute_queue), +// _have_port_context_id (param._have_port_context_id ), +// _have_port_front_end_id (param._have_port_front_end_id ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id ), +// _have_port_packet_id (param._have_port_packet_id ) +// { +// log_printf(FUNC,Write_unit,FUNCTION,"Begin"); - _param_write_queue = param._param_write_queue ; - _param_execute_queue = param._param_execute_queue; +// _param_write_queue = param._param_write_queue ; +// _param_execute_queue = param._param_execute_queue; - test(); - log_printf(FUNC,Write_unit,FUNCTION,"End"); - }; +// test(); +// log_printf(FUNC,Write_unit,FUNCTION,"End"); +// }; #undef FUNCTION #define FUNCTION "Write_unit::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) { log_printf(FUNC,Write_unit,FUNCTION,"Begin"); @@ -139,4 +147,17 @@ }; +#undef FUNCTION +#define FUNCTION "Write_unit::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Write_unit,FUNCTION,"Begin"); + + COPY(_param_write_queue); + if (_have_component_execute_queue) + COPY(_param_execute_queue); + + log_printf(FUNC,Write_unit,FUNCTION,"End"); + }; + }; // end namespace write_unit }; // end namespace multi_write_unit @@ -144,5 +165,4 @@ }; // end namespace multi_execute_loop }; // end namespace core - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Write_unit,FUNCTION,"Begin"); +#if DEBUG_Write_unit == true + log_printf(INFO,Write_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Write_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Write_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Write_unit,FUNCTION,"Method - transition"); @@ -90,5 +96,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Write_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 88) @@ -23,9 +23,9 @@ void Write_unit::allocation ( #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics + morpheo::behavioural::Parameters_Statistics * param_statistics #else - void -#endif - ) + void +#endif + ) { log_printf(FUNC,Write_unit,FUNCTION,"Begin"); @@ -34,9 +34,9 @@ Entity * entity = _component->set_entity (_name - ,"Write_unit" -#ifdef POSITION - ,COMBINATORY -#endif - ); + ,"Write_unit" +#ifdef POSITION + ,COMBINATORY +#endif + ); _interfaces = entity->set_interfaces(); @@ -46,9 +46,9 @@ Interface * interface = _interfaces->set_interface("" #ifdef POSITION - ,IN - ,SOUTH, - "Generalist interface" -#endif - ); + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); @@ -64,5 +64,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -87,5 +87,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); // ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -94,4 +94,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } @@ -138,18 +139,19 @@ { name = _name+"_write_queue"; - + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + component_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue - (name.c_str() + (name.c_str() #ifdef STATISTICS - ,param_statistics -#endif - ,_param->_param_write_queue - ,_usage); + ,param_statistics +#endif + ,_param->_param_write_queue + ,_usage); _component->set_component (component_write_queue->_component #ifdef POSITION - , 50, 50, 10, 10 -#endif - ); + , 50, 50, 10, 10 +#endif + ); } @@ -157,18 +159,19 @@ { name = _name+"_execute_queue"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); component_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue - (name.c_str() + (name.c_str() #ifdef STATISTICS - ,param_statistics -#endif - ,_param->_param_execute_queue - ,_usage); + ,param_statistics +#endif + ,_param->_param_execute_queue + ,_usage); _component->set_component (component_execute_queue->_component #ifdef POSITION - , 50, 50, 10, 10 -#endif - ); + , 50, 50, 10, 10 +#endif + ); } @@ -176,9 +179,9 @@ { name = _name+"_write_queue"; - std::cout << "Instance : " << name << std::endl; - + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str()); + #ifdef POSITION _component->interface_map (name ,"", - _name,""); + _name,""); #endif @@ -189,5 +192,5 @@ #ifdef POSITION _component->interface_map (name ,"write_queue_in", - _name,"write_unit_in"); + _name,"write_unit_in"); #endif @@ -200,5 +203,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" ); //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" ); @@ -216,118 +219,120 @@ if (_param->_have_component_execute_queue) - { -#ifdef POSITION - _component->interface_map (name ,"write_queue_out", - _name+"_execute_queue", "execute_queue_in"); -#endif - - _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL" ); - _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK" ); - if (_param->_have_port_context_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID" ); - //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION" ); - //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS" ); - } + { +#ifdef POSITION + _component->interface_map (name ,"write_queue_out", + _name+"_execute_queue", "execute_queue_in"); +#endif + + _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL" ); + _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK" ); + if (_param->_have_port_context_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" ); + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr) + _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID" ); + //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION" ); + //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_DATA" ); + } else - { -#ifdef POSITION - _component->interface_map (name ,"write_queue_out", - _name,"write_unit_out"); -#endif - - _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); - _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); - if (_param->_have_port_context_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); - //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); - //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); - _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); - } + { +#ifdef POSITION + _component->interface_map (name ,"write_queue_out", + _name,"write_unit_out"); +#endif + + _component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); + _component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); + if (_param->_have_port_context_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr) + _component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); + //_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); + //_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); + _component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" ); + } for (uint32_t i=0; i<_param->_nb_gpr_write; i++) - { -#ifdef POSITION - _component->interface_map (name ,"gpr_write_"+toString(i), - _name,"gpr_write_"+toString(i)); -#endif - - _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL" ); - _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK" ); - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); - _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ); - _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA" ); - } + { +#ifdef POSITION + _component->interface_map (name ,"gpr_write_"+toString(i), + _name,"gpr_write_"+toString(i)); +#endif + + _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL" ); + _component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); + _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ); + _component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA" ); + } for (uint32_t i=0; i<_param->_nb_spr_write; i++) - { -#ifdef POSITION - _component->interface_map (name ,"spr_write_"+toString(i), - _name,"spr_write_"+toString(i)); -#endif - - _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL" ); - _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK" ); - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); - _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ); - _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA" ); - } + { +#ifdef POSITION + _component->interface_map (name ,"spr_write_"+toString(i), + _name,"spr_write_"+toString(i)); +#endif + + _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL" ); + _component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); + _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ); + _component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA" ); + } for (uint32_t i=0; i<_param->_nb_bypass_write; i++) - { -#ifdef POSITION - _component->interface_map (name ,"bypass_write_"+toString(i), - _name,"bypass_write_"+toString(i)); -#endif - - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ); - _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ); - } + { +#ifdef POSITION + _component->interface_map (name ,"bypass_write_"+toString(i), + _name,"bypass_write_"+toString(i)); +#endif + + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ); + _component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ); + } } if (_param->_have_component_execute_queue) { - name = _name+"_execute_queue"; - std::cout << "Instance : " << name << std::endl; - -#ifdef POSITION - _component->interface_map (name ,"", - _name,""); -#endif - - _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK"); - _component->port_map(name,"in_NRESET", _name, "in_NRESET"); - - -#ifdef POSITION - _component->interface_map (name ,"execute_queue_in", - _name+"_write_queue","write_queue_in"); + name = _name+"_execute_queue"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str()); + +#ifdef POSITION + _component->interface_map (name ,"", + _name,""); +#endif + + _component->port_map(name,"in_CLOCK" , _name, "in_CLOCK"); + _component->port_map(name,"in_NRESET", _name, "in_NRESET"); + + +#ifdef POSITION + _component->interface_map (name ,"execute_queue_in", + _name+"_write_queue","write_queue_in"); #endif @@ -340,5 +345,5 @@ if (_param->_have_port_ooo_engine_id) _component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) _component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID" ); //_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION" ); @@ -348,30 +353,33 @@ _component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE" ); _component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS" ); - -#ifdef POSITION - _component->interface_map (name ,"execute_queue_out", - _name,"write_unit_out"); -#endif - - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); - _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); - if (_param->_have_port_context_id) - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); - //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); - //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); - _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); + _component->port_map(name, "in_EXECUTE_QUEUE_IN_DATA" , _name+"_write_queue","out_WRITE_QUEUE_OUT_DATA" ); + +#ifdef POSITION + _component->interface_map (name ,"execute_queue_out", + _name,"write_unit_out"); +#endif + + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" ); + _component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" ); + if (_param->_have_port_context_id) + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" ); + if (_param->_have_port_ooo_engine_id) + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr) + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" ); + //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" ); + //_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" ); + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" ); + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" ); + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ); + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" ); + _component->port_map(name,"out_EXECUTE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" ); } #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Write_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -37,5 +37,5 @@ if (_param->_have_port_ooo_engine_id) delete in_WRITE_UNIT_IN_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete in_WRITE_UNIT_IN_PACKET_ID ; // delete in_WRITE_UNIT_IN_OPERATION ; @@ -60,5 +60,5 @@ if (_param->_have_port_ooo_engine_id) delete out_WRITE_UNIT_OUT_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr) delete out_WRITE_UNIT_OUT_PACKET_ID ; // delete out_WRITE_UNIT_OUT_OPERATION ; @@ -68,4 +68,5 @@ delete out_WRITE_UNIT_OUT_NO_SEQUENCE ; delete out_WRITE_UNIT_OUT_ADDRESS ; + delete out_WRITE_UNIT_OUT_DATA ; // -----[ Interface "gpr_write" ]------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Execution_unit_to_Write_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_min.cfg (revision 88) @@ -1,4 +1,6 @@ Execution_unit_to_Write_unit 2 2 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] 1 1 *2 # nb_write_unit 1 1 *2 # nb_context @@ -11,5 +13,5 @@ 16 16 *2 # nb_special_register 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -1 1 +1 # table_routing [1][0] +1 1 +1 # table_routing [0][0][0] +1 1 +1 # table_routing [1][0][0] 1 1 +1 # table_execute_thread [0][0] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-mono_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-mono_thread.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-mono_thread.cfg (revision 88) @@ -1,4 +1,8 @@ Execution_unit_to_Write_unit 4 4 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [3] [nb_execute_unit] 3 3 *2 # nb_write_unit 1 1 *2 # nb_context @@ -11,16 +15,16 @@ 16 16 *2 # nb_special_register 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -0 0 +1 # table_routing [0][1] -0 0 +1 # table_routing [0][2] -0 0 +1 # table_routing [1][0] -1 1 +1 # table_routing [1][1] -1 1 +1 # table_routing [1][2] -0 0 +1 # table_routing [2][0] -0 0 +1 # table_routing [2][1] -1 1 +1 # table_routing [2][2] -1 1 +1 # table_routing [3][0] -1 1 +1 # table_routing [3][1] -1 1 +1 # table_routing [3][2] +1 1 +1 # table_routing [0][0][0] +0 0 +1 # table_routing [0][1][0] +0 0 +1 # table_routing [0][2][0] +0 0 +1 # table_routing [1][0][0] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][2][0] +0 0 +1 # table_routing [2][0][0] +0 0 +1 # table_routing [2][1][0] +1 1 +1 # table_routing [2][2][0] +1 1 +1 # table_routing [3][0][0] +1 1 +1 # table_routing [3][1][0] +1 1 +1 # table_routing [3][2][0] 1 1 +1 # table_thread [0][0] 1 1 +1 # table_thread [1][0] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread-multi_port.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread-multi_port.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread-multi_port.cfg (revision 88) @@ -0,0 +1,52 @@ +Execution_unit_to_Write_unit +4 4 *2 # nb_execute_unit +2 2 +1 # nb_execute_unit_port [0] [nb_execute_unit] +3 3 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +2 2 +1 # nb_execute_unit_port [3] [nb_execute_unit] +3 3 *2 # nb_write_unit +2 2 *2 # nb_context +2 2 *2 # nb_front_end +1 1 *2 # nb_ooo_engine +64 64 *2 # nb_packet +32 32 *2 # size_general_data +2 2 *2 # size_special_data +64 64 *2 # nb_general_register +16 16 *2 # nb_special_register +0 1 +1 # priority +1 1 +1 # table_routing [0][0][0] +1 1 +1 # table_routing [0][0][1] +0 0 +1 # table_routing [0][0][2] +0 0 +1 # table_routing [0][1][0] +1 1 +1 # table_routing [0][1][1] +0 0 +1 # table_routing [0][1][2] +0 0 +1 # table_routing [1][0][0] +1 1 +1 # table_routing [1][0][1] +0 0 +1 # table_routing [1][0][2] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][1][1] +1 1 +1 # table_routing [1][1][2] +1 1 +1 # table_routing [1][2][0] +1 1 +1 # table_routing [1][2][1] +1 1 +1 # table_routing [1][2][2] +0 0 +1 # table_routing [2][0][0] +0 0 +1 # table_routing [2][0][1] +1 1 +1 # table_routing [2][0][2] +1 1 +1 # table_routing [3][0][0] +1 1 +1 # table_routing [3][0][1] +1 1 +1 # table_routing [3][0][2] +1 1 +1 # table_routing [3][1][0] +1 1 +1 # table_routing [3][1][1] +1 1 +1 # table_routing [3][1][2] +1 1 +1 # table_thread [0][0] +0 0 +1 # table_thread [0][1] +0 0 +1 # table_thread [0][2] +0 0 +1 # table_thread [0][3] +0 0 +1 # table_thread [1][0] +1 1 +1 # table_thread [1][1] +1 1 +1 # table_thread [1][2] +0 0 +1 # table_thread [1][3] +0 0 +1 # table_thread [2][0] +0 0 +1 # table_thread [2][1] +0 0 +1 # table_thread [2][2] +1 1 +1 # table_thread [2][3] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/config_multi_execute-multi_thread.cfg (revision 88) @@ -1,4 +1,8 @@ Execution_unit_to_Write_unit 4 4 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [3] [nb_execute_unit] 3 3 *2 # nb_write_unit 2 2 *2 # nb_context @@ -11,16 +15,16 @@ 16 16 *2 # nb_special_register 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -0 0 +1 # table_routing [0][1] -0 0 +1 # table_routing [0][2] -0 0 +1 # table_routing [1][0] -1 1 +1 # table_routing [1][1] -1 1 +1 # table_routing [1][2] -0 0 +1 # table_routing [2][0] -0 0 +1 # table_routing [2][1] -1 1 +1 # table_routing [2][2] -1 1 +1 # table_routing [3][0] -1 1 +1 # table_routing [3][1] -1 1 +1 # table_routing [3][2] +1 1 +1 # table_routing [0][0][0] +0 0 +1 # table_routing [0][1][0] +0 0 +1 # table_routing [0][2][0] +0 0 +1 # table_routing [1][0][0] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][2][0] +0 0 +1 # table_routing [2][0][0] +0 0 +1 # table_routing [2][1][0] +1 1 +1 # table_routing [2][2][0] +1 1 +1 # table_routing [3][0][0] +1 1 +1 # table_routing [3][1][0] +1 1 +1 # table_routing [3][2][0] 1 1 +1 # table_thread [0][0] 0 0 +1 # table_thread [0][1] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/include/test.h (revision 88) @@ -15,6 +15,10 @@ #include +#define NB_ITERATION 1 +#define CYCLE_MAX (128*NB_ITERATION) + #include "Common/include/Time.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h" +#include "Common/include/Test.h" using namespace std; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/main.cpp (revision 88) @@ -14,17 +14,18 @@ err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); - err (_(" * nb_execute_unit (uint32_t)\n")); - err (_(" * nb_write_unit (uint32_t)\n")); - err (_(" * nb_context (uint32_t)\n")); - err (_(" * nb_front_end (uint32_t)\n")); - err (_(" * nb_ooo_engine (uint32_t)\n")); - err (_(" * nb_packet (uint32_t)\n")); - err (_(" * size_general_data (uint32_t)\n")); - err (_(" * size_special_data (uint32_t)\n")); - err (_(" * nb_general_register (uint32_t)\n")); - err (_(" * nb_special_register (uint32_t)\n")); - err (_(" * priority (uint32_t)\n")); - err (_(" * table_routing [nb_execute_unit][nb_write_unit] (bool )\n")); - err (_(" * table_thread [nb_write_unit][nb_thread] (bool )\n")); + err (_(" * nb_execute_unit (uint32_t)\n")); + err (_(" * nb_execute_unit_port [nb_execute_unit] (uint32_t)\n")); + err (_(" * nb_write_unit (uint32_t)\n")); + err (_(" * nb_context (uint32_t)\n")); + err (_(" * nb_front_end (uint32_t)\n")); + err (_(" * nb_ooo_engine (uint32_t)\n")); + err (_(" * nb_packet (uint32_t)\n")); + err (_(" * size_general_data (uint32_t)\n")); + err (_(" * size_special_data (uint32_t)\n")); + err (_(" * nb_general_register (uint32_t)\n")); + err (_(" * nb_special_register (uint32_t)\n")); + err (_(" * priority (uint32_t)\n")); + err (_(" * table_routing [nb_execute_unit][nb_execute_unit_port][nb_write_unit] (bool )\n")); + err (_(" * table_thread [nb_write_unit][nb_thread] (bool )\n")); exit (1); @@ -43,30 +44,46 @@ const string name = argv[x++]; - uint32_t _nb_execute_unit = atoi(argv[x++]); - uint32_t _nb_write_unit = atoi(argv[x++]); - uint32_t _nb_context = atoi(argv[x++]); - uint32_t _nb_front_end = atoi(argv[x++]); - uint32_t _nb_ooo_engine = atoi(argv[x++]); - uint32_t _nb_packet = atoi(argv[x++]); - uint32_t _size_general_data = atoi(argv[x++]); - uint32_t _size_special_data = atoi(argv[x++]); - uint32_t _nb_general_register = atoi(argv[x++]); - uint32_t _nb_special_register = atoi(argv[x++]); + uint32_t _nb_execute_unit = fromString(argv[x++]); + + if (static_cast(argc) <= 2+NB_PARAMS+_nb_execute_unit) + usage (argc, argv); + + uint32_t _sum_execute_unit_port = 0; + uint32_t * _nb_execute_unit_port = new uint32_t [_nb_execute_unit]; + for (uint32_t i=0; i<_nb_execute_unit; i++) + { + _nb_execute_unit_port [i] = fromString(argv[x++]); + _sum_execute_unit_port += _nb_execute_unit_port [i]; + } + + uint32_t _nb_write_unit = fromString(argv[x++]); + uint32_t _nb_context = fromString(argv[x++]); + uint32_t _nb_front_end = fromString(argv[x++]); + uint32_t _nb_ooo_engine = fromString(argv[x++]); + uint32_t _nb_packet = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + uint32_t _nb_general_register = fromString(argv[x++]); + uint32_t _nb_special_register = fromString(argv[x++]); Tpriority_t _priority = fromString(argv[x++]); uint32_t _nb_thread = get_nb_thread(_nb_context, _nb_front_end, _nb_ooo_engine); - if (static_cast(argc) != 2+NB_PARAMS+(_nb_write_unit*_nb_execute_unit)+(_nb_write_unit*_nb_thread)) + if (static_cast(argc) != 2+NB_PARAMS+_nb_execute_unit+(_nb_write_unit*_sum_execute_unit_port)+(_nb_write_unit*_nb_thread)) usage (argc, argv); - bool ** _table_routing; - bool ** _table_thread ; + bool *** _table_routing; + bool ** _table_thread ; - _table_routing = new bool * [_nb_execute_unit]; + _table_routing = new bool ** [_nb_execute_unit]; for (uint32_t i=0; i<_nb_execute_unit; i++) { - _table_routing [i] = new bool [_nb_write_unit]; - for (uint32_t j=0; j<_nb_write_unit; j++) - _table_routing [i][j] = atoi(argv[x++]); + _table_routing [i] = new bool * [_nb_execute_unit_port [i]]; + for (uint32_t j=0; j<_nb_execute_unit_port [i]; j++) + { + _table_routing [i][j] = new bool [_nb_write_unit]; + for (uint32_t k=0; k<_nb_write_unit; k++) + _table_routing [i][j][k] = fromString(argv[x++]); + } } @@ -77,11 +94,13 @@ for (uint32_t j=0; j<_nb_thread; j++) - _table_thread [i][j] = atoi(argv[x++]); + _table_thread [i][j] = fromString(argv[x++]); } + int _return = EXIT_SUCCESS; try { morpheo::behavioural::core::multi_execute_loop::execute_loop::network::execution_unit_to_write_unit::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::execution_unit_to_write_unit::Parameters (_nb_execute_unit , + _nb_execute_unit_port , _nb_write_unit , _nb_context , @@ -95,8 +114,9 @@ _priority , _table_routing , - _table_thread + _table_thread , + true //is_toplevel ); - msg(_("%s"),param->print(1).c_str()); + msg(_("%s"),param->print(0).c_str()); test (name,param); @@ -104,11 +124,19 @@ catch (morpheo::ErrorMorpheo & error) { - msg (_("<%s> : %s.\n"),name.c_str(), error.what ()); - exit (EXIT_FAILURE); + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; } - catch (...) + + try { - err (_("<%s> : This test must generate a error.\n"),name.c_str()); - exit (EXIT_FAILURE); + if (_return == EXIT_SUCCESS) + TEST_OK("Execution_unit_to_Write_unit : no error"); + else + TEST_KO("Execution_unit_to_Write_unit : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp (revision 88) @@ -7,9 +7,5 @@ */ -#define NB_ITERATION 1 -#define CYCLE_MAX (128*NB_ITERATION) - #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/include/test.h" -#include "Common/include/Test.h" #include "Common/include/BitManipulation.h" #include "Behavioural/include/Allocation.h" @@ -78,4 +74,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Execution_unit_to_Write_unit * _Execution_unit_to_Write_unit = new Execution_unit_to_Write_unit (name.c_str(), @@ -84,5 +90,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -95,21 +101,22 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_VAL ," in_EXECUTE_UNIT_OUT_VAL ",Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_OUT_ACK ,"out_EXECUTE_UNIT_OUT_ACK ",Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_CONTEXT_ID ," in_EXECUTE_UNIT_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_FRONT_END_ID ," in_EXECUTE_UNIT_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID," in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID",Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ," in_EXECUTE_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_execute_unit); -//ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ," in_EXECUTE_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ," in_EXECUTE_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ," in_EXECUTE_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ," in_EXECUTE_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RD ," in_EXECUTE_UNIT_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RE ," in_EXECUTE_UNIT_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RE ," in_EXECUTE_UNIT_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RE ," in_EXECUTE_UNIT_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION ," in_EXECUTE_UNIT_OUT_EXCEPTION ",Texception_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ," in_EXECUTE_UNIT_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_unit); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_VAL ," in_EXECUTE_UNIT_OUT_VAL ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_OUT_ACK ,"out_EXECUTE_UNIT_OUT_ACK ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_CONTEXT_ID ," in_EXECUTE_UNIT_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_FRONT_END_ID ," in_EXECUTE_UNIT_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID," in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID",Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ," in_EXECUTE_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ," in_EXECUTE_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ," in_EXECUTE_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ," in_EXECUTE_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ," in_EXECUTE_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RD ," in_EXECUTE_UNIT_OUT_DATA_RD ",Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RE ," in_EXECUTE_UNIT_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RE ," in_EXECUTE_UNIT_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RE ," in_EXECUTE_UNIT_OUT_DATA_RE ",Tspecial_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION ," in_EXECUTE_UNIT_OUT_EXCEPTION ",Texception_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ," in_EXECUTE_UNIT_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_VAL ,"out_WRITE_UNIT_IN_VAL ",Tcontrol_t ,_param->_nb_write_unit ); ALLOC1_SC_SIGNAL( in_WRITE_UNIT_IN_ACK ," in_WRITE_UNIT_IN_ACK ",Tcontrol_t ,_param->_nb_write_unit ); @@ -139,25 +146,25 @@ (*(_Execution_unit_to_Write_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_VAL ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_EXECUTE_UNIT_OUT_ACK ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_VAL ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit,out_EXECUTE_UNIT_OUT_ACK ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_context_id) - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_CONTEXT_ID ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_CONTEXT_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_front_end_id) - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_FRONT_END_ID ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_FRONT_END_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_ooo_engine_id) - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID,_param->_nb_execute_unit); - if (_param->_have_port_packet_id) - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit); -//INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_DATA_RD ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_DATA_RE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_EXCEPTION ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_ADDRESS ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_DATA_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_DATA_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_EXCEPTION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_ADDRESS ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_VAL ,_param->_nb_write_unit ); @@ -169,5 +176,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_OOO_ENGINE_ID ,_param->_nb_write_unit ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); //INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); @@ -201,14 +208,16 @@ const int32_t percent_transaction_out = 75; - set execute_unit_thread [_param->_nb_execute_unit]; + set execute_unit_thread [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port]; for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - for (uint32_t j=0; j<_param->_nb_write_unit; j++) - if (_param->_table_routing[i][j]) - for (uint32_t k=0; k<_param->_nb_thread; k++) - if (_param->_table_thread[j][k]) - { - execute_unit_thread [i].insert(k); - } + for (uint32_t ii=0; ii<_param->_nb_execute_unit_port[i]; ii++) + for (uint32_t j=0; j<_param->_nb_write_unit; j++) + if (_param->_table_routing[i][ii][j]) + for (uint32_t k=0; k<_param->_nb_thread; k++) + if (_param->_table_thread[j][k]) + { + execute_unit_thread [i][ii].insert(k); + } + SC_START(0); LABEL("Initialisation"); @@ -225,49 +234,50 @@ LABEL("Iteration %d",iteration); - list request [_param->_nb_execute_unit]; + list request [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port]; uint32_t nb_request_in; for (nb_request_in=0; nb_request_in < _param->_nb_packet; ) for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - if (nb_request_in >= _param->_nb_packet) - break; - - Tcontext_t context_id ; - Tcontext_t front_end_id ; - Tcontext_t ooo_engine_id; - Tcontext_t num_thread ; - - // Find compatible thread - do - { - context_id = range (rand(), _param->_size_context_id ); - front_end_id = range (rand(), _param->_size_front_end_id ); - ooo_engine_id = range (rand(), _param->_size_ooo_engine_id); - num_thread = get_num_thread (context_id , _param->_size_context_id , - front_end_id , _param->_size_front_end_id , - ooo_engine_id, _param->_size_ooo_engine_id); - } - while (execute_unit_thread[i].find(num_thread) == execute_unit_thread[i].end()); - - request[i].push_back(entry_t (context_id , - front_end_id , - ooo_engine_id, - nb_request_in, - //range (rand(), _param->_size_operation ), - range (rand(), _param->_size_type ), - range (rand(), 2 ), - range (rand(), _param->_size_general_register), - range (rand(), _param->_size_general_data ), - range (rand(), 2 ), - range (rand(), _param->_size_special_register), - range (rand(), _param->_size_special_data ), - range (rand(), _param->_size_exception ), - range (rand(), 2 ), - range (rand(), _param->_size_general_data ) - )); - - nb_request_in++; - } + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + if (nb_request_in >= _param->_nb_packet) + break; + + Tcontext_t context_id ; + Tcontext_t front_end_id ; + Tcontext_t ooo_engine_id; + Tcontext_t num_thread ; + + // Find compatible thread + do + { + context_id = range (rand(), _param->_size_context_id ); + front_end_id = range (rand(), _param->_size_front_end_id ); + ooo_engine_id = range (rand(), _param->_size_ooo_engine_id); + num_thread = get_num_thread (context_id , _param->_size_context_id , + front_end_id , _param->_size_front_end_id , + ooo_engine_id, _param->_size_ooo_engine_id); + } + while (execute_unit_thread[i][j].find(num_thread) == execute_unit_thread[i][j].end()); + + request[i][j].push_back(entry_t (context_id , + front_end_id , + ooo_engine_id, + nb_request_in, + //range (rand(), _param->_size_operation ), + range (rand(), _param->_size_type ), + range (rand(), 2 ), + range (rand(), _param->_size_general_register), + range (rand(), _param->_size_general_data ), + range (rand(), 2 ), + range (rand(), _param->_size_special_register), + range (rand(), _param->_size_special_data ), + range (rand(), _param->_size_exception ), + range (rand(), 2 ), + range (rand(), _param->_size_general_data ) + )); + + nb_request_in++; + } uint32_t nb_request_out = 0; @@ -276,28 +286,29 @@ { for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - bool val = not request[i].empty() and ((rand()%100) < percent_transaction_in); + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + bool val = not request[i][j].empty() and ((rand()%100) < percent_transaction_in); - in_EXECUTE_UNIT_OUT_VAL [i]->write(val); - - if (val) - { - in_EXECUTE_UNIT_OUT_CONTEXT_ID [i] ->write(request[i].front()._context_id ); - in_EXECUTE_UNIT_OUT_FRONT_END_ID [i] ->write(request[i].front()._front_end_id ); - in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i] ->write(request[i].front()._ooo_engine_id ); - in_EXECUTE_UNIT_OUT_PACKET_ID [i] ->write(request[i].front()._packet_id ); -// in_EXECUTE_UNIT_OUT_OPERATION [i] ->write(request[i].front()._operation ); - in_EXECUTE_UNIT_OUT_TYPE [i] ->write(request[i].front()._type ); - in_EXECUTE_UNIT_OUT_WRITE_RD [i] ->write(request[i].front()._write_rd ); - in_EXECUTE_UNIT_OUT_NUM_REG_RD [i] ->write(request[i].front()._num_reg_rd ); - in_EXECUTE_UNIT_OUT_DATA_RD [i] ->write(request[i].front()._data_rd ); - in_EXECUTE_UNIT_OUT_WRITE_RE [i] ->write(request[i].front()._write_re ); - in_EXECUTE_UNIT_OUT_NUM_REG_RE [i] ->write(request[i].front()._num_reg_re ); - in_EXECUTE_UNIT_OUT_DATA_RE [i] ->write(request[i].front()._data_re ); - in_EXECUTE_UNIT_OUT_EXCEPTION [i] ->write(request[i].front()._exception ); - in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i] ->write(request[i].front()._no_sequence ); - in_EXECUTE_UNIT_OUT_ADDRESS [i] ->write(request[i].front()._address ); - } - } + in_EXECUTE_UNIT_OUT_VAL [i][j]->write(val); + + if (val) + { + in_EXECUTE_UNIT_OUT_CONTEXT_ID [i][j] ->write(request[i][j].front()._context_id ); + in_EXECUTE_UNIT_OUT_FRONT_END_ID [i][j] ->write(request[i][j].front()._front_end_id ); + in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i][j] ->write(request[i][j].front()._ooo_engine_id ); + in_EXECUTE_UNIT_OUT_PACKET_ID [i][j] ->write(request[i][j].front()._packet_id ); +// in_EXECUTE_UNIT_OUT_OPERATION [i][j] ->write(request[i][j].front()._operation ); + in_EXECUTE_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type ); + in_EXECUTE_UNIT_OUT_WRITE_RD [i][j] ->write(request[i][j].front()._write_rd ); + in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j] ->write(request[i][j].front()._num_reg_rd ); + in_EXECUTE_UNIT_OUT_DATA_RD [i][j] ->write(request[i][j].front()._data_rd ); + in_EXECUTE_UNIT_OUT_WRITE_RE [i][j] ->write(request[i][j].front()._write_re ); + in_EXECUTE_UNIT_OUT_NUM_REG_RE [i][j] ->write(request[i][j].front()._num_reg_re ); + in_EXECUTE_UNIT_OUT_DATA_RE [i][j] ->write(request[i][j].front()._data_re ); + in_EXECUTE_UNIT_OUT_EXCEPTION [i][j] ->write(request[i][j].front()._exception ); + in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i][j] ->write(request[i][j].front()._no_sequence ); + in_EXECUTE_UNIT_OUT_ADDRESS [i][j] ->write(request[i][j].front()._address ); + } + } for (uint32_t i=0; i<_param->_nb_write_unit; i++) @@ -307,9 +318,10 @@ for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - if (in_EXECUTE_UNIT_OUT_VAL [i]->read() and out_EXECUTE_UNIT_OUT_ACK [i]->read()) - { - LABEL("EXECUTE_UNIT_OUT [%d] - Transaction accepted",i); - } - + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + if (in_EXECUTE_UNIT_OUT_VAL [i][j]->read() and out_EXECUTE_UNIT_OUT_ACK [i][j]->read()) + { + LABEL("EXECUTE_UNIT_OUT [%d][%d] - Transaction accepted",i,j); + } + for (uint32_t i=0; i<_param->_nb_write_unit; i++) if (out_WRITE_UNIT_IN_VAL [i]->read() and in_WRITE_UNIT_IN_ACK [i]->read()) @@ -318,40 +330,53 @@ nb_request_out ++; - Tpacket_t packet = (_param->_have_port_packet_id)?out_WRITE_UNIT_IN_PACKET_ID[i]->read():0; - LABEL(" * packet : %d",packet); - uint32_t execute_unit; + Tpacket_t packet = (_param->_have_port_rob_ptr )?out_WRITE_UNIT_IN_PACKET_ID[i]->read():0; + LABEL(" * packet : %d",packet); // find execute_unit - for (execute_unit=0; execute_unit<_param->_nb_execute_unit; execute_unit++) - if (packet == ((_param->_have_port_packet_id)?request[execute_unit].front()._packet_id:0)) - break; - - LABEL(" * execute_unit source : %d",execute_unit); - - if (_param->_have_port_packet_id) - TEST(Tcontext_t ,out_WRITE_UNIT_IN_PACKET_ID [i]->read(), request[execute_unit].front()._packet_id ); + uint32_t x = 0; + uint32_t y = 0; + bool find = false; + for (x=0; x<_param->_nb_execute_unit; x++) + { + for (y=0; y<_param->_nb_execute_unit_port[x]; y++) + if (packet == ((_param->_have_port_rob_ptr )?request[x][y].front()._packet_id:0)) + { + find = true; + break; + } + if (find) + break; + } + + LABEL(" * execute_unit source : %d",x); + LABEL(" * execute_unit port : %d",y); + TEST(bool,x<_param->_nb_execute_unit, true); + TEST(bool,y<_param->_nb_execute_unit_port[x],true); + + if (_param->_have_port_rob_ptr ) + TEST(Tpacket_t ,packet , request[x][y].front()._packet_id ); // Authorised link ? execute_unit -> write_unit - TEST(bool, _param->_table_routing[execute_unit][i], true); + TEST(bool, _param->_table_routing[x][y][i], true); if (_param->_have_port_context_id) - TEST(Tcontext_t ,out_WRITE_UNIT_IN_CONTEXT_ID [i]->read(), request[execute_unit].front()._context_id ); + TEST(Tcontext_t ,out_WRITE_UNIT_IN_CONTEXT_ID [i]->read(), request[x][y].front()._context_id ); if (_param->_have_port_front_end_id) - TEST(Tcontext_t ,out_WRITE_UNIT_IN_FRONT_END_ID [i]->read(), request[execute_unit].front()._front_end_id ); + TEST(Tcontext_t ,out_WRITE_UNIT_IN_FRONT_END_ID [i]->read(), request[x][y].front()._front_end_id ); if (_param->_have_port_ooo_engine_id) - TEST(Tcontext_t ,out_WRITE_UNIT_IN_OOO_ENGINE_ID [i]->read(), request[execute_unit].front()._ooo_engine_id ); -// TEST(Toperation_t ,out_WRITE_UNIT_IN_OPERATION [i]->read(), request[execute_unit].front()._operation ); - TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[execute_unit].front()._type ); - TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RD [i]->read(), request[execute_unit].front()._write_rd ); - TEST(Tgeneral_address_t,out_WRITE_UNIT_IN_NUM_REG_RD [i]->read(), request[execute_unit].front()._num_reg_rd ); - TEST(Tgeneral_data_t ,out_WRITE_UNIT_IN_DATA_RD [i]->read(), request[execute_unit].front()._data_rd ); - TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RE [i]->read(), request[execute_unit].front()._write_re ); - TEST(Tspecial_address_t,out_WRITE_UNIT_IN_NUM_REG_RE [i]->read(), request[execute_unit].front()._num_reg_re ); - TEST(Tspecial_data_t ,out_WRITE_UNIT_IN_DATA_RE [i]->read(), request[execute_unit].front()._data_re ); - TEST(Texception_t ,out_WRITE_UNIT_IN_EXCEPTION [i]->read(), request[execute_unit].front()._exception ); - TEST(Tcontrol_t ,out_WRITE_UNIT_IN_NO_SEQUENCE [i]->read(), request[execute_unit].front()._no_sequence ); - TEST(Tgeneral_data_t ,out_WRITE_UNIT_IN_ADDRESS [i]->read(), request[execute_unit].front()._address ); + TEST(Tcontext_t ,out_WRITE_UNIT_IN_OOO_ENGINE_ID [i]->read(), request[x][y].front()._ooo_engine_id ); +// TEST(Toperation_t ,out_WRITE_UNIT_IN_OPERATION [i]->read(), request[x][y].front()._operation ); + TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[x][y].front()._type ); + TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RD [i]->read(), request[x][y].front()._write_rd ); + TEST(Tgeneral_address_t,out_WRITE_UNIT_IN_NUM_REG_RD [i]->read(), request[x][y].front()._num_reg_rd ); + TEST(Tgeneral_data_t ,out_WRITE_UNIT_IN_DATA_RD [i]->read(), request[x][y].front()._data_rd ); + TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RE [i]->read(), request[x][y].front()._write_re ); + TEST(Tspecial_address_t,out_WRITE_UNIT_IN_NUM_REG_RE [i]->read(), request[x][y].front()._num_reg_re ); + TEST(Tspecial_data_t ,out_WRITE_UNIT_IN_DATA_RE [i]->read(), request[x][y].front()._data_re ); + TEST(Texception_t ,out_WRITE_UNIT_IN_EXCEPTION [i]->read(), request[x][y].front()._exception ); + TEST(Tcontrol_t ,out_WRITE_UNIT_IN_NO_SEQUENCE [i]->read(), request[x][y].front()._no_sequence ); + TEST(Tgeneral_data_t ,out_WRITE_UNIT_IN_ADDRESS [i]->read(), request[x][y].front()._address ); - request[execute_unit].pop_front(); + request[x][y].pop_front(); } SC_START(1); @@ -372,39 +397,39 @@ delete in_NRESET; - delete [] in_EXECUTE_UNIT_OUT_VAL ; - delete [] out_EXECUTE_UNIT_OUT_ACK ; - delete [] in_EXECUTE_UNIT_OUT_CONTEXT_ID ; - delete [] in_EXECUTE_UNIT_OUT_FRONT_END_ID ; - delete [] in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID; - delete [] in_EXECUTE_UNIT_OUT_PACKET_ID ; -//delete [] in_EXECUTE_UNIT_OUT_OPERATION ; - delete [] in_EXECUTE_UNIT_OUT_TYPE ; - delete [] in_EXECUTE_UNIT_OUT_WRITE_RD ; - delete [] in_EXECUTE_UNIT_OUT_NUM_REG_RD ; - delete [] in_EXECUTE_UNIT_OUT_DATA_RD ; - delete [] in_EXECUTE_UNIT_OUT_WRITE_RE ; - delete [] in_EXECUTE_UNIT_OUT_NUM_REG_RE ; - delete [] in_EXECUTE_UNIT_OUT_DATA_RE ; - delete [] in_EXECUTE_UNIT_OUT_EXCEPTION ; - delete [] in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; - delete [] in_EXECUTE_UNIT_OUT_ADDRESS ; - - delete [] out_WRITE_UNIT_IN_VAL ; - delete [] in_WRITE_UNIT_IN_ACK ; - delete [] out_WRITE_UNIT_IN_CONTEXT_ID ; - delete [] out_WRITE_UNIT_IN_FRONT_END_ID ; - delete [] out_WRITE_UNIT_IN_OOO_ENGINE_ID ; - delete [] out_WRITE_UNIT_IN_PACKET_ID ; -//delete [] out_WRITE_UNIT_IN_OPERATION ; - delete [] out_WRITE_UNIT_IN_TYPE ; - delete [] out_WRITE_UNIT_IN_WRITE_RD ; - delete [] out_WRITE_UNIT_IN_NUM_REG_RD ; - delete [] out_WRITE_UNIT_IN_DATA_RD ; - delete [] out_WRITE_UNIT_IN_WRITE_RE ; - delete [] out_WRITE_UNIT_IN_NUM_REG_RE ; - delete [] out_WRITE_UNIT_IN_DATA_RE ; - delete [] out_WRITE_UNIT_IN_EXCEPTION ; - delete [] out_WRITE_UNIT_IN_NO_SEQUENCE ; - delete [] out_WRITE_UNIT_IN_ADDRESS ; + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_VAL ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_OUT_ACK ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_CONTEXT_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_FRONT_END_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_VAL ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL( in_WRITE_UNIT_IN_ACK ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_CONTEXT_ID ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_FRONT_END_ID ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_OOO_ENGINE_ID ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); +//DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_DATA_RD ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RE ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RE ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_DATA_RE ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_EXCEPTION ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_NO_SEQUENCE ,_param->_nb_write_unit ); + DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_ADDRESS ,_param->_nb_write_unit ); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h (revision 88) @@ -65,21 +65,21 @@ // ~~~~~[ Interface "execute_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_EXECUTE_UNIT_OUT_VAL ; - public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_UNIT_OUT_ACK ; - public : SC_IN (Tcontext_t ) ** in_EXECUTE_UNIT_OUT_CONTEXT_ID ; - public : SC_IN (Tcontext_t ) ** in_EXECUTE_UNIT_OUT_FRONT_END_ID ; - public : SC_IN (Tcontext_t ) ** in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID ; - public : SC_IN (Tpacket_t ) ** in_EXECUTE_UNIT_OUT_PACKET_ID ; -//public : SC_IN (Toperation_t ) ** in_EXECUTE_UNIT_OUT_OPERATION ; - public : SC_IN (Ttype_t ) ** in_EXECUTE_UNIT_OUT_TYPE ; - public : SC_IN (Tcontrol_t ) ** in_EXECUTE_UNIT_OUT_WRITE_RD ; - public : SC_IN (Tgeneral_address_t) ** in_EXECUTE_UNIT_OUT_NUM_REG_RD ; - public : SC_IN (Tgeneral_data_t ) ** in_EXECUTE_UNIT_OUT_DATA_RD ; - public : SC_IN (Tcontrol_t ) ** in_EXECUTE_UNIT_OUT_WRITE_RE ; - public : SC_IN (Tspecial_address_t) ** in_EXECUTE_UNIT_OUT_NUM_REG_RE ; - public : SC_IN (Tspecial_data_t ) ** in_EXECUTE_UNIT_OUT_DATA_RE ; - public : SC_IN (Texception_t ) ** in_EXECUTE_UNIT_OUT_EXCEPTION ; - public : SC_IN (Tcontrol_t ) ** in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; - public : SC_IN (Tgeneral_data_t ) ** in_EXECUTE_UNIT_OUT_ADDRESS ; + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_VAL ; + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_UNIT_OUT_ACK ; + public : SC_IN (Tcontext_t ) *** in_EXECUTE_UNIT_OUT_CONTEXT_ID ; + public : SC_IN (Tcontext_t ) *** in_EXECUTE_UNIT_OUT_FRONT_END_ID ; + public : SC_IN (Tcontext_t ) *** in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID ; + public : SC_IN (Tpacket_t ) *** in_EXECUTE_UNIT_OUT_PACKET_ID ; +//public : SC_IN (Toperation_t ) *** in_EXECUTE_UNIT_OUT_OPERATION ; + public : SC_IN (Ttype_t ) *** in_EXECUTE_UNIT_OUT_TYPE ; + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_WRITE_RD ; + public : SC_IN (Tgeneral_address_t) *** in_EXECUTE_UNIT_OUT_NUM_REG_RD ; + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_UNIT_OUT_DATA_RD ; + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_WRITE_RE ; + public : SC_IN (Tspecial_address_t) *** in_EXECUTE_UNIT_OUT_NUM_REG_RE ; + public : SC_IN (Tspecial_data_t ) *** in_EXECUTE_UNIT_OUT_DATA_RE ; + public : SC_IN (Texception_t ) *** in_EXECUTE_UNIT_OUT_EXCEPTION ; + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_UNIT_OUT_ADDRESS ; // ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -107,5 +107,5 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : std::list ** _destination; // [nb_execute_unit][nb_thread]; + private : std::list *** _destination; //[nb_execute_unit][nb_execute_unit_port][nb_thread]; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Parameters.h (revision 88) @@ -26,34 +26,37 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _nb_execute_unit ; - public : const uint32_t _nb_write_unit ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _nb_special_register ; - public : const Tpriority_t _priority ; - public : bool ** _table_routing ; //array [nb_execute_unit][nb_write_unit] - public : bool ** _table_thread ; //array [nb_write_unit][nb_thread] + public : uint32_t _nb_execute_unit ; + public : uint32_t * _nb_execute_unit_port ;//[nb_execute_unit] + public : uint32_t _nb_write_unit ; + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; + public : Tpriority_t _priority ; + public : bool *** _table_routing ; //[nb_execute_unit][nb_execute_unit_port][nb_write_unit] + public : bool ** _table_thread ; //[nb_write_unit][nb_thread] - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; + public : uint32_t _max_nb_execute_unit_port ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id ; - public : const bool _have_port_packet_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; - public : const uint32_t _nb_thread ; + public : uint32_t _nb_thread ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_execute_unit , + uint32_t * nb_execute_unit_port , uint32_t nb_write_unit , uint32_t nb_context , @@ -66,8 +69,12 @@ uint32_t nb_special_register , Tpriority_t priority , - bool ** table_routing , - bool ** table_thread ); - public : Parameters (Parameters & param) ; + bool *** table_routing , + bool ** table_thread , + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; public : ~Parameters (); + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); +#if DEBUG_Execution_unit_to_Write_unit == true + log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,"Method - transition"); @@ -84,27 +90,28 @@ sensitive << (*(in_CLOCK)).pos(); for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - if (_param->_have_port_context_id) - sensitive << (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i])); - if (_param->_have_port_front_end_id) - sensitive << (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i])); - if (_param->_have_port_ooo_engine_id) - sensitive << (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i])); - if (_param->_have_port_packet_id) - sensitive << (*(in_EXECUTE_UNIT_OUT_PACKET_ID [i])); - - sensitive << (*(in_EXECUTE_UNIT_OUT_VAL [i])) - //<< (*(in_EXECUTE_UNIT_OUT_OPERATION [i])) - //<< (*(in_EXECUTE_UNIT_OUT_TYPE [i])) - << (*(in_EXECUTE_UNIT_OUT_WRITE_RD [i])) - << (*(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i])) - << (*(in_EXECUTE_UNIT_OUT_DATA_RD [i])) - << (*(in_EXECUTE_UNIT_OUT_WRITE_RE [i])) - << (*(in_EXECUTE_UNIT_OUT_NUM_REG_RE [i])) - << (*(in_EXECUTE_UNIT_OUT_DATA_RE [i])) - << (*(in_EXECUTE_UNIT_OUT_EXCEPTION [i])) - << (*(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i])) - << (*(in_EXECUTE_UNIT_OUT_ADDRESS [i])); - } + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + if (_param->_have_port_context_id) + sensitive << (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i][j])); + if (_param->_have_port_ooo_engine_id) + sensitive << (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i][j])); + if (_param->_have_port_rob_ptr ) + sensitive << (*(in_EXECUTE_UNIT_OUT_PACKET_ID [i][j])); + + sensitive << (*(in_EXECUTE_UNIT_OUT_VAL [i][j])) + //<< (*(in_EXECUTE_UNIT_OUT_OPERATION [i][j])) + //<< (*(in_EXECUTE_UNIT_OUT_TYPE [i][j])) + << (*(in_EXECUTE_UNIT_OUT_WRITE_RD [i][j])) + << (*(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j])) + << (*(in_EXECUTE_UNIT_OUT_DATA_RD [i][j])) + << (*(in_EXECUTE_UNIT_OUT_WRITE_RE [i][j])) + << (*(in_EXECUTE_UNIT_OUT_NUM_REG_RE [i][j])) + << (*(in_EXECUTE_UNIT_OUT_DATA_RE [i][j])) + << (*(in_EXECUTE_UNIT_OUT_EXCEPTION [i][j])) + << (*(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i][j])) + << (*(in_EXECUTE_UNIT_OUT_ADDRESS [i][j])); + } for (uint32_t i=0; i<_param->_nb_write_unit; i++) sensitive << (*(in_WRITE_UNIT_IN_ACK [i])); @@ -113,29 +120,31 @@ // List dependency information for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - (*(out_EXECUTE_UNIT_OUT_ACK [i])) (*(in_EXECUTE_UNIT_OUT_VAL [i])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_OUT_ACK [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_OUT_ACK [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_OUT_ACK [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i])); - - for (uint32_t j=0; j<_param->_nb_write_unit; j++) - (*(out_EXECUTE_UNIT_OUT_ACK [i])) (*(in_WRITE_UNIT_IN_ACK [j])); - } + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + (*(out_EXECUTE_UNIT_OUT_ACK [i][j])) (*(in_EXECUTE_UNIT_OUT_VAL [i][j])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_OUT_ACK [i][j])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_OUT_ACK [i][j])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i][j])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_OUT_ACK [i][j])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i][j])); + + for (uint32_t x=0; x<_param->_nb_write_unit; x++) + (*(out_EXECUTE_UNIT_OUT_ACK [i][j])) (*(in_WRITE_UNIT_IN_ACK [x])); + } for (uint32_t i=0; i<_param->_nb_write_unit; i++) { (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } @@ -143,13 +152,14 @@ { (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } @@ -157,13 +167,14 @@ { (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } @@ -171,175 +182,187 @@ { (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); - } - } - - if (_param->_have_port_packet_id) + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + } + + if (_param->_have_port_rob_ptr ) { (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_PACKET_ID [j])); - (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_PACKET_ID [x][y])); + (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } // (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_WRITE_UNIT_IN_ACK [i])); -// for (uint32_t j=0; j<_param->_nb_execute_unit; j++) +// for (uint32_t x=0; x<_param->_nb_execute_unit; x++) +// for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) // { -// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_OPERATION [j])); -// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); +// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_OPERATION [x][y])); +// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); // if (_param->_have_port_context_id) -// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); +// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); // if (_param->_have_port_front_end_id) -// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); +// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); // if (_param->_have_port_ooo_engine_id) -// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); +// (*(out_WRITE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); // } // (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_WRITE_UNIT_IN_ACK [i])); -// for (uint32_t j=0; j<_param->_nb_execute_unit; j++) +// for (uint32_t x=0; x<_param->_nb_execute_unit; x++) +// for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) // { -// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_TYPE [j])); -// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); +// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_TYPE [x][y])); +// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); // if (_param->_have_port_context_id) -// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); +// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); // if (_param->_have_port_front_end_id) -// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); +// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); // if (_param->_have_port_ooo_engine_id) -// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); +// (*(out_WRITE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); // } (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_WRITE_RD [j])); - (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_WRITE_RD [x][y])); + (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_NUM_REG_RD [j])); - (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_NUM_REG_RD [x][y])); + (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_DATA_RD [j])); - (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_DATA_RD [x][y])); + (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_DATA_RD [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_WRITE_RE [j])); - (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_WRITE_RE [x][y])); + (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_NUM_REG_RE [j])); - (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_NUM_REG_RE [x][y])); + (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_DATA_RE [j])); - (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_DATA_RE [x][y])); + (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_DATA_RE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_EXCEPTION [j])); - (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_EXCEPTION [x][y])); + (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_EXCEPTION [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [j])); - (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [x][y])); + (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_NO_SEQUENCE [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); } (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_WRITE_UNIT_IN_ACK [i])); - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - { - (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_ADDRESS [j])); - (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_VAL [j])); - if (_param->_have_port_context_id) - (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [j])); - } - + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + { + (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_ADDRESS [x][y])); + (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_VAL [x][y])); + if (_param->_have_port_context_id) + (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_WRITE_UNIT_IN_ADDRESS [i])) (*(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } } # endif @@ -357,5 +380,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execution_unit_to_Write_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 88) @@ -58,24 +58,25 @@ // ~~~~~[ Interface "execute_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("execute_unit_out", IN, EAST, "Output of execution_unit", _param->_nb_execute_unit); + ALLOC2_INTERFACE("execute_unit_out", IN, EAST, "Output of execution_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); - ALLOC1_VALACK_IN ( in_EXECUTE_UNIT_OUT_VAL,VAL); - ALLOC1_VALACK_OUT(out_EXECUTE_UNIT_OUT_ACK,ACK); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); - //ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + _ALLOC2_VALACK_IN ( in_EXECUTE_UNIT_OUT_VAL,VAL, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_VALACK_OUT(out_EXECUTE_UNIT_OUT_ACK,ACK, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + //_ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); } + // ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { @@ -87,5 +88,5 @@ ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id ); + ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); //ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); @@ -102,12 +103,20 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _destination = new std::list * [_param->_nb_execute_unit]; + if (usage_is_set(_usage,USE_SYSTEMC)) + { + _destination = new std::list ** [_param->_nb_execute_unit]; for (uint32_t i=0; i<_param->_nb_execute_unit; i++) { - _destination [i] = new std::list [_param->_nb_thread]; + _destination [i] = new std::list * [_param->_nb_execute_unit_port[i]]; + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + _destination [i][j] = new std::list [_param->_nb_thread]; + } } + } #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -23,56 +24,49 @@ log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; delete in_NRESET; - delete [] in_EXECUTE_UNIT_OUT_VAL; - delete [] out_EXECUTE_UNIT_OUT_ACK; - if (_param->_have_port_context_id) - delete [] in_EXECUTE_UNIT_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] in_EXECUTE_UNIT_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) - delete [] in_EXECUTE_UNIT_OUT_PACKET_ID ; - //delete [] in_EXECUTE_UNIT_OUT_OPERATION ; - delete [] in_EXECUTE_UNIT_OUT_TYPE ; - delete [] in_EXECUTE_UNIT_OUT_WRITE_RD ; - delete [] in_EXECUTE_UNIT_OUT_NUM_REG_RD ; - delete [] in_EXECUTE_UNIT_OUT_DATA_RD ; - delete [] in_EXECUTE_UNIT_OUT_WRITE_RE ; - delete [] in_EXECUTE_UNIT_OUT_NUM_REG_RE ; - delete [] in_EXECUTE_UNIT_OUT_DATA_RE ; - delete [] in_EXECUTE_UNIT_OUT_EXCEPTION ; - delete [] in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; - delete [] in_EXECUTE_UNIT_OUT_ADDRESS ; + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_VAL , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1); + DELETE2_SIGNAL(out_EXECUTE_UNIT_OUT_ACK , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_CONTEXT_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_FRONT_END_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_ooo_engine_id ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_rob_ptr ); + // DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_type ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_special_register); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_DATA_RE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_special_data ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_exception ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_general_data ); - delete [] out_WRITE_UNIT_IN_VAL; - delete [] in_WRITE_UNIT_IN_ACK; - if (_param->_have_port_context_id) - delete [] out_WRITE_UNIT_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] out_WRITE_UNIT_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] out_WRITE_UNIT_IN_OOO_ENGINE_ID; - if (_param->_have_port_packet_id) - delete [] out_WRITE_UNIT_IN_PACKET_ID ; - //delete [] out_WRITE_UNIT_IN_OPERATION ; - delete [] out_WRITE_UNIT_IN_TYPE ; - delete [] out_WRITE_UNIT_IN_WRITE_RD ; - delete [] out_WRITE_UNIT_IN_NUM_REG_RD ; - delete [] out_WRITE_UNIT_IN_DATA_RD ; - delete [] out_WRITE_UNIT_IN_WRITE_RE ; - delete [] out_WRITE_UNIT_IN_NUM_REG_RE ; - delete [] out_WRITE_UNIT_IN_DATA_RE ; - delete [] out_WRITE_UNIT_IN_EXCEPTION ; - delete [] out_WRITE_UNIT_IN_NO_SEQUENCE ; - delete [] out_WRITE_UNIT_IN_ADDRESS ; + DELETE1_SIGNAL(out_WRITE_UNIT_IN_VAL , _param->_nb_write_unit,1); + DELETE1_SIGNAL( in_WRITE_UNIT_IN_ACK , _param->_nb_write_unit,1); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_CONTEXT_ID , _param->_nb_write_unit,_param->_size_context_id ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_FRONT_END_ID , _param->_nb_write_unit,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_OOO_ENGINE_ID, _param->_nb_write_unit,_param->_size_ooo_engine_id ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID , _param->_nb_write_unit,_param->_size_rob_ptr ); + // DELETE1_SIGNAL(out_WRITE_UNIT_IN_OPERATION , _param->_nb_write_unit,_param->_size_operation ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_TYPE , _param->_nb_write_unit,_param->_size_type ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD , _param->_nb_write_unit,1 ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD , _param->_nb_write_unit,_param->_size_general_register); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_DATA_RD , _param->_nb_write_unit,_param->_size_general_data ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_WRITE_RE , _param->_nb_write_unit,1 ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RE , _param->_nb_write_unit,_param->_size_special_register); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_DATA_RE , _param->_nb_write_unit,_param->_size_special_data ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_EXCEPTION , _param->_nb_write_unit,_param->_size_exception ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_NO_SEQUENCE , _param->_nb_write_unit,1 ); + DELETE1_SIGNAL(out_WRITE_UNIT_IN_ADDRESS , _param->_nb_write_unit,_param->_size_general_data ); + + delete [] _destination; } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] _destination; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp (revision 88) @@ -30,63 +30,64 @@ for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - bool ack = false; - - log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION,"Test execute_unit[%d]",i); - - if (PORT_READ(in_EXECUTE_UNIT_OUT_VAL [i]) == true) - { - log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * have a valid entry."); - - Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i]):0; - Tcontext_t front_end_id = (_param->_have_port_front_end_id )?PORT_READ(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i]):0; - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i]):0; - Tcontext_t num_thread = get_num_thread(context_id , _param->_size_context_id , - front_end_id , _param->_size_front_end_id , - ooo_engine_id, _param->_size_ooo_engine_id); + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + { + bool ack = false; + + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION,"Test execute_unit[%d][%d]",i,j); + + if (PORT_READ(in_EXECUTE_UNIT_OUT_VAL [i][j]) == true) + { + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * have a valid entry."); + + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i][j]):0; + Tcontext_t front_end_id = (_param->_have_port_front_end_id )?PORT_READ(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i][j]):0; + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i][j]):0; + Tcontext_t num_thread = get_num_thread(context_id , _param->_size_context_id , + front_end_id , _param->_size_front_end_id , + ooo_engine_id, _param->_size_ooo_engine_id); #ifdef DEBUG_TEST - if (_destination[i][num_thread].empty()) - throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no write_unit to receive a operation from the execute_unit ["+toString(i)+"], thread ["+toString(num_thread)+"]."); + if (_destination[i][j][num_thread].empty()) + throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no write_unit to receive a operation from the execute_unit ["+toString(i)+"]["+toString(j)+"], thread ["+toString(num_thread)+"]."); #endif - - // find a free write_unit - for (std::list::iterator it=_destination[i][num_thread].begin(); - (it != _destination[i][num_thread].end()) and (ack == false); - it++) - { - uint32_t dest = *it; - - log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * Test destination [%d].",dest); - - if (write_unit_use [dest] == false) - { - log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * Is ok! Link."); - // have find !!! - ack = true; - write_unit_use [dest] = true; - - if (_param->_have_port_context_id) - PORT_WRITE(out_WRITE_UNIT_IN_CONTEXT_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_CONTEXT_ID [i])); - if (_param->_have_port_front_end_id) - PORT_WRITE(out_WRITE_UNIT_IN_FRONT_END_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_FRONT_END_ID [i])); - if (_param->_have_port_ooo_engine_id) - PORT_WRITE(out_WRITE_UNIT_IN_OOO_ENGINE_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OOO_ENGINE_ID [i])); - if (_param->_have_port_packet_id) - PORT_WRITE(out_WRITE_UNIT_IN_PACKET_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_PACKET_ID [i])); - //PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i])); - PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i])); - PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RD [i])); - PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i])); - PORT_WRITE(out_WRITE_UNIT_IN_DATA_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_DATA_RD [i])); - PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RE [i])); - PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RE [i])); - PORT_WRITE(out_WRITE_UNIT_IN_DATA_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_DATA_RE [i])); - PORT_WRITE(out_WRITE_UNIT_IN_EXCEPTION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_EXCEPTION [i])); - PORT_WRITE(out_WRITE_UNIT_IN_NO_SEQUENCE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i])); - PORT_WRITE(out_WRITE_UNIT_IN_ADDRESS [dest], PORT_READ(in_EXECUTE_UNIT_OUT_ADDRESS [i])); - } - } - } - PORT_WRITE(out_EXECUTE_UNIT_OUT_ACK [i], ack); + + // find a free write_unit + for (std::list::iterator it=_destination[i][j][num_thread].begin(); + (it != _destination[i][j][num_thread].end()) and (ack == false); + it++) + { + uint32_t dest = *it; + + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * Test destination [%d].",dest); + + if (write_unit_use [dest] == false) + { + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * Is ok! Link."); + // have find !!! + ack = true; + write_unit_use [dest] = true; + + if (_param->_have_port_context_id) + PORT_WRITE(out_WRITE_UNIT_IN_CONTEXT_ID [dest], context_id); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_WRITE_UNIT_IN_FRONT_END_ID [dest], front_end_id); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_WRITE_UNIT_IN_OOO_ENGINE_ID [dest], ooo_engine_id); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_WRITE_UNIT_IN_PACKET_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_PACKET_ID [i][j])); + // PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RD [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_DATA_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_DATA_RD [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RE [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RE [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_DATA_RE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_DATA_RE [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_EXCEPTION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_EXCEPTION [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_NO_SEQUENCE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NO_SEQUENCE [i][j])); + PORT_WRITE(out_WRITE_UNIT_IN_ADDRESS [dest], PORT_READ(in_EXECUTE_UNIT_OUT_ADDRESS [i][j])); + } + } + } + PORT_WRITE(out_EXECUTE_UNIT_OUT_ACK [i][j], ack); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_transition.cpp (revision 88) @@ -27,42 +27,46 @@ { // Flush routing_table - for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - for (uint32_t j=0; j<_param->_nb_thread; j++) - _destination [i][j].clear(); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + for (uint32_t j=0; j<_param->_nb_thread; j++) + _destination [x][y][j].clear(); // Fill routing table - for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - // Test if link between src and dest - if (_param->_table_routing [i][j]) - // Test the thread accepted by the execute_unit - for (uint32_t k=0; k<_param->_nb_thread; k++) - if (_param->_table_thread[j][k]) - // push_back == minor have a better priority - _destination [i][k].push_back(j); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + for (uint32_t j=0; j<_param->_nb_write_unit; j++) + // Test if link between src and dest + if (_param->_table_routing [x][y][j]) + // Test the thread accepted by the execute_unit + for (uint32_t k=0; k<_param->_nb_thread; k++) + if (_param->_table_thread[j][k]) + // push_back == minor have a better priority + _destination [x][y][k].push_back(j); } else { if (_param->_priority == PRIORITY_ROUND_ROBIN) - for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - for (uint32_t j=0; j<_param->_nb_thread; j++) - if (_destination [i][j].size() > 1) - { - // Head queue became the Tail queue - _destination [i][j].push_back(_destination [i][j].front()); - _destination [i][j].pop_front(); - } + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + for (uint32_t j=0; j<_param->_nb_thread; j++) + if (_destination [x][y][j].size() > 1) + { + // Head queue became the Tail queue + _destination [x][y][j].push_back(_destination [x][y][j].front()); + _destination [x][y][j].pop_front(); + } } - - + + #if (DEBUG >= DEBUG_TRACE) // Print log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"Routing Table"); - for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - for (uint32_t j=0; j<_param->_nb_thread; j++) - for (std::list::iterator k=_destination[i][j].begin(); - k != _destination[i][j].end(); - k++) - log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Execute_unit [%d], send at the write_unit [%d], the operation of thread [%d].",i,*k,j); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + for (uint32_t j=0; j<_param->_nb_thread; j++) + for (std::list::iterator k=_destination[x][y][j].begin(); + k != _destination[x][y][j].end(); + k++) + log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Execute_unit [%d][%d], send at the write_unit [%d], the operation of thread [%d].",x,y,*k,j); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp (revision 88) @@ -7,5 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Parameters.h" - +#include "Common/include/Max.h" namespace morpheo { namespace behavioural { @@ -20,4 +20,5 @@ #define FUNCTION "Execution_unit_to_Write_unit::Parameters" Parameters::Parameters (uint32_t nb_execute_unit , + uint32_t * nb_execute_unit_port ,//[nb_execute_unit] uint32_t nb_write_unit , uint32_t nb_context , @@ -30,82 +31,72 @@ uint32_t nb_special_register , Tpriority_t priority , - bool ** table_routing , - bool ** table_thread ): - _nb_execute_unit (nb_execute_unit ), - _nb_write_unit (nb_write_unit ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_general_register (nb_general_register), - _nb_special_register (nb_special_register), - _priority (priority ), - - _size_context_id (log2(nb_context )), - _size_front_end_id (log2(nb_front_end )), - _size_ooo_engine_id (log2(nb_ooo_engine )), - _size_packet_id (log2(nb_packet )), - _size_general_register (log2(nb_general_register)), - _size_special_register (log2(nb_special_register)), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0), - - _nb_thread (get_nb_thread (nb_context, nb_front_end, nb_ooo_engine)) + bool *** table_routing ,//[nb_execute_unit][nb_execute_unit_port][nb_write_unit] + bool ** table_thread ,//[nb_write_unit][nb_thread] + bool is_toplevel ) { log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); - _table_routing = table_routing ; - _table_thread = table_thread ; + _nb_execute_unit = nb_execute_unit ; + _nb_execute_unit_port = nb_execute_unit_port; + _nb_write_unit = nb_write_unit ; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _priority = priority ; + _table_routing = table_routing ; + _table_thread = table_thread ; + + _max_nb_execute_unit_port= max(_nb_execute_unit_port, _nb_execute_unit); + + _nb_thread = get_nb_thread (nb_context, nb_front_end, nb_ooo_engine); test(); + + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_front_end_id = log2(nb_front_end ); + _size_ooo_engine_id = log2(nb_ooo_engine ); + _size_rob_ptr = log2(nb_packet ); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + + copy(); + } + log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Execution_unit_to_Write_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); + +// test(); +// log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Execution_unit_to_Write_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _nb_execute_unit (param._nb_execute_unit ), - _nb_write_unit (param._nb_write_unit ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _priority (param._priority ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ), - - _nb_thread (param._nb_thread ) +#define FUNCTION "Execution_unit_to_Write_unit::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); - - _table_routing = param._table_routing ; - _table_thread = param._table_thread ; - - test(); log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Execution_unit_to_Write_unit::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Execution_unit_to_Write_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters_msg_error.cpp (revision 88) @@ -24,18 +24,32 @@ { log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"Begin"); + + Parameters_test test("Execution_unit_to_Write_unit"); + + bool is_link [_nb_execute_unit][_max_nb_execute_unit_port]; + for (uint32_t i=0; i<_nb_execute_unit; i++) + for (uint32_t j=0; j<_nb_execute_unit_port[i]; j++) + is_link[i][j] = false; + + for (uint32_t i=0; i<_nb_execute_unit; i++) + for (uint32_t j=0; j<_nb_execute_unit_port[i]; j++) + for (uint32_t k=0; k<_nb_write_unit; k++) + { + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION,"[%d][%d][%d]",i,j,k); + + if (_table_routing [i][j][k] == true) + { + log_printf(TRACE,Execution_unit_to_Write_unit,FUNCTION," * is link"); - Parameters_test test("Execution_unit_to_Write_unit"); + is_link [i][j] = true; + break; + } + } for (uint32_t i=0; i<_nb_execute_unit; i++) - { - uint32_t j; - for (j=0; j<_nb_write_unit; j++) - if (_table_routing [i][j] == true) - break; - - if (j == _nb_write_unit) - test.error("The execute_unit ["+toString(i)+"] is link with none write_unit."); - } - + for (uint32_t j=0; j<_nb_execute_unit_port[i]; j++) + if (not is_link[i][j]) + test.error(toString(_("The execute_unit [%d][%d] is link with none write_unit.\n"),i,j)); + for (uint32_t i=0; i<_nb_write_unit; i++) { @@ -44,12 +58,12 @@ if (_table_thread [i][j] == true) break; - + if (j == _nb_thread) - test.error("The write_unit ["+toString(i)+"] have none source's thread."); + test.error(toString(_("The write_unit [%d] have none source's thread.\n"),i)); } if ( (_priority != PRIORITY_STATIC ) and (_priority != PRIORITY_ROUND_ROBIN)) - test.error("Unsupported priority scheme. It must be Static or Round Robin."); + test.error(_("Unsupported priority scheme. It must be Static or Round Robin.\n")); log_printf(FUNC,Execution_unit_to_Write_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Read_unit_to_Execution_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_min.cfg (revision 88) @@ -1,5 +1,8 @@ Read_unit_to_Execution_unit 1 1 *2 # nb_read_unit -2 2 *2 # nb_execute_unit +1 1 +1 # nb_read_unit_port [0] [nb_read_unit] +2 2 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] 1 1 *2 # nb_context 1 1 *2 # nb_front_end @@ -13,11 +16,12 @@ 4 4 *2 # size_load_queue 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -1 1 +1 # table_routing [0][1] +1 1 +1 # table_routing [0][0][0] +1 1 +1 # table_routing [0][1][0] 0 0 +1 # table_execute_type [0][TYPE_ALU ] 0 0 +1 # table_execute_type [0][TYPE_SHIFT ] 0 0 +1 # table_execute_type [0][TYPE_MOVE ] 0 0 +1 # table_execute_type [0][TYPE_TEST ] -0 0 +1 # table_execute_type [0][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [0][TYPE_MUL ] +0 0 +1 # table_execute_type [0][TYPE_DIV ] 0 0 +1 # table_execute_type [0][TYPE_EXTEND ] 0 0 +1 # table_execute_type [0][TYPE_FIND ] @@ -30,5 +34,6 @@ 1 1 +1 # table_execute_type [1][TYPE_MOVE ] 1 1 +1 # table_execute_type [1][TYPE_TEST ] -1 1 +1 # table_execute_type [1][TYPE_MUL_DIV] +1 1 +1 # table_execute_type [1][TYPE_MUL ] +1 1 +1 # table_execute_type [1][TYPE_DIV ] 1 1 +1 # table_execute_type [1][TYPE_EXTEND ] 1 1 +1 # table_execute_type [1][TYPE_FIND ] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread-multi_lsq.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread-multi_lsq.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread-multi_lsq.cfg (revision 88) @@ -0,0 +1,105 @@ +Read_unit_to_Execution_unit +3 3 *2 # nb_read_unit +2 2 +1 # nb_read_unit_port [0] [nb_read_unit] +3 3 +1 # nb_read_unit_port [1] [nb_read_unit] +1 1 +1 # nb_read_unit_port [2] [nb_read_unit] +5 5 *2 # nb_execute_unit +2 2 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [3] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [4] [nb_execute_unit] +1 1 *2 # nb_context +1 1 *2 # nb_front_end +1 1 *2 # nb_ooo_engine +64 64 *2 # nb_packet +32 32 *2 # size_general_data +2 2 *2 # size_special_data +64 64 *2 # nb_general_register +16 16 *2 # nb_special_register +4 4 *2 # size_store_queue +1 4 *4 # size_load_queue +0 1 +1 # priority +1 1 +1 # table_routing [0][0][0] +1 1 +1 # table_routing [0][0][0] +0 0 +1 # table_routing [0][1][0] +0 0 +1 # table_routing [0][2][0] +0 0 +1 # table_routing [0][3][0] +0 0 +1 # table_routing [0][4][0] +0 0 +1 # table_routing [1][0][0] +0 0 +1 # table_routing [1][0][1] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][2][0] +0 0 +1 # table_routing [1][3][0] +0 0 +1 # table_routing [1][4][0] +0 0 +1 # table_routing [2][0][0] +1 1 +1 # table_routing [2][0][1] +0 0 +1 # table_routing [2][1][0] +1 1 +1 # table_routing [2][2][0] +1 1 +1 # table_routing [2][3][0] +1 1 +1 # table_routing [2][4][0] +0 0 +1 # table_execute_type [0][TYPE_ALU ] +0 0 +1 # table_execute_type [0][TYPE_SHIFT ] +0 0 +1 # table_execute_type [0][TYPE_MOVE ] +0 0 +1 # table_execute_type [0][TYPE_TEST ] +0 0 +1 # table_execute_type [0][TYPE_MUL ] +0 0 +1 # table_execute_type [0][TYPE_DIV ] +0 0 +1 # table_execute_type [0][TYPE_EXTEND ] +0 0 +1 # table_execute_type [0][TYPE_FIND ] +0 0 +1 # table_execute_type [0][TYPE_SPECIAL] +0 0 +1 # table_execute_type [0][TYPE_CUSTOM ] +0 0 +1 # table_execute_type [0][TYPE_BRANCH ] +1 1 +1 # table_execute_type [0][TYPE_MEMORY ] +1 1 +1 # table_execute_type [1][TYPE_ALU ] +1 1 +1 # table_execute_type [1][TYPE_SHIFT ] +1 1 +1 # table_execute_type [1][TYPE_MOVE ] +1 1 +1 # table_execute_type [1][TYPE_TEST ] +1 1 +1 # table_execute_type [1][TYPE_MUL ] +1 1 +1 # table_execute_type [1][TYPE_DIV ] +1 1 +1 # table_execute_type [1][TYPE_EXTEND ] +1 1 +1 # table_execute_type [1][TYPE_FIND ] +1 1 +1 # table_execute_type [1][TYPE_SPECIAL] +1 1 +1 # table_execute_type [1][TYPE_CUSTOM ] +1 1 +1 # table_execute_type [1][TYPE_BRANCH ] +0 0 +1 # table_execute_type [1][TYPE_MEMORY ] +1 1 +1 # table_execute_type [2][TYPE_ALU ] +0 0 +1 # table_execute_type [2][TYPE_SHIFT ] +0 0 +1 # table_execute_type [2][TYPE_MOVE ] +0 0 +1 # table_execute_type [2][TYPE_TEST ] +0 0 +1 # table_execute_type [2][TYPE_MUL ] +0 0 +1 # table_execute_type [2][TYPE_DIV ] +0 0 +1 # table_execute_type [2][TYPE_EXTEND ] +0 0 +1 # table_execute_type [2][TYPE_FIND ] +0 0 +1 # table_execute_type [2][TYPE_SPECIAL] +0 0 +1 # table_execute_type [2][TYPE_CUSTOM ] +1 1 +1 # table_execute_type [2][TYPE_BRANCH ] +0 0 +1 # table_execute_type [2][TYPE_MEMORY ] +1 1 +1 # table_execute_type [3][TYPE_ALU ] +1 1 +1 # table_execute_type [3][TYPE_SHIFT ] +1 1 +1 # table_execute_type [3][TYPE_MOVE ] +1 1 +1 # table_execute_type [3][TYPE_TEST ] +0 0 +1 # table_execute_type [3][TYPE_MUL ] +0 0 +1 # table_execute_type [3][TYPE_DIV ] +1 1 +1 # table_execute_type [3][TYPE_EXTEND ] +1 1 +1 # table_execute_type [3][TYPE_FIND ] +0 0 +1 # table_execute_type [3][TYPE_SPECIAL] +0 0 +1 # table_execute_type [3][TYPE_CUSTOM ] +1 1 +1 # table_execute_type [3][TYPE_BRANCH ] +0 0 +1 # table_execute_type [3][TYPE_MEMORY ] +0 0 +1 # table_execute_type [4][TYPE_ALU ] +1 1 +1 # table_execute_type [4][TYPE_SHIFT ] +1 1 +1 # table_execute_type [4][TYPE_MOVE ] +0 0 +1 # table_execute_type [4][TYPE_TEST ] +1 1 +1 # table_execute_type [4][TYPE_MUL ] +1 1 +1 # table_execute_type [4][TYPE_DIV ] +0 0 +1 # table_execute_type [4][TYPE_EXTEND ] +0 0 +1 # table_execute_type [4][TYPE_FIND ] +0 0 +1 # table_execute_type [4][TYPE_SPECIAL] +0 0 +1 # table_execute_type [4][TYPE_CUSTOM ] +0 0 +1 # table_execute_type [4][TYPE_BRANCH ] +0 0 +1 # table_execute_type [4][TYPE_MEMORY ] +1 1 +1 # table_execute_thread [0][0] +1 1 +1 # table_execute_thread [1][0] +1 1 +1 # table_execute_thread [2][0] +1 1 +1 # table_execute_thread [3][0] +1 1 +1 # table_execute_thread [4][0] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-mono_thread.cfg (revision 88) @@ -1,5 +1,12 @@ Read_unit_to_Execution_unit 3 3 *2 # nb_read_unit +1 1 +1 # nb_read_unit_port [0] [nb_read_unit] +2 2 +1 # nb_read_unit_port [1] [nb_read_unit] +4 4 +1 # nb_read_unit_port [2] [nb_read_unit] 4 4 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [3] [nb_execute_unit] 1 1 *2 # nb_context 1 1 *2 # nb_front_end @@ -13,21 +20,22 @@ 1 4 *4 # size_load_queue 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -0 0 +1 # table_routing [0][1] -0 0 +1 # table_routing [0][2] -0 0 +1 # table_routing [0][3] -0 0 +1 # table_routing [1][0] -1 1 +1 # table_routing [1][1] -1 1 +1 # table_routing [1][2] -0 0 +1 # table_routing [1][3] -0 0 +1 # table_routing [2][0] -0 0 +1 # table_routing [2][1] -1 1 +1 # table_routing [2][2] -1 1 +1 # table_routing [2][3] +1 1 +1 # table_routing [0][0][0] +0 0 +1 # table_routing [0][1][0] +0 0 +1 # table_routing [0][2][0] +0 0 +1 # table_routing [0][3][0] +0 0 +1 # table_routing [1][0][0] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][2][0] +0 0 +1 # table_routing [1][3][0] +0 0 +1 # table_routing [2][0][0] +0 0 +1 # table_routing [2][1][0] +1 1 +1 # table_routing [2][2][0] +1 1 +1 # table_routing [2][3][0] 0 0 +1 # table_execute_type [0][TYPE_ALU ] 0 0 +1 # table_execute_type [0][TYPE_SHIFT ] 0 0 +1 # table_execute_type [0][TYPE_MOVE ] 0 0 +1 # table_execute_type [0][TYPE_TEST ] -0 0 +1 # table_execute_type [0][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [0][TYPE_MUL ] +0 0 +1 # table_execute_type [0][TYPE_DIV ] 0 0 +1 # table_execute_type [0][TYPE_EXTEND ] 0 0 +1 # table_execute_type [0][TYPE_FIND ] @@ -40,5 +48,6 @@ 1 1 +1 # table_execute_type [1][TYPE_MOVE ] 1 1 +1 # table_execute_type [1][TYPE_TEST ] -1 1 +1 # table_execute_type [1][TYPE_MUL_DIV] +1 1 +1 # table_execute_type [1][TYPE_MUL ] +1 1 +1 # table_execute_type [1][TYPE_DIV ] 1 1 +1 # table_execute_type [1][TYPE_EXTEND ] 1 1 +1 # table_execute_type [1][TYPE_FIND ] @@ -51,5 +60,6 @@ 0 0 +1 # table_execute_type [2][TYPE_MOVE ] 0 0 +1 # table_execute_type [2][TYPE_TEST ] -0 0 +1 # table_execute_type [2][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [2][TYPE_MUL ] +0 0 +1 # table_execute_type [2][TYPE_DIV ] 0 0 +1 # table_execute_type [2][TYPE_EXTEND ] 0 0 +1 # table_execute_type [2][TYPE_FIND ] @@ -62,5 +72,6 @@ 1 1 +1 # table_execute_type [3][TYPE_MOVE ] 1 1 +1 # table_execute_type [3][TYPE_TEST ] -0 0 +1 # table_execute_type [3][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [3][TYPE_MUL ] +0 0 +1 # table_execute_type [3][TYPE_DIV ] 1 1 +1 # table_execute_type [3][TYPE_EXTEND ] 1 1 +1 # table_execute_type [3][TYPE_FIND ] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-multi_thread.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-multi_thread.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/config_multi_execute-multi_thread.cfg (revision 88) @@ -1,5 +1,12 @@ Read_unit_to_Execution_unit 3 3 *2 # nb_read_unit +1 1 +1 # nb_read_unit_port [0] [nb_read_unit] +1 1 +1 # nb_read_unit_port [1] [nb_read_unit] +1 1 +1 # nb_read_unit_port [2] [nb_read_unit] 4 4 *2 # nb_execute_unit +1 1 +1 # nb_execute_unit_port [0] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [1] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [2] [nb_execute_unit] +1 1 +1 # nb_execute_unit_port [3] [nb_execute_unit] 4 4 *2 # nb_context 1 1 *2 # nb_front_end @@ -13,21 +20,22 @@ 4 4 *2 # size_load_queue 0 1 +1 # priority -1 1 +1 # table_routing [0][0] -0 0 +1 # table_routing [0][1] -0 0 +1 # table_routing [0][2] -0 0 +1 # table_routing [0][3] -0 0 +1 # table_routing [1][0] -1 1 +1 # table_routing [1][1] -1 1 +1 # table_routing [1][2] -0 0 +1 # table_routing [1][3] -0 0 +1 # table_routing [2][0] -0 0 +1 # table_routing [2][1] -1 1 +1 # table_routing [2][2] -1 1 +1 # table_routing [2][3] +1 1 +1 # table_routing [0][0][0] +0 0 +1 # table_routing [0][1][0] +0 0 +1 # table_routing [0][2][0] +0 0 +1 # table_routing [0][3][0] +0 0 +1 # table_routing [1][0][0] +1 1 +1 # table_routing [1][1][0] +1 1 +1 # table_routing [1][2][0] +0 0 +1 # table_routing [1][3][0] +0 0 +1 # table_routing [2][0][0] +0 0 +1 # table_routing [2][1][0] +1 1 +1 # table_routing [2][2][0] +1 1 +1 # table_routing [2][3][0] 0 0 +1 # table_execute_type [0][TYPE_ALU ] 0 0 +1 # table_execute_type [0][TYPE_SHIFT ] 0 0 +1 # table_execute_type [0][TYPE_MOVE ] 0 0 +1 # table_execute_type [0][TYPE_TEST ] -0 0 +1 # table_execute_type [0][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [0][TYPE_MUL ] +0 0 +1 # table_execute_type [0][TYPE_DIV ] 0 0 +1 # table_execute_type [0][TYPE_EXTEND ] 0 0 +1 # table_execute_type [0][TYPE_FIND ] @@ -40,5 +48,6 @@ 1 1 +1 # table_execute_type [1][TYPE_MOVE ] 1 1 +1 # table_execute_type [1][TYPE_TEST ] -1 1 +1 # table_execute_type [1][TYPE_MUL_DIV] +1 1 +1 # table_execute_type [1][TYPE_MUL ] +1 1 +1 # table_execute_type [1][TYPE_DIV ] 1 1 +1 # table_execute_type [1][TYPE_EXTEND ] 1 1 +1 # table_execute_type [1][TYPE_FIND ] @@ -51,5 +60,6 @@ 0 0 +1 # table_execute_type [2][TYPE_MOVE ] 0 0 +1 # table_execute_type [2][TYPE_TEST ] -0 0 +1 # table_execute_type [2][TYPE_MUL_DIV] +0 0 +1 # table_execute_type [2][TYPE_MUL ] +0 0 +1 # table_execute_type [2][TYPE_DIV ] 0 0 +1 # table_execute_type [2][TYPE_EXTEND ] 0 0 +1 # table_execute_type [2][TYPE_FIND ] @@ -62,5 +72,6 @@ 1 1 +1 # table_execute_type [3][TYPE_MOVE ] 1 1 +1 # table_execute_type [3][TYPE_TEST ] -1 1 +1 # table_execute_type [3][TYPE_MUL_DIV] +1 1 +1 # table_execute_type [3][TYPE_MUL ] +1 1 +1 # table_execute_type [3][TYPE_DIV ] 0 0 +1 # table_execute_type [3][TYPE_EXTEND ] 0 0 +1 # table_execute_type [3][TYPE_FIND ] @@ -84,3 +95,3 @@ 0 0 +1 # table_execute_thread [3][1] 0 0 +1 # table_execute_thread [3][2] -1 1 +1 # table_execute_thread [3][3] +1 1 +1 # table_execute_thread [3][3] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/main.cpp (revision 88) @@ -15,5 +15,7 @@ err (_("list_params is :\n")); err (_(" * nb_read_unit (uint32_t)\n")); + err (_(" * nb_read_unit_port [nb_read_unit] (uint32_t)\n")); err (_(" * nb_execute_unit (uint32_t)\n")); + err (_(" * nb_execute_unit_port [nb_execute_unit] (uint32_t)\n")); err (_(" * nb_context (uint32_t)\n")); err (_(" * nb_front_end (uint32_t)\n")); @@ -33,5 +35,6 @@ err (_(" * [TYPE_MOVE ]\n")); err (_(" * [TYPE_TEST ]\n")); - err (_(" * [TYPE_MUL_DIV]\n")); + err (_(" * [TYPE_MUL ]\n")); + err (_(" * [TYPE_DIV ]\n")); err (_(" * [TYPE_EXTEND ]\n")); err (_(" * [TYPE_FIND ]\n")); @@ -58,5 +61,25 @@ string name = argv[x++]; uint32_t _nb_read_unit = atoi(argv[x++]); + + if (static_cast(argc) < 2+NB_PARAMS+_nb_read_unit) + usage (argc, argv); + + uint32_t * _nb_read_unit_port = new uint32_t [_nb_read_unit]; + for (uint32_t i=0; i<_nb_read_unit; i++) + _nb_read_unit_port [i] = atoi(argv[x++]); + uint32_t _nb_execute_unit = atoi(argv[x++]); + + if (static_cast(argc) < 2+NB_PARAMS+_nb_read_unit+_nb_execute_unit) + usage (argc, argv); + + uint32_t _sum_execute_unit_port = 0; + uint32_t * _nb_execute_unit_port = new uint32_t [_nb_execute_unit]; + for (uint32_t i=0; i<_nb_execute_unit; i++) + { + _nb_execute_unit_port [i] = atoi(argv[x++]); + _sum_execute_unit_port += _nb_execute_unit_port [i]; + } + uint32_t _nb_context = atoi(argv[x++]); uint32_t _nb_front_end = atoi(argv[x++]); @@ -70,22 +93,30 @@ uint32_t _size_load_queue = atoi(argv[x++]); Tpriority_t _priority = fromString(argv[x++]); - + uint32_t _nb_thread = get_nb_thread(_nb_context, _nb_front_end, _nb_ooo_engine); - if (static_cast(argc) != 2+NB_PARAMS+(_nb_read_unit*_nb_execute_unit)+(_nb_execute_unit*11)+(_nb_execute_unit*_nb_thread)) - usage (argc, argv); - - bool ** _table_routing ; - bool ** _table_execute_type ; - bool ** _table_execute_thread ; - - _table_routing = new bool * [_nb_read_unit]; + msg("%d\n",argc); + msg("%d\n",2+NB_PARAMS+(_nb_read_unit+_nb_execute_unit+(_nb_read_unit*_sum_execute_unit_port)+(_nb_execute_unit*12)+(_nb_execute_unit*_nb_thread))); + + if (static_cast(argc) != 2+NB_PARAMS+(_nb_read_unit+_nb_execute_unit+(_nb_read_unit*_sum_execute_unit_port)+(_nb_execute_unit*12)+(_nb_execute_unit*_nb_thread))) + usage (argc, argv); + + bool *** _table_routing ; + bool ** _table_execute_type ; + bool ** _table_execute_thread ; + + _table_routing = new bool ** [_nb_read_unit]; for (uint32_t i=0; i<_nb_read_unit; i++) { - _table_routing [i] = new bool [_nb_execute_unit]; + _table_routing [i] = new bool * [_nb_execute_unit]; for (uint32_t j=0; j<_nb_execute_unit; j++) - _table_routing [i][j] = atoi(argv[x++]); - } - + { + _table_routing [i][j] = new bool [_nb_execute_unit_port [j]]; + + for (uint32_t k=0; k<_nb_execute_unit_port [j]; k++) + _table_routing [i][j][k] = atoi(argv[x++]); + } + } + _table_execute_type = new bool * [_nb_execute_unit]; for (uint32_t i=0; i<_nb_execute_unit; i++) @@ -97,5 +128,6 @@ _table_execute_type [i][TYPE_MOVE ] = atoi(argv[x++]); _table_execute_type [i][TYPE_TEST ] = atoi(argv[x++]); - _table_execute_type [i][TYPE_MUL_DIV] = atoi(argv[x++]); + _table_execute_type [i][TYPE_MUL ] = atoi(argv[x++]); + _table_execute_type [i][TYPE_DIV ] = atoi(argv[x++]); _table_execute_type [i][TYPE_EXTEND ] = atoi(argv[x++]); _table_execute_type [i][TYPE_FIND ] = atoi(argv[x++]); @@ -119,5 +151,7 @@ morpheo::behavioural::core::multi_execute_loop::execute_loop::network::read_unit_to_execution_unit::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::read_unit_to_execution_unit::Parameters (_nb_read_unit , + _nb_read_unit_port , _nb_execute_unit , + _nb_execute_unit_port , _nb_context , _nb_front_end , @@ -133,5 +167,6 @@ _table_routing , _table_execute_type , - _table_execute_thread + _table_execute_thread , + true // is_toplevel ); @@ -151,7 +186,24 @@ } - delete [] _table_routing ; + delete [] _nb_read_unit_port; + delete [] _nb_execute_unit_port ; + + for (uint32_t i=0; i<_nb_read_unit; i++) + { + for (uint32_t j=0; j<_nb_execute_unit; j++) + delete [] _table_routing [i][j]; + delete [] _table_routing [i]; + } + delete [] _table_routing; + + + for (uint32_t i=0; i<_nb_execute_unit; i++) + delete [] _table_execute_type [i]; delete [] _table_execute_type ; + + for (uint32_t i=0; i<_nb_execute_unit; i++) + delete [] _table_execute_thread [i]; delete [] _table_execute_thread ; + return (EXIT_SUCCESS); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/SelfTest/src/test.cpp (revision 88) @@ -84,4 +84,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Read_unit_to_Execution_unit * _Read_unit_to_Execution_unit = new Read_unit_to_Execution_unit (name.c_str(), @@ -90,5 +100,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -101,42 +111,42 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_VAL ," in_READ_UNIT_OUT_VAL" ,Tcontrol_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_ACK ,"out_READ_UNIT_OUT_ACK" ,Tcontrol_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_CONTEXT_ID ," in_READ_UNIT_OUT_CONTEXT_ID" ,Tcontext_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_FRONT_END_ID ," in_READ_UNIT_OUT_FRONT_END_ID" ,Tcontext_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_OOO_ENGINE_ID ," in_READ_UNIT_OUT_OOO_ENGINE_ID" ,Tcontext_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_PACKET_ID ," in_READ_UNIT_OUT_PACKET_ID" ,Tpacket_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_OPERATION ," in_READ_UNIT_OUT_OPERATION" ,Toperation_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_TYPE ," in_READ_UNIT_OUT_TYPE" ,Ttype_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE," in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_HAS_IMMEDIAT ," in_READ_UNIT_OUT_HAS_IMMEDIAT" ,Tcontrol_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_IMMEDIAT ," in_READ_UNIT_OUT_IMMEDIAT" ,Tgeneral_data_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RA ," in_READ_UNIT_OUT_DATA_RA" ,Tgeneral_data_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RB ," in_READ_UNIT_OUT_DATA_RB" ,Tgeneral_data_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RC ," in_READ_UNIT_OUT_DATA_RC" ,Tspecial_data_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RD ," in_READ_UNIT_OUT_WRITE_RD" ,Tcontrol_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RD ," in_READ_UNIT_OUT_NUM_REG_RD" ,Tgeneral_address_t,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RE ," in_READ_UNIT_OUT_WRITE_RE" ,Tcontrol_t ,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RE ," in_READ_UNIT_OUT_NUM_REG_RE" ,Tspecial_address_t,_param->_nb_read_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_VAL ,"out_EXECUTE_UNIT_IN_VAL" ,Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL( in_EXECUTE_UNIT_IN_ACK ," in_EXECUTE_UNIT_IN_ACK" ,Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_CONTEXT_ID ,"out_EXECUTE_UNIT_IN_CONTEXT_ID" ,Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_FRONT_END_ID ,"out_EXECUTE_UNIT_IN_FRONT_END_ID" ,Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,"out_EXECUTE_UNIT_IN_OOO_ENGINE_ID" ,Tcontext_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_PACKET_ID ,"out_EXECUTE_UNIT_IN_PACKET_ID" ,Tpacket_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_OPERATION ,"out_EXECUTE_UNIT_IN_OPERATION" ,Toperation_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_TYPE ,"out_EXECUTE_UNIT_IN_TYPE" ,Ttype_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,"out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,"out_EXECUTE_UNIT_IN_HAS_IMMEDIAT" ,Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_IMMEDIAT ,"out_EXECUTE_UNIT_IN_IMMEDIAT" ,Tgeneral_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RA ,"out_EXECUTE_UNIT_IN_DATA_RA" ,Tgeneral_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RB ,"out_EXECUTE_UNIT_IN_DATA_RB" ,Tgeneral_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RC ,"out_EXECUTE_UNIT_IN_DATA_RC" ,Tspecial_data_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RD ,"out_EXECUTE_UNIT_IN_WRITE_RD" ,Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RD ,"out_EXECUTE_UNIT_IN_NUM_REG_RD" ,Tgeneral_address_t,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RE ,"out_EXECUTE_UNIT_IN_WRITE_RE" ,Tcontrol_t ,_param->_nb_execute_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RE ,"out_EXECUTE_UNIT_IN_NUM_REG_RE" ,Tspecial_address_t,_param->_nb_execute_unit); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_VAL ," in_READ_UNIT_OUT_VAL" ,Tcontrol_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_READ_UNIT_OUT_ACK ,"out_READ_UNIT_OUT_ACK" ,Tcontrol_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_CONTEXT_ID ," in_READ_UNIT_OUT_CONTEXT_ID" ,Tcontext_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_FRONT_END_ID ," in_READ_UNIT_OUT_FRONT_END_ID" ,Tcontext_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_OOO_ENGINE_ID ," in_READ_UNIT_OUT_OOO_ENGINE_ID" ,Tcontext_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_PACKET_ID ," in_READ_UNIT_OUT_PACKET_ID" ,Tpacket_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_OPERATION ," in_READ_UNIT_OUT_OPERATION" ,Toperation_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_TYPE ," in_READ_UNIT_OUT_TYPE" ,Ttype_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE," in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_HAS_IMMEDIAT ," in_READ_UNIT_OUT_HAS_IMMEDIAT" ,Tcontrol_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_IMMEDIAT ," in_READ_UNIT_OUT_IMMEDIAT" ,Tgeneral_data_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RA ," in_READ_UNIT_OUT_DATA_RA" ,Tgeneral_data_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RB ," in_READ_UNIT_OUT_DATA_RB" ,Tgeneral_data_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RC ," in_READ_UNIT_OUT_DATA_RC" ,Tspecial_data_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RD ," in_READ_UNIT_OUT_WRITE_RD" ,Tcontrol_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RD ," in_READ_UNIT_OUT_NUM_REG_RD" ,Tgeneral_address_t,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RE ," in_READ_UNIT_OUT_WRITE_RE" ,Tcontrol_t ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RE ," in_READ_UNIT_OUT_NUM_REG_RE" ,Tspecial_address_t,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_VAL ,"out_EXECUTE_UNIT_IN_VAL" ,Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_IN_ACK ," in_EXECUTE_UNIT_IN_ACK" ,Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_CONTEXT_ID ,"out_EXECUTE_UNIT_IN_CONTEXT_ID" ,Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_FRONT_END_ID ,"out_EXECUTE_UNIT_IN_FRONT_END_ID" ,Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,"out_EXECUTE_UNIT_IN_OOO_ENGINE_ID" ,Tcontext_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_PACKET_ID ,"out_EXECUTE_UNIT_IN_PACKET_ID" ,Tpacket_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_OPERATION ,"out_EXECUTE_UNIT_IN_OPERATION" ,Toperation_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_TYPE ,"out_EXECUTE_UNIT_IN_TYPE" ,Ttype_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,"out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,"out_EXECUTE_UNIT_IN_HAS_IMMEDIAT" ,Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_IMMEDIAT ,"out_EXECUTE_UNIT_IN_IMMEDIAT" ,Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RA ,"out_EXECUTE_UNIT_IN_DATA_RA" ,Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RB ,"out_EXECUTE_UNIT_IN_DATA_RB" ,Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RC ,"out_EXECUTE_UNIT_IN_DATA_RC" ,Tspecial_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RD ,"out_EXECUTE_UNIT_IN_WRITE_RD" ,Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RD ,"out_EXECUTE_UNIT_IN_NUM_REG_RD" ,Tgeneral_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RE ,"out_EXECUTE_UNIT_IN_WRITE_RE" ,Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RE ,"out_EXECUTE_UNIT_IN_NUM_REG_RE" ,Tspecial_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); @@ -150,53 +160,53 @@ (*(_Read_unit_to_Execution_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_VAL ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_READ_UNIT_OUT_ACK ,_param->_nb_read_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_VAL ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_READ_UNIT_OUT_ACK ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); if (_param->_have_port_context_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_read_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); if (_param->_have_port_front_end_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_read_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); if (_param->_have_port_ooo_engine_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_read_unit); - if (_param->_have_port_packet_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_PACKET_ID ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_OPERATION ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_TYPE ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_PACKET_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_OPERATION ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_TYPE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); if (_param->_have_port_load_queue_ptr) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RA ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RB ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RC ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_WRITE_RD ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_WRITE_RE ,_param->_nb_read_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_read_unit); - - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_VAL ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit, in_EXECUTE_UNIT_IN_ACK ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RA ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RB ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_DATA_RC ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_WRITE_RD ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_WRITE_RE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_VAL ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit, in_EXECUTE_UNIT_IN_ACK ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_context_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_CONTEXT_ID ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_CONTEXT_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_front_end_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_FRONT_END_ID ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_FRONT_END_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_ooo_engine_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,_param->_nb_execute_unit); - if (_param->_have_port_packet_id) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_PACKET_ID ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_OPERATION ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_TYPE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); if (_param->_have_port_load_queue_ptr) - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_IMMEDIAT ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RA ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RB ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RC ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_WRITE_RD ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_NUM_REG_RD ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_WRITE_RE ,_param->_nb_execute_unit); - INSTANCE1_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_NUM_REG_RE ,_param->_nb_execute_unit); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_IMMEDIAT ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RA ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RB ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_DATA_RC ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_WRITE_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + INSTANCE2_SC_SIGNAL(_Read_unit_to_Execution_unit,out_EXECUTE_UNIT_IN_NUM_REG_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -222,15 +232,16 @@ for (uint32_t i=0; i<_param->_nb_read_unit; i++) - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - if (_param->_table_routing[i][j]) - for (uint32_t k=0; k<_param->_nb_thread; k++) - if (_param->_table_execute_thread[j][k]) - { - read_unit_thread [i].insert(k); - - for (uint32_t l=0; l<_param->_nb_type; l++) - if (_param->_table_execute_type[j][l]) - read_unit_type [i][k].insert(l); - } + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + if (_param->_table_routing[i][x][y]) + for (uint32_t k=0; k<_param->_nb_thread; k++) + if (_param->_table_execute_thread[x][k]) + { + read_unit_thread [i].insert(k); + + for (uint32_t l=0; l<_param->_nb_type; l++) + if (_param->_table_execute_type[x][l]) + read_unit_type [i][k].insert(l); + } //bool ** _table_routing ; //array [nb_read_unit][nb_execute_unit] //bool ** _table_execute_type ; //array [nb_execute_unit][nb_type] @@ -251,60 +262,61 @@ LABEL("Iteration %d",iteration); - list request [_param->_nb_read_unit]; + list request [_param->_nb_read_unit][_param->_max_nb_read_unit_port]; uint32_t nb_request_in; for (nb_request_in=0; nb_request_in < _param->_nb_packet; ) for (uint32_t i=0; i<_param->_nb_read_unit; i++) - { - if (nb_request_in >= _param->_nb_packet) - break; - - Tcontext_t context_id ; - Tcontext_t front_end_id ; - Tcontext_t ooo_engine_id; - Tcontext_t num_thread ; - - // Find compatible thread - do - { - context_id = range (rand(), _param->_size_context_id ); - front_end_id = range (rand(), _param->_size_front_end_id ); - ooo_engine_id = range (rand(), _param->_size_ooo_engine_id); - num_thread = get_num_thread (context_id , _param->_size_context_id , - front_end_id , _param->_size_front_end_id , - ooo_engine_id, _param->_size_ooo_engine_id); - } - while (read_unit_thread[i].find(num_thread) == read_unit_thread[i].end()); - - Ttype_t type; - - // Find a compatible type - do - { - type = range (rand(), _param->_size_type); - } - while (read_unit_type[i][num_thread].find(type) == read_unit_type[i][num_thread].end()); - - request[i].push_back(entry_t (context_id , - front_end_id , - ooo_engine_id, - nb_request_in, - range (rand(), _param->_size_operation ), - type, - range (rand(), _param->_size_store_queue ), - range (rand(), _param->_size_load_queue ), - range (rand(), 2 ), - range (rand(), _param->_size_general_data ), - range (rand(), _param->_size_general_data ), - range (rand(), _param->_size_general_data ), - range (rand(), _param->_size_special_data ), - range (rand(), 2 ), - range (rand(), _param->_size_general_register), - range (rand(), 2 ), - range (rand(), _param->_size_special_register) - )); - - nb_request_in++; - } + for (uint32_t j=0; j<_param->_nb_read_unit_port [i]; j++) + { + if (nb_request_in >= _param->_nb_packet) + break; + + Tcontext_t context_id ; + Tcontext_t front_end_id ; + Tcontext_t ooo_engine_id; + Tcontext_t num_thread ; + + // Find compatible thread + do + { + context_id = range (rand(), _param->_size_context_id ); + front_end_id = range (rand(), _param->_size_front_end_id ); + ooo_engine_id = range (rand(), _param->_size_ooo_engine_id); + num_thread = get_num_thread (context_id , _param->_size_context_id , + front_end_id , _param->_size_front_end_id , + ooo_engine_id, _param->_size_ooo_engine_id); + } + while (read_unit_thread[i].find(num_thread) == read_unit_thread[i].end()); + + Ttype_t type; + + // Find a compatible type + do + { + type = range (rand(), _param->_size_type); + } + while (read_unit_type[i][num_thread].find(type) == read_unit_type[i][num_thread].end()); + + request[i][j].push_back(entry_t (context_id , + front_end_id , + ooo_engine_id, + nb_request_in, + range (rand(), _param->_size_operation ), + type, + range (rand(), (1<<_param->_size_store_queue_ptr)), + range (rand(), (1<<_param->_size_load_queue_ptr )), + range (rand(), 2 ), + range (rand(), _param->_size_general_data ), + range (rand(), _param->_size_general_data ), + range (rand(), _param->_size_general_data ), + range (rand(), _param->_size_special_data ), + range (rand(), 2 ), + range (rand(), _param->_size_general_register), + range (rand(), 2 ), + range (rand(), _param->_size_special_register) + )); + + nb_request_in++; + } uint32_t nb_request_out = 0; @@ -313,92 +325,105 @@ { for (uint32_t i=0; i<_param->_nb_read_unit; i++) - { - bool val = not request[i].empty() and ((rand()%100) < percent_transaction_in); + for (uint32_t j=0; j<_param->_nb_read_unit_port [i]; j++) + { + bool val = not request[i][j].empty() and ((rand()%100) < percent_transaction_in); - in_READ_UNIT_OUT_VAL [i]->write(val); - - if (val) + in_READ_UNIT_OUT_VAL [i][j]->write(val); + + if (val) { - in_READ_UNIT_OUT_CONTEXT_ID [i] ->write(request[i].front()._context_id ); - in_READ_UNIT_OUT_FRONT_END_ID [i] ->write(request[i].front()._front_end_id ); - in_READ_UNIT_OUT_OOO_ENGINE_ID [i] ->write(request[i].front()._ooo_engine_id ); - in_READ_UNIT_OUT_PACKET_ID [i] ->write(request[i].front()._packet_id ); - in_READ_UNIT_OUT_OPERATION [i] ->write(request[i].front()._operation ); - in_READ_UNIT_OUT_TYPE [i] ->write(request[i].front()._type ); - in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE[i] ->write(request[i].front()._store_queue_ptr_write); + in_READ_UNIT_OUT_CONTEXT_ID [i][j] ->write(request[i][j].front()._context_id ); + in_READ_UNIT_OUT_FRONT_END_ID [i][j] ->write(request[i][j].front()._front_end_id ); + in_READ_UNIT_OUT_OOO_ENGINE_ID [i][j] ->write(request[i][j].front()._ooo_engine_id ); + in_READ_UNIT_OUT_PACKET_ID [i][j] ->write(request[i][j].front()._packet_id ); + in_READ_UNIT_OUT_OPERATION [i][j] ->write(request[i][j].front()._operation ); + in_READ_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type ); + in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE[i][j] ->write(request[i][j].front()._store_queue_ptr_write); if (_param->_have_port_load_queue_ptr) - in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i] ->write(request[i].front()._load_queue_ptr_write ); - in_READ_UNIT_OUT_HAS_IMMEDIAT [i] ->write(request[i].front()._has_immediat ); - in_READ_UNIT_OUT_IMMEDIAT [i] ->write(request[i].front()._immediat ); - in_READ_UNIT_OUT_DATA_RA [i] ->write(request[i].front()._data_ra ); - in_READ_UNIT_OUT_DATA_RB [i] ->write(request[i].front()._data_rb ); - in_READ_UNIT_OUT_DATA_RC [i] ->write(request[i].front()._data_rc ); - in_READ_UNIT_OUT_WRITE_RD [i] ->write(request[i].front()._write_rd ); - in_READ_UNIT_OUT_NUM_REG_RD [i] ->write(request[i].front()._num_reg_rd ); - in_READ_UNIT_OUT_WRITE_RE [i] ->write(request[i].front()._write_re ); - in_READ_UNIT_OUT_NUM_REG_RE [i] ->write(request[i].front()._num_reg_re ); + in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i][j] ->write(request[i][j].front()._load_queue_ptr_write ); + in_READ_UNIT_OUT_HAS_IMMEDIAT [i][j] ->write(request[i][j].front()._has_immediat ); + in_READ_UNIT_OUT_IMMEDIAT [i][j] ->write(request[i][j].front()._immediat ); + in_READ_UNIT_OUT_DATA_RA [i][j] ->write(request[i][j].front()._data_ra ); + in_READ_UNIT_OUT_DATA_RB [i][j] ->write(request[i][j].front()._data_rb ); + in_READ_UNIT_OUT_DATA_RC [i][j] ->write(request[i][j].front()._data_rc ); + in_READ_UNIT_OUT_WRITE_RD [i][j] ->write(request[i][j].front()._write_rd ); + in_READ_UNIT_OUT_NUM_REG_RD [i][j] ->write(request[i][j].front()._num_reg_rd ); + in_READ_UNIT_OUT_WRITE_RE [i][j] ->write(request[i][j].front()._write_re ); + in_READ_UNIT_OUT_NUM_REG_RE [i][j] ->write(request[i][j].front()._num_reg_re ); } - } + } for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - in_EXECUTE_UNIT_IN_ACK [i]->write((rand()%100) < percent_transaction_out); + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + in_EXECUTE_UNIT_IN_ACK [i][j]->write((rand()%100) < percent_transaction_out); SC_START(0); for (uint32_t i=0; i<_param->_nb_read_unit; i++) - if (in_READ_UNIT_OUT_VAL [i]->read() and out_READ_UNIT_OUT_ACK [i]->read()) - { - LABEL("READ_UNIT_OUT [%d] - Transaction accepted",i); - } + for (uint32_t j=0; j<_param->_nb_read_unit_port [i]; j++) + if (in_READ_UNIT_OUT_VAL [i][j]->read() and out_READ_UNIT_OUT_ACK [i][j]->read()) + { + LABEL("READ_UNIT_OUT [%d][%d] - Transaction accepted",i,j); + } for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - if (out_EXECUTE_UNIT_IN_VAL [i]->read() and in_EXECUTE_UNIT_IN_ACK [i]->read()) - { - LABEL("EXECUTE_UNIT_IN [%d] - Transaction accepted (%d)",i,nb_request_out); - nb_request_out ++; - - Tpacket_t packet = (_param->_have_port_packet_id)?out_EXECUTE_UNIT_IN_PACKET_ID[i]->read():0; - LABEL(" * packet : %d",packet); - uint32_t read_unit; - - // find read_unit - for (read_unit=0; read_unit<_param->_nb_read_unit; read_unit++) - if (packet == ((_param->_have_port_packet_id)?request[read_unit].front()._packet_id:0)) - break; - - LABEL(" * read_unit source : %d",read_unit); - - if (_param->_have_port_packet_id) - TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_PACKET_ID [i]->read(), request[read_unit].front()._packet_id ); - - // Authorised link ? read_unit -> execute_unit - TEST(bool, _param->_table_routing[read_unit][i], true); - - if (_param->_have_port_context_id) - TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_CONTEXT_ID [i]->read(), request[read_unit].front()._context_id ); - if (_param->_have_port_front_end_id) - TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_FRONT_END_ID [i]->read(), request[read_unit].front()._front_end_id ); - if (_param->_have_port_ooo_engine_id) - TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i]->read(), request[read_unit].front()._ooo_engine_id ); - TEST(Toperation_t ,out_EXECUTE_UNIT_IN_OPERATION [i]->read(), request[read_unit].front()._operation ); - TEST(Ttype_t ,out_EXECUTE_UNIT_IN_TYPE [i]->read(), request[read_unit].front()._type ); - TEST(Tlsq_ptr_t ,out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE[i]->read(), request[read_unit].front()._store_queue_ptr_write); - if (_param->_have_port_load_queue_ptr) - TEST(Tlsq_ptr_t ,out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i]->read(), request[read_unit].front()._load_queue_ptr_write ); - TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i]->read(), request[read_unit].front()._has_immediat ); - TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_IMMEDIAT [i]->read(), request[read_unit].front()._immediat ); - TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_DATA_RA [i]->read(), request[read_unit].front()._data_ra ); - TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_DATA_RB [i]->read(), request[read_unit].front()._data_rb ); - TEST(Tspecial_data_t ,out_EXECUTE_UNIT_IN_DATA_RC [i]->read(), request[read_unit].front()._data_rc ); - TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_WRITE_RD [i]->read(), request[read_unit].front()._write_rd ); - TEST(Tgeneral_address_t,out_EXECUTE_UNIT_IN_NUM_REG_RD [i]->read(), request[read_unit].front()._num_reg_rd ); - TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_WRITE_RE [i]->read(), request[read_unit].front()._write_re ); - TEST(Tspecial_address_t,out_EXECUTE_UNIT_IN_NUM_REG_RE [i]->read(), request[read_unit].front()._num_reg_re ); - - request[read_unit].pop_front(); - } + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + if (out_EXECUTE_UNIT_IN_VAL [i][j]->read() and in_EXECUTE_UNIT_IN_ACK [i][j]->read()) + { + LABEL("EXECUTE_UNIT_IN [%d][%d] - Transaction accepted (%d)",i,j,nb_request_out); + nb_request_out ++; + + Tpacket_t packet = (_param->_have_port_rob_ptr )?out_EXECUTE_UNIT_IN_PACKET_ID[i][j]->read():0; + LABEL(" * packet : %d",packet); + uint32_t x; + uint32_t y; + + // find read_unit + bool find = false; + for (x=0; x<_param->_nb_read_unit; x++) + { + for (y=0; y<_param->_nb_read_unit_port[x]; y++) + if (packet == ((_param->_have_port_rob_ptr )?request[x][y].front()._packet_id:0)) + { + find = true; + break; + } + if (find) + break; + } + + LABEL(" * read_unit source : [%d][%d]",x,y); + + if (_param->_have_port_rob_ptr ) + TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_PACKET_ID [i][j]->read(), request[x][y].front()._packet_id ); + + // Authorised link ? read_unit -> execute_unit + TEST(bool, _param->_table_routing[x][i][j], true); + + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j]->read(), request[x][y].front()._context_id ); + if (_param->_have_port_front_end_id) + TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j]->read(), request[x][y].front()._front_end_id ); + if (_param->_have_port_ooo_engine_id) + TEST(Tcontext_t ,out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j]->read(), request[x][y].front()._ooo_engine_id ); + TEST(Toperation_t ,out_EXECUTE_UNIT_IN_OPERATION [i][j]->read(), request[x][y].front()._operation ); + TEST(Ttype_t ,out_EXECUTE_UNIT_IN_TYPE [i][j]->read(), request[x][y].front()._type ); + TEST(Tlsq_ptr_t ,out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE[i][j]->read(), request[x][y].front()._store_queue_ptr_write); + if (_param->_have_port_load_queue_ptr) + TEST(Tlsq_ptr_t ,out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j]->read(), request[x][y].front()._load_queue_ptr_write ); + TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j]->read(), request[x][y].front()._has_immediat ); + TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_IMMEDIAT [i][j]->read(), request[x][y].front()._immediat ); + TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_DATA_RA [i][j]->read(), request[x][y].front()._data_ra ); + TEST(Tgeneral_data_t ,out_EXECUTE_UNIT_IN_DATA_RB [i][j]->read(), request[x][y].front()._data_rb ); + TEST(Tspecial_data_t ,out_EXECUTE_UNIT_IN_DATA_RC [i][j]->read(), request[x][y].front()._data_rc ); + TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_WRITE_RD [i][j]->read(), request[x][y].front()._write_rd ); + TEST(Tgeneral_address_t,out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j]->read(), request[x][y].front()._num_reg_rd ); + TEST(Tcontrol_t ,out_EXECUTE_UNIT_IN_WRITE_RE [i][j]->read(), request[x][y].front()._write_re ); + TEST(Tspecial_address_t,out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j]->read(), request[x][y].front()._num_reg_re ); + + request[x][y].pop_front(); + } SC_START(1); } - } @@ -414,44 +439,43 @@ delete in_CLOCK; delete in_NRESET; - - delete [] in_READ_UNIT_OUT_VAL ; - delete [] out_READ_UNIT_OUT_ACK ; - delete [] in_READ_UNIT_OUT_CONTEXT_ID ; - delete [] in_READ_UNIT_OUT_FRONT_END_ID ; - delete [] in_READ_UNIT_OUT_OOO_ENGINE_ID ; - delete [] in_READ_UNIT_OUT_PACKET_ID ; - delete [] in_READ_UNIT_OUT_OPERATION ; - delete [] in_READ_UNIT_OUT_TYPE ; - delete [] in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE; - delete [] in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ; - delete [] in_READ_UNIT_OUT_HAS_IMMEDIAT ; - delete [] in_READ_UNIT_OUT_IMMEDIAT ; - delete [] in_READ_UNIT_OUT_DATA_RA ; - delete [] in_READ_UNIT_OUT_DATA_RB ; - delete [] in_READ_UNIT_OUT_DATA_RC ; - delete [] in_READ_UNIT_OUT_WRITE_RD ; - delete [] in_READ_UNIT_OUT_NUM_REG_RD ; - delete [] in_READ_UNIT_OUT_WRITE_RE ; - delete [] in_READ_UNIT_OUT_NUM_REG_RE ; - - delete [] out_EXECUTE_UNIT_IN_VAL ; - delete [] in_EXECUTE_UNIT_IN_ACK ; - delete [] out_EXECUTE_UNIT_IN_CONTEXT_ID ; - delete [] out_EXECUTE_UNIT_IN_FRONT_END_ID ; - delete [] out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ; - delete [] out_EXECUTE_UNIT_IN_PACKET_ID ; - delete [] out_EXECUTE_UNIT_IN_OPERATION ; - delete [] out_EXECUTE_UNIT_IN_TYPE ; - delete [] out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE; - delete [] out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ; - delete [] out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ; - delete [] out_EXECUTE_UNIT_IN_IMMEDIAT ; - delete [] out_EXECUTE_UNIT_IN_DATA_RA ; - delete [] out_EXECUTE_UNIT_IN_DATA_RB ; - delete [] out_EXECUTE_UNIT_IN_DATA_RC ; - delete [] out_EXECUTE_UNIT_IN_WRITE_RD ; - delete [] out_EXECUTE_UNIT_IN_NUM_REG_RD ; - delete [] out_EXECUTE_UNIT_IN_WRITE_RE ; - delete [] out_EXECUTE_UNIT_IN_NUM_REG_RE ; + + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_VAL ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL(out_READ_UNIT_OUT_ACK ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_PACKET_ID ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_OPERATION ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_TYPE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RA ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RB ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_DATA_RC ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RD ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_WRITE_RE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_VAL ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_IN_ACK ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_CONTEXT_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_FRONT_END_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_IMMEDIAT ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RA ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RB ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RC ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Parameters.h (revision 88) @@ -26,41 +26,47 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _nb_read_unit ; - public : const uint32_t _nb_execute_unit ; - public : const uint32_t _nb_context ; - public : const uint32_t _nb_front_end ; - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _nb_packet ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_general_register ; - public : const uint32_t _nb_special_register ; - public : const uint32_t _size_store_queue ; - public : const uint32_t _size_load_queue ; - public : const Tpriority_t _priority ; - public : bool ** _table_routing ; //[nb_read_unit][nb_execute_unit] - public : bool ** _table_execute_type ; //[nb_execute_unit][nb_type] - public : bool ** _table_execute_thread ; //[nb_execute_unit][nb_thread] + public : uint32_t _nb_read_unit ; + public : uint32_t * _nb_read_unit_port ;//[nb_read_unit] + public : uint32_t _nb_execute_unit ; + public : uint32_t * _nb_execute_unit_port ;//[nb_execute_unit] + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_ooo_engine ; + public : uint32_t _nb_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; +//public : uint32_t _size_store_queue ; +//public : uint32_t _size_load_queue ; + public : Tpriority_t _priority ; + public : bool *** _table_routing ; //[nb_read_unit][nb_execute_unit][nb_execute_unit_port] + public : bool ** _table_execute_type ; //[nb_execute_unit][nb_type] + public : bool ** _table_execute_thread ; //[nb_execute_unit][nb_thread] - public : const uint32_t _size_context_id ; - public : const uint32_t _size_front_end_id ; - public : const uint32_t _size_ooo_engine_id ; - public : const uint32_t _size_packet_id ; - public : const uint32_t _size_general_register ; - public : const uint32_t _size_special_register ; + public : uint32_t _max_nb_read_unit_port ; + public : uint32_t _max_nb_execute_unit_port; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : const bool _have_port_context_id ; - public : const bool _have_port_front_end_id ; - public : const bool _have_port_ooo_engine_id; - public : const bool _have_port_packet_id ; - public : const bool _have_port_load_queue_ptr; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr; - public : const uint32_t _nb_thread ; - public : uint32_t _nb_load_store_unit ; - public : uint32_t _nb_functionnal_unit ; + public : uint32_t _nb_thread ; + public : uint32_t _nb_load_store_unit ; + public : uint32_t _nb_functionnal_unit ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_read_unit , + uint32_t * nb_read_unit_port , uint32_t nb_execute_unit , + uint32_t * nb_execute_unit_port , uint32_t nb_context , uint32_t nb_front_end , @@ -74,9 +80,12 @@ uint32_t size_load_queue , Tpriority_t priority , - bool ** table_routing , + bool *** table_routing , bool ** table_execute_type , - bool ** table_execute_thread ); - public : Parameters (Parameters & param) ; + bool ** table_execute_thread , + bool is_toplevel=false ); +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h (revision 88) @@ -39,4 +39,15 @@ namespace read_unit_to_execution_unit { + class destination_t + { + public : uint32_t grp; + public : uint32_t elt; + + public : destination_t (uint32_t grp, uint32_t elt) + { + this->grp = grp; + this->elt = elt; + } + }; class Read_unit_to_Execution_unit @@ -65,44 +76,44 @@ // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_READ_UNIT_OUT_VAL ; - public : SC_OUT(Tcontrol_t ) ** out_READ_UNIT_OUT_ACK ; - public : SC_IN (Tcontext_t ) ** in_READ_UNIT_OUT_CONTEXT_ID ; - public : SC_IN (Tcontext_t ) ** in_READ_UNIT_OUT_FRONT_END_ID ; - public : SC_IN (Tcontext_t ) ** in_READ_UNIT_OUT_OOO_ENGINE_ID ; - public : SC_IN (Tpacket_t ) ** in_READ_UNIT_OUT_PACKET_ID ; - public : SC_IN (Toperation_t ) ** in_READ_UNIT_OUT_OPERATION ; - public : SC_IN (Ttype_t ) ** in_READ_UNIT_OUT_TYPE ; - public : SC_IN (Tlsq_ptr_t ) ** in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE; - public : SC_IN (Tlsq_ptr_t ) ** in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ; - public : SC_IN (Tcontrol_t ) ** in_READ_UNIT_OUT_HAS_IMMEDIAT ; - public : SC_IN (Tgeneral_data_t ) ** in_READ_UNIT_OUT_IMMEDIAT ; - public : SC_IN (Tgeneral_data_t ) ** in_READ_UNIT_OUT_DATA_RA ; - public : SC_IN (Tgeneral_data_t ) ** in_READ_UNIT_OUT_DATA_RB ; - public : SC_IN (Tspecial_data_t ) ** in_READ_UNIT_OUT_DATA_RC ; - public : SC_IN (Tcontrol_t ) ** in_READ_UNIT_OUT_WRITE_RD ; - public : SC_IN (Tgeneral_address_t) ** in_READ_UNIT_OUT_NUM_REG_RD ; - public : SC_IN (Tcontrol_t ) ** in_READ_UNIT_OUT_WRITE_RE ; - public : SC_IN (Tspecial_address_t) ** in_READ_UNIT_OUT_NUM_REG_RE ; + public : SC_IN (Tcontrol_t ) *** in_READ_UNIT_OUT_VAL ;//[nb_read_unit][nb_read_unit_port] + public : SC_OUT(Tcontrol_t ) *** out_READ_UNIT_OUT_ACK ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontext_t ) *** in_READ_UNIT_OUT_CONTEXT_ID ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontext_t ) *** in_READ_UNIT_OUT_FRONT_END_ID ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontext_t ) *** in_READ_UNIT_OUT_OOO_ENGINE_ID ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tpacket_t ) *** in_READ_UNIT_OUT_PACKET_ID ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Toperation_t ) *** in_READ_UNIT_OUT_OPERATION ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Ttype_t ) *** in_READ_UNIT_OUT_TYPE ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tlsq_ptr_t ) *** in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tlsq_ptr_t ) *** in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontrol_t ) *** in_READ_UNIT_OUT_HAS_IMMEDIAT ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tgeneral_data_t ) *** in_READ_UNIT_OUT_IMMEDIAT ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tgeneral_data_t ) *** in_READ_UNIT_OUT_DATA_RA ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tgeneral_data_t ) *** in_READ_UNIT_OUT_DATA_RB ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tspecial_data_t ) *** in_READ_UNIT_OUT_DATA_RC ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontrol_t ) *** in_READ_UNIT_OUT_WRITE_RD ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tgeneral_address_t) *** in_READ_UNIT_OUT_NUM_REG_RD ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tcontrol_t ) *** in_READ_UNIT_OUT_WRITE_RE ;//[nb_read_unit][nb_read_unit_port] + public : SC_IN (Tspecial_address_t) *** in_READ_UNIT_OUT_NUM_REG_RE ;//[nb_read_unit][nb_read_unit_port] // ~~~~~[ Interface "execute_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_UNIT_IN_VAL ; - public : SC_IN (Tcontrol_t ) ** in_EXECUTE_UNIT_IN_ACK ; - public : SC_OUT(Tcontext_t ) ** out_EXECUTE_UNIT_IN_CONTEXT_ID ; - public : SC_OUT(Tcontext_t ) ** out_EXECUTE_UNIT_IN_FRONT_END_ID ; - public : SC_OUT(Tcontext_t ) ** out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ; - public : SC_OUT(Tpacket_t ) ** out_EXECUTE_UNIT_IN_PACKET_ID ; - public : SC_OUT(Toperation_t ) ** out_EXECUTE_UNIT_IN_OPERATION ; - public : SC_OUT(Ttype_t ) ** out_EXECUTE_UNIT_IN_TYPE ; - public : SC_OUT(Tlsq_ptr_t ) ** out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE; - public : SC_OUT(Tlsq_ptr_t ) ** out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ; - public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ; - public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_UNIT_IN_IMMEDIAT ; - public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_UNIT_IN_DATA_RA ; - public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_UNIT_IN_DATA_RB ; - public : SC_OUT(Tspecial_data_t ) ** out_EXECUTE_UNIT_IN_DATA_RC ; - public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_UNIT_IN_WRITE_RD ; - public : SC_OUT(Tgeneral_address_t) ** out_EXECUTE_UNIT_IN_NUM_REG_RD ; - public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_UNIT_IN_WRITE_RE ; - public : SC_OUT(Tspecial_address_t) ** out_EXECUTE_UNIT_IN_NUM_REG_RE ; + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_UNIT_IN_VAL ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_IN_ACK ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontext_t ) *** out_EXECUTE_UNIT_IN_CONTEXT_ID ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontext_t ) *** out_EXECUTE_UNIT_IN_FRONT_END_ID ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontext_t ) *** out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tpacket_t ) *** out_EXECUTE_UNIT_IN_PACKET_ID ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Toperation_t ) *** out_EXECUTE_UNIT_IN_OPERATION ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Ttype_t ) *** out_EXECUTE_UNIT_IN_TYPE ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tlsq_ptr_t ) *** out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tlsq_ptr_t ) *** out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tgeneral_data_t ) *** out_EXECUTE_UNIT_IN_IMMEDIAT ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tgeneral_data_t ) *** out_EXECUTE_UNIT_IN_DATA_RA ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tgeneral_data_t ) *** out_EXECUTE_UNIT_IN_DATA_RB ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tspecial_data_t ) *** out_EXECUTE_UNIT_IN_DATA_RC ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_UNIT_IN_WRITE_RD ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tgeneral_address_t) *** out_EXECUTE_UNIT_IN_NUM_REG_RD ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_UNIT_IN_WRITE_RE ;//[nb_execute_unit][nb_execute_unit_port] + public : SC_OUT(Tspecial_address_t) *** out_EXECUTE_UNIT_IN_NUM_REG_RE ;//[nb_execute_unit][nb_execute_unit_port] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -111,5 +122,5 @@ // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : std::list *** _destination; // [nb_read_unit][nb_thread][nb_type]; + private : std::list *** _destination; // [nb_read_unit][nb_thread][nb_type]; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Parameters.h" +#include "Common/include/Max.h" namespace morpheo { @@ -20,5 +21,7 @@ #define FUNCTION "Read_unit_to_Execution_unit::Parameters" Parameters::Parameters (uint32_t nb_read_unit , + uint32_t * nb_read_unit_port , uint32_t nb_execute_unit , + uint32_t * nb_execute_unit_port , uint32_t nb_context , uint32_t nb_front_end , @@ -32,43 +35,31 @@ uint32_t size_load_queue , Tpriority_t priority , - bool ** table_routing , + bool *** table_routing , bool ** table_execute_type , - bool ** table_execute_thread ): - _nb_read_unit (nb_read_unit ), - _nb_execute_unit (nb_execute_unit ), - _nb_context (nb_context ), - _nb_front_end (nb_front_end ), - _nb_ooo_engine (nb_ooo_engine ), - _nb_packet (nb_packet ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_general_register (nb_general_register), - _nb_special_register (nb_special_register), - _size_store_queue (size_store_queue ), - _size_load_queue (size_load_queue ), - _priority (priority ), - - _size_context_id (log2(nb_context )), - _size_front_end_id (log2(nb_front_end )), - _size_ooo_engine_id (log2(nb_ooo_engine )), - _size_packet_id (log2(nb_packet )), - _size_general_register (log2(nb_general_register)), - _size_special_register (log2(nb_special_register)), - - _have_port_context_id (_size_context_id > 0), - _have_port_front_end_id (_size_front_end_id > 0), - _have_port_ooo_engine_id (_size_ooo_engine_id > 0), - _have_port_packet_id (_size_packet_id > 0), - _have_port_load_queue_ptr(_size_load_queue > 1), - - _nb_thread (get_nb_thread (nb_context, nb_front_end, nb_ooo_engine)) + bool ** table_execute_thread , + bool is_toplevel ) { log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); - _table_routing = table_routing ; - _table_execute_type = table_execute_type ; - _table_execute_thread = table_execute_thread; + _nb_read_unit = nb_read_unit ; + _nb_read_unit_port = nb_read_unit_port ; + _nb_execute_unit = nb_execute_unit ; + _nb_execute_unit_port = nb_execute_unit_port; + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _priority = priority ; + _table_routing = table_routing ; + _table_execute_type = table_execute_type ; + _table_execute_thread = table_execute_thread; - _nb_load_store_unit = 0; + _max_nb_read_unit_port = max(_nb_read_unit_port, _nb_read_unit); + _max_nb_execute_unit_port= max(_nb_execute_unit_port, _nb_execute_unit); + + _nb_thread = get_nb_thread (nb_context, nb_front_end, nb_ooo_engine); + _nb_load_store_unit = 0; for (uint32_t i=0; i 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr= _size_load_queue_ptr> 0; + + copy(); + } + log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Read_unit_to_Execution_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); + +// test(); +// log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Read_unit_to_Execution_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _nb_read_unit (param._nb_read_unit ), - _nb_execute_unit (param._nb_execute_unit ), - _nb_context (param._nb_context ), - _nb_front_end (param._nb_front_end ), - _nb_ooo_engine (param._nb_ooo_engine ), - _nb_packet (param._nb_packet ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _size_store_queue (param._size_store_queue ), - _size_load_queue (param._size_load_queue ), - _priority (param._priority ), - - _size_context_id (param._size_context_id ), - _size_front_end_id (param._size_front_end_id ), - _size_ooo_engine_id (param._size_ooo_engine_id ), - _size_packet_id (param._size_packet_id ), - _size_general_register (param._size_general_register ), - _size_special_register (param._size_special_register ), - - _have_port_context_id (param._have_port_context_id ), - _have_port_front_end_id (param._have_port_front_end_id ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id), - _have_port_packet_id (param._have_port_packet_id ), - _have_port_load_queue_ptr(param._have_port_load_queue_ptr), - - _nb_thread (param._nb_thread ) +#define FUNCTION "Read_unit_to_Execution_unit::~Parameters" + Parameters::~Parameters () { log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); - - _table_routing = param._table_routing ; - _table_execute_type = param._table_execute_type ; - _table_execute_thread = param._table_execute_thread; - _nb_load_store_unit = param._nb_load_store_unit ; - _nb_functionnal_unit = param._nb_functionnal_unit ; - - test(); log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Read_unit_to_Execution_unit::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Read_unit_to_Execution_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp (revision 88) @@ -33,5 +33,6 @@ // TYPE_MOVE | X | | | cmov is optionnal // TYPE_TEST | X | | | - // TYPE_MUL_DIV | X | | | div is optionnal + // TYPE_MUL | X | | | + // TYPE_DIV | X | X | | // TYPE_EXTEND | X | X | | // TYPE_FIND | X | X | | @@ -58,5 +59,6 @@ type_valid [TYPE_MOVE ] = true; type_valid [TYPE_TEST ] = true; - type_valid [TYPE_MUL_DIV] = true; + type_valid [TYPE_MUL ] = true; + type_valid [TYPE_DIV ] = true; type_valid [TYPE_EXTEND ] = true; type_valid [TYPE_FIND ] = true; @@ -70,4 +72,5 @@ type_uniq [TYPE_MEMORY ] = true; + type_optionnal [TYPE_DIV ] = true; type_optionnal [TYPE_EXTEND ] = true; type_optionnal [TYPE_FIND ] = true; @@ -85,13 +88,21 @@ if (_table_execute_thread [i][j] == true) // this execute_unit execute this thread ! - for (Ttype_t k=0; k<=_nb_type; k++) - if (_table_execute_type[i][k] == true) - { - // Test uniq type - if (type_present [j][k] and type_uniq[k]) - test.error("The execute_unit '"+toString(i)+"' can execute operation of type '"+toString_type(k)+"' at the thread '"+toString(j)+"'. But an another execute_unit can be execute the same type for the same thread. And the type must be uniq !."); - - type_present [j][k] = true; - } + for (Ttype_t k=0; k<_nb_type; k++) + if (_table_execute_type[i][k] == true) + { +// test.information(toString(_("Execute_unit [%d], Thread [%d], Type [%d], type_valid %d, type_present %d, type_uniq %d\n"),i,j,k,type_valid[k],type_present[j][k],type_uniq[k])); + + // Test uniq type + if (type_present [j][k] and type_uniq[k]) + test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString_type(k).c_str(),j)); + + type_present [j][k] = true; + } + + for (Ttype_t j=0; j<_nb_type; j++) + if (not type_valid [j]) + for (uint32_t i=0; i<_nb_thread; i++) + if (type_present [i][j]) + test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString_type(j).c_str())); for (Ttype_t j=0; j<_nb_type; j++) @@ -99,14 +110,14 @@ for (uint32_t i=0; i<_nb_thread; i++) if (not type_present [i][j]) - test.error("The thread '"+toString(i)+"' can't access at the execute_unit to execute the type's operation '"+toString_type(j)+"' (and this type is not optionnal !)."); + test.error(toString(_("The thread '%d' can't access at the execute_unit to execute the type's operation '%s' (and this type is not optional !).\n"),i,toString_type(j).c_str())); // Test all excluve type for (uint32_t i=0; i<_nb_execute_unit; i++) - for (Ttype_t j=0; j<=_nb_type; j++) + for (Ttype_t j=0; j<_nb_type; j++) if (type_exclusive [j] and _table_execute_type[i][j]) - for (Ttype_t k=0; k<=_nb_type; k++) + for (Ttype_t k=0; k<_nb_type; k++) if ((j != k) and (_table_execute_type[i][k] == true)) { - test.error("The execute_unit ["+toString(i)+"] implement the type '"+toString_type(j)+"', and this type is exclusive with all others type."); + test.error(toString(_("The execute_unit [%d] implement the type '%s', and this type is exclusive with all others type.\n"),i,toString_type(j).c_str())); break; } @@ -120,10 +131,10 @@ if (j == _nb_thread) - test.error("The execute_unit ["+toString(i)+"] have none source's thread."); + test.error(toString(_("The execute_unit [%d] have none source's thread.\n"),i)); } if ( (_priority != PRIORITY_STATIC ) and (_priority != PRIORITY_ROUND_ROBIN)) - test.error("Unsupported priority scheme. It must be Static or Round Robin."); + test.error(_("Unsupported priority scheme. It must be Static or Round Robin.\n")); log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_print.cpp (revision 88) @@ -37,6 +37,6 @@ xml.singleton_begin("nb_general_register"); xml.attribut("value",toString(_nb_general_register)); xml.singleton_end(); xml.singleton_begin("nb_special_register"); xml.attribut("value",toString(_nb_special_register)); xml.singleton_end(); - xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); - xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); +// xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue )); xml.singleton_end(); +// xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue )); xml.singleton_end(); xml.singleton_begin("priority "); xml.attribut("value",toString(_priority )); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); +#if DEBUG_Read_unit_to_Execution_unit == true + log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,"Method - transition"); @@ -85,81 +91,88 @@ for (uint32_t i=0; i<_param->_nb_read_unit; i++) - { - sensitive << (*(in_READ_UNIT_OUT_VAL [i])) - << (*(in_READ_UNIT_OUT_OPERATION [i])) - << (*(in_READ_UNIT_OUT_TYPE [i])) - << (*(in_READ_UNIT_OUT_HAS_IMMEDIAT [i])) - << (*(in_READ_UNIT_OUT_IMMEDIAT [i])) - << (*(in_READ_UNIT_OUT_DATA_RA [i])) - << (*(in_READ_UNIT_OUT_DATA_RB [i])) - << (*(in_READ_UNIT_OUT_DATA_RC [i])) - << (*(in_READ_UNIT_OUT_WRITE_RD [i])) - << (*(in_READ_UNIT_OUT_NUM_REG_RD [i])) - << (*(in_READ_UNIT_OUT_WRITE_RE [i])) - << (*(in_READ_UNIT_OUT_NUM_REG_RE [i])) - << (*(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [i])); - - if (_param->_have_port_load_queue_ptr) - sensitive << (*(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i])); - if (_param->_have_port_context_id) - sensitive << (*(in_READ_UNIT_OUT_CONTEXT_ID [i])); - if (_param->_have_port_front_end_id) - sensitive << (*(in_READ_UNIT_OUT_FRONT_END_ID [i])); - if (_param->_have_port_ooo_engine_id) - sensitive << (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [i])); - if (_param->_have_port_packet_id) - sensitive << (*(in_READ_UNIT_OUT_PACKET_ID [i])); - } + for (uint32_t j=0; j<_param->_nb_read_unit_port[i]; j++) + { + sensitive << (*(in_READ_UNIT_OUT_VAL [i][j])) + << (*(in_READ_UNIT_OUT_OPERATION [i][j])) + << (*(in_READ_UNIT_OUT_TYPE [i][j])) + << (*(in_READ_UNIT_OUT_HAS_IMMEDIAT [i][j])) + << (*(in_READ_UNIT_OUT_IMMEDIAT [i][j])) + << (*(in_READ_UNIT_OUT_DATA_RA [i][j])) + << (*(in_READ_UNIT_OUT_DATA_RB [i][j])) + << (*(in_READ_UNIT_OUT_DATA_RC [i][j])) + << (*(in_READ_UNIT_OUT_WRITE_RD [i][j])) + << (*(in_READ_UNIT_OUT_NUM_REG_RD [i][j])) + << (*(in_READ_UNIT_OUT_WRITE_RE [i][j])) + << (*(in_READ_UNIT_OUT_NUM_REG_RE [i][j])) + << (*(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [i][j])); + + if (_param->_have_port_load_queue_ptr) + sensitive << (*(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i][j])); + if (_param->_have_port_context_id) + sensitive << (*(in_READ_UNIT_OUT_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_READ_UNIT_OUT_FRONT_END_ID [i][j])); + if (_param->_have_port_ooo_engine_id) + sensitive << (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [i][j])); + if (_param->_have_port_rob_ptr ) + sensitive << (*(in_READ_UNIT_OUT_PACKET_ID [i][j])); + } for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - sensitive << (*(in_EXECUTE_UNIT_IN_ACK [i])); + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + sensitive << (*(in_EXECUTE_UNIT_IN_ACK [i][j])); # ifdef SYSTEMCASS_SPECIFIC // List dependency information for (uint32_t i=0; i<_param->_nb_read_unit; i++) + for (uint32_t j=0; j<_param->_nb_read_unit_port[i]; j++) { - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_READ_UNIT_OUT_VAL [i])); - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_READ_UNIT_OUT_TYPE [i])); + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_READ_UNIT_OUT_VAL [i][j])); + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_READ_UNIT_OUT_TYPE [i][j])); if (_param->_have_port_context_id) - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [i])); + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [i][j])); if (_param->_have_port_front_end_id) - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [i])); + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [i][j])); if (_param->_have_port_ooo_engine_id) - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [i])); - - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - (*(out_READ_UNIT_OUT_ACK [i])) (*(in_EXECUTE_UNIT_IN_ACK [j])); + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [i][j])); + + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + (*(out_READ_UNIT_OUT_ACK [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [x][y])); } for (uint32_t i=0; i<_param->_nb_execute_unit; i++) + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) { - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_VAL [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_VAL [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } if (_param->_have_port_context_id) { - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_CONTEXT_ID [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } @@ -167,16 +180,17 @@ if (_param->_have_port_front_end_id) { - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_FRONT_END_ID [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } @@ -184,232 +198,247 @@ if (_param->_have_port_ooo_engine_id) { - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - } - - if (_param->_have_port_packet_id) - { - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_PACKET_ID [j])); - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_PACKET_ID [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - } - - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_OPERATION [j])); - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_OPERATION [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_TYPE [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [j])); - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + } + + if (_param->_have_port_rob_ptr ) + { + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_PACKET_ID [x][y])); + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_PACKET_ID [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + } + + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_OPERATION [x][y])); + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_OPERATION [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_TYPE [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [x][y])); + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } if (_param->_have_port_load_queue_ptr) { - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [j])); - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [x][y])); + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_HAS_IMMEDIAT [j])); - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_IMMEDIAT [j])); - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_DATA_RA [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_DATA_RA [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_DATA_RB [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_DATA_RB [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_DATA_RC [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_DATA_RC [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_WRITE_RD [j])); - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RD [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_HAS_IMMEDIAT [x][y])); + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_IMMEDIAT [x][y])); + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_IMMEDIAT [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_DATA_RA [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_DATA_RA [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_DATA_RB [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_DATA_RB [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_DATA_RC [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_DATA_RC [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_WRITE_RD [x][y])); + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RD [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_NUM_REG_RD [j])); - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_WRITE_RE [j])); - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_WRITE_RE [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); - } - - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_EXECUTE_UNIT_IN_ACK [i])); - - for (uint32_t j=0; j<_param->_nb_read_unit; j++) - { - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_NUM_REG_RE [j])); - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_VAL [j])); - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_TYPE [j])); - if (_param->_have_port_context_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_CONTEXT_ID [j])); - if (_param->_have_port_front_end_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_FRONT_END_ID [j])); - if (_param->_have_port_ooo_engine_id) - (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [j])); + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_NUM_REG_RD [x][y])); + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RD [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_WRITE_RE [x][y])); + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_WRITE_RE [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); + } + + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_EXECUTE_UNIT_IN_ACK [i][j])); + + for (uint32_t x=0; x<_param->_nb_read_unit; x++) + for (uint32_t y=0; y<_param->_nb_read_unit_port[x]; y++) + { + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_NUM_REG_RE [x][y])); + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_VAL [x][y])); + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_TYPE [x][y])); + if (_param->_have_port_context_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_FRONT_END_ID [x][y])); + if (_param->_have_port_ooo_engine_id) + (*(out_EXECUTE_UNIT_IN_NUM_REG_RE [i][j])) (*(in_READ_UNIT_OUT_OOO_ENGINE_ID [x][y])); } } @@ -428,5 +457,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Read_unit_to_Execution_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_allocation.cpp (revision 88) @@ -57,65 +57,68 @@ // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("read_unit_out", IN, EAST, "Output of read_unit", _param->_nb_read_unit); + ALLOC2_INTERFACE("read_unit_out", IN, EAST, "Output of read_unit",_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); - ALLOC1_VALACK_IN ( in_READ_UNIT_OUT_VAL,VAL); - ALLOC1_VALACK_OUT(out_READ_UNIT_OUT_ACK,ACK); - - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_packet_id); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,log2(_param->_size_store_queue)); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,log2(_param->_size_load_queue)); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RA ,"DATA_RA" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RB ,"DATA_RB" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RC ,"DATA_RC" ,Tspecial_data_t ,_param->_size_special_data); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_READ_UNIT_OUT_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register); + _ALLOC2_VALACK_IN ( in_READ_UNIT_OUT_VAL,VAL,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_VALACK_OUT(out_READ_UNIT_OUT_ACK,ACK,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RA ,"DATA_RA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RB ,"DATA_RB" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_DATA_RC ,"DATA_RC" ,Tspecial_data_t ,_param->_size_special_data ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_READ_UNIT_OUT_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_read_unit,_param->_nb_read_unit_port[it1]); } // ~~~~~[ Interface "execute_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("execute_unit_in", OUT, WEST, "Input of execute_unit", _param->_nb_execute_unit); + ALLOC2_INTERFACE("execute_unit_in", OUT, WEST, "Input of execute_unit", _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); - ALLOC1_VALACK_OUT(out_EXECUTE_UNIT_IN_VAL,VAL); - ALLOC1_VALACK_IN ( in_EXECUTE_UNIT_IN_ACK,ACK); + _ALLOC2_VALACK_OUT(out_EXECUTE_UNIT_IN_VAL,VAL, _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_VALACK_IN ( in_EXECUTE_UNIT_IN_ACK,ACK, _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RC ,"DATA_RC" ,Tspecial_data_t ,_param->_size_special_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_size_store_queue_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RA ,"DATA_RA" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RB ,"DATA_RB" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + _ALLOC2_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1]); + } - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ,"OOO_ENGINE_ID" ,Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_packet_id); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RC ,"DATA_RC" ,Tspecial_data_t ,_param->_size_special_data); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE,"STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,log2(_param->_size_store_queue)); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,log2(_param->_size_load_queue)); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RA ,"DATA_RA" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_DATA_RB ,"DATA_RB" ,Tgeneral_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_OUT(out_EXECUTE_UNIT_IN_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register); - } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _destination = new std::list ** [_param->_nb_read_unit]; + if (usage_is_set(_usage,USE_SYSTEMC)) + { + _destination = new std::list ** [_param->_nb_read_unit]; for (uint32_t i=0; i<_param->_nb_read_unit; i++) { - _destination [i] = new std::list * [_param->_nb_thread]; + _destination [i] = new std::list * [_param->_nb_thread]; for (uint32_t j=0; j<_param->_nb_thread; j++) { - _destination [i][j] = new std::list [_param->_nb_type]; + _destination [i][j] = new std::list [_param->_nb_type]; } + } } #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/include/Read_unit_to_Execution_unit.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -23,64 +24,53 @@ log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; delete in_NRESET; - // ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_READ_UNIT_OUT_VAL ; - delete []out_READ_UNIT_OUT_ACK ; - if (_param->_have_port_context_id) - delete [] in_READ_UNIT_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] in_READ_UNIT_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] in_READ_UNIT_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) - delete [] in_READ_UNIT_OUT_PACKET_ID ; - delete [] in_READ_UNIT_OUT_OPERATION ; - delete [] in_READ_UNIT_OUT_TYPE ; - delete [] in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ; - delete [] in_READ_UNIT_OUT_HAS_IMMEDIAT ; - delete [] in_READ_UNIT_OUT_IMMEDIAT ; - delete [] in_READ_UNIT_OUT_DATA_RA ; - delete [] in_READ_UNIT_OUT_DATA_RB ; - delete [] in_READ_UNIT_OUT_DATA_RC ; - delete [] in_READ_UNIT_OUT_WRITE_RD ; - delete [] in_READ_UNIT_OUT_NUM_REG_RD ; - delete [] in_READ_UNIT_OUT_WRITE_RE ; - delete [] in_READ_UNIT_OUT_NUM_REG_RE ; + DELETE2_SIGNAL( in_READ_UNIT_OUT_VAL , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1 ); + DELETE2_SIGNAL(out_READ_UNIT_OUT_ACK , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1 ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_CONTEXT_ID , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_FRONT_END_ID , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_OOO_ENGINE_ID , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_ooo_engine_id ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_PACKET_ID , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_rob_ptr ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_OPERATION , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_operation ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_TYPE , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_type ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_HAS_IMMEDIAT , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1 ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_IMMEDIAT , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_DATA_RA , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_DATA_RB , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_DATA_RC , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_special_data ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_WRITE_RD , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1 ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RD , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_general_register ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_WRITE_RE , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],1 ); + DELETE2_SIGNAL( in_READ_UNIT_OUT_NUM_REG_RE , _param->_nb_read_unit, _param->_nb_read_unit_port [it1],_param->_size_special_register ); + + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_VAL , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_UNIT_IN_ACK , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1 ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_CONTEXT_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_context_id ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_FRONT_END_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_front_end_id ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_ooo_engine_id ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_PACKET_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_rob_ptr ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_OPERATION , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_operation ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_TYPE , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_type ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1 ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RC , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_special_data ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1 ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_WRITE_RE , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],1 ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RE , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_special_register ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE, _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_IMMEDIAT , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RA , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_DATA_RB , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_data ); + DELETE2_SIGNAL(out_EXECUTE_UNIT_IN_NUM_REG_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port [it1],_param->_size_general_register ); - // ~~~~~[ Interface "execute_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_EXECUTE_UNIT_IN_VAL ; - delete [] in_EXECUTE_UNIT_IN_ACK ; - if (_param->_have_port_context_id) - delete [] out_EXECUTE_UNIT_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] out_EXECUTE_UNIT_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] out_EXECUTE_UNIT_IN_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) - delete [] out_EXECUTE_UNIT_IN_PACKET_ID ; - delete [] out_EXECUTE_UNIT_IN_OPERATION ; - delete [] out_EXECUTE_UNIT_IN_TYPE ; - delete [] out_EXECUTE_UNIT_IN_HAS_IMMEDIAT ; - delete [] out_EXECUTE_UNIT_IN_DATA_RC ; - delete [] out_EXECUTE_UNIT_IN_WRITE_RD ; - delete [] out_EXECUTE_UNIT_IN_WRITE_RE ; - delete [] out_EXECUTE_UNIT_IN_NUM_REG_RE ; - delete [] out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE ; - delete [] out_EXECUTE_UNIT_IN_IMMEDIAT ; - delete [] out_EXECUTE_UNIT_IN_DATA_RA ; - delete [] out_EXECUTE_UNIT_IN_DATA_RB ; - delete [] out_EXECUTE_UNIT_IN_NUM_REG_RD ; + delete [] _destination; } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] _destination; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp (revision 88) @@ -24,80 +24,83 @@ log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"Begin"); - bool execute_unit_use [_param->_nb_execute_unit]; + bool execute_unit_use [_param->_nb_execute_unit][_param->_max_nb_execute_unit_port]; for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - execute_unit_use[i] = (PORT_READ(in_EXECUTE_UNIT_IN_ACK [i]) == 0); + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + execute_unit_use[i][j] = false; for (uint32_t i=0; i<_param->_nb_read_unit; i++) - { - bool ack = false; + for (uint32_t j=0; j<_param->_nb_read_unit_port[i]; j++) + { + bool ack = false; + + log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"Test Read_unit[%d][%d]",i,j); + + if (PORT_READ(in_READ_UNIT_OUT_VAL [i][j]) == true) + { + log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * have a valid entry."); + + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i][j]):0; + Tcontext_t front_end_id = (_param->_have_port_front_end_id )?PORT_READ(in_READ_UNIT_OUT_FRONT_END_ID [i][j]):0; + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_READ_UNIT_OUT_OOO_ENGINE_ID [i][j]):0; + Tcontext_t num_thread = get_num_thread(context_id , _param->_size_context_id , + front_end_id , _param->_size_front_end_id , + ooo_engine_id, _param->_size_ooo_engine_id); + Ttype_t type = PORT_READ(in_READ_UNIT_OUT_TYPE [i][j]); + +#ifdef DEBUG_TEST + if (_destination[i][num_thread][type].empty()) + throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString_type(type)+"]."); +#endif + + // find a free execute_unit + for (std::list::iterator it=_destination[i][num_thread][type].begin(); + (it != _destination[i][num_thread][type].end()) and (ack == false); + it++) + { + uint32_t dest = (*it).grp; + uint32_t port = (*it).elt; + + log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d][%d].",dest,port); + + if (execute_unit_use [dest][port] == false) + { + log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Is ok! Link."); + + // have find !!! + ack = PORT_READ(in_EXECUTE_UNIT_IN_ACK [dest][port]); + execute_unit_use [dest][port] = true; - log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION,"Test Read_unit[%d]",i); - - if (PORT_READ(in_READ_UNIT_OUT_VAL [i]) == true) - { - log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * have a valid entry."); - - Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i]):0; - Tcontext_t front_end_id = (_param->_have_port_front_end_id )?PORT_READ(in_READ_UNIT_OUT_FRONT_END_ID [i]):0; - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?PORT_READ(in_READ_UNIT_OUT_OOO_ENGINE_ID [i]):0; - Tcontext_t num_thread = get_num_thread(context_id , _param->_size_context_id , - front_end_id , _param->_size_front_end_id , - ooo_engine_id, _param->_size_ooo_engine_id); - Ttype_t type = PORT_READ(in_READ_UNIT_OUT_TYPE [i]); - -#ifdef DEBUG_TEST - if (_destination[i][num_thread][type].empty()) - throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString_type(type)+"]."); -#endif - - // find a free execute_unit - for (std::list::iterator it=_destination[i][num_thread][type].begin(); - (it != _destination[i][num_thread][type].end()) and (ack == false); - it++) - { - uint32_t dest = *it; - - log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Test destination [%d].",dest); - - if (execute_unit_use [dest] == false) - { - log_printf(TRACE,Read_unit_to_Execution_unit,FUNCTION," * Is ok! Link."); - // have find !!! - ack = true; - execute_unit_use [dest] = true; - - if (_param->_have_port_context_id) - PORT_WRITE(out_EXECUTE_UNIT_IN_CONTEXT_ID [dest], PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i])); - if (_param->_have_port_front_end_id) - PORT_WRITE(out_EXECUTE_UNIT_IN_FRONT_END_ID [dest], PORT_READ(in_READ_UNIT_OUT_FRONT_END_ID [i])); - if (_param->_have_port_ooo_engine_id) - PORT_WRITE(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [dest], PORT_READ(in_READ_UNIT_OUT_OOO_ENGINE_ID [i])); - if (_param->_have_port_packet_id) - PORT_WRITE(out_EXECUTE_UNIT_IN_PACKET_ID [dest], PORT_READ(in_READ_UNIT_OUT_PACKET_ID [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_OPERATION [dest], PORT_READ(in_READ_UNIT_OUT_OPERATION [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_TYPE [dest], PORT_READ(in_READ_UNIT_OUT_TYPE [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [dest], PORT_READ(in_READ_UNIT_OUT_HAS_IMMEDIAT [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RC [dest], PORT_READ(in_READ_UNIT_OUT_DATA_RC [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_WRITE_RD [dest], PORT_READ(in_READ_UNIT_OUT_WRITE_RD [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_WRITE_RE [dest], PORT_READ(in_READ_UNIT_OUT_WRITE_RE [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_NUM_REG_RE [dest], PORT_READ(in_READ_UNIT_OUT_NUM_REG_RE [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [dest], PORT_READ(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [i])); - if (_param->_have_port_load_queue_ptr) - PORT_WRITE(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [dest], PORT_READ(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_IMMEDIAT [dest], PORT_READ(in_READ_UNIT_OUT_IMMEDIAT [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RA [dest], PORT_READ(in_READ_UNIT_OUT_DATA_RA [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RB [dest], PORT_READ(in_READ_UNIT_OUT_DATA_RB [i])); - PORT_WRITE(out_EXECUTE_UNIT_IN_NUM_REG_RD [dest], PORT_READ(in_READ_UNIT_OUT_NUM_REG_RD [i])); - } - } - } - PORT_WRITE(out_READ_UNIT_OUT_ACK [i], ack); - } + if (_param->_have_port_context_id) + PORT_WRITE(out_EXECUTE_UNIT_IN_CONTEXT_ID [dest][port], PORT_READ(in_READ_UNIT_OUT_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_EXECUTE_UNIT_IN_FRONT_END_ID [dest][port], PORT_READ(in_READ_UNIT_OUT_FRONT_END_ID [i][j])); + if (_param->_have_port_ooo_engine_id) + PORT_WRITE(out_EXECUTE_UNIT_IN_OOO_ENGINE_ID [dest][port], PORT_READ(in_READ_UNIT_OUT_OOO_ENGINE_ID [i][j])); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_EXECUTE_UNIT_IN_PACKET_ID [dest][port], PORT_READ(in_READ_UNIT_OUT_PACKET_ID [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_OPERATION [dest][port], PORT_READ(in_READ_UNIT_OUT_OPERATION [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_TYPE [dest][port], PORT_READ(in_READ_UNIT_OUT_TYPE [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_HAS_IMMEDIAT [dest][port], PORT_READ(in_READ_UNIT_OUT_HAS_IMMEDIAT [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RC [dest][port], PORT_READ(in_READ_UNIT_OUT_DATA_RC [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_WRITE_RD [dest][port], PORT_READ(in_READ_UNIT_OUT_WRITE_RD [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_WRITE_RE [dest][port], PORT_READ(in_READ_UNIT_OUT_WRITE_RE [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_NUM_REG_RE [dest][port], PORT_READ(in_READ_UNIT_OUT_NUM_REG_RE [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_STORE_QUEUE_PTR_WRITE [dest][port], PORT_READ(in_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE [i][j])); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_EXECUTE_UNIT_IN_LOAD_QUEUE_PTR_WRITE [dest][port], PORT_READ(in_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_IMMEDIAT [dest][port], PORT_READ(in_READ_UNIT_OUT_IMMEDIAT [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RA [dest][port], PORT_READ(in_READ_UNIT_OUT_DATA_RA [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_DATA_RB [dest][port], PORT_READ(in_READ_UNIT_OUT_DATA_RB [i][j])); + PORT_WRITE(out_EXECUTE_UNIT_IN_NUM_REG_RD [dest][port], PORT_READ(in_READ_UNIT_OUT_NUM_REG_RD [i][j])); + } + } + } + PORT_WRITE(out_READ_UNIT_OUT_ACK [i][j], ack); + } for (uint32_t i=0; i<_param->_nb_execute_unit; i++) - { - PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i], execute_unit_use[i]); - } + for (uint32_t j=0; j<_param->_nb_execute_unit_port[i]; j++) + PORT_WRITE(out_EXECUTE_UNIT_IN_VAL[i][j], execute_unit_use[i][j]); log_printf(FUNC,Read_unit_to_Execution_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_transition.cpp (revision 88) @@ -34,15 +34,16 @@ // Fill routing table for (uint32_t i=0; i<_param->_nb_read_unit; i++) - for (uint32_t j=0; j<_param->_nb_execute_unit; j++) - // Test if link between src and dest - if (_param->_table_routing [i][j]) - // Test the thread accepted by the execute_unit - for (uint32_t k=0; k<_param->_nb_thread; k++) - if (_param->_table_execute_thread[j][k]) - // Test the type accepted by the execute_unit - for (uint32_t l=0; l<_param->_nb_type; l++) - if (_param->_table_execute_type [j][l]) - // push_back == minor have a better priority - _destination [i][k][l].push_back(j); + for (uint32_t x=0; x<_param->_nb_execute_unit; x++) + for (uint32_t y=0; y<_param->_nb_execute_unit_port[x]; y++) + // Test if link between src and dest + if (_param->_table_routing [i][x][y]) + // Test the thread accepted by the execute_unit + for (uint32_t k=0; k<_param->_nb_thread; k++) + if (_param->_table_execute_thread[x][k]) + // Test the type accepted by the execute_unit + for (uint32_t l=0; l<_param->_nb_type; l++) + if (_param->_table_execute_type [x][l]) + // push_back == minor have a better priority + _destination [i][k][l].push_back(destination_t(x,y)); } else Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Register_unit_Glue_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/include/test.h (revision 88) @@ -15,4 +15,5 @@ #include +#include "Common/include/Time.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h" @@ -29,34 +30,2 @@ void test (string name, morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::register_unit_glue::Parameters * param); - -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/main.cpp (revision 88) @@ -74,5 +74,7 @@ _nb_spr_write , _nb_inst_insert_rob, - _nb_inst_retire_rob); + _nb_inst_retire_rob, + true //is_toplevel + ); cout << param->print(1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/SelfTest/src/test.cpp (revision 88) @@ -22,4 +22,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Register_unit_Glue * _Register_unit_Glue = new Register_unit_Glue (name.c_str(), @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -88,18 +98,18 @@ sc_signal *** in_INSERT_ROB_SPR_STATUS_ACK ; - sc_signal *** in_RETIRE_ROB_VAL ; - sc_signal *** out_RETIRE_ROB_ACK ; - sc_signal *** in_RETIRE_ROB_RD_OLD_USE ; - sc_signal *** in_RETIRE_ROB_RD_NEW_USE ; - sc_signal *** in_RETIRE_ROB_RE_OLD_USE ; - sc_signal *** in_RETIRE_ROB_RE_NEW_USE ; - sc_signal *** out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; - sc_signal *** in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; - sc_signal *** out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; - sc_signal *** in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; - sc_signal *** out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; - sc_signal *** in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; - sc_signal *** out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; - sc_signal *** in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; +// sc_signal *** in_RETIRE_ROB_VAL ; +// sc_signal *** out_RETIRE_ROB_ACK ; +// sc_signal *** in_RETIRE_ROB_RD_OLD_USE ; +// sc_signal *** in_RETIRE_ROB_RD_NEW_USE ; +// sc_signal *** in_RETIRE_ROB_RE_OLD_USE ; +// sc_signal *** in_RETIRE_ROB_RE_NEW_USE ; +// sc_signal *** out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; +// sc_signal *** in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; +// sc_signal *** out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; +// sc_signal *** in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; +// sc_signal *** out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; +// sc_signal *** in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; +// sc_signal *** out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; +// sc_signal *** in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; string rename; @@ -294,57 +304,57 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_RETIRE_ROB_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_GPR_STATUS_OLD_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_GPR_STATUS_NEW_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_GPR_STATUS_OLD_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_GPR_STATUS_NEW_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_SPR_STATUS_OLD_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_SPR_STATUS_NEW_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_SPR_STATUS_OLD_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_SPR_STATUS_NEW_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - - in_RETIRE_ROB_VAL [i] = new sc_signal * [x]; - out_RETIRE_ROB_ACK [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_OLD_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_NEW_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_OLD_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_NEW_USE [i] = new sc_signal * [x]; - out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i] = new sc_signal * [x]; - out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i] = new sc_signal * [x]; - in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i] = new sc_signal * [x]; - in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i] = new sc_signal * [x]; - out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i] = new sc_signal * [x]; - out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i] = new sc_signal * [x]; - in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i] = new sc_signal * [x]; - in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i] = new sc_signal * [x]; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// in_RETIRE_ROB_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_ACK = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK = new sc_signal ** [_param->_nb_ooo_engine]; + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; + +// in_RETIRE_ROB_VAL [i] = new sc_signal * [x]; +// out_RETIRE_ROB_ACK [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_OLD_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_NEW_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_OLD_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_NEW_USE [i] = new sc_signal * [x]; +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i] = new sc_signal * [x]; +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i] = new sc_signal * [x]; +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i] = new sc_signal * [x]; +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i] = new sc_signal * [x]; +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i] = new sc_signal * [x]; +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i] = new sc_signal * [x]; +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i] = new sc_signal * [x]; +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i] = new sc_signal * [x]; - for (uint32_t j=0; j (rename.c_str()); - out_RETIRE_ROB_ACK [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_OLD_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_NEW_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_OLD_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_NEW_USE [i][j] = new sc_signal (rename.c_str()); - out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j] = new sc_signal (rename.c_str()); - out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j] = new sc_signal (rename.c_str()); - out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j] = new sc_signal (rename.c_str()); - out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j] = new sc_signal (rename.c_str()); - } - } +// for (uint32_t j=0; j (rename.c_str()); +// out_RETIRE_ROB_ACK [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_OLD_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_NEW_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_OLD_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_NEW_USE [i][j] = new sc_signal (rename.c_str()); +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j] = new sc_signal (rename.c_str()); +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j] = new sc_signal (rename.c_str()); +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j] = new sc_signal (rename.c_str()); +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j] = new sc_signal (rename.c_str()); +// } +// } @@ -451,28 +461,28 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - - for (uint32_t j=0; j in_RETIRE_ROB_VAL [i][j]))(*( in_RETIRE_ROB_VAL [i][j])); - (*(_Register_unit_Glue->out_RETIRE_ROB_ACK [i][j]))(*(out_RETIRE_ROB_ACK [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_RD_OLD_USE [i][j]))(*( in_RETIRE_ROB_RD_OLD_USE [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_RD_NEW_USE [i][j]))(*( in_RETIRE_ROB_RD_NEW_USE [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_RE_OLD_USE [i][j]))(*( in_RETIRE_ROB_RE_OLD_USE [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_RE_NEW_USE [i][j]))(*( in_RETIRE_ROB_RE_NEW_USE [i][j])); - (*(_Register_unit_Glue->out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j]))(*(out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j]))(*( in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j])); - (*(_Register_unit_Glue->out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j]))(*(out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j]))(*( in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j])); - (*(_Register_unit_Glue->out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j]))(*(out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j]))(*( in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j])); - (*(_Register_unit_Glue->out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j]))(*(out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j])); - (*(_Register_unit_Glue-> in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j]))(*( in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j])); - } - } +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; + +// for (uint32_t j=0; j in_RETIRE_ROB_VAL [i][j]))(*( in_RETIRE_ROB_VAL [i][j])); +// (*(_Register_unit_Glue->out_RETIRE_ROB_ACK [i][j]))(*(out_RETIRE_ROB_ACK [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_RD_OLD_USE [i][j]))(*( in_RETIRE_ROB_RD_OLD_USE [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_RD_NEW_USE [i][j]))(*( in_RETIRE_ROB_RD_NEW_USE [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_RE_OLD_USE [i][j]))(*( in_RETIRE_ROB_RE_OLD_USE [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_RE_NEW_USE [i][j]))(*( in_RETIRE_ROB_RE_NEW_USE [i][j])); +// (*(_Register_unit_Glue->out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j]))(*(out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j]))(*( in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j])); +// (*(_Register_unit_Glue->out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j]))(*(out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j]))(*( in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j])); +// (*(_Register_unit_Glue->out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j]))(*(out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j]))(*( in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j])); +// (*(_Register_unit_Glue->out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j]))(*(out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j])); +// (*(_Register_unit_Glue-> in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j]))(*( in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j])); +// } +// } cout << "<" << name << "> Start Simulation ............" << endl; @@ -487,5 +497,5 @@ const bool test_write = true; const bool test_insert = true; - const bool test_retire = true; +// const bool test_retire = true; const int32_t percent_transaction = 75; @@ -517,15 +527,15 @@ Tcontrol_t spr_write_status_val [_param->_nb_ooo_engine][_param->_nb_spr_write]; - uint32_t max_nb_inst_retire_rob = 0; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - if (_param->_nb_inst_retire_rob [i] > max_nb_inst_retire_rob) - max_nb_inst_retire_rob = _param->_nb_inst_retire_rob [i]; - - Tcontrol_t retire_rob_ack [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; - Tcontrol_t retire_rob_gpr_status_new_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; - Tcontrol_t retire_rob_gpr_status_old_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; - Tcontrol_t retire_rob_spr_status_new_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; - Tcontrol_t retire_rob_spr_status_old_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; +// uint32_t max_nb_inst_retire_rob = 0; + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// if (_param->_nb_inst_retire_rob [i] > max_nb_inst_retire_rob) +// max_nb_inst_retire_rob = _param->_nb_inst_retire_rob [i]; + +// Tcontrol_t retire_rob_ack [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; +// Tcontrol_t retire_rob_gpr_status_new_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; +// Tcontrol_t retire_rob_gpr_status_old_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; +// Tcontrol_t retire_rob_spr_status_new_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; +// Tcontrol_t retire_rob_spr_status_old_val [_param->_nb_ooo_engine][max_nb_inst_retire_rob]; uint32_t max_nb_inst_insert_rob = 0; @@ -706,45 +716,45 @@ } - if (test_retire == true) - { - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x = _param->_nb_inst_retire_rob [i]; - - for (uint32_t j=0; jwrite(val ); - in_RETIRE_ROB_RD_OLD_USE [i][j]->write(rd_old_use ); - in_RETIRE_ROB_RD_NEW_USE [i][j]->write(rd_new_use ); - in_RETIRE_ROB_RE_OLD_USE [i][j]->write(re_old_use ); - in_RETIRE_ROB_RE_NEW_USE [i][j]->write(re_new_use ); - in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j]->write(gpr_status_old_ack); - in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j]->write(gpr_status_new_ack); - in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j]->write(spr_status_old_ack); - in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j]->write(spr_status_new_ack); +// if (test_retire == true) +// { +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x = _param->_nb_inst_retire_rob [i]; + +// for (uint32_t j=0; jwrite(val ); +// in_RETIRE_ROB_RD_OLD_USE [i][j]->write(rd_old_use ); +// in_RETIRE_ROB_RD_NEW_USE [i][j]->write(rd_new_use ); +// in_RETIRE_ROB_RE_OLD_USE [i][j]->write(re_old_use ); +// in_RETIRE_ROB_RE_NEW_USE [i][j]->write(re_new_use ); +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j]->write(gpr_status_old_ack); +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j]->write(gpr_status_new_ack); +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j]->write(spr_status_old_ack); +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j]->write(spr_status_new_ack); - retire_rob_ack [i][j] = (gpr_status_new_ack and - gpr_status_old_ack and - spr_status_new_ack and - spr_status_old_ack); - - - retire_rob_gpr_status_old_val [i][j] = val and rd_old_use and gpr_status_new_ack and spr_status_old_ack and spr_status_new_ack; - retire_rob_gpr_status_new_val [i][j] = val and rd_new_use and gpr_status_old_ack and spr_status_old_ack and spr_status_new_ack; - retire_rob_spr_status_old_val [i][j] = val and re_old_use and gpr_status_old_ack and gpr_status_new_ack and spr_status_new_ack; - retire_rob_spr_status_new_val [i][j] = val and re_new_use and gpr_status_old_ack and gpr_status_new_ack and spr_status_old_ack ; - } - } - } +// retire_rob_ack [i][j] = (gpr_status_new_ack and +// gpr_status_old_ack and +// spr_status_new_ack and +// spr_status_old_ack); + + +// retire_rob_gpr_status_old_val [i][j] = val and rd_old_use and gpr_status_new_ack and spr_status_old_ack and spr_status_new_ack; +// retire_rob_gpr_status_new_val [i][j] = val and rd_new_use and gpr_status_old_ack and spr_status_old_ack and spr_status_new_ack; +// retire_rob_spr_status_old_val [i][j] = val and re_old_use and gpr_status_old_ack and gpr_status_new_ack and spr_status_new_ack; +// retire_rob_spr_status_new_val [i][j] = val and re_new_use and gpr_status_old_ack and gpr_status_new_ack and spr_status_old_ack ; +// } +// } +// } if (test_insert == true) @@ -837,20 +847,20 @@ - if (test_retire == true) - { - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x = _param->_nb_inst_retire_rob [i]; - - for (uint32_t j=0; jread(), retire_rob_ack [i][j]); - TEST(Tcontrol_t, out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j]->read(), retire_rob_gpr_status_old_val [i][j]); - TEST(Tcontrol_t, out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j]->read(), retire_rob_gpr_status_new_val [i][j]); - TEST(Tcontrol_t, out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j]->read(), retire_rob_spr_status_old_val [i][j]); - TEST(Tcontrol_t, out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j]->read(), retire_rob_spr_status_new_val [i][j]); - } - } - } +// if (test_retire == true) +// { +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x = _param->_nb_inst_retire_rob [i]; + +// for (uint32_t j=0; jread(), retire_rob_ack [i][j]); +// TEST(Tcontrol_t, out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j]->read(), retire_rob_gpr_status_old_val [i][j]); +// TEST(Tcontrol_t, out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j]->read(), retire_rob_gpr_status_new_val [i][j]); +// TEST(Tcontrol_t, out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j]->read(), retire_rob_spr_status_old_val [i][j]); +// TEST(Tcontrol_t, out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j]->read(), retire_rob_spr_status_new_val [i][j]); +// } +// } +// } if (test_insert == true) @@ -927,18 +937,18 @@ delete [] out_INSERT_ROB_SPR_STATUS_VAL ; delete [] in_INSERT_ROB_SPR_STATUS_ACK ; - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; - delete [] out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; - delete [] in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; - delete [] in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; - delete [] out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; - delete [] out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; - delete [] in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; - delete [] in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; +// delete [] in_RETIRE_ROB_VAL ; +// delete [] out_RETIRE_ROB_ACK ; +// delete [] in_RETIRE_ROB_RD_OLD_USE ; +// delete [] in_RETIRE_ROB_RD_NEW_USE ; +// delete [] in_RETIRE_ROB_RE_OLD_USE ; +// delete [] in_RETIRE_ROB_RE_NEW_USE ; +// delete [] out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; +// delete [] out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; +// delete [] in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; +// delete [] in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; +// delete [] out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; +// delete [] out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; +// delete [] in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; +// delete [] in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Parameters.h (revision 88) @@ -22,32 +22,37 @@ + + class Parameters : public morpheo::behavioural::Parameters { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_gpr_read ; - public : const uint32_t _nb_spr_read ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_spr_write ; - public : const uint32_t * _nb_inst_insert_rob ; - public : const uint32_t * _nb_inst_retire_rob ; + public : uint32_t _nb_ooo_engine ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_gpr_read ; + public : uint32_t _nb_spr_read ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_spr_write ; + public : uint32_t * _nb_inst_insert_rob ; + public : uint32_t * _nb_inst_retire_rob ; - public : const bool _have_port_ooo_engine_id; +//public : bool _have_port_ooo_engine_id; //-----[ methods ]----------------------------------------------------------- - public : Parameters (const uint32_t nb_ooo_engine , - const uint32_t size_general_data , - const uint32_t size_special_data , - const uint32_t nb_gpr_read , - const uint32_t nb_spr_read , - const uint32_t nb_gpr_write , - const uint32_t nb_spr_write , - const uint32_t * nb_inst_insert_rob , - const uint32_t * nb_inst_retire_rob ); - public : Parameters (Parameters & param) ; + public : Parameters (uint32_t nb_ooo_engine , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t nb_gpr_read , + uint32_t nb_spr_read , + uint32_t nb_gpr_write , + uint32_t nb_spr_write , + uint32_t * nb_inst_insert_rob , + uint32_t * nb_inst_retire_rob , + bool is_toplevel=false); +//public : Parameters (Parameters & param) ; public : ~Parameters () ; - + + public : void copy (void); + public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/include/Register_unit_Glue.h (revision 88) @@ -128,21 +128,21 @@ public : SC_IN (Tcontrol_t ) *** in_INSERT_ROB_SPR_STATUS_ACK ; - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ; - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ; - - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; - - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ; +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ; + +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; + +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Parameters.cpp (revision 88) @@ -19,51 +19,71 @@ #undef FUNCTION #define FUNCTION "Register_unit_Glue::Parameters" - Parameters::Parameters (const uint32_t nb_ooo_engine , - const uint32_t size_general_data , - const uint32_t size_special_data , - const uint32_t nb_gpr_read , - const uint32_t nb_spr_read , - const uint32_t nb_gpr_write , - const uint32_t nb_spr_write , - const uint32_t * nb_inst_insert_rob , - const uint32_t * nb_inst_retire_rob ): - _nb_ooo_engine (nb_ooo_engine ), - _size_general_data (size_general_data), - _size_special_data (size_special_data), - _nb_gpr_read (nb_gpr_read ), - _nb_spr_read (nb_spr_read ), - _nb_gpr_write (nb_gpr_write ), - _nb_spr_write (nb_spr_write ), - _nb_inst_insert_rob (nb_inst_insert_rob), - _nb_inst_retire_rob (nb_inst_retire_rob), - _have_port_ooo_engine_id (nb_ooo_engine>1) + Parameters::Parameters (uint32_t nb_ooo_engine , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t nb_gpr_read , + uint32_t nb_spr_read , + uint32_t nb_gpr_write , + uint32_t nb_spr_write , + uint32_t * nb_inst_insert_rob , + uint32_t * nb_inst_retire_rob , + bool is_toplevel ) { log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + + _nb_ooo_engine = nb_ooo_engine ; + _nb_gpr_read = nb_gpr_read ; + _nb_spr_read = nb_spr_read ; + _nb_gpr_write = nb_gpr_write ; + _nb_spr_write = nb_spr_write ; + _nb_inst_insert_rob = nb_inst_insert_rob; + _nb_inst_retire_rob = nb_inst_retire_rob; + test(); + + if (is_toplevel) + { + _size_ooo_engine_id = log2(nb_ooo_engine); + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + + copy(); + } + log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Register_unit_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _nb_ooo_engine (param._nb_ooo_engine ), +// _size_general_data (param._size_general_data), +// _size_special_data (param._size_special_data), +// _nb_gpr_read (param._nb_gpr_read ), +// _nb_spr_read (param._nb_spr_read ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_spr_write (param._nb_spr_write ), +// _nb_inst_insert_rob (param._nb_inst_insert_rob), +// _nb_inst_retire_rob (param._nb_inst_retire_rob), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id) +// { +// log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Register_unit_Glue::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _nb_ooo_engine (param._nb_ooo_engine ), - _size_general_data (param._size_general_data), - _size_special_data (param._size_special_data), - _nb_gpr_read (param._nb_gpr_read ), - _nb_spr_read (param._nb_spr_read ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_spr_write (param._nb_spr_write ), - _nb_inst_insert_rob (param._nb_inst_insert_rob), - _nb_inst_retire_rob (param._nb_inst_retire_rob), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id) +#define FUNCTION "Register_unit_Glue::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); - test(); log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Register_unit_Glue::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Register_unit_Glue::copy" + void Parameters::copy (void) { log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue.cpp (revision 88) @@ -38,22 +38,36 @@ log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); +#if DEBUG_Register_unit_Glue == true + log_printf(INFO,Register_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Register_unit_Glue,FUNCTION,"Allocation"); allocation (); #ifdef STATISTICS - log_printf(INFO,Register_unit_Glue,FUNCTION,"Allocation of statistics"); - - // Allocation of statistics - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Register_unit_Glue,FUNCTION,"Allocation of statistics"); + + // Allocation of statistics + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,Register_unit_Glue,FUNCTION,"Generate the vhdl"); - - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Register_unit_Glue,FUNCTION,"Generate the vhdl"); + + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { // Constant @@ -473,62 +487,62 @@ #endif - log_printf(INFO,Register_unit_Glue,FUNCTION,"Method - genMealy_retire"); - - SC_METHOD (genMealy_retire); - dont_initialize (); -// sensitive_neg << *(in_CLOCK); - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - for (uint32_t j=0; j_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - for (uint32_t j=0; j_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; +// for (uint32_t j=0; j_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; +// for (uint32_t j=0; jset_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", log2(_param->_nb_ooo_engine)); + in_GPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); out_GPR_READ_DATA [j] = interface->set_signal_out ("data" , _param->_size_general_data); out_GPR_READ_DATA_VAL [j] = interface->set_signal_out ("data_val" , 1); @@ -166,5 +166,5 @@ out_SPR_READ_ACK [j] = interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", log2(_param->_nb_ooo_engine)); + in_SPR_READ_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); out_SPR_READ_DATA [j] = interface->set_signal_out ("data" , _param->_size_special_data); out_SPR_READ_DATA_VAL [j] = interface->set_signal_out ("data_val" , 1); @@ -236,5 +236,5 @@ out_GPR_WRITE_ACK [j] = interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", log2(_param->_nb_ooo_engine)); + in_GPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) @@ -302,5 +302,5 @@ out_SPR_WRITE_ACK [j] = interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", log2(_param->_nb_ooo_engine)); + in_SPR_WRITE_OOO_ENGINE_ID [j] = interface->set_signal_in ("ooo_engine_id", _param->_size_ooo_engine_id); for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) @@ -400,112 +400,113 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_RETIRE_ROB_VAL = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_ACK = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_GPR_STATUS_OLD_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_GPR_STATUS_NEW_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_GPR_STATUS_OLD_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_GPR_STATUS_NEW_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_SPR_STATUS_OLD_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_SPR_STATUS_NEW_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_SPR_STATUS_OLD_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_SPR_STATUS_NEW_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - - in_RETIRE_ROB_VAL [i] = new SC_IN (Tcontrol_t) * [x]; - out_RETIRE_ROB_ACK [i] = new SC_OUT(Tcontrol_t) * [x]; - in_RETIRE_ROB_RD_OLD_USE [i] = new SC_IN (Tcontrol_t) * [x]; - in_RETIRE_ROB_RD_NEW_USE [i] = new SC_IN (Tcontrol_t) * [x]; - in_RETIRE_ROB_RE_OLD_USE [i] = new SC_IN (Tcontrol_t) * [x]; - in_RETIRE_ROB_RE_NEW_USE [i] = new SC_IN (Tcontrol_t) * [x]; - out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; - in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i] = new SC_IN (Tcontrol_t) * [x]; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// in_RETIRE_ROB_VAL = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_ACK = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_USE = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL = new SC_OUT(Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK = new SC_IN (Tcontrol_t) ** [_param->_nb_ooo_engine]; + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; + +// in_RETIRE_ROB_VAL [i] = new SC_IN (Tcontrol_t) * [x]; +// out_RETIRE_ROB_ACK [i] = new SC_OUT(Tcontrol_t) * [x]; +// in_RETIRE_ROB_RD_OLD_USE [i] = new SC_IN (Tcontrol_t) * [x]; +// in_RETIRE_ROB_RD_NEW_USE [i] = new SC_IN (Tcontrol_t) * [x]; +// in_RETIRE_ROB_RE_OLD_USE [i] = new SC_IN (Tcontrol_t) * [x]; +// in_RETIRE_ROB_RE_NEW_USE [i] = new SC_IN (Tcontrol_t) * [x]; +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i] = new SC_IN (Tcontrol_t) * [x]; +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i] = new SC_IN (Tcontrol_t) * [x]; +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i] = new SC_OUT(Tcontrol_t) * [x]; +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i] = new SC_IN (Tcontrol_t) * [x]; +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i] = new SC_IN (Tcontrol_t) * [x]; - for (uint32_t j=0; jset_interface("retire_rob_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,WEST - ,"Interface to update status (retire)" -#endif - ); - - in_RETIRE_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); - out_RETIRE_ROB_ACK [i][j] = interface->set_signal_valack_out(ACK); - in_RETIRE_ROB_RD_OLD_USE [i][j] = interface->set_signal_in ("rd_old_use", 1); - in_RETIRE_ROB_RD_NEW_USE [i][j] = interface->set_signal_in ("rd_new_use", 1); - in_RETIRE_ROB_RE_OLD_USE [i][j] = interface->set_signal_in ("re_old_use", 1); - in_RETIRE_ROB_RE_NEW_USE [i][j] = interface->set_signal_in ("re_new_use", 1); - } - { - Interface_fifo * interface = _interfaces->set_interface("retire_rob_gpr_status_old_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (retire)" -#endif - ); - - out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("retire_rob_gpr_status_new_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (retire)" -#endif - ); - - out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("retire_rob_spr_status_old_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (retire)" -#endif - ); - - out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - { - Interface_fifo * interface = _interfaces->set_interface("retire_rob_spr_status_new_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,EAST - ,"Interface to update status (retire)" -#endif - ); - - out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j] = interface->set_signal_valack_out(VAL); - in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j] = interface->set_signal_valack_in (ACK); - } - } - } +// for (uint32_t j=0; jset_interface("retire_rob_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,WEST +// ,"Interface to update status (retire)" +// #endif +// ); + +// in_RETIRE_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); +// out_RETIRE_ROB_ACK [i][j] = interface->set_signal_valack_out(ACK); +// in_RETIRE_ROB_RD_OLD_USE [i][j] = interface->set_signal_in ("rd_old_use", 1); +// in_RETIRE_ROB_RD_NEW_USE [i][j] = interface->set_signal_in ("rd_new_use", 1); +// in_RETIRE_ROB_RE_OLD_USE [i][j] = interface->set_signal_in ("re_old_use", 1); +// in_RETIRE_ROB_RE_NEW_USE [i][j] = interface->set_signal_in ("re_new_use", 1); +// } +// { +// Interface_fifo * interface = _interfaces->set_interface("retire_rob_gpr_status_old_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,EAST +// ,"Interface to update status (retire)" +// #endif +// ); + +// out_RETIRE_ROB_GPR_STATUS_OLD_VAL [i][j] = interface->set_signal_valack_out(VAL); +// in_RETIRE_ROB_GPR_STATUS_OLD_ACK [i][j] = interface->set_signal_valack_in (ACK); +// } +// { +// Interface_fifo * interface = _interfaces->set_interface("retire_rob_gpr_status_new_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,EAST +// ,"Interface to update status (retire)" +// #endif +// ); + +// out_RETIRE_ROB_GPR_STATUS_NEW_VAL [i][j] = interface->set_signal_valack_out(VAL); +// in_RETIRE_ROB_GPR_STATUS_NEW_ACK [i][j] = interface->set_signal_valack_in (ACK); +// } +// { +// Interface_fifo * interface = _interfaces->set_interface("retire_rob_spr_status_old_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,EAST +// ,"Interface to update status (retire)" +// #endif +// ); + +// out_RETIRE_ROB_SPR_STATUS_OLD_VAL [i][j] = interface->set_signal_valack_out(VAL); +// in_RETIRE_ROB_SPR_STATUS_OLD_ACK [i][j] = interface->set_signal_valack_in (ACK); +// } +// { +// Interface_fifo * interface = _interfaces->set_interface("retire_rob_spr_status_new_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,EAST +// ,"Interface to update status (retire)" +// #endif +// ); + +// out_RETIRE_ROB_SPR_STATUS_NEW_VAL [i][j] = interface->set_signal_valack_out(VAL); +// in_RETIRE_ROB_SPR_STATUS_NEW_ACK [i][j] = interface->set_signal_valack_in (ACK); +// } +// } +// } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_deallocation.cpp (revision 88) @@ -23,4 +23,6 @@ log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + if (usage_is_set(_usage,USE_VHDL)) + { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) delete in_CLOCK ; @@ -95,20 +97,20 @@ delete [] in_INSERT_ROB_SPR_STATUS_ACK ; - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; - delete [] out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; - delete [] in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; - delete [] in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; - delete [] out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; - delete [] out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; - delete [] in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; - delete [] in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; - +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// delete [] in_RETIRE_ROB_VAL ; +// delete [] out_RETIRE_ROB_ACK ; +// delete [] in_RETIRE_ROB_RD_OLD_USE ; +// delete [] in_RETIRE_ROB_RD_NEW_USE ; +// delete [] in_RETIRE_ROB_RE_OLD_USE ; +// delete [] in_RETIRE_ROB_RE_NEW_USE ; +// delete [] out_RETIRE_ROB_GPR_STATUS_OLD_VAL ; +// delete [] out_RETIRE_ROB_GPR_STATUS_NEW_VAL ; +// delete [] in_RETIRE_ROB_GPR_STATUS_OLD_ACK ; +// delete [] in_RETIRE_ROB_GPR_STATUS_NEW_ACK ; +// delete [] out_RETIRE_ROB_SPR_STATUS_OLD_VAL ; +// delete [] out_RETIRE_ROB_SPR_STATUS_NEW_VAL ; +// delete [] in_RETIRE_ROB_SPR_STATUS_OLD_ACK ; +// delete [] in_RETIRE_ROB_SPR_STATUS_NEW_ACK ; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_end_cycle.cpp (revision 88) @@ -24,5 +24,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -30,5 +31,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read.cpp (revision 88) @@ -23,19 +23,28 @@ void Register_unit_Glue::genMealy_gpr_read (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// PORT_WRITE(out_GPR_READ_ACK [j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t registerfile_ack = PORT_READ(in_GPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_ack = PORT_READ(in_GPR_READ_STATUS_ACK [ooo_engine_id][j]); - - // multiplexor - PORT_WRITE(out_GPR_READ_ACK [j], registerfile_ack and status_ack); - PORT_WRITE(out_GPR_READ_DATA [j], PORT_READ(in_GPR_READ_REGISTERFILE_DATA[ooo_engine_id][j])); - PORT_WRITE(out_GPR_READ_DATA_VAL [j], PORT_READ(in_GPR_READ_STATUS_DATA_VAL [ooo_engine_id][j])); + for (uint32_t j=0; j<_param->_nb_gpr_read; j++) + { + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t registerfile_ack = PORT_READ(in_GPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_ack = PORT_READ(in_GPR_READ_STATUS_ACK [ooo_engine_id][j]); + + // multiplexor + PORT_WRITE(out_GPR_READ_ACK [j], registerfile_ack and status_ack); + PORT_WRITE(out_GPR_READ_DATA [j], PORT_READ(in_GPR_READ_REGISTERFILE_DATA[ooo_engine_id][j])); + PORT_WRITE(out_GPR_READ_DATA_VAL [j], PORT_READ(in_GPR_READ_STATUS_DATA_VAL [ooo_engine_id][j])); + } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_registerfile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_registerfile.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_registerfile.cpp (revision 88) @@ -23,22 +23,32 @@ void Register_unit_Glue::genMealy_gpr_read_registerfile (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_GPR_READ_REGISTERFILE_VAL [i][j],0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_GPR_READ_VAL [j]); - Tcontrol_t status_ack = PORT_READ(in_GPR_READ_STATUS_ACK [ooo_engine_id][j]); - - Tcontrol_t registerfile_val = val and status_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_gpr_read; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_GPR_READ_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_GPR_READ_VAL [j]); + Tcontrol_t status_ack = PORT_READ(in_GPR_READ_STATUS_ACK [ooo_engine_id][j]); + + Tcontrol_t registerfile_val = val and status_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_GPR_READ_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_status.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_status.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_read_status.cpp (revision 88) @@ -23,22 +23,32 @@ void Register_unit_Glue::genMealy_gpr_read_status (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_read; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_GPR_READ_STATUS_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_GPR_READ_VAL [j]); - Tcontrol_t registerfile_ack = PORT_READ(in_GPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); - - Tcontrol_t status_val = val and registerfile_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_gpr_read; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_GPR_READ_STATUS_VAL [i][j], (id and status_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_GPR_READ_VAL [j]); + Tcontrol_t registerfile_ack = PORT_READ(in_GPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); + + Tcontrol_t status_val = val and registerfile_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_GPR_READ_STATUS_VAL [i][j], (id and status_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_registerfile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_registerfile.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_registerfile.cpp (revision 88) @@ -23,21 +23,31 @@ void Register_unit_Glue::genMealy_gpr_write_registerfile (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_gpr_write; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_GPR_WRITE_REGISTERFILE_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_GPR_WRITE_VAL [j]); - Tcontrol_t status_ack = PORT_READ(in_GPR_WRITE_STATUS_ACK [ooo_engine_id][j]); - Tcontrol_t registerfile_val = val and status_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_gpr_write; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_GPR_WRITE_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_GPR_WRITE_VAL [j]); + Tcontrol_t status_ack = PORT_READ(in_GPR_WRITE_STATUS_ACK [ooo_engine_id][j]); + Tcontrol_t registerfile_val = val and status_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_GPR_WRITE_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write.cpp (revision 88) @@ -23,17 +23,26 @@ void Register_unit_Glue::genMealy_gpr_write (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); - - for (uint32_t j=0; j<_param->_nb_gpr_write; j++) + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_GPR_WRITE_ACK [j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t registerfile_ack = PORT_READ(in_GPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_ack = PORT_READ(in_GPR_WRITE_STATUS_ACK [ooo_engine_id][j]); - - // multiplexor - PORT_WRITE(out_GPR_WRITE_ACK [j],registerfile_ack and status_ack); + for (uint32_t j=0; j<_param->_nb_gpr_write; j++) + { + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t registerfile_ack = PORT_READ(in_GPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_ack = PORT_READ(in_GPR_WRITE_STATUS_ACK [ooo_engine_id][j]); + + // multiplexor + PORT_WRITE(out_GPR_WRITE_ACK [j],registerfile_ack and status_ack); + } } - - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_gpr_write_status.cpp (revision 88) @@ -23,21 +23,31 @@ void Register_unit_Glue::genMealy_gpr_write_status (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_gpr_write; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_gpr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_GPR_WRITE_STATUS_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_GPR_WRITE_VAL [j]); - Tcontrol_t registerfile_ack = PORT_READ(in_GPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_val = val and registerfile_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_gpr_write; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_GPR_WRITE_STATUS_VAL [i][j], (id and status_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_GPR_WRITE_VAL [j]); + Tcontrol_t registerfile_ack = PORT_READ(in_GPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_val = val and registerfile_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_GPR_WRITE_STATUS_VAL [i][j], (id and status_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_insert.cpp (revision 88) @@ -23,25 +23,42 @@ void Register_unit_Glue::genMealy_insert (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_insert_rob [i]; + for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) + { + Tcontrol_t val = PORT_READ(in_INSERT_ROB_VAL [i][j]); + Tcontrol_t gpr_use = PORT_READ(in_INSERT_ROB_RD_USE [i][j]); + Tcontrol_t spr_use = PORT_READ(in_INSERT_ROB_RE_USE [i][j]); + Tcontrol_t gpr_status_ack = PORT_READ(in_INSERT_ROB_GPR_STATUS_ACK [i][j]); + Tcontrol_t spr_status_ack = PORT_READ(in_INSERT_ROB_SPR_STATUS_ACK [i][j]); + + Tcontrol_t ack = (gpr_status_ack and + spr_status_ack); + Tcontrol_t gpr_status_val = (val and + gpr_use and + spr_status_ack); + Tcontrol_t spr_status_val = (val and + spr_use and + gpr_status_ack); - for (uint32_t j=0; j_nb_ooo_engine; i++) @@ -57,5 +59,5 @@ } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; @@ -68,4 +70,5 @@ }; // end namespace behavioural }; // end namespace morpheo +*/ #endif //#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read.cpp (revision 88) @@ -23,19 +23,28 @@ void Register_unit_Glue::genMealy_spr_read (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// PORT_WRITE(out_SPR_READ_ACK [j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t registerfile_ack = PORT_READ(in_SPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_ack = PORT_READ(in_SPR_READ_STATUS_ACK [ooo_engine_id][j]); - - // multiplexor - PORT_WRITE(out_SPR_READ_ACK [j], registerfile_ack and status_ack); - PORT_WRITE(out_SPR_READ_DATA [j], PORT_READ(in_SPR_READ_REGISTERFILE_DATA[ooo_engine_id][j])); - PORT_WRITE(out_SPR_READ_DATA_VAL [j], PORT_READ(in_SPR_READ_STATUS_DATA_VAL [ooo_engine_id][j])); + for (uint32_t j=0; j<_param->_nb_spr_read; j++) + { + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t registerfile_ack = PORT_READ(in_SPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_ack = PORT_READ(in_SPR_READ_STATUS_ACK [ooo_engine_id][j]); + + // multiplexor + PORT_WRITE(out_SPR_READ_ACK [j], registerfile_ack and status_ack); + PORT_WRITE(out_SPR_READ_DATA [j], PORT_READ(in_SPR_READ_REGISTERFILE_DATA[ooo_engine_id][j])); + PORT_WRITE(out_SPR_READ_DATA_VAL [j], PORT_READ(in_SPR_READ_STATUS_DATA_VAL [ooo_engine_id][j])); + } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_registerfile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_registerfile.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_registerfile.cpp (revision 88) @@ -23,22 +23,31 @@ void Register_unit_Glue::genMealy_spr_read_registerfile (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_SPR_READ_REGISTERFILE_VAL [i][j],0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_SPR_READ_VAL [j]); - Tcontrol_t status_ack = PORT_READ(in_SPR_READ_STATUS_ACK [ooo_engine_id][j]); - - Tcontrol_t registerfile_val = val and status_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_spr_read; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_SPR_READ_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_SPR_READ_VAL [j]); + + Tcontrol_t registerfile_val = val and PORT_READ(in_SPR_READ_STATUS_ACK [ooo_engine_id][j]); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_SPR_READ_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_status.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_status.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_read_status.cpp (revision 88) @@ -23,22 +23,31 @@ void Register_unit_Glue::genMealy_spr_read_status (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_read; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_SPR_READ_STATUS_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_SPR_READ_VAL [j]); - Tcontrol_t registerfile_ack = PORT_READ(in_SPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); - - Tcontrol_t status_val = val and registerfile_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_spr_read; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_SPR_READ_STATUS_VAL [i][j], (id and status_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_READ_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_SPR_READ_VAL [j]); + + Tcontrol_t status_val = val and PORT_READ(in_SPR_READ_REGISTERFILE_ACK [ooo_engine_id][j]); + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_SPR_READ_STATUS_VAL [i][j], (id and status_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_registerfile.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_registerfile.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_registerfile.cpp (revision 88) @@ -23,21 +23,31 @@ void Register_unit_Glue::genMealy_spr_write_registerfile (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_SPR_WRITE_REGISTERFILE_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_SPR_WRITE_VAL [j]); - Tcontrol_t status_ack = PORT_READ(in_SPR_WRITE_STATUS_ACK [ooo_engine_id][j]); - Tcontrol_t registerfile_val = val and status_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_spr_write; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_SPR_WRITE_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_SPR_WRITE_VAL [j]); + Tcontrol_t status_ack = PORT_READ(in_SPR_WRITE_STATUS_ACK [ooo_engine_id][j]); + Tcontrol_t registerfile_val = val and status_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_SPR_WRITE_REGISTERFILE_VAL [i][j], (id and registerfile_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write.cpp (revision 88) @@ -23,17 +23,27 @@ void Register_unit_Glue::genMealy_spr_write (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_SPR_WRITE_ACK [j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t registerfile_ack = PORT_READ(in_SPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_ack = PORT_READ(in_SPR_WRITE_STATUS_ACK [ooo_engine_id][j]); - - // multiplexor - PORT_WRITE(out_SPR_WRITE_ACK [j],registerfile_ack and status_ack); + for (uint32_t j=0; j<_param->_nb_spr_write; j++) + { + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t registerfile_ack = PORT_READ(in_SPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_ack = PORT_READ(in_SPR_WRITE_STATUS_ACK [ooo_engine_id][j]); + + // multiplexor + PORT_WRITE(out_SPR_WRITE_ACK [j],registerfile_ack and status_ack); + } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write_status.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write_status.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_genMealy_spr_write_status.cpp (revision 88) @@ -23,21 +23,31 @@ void Register_unit_Glue::genMealy_spr_write_status (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); + log_function(Register_unit_Glue,FUNCTION,_name.c_str()); - for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// if (not PORT_READ(in_NRESET)) +// { +// for (uint32_t j=0; j<_param->_nb_spr_write; j++) +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// PORT_WRITE(out_SPR_WRITE_STATUS_VAL [i][j], 0); +// } +// else { - Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; - Tcontrol_t val = PORT_READ(in_SPR_WRITE_VAL [j]); - Tcontrol_t registerfile_ack = PORT_READ(in_SPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); - Tcontrol_t status_val = val and registerfile_ack; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + for (uint32_t j=0; j<_param->_nb_spr_write; j++) { - Tcontrol_t id = (i == ooo_engine_id)?1:0; - PORT_WRITE(out_SPR_WRITE_STATUS_VAL [i][j], (id and status_val)); + Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id == true)?PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID[j]):0; + Tcontrol_t val = PORT_READ(in_SPR_WRITE_VAL [j]); + Tcontrol_t registerfile_ack = PORT_READ(in_SPR_WRITE_REGISTERFILE_ACK [ooo_engine_id][j]); + Tcontrol_t status_val = val and registerfile_ack; + + for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) + { + Tcontrol_t id = (i == ooo_engine_id)?1:0; + PORT_WRITE(out_SPR_WRITE_STATUS_VAL [i][j], (id and status_val)); + } } } - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_transition.cpp (revision 88) @@ -22,5 +22,5 @@ void Register_unit_Glue::transition (void) { - log_printf(FUNC,Register_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_unit_Glue,FUNCTION); #if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -28,5 +28,5 @@ #endif - log_printf(FUNC,Register_unit_Glue,FUNCTION,"End"); + log_end(Register_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_vhdl_body.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue/src/Register_unit_Glue_vhdl_body.cpp (revision 88) @@ -37,5 +37,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_0_"+toString(j)+"_ACK and in_GPR_READ_STATUS_0_"+toString(j)+"_ACK;"); @@ -48,5 +48,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_GPR_READ_REGISTERFILE_0_"+toString(j)+"_DATA;"); @@ -59,5 +59,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_GPR_READ_STATUS_0_"+toString(j)+"_DATA_VAL;"); @@ -71,5 +71,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_READ_"+toString(j)+"_VAL and in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_READ_"+toString(j)+"_VAL and in_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -80,5 +80,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_READ_"+toString(j)+"_VAL and in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_GPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_READ_"+toString(j)+"_VAL and in_GPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -102,5 +102,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_GPR_WRITE_REGISTERFILE_0_"+toString(j)+"_ACK and in_GPR_WRITE_STATUS_0_"+toString(j)+"_ACK;"); @@ -114,5 +114,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_WRITE_"+toString(j)+"_VAL and in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_WRITE_"+toString(j)+"_VAL and in_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -123,5 +123,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_WRITE_"+toString(j)+"_VAL and in_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_GPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_GPR_WRITE_"+toString(j)+"_VAL and in_GPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_GPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -145,5 +145,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_0_"+toString(j)+"_ACK and in_SPR_READ_STATUS_0_"+toString(j)+"_ACK;"); @@ -156,5 +156,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_DATA when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_SPR_READ_REGISTERFILE_0_"+toString(j)+"_DATA;"); @@ -167,5 +167,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_DATA_VAL when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_SPR_READ_STATUS_0_"+toString(j)+"_DATA_VAL;"); @@ -179,5 +179,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_READ_"+toString(j)+"_VAL and in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_READ_"+toString(j)+"_VAL and in_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -188,5 +188,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_READ_"+toString(j)+"_VAL and in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_SPR_READ_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_READ_"+toString(j)+"_VAL and in_SPR_READ_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_READ_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -210,5 +210,5 @@ for (uint32_t i=_param->_nb_ooo_engine-1; i>=1; i--) { - vhdl->set_body ("\tin_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else"); + vhdl->set_body ("\tin_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK and in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else"); } vhdl->set_body ("\tin_SPR_WRITE_REGISTERFILE_0_"+toString(j)+"_ACK and in_SPR_WRITE_STATUS_0_"+toString(j)+"_ACK;"); @@ -222,5 +222,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_WRITE_"+toString(j)+"_VAL and in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_WRITE_"+toString(j)+"_VAL and in_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } @@ -231,5 +231,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) { - vhdl->set_body ("out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_WRITE_"+toString(j)+"_VAL and in_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(log2(_param->_nb_ooo_engine),i)+" else '0';"); + vhdl->set_body ("out_SPR_WRITE_STATUS_"+toString(i)+"_"+toString(j)+"_VAL <= in_SPR_WRITE_"+toString(j)+"_VAL and in_SPR_WRITE_REGISTERFILE_"+toString(i)+"_"+toString(j)+"_ACK when in_SPR_WRITE_"+toString(j)+"_OOO_ENGINE_ID = "+std_logic_conv(_param->_size_ooo_engine_id,i)+" else '0';"); } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Register_unit_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/include/test.h (revision 88) @@ -16,4 +16,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h" +#include "Common/include/Time.h" using namespace std; @@ -28,34 +29,2 @@ void test (string name, morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::Parameters * param); - -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/main.cpp (revision 88) @@ -104,5 +104,7 @@ _nb_special_register , _nb_inst_insert_rob , - _nb_inst_retire_rob ); + _nb_inst_retire_rob , + true //is_toplevel + ); cout << param->print(1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/src/test.cpp (revision 88) @@ -22,4 +22,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Register_unit * _Register_unit = new Register_unit (name.c_str(), @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -75,15 +85,15 @@ sc_signal *** in_INSERT_ROB_RE_NUM_REG ; - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - sc_signal *** in_RETIRE_ROB_VAL ; - sc_signal *** out_RETIRE_ROB_ACK ; - sc_signal *** in_RETIRE_ROB_RD_OLD_USE ; - sc_signal *** in_RETIRE_ROB_RD_OLD_NUM_REG ; // old_use=1 : status[old_num_reg]<- 0 - sc_signal *** in_RETIRE_ROB_RD_NEW_USE ; - sc_signal *** in_RETIRE_ROB_RD_NEW_NUM_REG ; // new_use=1 : status[new_num_reg]<- 1 - sc_signal *** in_RETIRE_ROB_RE_OLD_USE ; - sc_signal *** in_RETIRE_ROB_RE_OLD_NUM_REG ; - sc_signal *** in_RETIRE_ROB_RE_NEW_USE ; - sc_signal *** in_RETIRE_ROB_RE_NEW_NUM_REG ; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// sc_signal *** in_RETIRE_ROB_VAL ; +// sc_signal *** out_RETIRE_ROB_ACK ; +// sc_signal *** in_RETIRE_ROB_RD_OLD_USE ; +// sc_signal *** in_RETIRE_ROB_RD_OLD_NUM_REG ; // old_use=1 : status[old_num_reg]<- 0 +// sc_signal *** in_RETIRE_ROB_RD_NEW_USE ; +// sc_signal *** in_RETIRE_ROB_RD_NEW_NUM_REG ; // new_use=1 : status[new_num_reg]<- 1 +// sc_signal *** in_RETIRE_ROB_RE_OLD_USE ; +// sc_signal *** in_RETIRE_ROB_RE_OLD_NUM_REG ; +// sc_signal *** in_RETIRE_ROB_RE_NEW_USE ; +// sc_signal *** in_RETIRE_ROB_RE_NEW_NUM_REG ; string rename = "signal"; @@ -192,45 +202,45 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_RETIRE_ROB_VAL = new sc_signal ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_ACK = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - - in_RETIRE_ROB_VAL [i] = new sc_signal * [x]; - out_RETIRE_ROB_ACK [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_OLD_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_OLD_NUM_REG [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_OLD_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_OLD_NUM_REG [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_NEW_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RD_NEW_NUM_REG [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_NEW_USE [i] = new sc_signal * [x]; - in_RETIRE_ROB_RE_NEW_NUM_REG [i] = new sc_signal * [x]; - - for (uint32_t j=0; j (rename.c_str()); - out_RETIRE_ROB_ACK [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_OLD_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_OLD_NUM_REG [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_OLD_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_OLD_NUM_REG [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_NEW_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RD_NEW_NUM_REG [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_NEW_USE [i][j] = new sc_signal (rename.c_str()); - in_RETIRE_ROB_RE_NEW_NUM_REG [i][j] = new sc_signal (rename.c_str()); - } - } +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// in_RETIRE_ROB_VAL = new sc_signal ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_ACK = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_USE = new sc_signal ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_NUM_REG = new sc_signal ** [_param->_nb_ooo_engine]; + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; + +// in_RETIRE_ROB_VAL [i] = new sc_signal * [x]; +// out_RETIRE_ROB_ACK [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_OLD_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_OLD_NUM_REG [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_OLD_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_OLD_NUM_REG [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_NEW_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RD_NEW_NUM_REG [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_NEW_USE [i] = new sc_signal * [x]; +// in_RETIRE_ROB_RE_NEW_NUM_REG [i] = new sc_signal * [x]; + +// for (uint32_t j=0; j (rename.c_str()); +// out_RETIRE_ROB_ACK [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_OLD_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_OLD_NUM_REG [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_OLD_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_OLD_NUM_REG [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_NEW_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RD_NEW_NUM_REG [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_NEW_USE [i][j] = new sc_signal (rename.c_str()); +// in_RETIRE_ROB_RE_NEW_NUM_REG [i][j] = new sc_signal (rename.c_str()); +// } +// } @@ -292,18 +302,18 @@ (*(_Register_unit-> in_INSERT_ROB_RE_NUM_REG [i][j]))(*( in_INSERT_ROB_RE_NUM_REG [i][j])); } - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) - { - (*(_Register_unit-> in_RETIRE_ROB_VAL [i][j]))(*( in_RETIRE_ROB_VAL [i][j])); - (*(_Register_unit->out_RETIRE_ROB_ACK [i][j]))(*(out_RETIRE_ROB_ACK [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_USE [i][j]))(*( in_RETIRE_ROB_RD_OLD_USE [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_OLD_NUM_REG [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_USE [i][j]))(*( in_RETIRE_ROB_RE_OLD_USE [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_OLD_NUM_REG [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_USE [i][j]))(*( in_RETIRE_ROB_RD_NEW_USE [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_NEW_NUM_REG [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_USE [i][j]))(*( in_RETIRE_ROB_RE_NEW_USE [i][j])); - (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_NEW_NUM_REG [i][j])); - } +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) +// { +// (*(_Register_unit-> in_RETIRE_ROB_VAL [i][j]))(*( in_RETIRE_ROB_VAL [i][j])); +// (*(_Register_unit->out_RETIRE_ROB_ACK [i][j]))(*(out_RETIRE_ROB_ACK [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_USE [i][j]))(*( in_RETIRE_ROB_RD_OLD_USE [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_OLD_NUM_REG [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_USE [i][j]))(*( in_RETIRE_ROB_RE_OLD_USE [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_OLD_NUM_REG [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_USE [i][j]))(*( in_RETIRE_ROB_RD_NEW_USE [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_NEW_NUM_REG [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_USE [i][j]))(*( in_RETIRE_ROB_RE_NEW_USE [i][j])); +// (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_NEW_NUM_REG [i][j])); +// } cout << "<" << name << "> Start Simulation ............" << endl; @@ -331,6 +341,6 @@ const int32_t percent_transaction_insert = 70; const int32_t percent_transaction_insert_use = 70; - const int32_t percent_transaction_retire = 70; - const int32_t percent_transaction_retire_use = 70; +// const int32_t percent_transaction_retire = 70; +// const int32_t percent_transaction_retire_use = 70; const uint32_t nb_request = max_nb_general_register; @@ -365,6 +375,6 @@ for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) in_INSERT_ROB_VAL [i][j]->write(0); - for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) - in_RETIRE_ROB_VAL [i][j]->write(0); +// for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) +// in_RETIRE_ROB_VAL [i][j]->write(0); } @@ -709,53 +719,53 @@ } - LABEL("retire rob"); - - cpt = 0; - - while (cpt < nb_request) - { - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - for (uint32_t j=0; jwrite((rand() % 100) < percent_transaction_retire); - in_RETIRE_ROB_RD_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); - in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); - in_RETIRE_ROB_RD_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); - in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); - in_RETIRE_ROB_RE_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); - in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); - in_RETIRE_ROB_RE_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); - in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); - } - } - - SC_START(1); - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - for (uint32_t j=0; jread() and out_RETIRE_ROB_ACK [i][j]->read()) - { - cpt ++; +// LABEL("retire rob"); + +// cpt = 0; + +// while (cpt < nb_request) +// { +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; +// for (uint32_t j=0; jwrite((rand() % 100) < percent_transaction_retire); +// in_RETIRE_ROB_RD_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); +// in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); +// in_RETIRE_ROB_RD_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); +// in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); +// in_RETIRE_ROB_RE_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); +// in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); +// in_RETIRE_ROB_RE_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); +// in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); +// } +// } + +// SC_START(1); + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; +// for (uint32_t j=0; jread() and out_RETIRE_ROB_ACK [i][j]->read()) +// { +// cpt ++; - if (in_RETIRE_ROB_RD_OLD_USE [i][j]->read()) - gpr_status [i][in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->read()] = 0; - if (in_RETIRE_ROB_RD_NEW_USE [i][j]->read()) - gpr_status [i][in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->read()] = 1; - if (in_RETIRE_ROB_RE_OLD_USE [i][j]->read()) - spr_status [i][in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->read()] = 0; - if (in_RETIRE_ROB_RE_NEW_USE [i][j]->read()) - spr_status [i][in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->read()] = 1; - } - } - } - } - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) - in_RETIRE_ROB_VAL [i][j]->write(0); +// if (in_RETIRE_ROB_RD_OLD_USE [i][j]->read()) +// gpr_status [i][in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->read()] = 0; +// if (in_RETIRE_ROB_RD_NEW_USE [i][j]->read()) +// gpr_status [i][in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->read()] = 1; +// if (in_RETIRE_ROB_RE_OLD_USE [i][j]->read()) +// spr_status [i][in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->read()] = 0; +// if (in_RETIRE_ROB_RE_NEW_USE [i][j]->read()) +// spr_status [i][in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->read()] = 1; +// } +// } +// } +// } +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) +// in_RETIRE_ROB_VAL [i][j]->write(0); LABEL("(GPR) Read - and test data writted"); @@ -889,14 +899,14 @@ delete [] in_INSERT_ROB_RE_USE ; delete [] in_INSERT_ROB_RE_NUM_REG ; - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; +// delete [] in_RETIRE_ROB_VAL ; +// delete [] out_RETIRE_ROB_ACK ; +// delete [] in_RETIRE_ROB_RD_OLD_USE ; +// delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; +// delete [] in_RETIRE_ROB_RD_NEW_USE ; +// delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; +// delete [] in_RETIRE_ROB_RE_OLD_USE ; +// delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; +// delete [] in_RETIRE_ROB_RE_NEW_USE ; +// delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Parameters.h (revision 88) @@ -25,25 +25,25 @@ { //-----[ fields ]------------------------------------------------------------ - public : const uint32_t _nb_ooo_engine ; - public : const uint32_t _size_general_data ; - public : const uint32_t _size_special_data ; - public : const uint32_t _nb_gpr_read ; - public : const uint32_t _nb_gpr_write ; - public : const uint32_t _nb_gpr_bank ; - public : const uint32_t _nb_gpr_port_read_by_bank ; - public : const uint32_t _nb_gpr_port_write_by_bank; - public : const uint32_t _nb_spr_read ; - public : const uint32_t _nb_spr_write ; - public : const uint32_t _nb_spr_bank ; - public : const uint32_t _nb_spr_port_read_by_bank ; - public : const uint32_t _nb_spr_port_write_by_bank; - public : const uint32_t * _nb_general_register ; - public : const uint32_t * _nb_special_register ; - public : const uint32_t * _nb_inst_insert_rob ; - public : const uint32_t * _nb_inst_retire_rob ; + public : uint32_t _nb_ooo_engine ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t _nb_gpr_read ; + public : uint32_t _nb_gpr_write ; + public : uint32_t _nb_gpr_bank ; + public : uint32_t _nb_gpr_port_read_by_bank ; + public : uint32_t _nb_gpr_port_write_by_bank; + public : uint32_t _nb_spr_read ; + public : uint32_t _nb_spr_write ; + public : uint32_t _nb_spr_bank ; + public : uint32_t _nb_spr_port_read_by_bank ; + public : uint32_t _nb_spr_port_write_by_bank; + public : uint32_t * _nb_general_register ; + public : uint32_t * _nb_special_register ; + public : uint32_t * _nb_inst_insert_rob ; + public : uint32_t * _nb_inst_retire_rob ; - public : const bool _have_port_ooo_engine_id ; - public : uint32_t _size_gpr_address ; - public : uint32_t _size_spr_address ; +//public : bool _have_port_ooo_engine_id ; + public : uint32_t _size_gpr_address ; + public : uint32_t _size_spr_address ; public : morpheo::behavioural::generic::registerfile::Parameters ** _param_gpr ; @@ -51,8 +51,8 @@ public : morpheo::behavioural::generic::registerfile::Parameters ** _param_spr ; public : morpheo::behavioural::generic::registerfile::Parameters ** _param_spr_status ; - public : morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters ** __param_gpr ; - public : morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters ** __param_gpr_status; - public : morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters ** __param_spr ; - public : morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters ** __param_spr_status; + private: morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters ** __param_gpr ; + private: morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters ** __param_gpr_status; + private: morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters ** __param_spr ; + private: morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters ** __param_spr_status; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::register_unit_glue::Parameters * _param_glue ; @@ -74,10 +74,14 @@ uint32_t * nb_special_register , uint32_t * nb_inst_insert_rob , - uint32_t * nb_inst_retire_rob ); + uint32_t * nb_inst_retire_rob , + bool is_toplevel=false); - public : Parameters (Parameters & param) ; +//public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h (revision 88) @@ -102,15 +102,15 @@ public : SC_IN (Tspecial_address_t) *** in_INSERT_ROB_RE_NUM_REG ; - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ; - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ; - public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_OLD_NUM_REG ; // old_use=1 : status[old_num_reg]<- 0 - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ; - public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_NEW_NUM_REG ; // new_use=1 : status[new_num_reg]<- 1 - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ; - public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_OLD_NUM_REG ; - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ; - public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_NEW_NUM_REG ; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ; +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ; +// public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_OLD_NUM_REG ; // old_use=1 : status[old_num_reg]<- 0 +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ; +// public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_NEW_NUM_REG ; // new_use=1 : status[new_num_reg]<- 1 +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ; +// public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_OLD_NUM_REG ; +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ; +// public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_NEW_NUM_REG ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Parameters.cpp (revision 88) @@ -34,26 +34,25 @@ uint32_t * nb_special_register , uint32_t * nb_inst_insert_rob , - uint32_t * nb_inst_retire_rob ): - _nb_ooo_engine (nb_ooo_engine ), - _size_general_data (size_general_data ), - _size_special_data (size_special_data ), - _nb_gpr_read (nb_gpr_read ), - _nb_gpr_write (nb_gpr_write ), - _nb_gpr_bank (nb_gpr_bank ), - _nb_gpr_port_read_by_bank (nb_gpr_port_read_by_bank ), - _nb_gpr_port_write_by_bank (nb_gpr_port_write_by_bank), - _nb_spr_read (nb_spr_read ), - _nb_spr_write (nb_spr_write ), - _nb_spr_bank (nb_spr_bank ), - _nb_spr_port_read_by_bank (nb_spr_port_read_by_bank ), - _nb_spr_port_write_by_bank (nb_spr_port_write_by_bank), - _nb_general_register (nb_general_register ), - _nb_special_register (nb_special_register ), - _nb_inst_insert_rob (nb_inst_insert_rob ), - _nb_inst_retire_rob (nb_inst_retire_rob ), - _have_port_ooo_engine_id (nb_ooo_engine>1 ) - + uint32_t * nb_inst_retire_rob , + bool is_toplevel ) { log_printf(FUNC,Register_unit,FUNCTION,"Begin"); + + + _nb_ooo_engine = nb_ooo_engine ; + _nb_gpr_read = nb_gpr_read ; + _nb_gpr_write = nb_gpr_write ; + _nb_gpr_bank = nb_gpr_bank ; + _nb_gpr_port_read_by_bank = nb_gpr_port_read_by_bank ; + _nb_gpr_port_write_by_bank = nb_gpr_port_write_by_bank; + _nb_spr_read = nb_spr_read ; + _nb_spr_write = nb_spr_write ; + _nb_spr_bank = nb_spr_bank ; + _nb_spr_port_read_by_bank = nb_spr_port_read_by_bank ; + _nb_spr_port_write_by_bank = nb_spr_port_write_by_bank; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_inst_insert_rob = nb_inst_insert_rob ; + _nb_inst_retire_rob = nb_inst_retire_rob ; _size_gpr_address = log2(nb_general_register [0]); @@ -74,5 +73,4 @@ _size_spr_address = new_size; } - _param_gpr = new morpheo::behavioural::generic::registerfile::Parameters * [_nb_ooo_engine]; @@ -86,116 +84,138 @@ __param_spr_status = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters * [_nb_ooo_engine]; - for (uint32_t i=0; i<_nb_ooo_engine; i++) - { - Tcrossbar_t crossbar = PARTIAL_CROSSBAR; - - __param_gpr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters - (_nb_gpr_read , - _nb_gpr_write , - _nb_general_register[i] , - _size_general_data , - _nb_gpr_bank , - _nb_gpr_port_read_by_bank , - _nb_gpr_port_write_by_bank, - crossbar ); - - __param_gpr_status [i] = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters - (_nb_gpr_read , - _nb_gpr_write+_nb_inst_insert_rob[i]+2*_nb_inst_retire_rob[i], - 0, - nb_general_register[i], - 1); - - __param_spr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters - (_nb_spr_read , - _nb_spr_write , - _nb_special_register[i] , - _size_special_data , - _nb_spr_bank , - _nb_spr_port_read_by_bank , - _nb_spr_port_write_by_bank, - crossbar ); - - __param_spr_status [i] = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters - (_nb_spr_read , - _nb_spr_write+_nb_inst_insert_rob[i]+2*_nb_inst_retire_rob[i], - 0, - nb_special_register[i], - 1); - - _param_gpr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr [i]); - _param_gpr_status [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr_status [i]); - _param_spr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_spr [i]); - _param_spr_status [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_spr_status [i]); - } - - _param_glue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::register_unit_glue::Parameters (_nb_ooo_engine , - _size_general_data , - _size_special_data , - _nb_gpr_read , - _nb_spr_read , - _nb_gpr_write , - _nb_spr_write , - _nb_inst_insert_rob , - _nb_inst_retire_rob ); - + for (uint32_t i=0; i<_nb_ooo_engine; i++) + { + Tcrossbar_t crossbar = PARTIAL_CROSSBAR; + + __param_gpr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters + (_nb_gpr_read , + _nb_gpr_write , + _nb_general_register[i] , + size_general_data , + _nb_gpr_bank , + _nb_gpr_port_read_by_bank , + _nb_gpr_port_write_by_bank, + crossbar ); + + __param_gpr_status [i] = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters + (_nb_gpr_read , +// _nb_gpr_write+_nb_inst_insert_rob[i]+2*_nb_inst_retire_rob[i], + _nb_gpr_write+_nb_inst_insert_rob[i], + 0, + nb_general_register[i], + 1); + + __param_spr [i] = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters + (_nb_spr_read , + _nb_spr_write , + _nb_special_register[i] , + size_special_data , + _nb_spr_bank , + _nb_spr_port_read_by_bank , + _nb_spr_port_write_by_bank, + crossbar ); + + __param_spr_status [i] = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters + (_nb_spr_read , +// _nb_spr_write+_nb_inst_insert_rob[i]+2*_nb_inst_retire_rob[i], + _nb_spr_write+_nb_inst_insert_rob[i], + 0, + nb_special_register[i], + 1); + + _param_gpr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr [i]); + _param_gpr_status [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_gpr_status [i]); + _param_spr [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_spr [i]); + _param_spr_status [i] = new morpheo::behavioural::generic::registerfile::Parameters (__param_spr_status [i]); + } - - + _param_glue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::register_unit_glue::Parameters (_nb_ooo_engine , + size_general_data , + size_special_data , + _nb_gpr_read , + _nb_spr_read , + _nb_gpr_write , + _nb_spr_write , + _nb_inst_insert_rob , + _nb_inst_retire_rob ); + test(); - log_printf(FUNC,Register_unit,FUNCTION,"End"); + + if (is_toplevel) + { + _size_ooo_engine_id = log2(nb_ooo_engine); + _size_general_data = size_general_data; + _size_special_data = size_special_data; + + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + + copy(); + } + + log_printf(FUNC,Register_unit,FUNCTION,"End"); }; +// #undef FUNCTION +// #define FUNCTION "Register_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _nb_ooo_engine (param._nb_ooo_engine ), +// _size_general_data (param._size_general_data ), +// _size_special_data (param._size_special_data ), +// _nb_gpr_read (param._nb_gpr_read ), +// _nb_gpr_write (param._nb_gpr_write ), +// _nb_gpr_bank (param._nb_gpr_bank ), +// _nb_gpr_port_read_by_bank (param._nb_gpr_port_read_by_bank ), +// _nb_gpr_port_write_by_bank (param._nb_gpr_port_write_by_bank), +// _nb_spr_read (param._nb_spr_read ), +// _nb_spr_write (param._nb_spr_write ), +// _nb_spr_bank (param._nb_spr_bank ), +// _nb_spr_port_read_by_bank (param._nb_spr_port_read_by_bank ), +// _nb_spr_port_write_by_bank (param._nb_spr_port_write_by_bank), +// _nb_general_register (param._nb_general_register ), +// _nb_special_register (param._nb_special_register ), +// _nb_inst_insert_rob (param._nb_inst_insert_rob ), +// _nb_inst_retire_rob (param._nb_inst_retire_rob ), +// _have_port_ooo_engine_id (param._have_port_ooo_engine_id ) +// { +// log_printf(FUNC,Register_unit,FUNCTION,"Begin"); + +// _size_gpr_address = param._size_gpr_address; +// _size_spr_address = param._size_spr_address; + +// __param_gpr = param.__param_gpr ; +// __param_gpr_status = param.__param_gpr_status; +// __param_spr = param.__param_spr ; +// __param_spr_status = param.__param_spr_status; +// _param_gpr = param._param_gpr ; +// _param_gpr_status = param._param_gpr_status; +// _param_spr = param._param_spr ; +// _param_spr_status = param._param_spr_status; +// _param_glue = param._param_glue ; + +// test(); +// log_printf(FUNC,Register_unit,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Register_unit::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _nb_ooo_engine (param._nb_ooo_engine ), - _size_general_data (param._size_general_data ), - _size_special_data (param._size_special_data ), - _nb_gpr_read (param._nb_gpr_read ), - _nb_gpr_write (param._nb_gpr_write ), - _nb_gpr_bank (param._nb_gpr_bank ), - _nb_gpr_port_read_by_bank (param._nb_gpr_port_read_by_bank ), - _nb_gpr_port_write_by_bank (param._nb_gpr_port_write_by_bank), - _nb_spr_read (param._nb_spr_read ), - _nb_spr_write (param._nb_spr_write ), - _nb_spr_bank (param._nb_spr_bank ), - _nb_spr_port_read_by_bank (param._nb_spr_port_read_by_bank ), - _nb_spr_port_write_by_bank (param._nb_spr_port_write_by_bank), - _nb_general_register (param._nb_general_register ), - _nb_special_register (param._nb_special_register ), - _nb_inst_insert_rob (param._nb_inst_insert_rob ), - _nb_inst_retire_rob (param._nb_inst_retire_rob ), - _have_port_ooo_engine_id (param._have_port_ooo_engine_id ) +#define FUNCTION "Register_unit::~Parameters" + Parameters::~Parameters (void) { log_printf(FUNC,Register_unit,FUNCTION,"Begin"); - _size_gpr_address = param._size_gpr_address; - _size_spr_address = param._size_spr_address; - - __param_gpr = param.__param_gpr ; - __param_gpr_status = param.__param_gpr_status; - __param_spr = param.__param_spr ; - __param_spr_status = param.__param_spr_status; - _param_gpr = param._param_gpr ; - _param_gpr_status = param._param_gpr_status; - _param_spr = param._param_spr ; - _param_spr_status = param._param_spr_status; - _param_glue = param._param_glue ; - - test(); - log_printf(FUNC,Register_unit,FUNCTION,"End"); - }; - -#undef FUNCTION -#define FUNCTION "Register_unit::~Parameters" - Parameters::~Parameters () - { - log_printf(FUNC,Register_unit,FUNCTION,"Begin"); - - delete [] _param_gpr ; - delete [] _param_gpr_status; - delete [] _param_spr ; - delete [] _param_spr_status; + for (uint32_t i=0; i<_nb_ooo_engine; i++) + { + delete _param_gpr [i]; + delete _param_gpr_status [i]; + delete _param_spr [i]; + delete _param_spr_status [i]; + delete __param_gpr [i]; + delete __param_gpr_status [i]; + delete __param_spr [i]; + delete __param_spr_status [i]; + } + delete [] _param_gpr ; + delete [] _param_gpr_status ; + delete [] _param_spr ; + delete [] _param_spr_status ; delete [] __param_gpr ; delete [] __param_gpr_status; @@ -207,4 +227,22 @@ }; +#undef FUNCTION +#define FUNCTION "Register_unit::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Register_unit,FUNCTION,"Begin"); + + for (uint32_t i=0; i<_nb_ooo_engine; i++) + { + COPY(__param_gpr [i]); + COPY(__param_gpr_status [i]); + COPY(__param_spr [i]); + COPY(__param_spr_status [i]); + } + COPY(_param_glue); + + log_printf(FUNC,Register_unit,FUNCTION,"End"); + }; + }; // end namespace register_unit }; // end namespace execute_loop Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit.cpp (revision 88) @@ -37,4 +37,10 @@ log_printf(FUNC,Register_unit,FUNCTION,"Begin"); +#if DEBUG_Register_unit == true + log_printf(INFO,Register_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Register_unit,FUNCTION,"Allocation"); allocation ( @@ -45,18 +51,25 @@ #ifdef STATISTICS - log_printf(INFO,Register_unit,FUNCTION,"Allocation of statistics"); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Register_unit,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); - // Allocation of statistics - statistics_declaration(param_statistics); + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,Register_unit,FUNCTION,"Generate the vhdl"); - - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Register_unit,FUNCTION,"Generate the vhdl"); + + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) log_printf(INFO,Register_unit,FUNCTION,"Method - transition"); @@ -70,5 +83,5 @@ // List dependency information #endif - + } #endif log_printf(FUNC,Register_unit,FUNCTION,"End"); @@ -82,6 +95,9 @@ #ifdef STATISTICS - log_printf(INFO,Register_unit,FUNCTION,"Generate Statistics file"); - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Register_unit,FUNCTION,"Generate Statistics file"); + delete _stat; + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_allocation.cpp (revision 88) @@ -2,5 +2,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/include/Register_unit.h" -namespace morpheo { +namespace morpheo { namespace behavioural { namespace core { @@ -14,6 +14,4 @@ namespace execute_loop { namespace register_unit { - - #undef FUNCTION @@ -40,5 +38,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Interface * interface = _interfaces->set_interface("" @@ -53,5 +51,5 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); - // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_GPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_read]; out_GPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_read]; @@ -75,5 +73,5 @@ out_GPR_READ_ACK [i]= interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_GPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , log2(_param->_nb_ooo_engine)); + in_GPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); in_GPR_READ_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_gpr_address); out_GPR_READ_DATA [i]= interface->set_signal_out ("data" , _param->_size_general_data); @@ -81,5 +79,5 @@ } - // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_GPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_gpr_write]; out_GPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_gpr_write]; @@ -102,10 +100,10 @@ out_GPR_WRITE_ACK [i]= interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_GPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , log2(_param->_nb_ooo_engine)); + in_GPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); in_GPR_WRITE_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_gpr_address); in_GPR_WRITE_DATA [i]= interface->set_signal_in ("data" , _param->_size_general_data); } - // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_SPR_READ_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_read]; out_SPR_READ_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_read]; @@ -129,5 +127,5 @@ out_SPR_READ_ACK [i]= interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_SPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , log2(_param->_nb_ooo_engine)); + in_SPR_READ_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); in_SPR_READ_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_spr_address); out_SPR_READ_DATA [i]= interface->set_signal_out ("data" , _param->_size_special_data); @@ -135,5 +133,5 @@ } - // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_SPR_WRITE_VAL = new SC_IN (Tcontrol_t ) * [_param->_nb_spr_write]; out_SPR_WRITE_ACK = new SC_OUT(Tcontrol_t ) * [_param->_nb_spr_write]; @@ -156,10 +154,10 @@ out_SPR_WRITE_ACK [i]= interface->set_signal_valack_out (ACK); if (_param->_have_port_ooo_engine_id == true) - in_SPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , log2(_param->_nb_ooo_engine)); + in_SPR_WRITE_OOO_ENGINE_ID [i]= interface->set_signal_in ("ooo_engine_id" , _param->_size_ooo_engine_id); in_SPR_WRITE_NUM_REG [i]= interface->set_signal_in ("num_reg" , _param->_size_spr_address); in_SPR_WRITE_DATA [i]= interface->set_signal_in ("data" , _param->_size_special_data); } - // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_INSERT_ROB_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; out_INSERT_ROB_ACK = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; @@ -201,55 +199,56 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - in_RETIRE_ROB_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - out_RETIRE_ROB_ACK = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_OLD_NUM_REG = new SC_IN (Tgeneral_address_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_OLD_NUM_REG = new SC_IN (Tspecial_address_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RD_NEW_NUM_REG = new SC_IN (Tgeneral_address_t) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; - in_RETIRE_ROB_RE_NEW_NUM_REG = new SC_IN (Tspecial_address_t) ** [_param->_nb_ooo_engine]; - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; - - in_RETIRE_ROB_VAL [i] = new SC_IN (Tcontrol_t ) * [x]; - out_RETIRE_ROB_ACK [i] = new SC_OUT(Tcontrol_t ) * [x]; - in_RETIRE_ROB_RD_OLD_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_RETIRE_ROB_RD_OLD_NUM_REG [i] = new SC_IN (Tgeneral_address_t) * [x]; - in_RETIRE_ROB_RE_OLD_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_RETIRE_ROB_RE_OLD_NUM_REG [i] = new SC_IN (Tspecial_address_t) * [x]; - in_RETIRE_ROB_RD_NEW_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_RETIRE_ROB_RD_NEW_NUM_REG [i] = new SC_IN (Tgeneral_address_t) * [x]; - in_RETIRE_ROB_RE_NEW_USE [i] = new SC_IN (Tcontrol_t ) * [x]; - in_RETIRE_ROB_RE_NEW_NUM_REG [i] = new SC_IN (Tspecial_address_t) * [x]; - - for (uint32_t j=0; jset_interface("retire_rob_"+toString(i)+"_"+toString(j) -#ifdef POSITION - ,IN - ,WEST - ,"Interface to update status (retire)" -#endif - ); - - - in_RETIRE_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); - out_RETIRE_ROB_ACK [i][j] = interface->set_signal_valack_out (ACK); - in_RETIRE_ROB_RD_OLD_USE [i][j] = interface->set_signal_in ("rd_old_use" , 1); - in_RETIRE_ROB_RD_OLD_NUM_REG [i][j] = interface->set_signal_in ("rd_old_num_reg", _param->_size_gpr_address); - in_RETIRE_ROB_RE_OLD_USE [i][j] = interface->set_signal_in ("re_old_use" , 1); - in_RETIRE_ROB_RE_OLD_NUM_REG [i][j] = interface->set_signal_in ("re_old_num_reg", _param->_size_spr_address); - in_RETIRE_ROB_RD_NEW_USE [i][j] = interface->set_signal_in ("rd_new_use" , 1); - in_RETIRE_ROB_RD_NEW_NUM_REG [i][j] = interface->set_signal_in ("rd_new_num_reg", _param->_size_gpr_address); - in_RETIRE_ROB_RE_NEW_USE [i][j] = interface->set_signal_in ("re_new_use" , 1); - in_RETIRE_ROB_RE_NEW_NUM_REG [i][j] = interface->set_signal_in ("re_new_num_reg", _param->_size_spr_address); - } - } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// in_RETIRE_ROB_VAL = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// out_RETIRE_ROB_ACK = new SC_OUT(Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_OLD_NUM_REG = new SC_IN (Tgeneral_address_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_OLD_NUM_REG = new SC_IN (Tspecial_address_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RD_NEW_NUM_REG = new SC_IN (Tgeneral_address_t) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_USE = new SC_IN (Tcontrol_t ) ** [_param->_nb_ooo_engine]; +// in_RETIRE_ROB_RE_NEW_NUM_REG = new SC_IN (Tspecial_address_t) ** [_param->_nb_ooo_engine]; + +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; + +// in_RETIRE_ROB_VAL [i] = new SC_IN (Tcontrol_t ) * [x]; +// out_RETIRE_ROB_ACK [i] = new SC_OUT(Tcontrol_t ) * [x]; +// in_RETIRE_ROB_RD_OLD_USE [i] = new SC_IN (Tcontrol_t ) * [x]; +// in_RETIRE_ROB_RD_OLD_NUM_REG [i] = new SC_IN (Tgeneral_address_t) * [x]; +// in_RETIRE_ROB_RE_OLD_USE [i] = new SC_IN (Tcontrol_t ) * [x]; +// in_RETIRE_ROB_RE_OLD_NUM_REG [i] = new SC_IN (Tspecial_address_t) * [x]; +// in_RETIRE_ROB_RD_NEW_USE [i] = new SC_IN (Tcontrol_t ) * [x]; +// in_RETIRE_ROB_RD_NEW_NUM_REG [i] = new SC_IN (Tgeneral_address_t) * [x]; +// in_RETIRE_ROB_RE_NEW_USE [i] = new SC_IN (Tcontrol_t ) * [x]; +// in_RETIRE_ROB_RE_NEW_NUM_REG [i] = new SC_IN (Tspecial_address_t) * [x]; + +// for (uint32_t j=0; jset_interface("retire_rob_"+toString(i)+"_"+toString(j) +// #ifdef POSITION +// ,IN +// ,WEST +// ,"Interface to update status (retire)" +// #endif +// ); + + +// in_RETIRE_ROB_VAL [i][j] = interface->set_signal_valack_in (VAL); +// out_RETIRE_ROB_ACK [i][j] = interface->set_signal_valack_out (ACK); +// in_RETIRE_ROB_RD_OLD_USE [i][j] = interface->set_signal_in ("rd_old_use" , 1); +// in_RETIRE_ROB_RD_OLD_NUM_REG [i][j] = interface->set_signal_in ("rd_old_num_reg", _param->_size_gpr_address); +// in_RETIRE_ROB_RE_OLD_USE [i][j] = interface->set_signal_in ("re_old_use" , 1); +// in_RETIRE_ROB_RE_OLD_NUM_REG [i][j] = interface->set_signal_in ("re_old_num_reg", _param->_size_spr_address); +// in_RETIRE_ROB_RD_NEW_USE [i][j] = interface->set_signal_in ("rd_new_use" , 1); +// in_RETIRE_ROB_RD_NEW_NUM_REG [i][j] = interface->set_signal_in ("rd_new_num_reg", _param->_size_gpr_address); +// in_RETIRE_ROB_RE_NEW_USE [i][j] = interface->set_signal_in ("re_new_use" , 1); +// in_RETIRE_ROB_RE_NEW_NUM_REG [i][j] = interface->set_signal_in ("re_new_num_reg", _param->_size_spr_address); +// } +// } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ std::string name; @@ -263,4 +262,5 @@ { name = _name+"_gpr_"+toString(i); + log_printf(INFO,Register_unit,FUNCTION,_("Create : %s"),name.c_str()); component_gpr [i] = new morpheo::behavioural::generic::registerfile::RegisterFile::RegisterFile @@ -284,4 +284,5 @@ name = _name+"_gpr_status_"+toString(i); + log_printf(INFO,Register_unit,FUNCTION,_("Create : %s"),name.c_str()); component_gpr_status [i] = new morpheo::behavioural::generic::registerfile::RegisterFile::RegisterFile @@ -305,4 +306,5 @@ name = _name+"_spr_"+toString(i); + log_printf(INFO,Register_unit,FUNCTION,_("Create : %s"),name.c_str()); component_spr [i] = new morpheo::behavioural::generic::registerfile::RegisterFile::RegisterFile @@ -325,4 +327,5 @@ name = _name+"_spr_status_"+toString(i); + log_printf(INFO,Register_unit,FUNCTION,_("Create : %s"),name.c_str()); component_spr_status [i] = new morpheo::behavioural::generic::registerfile::RegisterFile::RegisterFile @@ -347,4 +350,5 @@ name = _name+"_glue"; + log_printf(INFO,Register_unit,FUNCTION,_("Create : %s"),name.c_str()); component_glue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::register_unit_glue::Register_unit_Glue::Register_unit_Glue @@ -373,5 +377,5 @@ name_component = _name+"_gpr_"+toString(i); - std::cout << "Instance : " << name_component << std::endl; + log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str()); #ifdef POSITION @@ -430,5 +434,5 @@ name_component = _name+"_gpr_status_"+toString(i); - std::cout << "Instance : " << name_component << std::endl; + log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str()); #ifdef POSITION @@ -516,54 +520,54 @@ } - for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) - { - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_VAL" , - _name+"_glue", - "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL"); - _component->port_map(name_component, - "out_WRITE_"+toString(x)+"_ACK", - _name+"_glue", - "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_DATA" , - _name+"_glue", - "out_CONST_0"); - _component->port_map(_name+"_glue", - "out_CONST_0", - name_component, - "in_WRITE_"+toString(x)+"_DATA" ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x++)+"_ADDRESS", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG"); +// for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) +// { +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_VAL" , +// _name+"_glue", +// "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL"); +// _component->port_map(name_component, +// "out_WRITE_"+toString(x)+"_ACK", +// _name+"_glue", +// "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_DATA" , +// _name+"_glue", +// "out_CONST_0"); +// _component->port_map(_name+"_glue", +// "out_CONST_0", +// name_component, +// "in_WRITE_"+toString(x)+"_DATA" ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x++)+"_ADDRESS", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG"); - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_VAL" , - _name+"_glue", - "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL"); - _component->port_map(name_component, - "out_WRITE_"+toString(x)+"_ACK", - _name+"_glue", - "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_DATA" , - _name+"_glue", - "out_CONST_1" - ); - _component->port_map(_name+"_glue", - "out_CONST_1", - name_component, - "in_WRITE_"+toString(x)+"_DATA" - ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x++)+"_ADDRESS", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG"); - } +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_VAL" , +// _name+"_glue", +// "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL"); +// _component->port_map(name_component, +// "out_WRITE_"+toString(x)+"_ACK", +// _name+"_glue", +// "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_DATA" , +// _name+"_glue", +// "out_CONST_1" +// ); +// _component->port_map(_name+"_glue", +// "out_CONST_1", +// name_component, +// "in_WRITE_"+toString(x)+"_DATA" +// ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x++)+"_ADDRESS", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG"); +// } } @@ -574,5 +578,5 @@ name_component = _name+"_spr_"+toString(i); - std::cout << "Instance : " << name_component << std::endl; + log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str()); #ifdef POSITION @@ -631,6 +635,6 @@ name_component = _name+"_spr_status_"+toString(i); - std::cout << "Instance : " << name_component << std::endl; - + log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str()); + #ifdef POSITION _component->interface_map (name_component,"", @@ -717,55 +721,55 @@ } - for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) - { - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_VAL" , - _name+"_glue", - "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL"); - _component->port_map(name_component, - "out_WRITE_"+toString(x)+"_ACK", - _name+"_glue", - "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_DATA" , - _name+"_glue", - "out_CONST_0"); - _component->port_map(_name+"_glue", - "out_CONST_0", - name_component, - "in_WRITE_"+toString(x)+"_DATA" - ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x++)+"_ADDRESS", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG"); +// for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) +// { +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_VAL" , +// _name+"_glue", +// "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL"); +// _component->port_map(name_component, +// "out_WRITE_"+toString(x)+"_ACK", +// _name+"_glue", +// "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK" ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_DATA" , +// _name+"_glue", +// "out_CONST_0"); +// _component->port_map(_name+"_glue", +// "out_CONST_0", +// name_component, +// "in_WRITE_"+toString(x)+"_DATA" +// ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x++)+"_ADDRESS", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG"); - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_VAL" , - _name+"_glue", - "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL"); - _component->port_map(name_component, - "out_WRITE_"+toString(x)+"_ACK", - _name+"_glue", - "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x)+"_DATA" , - _name+"_glue", - "out_CONST_1" - ); - _component->port_map(_name+"_glue", - "out_CONST_1", - name_component, - "in_WRITE_"+toString(x)+"_DATA" - ); - - _component->port_map(name_component, - "in_WRITE_"+toString(x++)+"_ADDRESS", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG"); - } +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_VAL" , +// _name+"_glue", +// "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL"); +// _component->port_map(name_component, +// "out_WRITE_"+toString(x)+"_ACK", +// _name+"_glue", +// "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK" ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x)+"_DATA" , +// _name+"_glue", +// "out_CONST_1" +// ); +// _component->port_map(_name+"_glue", +// "out_CONST_1", +// name_component, +// "in_WRITE_"+toString(x)+"_DATA" +// ); + +// _component->port_map(name_component, +// "in_WRITE_"+toString(x++)+"_ADDRESS", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG"); +// } } @@ -775,6 +779,6 @@ name_component = _name+"_glue"; - std::cout << "Instance : " << name_component << std::endl; - + log_printf(INFO,Register_unit,FUNCTION,_("Instance : %s"),name_component.c_str()); + #ifdef POSITION _component->interface_map (name_component,"", @@ -1010,77 +1014,80 @@ } - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x =_param->_nb_inst_retire_rob [i]; - uint32_t gpr_j = _param->_nb_gpr_write + _param->_nb_inst_insert_rob [i]; - uint32_t spr_j = _param->_nb_spr_write + _param->_nb_inst_insert_rob [i]; - - for (uint32_t j=0; jport_map(name_component, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL"); - _component->port_map(name_component, - "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK", - _name, - "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK"); - _component->port_map(name_component, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE"); - _component->port_map(name_component, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE"); - _component->port_map(name_component, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE"); - _component->port_map(name_component, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE", - _name, - "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE"); +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x =_param->_nb_inst_retire_rob [i]; +// uint32_t gpr_j = _param->_nb_gpr_write + _param->_nb_inst_insert_rob [i]; +// uint32_t spr_j = _param->_nb_spr_write + _param->_nb_inst_insert_rob [i]; + +// for (uint32_t j=0; jport_map(name_component, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL"); +// _component->port_map(name_component, +// "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK", +// _name, +// "out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE", +// _name, +// "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE"); - _component->port_map(name_component, - "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL", - _name+"_gpr_status_"+toString(i), - "in_WRITE_"+toString(gpr_j)+"_VAL"); - _component->port_map(name_component, - "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK", - _name+"_gpr_status_"+toString(i), - "out_WRITE_"+toString(gpr_j++)+"_ACK"); - _component->port_map(name_component, - "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL", - _name+"_gpr_status_"+toString(i), - "in_WRITE_"+toString(gpr_j)+"_VAL"); - _component->port_map(name_component, - "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK", - _name+"_gpr_status_"+toString(i), - "out_WRITE_"+toString(gpr_j++)+"_ACK"); - _component->port_map(name_component, - "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL", - _name+"_spr_status_"+toString(i), - "in_WRITE_"+toString(spr_j)+"_VAL"); - _component->port_map(name_component, - "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK", - _name+"_spr_status_"+toString(i), - "out_WRITE_"+toString(spr_j++)+"_ACK"); - _component->port_map(name_component, - "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL", - _name+"_spr_status_"+toString(i), - "in_WRITE_"+toString(spr_j)+"_VAL"); - _component->port_map(name_component, - "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK", - _name+"_spr_status_"+toString(i), - "out_WRITE_"+toString(spr_j++)+"_ACK"); - } - } +// _component->port_map(name_component, +// "out_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL", +// _name+"_gpr_status_"+toString(i), +// "in_WRITE_"+toString(gpr_j)+"_VAL"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_GPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK", +// _name+"_gpr_status_"+toString(i), +// "out_WRITE_"+toString(gpr_j++)+"_ACK"); +// _component->port_map(name_component, +// "out_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL", +// _name+"_gpr_status_"+toString(i), +// "in_WRITE_"+toString(gpr_j)+"_VAL"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_GPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK", +// _name+"_gpr_status_"+toString(i), +// "out_WRITE_"+toString(gpr_j++)+"_ACK"); +// _component->port_map(name_component, +// "out_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_VAL", +// _name+"_spr_status_"+toString(i), +// "in_WRITE_"+toString(spr_j)+"_VAL"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_SPR_STATUS_OLD_"+toString(i)+"_"+toString(j)+"_ACK", +// _name+"_spr_status_"+toString(i), +// "out_WRITE_"+toString(spr_j++)+"_ACK"); +// _component->port_map(name_component, +// "out_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_VAL", +// _name+"_spr_status_"+toString(i), +// "in_WRITE_"+toString(spr_j)+"_VAL"); +// _component->port_map(name_component, +// "in_RETIRE_ROB_SPR_STATUS_NEW_"+toString(i)+"_"+toString(j)+"_ACK", +// _name+"_spr_status_"+toString(i), +// "out_WRITE_"+toString(spr_j++)+"_ACK"); +// } +// } }// glue -// _component->test_map (); - -#ifdef POSITION - _component->generate_file(); +#if DEBUG_Register_unit == true + _component->test_map (); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_deallocation.cpp (revision 88) @@ -22,4 +22,6 @@ log_printf(FUNC,Register_unit,FUNCTION,"Begin"); + if (usage_is_set(_usage,USE_SYSTEMC)) + { //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) delete in_CLOCK ; @@ -59,14 +61,15 @@ delete [] in_INSERT_ROB_RE_USE ; delete [] in_INSERT_ROB_RE_NUM_REG ; - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; +// delete [] in_RETIRE_ROB_VAL ; +// delete [] out_RETIRE_ROB_ACK ; +// delete [] in_RETIRE_ROB_RD_OLD_USE ; +// delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; +// delete [] in_RETIRE_ROB_RD_NEW_USE ; +// delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; +// delete [] in_RETIRE_ROB_RE_OLD_USE ; +// delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; +// delete [] in_RETIRE_ROB_RE_NEW_USE ; +// delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/src/Register_unit_end_cycle.cpp (revision 88) @@ -23,5 +23,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -29,5 +30,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Execute_loop_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_min.cfg (revision 88) @@ -0,0 +1,49 @@ +Execute_loop +1 1 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +1 1 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +1 1 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +1 1 +1 # size_read_queue [0] [nb_read_unit] +1 1 +1 # size_reservation_station [0] [nb_read_unit] +1 1 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +2 2 +1 # size_store_queue [0] [nb_load_store_unit] +1 1 +1 # size_load_queue [0] [nb_load_store_unit] +1 1 +1 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +1 1 +1 # size_write_queue [0] [nb_write_unit] +1 1 +1 # size_execute_queue [0] [nb_write_unit] +1 1 +1 # nb_bypass_write [0] [nb_write_unit] +1 1 +1 # nb_gpr_bank +1 1 +1 # nb_gpr_port_read_by_bank +1 1 +1 # nb_gpr_port_write_by_bank +1 1 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +0 0 +1 # is_load_store_unit [0] [nb_execute_unit] +1 1 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2a.cfg (revision 88) @@ -0,0 +1,49 @@ +Execute_loop +1 1 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +1 1 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +1 1 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +4 4 *4 # size_reservation_station [0] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +4 4 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +4 4 +1 # nb_gpr_bank +1 1 +1 # nb_gpr_port_read_by_bank +1 1 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +0 0 +1 # is_load_store_unit [0] [nb_execute_unit] +1 1 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_2b.cfg (revision 88) @@ -0,0 +1,90 @@ +Execute_loop +4 4 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +4 4 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +1 1 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +8 8 *4 # size_read_queue [1] [nb_read_unit] +1 1 *4 # size_read_queue [2] [nb_read_unit] +8 8 *4 # size_read_queue [3] [nb_read_unit] +8 8 *4 # size_reservation_station [0] [nb_read_unit] +1 1 *4 # size_reservation_station [1] [nb_read_unit] +4 4 *4 # size_reservation_station [2] [nb_read_unit] +2 2 *4 # size_reservation_station [3] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_retire [1] [nb_read_unit] +4 4 +1 # nb_inst_retire [2] [nb_read_unit] +2 2 +1 # nb_inst_retire [3] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +2 2 +1 # nb_inst_memory [0] [nb_load_store_unit] +2 2 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_write_queue [1] [nb_write_unit] +1 1 *4 # size_write_queue [2] [nb_write_unit] +8 8 *4 # size_write_queue [3] [nb_write_unit] +0 0 *4 # size_execute_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [1] [nb_write_unit] +2 2 *4 # size_execute_queue [2] [nb_write_unit] +1 1 *4 # size_execute_queue [3] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [1] [nb_write_unit] +1 1 +1 # nb_bypass_write [2] [nb_write_unit] +4 4 +1 # nb_bypass_write [3] [nb_write_unit] +4 4 +1 # nb_gpr_bank +2 2 +1 # nb_gpr_port_read_by_bank +2 2 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [1][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [2][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [3][0] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # is_load_store_unit [0] [nb_execute_unit] +0 0 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_3a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_3a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_3a.cfg (revision 88) @@ -0,0 +1,102 @@ +Execute_loop +4 4 +1 # nb_read_unit +2 2 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +4 4 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +1 1 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +8 8 *4 # size_read_queue [1] [nb_read_unit] +1 1 *4 # size_read_queue [2] [nb_read_unit] +8 8 *4 # size_read_queue [3] [nb_read_unit] +8 8 *4 # size_reservation_station [0] [nb_read_unit] +1 1 *4 # size_reservation_station [1] [nb_read_unit] +4 4 *4 # size_reservation_station [2] [nb_read_unit] +2 2 *4 # size_reservation_station [3] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_retire [1] [nb_read_unit] +4 4 +1 # nb_inst_retire [2] [nb_read_unit] +2 2 +1 # nb_inst_retire [3] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +1 1 +1 # nb_inst_functionnal_unit [1] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +2 2 +1 # nb_inst_memory [0] [nb_load_store_unit] +2 2 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_write_queue [1] [nb_write_unit] +1 1 *4 # size_write_queue [2] [nb_write_unit] +8 8 *4 # size_write_queue [3] [nb_write_unit] +0 0 *4 # size_execute_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [1] [nb_write_unit] +2 2 *4 # size_execute_queue [2] [nb_write_unit] +1 1 *4 # size_execute_queue [3] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [1] [nb_write_unit] +1 1 +1 # nb_bypass_write [2] [nb_write_unit] +4 4 +1 # nb_bypass_write [3] [nb_write_unit] +4 4 +1 # nb_gpr_bank +2 2 +1 # nb_gpr_port_read_by_bank +2 2 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [1][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [2][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [3][0] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [2][0] [nb_execute_unit][nb_thread] +1 1 +1 # is_load_store_unit [0] [nb_execute_unit] +0 0 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # is_load_store_unit [2] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] +1 1 +1 # translate_num_execute_unit [2] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_6a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_6a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_1_execute_6a.cfg (revision 88) @@ -0,0 +1,138 @@ +Execute_loop +4 4 +1 # nb_read_unit +5 5 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +4 4 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +1 1 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +8 8 *4 # size_read_queue [1] [nb_read_unit] +1 1 *4 # size_read_queue [2] [nb_read_unit] +8 8 *4 # size_read_queue [3] [nb_read_unit] +8 8 *4 # size_reservation_station [0] [nb_read_unit] +1 1 *4 # size_reservation_station [1] [nb_read_unit] +4 4 *4 # size_reservation_station [2] [nb_read_unit] +2 2 *4 # size_reservation_station [3] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_retire [1] [nb_read_unit] +4 4 +1 # nb_inst_retire [2] [nb_read_unit] +2 2 +1 # nb_inst_retire [3] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_functionnal_unit] +1 1 +1 # nb_inst_functionnal_unit [1] [nb_functionnal_unit] +1 1 +1 # nb_inst_functionnal_unit [2] [nb_functionnal_unit] +1 1 +1 # nb_inst_functionnal_unit [3] [nb_functionnal_unit] +1 1 +1 # nb_inst_functionnal_unit [4] [nb_functionnal_unit] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +2 2 +1 # nb_inst_memory [0] [nb_load_store_unit] +2 2 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_write_queue [1] [nb_write_unit] +1 1 *4 # size_write_queue [2] [nb_write_unit] +8 8 *4 # size_write_queue [3] [nb_write_unit] +0 0 *4 # size_execute_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [1] [nb_write_unit] +2 2 *4 # size_execute_queue [2] [nb_write_unit] +1 1 *4 # size_execute_queue [3] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [1] [nb_write_unit] +1 1 +1 # nb_bypass_write [2] [nb_write_unit] +4 4 +1 # nb_bypass_write [3] [nb_write_unit] +4 4 +1 # nb_gpr_bank +2 2 +1 # nb_gpr_port_read_by_bank +2 2 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [0][1][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +0 0 +1 # execution_unit_to_write_unit_table_routing [0][1][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [2][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [3][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [3][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [3][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [3][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [4][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [4][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [4][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [4][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [5][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [5][0][1] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [5][0][2] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [5][0][3] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [1][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [2][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [3][0] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [0][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [1][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [2][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [2][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +0 0 +1 # read_unit_to_execution_unit_table_routing [3][0][1] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][2][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][3][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][4][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [3][5][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [2][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [3][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [4][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [5][0] [nb_execute_unit][nb_thread] +1 1 +1 # is_load_store_unit [0] [nb_execute_unit] +0 0 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # is_load_store_unit [2] [nb_execute_unit] +0 0 +1 # is_load_store_unit [3] [nb_execute_unit] +0 0 +1 # is_load_store_unit [4] [nb_execute_unit] +0 0 +1 # is_load_store_unit [5] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] +1 1 +1 # translate_num_execute_unit [2] [nb_execute_unit] +4 4 +1 # translate_num_execute_unit [3] [nb_execute_unit] +3 3 +1 # translate_num_execute_unit [4] [nb_execute_unit] +2 2 +1 # translate_num_execute_unit [5] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2a.cfg (revision 88) @@ -0,0 +1,74 @@ +Execute_loop +1 1 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +1 1 +1 # nb_write_unit +2 2 +1 # nb_context +2 2 +1 # nb_front_end +2 2 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +4 4 *4 # size_reservation_station [0] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +4 4 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +4 4 +1 # nb_gpr_bank +1 1 +1 # nb_gpr_port_read_by_bank +1 1 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +128 128 +1 # nb_general_register [1] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +8 8 +1 # nb_special_register [1] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +2 2 +1 # nb_inst_insert_rob [1] [nb_ooo_engine] +2 2 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [1] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][1] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][2] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][3] [nb_write_unit][nb_thread] +0 0 +1 # execution_unit_to_write_unit_table_thread [0][4] [nb_write_unit][nb_thread] +0 0 +1 # execution_unit_to_write_unit_table_thread [0][5] [nb_write_unit][nb_thread] +0 0 +1 # execution_unit_to_write_unit_table_thread [0][6] [nb_write_unit][nb_thread] +0 0 +1 # execution_unit_to_write_unit_table_thread [0][7] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][7] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][7] [nb_execute_unit][nb_thread] +0 0 +1 # is_load_store_unit [0] [nb_execute_unit] +1 1 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2b.cfg (revision 88) @@ -0,0 +1,82 @@ +Execute_loop +1 1 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +1 1 +1 # nb_write_unit +2 2 +1 # nb_context +1 1 +1 # nb_front_end +4 4 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +4 4 *4 # size_reservation_station [0] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +4 4 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +4 4 +1 # nb_gpr_bank +1 1 +1 # nb_gpr_port_read_by_bank +1 1 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +64 64 +1 # nb_general_register [1] [nb_ooo_engine] +64 64 +1 # nb_general_register [2] [nb_ooo_engine] +64 64 +1 # nb_general_register [3] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [1] [nb_ooo_engine] +16 16 +1 # nb_special_register [2] [nb_ooo_engine] +16 16 +1 # nb_special_register [3] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [1] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [2] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [3] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [1] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [2] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [3] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][1] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][2] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][3] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][4] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][5] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][6] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][7] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][7] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][7] [nb_execute_unit][nb_thread] +0 0 +1 # is_load_store_unit [0] [nb_execute_unit] +1 1 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2c.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2c.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/config_thread_8_execute_2c.cfg (revision 88) @@ -0,0 +1,98 @@ +Execute_loop +1 1 +1 # nb_read_unit +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_load_store_unit +1 1 +1 # nb_write_unit +1 1 +1 # nb_context +1 1 +1 # nb_front_end +8 8 +1 # nb_ooo_engine +32 32 +1 # nb_packet +32 32 +1 # size_general_data +2 2 +1 # size_special_data +4 4 *4 # size_read_queue [0] [nb_read_unit] +4 4 *4 # size_reservation_station [0] [nb_read_unit] +2 2 +1 # nb_inst_retire [0] [nb_read_unit] +1 1 +1 # nb_inst_functionnal_unit [0] [nb_inst_functionnal] +4 4 *2 # size_store_queue [0] [nb_load_store_unit] +4 4 *2 # size_load_queue [0] [nb_load_store_unit] +4 4 *2 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +4 4 *4 # size_write_queue [0] [nb_write_unit] +4 4 *4 # size_execute_queue [0] [nb_write_unit] +2 2 +1 # nb_bypass_write [0] [nb_write_unit] +4 4 +1 # nb_gpr_bank +1 1 +1 # nb_gpr_port_read_by_bank +1 1 +1 # nb_gpr_port_write_by_bank +4 4 +1 # nb_spr_bank +1 1 +1 # nb_spr_port_read_by_bank +1 1 +1 # nb_spr_port_write_by_bank +64 64 +1 # nb_general_register [0] [nb_ooo_engine] +64 64 +1 # nb_general_register [1] [nb_ooo_engine] +64 64 +1 # nb_general_register [2] [nb_ooo_engine] +64 64 +1 # nb_general_register [3] [nb_ooo_engine] +64 64 +1 # nb_general_register [4] [nb_ooo_engine] +64 64 +1 # nb_general_register [5] [nb_ooo_engine] +64 64 +1 # nb_general_register [6] [nb_ooo_engine] +64 64 +1 # nb_general_register [7] [nb_ooo_engine] +16 16 +1 # nb_special_register [0] [nb_ooo_engine] +16 16 +1 # nb_special_register [1] [nb_ooo_engine] +16 16 +1 # nb_special_register [2] [nb_ooo_engine] +16 16 +1 # nb_special_register [3] [nb_ooo_engine] +16 16 +1 # nb_special_register [4] [nb_ooo_engine] +16 16 +1 # nb_special_register [5] [nb_ooo_engine] +16 16 +1 # nb_special_register [6] [nb_ooo_engine] +16 16 +1 # nb_special_register [7] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [1] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [2] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [3] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [4] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [5] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [6] [nb_ooo_engine] +1 1 +1 # nb_inst_insert_rob [7] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [1] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [2] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [3] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [4] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [5] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [6] [nb_ooo_engine] +1 1 +1 # nb_inst_retire_rob [7] [nb_ooo_engine] +1 1 +1 # execution_unit_to_write_unit_priority +1 1 +1 # execution_unit_to_write_unit_table_routing [0][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_routing [1][0][0] [nb_execute_unit][nb_execute_unit_port][nb_write_unit] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][1] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][2] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][3] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][4] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][5] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][6] [nb_write_unit][nb_thread] +1 1 +1 # execution_unit_to_write_unit_table_thread [0][7] [nb_write_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_priority +1 1 +1 # read_unit_to_execution_unit_table_routing [0][0][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_routing [0][1][0] [nb_read_unit][nb_execute_unit][nb_execute_unit_port] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [0][7] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][1] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][2] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][3] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][4] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][5] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][6] [nb_execute_unit][nb_thread] +1 1 +1 # read_unit_to_execution_unit_table_thread [1][7] [nb_execute_unit][nb_thread] +0 0 +1 # is_load_store_unit [0] [nb_execute_unit] +1 1 +1 # is_load_store_unit [1] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [0] [nb_execute_unit] +0 0 +1 # translate_num_execute_unit [1] [nb_execute_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/configuration.cfg (revision 87) +++ (revision ) @@ -1,42 +1,0 @@ -Execute_loop -1 1 +1 # nb_read_unit -1 1 +1 # nb_functionnal_unit -1 1 +1 # nb_load_store_unit -1 1 +1 # nb_write_unit -1 1 +1 # nb_context -1 1 +1 # nb_front_end -1 1 +1 # nb_ooo_engine -32 32 +1 # nb_packet -32 32 +1 # size_general_data -2 2 +1 # size_special_data -1 1 +1 # size_read_queue [0] [read_unit] -1 1 +1 # size_reservation_station [0] [read_unit] -1 1 +1 # nb_inst_retire [0] [read_unit] -2 2 +1 # size_store_queue [0] [load_store_unit] -1 1 +1 # size_load_queue [0] [load_store_unit] -1 1 +1 # size_speculative_access_queue [0] [load_store_unit] -1 1 +1 # nb_port_check [0] [load_store_unit] -2 2 +1 # speculative_load [0] [load_store_unit] -0 0 +1 # nb_bypass_memory [0] [load_store_unit] -1 1 +1 # size_write_queue [0] [write_unit] -1 1 +1 # size_execute_queue [0] [write_unit] -1 1 +1 # nb_bypass_write [0] [write_unit] -1 1 +1 # nb_gpr_bank -1 1 +1 # nb_gpr_port_read_by_bank -1 1 +1 # nb_gpr_port_write_by_bank -1 1 +1 # nb_spr_bank -1 1 +1 # nb_spr_port_read_by_bank -1 1 +1 # nb_spr_port_write_by_bank -64 64 +1 # nb_general_register [0] [nb_ooo_engine] -16 16 +1 # nb_special_register [0] [nb_ooo_engine] -1 1 +1 # nb_inst_insert_rob [0] [nb_ooo_engine] -1 1 +1 # nb_inst_retire_rob [0] [nb_ooo_engine] -1 1 +1 # execution_unit_to_write_unit_priority -1 1 +1 # execution_unit_to_write_unit_table_routing [0][0] [nb_execute_unit][nb_write_unit] -1 1 +1 # execution_unit_to_write_unit_table_routing [1][0] [nb_execute_unit][nb_write_unit] -1 1 +1 # execution_unit_to_write_unit_table_thread [0][0] [nb_write_unit][nb_thread] -1 1 +1 # read_unit_to_execution_unit_priority -1 1 +1 # read_unit_to_execution_unit_table_routing [0][0] [nb_read_unit][nb_execute_unit] -1 1 +1 # read_unit_to_execution_unit_table_routing [0][1] [nb_read_unit][nb_execute_unit] -1 1 +1 # read_unit_to_execution_unit_table_thread [0][0] [nb_execute_unit][nb_thread] -1 1 +1 # read_unit_to_execution_unit_table_thread [1][0] [nb_execute_unit][nb_thread] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/include/test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/include/test.h (revision 88) @@ -16,4 +16,5 @@ #include "Common/include/Time.h" +#include "Behavioural/include/Selftest.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/main.cpp (revision 88) @@ -14,42 +14,48 @@ err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); - err (_(" * nb_read_unit (uint32_t )\n")); - err (_(" * nb_functionnal_unit (uint32_t )\n")); - err (_(" * nb_load_store_unit (uint32_t )\n")); - err (_(" * nb_write_unit (uint32_t )\n")); - err (_(" * nb_context (uint32_t )\n")); - err (_(" * nb_front_end (uint32_t )\n")); - err (_(" * nb_ooo_engine (uint32_t )\n")); - err (_(" * nb_packet (uint32_t )\n")); - err (_(" * size_general_data (uint32_t )\n")); - err (_(" * size_special_data (uint32_t )\n")); - err (_(" * size_read_queue [read_unit] (uint32_t )\n")); - err (_(" * size_reservation_station [read_unit] (uint32_t )\n")); - err (_(" * nb_inst_retire [read_unit] (uint32_t )\n")); - err (_(" * size_store_queue [load_store_unit] (uint32_t )\n")); - err (_(" * size_load_queue [load_store_unit] (uint32_t )\n")); - err (_(" * size_speculative_access_queue [load_store_unit] (uint32_t )\n")); - err (_(" * nb_port_check [load_store_unit] (uint32_t )\n")); - err (_(" * speculative_load [load_store_unit] (Tspeculative_load_t)\n")); - err (_(" * nb_bypass_memory [load_store_unit] (uint32_t )\n")); - err (_(" * size_write_queue [write_unit] (uint32_t )\n")); - err (_(" * size_execute_queue [write_unit] (uint32_t )\n")); - err (_(" * nb_bypass_write [write_unit] (uint32_t )\n")); - err (_(" * nb_gpr_bank (uint32_t )\n")); - err (_(" * nb_gpr_port_read_by_bank (uint32_t )\n")); - err (_(" * nb_gpr_port_write_by_bank (uint32_t )\n")); - err (_(" * nb_spr_bank (uint32_t )\n")); - err (_(" * nb_spr_port_read_by_bank (uint32_t )\n")); - err (_(" * nb_spr_port_write_by_bank (uint32_t )\n")); - err (_(" * nb_general_register [nb_ooo_engine] (uint32_t )\n")); - err (_(" * nb_special_register [nb_ooo_engine] (uint32_t )\n")); - err (_(" * nb_inst_insert_rob [nb_ooo_engine] (uint32_t )\n")); - err (_(" * nb_inst_retire_rob [nb_ooo_engine] (uint32_t )\n")); - err (_(" * execution_unit_to_write_unit_priority (Tpriority_t )\n")); - err (_(" * execution_unit_to_write_unit_table_routing[nb_execute_unit][nb_write_unit] (bool )\n")); - err (_(" * execution_unit_to_write_unit_table_thread [nb_write_unit][nb_thread] (bool )\n")); - err (_(" * read_unit_to_execution_unit_priority (Tpriority_t )\n")); - err (_(" * read_unit_to_execution_unit_table_routing [nb_read_unit][nb_execute_unit] (bool )\n")); - err (_(" * read_unit_to_execution_unit_table_thread [nb_execute_unit][nb_thread] (bool )\n")); + err (_(" * nb_read_unit (uint32_t )\n")); + err (_(" * nb_functionnal_unit (uint32_t )\n")); + err (_(" * nb_load_store_unit (uint32_t )\n")); + err (_(" * nb_write_unit (uint32_t )\n")); + err (_(" * nb_context (uint32_t )\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_ooo_engine (uint32_t )\n")); + err (_(" * nb_packet (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); + err (_(" * size_read_queue [nb_read_unit] (uint32_t )\n")); + err (_(" * size_reservation_station [nb_read_unit] (uint32_t )\n")); + err (_(" * nb_inst_retire [nb_read_unit] (uint32_t )\n")); + err (_(" * nb_inst_functionnal_unit [nb_functionnal_unit] (uint32_t )\n")); + err (_(" * size_store_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_load_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_speculative_access_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_port_check [nb_load_store_unit] (uint32_t )\n")); + err (_(" * speculative_load [nb_load_store_unit] (Tspeculative_load_t)\n")); + err (_(" * nb_bypass_memory [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_cache_port [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_inst_memory [nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_write_queue [nb_write_unit] (uint32_t )\n")); + err (_(" * size_execute_queue [nb_write_unit] (uint32_t )\n")); + err (_(" * nb_bypass_write [nb_write_unit] (uint32_t )\n")); + err (_(" * nb_gpr_bank (uint32_t )\n")); + err (_(" * nb_gpr_port_read_by_bank (uint32_t )\n")); + err (_(" * nb_gpr_port_write_by_bank (uint32_t )\n")); + err (_(" * nb_spr_bank (uint32_t )\n")); + err (_(" * nb_spr_port_read_by_bank (uint32_t )\n")); + err (_(" * nb_spr_port_write_by_bank (uint32_t )\n")); + err (_(" * nb_general_register [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_special_register [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_insert_rob [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_retire_rob [nb_ooo_engine] (uint32_t )\n")); + err (_(" * execution_unit_to_write_unit_priority (Tpriority_t )\n")); + err (_(" * execution_unit_to_write_unit_table_routing[nb_execute_unit][nb_execute_unit_port][nb_write_unit] (bool )\n")); + err (_(" * execution_unit_to_write_unit_table_thread [nb_write_unit][nb_thread] (bool )\n")); + err (_(" * read_unit_to_execution_unit_priority (Tpriority_t )\n")); + err (_(" * read_unit_to_execution_unit_table_routing [nb_read_unit][nb_execute_unit][nb_execute_unit_port] (bool )\n")); + err (_(" * read_unit_to_execution_unit_table_thread [nb_execute_unit][nb_thread] (bool )\n")); + err (_(" * is_load_store_unit [nb_execute_unit] (bool )\n")); + err (_(" * translate_num_execute_unit [nb_execute_unit] (uint32_t )\n")); + exit (1); @@ -62,4 +68,9 @@ #endif { + // Command + for (int32_t i=0; i(argv[x++]); - bool ** execution_unit_to_write_unit_table_routing = new bool * [nb_execute_unit]; + bool *** execution_unit_to_write_unit_table_routing = new bool ** [nb_execute_unit]; for (uint32_t i=0; i(argv[x++]); - bool ** read_unit_to_execution_unit_table_routing = new bool * [nb_read_unit]; + bool *** read_unit_to_execution_unit_table_routing = new bool ** [nb_read_unit]; for (uint32_t i=0; i(argv[x++]); + + uint32_t * translate_num_execute_unit = new uint32_t [nb_execute_unit]; + for (uint32_t i=0; i(argv[x++]); + + execute_timing_t *** timing = new execute_timing_t ** [nb_functionnal_unit]; // alloc and reset timing array - for (uint32_t i=0; i< nb_execute_unit; i++) + for (uint32_t i=0; i< nb_functionnal_unit; i++) { timing [i] = new execute_timing_t * [MAX_TYPE]; @@ -218,14 +292,15 @@ } - for (uint32_t i=0; i< nb_load_store_unit; i++) - for (uint32_t k=0; k< MAX_OPERATION; k++) - timing[i][TYPE_MEMORY][k]._delay = timing[i][TYPE_MEMORY][k]._latence = 1; for (uint32_t i=0; i< nb_functionnal_unit; i++) for (uint32_t j=0; j< MAX_TYPE; j++) - if (j != TYPE_MEMORY) - for (uint32_t k=0; k< MAX_OPERATION; k++) - timing[i+nb_load_store_unit][j][k]._delay = timing[i+nb_load_store_unit][j][k]._latence = 1; - - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t) = &(morpheo::behavioural::custom::default_get_custom_information); + { + if ( (j != TYPE_MEMORY) and + not ((i!=0) and ((j == TYPE_SPECIAL) or + (j == TYPE_CUSTOM)))) + for (uint32_t k=0; k< MAX_OPERATION; k++) + timing[i][j][k]._delay = timing[i][j][k]._latence = 1; + } + + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information); try @@ -247,5 +322,6 @@ size_reservation_station , nb_inst_retire , - + + nb_inst_functionnal_unit , timing , get_custom_information , @@ -256,6 +332,8 @@ nb_port_check , speculative_load , - nb_bypass_memory , + nb_cache_port , + nb_inst_memory , + size_write_queue , size_execute_queue , @@ -279,7 +357,10 @@ read_unit_to_execution_unit_priority , read_unit_to_execution_unit_table_routing , - read_unit_to_execution_unit_table_thread ); - - msg(_("%s"),param->print(1).c_str()); + read_unit_to_execution_unit_table_thread , + + is_load_store_unit , //[nb_execute_unit] + translate_num_execute_unit , //[nb_execute_unit] + true // is_toplevel + ); test (name,param); @@ -287,10 +368,10 @@ catch (morpheo::ErrorMorpheo & error) { - msg (_("<%s> : %s.\n"),name.c_str(), error.what ()); + msg (_("%s\n"),error.what ()); exit (EXIT_FAILURE); } catch (...) { - err (_("<%s> : This test must generate a error.\n"),name.c_str()); + err (_("This test must generate a error.\n")); exit (EXIT_FAILURE); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp (revision 88) @@ -7,5 +7,5 @@ */ -#define NB_ITERATION 1 +#define NB_ITERATION 128 #define CYCLE_MAX (128*NB_ITERATION) @@ -21,6 +21,16 @@ #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Execute_loop * _Execute_loop = new Execute_loop @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -75,33 +85,34 @@ ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"out_EXECUTE_LOOP_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_write_unit); ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,"out_EXECUTE_LOOP_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_write_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_load_store_unit); - ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_load_store_unit); - ALLOC2_SC_SIGNAL( in_INSERT_ROB_VAL ," in_INSERT_ROB_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_INSERT_ROB_ACK ,"out_INSERT_ROB_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_INSERT_ROB_RD_USE ," in_INSERT_ROB_RD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_INSERT_ROB_RD_NUM_REG ," in_INSERT_ROB_RD_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_INSERT_ROB_RE_USE ," in_INSERT_ROB_RE_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_INSERT_ROB_RE_NUM_REG ," in_INSERT_ROB_RE_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_VAL ," in_RETIRE_ROB_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_RETIRE_ROB_ACK ,"out_RETIRE_ROB_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_USE ," in_RETIRE_ROB_RD_OLD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_NUM_REG ," in_RETIRE_ROB_RD_OLD_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_USE ," in_RETIRE_ROB_RD_NEW_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_NUM_REG ," in_RETIRE_ROB_RD_NEW_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_USE ," in_RETIRE_ROB_RE_OLD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_NUM_REG ," in_RETIRE_ROB_RE_OLD_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_USE ," in_RETIRE_ROB_RE_NEW_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_NUM_REG ," in_RETIRE_ROB_RE_NEW_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); + ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_DATA ,"out_EXECUTE_LOOP_OUT_DATA ",Tgeneral_data_t ,_param->_nb_write_unit); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,"out_DCACHE_REQ_CONTEXT_ID ",Tcontext_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ," in_DCACHE_RSP_CONTEXT_ID ",Tcontext_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ROB_VAL ," in_INSERT_ROB_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ROB_ACK ,"out_INSERT_ROB_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ROB_RD_USE ," in_INSERT_ROB_RD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ROB_RD_NUM_REG ," in_INSERT_ROB_RD_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ROB_RE_USE ," in_INSERT_ROB_RE_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ROB_RE_NUM_REG ," in_INSERT_ROB_RE_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_VAL ," in_RETIRE_ROB_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_ROB_ACK ,"out_RETIRE_ROB_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_USE ," in_RETIRE_ROB_RD_OLD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_NUM_REG ," in_RETIRE_ROB_RD_OLD_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_USE ," in_RETIRE_ROB_RD_NEW_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_NUM_REG ," in_RETIRE_ROB_RD_NEW_NUM_REG ",Tgeneral_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_USE ," in_RETIRE_ROB_RE_OLD_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_NUM_REG ," in_RETIRE_ROB_RE_OLD_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_USE ," in_RETIRE_ROB_RE_NEW_USE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_NUM_REG ," in_RETIRE_ROB_RE_NEW_NUM_REG ",Tspecial_address_t,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); /******************************************************** @@ -122,5 +133,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE1_SC_SIGNAL(_Execute_loop, in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ,_param->_nb_read_unit); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) INSTANCE1_SC_SIGNAL(_Execute_loop, in_EXECUTE_LOOP_IN_PACKET_ID ,_param->_nb_read_unit); INSTANCE1_SC_SIGNAL(_Execute_loop, in_EXECUTE_LOOP_IN_OPERATION ,_param->_nb_read_unit); @@ -149,5 +160,5 @@ if (_param->_have_port_ooo_engine_id) INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID ,_param->_nb_write_unit); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_PACKET_ID ,_param->_nb_write_unit); //INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_OPERATION ,_param->_nb_write_unit); @@ -157,35 +168,36 @@ INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,_param->_nb_write_unit); INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_ADDRESS ,_param->_nb_write_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_VAL ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_REQ_ACK ,_param->_nb_load_store_unit); + INSTANCE1_SC_SIGNAL(_Execute_loop,out_EXECUTE_LOOP_OUT_DATA ,_param->_nb_write_unit); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_VAL ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_REQ_ACK ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); if (_param->_have_port_dcache_context_id) - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_PACKET_ID ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_ADDRESS ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_TYPE ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_WDATA ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_VAL ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop,out_DCACHE_RSP_ACK ,_param->_nb_load_store_unit); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_PACKET_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_ADDRESS ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_TYPE ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_REQ_WDATA ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_VAL ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_DCACHE_RSP_ACK ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); if (_param->_have_port_dcache_context_id) - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_PACKET_ID ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_RDATA ,_param->_nb_load_store_unit); - INSTANCE1_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_ERROR ,_param->_nb_load_store_unit); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop,out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop,out_RETIRE_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_PACKET_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_RDATA ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_DCACHE_RSP_ERROR ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop,out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + INSTANCE2_SC_SIGNAL(_Execute_loop, in_INSERT_ROB_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop,out_RETIRE_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RD_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// INSTANCE2_SC_SIGNAL(_Execute_loop, in_RETIRE_ROB_RE_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -233,67 +245,68 @@ delete in_NRESET; - delete [] in_EXECUTE_LOOP_IN_VAL ; - delete [] out_EXECUTE_LOOP_IN_ACK ; - delete [] in_EXECUTE_LOOP_IN_CONTEXT_ID ; - delete [] in_EXECUTE_LOOP_IN_FRONT_END_ID ; - delete [] in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ; - delete [] in_EXECUTE_LOOP_IN_PACKET_ID ; - delete [] in_EXECUTE_LOOP_IN_OPERATION ; - delete [] in_EXECUTE_LOOP_IN_TYPE ; - delete [] in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE; - delete [] in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ; - delete [] in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ; - delete [] in_EXECUTE_LOOP_IN_IMMEDIAT ; - delete [] in_EXECUTE_LOOP_IN_READ_RA ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RA ; - delete [] in_EXECUTE_LOOP_IN_READ_RB ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RB ; - delete [] in_EXECUTE_LOOP_IN_READ_RC ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RC ; - delete [] in_EXECUTE_LOOP_IN_WRITE_RD ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RD ; - delete [] in_EXECUTE_LOOP_IN_WRITE_RE ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RE ; - delete [] out_EXECUTE_LOOP_OUT_VAL ; - delete [] in_EXECUTE_LOOP_OUT_ACK ; - delete [] out_EXECUTE_LOOP_OUT_CONTEXT_ID ; - delete [] out_EXECUTE_LOOP_OUT_FRONT_END_ID ; - delete [] out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID ; - delete [] out_EXECUTE_LOOP_OUT_PACKET_ID ; -//delete [] out_EXECUTE_LOOP_OUT_OPERATION ; -//delete [] out_EXECUTE_LOOP_OUT_TYPE ; - delete [] out_EXECUTE_LOOP_OUT_FLAGS ; - delete [] out_EXECUTE_LOOP_OUT_EXCEPTION ; - delete [] out_EXECUTE_LOOP_OUT_NO_SEQUENCE ; - delete [] out_EXECUTE_LOOP_OUT_ADDRESS ; - delete [] out_DCACHE_REQ_VAL ; - delete [] in_DCACHE_REQ_ACK ; - delete [] out_DCACHE_REQ_CONTEXT_ID ; - delete [] out_DCACHE_REQ_PACKET_ID ; - delete [] out_DCACHE_REQ_ADDRESS ; - delete [] out_DCACHE_REQ_TYPE ; - delete [] out_DCACHE_REQ_WDATA ; - delete [] in_DCACHE_RSP_VAL ; - delete [] out_DCACHE_RSP_ACK ; - delete [] in_DCACHE_RSP_CONTEXT_ID ; - delete [] in_DCACHE_RSP_PACKET_ID ; - delete [] in_DCACHE_RSP_RDATA ; - delete [] in_DCACHE_RSP_ERROR ; - delete [] in_INSERT_ROB_VAL ; - delete [] out_INSERT_ROB_ACK ; - delete [] in_INSERT_ROB_RD_USE ; - delete [] in_INSERT_ROB_RD_NUM_REG ; - delete [] in_INSERT_ROB_RE_USE ; - delete [] in_INSERT_ROB_RE_NUM_REG ; - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_VAL ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_IN_ACK ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_CONTEXT_ID ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_FRONT_END_ID ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_PACKET_ID ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_OPERATION ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_TYPE ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_IMMEDIAT ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_READ_RA ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RA ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_READ_RB ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RB ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_READ_RC ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RC ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_WRITE_RD ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RD ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_WRITE_RE ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RE ,_param->_nb_read_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_VAL ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL( in_EXECUTE_LOOP_OUT_ACK ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_CONTEXT_ID ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_FRONT_END_ID ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_PACKET_ID ,_param->_nb_write_unit); +//DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_OPERATION ,_param->_nb_write_unit); +//DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_TYPE ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_FLAGS ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_EXCEPTION ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,_param->_nb_write_unit); + DELETE1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_DATA ,_param->_nb_write_unit); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_CONTEXT_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_RSP_CONTEXT_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ROB_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ROB_RD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ROB_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ROB_RE_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RD_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RD_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RE_OLD_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_ROB_RE_NEW_NUM_REG ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h (revision 88) @@ -29,4 +29,5 @@ #include "Behavioural/include/Usage.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Execute_loop_Glue.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" @@ -107,21 +108,22 @@ public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_LOOP_OUT_NO_SEQUENCE ;//[nb_write_unit] public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_LOOP_OUT_ADDRESS ;//[nb_write_unit] + public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_LOOP_OUT_DATA ;//[nb_write_unit] // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_load_store_queue] - public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_load_store_queue] - public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_CONTEXT_ID ;//[nb_load_store_queue] - public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_load_store_queue] - public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_load_store_queue] - public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_load_store_queue] - public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_load_store_queue] + public : SC_OUT(Tcontrol_t ) *** out_DCACHE_REQ_VAL ;//[nb_load_store_queue][nb_cache_port] + public : SC_IN (Tcontrol_t ) *** in_DCACHE_REQ_ACK ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tcontext_t ) *** out_DCACHE_REQ_CONTEXT_ID ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tpacket_t ) *** out_DCACHE_REQ_PACKET_ID ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tdcache_address_t ) *** out_DCACHE_REQ_ADDRESS ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tdcache_type_t ) *** out_DCACHE_REQ_TYPE ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tdcache_data_t ) *** out_DCACHE_REQ_WDATA ;//[nb_load_store_queue][nb_cache_port] // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_load_store_queue] - public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_load_store_queue] - public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_CONTEXT_ID ;//[nb_load_store_queue] - public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_load_store_queue] - public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_load_store_queue] - public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_load_store_queue] + public : SC_IN (Tcontrol_t ) *** in_DCACHE_RSP_VAL ;//[nb_load_store_queue][nb_cache_port] + public : SC_OUT(Tcontrol_t ) *** out_DCACHE_RSP_ACK ;//[nb_load_store_queue][nb_cache_port] + public : SC_IN (Tcontext_t ) *** in_DCACHE_RSP_CONTEXT_ID ;//[nb_load_store_queue][nb_cache_port] + public : SC_IN (Tpacket_t ) *** in_DCACHE_RSP_PACKET_ID ;//[nb_load_store_queue][nb_cache_port] + public : SC_IN (Tdcache_data_t ) *** in_DCACHE_RSP_RDATA ;//[nb_load_store_queue][nb_cache_port] + public : SC_IN (Tdcache_error_t ) *** in_DCACHE_RSP_ERROR ;//[nb_load_store_queue][nb_cache_port] // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -133,18 +135,19 @@ public : SC_IN (Tspecial_address_t) *** in_INSERT_ROB_RE_NUM_REG ;//[nb_ooo_engine][nb_inst_insert_rob] - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_OLD_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_NEW_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_OLD_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ;//[nb_ooo_engine][nb_inst_retire_rob] - public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_NEW_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_VAL ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_ROB_ACK ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_OLD_USE ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_OLD_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RD_NEW_USE ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tgeneral_address_t) *** in_RETIRE_ROB_RD_NEW_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_OLD_USE ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_OLD_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_ROB_RE_NEW_USE ;//[nb_ooo_engine][nb_inst_retire_rob] +// public : SC_IN (Tspecial_address_t) *** in_RETIRE_ROB_RE_NEW_NUM_REG ;//[nb_ooo_engine][nb_inst_retire_rob] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue:: Execute_loop_Glue * _component_glue ; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit:: Read_unit ** _component_read_unit ; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Functionnal_unit ** _component_functionnal_unit ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h (revision 88) @@ -12,4 +12,5 @@ #include "Behavioural/include/Parameters.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Types.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue/include/Parameters.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Parameters.h" #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Parameters.h" @@ -36,26 +37,17 @@ public : uint32_t _nb_load_store_unit ; public : uint32_t _nb_write_unit ; - // generic parameters + // generic parameters public : uint32_t _nb_context ; public : uint32_t _nb_front_end ; public : uint32_t _nb_ooo_engine ; public : uint32_t _nb_packet ; - public : uint32_t _size_general_data ; - public : uint32_t _size_special_data ; - // specific parameters - // * read_unit - public : uint32_t * _size_read_queue ; //[nb_read_unit] - public : uint32_t * _size_reservation_station ; //[nb_read_unit] - public : uint32_t * _nb_inst_retire ; //[nb_read_unit] - public : uint32_t * _read_unit_nb_register_write ; //[nb_read_unit] - public : uint32_t * _read_unit_nb_bypass_write ; //[nb_read_unit] - public : uint32_t * _read_unit_nb_bypass_memory ; //[nb_read_unit] - public : bool ** _link_read_unit_with_load_store_unit ; //[nb_read_unit][nb_load_store_unit] - public : bool ** _link_read_unit_with_write_unit ; //[nb_read_unit][nb_write_unit] - public : bool ** _link_read_unit_with_thread ; //[nb_read_unit][nb_thread] - - // * functionnal_unit - public : execute_timing_t *** _timing ; //[nb_execute_unit][nb_type][nb_operation] - public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t); +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + // specific parameters + // * functionnal_unit + public : uint32_t * _nb_inst_functionnal_unit ; //[nb_functionnal_unit] + public : execute_timing_t *** _timing ; //[nb_functionnal_unit][nb_type][nb_operation] + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); + // * load_store_unit public : uint32_t * _size_store_queue ; //[nb_load_store_unit] @@ -65,9 +57,21 @@ public : Tspeculative_load_t * _speculative_load ; //[nb_load_store_unit] public : uint32_t * _nb_bypass_memory ; //[nb_load_store_unit] - // * write_unit + public : uint32_t * _nb_cache_port ; //[nb_load_store_unit] + public : uint32_t * _nb_inst_memory ; //[nb_load_store_unit] + // * read_unit + public : uint32_t * _size_read_queue ; //[nb_read_unit] + public : uint32_t * _size_reservation_station ; //[nb_read_unit] + public : uint32_t * _nb_inst_retire ; //[nb_read_unit] + public : uint32_t * _read_unit_nb_register_write ; //[nb_read_unit] + public : uint32_t * _read_unit_nb_bypass_write ; //[nb_read_unit] + public : uint32_t * _read_unit_nb_bypass_memory ; //[nb_read_unit] + public : bool *** _link_read_unit_with_load_store_unit ; //[nb_read_unit][nb_load_store_unit][nb_inst_memory] + public : bool ** _link_read_unit_with_write_unit ; //[nb_read_unit][nb_write_unit] + public : bool ** _link_read_unit_with_thread ; //[nb_read_unit][nb_thread] + // * write_unit public : uint32_t * _size_write_queue ; //[nb_write_unit] public : uint32_t * _size_execute_queue ; //[nb_write_unit] public : uint32_t * _nb_bypass_write ; //[nb_write_unit] - // * register_unit + // * register_unit public : uint32_t _nb_gpr_read ; public : uint32_t _nb_gpr_write ; @@ -86,9 +90,9 @@ // * network public : Tpriority_t _execution_unit_to_write_unit_priority ; - public : bool ** _execution_unit_to_write_unit_table_routing ; //[nb_execute_unit][nb_write_unit] + public : bool *** _execution_unit_to_write_unit_table_routing ; //[nb_execute_unit][nb_execute_unit_port][nb_write_unit] public : bool ** _execution_unit_to_write_unit_table_thread ; //[nb_write_unit][nb_thread] public : Tpriority_t _read_unit_to_execution_unit_priority ; - public : bool ** _read_unit_to_execution_unit_table_routing ; //[nb_read_unit][nb_execute_unit] + public : bool *** _read_unit_to_execution_unit_table_routing ; //[nb_read_unit][nb_execute_unit][nb_execute_unit_port] public : bool ** _read_unit_to_execution_unit_table_execute_type; //[nb_execute_unit][nb_type] public : bool ** _read_unit_to_execution_unit_table_thread ; //[nb_execute_unit][nb_thread] @@ -98,14 +102,15 @@ public : uint32_t _nb_execute_unit ; - - public : uint32_t _size_context_id ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_ooo_engine_id ; - public : uint32_t _size_packet_id ; - public : bool _have_port_context_id ; - public : bool _have_port_front_end_id ; - public : bool _have_port_ooo_engine_id ; - public : bool _have_port_packet_id ; - public : bool _have_port_load_queue_ptr ; + public : uint32_t * _nb_execute_unit_port ; + +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_ooo_engine_id ; +//public : uint32_t _size_packet_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_ooo_engine_id ; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr ; public : bool _have_port_dcache_context_id ; @@ -115,6 +120,6 @@ public : uint32_t _max_size_load_queue ; - public : uint32_t _size_general_register ; - public : uint32_t _size_special_register ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; public : uint32_t _max_size_dcache_context_id; @@ -125,4 +130,5 @@ public : std::set * _set_read_unit_source_bypass_memory ; //[nb_read_unit] + public : morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue:: Parameters * _param_glue; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit:: Parameters ** _param_read_unit; public : morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Parameters ** _param_functionnal_unit; @@ -135,60 +141,70 @@ //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_read_unit , - uint32_t nb_functionnal_unit , - uint32_t nb_load_store_unit , - uint32_t nb_write_unit , - - uint32_t nb_context , - uint32_t nb_front_end , - uint32_t nb_ooo_engine , - uint32_t nb_packet , - uint32_t size_general_data , - uint32_t size_special_data , - - uint32_t * size_read_queue , - uint32_t * size_reservation_station , - uint32_t * nb_inst_retire , - - execute_timing_t *** timing , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t), - - uint32_t * size_store_queue , - uint32_t * size_load_queue , - uint32_t * size_speculative_access_queue , - uint32_t * nb_port_check , - Tspeculative_load_t * speculative_load , - uint32_t * nb_bypass_memory , - - uint32_t * size_write_queue , - uint32_t * size_execute_queue , - uint32_t * nb_bypass_write , - - uint32_t nb_gpr_bank , - uint32_t nb_gpr_port_read_by_bank , - uint32_t nb_gpr_port_write_by_bank , - uint32_t nb_spr_bank , - uint32_t nb_spr_port_read_by_bank , - uint32_t nb_spr_port_write_by_bank , - uint32_t * nb_general_register , - uint32_t * nb_special_register , - uint32_t * nb_inst_insert_rob , - uint32_t * nb_inst_retire_rob , - - Tpriority_t execution_unit_to_write_unit_priority , - bool ** execution_unit_to_write_unit_table_routing , - bool ** execution_unit_to_write_unit_table_thread , - - Tpriority_t read_unit_to_execution_unit_priority , - bool ** read_unit_to_execution_unit_table_routing , - bool ** read_unit_to_execution_unit_table_thread - ); + uint32_t nb_functionnal_unit , + uint32_t nb_load_store_unit , + uint32_t nb_write_unit , + + uint32_t nb_context , + uint32_t nb_front_end , + uint32_t nb_ooo_engine , + uint32_t nb_packet , + uint32_t size_general_data , + uint32_t size_special_data , + + uint32_t * size_read_queue ,//[nb_read_unit] + uint32_t * size_reservation_station ,//[nb_read_unit] + uint32_t * nb_inst_retire ,//[nb_read_unit] + + uint32_t * nb_inst_functionnal_unit ,//[nb_functionnal_unit] + execute_timing_t *** timing ,//[nb_functionnal_unit][nb_type][nb_operation] + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + + uint32_t * size_store_queue ,//[nb_load_store_unit] + uint32_t * size_load_queue ,//[nb_load_store_unit] + uint32_t * size_speculative_access_queue ,//[nb_load_store_unit] + uint32_t * nb_port_check ,//[nb_load_store_unit] + Tspeculative_load_t * speculative_load ,//[nb_load_store_unit] + uint32_t * nb_bypass_memory ,//[nb_load_store_unit] + uint32_t * nb_cache_port ,//[nb_load_store_unit] + uint32_t * nb_inst_memory ,//[nb_load_store_unit] + + uint32_t * size_write_queue ,//[nb_write_unit] + uint32_t * size_execute_queue ,//[nb_write_unit] + uint32_t * nb_bypass_write ,//[nb_write_unit] + + uint32_t nb_gpr_bank , + uint32_t nb_gpr_port_read_by_bank , + uint32_t nb_gpr_port_write_by_bank , + uint32_t nb_spr_bank , + uint32_t nb_spr_port_read_by_bank , + uint32_t nb_spr_port_write_by_bank , + uint32_t * nb_general_register ,//[nb_ooo_engine] + uint32_t * nb_special_register ,//[nb_ooo_engine] + uint32_t * nb_inst_insert_rob ,//[nb_ooo_engine] + uint32_t * nb_inst_retire_rob ,//[nb_ooo_engine] + + Tpriority_t execution_unit_to_write_unit_priority , + bool *** execution_unit_to_write_unit_table_routing ,//[nb_execute_unit][nb_execute_unit_port][nb_write_unit] + bool ** execution_unit_to_write_unit_table_thread ,//[nb_write_unit][nb_thread] + + Tpriority_t read_unit_to_execution_unit_priority , + bool *** read_unit_to_execution_unit_table_routing ,//[nb_read_unit][nb_execute_unit][nb_execute_unit_port] + bool ** read_unit_to_execution_unit_table_thread ,//[nb_execute_unit][nb_thread] + + bool * is_load_store_unit ,//[nb_execute_unit] + uint32_t * translate_num_execute_unit ,//[nb_execute_unit] + + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; - public : ~Parameters () ; + public : ~Parameters (void) ; + + public : void copy (void); public : Parameters_test msg_error (void); - public : std::string print (uint32_t depth); - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::core::multi_execute_loop::execute_loop::Parameters & x); + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_execute_loop::execute_loop::Parameters & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop.cpp (revision 88) @@ -36,4 +36,10 @@ log_printf(FUNC,Execute_loop,FUNCTION,"Begin"); +#if DEBUG_Execute_loop == true + log_printf(INFO,Execute_loop,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Execute_loop,FUNCTION,"Allocation"); @@ -45,5 +51,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execute_loop,FUNCTION,"Allocation of statistics"); @@ -54,5 +60,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -64,5 +70,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Execute_loop,FUNCTION,"Method - transition"); @@ -88,5 +94,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Execute_loop,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 88) @@ -62,10 +62,10 @@ ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id); + ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type); - ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_max_size_store_queue); + ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); if (_param->_have_port_load_queue_ptr) - ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_max_size_load_queue); + ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data); @@ -90,5 +90,5 @@ ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); - ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id); + ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); // ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type); @@ -97,59 +97,79 @@ ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data); } // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit); - - ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL,VAL); - ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK,ACK); - ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id); - ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id ); - ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); - ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type); - ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); + ALLOC2_INTERFACE("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + + _ALLOC2_VALACK_OUT(out_DCACHE_REQ_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_VALACK_IN ( in_DCACHE_REQ_ACK,ACK, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit); - - ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL,VAL); - ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK,ACK); - ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id); - ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id); - ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); - ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); + ALLOC2_INTERFACE("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + + _ALLOC2_VALACK_IN ( in_DCACHE_RSP_VAL,VAL, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_VALACK_OUT(out_DCACHE_RSP_ACK,ACK, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id, _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); + _ALLOC2_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error , _param->_nb_load_store_unit, _param->_nb_cache_port[it1]); } // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_interface_it1]); - - _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_INSERT_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - - _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_USE ,"rd_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_NUM_REG,"rd_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE ,"re_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]); + ALLOC2_INTERFACE("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + + _ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + _ALLOC2_VALACK_OUT(out_INSERT_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_USE ,"rd_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_NUM_REG,"rd_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE ,"re_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1]); } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - ALLOC2_INTERFACE("retire_rob",IN, EAST, "Rename's stage : retire a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_interface_it1]); - - _ALLOC2_VALACK_IN ( in_RETIRE_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_RETIRE_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_USE ,"rd_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_NUM_REG,"rd_old_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_USE ,"rd_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_NUM_REG,"rd_new_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_USE ,"re_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_NUM_REG,"re_old_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_USE ,"re_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_NUM_REG,"re_new_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]); - } +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// { +// ALLOC2_INTERFACE("retire_rob",IN, EAST, "Rename's stage : retire a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); + +// _ALLOC2_VALACK_IN ( in_RETIRE_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_VALACK_OUT(out_RETIRE_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); + +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_USE ,"rd_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_NUM_REG,"rd_old_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_USE ,"rd_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_NUM_REG,"rd_new_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_USE ,"re_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_NUM_REG,"re_old_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_USE ,"re_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_NUM_REG,"re_new_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1]); +// } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ std::string name; + + { + name = _name+"_glue"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_glue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Execute_loop_Glue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_glue + ,_usage); + + _component->set_component (_component_glue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } _component_read_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Read_unit * [_param->_nb_read_unit]; @@ -157,5 +177,5 @@ { name = _name+"_read_unit_"+toString(i); - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_read_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Read_unit @@ -178,5 +198,5 @@ { name = _name+"_functionnal_unit_"+toString(i); - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_functionnal_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Functionnal_unit @@ -199,5 +219,5 @@ { name = _name+"_load_store_unit_"+toString(i); - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_load_store_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit @@ -220,5 +240,5 @@ { name = _name+"_write_unit_"+toString(i); - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_write_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Write_unit @@ -239,5 +259,5 @@ { name = _name+"_read_unit_to_execution_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_read_unit_to_execution_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::read_unit_to_execution_unit::Read_unit_to_Execution_unit @@ -258,5 +278,5 @@ { name = _name+"_execution_unit_to_write_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_execution_unit_to_write_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::execution_unit_to_write_unit::Execution_unit_to_Write_unit @@ -277,5 +297,5 @@ { name = _name+"_register_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_register_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::Register_unit @@ -296,4 +316,116 @@ // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ std::string src,dest; + + // =================================================================== + // =====[ GLUE ]====================================================== + // =================================================================== + { + src = _name+"_glue"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET"); + } + + for (uint32_t i=0; i<_param->_nb_gpr_write; i++) + { + { + dest = _name+"_write_unit_"+toString(i); + +#ifdef POSITION + _component->interface_map (src ,"gpr_write_write_unit_"+toString(i), + dest,"gpr_write"); +#endif + + // in_GPR_WRITE_WRITE_UNIT_VAL + // out_GPR_WRITE_WRITE_UNIT_ACK + // in_GPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID + // in_GPR_WRITE_WRITE_UNIT_NUM_REG + // in_GPR_WRITE_WRITE_UNIT_DATA + } + + { + dest = _name+"_register_unit"; + +#ifdef POSITION + _component->interface_map (src ,"gpr_write_register_file_"+toString(i), + dest,"gpr_write_"+toString(i)); +#endif + // out_GPR_WRITE_REGISTER_FILE_VAL + // in_GPR_WRITE_REGISTER_FILE_ACK + // out_GPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID + // out_GPR_WRITE_REGISTER_FILE_NUM_REG + // out_GPR_WRITE_REGISTER_FILE_DATA + } + + { + dest = _name+"_read_unit_0"; + +#ifdef POSITION + _component->interface_map (src ,"gpr_write_read_unit_"+toString(i), + dest,"gpr_write"); +#endif + + // out_GPR_WRITE_READ_UNIT_VAL + // out_GPR_WRITE_READ_UNIT_OOO_ENGINE_ID + // out_GPR_WRITE_READ_UNIT_NUM_REG + // out_GPR_WRITE_READ_UNIT_DATA + } + } + + for (uint32_t i=0; i<_param->_nb_spr_write; i++) + { + { + dest = _name+"_write_unit_"+toString(i); + +#ifdef POSITION + _component->interface_map (src ,"spr_write_write_unit_"+toString(i), + dest,"spr_write"); +#endif + + // in_SPR_WRITE_WRITE_UNIT_VAL + // out_SPR_WRITE_WRITE_UNIT_ACK + // in_SPR_WRITE_WRITE_UNIT_OOO_ENGINE_ID + // in_SPR_WRITE_WRITE_UNIT_NUM_REG + // in_SPR_WRITE_WRITE_UNIT_DATA + } + + { + dest = _name+"_register_unit"; + +#ifdef POSITION + _component->interface_map (src ,"spr_write_register_file_"+toString(i), + dest,"spr_write_"+toString(i)); +#endif + // out_SPR_WRITE_REGISTER_FILE_VAL + // in_SPR_WRITE_REGISTER_FILE_ACK + // out_SPR_WRITE_REGISTER_FILE_OOO_ENGINE_ID + // out_SPR_WRITE_REGISTER_FILE_NUM_REG + // out_SPR_WRITE_REGISTER_FILE_DATA + } + + { + dest = _name+"_read_unit_0"; + +#ifdef POSITION + _component->interface_map (src ,"spr_write_read_unit_"+toString(i), + dest,"spr_write"); +#endif + + // out_SPR_WRITE_READ_UNIT_VAL + // out_SPR_WRITE_READ_UNIT_OOO_ENGINE_ID + // out_SPR_WRITE_READ_UNIT_NUM_REG + // out_SPR_WRITE_READ_UNIT_DATA + } + } + + + } // =================================================================== @@ -306,5 +438,5 @@ { src = _name+"_read_unit_"+toString(i); - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -334,5 +466,5 @@ if (_param->_have_port_ooo_engine_id) PORT_MAP(_component ,src , "in_READ_UNIT_IN_OOO_ENGINE_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) PORT_MAP(_component ,src , "in_READ_UNIT_IN_PACKET_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_PACKET_ID" ); PORT_MAP(_component ,src , "in_READ_UNIT_IN_OPERATION" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_OPERATION" ); @@ -361,54 +493,54 @@ #ifdef POSITION - _component->interface_map (src ,"read_unit_"+toString(i), + _component->interface_map (src ,"read_unit_"+toString(j), dest,"read_unit_"+toString(it_read_unit_out)); #endif - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_VAL" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_VAL" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(i )+"_ACK" , - dest,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_ACK" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_VAL" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(j )+"_ACK" , + dest,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_ACK" ); if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_CONTEXT_ID" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_CONTEXT_ID" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_CONTEXT_ID" ); if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_FRONT_END_ID" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_FRONT_END_ID" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_FRONT_END_ID" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_OOO_ENGINE_ID" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_PACKET_ID" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_PACKET_ID" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_OPERATION" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OPERATION" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_TYPE" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_TYPE" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_STORE_QUEUE_PTR_WRITE", - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_STORE_QUEUE_PTR_WRITE"); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_OOO_ENGINE_ID" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_OOO_ENGINE_ID" ); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_PACKET_ID" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_PACKET_ID" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_OPERATION" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_TYPE" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_STORE_QUEUE_PTR_WRITE", + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE"); if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_LOAD_QUEUE_PTR_WRITE" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_HAS_IMMEDIAT" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_IMMEDIAT" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RA" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RA" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RB" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RB" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RC" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RC" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_WRITE_RD" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_NUM_REG_RD" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_WRITE_RE" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_NUM_REG_RE" , - dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RE" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_LOAD_QUEUE_PTR_WRITE" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_HAS_IMMEDIAT" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_IMMEDIAT" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_IMMEDIAT" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RA" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_DATA_RA" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RB" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_DATA_RB" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RC" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_DATA_RC" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RD" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RD" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RE" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RE" , + dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_"+toString(j)+"_NUM_REG_RE" ); - it_read_unit_out ++; } + it_read_unit_out ++; // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -421,18 +553,18 @@ dest,"gpr_read_"+toString(2*i+1)); #endif - PORT_MAP(_component ,src ,"out_GPR_READ_0_VAL" , dest, "in_GPR_READ_"+toString(2*i )+"_VAL" ); - PORT_MAP(_component ,src , "in_GPR_READ_0_ACK" , dest,"out_GPR_READ_"+toString(2*i )+"_ACK" ); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_0_VAL" , dest, "in_GPR_READ_"+toString(2*i )+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_0_ACK" , dest,"out_GPR_READ_"+toString(2*i )+"_ACK" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_GPR_READ_0_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src ,"out_GPR_READ_0_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i )+"_NUM_REG" ); - PORT_MAP(_component ,src , "in_GPR_READ_0_DATA" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA" ); - PORT_MAP(_component ,src , "in_GPR_READ_0_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" ); - PORT_MAP(_component ,src ,"out_GPR_READ_1_VAL" , dest, "in_GPR_READ_"+toString(2*i+1)+"_VAL" ); - PORT_MAP(_component ,src , "in_GPR_READ_1_ACK" , dest,"out_GPR_READ_"+toString(2*i+1)+"_ACK" ); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_0_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_0_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i )+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_0_DATA" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_0_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" ); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_1_VAL" , dest, "in_GPR_READ_"+toString(2*i+1)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_1_ACK" , dest,"out_GPR_READ_"+toString(2*i+1)+"_ACK" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_GPR_READ_1_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src ,"out_GPR_READ_1_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" ); - PORT_MAP(_component ,src , "in_GPR_READ_1_DATA" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA" ); - PORT_MAP(_component ,src , "in_GPR_READ_1_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" ); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_1_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src ,"out_GPR_READ_1_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_1_DATA" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA" ); + COMPONENT_MAP(_component ,src , "in_GPR_READ_1_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" ); } @@ -442,13 +574,13 @@ #ifdef POSITION _component->interface_map (src ,"spr_read_0", - dest,"spr_read_"+toString(2*i )); -#endif - PORT_MAP(_component ,src ,"out_SPR_READ_0_VAL" , dest, "in_SPR_READ_"+toString(2*i )+"_VAL" ); - PORT_MAP(_component ,src , "in_SPR_READ_0_ACK" , dest,"out_SPR_READ_"+toString(2*i )+"_ACK" ); + dest,"spr_read_"+toString(i)); +#endif + COMPONENT_MAP(_component ,src ,"out_SPR_READ_0_VAL" , dest, "in_SPR_READ_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_SPR_READ_0_ACK" , dest,"out_SPR_READ_"+toString(i)+"_ACK" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_SPR_READ_0_OOO_ENGINE_ID", dest, "in_SPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src ,"out_SPR_READ_0_NUM_REG" , dest, "in_SPR_READ_"+toString(2*i )+"_NUM_REG" ); - PORT_MAP(_component ,src , "in_SPR_READ_0_DATA" , dest,"out_SPR_READ_"+toString(2*i )+"_DATA" ); - PORT_MAP(_component ,src , "in_SPR_READ_0_DATA_VAL" , dest,"out_SPR_READ_"+toString(2*i )+"_DATA_VAL" ); + COMPONENT_MAP(_component ,src ,"out_SPR_READ_0_OOO_ENGINE_ID", dest, "in_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src ,"out_SPR_READ_0_NUM_REG" , dest, "in_SPR_READ_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_SPR_READ_0_DATA" , dest,"out_SPR_READ_"+toString(i)+"_DATA" ); + COMPONENT_MAP(_component ,src , "in_SPR_READ_0_DATA_VAL" , dest,"out_SPR_READ_"+toString(i)+"_DATA_VAL" ); } @@ -459,35 +591,21 @@ it++) { - dest = _name+"_write_unit_"+toString(*it); + uint32_t num_port = (*it); + + dest = _name+"_glue"; #ifdef POSITION _component->interface_map (src ,"gpr_write_"+toString(it_gpr_write), - dest,"gpr_write"); + dest,"gpr_write_read_unit_"+toString(num_port)); #endif - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_VAL" , - dest,"out_GPR_WRITE_0_VAL" ); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_VAL" , + dest,"out_GPR_WRITE_READ_UNIT_"+toString(num_port)+"_VAL" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_OOO_ENGINE_ID", - dest,"out_GPR_WRITE_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_NUM_REG" , - dest,"out_GPR_WRITE_0_NUM_REG" ); - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_DATA" , - dest,"out_GPR_WRITE_0_DATA" ); - - // PORT MAP to the "write_unit" component -#ifdef POSITION - _component->interface_map (dest,"gpr_write", - src ,"gpr_write_"+toString(it_gpr_write)); -#endif - - PORT_MAP(_component ,dest,"out_GPR_WRITE_0_VAL" , - src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_VAL" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,dest,"out_GPR_WRITE_0_OOO_ENGINE_ID", - src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,dest,"out_GPR_WRITE_0_NUM_REG" , - src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_NUM_REG" ); - PORT_MAP(_component ,dest,"out_GPR_WRITE_0_DATA" , - src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_DATA" ); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_OOO_ENGINE_ID", + dest,"out_GPR_WRITE_READ_UNIT_"+toString(num_port)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_NUM_REG" , + dest,"out_GPR_WRITE_READ_UNIT_"+toString(num_port)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_DATA" , + dest,"out_GPR_WRITE_READ_UNIT_"+toString(num_port)+"_DATA" ); it_gpr_write ++; @@ -500,35 +618,23 @@ it++) { - dest = _name+"_write_unit_"+toString(*it); + uint32_t num_port = (*it); + + dest = _name+"_glue"; #ifdef POSITION _component->interface_map (src ,"spr_write_"+toString(it_spr_write), - dest,"spr_write"); + dest,"spr_write_read_unit_"+toString(num_port)); #endif - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_VAL" , - dest,"out_SPR_WRITE_0_VAL" ); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_VAL" , + dest,"out_SPR_WRITE_READ_UNIT_"+toString(num_port)+"_VAL" ); + if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_OOO_ENGINE_ID", - dest,"out_SPR_WRITE_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_NUM_REG" , - dest,"out_SPR_WRITE_0_NUM_REG" ); - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_DATA" , - dest,"out_SPR_WRITE_0_DATA" ); - - // PORT MAP to the "write_unit" component -#ifdef POSITION - _component->interface_map (dest,"spr_write", - src ,"spr_write_"+toString(it_spr_write)); -#endif - PORT_MAP(_component ,dest,"out_SPR_WRITE_0_VAL" , - src , "in_SPR_WRITE_"+toString(it_spr_write)+"_VAL" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,dest,"out_SPR_WRITE_0_OOO_ENGINE_ID", - src , "in_SPR_WRITE_"+toString(it_spr_write)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,dest,"out_SPR_WRITE_0_NUM_REG" , - src , "in_SPR_WRITE_"+toString(it_spr_write)+"_NUM_REG" ); - PORT_MAP(_component ,dest,"out_SPR_WRITE_0_DATA" , - src , "in_SPR_WRITE_"+toString(it_spr_write)+"_DATA" ); - + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_OOO_ENGINE_ID", + dest,"out_SPR_WRITE_READ_UNIT_"+toString(num_port)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_NUM_REG" , + dest,"out_SPR_WRITE_READ_UNIT_"+toString(num_port)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_DATA" , + dest,"out_SPR_WRITE_READ_UNIT_"+toString(num_port)+"_DATA" ); + it_spr_write ++; } @@ -550,18 +656,18 @@ if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID", - dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" ); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" ); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" ); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" ); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" ); - PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" , - dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID", + dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" , + dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" ); #ifdef POSITION @@ -570,19 +676,19 @@ #endif - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID", - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" ); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" ); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" ); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" ); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" ); - PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" , - src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID", +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID"); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" ); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" ); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" ); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" ); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" ); +// PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" , +// src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" ); it_bypass_write ++; @@ -606,12 +712,12 @@ if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID", - dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" , - dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" ); - PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" , - dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" ); - PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" , - dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID", + dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" , + dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" , + dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" , + dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" ); // port map to the "load_store_unit" component @@ -621,13 +727,13 @@ #endif - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID", - src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" , - src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" ); - PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" , - src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" ); - PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" , - src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID", +// src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID"); +// PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" , +// src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" ); +// PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" , +// src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" ); +// PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" , +// src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" ); it_bypass_memory ++; @@ -651,5 +757,5 @@ src = _name+"_functionnal_unit_"+toString(x); - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -669,50 +775,50 @@ #ifdef POSITION _component->interface_map (src ,"execute_in", - dest,"execute_unit_in_"+toString(i)); -#endif - - PORT_MAP(_component ,src , "in_EXECUTE_IN_VAL" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src ,"out_EXECUTE_IN_ACK" , - dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" ); + dest,"execute_unit_in_"+toString(i)+"_0"); +#endif + + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_VAL" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_VAL" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_IN_ACK" , + dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_0_ACK" ); if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_EXECUTE_IN_CONTEXT_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_CONTEXT_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_CONTEXT_ID" ); if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_EXECUTE_IN_FRONT_END_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_FRONT_END_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_FRONT_END_ID" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_EXECUTE_IN_OOO_ENGINE_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_EXECUTE_IN_PACKET_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_OPERATION" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_TYPE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE", - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_OOO_ENGINE_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_OOO_ENGINE_ID" ); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_PACKET_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_PACKET_ID" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_OPERATION" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_OPERATION" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_TYPE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_TYPE" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE", + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_STORE_QUEUE_PTR_WRITE"); if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src , "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_HAS_IMMEDIAT" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_IMMEDIAT" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RA" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RB" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RC" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RD" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RD" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_HAS_IMMEDIAT" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_IMMEDIAT" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_IMMEDIAT" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RA" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_DATA_RA" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RB" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_DATA_RB" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RC" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_DATA_RC" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RD" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_WRITE_RD" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RD" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_WRITE_RE" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_0_NUM_REG_RE" ); } @@ -723,45 +829,45 @@ #ifdef POSITION _component->interface_map (src ,"execute_out", - dest,"execute_unit_out_"+toString(i)); -#endif - - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_VAL" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src , "in_EXECUTE_OUT_ACK" , - dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" ); + dest,"execute_unit_out_"+toString(i)+"_0"); +#endif + + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_VAL" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_VAL" ); + COMPONENT_MAP(_component ,src , "in_EXECUTE_OUT_ACK" , + dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_0_ACK" ); if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_CONTEXT_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_CONTEXT_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_CONTEXT_ID" ); if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_FRONT_END_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_FRONT_END_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_FRONT_END_ID" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_OOO_ENGINE_ID", - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_PACKET_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" ); -// PORT_MAP(_component ,src ,"out_EXECUTE_OUT_OPERATION" , -// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_EXCEPTION" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NO_SEQUENCE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_OUT_ADDRESS" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_OOO_ENGINE_ID", + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_PACKET_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_PACKET_ID" ); +// COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_OPERATION" , +// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_OPERATION" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_TYPE" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_WRITE_RD" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_DATA_RD" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_WRITE_RE" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_NUM_REG_RE" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_DATA_RE" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_EXCEPTION" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_EXCEPTION" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_NO_SEQUENCE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_NO_SEQUENCE" ); + COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_ADDRESS" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_ADDRESS" ); } } @@ -773,5 +879,5 @@ src = _name+"_load_store_unit_"+toString(x); - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); // ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -787,139 +893,143 @@ // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - dest = _name+"_read_unit_to_execution_unit"; - -#ifdef POSITION - _component->interface_map (src ,"memory_in", - dest,"execute_unit_in_"+toString(i)); -#endif - - PORT_MAP(_component ,src , "in_MEMORY_IN_VAL" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src ,"out_MEMORY_IN_ACK" , - dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_MEMORY_IN_CONTEXT_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_MEMORY_IN_FRONT_END_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_MEMORY_IN_OOO_ENGINE_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_MEMORY_IN_PACKET_ID" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_OPERATION" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_TYPE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_STORE_QUEUE_PTR_WRITE", - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); - if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src , "in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_HAS_IMMEDIAT" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_IMMEDIAT" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RA" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RB" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RC" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_WRITE_RD" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_NUM_REG_RD" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_WRITE_RE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component ,src , "in_MEMORY_IN_NUM_REG_RE" , - dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ); - } + for (uint32_t j=0; j<_param->_nb_inst_memory [x]; j++) + { + dest = _name+"_read_unit_to_execution_unit"; + +#ifdef POSITION + _component->interface_map (src ,"memory_in_"+toString(j), + dest,"execute_unit_in_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_VAL" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_IN_"+toString(j)+"_ACK" , + dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_CONTEXT_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_FRONT_END_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_OOO_ENGINE_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_OOO_ENGINE_ID" ); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_PACKET_ID" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_OPERATION" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_TYPE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_STORE_QUEUE_PTR_WRITE", + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_HAS_IMMEDIAT" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_IMMEDIAT" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_IMMEDIAT" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_DATA_RA" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_DATA_RA" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_DATA_RB" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_DATA_RB" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_DATA_RC" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_DATA_RC" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_WRITE_RD" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_NUM_REG_RD" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_WRITE_RE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_IN_"+toString(j)+"_NUM_REG_RE" , + dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" ); + } // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { + for (uint32_t j=0; j<_param->_nb_inst_memory [x]; j++) + { dest = _name+"_execution_unit_to_write_unit"; #ifdef POSITION - _component->interface_map (src ,"memory_out", - dest,"execute_unit_out_"+toString(i)); -#endif - - PORT_MAP(_component ,src ,"out_MEMORY_OUT_VAL" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src , "in_MEMORY_OUT_ACK" , - dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" ); + _component->interface_map (src ,"memory_out_"+toString(j) + dest,"execute_unit_out_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_VAL" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_MEMORY_OUT_"+toString(j)+"_ACK" , + dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_ACK" ); if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_MEMORY_OUT_CONTEXT_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_CONTEXT_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_MEMORY_OUT_FRONT_END_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_FRONT_END_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_MEMORY_OUT_OOO_ENGINE_ID", - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_MEMORY_OUT_PACKET_ID" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" ); -// PORT_MAP(_component ,src ,"out_MEMORY_OUT_OPERATION" , -// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_TYPE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_WRITE_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_NUM_REG_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_DATA_RD" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_WRITE_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_NUM_REG_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_DATA_RE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_EXCEPTION" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_NO_SEQUENCE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" ); - PORT_MAP(_component ,src ,"out_MEMORY_OUT_ADDRESS" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_OOO_ENGINE_ID", + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_PACKET_ID" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); +// COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_OPERATION" , +// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_TYPE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_WRITE_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_NUM_REG_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_DATA_RD" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_DATA_RD" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_WRITE_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_NUM_REG_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_DATA_RE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_DATA_RE" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_EXCEPTION" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_NO_SEQUENCE" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" ); + COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_ADDRESS" , + dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); } - + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_cache_port [x]; j++) { dest = _name; #ifdef POSITION - _component->interface_map (src ,"dcache_req", - dest,"dcache_req_"+toString(i)); -#endif - PORT_MAP(_component ,src ,"out_DCACHE_REQ_VAL" ,dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src , "in_DCACHE_REQ_ACK" ,dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" ); + _component->interface_map (src ,"dcache_req_"+toString(j), + dest,"dcache_req_"+toString(x)+"_"+toString(j)); +#endif + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_VAL" ,dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component ,src , "in_DCACHE_REQ_"+toString(j)+"_ACK" ,dest, "in_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_ACK" ); if (_param->_have_port_dcache_context_id) - PORT_MAP(_component ,src ,"out_DCACHE_REQ_CONTEXT_ID",dest,"out_DCACHE_REQ_"+toString(i)+"_CONTEXT_ID"); - PORT_MAP(_component ,src ,"out_DCACHE_REQ_PACKET_ID" ,dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID" ); - PORT_MAP(_component ,src ,"out_DCACHE_REQ_ADDRESS" ,dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ); - PORT_MAP(_component ,src ,"out_DCACHE_REQ_TYPE" ,dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src ,"out_DCACHE_REQ_WDATA" ,dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ); + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_CONTEXT_ID",dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_CONTEXT_ID"); + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_PACKET_ID" ,dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_PACKET_ID" ); + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_ADDRESS" ,dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_ADDRESS" ); + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_TYPE" ,dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_TYPE" ); + PORT_MAP(_component ,src ,"out_DCACHE_REQ_"+toString(j)+"_WDATA" ,dest,"out_DCACHE_REQ_"+toString(x)+"_"+toString(j)+"_WDATA" ); } // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_cache_port [x]; j++) { dest = _name; #ifdef POSITION - _component->interface_map (src ,"dcache_rsp", - dest,"dcache_rsp_"+toString(i)); -#endif - PORT_MAP(_component ,src , "in_DCACHE_RSP_VAL" ,dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src ,"out_DCACHE_RSP_ACK" ,dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" ); + _component->interface_map (src ,"dcache_rsp_"+toString(j), + dest,"dcache_rsp_"+toString(x)+"_"+toString(j)); +#endif + PORT_MAP(_component ,src , "in_DCACHE_RSP_"+toString(j)+"_VAL" ,dest, "in_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component ,src ,"out_DCACHE_RSP_"+toString(j)+"_ACK" ,dest,"out_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_ACK" ); if (_param->_have_port_dcache_context_id) - PORT_MAP(_component ,src , "in_DCACHE_RSP_CONTEXT_ID",dest, "in_DCACHE_RSP_"+toString(i)+"_CONTEXT_ID"); - PORT_MAP(_component ,src , "in_DCACHE_RSP_PACKET_ID" ,dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID" ); - PORT_MAP(_component ,src , "in_DCACHE_RSP_RDATA" ,dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" ); - PORT_MAP(_component ,src , "in_DCACHE_RSP_ERROR" ,dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" ); + PORT_MAP(_component ,src , "in_DCACHE_RSP_"+toString(j)+"_CONTEXT_ID",dest, "in_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_CONTEXT_ID"); + PORT_MAP(_component ,src , "in_DCACHE_RSP_"+toString(j)+"_PACKET_ID" ,dest, "in_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_PACKET_ID" ); + PORT_MAP(_component ,src , "in_DCACHE_RSP_"+toString(j)+"_RDATA" ,dest, "in_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_RDATA" ); + PORT_MAP(_component ,src , "in_DCACHE_RSP_"+toString(j)+"_ERROR" ,dest, "in_DCACHE_RSP_"+toString(x)+"_"+toString(j)+"_ERROR" ); } @@ -937,5 +1047,5 @@ { src = _name+"_write_unit_"+toString(i); - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -957,42 +1067,42 @@ #endif - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_VAL" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_ACK" , - dest, "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_VAL" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src ,"out_WRITE_UNIT_IN_ACK" , + dest, "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" ); if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_CONTEXT_ID" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_CONTEXT_ID" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ); if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_FRONT_END_ID" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_FRONT_END_ID" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ); if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_OOO_ENGINE_ID", - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_PACKET_ID" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" ); -// PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_OPERATION" , -// dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RD" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RD" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RD" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_EXCEPTION" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NO_SEQUENCE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_ADDRESS" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_OOO_ENGINE_ID", + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr ) + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_PACKET_ID" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" ); +// COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_OPERATION" , +// dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RD" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RD" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RD" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RE" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RE" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RE" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_EXCEPTION" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_NO_SEQUENCE" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" ); + COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_ADDRESS" , + dest,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" ); } @@ -1018,5 +1128,5 @@ PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) + if (_param->_have_port_rob_ptr ) PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_PACKET_ID" , dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_PACKET_ID" ); @@ -1033,26 +1143,27 @@ PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_ADDRESS" , dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_DATA" , + dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_DATA" ); } + // -----[ Interface "gpr_write" ]------------------------------------- { - // Port map with "read_unit" is ok! - - dest = _name+"_register_unit"; + dest = _name+"_glue"; #ifdef POSITION _component->interface_map (src ,"gpr_write", - dest,"gpr_write_"+toString(i)); -#endif - - PORT_MAP(_component ,src ,"out_GPR_WRITE_0_VAL" , - dest, "in_GPR_WRITE_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src , "in_GPR_WRITE_0_ACK" , - dest,"out_GPR_WRITE_"+toString(i)+"_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_GPR_WRITE_0_OOO_ENGINE_ID", - dest, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src ,"out_GPR_WRITE_0_NUM_REG" , - dest, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ); - PORT_MAP(_component ,src ,"out_GPR_WRITE_0_DATA" , - dest, "in_GPR_WRITE_"+toString(i)+"_DATA" ); + dest,"gpr_write_write_unit_"+toString(i)); +#endif + + COMPONENT_MAP(_component ,src ,"out_GPR_WRITE_0_VAL" , + dest, "in_GPR_WRITE_WRITE_UNIT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_0_ACK" , + dest,"out_GPR_WRITE_WRITE_UNIT_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component ,src ,"out_GPR_WRITE_0_OOO_ENGINE_ID", + dest, "in_GPR_WRITE_WRITE_UNIT_"+toString(i)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src ,"out_GPR_WRITE_0_NUM_REG" , + dest, "in_GPR_WRITE_WRITE_UNIT_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src ,"out_GPR_WRITE_0_DATA" , + dest, "in_GPR_WRITE_WRITE_UNIT_"+toString(i)+"_DATA" ); } @@ -1061,21 +1172,21 @@ // Port map with "read_unit" is ok! - dest = _name+"_register_unit"; + dest = _name+"_glue"; #ifdef POSITION _component->interface_map (src ,"spr_write", - dest,"spr_write_"+toString(i)); -#endif - - PORT_MAP(_component ,src ,"out_SPR_WRITE_0_VAL" , - dest, "in_SPR_WRITE_"+toString(i)+"_VAL" ); - PORT_MAP(_component ,src , "in_SPR_WRITE_0_ACK" , - dest,"out_SPR_WRITE_"+toString(i)+"_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_SPR_WRITE_0_OOO_ENGINE_ID", - dest, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID"); - PORT_MAP(_component ,src ,"out_SPR_WRITE_0_NUM_REG" , - dest, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ); - PORT_MAP(_component ,src ,"out_SPR_WRITE_0_DATA" , - dest, "in_SPR_WRITE_"+toString(i)+"_DATA" ); + dest,"spr_write_write_unit_"+toString(i)); +#endif + + COMPONENT_MAP(_component ,src ,"out_SPR_WRITE_0_VAL" , + dest, "in_SPR_WRITE_WRITE_UNIT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_0_ACK" , + dest,"out_SPR_WRITE_WRITE_UNIT_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component ,src ,"out_SPR_WRITE_0_OOO_ENGINE_ID", + dest, "in_SPR_WRITE_WRITE_UNIT_"+toString(i)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src ,"out_SPR_WRITE_0_NUM_REG" , + dest, "in_SPR_WRITE_WRITE_UNIT_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src ,"out_SPR_WRITE_0_DATA" , + dest, "in_SPR_WRITE_WRITE_UNIT_"+toString(i)+"_DATA" ); } @@ -1091,5 +1202,5 @@ { src = _name+"_register_unit"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -1114,19 +1225,19 @@ #endif - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_VAL" ,dest,"out_GPR_READ_0_VAL" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_ACK" ,dest, "in_GPR_READ_0_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID",dest,"out_GPR_READ_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_NUM_REG" ,dest,"out_GPR_READ_0_NUM_REG" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA" ,dest, "in_GPR_READ_0_DATA" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" ,dest, "in_GPR_READ_0_DATA_VAL" ); - - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_VAL" ,dest,"out_GPR_READ_1_VAL" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_ACK" ,dest, "in_GPR_READ_1_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID",dest,"out_GPR_READ_1_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" ,dest,"out_GPR_READ_1_NUM_REG" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA" ,dest, "in_GPR_READ_1_DATA" ); - PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" ,dest, "in_GPR_READ_1_DATA_VAL" ); +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_VAL" ,dest,"out_GPR_READ_0_VAL" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_ACK" ,dest, "in_GPR_READ_0_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID",dest,"out_GPR_READ_0_OOO_ENGINE_ID"); +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_NUM_REG" ,dest,"out_GPR_READ_0_NUM_REG" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA" ,dest, "in_GPR_READ_0_DATA" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" ,dest, "in_GPR_READ_0_DATA_VAL" ); + +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_VAL" ,dest,"out_GPR_READ_1_VAL" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_ACK" ,dest, "in_GPR_READ_1_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID",dest,"out_GPR_READ_1_OOO_ENGINE_ID"); +// PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" ,dest,"out_GPR_READ_1_NUM_REG" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA" ,dest, "in_GPR_READ_1_DATA" ); +// PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" ,dest, "in_GPR_READ_1_DATA_VAL" ); } @@ -1134,16 +1245,16 @@ for (uint32_t i=0; i<_param->_nb_write_unit; i++) { - dest = _name+"_write_unit_"+toString(i); -#ifdef POSITION - _component->interface_map (src ,"gpr_write_"+toString(i) - dest,"gpr_write_0"); -#endif - - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_GPR_WRITE_0_VAL" ); - PORT_MAP(_component ,src ,"out_GPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_GPR_WRITE_0_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_GPR_WRITE_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_GPR_WRITE_0_NUM_REG" ); - PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_GPR_WRITE_0_DATA" ); + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"gpr_write_"+toString(i), + dest,"gpr_write_register_file_"+toString(i)); +#endif + + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_GPR_WRITE_REGISTER_FILE_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src ,"out_GPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_GPR_WRITE_REGISTER_FILE_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_GPR_WRITE_REGISTER_FILE_"+toString(i)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_GPR_WRITE_REGISTER_FILE_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_GPR_WRITE_REGISTER_FILE_"+toString(i)+"_DATA" ); } @@ -1157,11 +1268,11 @@ #endif - PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_VAL" ,dest,"out_SPR_READ_0_VAL" ); - PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_ACK" ,dest, "in_SPR_READ_0_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_READ_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_READ_0_NUM_REG" ); - PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA" ,dest, "in_SPR_READ_0_DATA" ); - PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA_VAL" ,dest, "in_SPR_READ_0_DATA_VAL" ); +// PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_VAL" ,dest,"out_SPR_READ_0_VAL" ); +// PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_ACK" ,dest, "in_SPR_READ_0_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_READ_0_OOO_ENGINE_ID"); +// PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_READ_0_NUM_REG" ); +// PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA" ,dest, "in_SPR_READ_0_DATA" ); +// PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA_VAL" ,dest, "in_SPR_READ_0_DATA_VAL" ); } @@ -1169,16 +1280,16 @@ for (uint32_t i=0; i<_param->_nb_write_unit; i++) { - dest = _name+"_write_unit_"+toString(i); -#ifdef POSITION - _component->interface_map (src ,"spr_write_"+toString(i) - dest,"spr_write_0"); -#endif - - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_SPR_WRITE_0_VAL" ); - PORT_MAP(_component ,src ,"out_SPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_SPR_WRITE_0_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_WRITE_0_OOO_ENGINE_ID"); - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_WRITE_0_NUM_REG" ); - PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_SPR_WRITE_0_DATA" ); + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"spr_write_"+toString(i), + dest,"spr_write_register_file_"+toString(i)); +#endif + + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_SPR_WRITE_REGISTER_FILE_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component ,src ,"out_SPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_SPR_WRITE_REGISTER_FILE_"+toString(i)+"_ACK" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_WRITE_REGISTER_FILE_"+toString(i)+"_OOO_ENGINE_ID"); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_WRITE_REGISTER_FILE_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_SPR_WRITE_REGISTER_FILE_"+toString(i)+"_DATA" ); } @@ -1211,39 +1322,39 @@ } - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - uint32_t x=_param->_nb_inst_retire_rob [i]; +// // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) +// { +// uint32_t x=_param->_nb_inst_retire_rob [i]; - for (uint32_t j=0; jinterface_map (src ,"retire_rob_"+toString(i)+"_"+toString(j), - dest,"retire_rob_"+toString(i)+"_"+toString(j)); -#endif - - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" , - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" ); - PORT_MAP(_component ,src ,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" , - dest,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" ); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" , - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" ); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG", - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG"); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" , - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" ); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG", - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG"); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" , - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" ); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG", - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG"); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" , - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" ); - PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG", - dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG"); - } - } +// for (uint32_t j=0; jinterface_map (src ,"retire_rob_"+toString(i)+"_"+toString(j), +// dest,"retire_rob_"+toString(i)+"_"+toString(j)); +// #endif + +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" , +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" ); +// PORT_MAP(_component ,src ,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" , +// dest,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" ); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" , +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" ); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG", +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG"); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" , +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" ); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG", +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG"); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" , +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" ); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG", +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG"); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" , +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" ); +// PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG", +// dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG"); +// } +// } } @@ -1253,5 +1364,5 @@ { src = _name+"_read_unit_to_execution_unit"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -1277,47 +1388,47 @@ #endif - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_VAL" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_VAL" ); - PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_ACK" , - dest, "in_READ_UNIT_OUT_"+toString(j )+"_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_CONTEXT_ID" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_FRONT_END_ID" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OOO_ENGINE_ID" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_PACKET_ID" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_PACKET_ID" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OPERATION" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_OPERATION" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_TYPE" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_TYPE" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_STORE_QUEUE_PTR_WRITE", - dest,"out_READ_UNIT_OUT_"+toString(j )+"_STORE_QUEUE_PTR_WRITE"); - if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_LOAD_QUEUE_PTR_WRITE" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_HAS_IMMEDIAT" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_IMMEDIAT" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_IMMEDIAT" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RA" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RA" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RB" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RB" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RC" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RC" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RD" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RD" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RD" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RE" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RE" ); - PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RE" , - dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RE" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_VAL" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_VAL" ); +// PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_ACK" , +// dest, "in_READ_UNIT_OUT_"+toString(j )+"_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_CONTEXT_ID" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_FRONT_END_ID" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OOO_ENGINE_ID" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_OOO_ENGINE_ID" ); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_PACKET_ID" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_PACKET_ID" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OPERATION" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_OPERATION" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_TYPE" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_TYPE" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_STORE_QUEUE_PTR_WRITE", +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_STORE_QUEUE_PTR_WRITE"); +// if (_param->_have_port_load_queue_ptr) +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_LOAD_QUEUE_PTR_WRITE" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_LOAD_QUEUE_PTR_WRITE" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_HAS_IMMEDIAT" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_HAS_IMMEDIAT" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_IMMEDIAT" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_IMMEDIAT" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RA" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RA" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RB" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RB" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RC" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RC" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RD" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RD" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RD" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RD" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RE" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RE" ); +// PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RE" , +// dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RE" ); it_read_unit_out ++; @@ -1338,47 +1449,47 @@ #endif - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" , - dest, "in_EXECUTE_IN_VAL" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" , - dest,"out_EXECUTE_IN_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , - dest, "in_EXECUTE_IN_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , - dest, "in_EXECUTE_IN_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" , - dest, "in_EXECUTE_IN_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" , - dest, "in_EXECUTE_IN_PACKET_ID" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" , - dest, "in_EXECUTE_IN_OPERATION" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" , - dest, "in_EXECUTE_IN_TYPE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", - dest, "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE"); - if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , - dest, "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" , - dest, "in_EXECUTE_IN_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" , - dest, "in_EXECUTE_IN_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" , - dest, "in_EXECUTE_IN_DATA_RA" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" , - dest, "in_EXECUTE_IN_DATA_RB" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" , - dest, "in_EXECUTE_IN_DATA_RC" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" , - dest, "in_EXECUTE_IN_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , - dest, "in_EXECUTE_IN_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" , - dest, "in_EXECUTE_IN_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , - dest, "in_EXECUTE_IN_NUM_REG_RE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" , +// dest, "in_EXECUTE_IN_VAL" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" , +// dest,"out_EXECUTE_IN_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , +// dest, "in_EXECUTE_IN_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , +// dest, "in_EXECUTE_IN_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" , +// dest, "in_EXECUTE_IN_OOO_ENGINE_ID" ); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" , +// dest, "in_EXECUTE_IN_PACKET_ID" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" , +// dest, "in_EXECUTE_IN_OPERATION" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" , +// dest, "in_EXECUTE_IN_TYPE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", +// dest, "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE"); +// if (_param->_have_port_load_queue_ptr) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , +// dest, "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" , +// dest, "in_EXECUTE_IN_HAS_IMMEDIAT" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" , +// dest, "in_EXECUTE_IN_IMMEDIAT" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" , +// dest, "in_EXECUTE_IN_DATA_RA" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" , +// dest, "in_EXECUTE_IN_DATA_RB" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" , +// dest, "in_EXECUTE_IN_DATA_RC" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" , +// dest, "in_EXECUTE_IN_WRITE_RD" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , +// dest, "in_EXECUTE_IN_NUM_REG_RD" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" , +// dest, "in_EXECUTE_IN_WRITE_RE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , +// dest, "in_EXECUTE_IN_NUM_REG_RE" ); } else @@ -1391,47 +1502,47 @@ #endif - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" , - dest, "in_MEMORY_IN_VAL" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" , - dest,"out_MEMORY_IN_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , - dest, "in_MEMORY_IN_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , - dest, "in_MEMORY_IN_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" , - dest, "in_MEMORY_IN_OOO_ENGINE_ID" ); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" , - dest, "in_MEMORY_IN_PACKET_ID" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" , - dest, "in_MEMORY_IN_OPERATION" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" , - dest, "in_MEMORY_IN_TYPE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", - dest, "in_MEMORY_IN_STORE_QUEUE_PTR_WRITE"); - if (_param->_have_port_load_queue_ptr) - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , - dest, "in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" , - dest, "in_MEMORY_IN_HAS_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" , - dest, "in_MEMORY_IN_IMMEDIAT" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" , - dest, "in_MEMORY_IN_DATA_RA" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" , - dest, "in_MEMORY_IN_DATA_RB" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" , - dest, "in_MEMORY_IN_DATA_RC" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" , - dest, "in_MEMORY_IN_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , - dest, "in_MEMORY_IN_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" , - dest, "in_MEMORY_IN_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , - dest, "in_MEMORY_IN_NUM_REG_RE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" , +// dest, "in_MEMORY_IN_VAL" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" , +// dest,"out_MEMORY_IN_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , +// dest, "in_MEMORY_IN_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , +// dest, "in_MEMORY_IN_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" , +// dest, "in_MEMORY_IN_OOO_ENGINE_ID" ); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" , +// dest, "in_MEMORY_IN_PACKET_ID" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" , +// dest, "in_MEMORY_IN_OPERATION" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" , +// dest, "in_MEMORY_IN_TYPE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", +// dest, "in_MEMORY_IN_STORE_QUEUE_PTR_WRITE"); +// if (_param->_have_port_load_queue_ptr) +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , +// dest, "in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" , +// dest, "in_MEMORY_IN_HAS_IMMEDIAT" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" , +// dest, "in_MEMORY_IN_IMMEDIAT" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" , +// dest, "in_MEMORY_IN_DATA_RA" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" , +// dest, "in_MEMORY_IN_DATA_RB" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" , +// dest, "in_MEMORY_IN_DATA_RC" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" , +// dest, "in_MEMORY_IN_WRITE_RD" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , +// dest, "in_MEMORY_IN_NUM_REG_RD" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" , +// dest, "in_MEMORY_IN_WRITE_RE" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , +// dest, "in_MEMORY_IN_NUM_REG_RE" ); } } @@ -1443,5 +1554,5 @@ { src = _name+"_execution_unit_to_write_unit"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -1468,42 +1579,42 @@ dest,"execute_out"); #endif - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" , - dest,"out_EXECUTE_OUT_VAL" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" , - dest, "in_EXECUTE_OUT_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" , - dest,"out_EXECUTE_OUT_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" , - dest,"out_EXECUTE_OUT_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID", - dest,"out_EXECUTE_OUT_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" , - dest,"out_EXECUTE_OUT_PACKET_ID" ); -// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , -// dest,"out_EXECUTE_OUT_OPERATION" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , - dest,"out_EXECUTE_OUT_TYPE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , - dest,"out_EXECUTE_OUT_WRITE_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" , - dest,"out_EXECUTE_OUT_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" , - dest,"out_EXECUTE_OUT_DATA_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" , - dest,"out_EXECUTE_OUT_WRITE_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" , - dest,"out_EXECUTE_OUT_NUM_REG_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" , - dest,"out_EXECUTE_OUT_DATA_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" , - dest,"out_EXECUTE_OUT_EXCEPTION" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" , - dest,"out_EXECUTE_OUT_NO_SEQUENCE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" , - dest,"out_EXECUTE_OUT_ADDRESS" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" , +// dest,"out_EXECUTE_OUT_VAL" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" , +// dest, "in_EXECUTE_OUT_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" , +// dest,"out_EXECUTE_OUT_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" , +// dest,"out_EXECUTE_OUT_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID", +// dest,"out_EXECUTE_OUT_OOO_ENGINE_ID"); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" , +// dest,"out_EXECUTE_OUT_PACKET_ID" ); +// // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , +// // dest,"out_EXECUTE_OUT_OPERATION" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , +// dest,"out_EXECUTE_OUT_TYPE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , +// dest,"out_EXECUTE_OUT_WRITE_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" , +// dest,"out_EXECUTE_OUT_NUM_REG_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" , +// dest,"out_EXECUTE_OUT_DATA_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" , +// dest,"out_EXECUTE_OUT_WRITE_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" , +// dest,"out_EXECUTE_OUT_NUM_REG_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" , +// dest,"out_EXECUTE_OUT_DATA_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" , +// dest,"out_EXECUTE_OUT_EXCEPTION" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" , +// dest,"out_EXECUTE_OUT_NO_SEQUENCE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" , +// dest,"out_EXECUTE_OUT_ADDRESS" ); } else @@ -1515,42 +1626,42 @@ dest,"memory_out"); #endif - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" , - dest,"out_MEMORY_OUT_VAL" ); - PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" , - dest, "in_MEMORY_OUT_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" , - dest,"out_MEMORY_OUT_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" , - dest,"out_MEMORY_OUT_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID", - dest,"out_MEMORY_OUT_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" , - dest,"out_MEMORY_OUT_PACKET_ID" ); -// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , -// dest,"out_MEMORY_OUT_OPERATION" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , - dest,"out_MEMORY_OUT_TYPE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , - dest,"out_MEMORY_OUT_WRITE_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" , - dest,"out_MEMORY_OUT_NUM_REG_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" , - dest,"out_MEMORY_OUT_DATA_RD" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" , - dest,"out_MEMORY_OUT_WRITE_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" , - dest,"out_MEMORY_OUT_NUM_REG_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" , - dest,"out_MEMORY_OUT_DATA_RE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" , - dest,"out_MEMORY_OUT_EXCEPTION" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" , - dest,"out_MEMORY_OUT_NO_SEQUENCE" ); - PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" , - dest,"out_MEMORY_OUT_ADDRESS" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" , +// dest,"out_MEMORY_OUT_VAL" ); +// PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" , +// dest, "in_MEMORY_OUT_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" , +// dest,"out_MEMORY_OUT_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" , +// dest,"out_MEMORY_OUT_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID", +// dest,"out_MEMORY_OUT_OOO_ENGINE_ID"); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" , +// dest,"out_MEMORY_OUT_PACKET_ID" ); +// // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , +// // dest,"out_MEMORY_OUT_OPERATION" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , +// dest,"out_MEMORY_OUT_TYPE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , +// dest,"out_MEMORY_OUT_WRITE_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" , +// dest,"out_MEMORY_OUT_NUM_REG_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" , +// dest,"out_MEMORY_OUT_DATA_RD" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" , +// dest,"out_MEMORY_OUT_WRITE_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" , +// dest,"out_MEMORY_OUT_NUM_REG_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" , +// dest,"out_MEMORY_OUT_DATA_RE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" , +// dest,"out_MEMORY_OUT_EXCEPTION" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" , +// dest,"out_MEMORY_OUT_NO_SEQUENCE" ); +// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" , +// dest,"out_MEMORY_OUT_ADDRESS" ); } } @@ -1566,60 +1677,52 @@ #endif - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" , - dest, "in_WRITE_UNIT_IN_VAL" ); - PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" , - dest,"out_WRITE_UNIT_IN_ACK" ); - if (_param->_have_port_context_id) - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , - dest, "in_WRITE_UNIT_IN_CONTEXT_ID" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , - dest, "in_WRITE_UNIT_IN_FRONT_END_ID" ); - if (_param->_have_port_ooo_engine_id) - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID", - dest, "in_WRITE_UNIT_IN_OOO_ENGINE_ID"); - if (_param->_have_port_packet_id) - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" , - dest, "in_WRITE_UNIT_IN_PACKET_ID" ); -// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" , -// dest, "in_WRITE_UNIT_IN_OPERATION" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" , - dest, "in_WRITE_UNIT_IN_TYPE" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" , - dest, "in_WRITE_UNIT_IN_WRITE_RD" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , - dest, "in_WRITE_UNIT_IN_NUM_REG_RD" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" , - dest, "in_WRITE_UNIT_IN_DATA_RD" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" , - dest, "in_WRITE_UNIT_IN_WRITE_RE" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , - dest, "in_WRITE_UNIT_IN_NUM_REG_RE" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" , - dest, "in_WRITE_UNIT_IN_DATA_RE" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" , - dest, "in_WRITE_UNIT_IN_EXCEPTION" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" , - dest, "in_WRITE_UNIT_IN_NO_SEQUENCE" ); - PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" , - dest, "in_WRITE_UNIT_IN_ADDRESS" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" , +// dest, "in_WRITE_UNIT_IN_VAL" ); +// PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" , +// dest,"out_WRITE_UNIT_IN_ACK" ); +// if (_param->_have_port_context_id) +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" , +// dest, "in_WRITE_UNIT_IN_CONTEXT_ID" ); +// if (_param->_have_port_front_end_id) +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" , +// dest, "in_WRITE_UNIT_IN_FRONT_END_ID" ); +// if (_param->_have_port_ooo_engine_id) +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID", +// dest, "in_WRITE_UNIT_IN_OOO_ENGINE_ID"); +// if (_param->_have_port_rob_ptr ) +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" , +// dest, "in_WRITE_UNIT_IN_PACKET_ID" ); +// // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" , +// // dest, "in_WRITE_UNIT_IN_OPERATION" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" , +// dest, "in_WRITE_UNIT_IN_TYPE" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" , +// dest, "in_WRITE_UNIT_IN_WRITE_RD" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" , +// dest, "in_WRITE_UNIT_IN_NUM_REG_RD" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" , +// dest, "in_WRITE_UNIT_IN_DATA_RD" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" , +// dest, "in_WRITE_UNIT_IN_WRITE_RE" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" , +// dest, "in_WRITE_UNIT_IN_NUM_REG_RE" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" , +// dest, "in_WRITE_UNIT_IN_DATA_RE" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" , +// dest, "in_WRITE_UNIT_IN_EXCEPTION" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" , +// dest, "in_WRITE_UNIT_IN_NO_SEQUENCE" ); +// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" , +// dest, "in_WRITE_UNIT_IN_ADDRESS" ); } } +#if DEBUG_Execute_loop == true _component->test_map(); - for (uint32_t i=0; i<_param->_nb_read_unit; i++) - _component_read_unit [i]->_component->test_map(); - for (uint32_t i=0; i<_param->_nb_functionnal_unit; i++) - _component_functionnal_unit [i]->_component->test_map(); - for (uint32_t i=0; i<_param->_nb_load_store_unit; i++) - _component_load_store_unit [i]->_component->test_map(); - for (uint32_t i=0; i<_param->_nb_write_unit; i++) - _component_write_unit [i]->_component->test_map(); - _component_read_unit_to_execution_unit->_component->test_map(); - _component_execution_unit_to_write_unit->_component->test_map(); - _component_register_unit->_component->test_map(); - -#ifdef POSITION - _component->generate_file(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_deallocation.cpp (revision 88) @@ -1,2 +1,3 @@ + /* * $Id$ @@ -7,5 +8,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h" - +#include "Behavioural/include/Allocation.h" namespace morpheo { namespace behavioural { @@ -21,105 +22,90 @@ log_printf(FUNC,Execute_loop,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; delete in_NRESET; - // ~~~~~[ Interface "execute_loop_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_EXECUTE_LOOP_IN_VAL ; - delete [] out_EXECUTE_LOOP_IN_ACK ; - if (_param->_have_port_context_id) - delete [] in_EXECUTE_LOOP_IN_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] in_EXECUTE_LOOP_IN_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) - delete [] in_EXECUTE_LOOP_IN_PACKET_ID ; - delete [] in_EXECUTE_LOOP_IN_OPERATION ; - delete [] in_EXECUTE_LOOP_IN_TYPE ; - delete [] in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE; - if (_param->_have_port_load_queue_ptr) - delete [] in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ; - delete [] in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ; - delete [] in_EXECUTE_LOOP_IN_IMMEDIAT ; - delete [] in_EXECUTE_LOOP_IN_READ_RA ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RA ; - delete [] in_EXECUTE_LOOP_IN_READ_RB ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RB ; - delete [] in_EXECUTE_LOOP_IN_READ_RC ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RC ; - delete [] in_EXECUTE_LOOP_IN_WRITE_RD ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RD ; - delete [] in_EXECUTE_LOOP_IN_WRITE_RE ; - delete [] in_EXECUTE_LOOP_IN_NUM_REG_RE ; + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_VAL ,_param->_nb_read_unit,1); + DELETE1_SIGNAL(out_EXECUTE_LOOP_IN_ACK ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_CONTEXT_ID ,_param->_nb_read_unit,_param->_size_context_id); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_FRONT_END_ID ,_param->_nb_read_unit,_param->_size_front_end_id); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ,_param->_nb_read_unit,_param->_size_ooo_engine_id); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_PACKET_ID ,_param->_nb_read_unit,_param->_size_rob_ptr ); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_OPERATION ,_param->_nb_read_unit,_param->_size_operation); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_TYPE ,_param->_nb_read_unit,_param->_size_type); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_read_unit,_param->_size_store_queue_ptr); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_read_unit,_param->_size_load_queue_ptr); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_IMMEDIAT ,_param->_nb_read_unit,_param->_size_general_data); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_READ_RA ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RA ,_param->_nb_read_unit,_param->_size_general_register); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_READ_RB ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RB ,_param->_nb_read_unit,_param->_size_general_register); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_READ_RC ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RC ,_param->_nb_read_unit,_param->_size_special_register); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_WRITE_RD ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RD ,_param->_nb_read_unit,_param->_size_general_register); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_WRITE_RE ,_param->_nb_read_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_IN_NUM_REG_RE ,_param->_nb_read_unit,_param->_size_special_register); + + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_VAL ,_param->_nb_write_unit,1); + DELETE1_SIGNAL( in_EXECUTE_LOOP_OUT_ACK ,_param->_nb_write_unit,1); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_CONTEXT_ID ,_param->_nb_write_unit,_param->_size_context_id); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_FRONT_END_ID ,_param->_nb_write_unit,_param->_size_front_end_id); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID,_param->_nb_write_unit,_param->_size_ooo_engine_id); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_PACKET_ID ,_param->_nb_write_unit,_param->_size_rob_ptr ); +// DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_OPERATION ,_param->_nb_write_unit,_param->_size_operation); +// DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_TYPE ,_param->_nb_write_unit,_param->_size_type); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_FLAGS ,_param->_nb_write_unit,_param->_size_special_data); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_EXCEPTION ,_param->_nb_write_unit,_param->_size_exception); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,_param->_nb_write_unit,1); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,_param->_nb_write_unit,_param->_size_general_data); + DELETE1_SIGNAL(out_EXECUTE_LOOP_OUT_DATA ,_param->_nb_write_unit,_param->_size_general_data); + + DELETE2_SIGNAL(out_DCACHE_REQ_VAL , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],1 ); + DELETE2_SIGNAL( in_DCACHE_REQ_ACK , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],1 ); + DELETE2_SIGNAL(out_DCACHE_REQ_CONTEXT_ID, _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_max_size_dcache_context_id); + DELETE2_SIGNAL(out_DCACHE_REQ_PACKET_ID , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_max_size_dcache_packet_id ); + DELETE2_SIGNAL(out_DCACHE_REQ_ADDRESS , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_size_general_data ); + DELETE2_SIGNAL(out_DCACHE_REQ_TYPE , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_size_dcache_type ); + DELETE2_SIGNAL(out_DCACHE_REQ_WDATA , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_size_general_data ); + + DELETE2_SIGNAL( in_DCACHE_RSP_VAL , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],1 ); + DELETE2_SIGNAL(out_DCACHE_RSP_ACK , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],1 ); + DELETE2_SIGNAL( in_DCACHE_RSP_CONTEXT_ID, _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_max_size_dcache_context_id); + DELETE2_SIGNAL( in_DCACHE_RSP_PACKET_ID , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_max_size_dcache_packet_id ); + DELETE2_SIGNAL( in_DCACHE_RSP_RDATA , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_DCACHE_RSP_ERROR , _param->_nb_load_store_unit, _param->_nb_cache_port[it1],_param->_size_dcache_error ); + + DELETE2_SIGNAL( in_INSERT_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],1 ); + DELETE2_SIGNAL( in_INSERT_ROB_RD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],1 ); + DELETE2_SIGNAL( in_INSERT_ROB_RD_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_ROB_RE_USE ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],1 ); + DELETE2_SIGNAL( in_INSERT_ROB_RE_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[it1],_param->_size_special_register); + +// DELETE2_SIGNAL( in_RETIRE_ROB_VAL ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL(out_RETIRE_ROB_ACK ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_ROB_RD_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_ROB_RD_OLD_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],_param->_size_general_register); +// DELETE2_SIGNAL( in_RETIRE_ROB_RD_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_ROB_RD_NEW_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],_param->_size_general_register); +// DELETE2_SIGNAL( in_RETIRE_ROB_RE_OLD_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_ROB_RE_OLD_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],_param->_size_special_register); +// DELETE2_SIGNAL( in_RETIRE_ROB_RE_NEW_USE ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_ROB_RE_NEW_NUM_REG,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[it1],_param->_size_special_register); + } - // ~~~~~[ Interface "execute_loop_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_EXECUTE_LOOP_OUT_VAL ; - delete [] in_EXECUTE_LOOP_OUT_ACK ; - if (_param->_have_port_context_id) - delete [] out_EXECUTE_LOOP_OUT_CONTEXT_ID ; - if (_param->_have_port_front_end_id) - delete [] out_EXECUTE_LOOP_OUT_FRONT_END_ID ; - if (_param->_have_port_ooo_engine_id) - delete [] out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID ; - if (_param->_have_port_packet_id) - delete [] out_EXECUTE_LOOP_OUT_PACKET_ID ; - //delete [] out_EXECUTE_LOOP_OUT_OPERATION ; - //delete [] out_EXECUTE_LOOP_OUT_TYPE ; - delete [] out_EXECUTE_LOOP_OUT_FLAGS ; - delete [] out_EXECUTE_LOOP_OUT_EXCEPTION ; - delete [] out_EXECUTE_LOOP_OUT_NO_SEQUENCE ; - delete [] out_EXECUTE_LOOP_OUT_ADDRESS ; - - // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_DCACHE_REQ_VAL ; - delete [] in_DCACHE_REQ_ACK ; - if (_param->_have_port_dcache_context_id) - delete [] out_DCACHE_REQ_CONTEXT_ID ; - delete [] out_DCACHE_REQ_PACKET_ID ; - delete [] out_DCACHE_REQ_ADDRESS ; - delete [] out_DCACHE_REQ_TYPE ; - delete [] out_DCACHE_REQ_WDATA ; - - // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_DCACHE_RSP_VAL ; - delete [] out_DCACHE_RSP_ACK ; - if (_param->_have_port_dcache_context_id) - delete [] in_DCACHE_RSP_CONTEXT_ID ; - delete [] in_DCACHE_RSP_PACKET_ID ; - delete [] in_DCACHE_RSP_RDATA ; - delete [] in_DCACHE_RSP_ERROR ; - - // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_INSERT_ROB_VAL ; - delete [] out_INSERT_ROB_ACK ; - delete [] in_INSERT_ROB_RD_USE ; - delete [] in_INSERT_ROB_RD_NUM_REG ; - delete [] in_INSERT_ROB_RE_USE ; - delete [] in_INSERT_ROB_RE_NUM_REG ; - - // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] in_RETIRE_ROB_VAL ; - delete [] out_RETIRE_ROB_ACK ; - delete [] in_RETIRE_ROB_RD_OLD_USE ; - delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RD_NEW_USE ; - delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; - delete [] in_RETIRE_ROB_RE_OLD_USE ; - delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; - delete [] in_RETIRE_ROB_RE_NEW_USE ; - delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; - } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete _component; + delete _component_glue ; delete [] _component_read_unit ; delete [] _component_functionnal_unit ; delete [] _component_load_store_unit ; delete [] _component_write_unit ; - delete [] _component_read_unit_to_execution_unit ; - delete [] _component_execution_unit_to_write_unit; - delete [] _component_register_unit ; + delete _component_read_unit_to_execution_unit ; + delete _component_execution_unit_to_write_unit; + delete _component_register_unit ; log_printf(FUNC,Execute_loop,FUNCTION,"End"); @@ -129,5 +115,4 @@ }; // end namespace multi_execute_loop }; // end namespace core - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_end_cycle.cpp (revision 88) @@ -23,5 +23,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -29,5 +30,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_statistics_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_statistics_declaration.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_statistics_declaration.cpp (revision 88) @@ -37,4 +37,5 @@ _stat->add_stat(_component_execution_unit_to_write_unit->_stat); _stat->add_stat(_component_register_unit ->_stat); + _stat->add_stat(_component_glue ->_stat); log_printf(FUNC,Execute_loop,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h" +#include "Common/include/Max.h" namespace morpheo { @@ -29,21 +30,24 @@ uint32_t size_special_data , - uint32_t * size_read_queue , - uint32_t * size_reservation_station , - uint32_t * nb_inst_retire , + uint32_t * size_read_queue ,//[nb_read_unit] + uint32_t * size_reservation_station ,//[nb_read_unit] + uint32_t * nb_inst_retire ,//[nb_read_unit] + + uint32_t * nb_inst_functionnal_unit ,//[nb_functionnal_unit] + execute_timing_t *** timing ,//[nb_functionnal_unit][nb_type][nb_operation] + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), - execute_timing_t *** timing , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t), - - uint32_t * size_store_queue , - uint32_t * size_load_queue , - uint32_t * size_speculative_access_queue , - uint32_t * nb_port_check , - Tspeculative_load_t * speculative_load , - uint32_t * nb_bypass_memory , - - uint32_t * size_write_queue , - uint32_t * size_execute_queue , - uint32_t * nb_bypass_write , + uint32_t * size_store_queue ,//[nb_load_store_unit] + uint32_t * size_load_queue ,//[nb_load_store_unit] + uint32_t * size_speculative_access_queue ,//[nb_load_store_unit] + uint32_t * nb_port_check ,//[nb_load_store_unit] + Tspeculative_load_t * speculative_load ,//[nb_load_store_unit] + uint32_t * nb_bypass_memory ,//[nb_load_store_unit] + uint32_t * nb_cache_port ,//[nb_load_store_unit] + uint32_t * nb_inst_memory ,//[nb_load_store_unit] + + uint32_t * size_write_queue ,//[nb_write_unit] + uint32_t * size_execute_queue ,//[nb_write_unit] + uint32_t * nb_bypass_write ,//[nb_write_unit] uint32_t nb_gpr_bank , @@ -53,60 +57,66 @@ uint32_t nb_spr_port_read_by_bank , uint32_t nb_spr_port_write_by_bank , - uint32_t * nb_general_register , - uint32_t * nb_special_register , - uint32_t * nb_inst_insert_rob , - uint32_t * nb_inst_retire_rob , + uint32_t * nb_general_register ,//[nb_ooo_engine] + uint32_t * nb_special_register ,//[nb_ooo_engine] + uint32_t * nb_inst_insert_rob ,//[nb_ooo_engine] + uint32_t * nb_inst_retire_rob ,//[nb_ooo_engine] Tpriority_t execution_unit_to_write_unit_priority , - bool ** execution_unit_to_write_unit_table_routing, - bool ** execution_unit_to_write_unit_table_thread , - - Tpriority_t read_unit_to_execution_unit_priority , - bool ** read_unit_to_execution_unit_table_routing , - bool ** read_unit_to_execution_unit_table_thread - ) + bool *** execution_unit_to_write_unit_table_routing,//[nb_execute_unit][nb_execute_unit_port][nb_write_unit] + bool ** execution_unit_to_write_unit_table_thread ,//[nb_write_unit][nb_thread] + + Tpriority_t read_unit_to_execution_unit_priority , + bool *** read_unit_to_execution_unit_table_routing ,//[nb_read_unit][nb_execute_unit][nb_execute_unit_port] + bool ** read_unit_to_execution_unit_table_thread ,//[nb_execute_unit][nb_thread] + + bool * is_load_store_unit ,//[nb_execute_unit] + uint32_t * translate_num_execute_unit ,//[nb_execute_unit] + + bool is_toplevel + ) { log_printf(FUNC,Execute_loop,FUNCTION,"Begin"); - _nb_read_unit = nb_read_unit ; - _nb_functionnal_unit = nb_functionnal_unit ; - _nb_load_store_unit = nb_load_store_unit ; - _nb_write_unit = nb_write_unit ; - - _nb_context = nb_context ; - _nb_front_end = nb_front_end ; - _nb_ooo_engine = nb_ooo_engine ; - _nb_packet = nb_packet ; - _size_general_data = size_general_data ; - _size_special_data = size_special_data ; - - _size_read_queue = size_read_queue ; - _size_reservation_station = size_reservation_station ; - _nb_inst_retire = nb_inst_retire ; - - _timing = timing ; - _get_custom_information = get_custom_information ; - - _size_store_queue = size_store_queue ; - _size_load_queue = size_load_queue ; - _size_speculative_access_queue = size_speculative_access_queue ; - _nb_port_check = nb_port_check ; - _speculative_load = speculative_load ; - _nb_bypass_memory = nb_bypass_memory ; - - _size_write_queue = size_write_queue ; - _size_execute_queue = size_execute_queue ; - _nb_bypass_write = nb_bypass_write ; - - _nb_gpr_bank = nb_gpr_bank ; - _nb_gpr_port_read_by_bank = nb_gpr_port_read_by_bank ; - _nb_gpr_port_write_by_bank = nb_gpr_port_write_by_bank ; - _nb_spr_bank = nb_spr_bank ; - _nb_spr_port_read_by_bank = nb_spr_port_read_by_bank ; - _nb_spr_port_write_by_bank = nb_spr_port_write_by_bank ; - _nb_general_register = nb_general_register ; - _nb_special_register = nb_special_register ; - _nb_inst_insert_rob = nb_inst_insert_rob ; - _nb_inst_retire_rob = nb_inst_retire_rob ; + _nb_read_unit = nb_read_unit ; + _nb_functionnal_unit = nb_functionnal_unit ; + _nb_load_store_unit = nb_load_store_unit ; + _nb_write_unit = nb_write_unit ; + + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_ooo_engine = nb_ooo_engine ; + _nb_packet = nb_packet ; + + _size_read_queue = size_read_queue ; + _size_reservation_station = size_reservation_station ; + _nb_inst_retire = nb_inst_retire ; + + _nb_inst_functionnal_unit = nb_inst_functionnal_unit ; + _timing = timing ; + _get_custom_information = get_custom_information ; + + _size_store_queue = size_store_queue ; + _size_load_queue = size_load_queue ; + _size_speculative_access_queue = size_speculative_access_queue ; + _nb_port_check = nb_port_check ; + _speculative_load = speculative_load ; + _nb_bypass_memory = nb_bypass_memory ; + _nb_cache_port = nb_cache_port ; + _nb_inst_memory = nb_inst_memory ; + + _size_write_queue = size_write_queue ; + _size_execute_queue = size_execute_queue ; + _nb_bypass_write = nb_bypass_write ; + + _nb_gpr_bank = nb_gpr_bank ; + _nb_gpr_port_read_by_bank = nb_gpr_port_read_by_bank ; + _nb_gpr_port_write_by_bank = nb_gpr_port_write_by_bank ; + _nb_spr_bank = nb_spr_bank ; + _nb_spr_port_read_by_bank = nb_spr_port_read_by_bank ; + _nb_spr_port_write_by_bank = nb_spr_port_write_by_bank ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_inst_insert_rob = nb_inst_insert_rob ; + _nb_inst_retire_rob = nb_inst_retire_rob ; _execution_unit_to_write_unit_priority = execution_unit_to_write_unit_priority; @@ -114,27 +124,18 @@ _execution_unit_to_write_unit_table_thread = execution_unit_to_write_unit_table_thread ; - _read_unit_to_execution_unit_priority = read_unit_to_execution_unit_priority ; + _read_unit_to_execution_unit_priority = read_unit_to_execution_unit_priority ; _read_unit_to_execution_unit_table_routing = read_unit_to_execution_unit_table_routing ; _read_unit_to_execution_unit_table_thread = read_unit_to_execution_unit_table_thread ; - _nb_execute_unit = _nb_functionnal_unit + _nb_load_store_unit; - - _size_context_id = log2(nb_context ); - _size_front_end_id = log2(nb_front_end ); - _size_ooo_engine_id = log2(nb_ooo_engine ); - _size_packet_id = log2(nb_packet ); - - _have_port_context_id = _size_context_id >= 1; - _have_port_front_end_id = _size_front_end_id >= 1; - _have_port_ooo_engine_id = _size_ooo_engine_id >= 1; - _have_port_packet_id = _size_packet_id >= 1; - - _is_load_store_unit = new bool [_nb_execute_unit]; - _translate_num_execute_unit = new uint32_t [_nb_execute_unit]; - + _is_load_store_unit = is_load_store_unit ; + _translate_num_execute_unit = translate_num_execute_unit; + + _nb_execute_unit = _nb_functionnal_unit + _nb_load_store_unit; + + _nb_execute_unit_port = new uint32_t [_nb_execute_unit]; + _read_unit_to_execution_unit_table_execute_type = new bool * [_nb_execute_unit]; for (uint32_t i=0; i<_nb_execute_unit; i++) { - _is_load_store_unit [i] = false; _read_unit_to_execution_unit_table_execute_type [i] = new bool [_nb_type]; for (uint32_t j=0; j<_nb_type; j++) @@ -144,19 +145,30 @@ // Fill execute_type for (uint32_t i=0; i<_nb_execute_unit; i++) - for (uint32_t j=0; j<_nb_type; j++) - for (uint32_t k=0; k<_nb_operation; k++) - // Test if operation is implemnted - if (timing[i][j][k]._latence > 0) - { - _read_unit_to_execution_unit_table_execute_type [i][j] = true; - _is_load_store_unit [i] = (j == TYPE_MEMORY); - break; - } + // is load store + if (is_load_store_unit [i]) + _read_unit_to_execution_unit_table_execute_type [i][TYPE_MEMORY] = true; + else + for (uint32_t j=0; j<_nb_type; j++) + if (is_type_valid (j)) + for (uint32_t k=0; k<_nb_operation; k++) + { + uint32_t x = translate_num_execute_unit [i]; + if (timing[x][j][k]._latence > 0) + { + log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString_type(j).c_str()); + _read_unit_to_execution_unit_table_execute_type [i][j] = true; + break; // find an operation + } + } for (uint32_t i=0; i<_nb_execute_unit; i++) - if (_is_load_store_unit [i]) - log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' is a Load Store unit",i); - else - log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' is a Functionnal unit",i); + { + uint32_t x = translate_num_execute_unit [i]; + + if (_is_load_store_unit [i]) + _nb_execute_unit_port [i] = _nb_inst_memory [x]; + else + _nb_execute_unit_port [i] = _nb_inst_functionnal_unit [x]; + } _nb_gpr_read = 2*_nb_read_unit; @@ -165,24 +177,9 @@ _nb_spr_write = 1*_nb_write_unit; - _max_nb_general_register = 0; - _max_nb_special_register = 0; - for (uint32_t i=0; i _max_nb_general_register) _max_nb_general_register = _nb_general_register[i]; - if (_nb_special_register[i] > _max_nb_special_register) _max_nb_special_register = _nb_special_register[i]; - } - - _max_size_store_queue = 0; - _max_size_load_queue = 0; - for (uint32_t i=0; i _max_size_store_queue) _max_size_store_queue = _size_store_queue[i]; - if (_size_load_queue [i] > _max_size_load_queue ) _max_size_load_queue = _size_load_queue [i]; - } - - _have_port_load_queue_ptr= _max_size_load_queue >= 2; - - _size_general_register = log2(_max_nb_general_register); - _size_special_register = log2(_max_nb_special_register); + _max_nb_general_register = max(nb_general_register,nb_ooo_engine); + _max_nb_special_register = max(nb_special_register,nb_ooo_engine); + + _max_size_store_queue = max(size_store_queue,nb_load_store_unit); + _max_size_load_queue = max(size_load_queue ,nb_load_store_unit); uint32_t _nb_thread = get_nb_thread(_nb_context, @@ -190,4 +187,6 @@ _nb_ooo_engine); + uint32_t _max_nb_inst_memory = max(_nb_inst_memory,_nb_load_store_unit); + _set_read_unit_source_register_write = new std::set [_nb_read_unit]; _set_read_unit_source_bypass_write = new std::set [_nb_read_unit]; @@ -198,7 +197,7 @@ _read_unit_nb_bypass_memory = new uint32_t [_nb_read_unit]; - _link_read_unit_with_load_store_unit = new bool * [nb_read_unit]; - _link_read_unit_with_write_unit = new bool * [nb_read_unit]; - _link_read_unit_with_thread = new bool * [nb_read_unit]; + _link_read_unit_with_load_store_unit = new bool ** [nb_read_unit]; + _link_read_unit_with_write_unit = new bool * [nb_read_unit]; + _link_read_unit_with_thread = new bool * [nb_read_unit]; for (uint32_t i=0; i<_nb_read_unit; i++) @@ -208,10 +207,15 @@ _read_unit_nb_bypass_memory [i] = 0; - _link_read_unit_with_load_store_unit [i] = new bool [_nb_execute_unit]; - _link_read_unit_with_write_unit [i] = new bool [_nb_write_unit]; - _link_read_unit_with_thread [i] = new bool [_nb_thread]; + _link_read_unit_with_load_store_unit [i] = new bool * [_nb_execute_unit]; + _link_read_unit_with_write_unit [i] = new bool [_nb_write_unit]; + _link_read_unit_with_thread [i] = new bool [_nb_thread]; for (uint32_t j=0; j<_nb_execute_unit; j++) - _link_read_unit_with_load_store_unit [i][j] = false; + { + _link_read_unit_with_load_store_unit [i][j] = new bool [_max_nb_inst_memory]; + + for (uint32_t k=0; k<_max_nb_inst_memory; k++) + _link_read_unit_with_load_store_unit [i][j][k] = false; + } for (uint32_t j=0; j<_nb_write_unit; j++) _link_read_unit_with_write_unit [i][j] = false; @@ -220,35 +224,36 @@ // fill link array - for (uint32_t j=0; j<_nb_execute_unit; j++) - { - // Test if this read unit can send operation at this execute_unit - if (_read_unit_to_execution_unit_table_routing [i][j]) - { - if (_is_load_store_unit [j]) - { - _link_read_unit_with_load_store_unit [i][j] = true; - } - - for (uint32_t k=0; k<_nb_thread; k++) - { - if (_read_unit_to_execution_unit_table_thread [j][k]) - { - _link_read_unit_with_thread [i][k] = true; - } - } - // Scearch associed write_unit - for (uint32_t k=0; k<_nb_write_unit; k++) - { - // Test if this execute_unit can send operation at this write_unit - // Test if have not a previous link ! (a same read_unit can send operation à two execute_unit and each execute_unit send at the same write_unit) - if (_execution_unit_to_write_unit_table_routing [j][k] and - not _link_read_unit_with_write_unit [i][k]) - // if yes : this write_unit can have operation sended by this read_unit - { - _link_read_unit_with_write_unit [i][k] = true; - } - } - } - } + for (uint32_t x=0; x<_nb_execute_unit; x++) + for (uint32_t y=0; y<_nb_execute_unit_port[x]; y++) + { + // Test if this read unit can send operation at this execute_unit + if (_read_unit_to_execution_unit_table_routing [i][x][y]) + { + if (_is_load_store_unit [x]) + { + _link_read_unit_with_load_store_unit [i][x][y] = true; + } + + for (uint32_t k=0; k<_nb_thread; k++) + { + if (_read_unit_to_execution_unit_table_thread [x][k]) + { + _link_read_unit_with_thread [i][k] = true; + } + } + // Scearch associed write_unit + for (uint32_t k=0; k<_nb_write_unit; k++) + { + // Test if this execute_unit can send operation at this write_unit + // Test if have not a previous link ! (a same read_unit can send operation à two execute_unit and each execute_unit send at the same write_unit) + if (_execution_unit_to_write_unit_table_routing [x][y][k] and + not _link_read_unit_with_write_unit [i][k]) + // if yes : this write_unit can have operation sended by this read_unit + { + _link_read_unit_with_write_unit [i][k] = true; + } + } + } + } } @@ -258,52 +263,53 @@ - std::cout << "_link_......." << std::endl; - std::cout << "_link_read_unit_with_load_store_unit" << std::endl; +// std::cout << "_link_......." << std::endl; +// std::cout << "_link_read_unit_with_load_store_unit" << std::endl; +// for (uint32_t i=0; i<_nb_read_unit; i++) +// { +// std::cout << "\t" << std::endl; +// for (uint32_t j=0; j<_nb_execute_unit; j++) +// for (uint32_t k=0; k<_nb_execute_unit_port[j]; k++) +// std::cout << _link_read_unit_with_load_store_unit [i][j][k] << " "; +// std::cout << std::endl; +// } +// std::cout << "_link_read_unit_with_write_unit" << std::endl; +// for (uint32_t i=0; i<_nb_read_unit; i++) +// { +// std::cout << "\t" << std::endl; +// for (uint32_t j=0; j<_nb_write_unit; j++) +// std::cout << _link_read_unit_with_write_unit [i][j] << " "; +// std::cout << std::endl; +// } +// std::cout << "_link_read_unit_with_thread" << std::endl; +// for (uint32_t i=0; i<_nb_read_unit; i++) +// { +// std::cout << "\t" << std::endl; +// for (uint32_t j=0; j<_nb_thread; j++) +// std::cout << _link_read_unit_with_thread [i][j] << " "; +// std::cout << std::endl; +// } + +// std::cout << "_set_......." << std::endl; + for (uint32_t i=0; i<_nb_read_unit; i++) { - std::cout << "\t" << std::endl; - for (uint32_t j=0; j<_nb_execute_unit; j++) - std::cout << _link_read_unit_with_load_store_unit [i][j] << " "; - std::cout << std::endl; - } - std::cout << "_link_read_unit_with_write_unit" << std::endl; - for (uint32_t i=0; i<_nb_read_unit; i++) - { - std::cout << "\t" << std::endl; - for (uint32_t j=0; j<_nb_write_unit; j++) - std::cout << _link_read_unit_with_write_unit [i][j] << " "; - std::cout << std::endl; - } - std::cout << "_link_read_unit_with_thread" << std::endl; - for (uint32_t i=0; i<_nb_read_unit; i++) - { - std::cout << "\t" << std::endl; - for (uint32_t j=0; j<_nb_thread; j++) - std::cout << _link_read_unit_with_thread [i][j] << " "; - std::cout << std::endl; - } - - std::cout << "_set_......." << std::endl; - - for (uint32_t i=0; i<_nb_read_unit; i++) - { - std::cout << " * Read_unit[" << i << "]" << std::endl; +// std::cout << " * Read_unit[" << i << "]" << std::endl; for (uint32_t j=0; j<_nb_write_unit; j++) { - std::cout << " * Write_unit[" << j << "]" << std::endl; +// std::cout << " * Write_unit[" << j << "]" << std::endl; // Test the thread executed on this write_unit for (uint32_t k=0; k<_nb_thread; k++) { - std::cout << " * Thread[" << k << "]" << std::endl; +// std::cout << " * Thread[" << k << "]" << std::endl; if ( (_execution_unit_to_write_unit_table_thread [j][k]) and (_link_read_unit_with_thread [i][k])) { - std::cout << " * Find !!!!" << std::endl; - std::cout << " * Read_unit "+toString(i)+" must take the gpr_write with write_unit "+toString(j)+"." << std::endl; +// std::cout << " * Find !!!!" << std::endl; +// std::cout << " * Read_unit "+toString(i)+" must take the gpr_write with write_unit "+toString(j)+"." << std::endl; _set_read_unit_source_register_write[i].insert(j); _read_unit_nb_register_write [i] ++; - std::cout << " * bypass_write : " << _nb_bypass_write [j] << std::endl; - std::cout << " * Read_unit "+toString(i)+" must take the bypass_write with write_unit "+toString(j)+"." << std::endl; +// std::cout << " * bypass_write : " << _nb_bypass_write [j] << std::endl; +// std::cout << " * Read_unit "+toString(i)+" must take the bypass_write with write_unit "+toString(j)+"." << std::endl; _set_read_unit_source_bypass_write [i].insert(j); _read_unit_nb_bypass_write [i] += _nb_bypass_write [j]; @@ -316,23 +322,26 @@ for (uint32_t i=0; i<_nb_read_unit; i++) { - std::cout << " * Read_unit[" << i << "]" << std::endl; +// std::cout << " * Read_unit[" << i << "]" << std::endl; for (uint32_t j=0; j<_nb_execute_unit; j++) { - std::cout << " * Execute_unit[" << j << "]" << std::endl; + uint32_t x = translate_num_execute_unit [j]; + +// std::cout << " * Execute_unit[" << j << "]" << std::endl; // Test the thread executed on this execute_unit for (uint32_t k=0; k<_nb_thread; k++) { - std::cout << " * Thread[" << k << "]" << std::endl; +// std::cout << " * Thread[" << k << "]" << std::endl; if ((_read_unit_to_execution_unit_table_thread [j][k]) and (_link_read_unit_with_thread [i][k]) and (_is_load_store_unit [j])) { - std::cout << " * Find !!!!" << std::endl; - std::cout << " * Bypass_memory !!!!" << std::endl; - std::cout << " * Read_unit "+toString(i)+" must take the bypass_memory with load_store_unit "+toString(j)+"." << std::endl; +// std::cout << " * Find !!!!" << std::endl; +// std::cout << " * Bypass_memory !!!!" << std::endl; +// std::cout << " * Read_unit "+toString(i)+" must take the bypass_memory with load_store_unit "+toString(j)+"." << std::endl; _set_read_unit_source_bypass_memory [i].insert(j); - _read_unit_nb_bypass_memory [i] += _nb_bypass_memory [j]; - break; + _read_unit_nb_bypass_memory [i] += _nb_bypass_memory [x]; + + break; // loop on thread } } @@ -340,5 +349,22 @@ } + uint32_t size_ooo_engine_id = log2(nb_ooo_engine ); + uint32_t size_general_register = log2(_max_nb_general_register); + uint32_t size_special_register = log2(_max_nb_special_register); + test(); + + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : glue"); + + _param_glue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::execute_loop_glue::Parameters + (_nb_gpr_write , + _nb_spr_write , + size_ooo_engine_id , + size_general_register , + size_special_register , + size_general_data , + size_special_data ); + + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : read_unit"); _param_read_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Parameters * [_nb_read_unit]; @@ -351,6 +377,6 @@ _nb_ooo_engine , _nb_packet , - _size_general_data , - _size_special_data , + size_general_data , + size_special_data , _max_nb_general_register , _max_nb_special_register , @@ -363,15 +389,13 @@ _read_unit_nb_bypass_memory [i]); + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : execute_unit"); + _param_functionnal_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Parameters * [_nb_functionnal_unit]; _param_load_store_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * [_nb_load_store_unit]; - uint32_t x=0; - uint32_t y=0; - for (uint32_t i=0; i<_nb_execute_unit; i++) - if (_is_load_store_unit [i] == false) - { - _translate_num_execute_unit [i] = x; - + { + uint32_t x = _translate_num_execute_unit [i]; + if (_is_load_store_unit [i] == false) _param_functionnal_unit [x] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Parameters (_nb_context , @@ -379,40 +403,34 @@ _nb_ooo_engine , _nb_packet , - _size_general_data , + size_general_data , _max_nb_general_register , - _size_special_data , + size_special_data , _max_nb_special_register , _max_size_store_queue , _max_size_load_queue , - _timing [i], + _timing [x], _get_custom_information ); - - x++; - } - else - { - _translate_num_execute_unit [i] = y; - - _param_load_store_unit [y] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters - (_size_store_queue [y], - _size_load_queue [y], - _size_speculative_access_queue [y], - _nb_port_check [y], - _speculative_load [y], - _nb_bypass_memory [y], + else + _param_load_store_unit [x] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters + (_size_store_queue [x], + _size_load_queue [x], + _size_speculative_access_queue [x], + _nb_port_check [x], + _speculative_load [x], + _nb_bypass_memory [x], + _nb_cache_port [x], + _nb_inst_memory [x], _nb_context , _nb_front_end , _nb_ooo_engine , _nb_packet , - _size_general_data , - _size_special_data , + size_general_data , + size_special_data , _max_nb_special_register , _max_nb_general_register ); - - y ++; - } - - for (uint32_t i=0; i<_nb_load_store_unit; i++) - + } + + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : write_unit"); + _param_write_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Parameters * [_nb_write_unit]; for (uint32_t i=0; i<_nb_write_unit; i++) @@ -424,20 +442,24 @@ _nb_ooo_engine , _nb_packet , - _size_general_data , + size_general_data , _max_nb_general_register , - _size_special_data , + size_special_data , _max_nb_special_register , _nb_bypass_write [i]); + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : read_unit_to_execution_unit"); + _param_read_unit_to_execution_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::read_unit_to_execution_unit::Parameters (_nb_read_unit , + _nb_inst_retire , _nb_execute_unit , + _nb_execute_unit_port , _nb_context , _nb_front_end , _nb_ooo_engine , _nb_packet , - _size_general_data , - _size_special_data , + size_general_data , + size_special_data , _max_nb_general_register , _max_nb_special_register , @@ -449,6 +471,9 @@ _read_unit_to_execution_unit_table_thread ); + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : execution_unit_to_write_unit"); + _param_execution_unit_to_write_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::execution_unit_to_write_unit::Parameters (_nb_execute_unit , + _nb_execute_unit_port , _nb_write_unit , _nb_context , @@ -456,6 +481,6 @@ _nb_ooo_engine , _nb_packet , - _size_general_data , - _size_special_data , + size_general_data , + size_special_data , _max_nb_general_register , _max_nb_special_register , @@ -464,8 +489,10 @@ _execution_unit_to_write_unit_table_thread ); + log_printf(TRACE,Execute_loop,FUNCTION,"Parameters : register_unit"); + _param_register_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::Parameters (_nb_ooo_engine , - _size_general_data , - _size_special_data , + size_general_data , + size_special_data , _nb_gpr_read , _nb_gpr_write , @@ -483,5 +510,4 @@ _nb_inst_retire_rob ); - _max_size_dcache_context_id = 0; _max_size_dcache_packet_id = 0; @@ -494,4 +520,28 @@ _have_port_dcache_context_id = (_max_size_dcache_context_id>1); + + + if (is_toplevel) + { + _size_context_id = log2(nb_context); + _size_front_end_id = log2(nb_front_end); + _size_ooo_engine_id = size_ooo_engine_id; + _size_rob_ptr = log2(nb_packet); + _size_general_data = size_general_data; + _size_special_data = size_special_data; + _size_general_register = size_general_register; + _size_special_register = size_special_register; + + _size_store_queue_ptr = log2(_max_size_store_queue); + _size_load_queue_ptr = log2(_max_size_load_queue ); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr= _size_load_queue_ptr > 0; + + copy(); + } log_printf(FUNC,Execute_loop,FUNCTION,"End"); @@ -511,11 +561,26 @@ #undef FUNCTION #define FUNCTION "Execute_loop::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) { log_printf(FUNC,Execute_loop,FUNCTION,"Begin"); + delete _param_glue; + for (uint32_t i=0; i<_nb_read_unit; i++) + delete _param_read_unit [i]; delete [] _param_read_unit; + + for (uint32_t i=0; i<_nb_execute_unit; i++) + { + uint32_t x = _translate_num_execute_unit [i]; + + if (_is_load_store_unit [i] == false) + delete _param_functionnal_unit [x]; + else + delete _param_load_store_unit [x]; + } delete [] _param_functionnal_unit; delete [] _param_load_store_unit; + for (uint32_t i=0; i<_nb_write_unit; i++) + delete _param_write_unit [i]; delete [] _param_write_unit; delete _param_read_unit_to_execution_unit; @@ -535,4 +600,33 @@ delete [] _is_load_store_unit; delete [] _translate_num_execute_unit; + delete [] _nb_execute_unit_port; + log_printf(FUNC,Execute_loop,FUNCTION,"End"); + }; + + +#undef FUNCTION +#define FUNCTION "Execute_loop::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Execute_loop,FUNCTION,"Begin"); + + COPY(_param_glue); + for (uint32_t i=0; i<_nb_read_unit; i++) + COPY(_param_read_unit [i]); + + for (uint32_t i=0; i<_nb_execute_unit; i++) + { + uint32_t x = _translate_num_execute_unit [i]; + + if (_is_load_store_unit [i] == false) + COPY(_param_functionnal_unit [x]); + else + COPY(_param_load_store_unit [x]); + } + for (uint32_t i=0; i<_nb_write_unit; i++) + COPY(_param_write_unit [i]); + COPY(_param_read_unit_to_execution_unit); + COPY(_param_execution_unit_to_write_unit); + COPY(_param_register_unit); log_printf(FUNC,Execute_loop,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_msg_error.cpp (revision 88) @@ -25,4 +25,8 @@ Parameters_test test ("Execute_loop"); + for (uint32_t i=0; i<_nb_functionnal_unit; i++) + if (_nb_inst_functionnal_unit [i] != 1) + test.error(toString(_("Functionnal_unit [%d] must treat once instruction.\n"),i)); + log_printf(FUNC,Execute_loop,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters_print.cpp (revision 88) @@ -68,4 +68,6 @@ xml. singleton_begin("speculative_load "); xml.attribut("value",toString(_speculative_load [i])); xml.singleton_end(); xml. singleton_begin("nb_bypass_memory "); xml.attribut("value",toString(_nb_bypass_memory [i])); xml.singleton_end(); + xml. singleton_begin("nb_cache_port "); xml.attribut("value",toString(_nb_cache_port [i])); xml.singleton_end(); + xml. singleton_begin("nb_inst_memory "); xml.attribut("value",toString(_nb_inst_memory [i])); xml.singleton_end(); xml.balise_close(); } @@ -109,4 +111,5 @@ str += _param_execution_unit_to_write_unit->print(depth+1); str += _param_register_unit->print(depth+1); + str += _param_glue->print(depth+1); xml.comment("\n"+str); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Context_State_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_min.cfg (revision 88) @@ -2,10 +2,8 @@ 1 1 +1 # nb_context 1 1 +1 # nb_decod_unit -1 1 +1 # nb_ooo_engine 1 1 +1 # nb_inst_branch_complete 0 0 +1 # size_depth [0] [nb_context] 30 30 +1 # size_address 1 1 +1 # size_inst_decod [0] [nb_decod_unit] -1 1 +1 # size_inst_commit [0] [nb_ooo_engine] +1 1 +1 # size_inst_commit 0 0 +1 # link_context_to_decod_unit [0] [nb_context] -0 0 +1 # link_decod_unit_to_ooo_engine [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_mono_context.cfg (revision 88) @@ -2,10 +2,8 @@ 1 1 +1 # nb_context 1 1 *4 # nb_decod_unit -1 1 *4 # nb_ooo_engine 1 4 *4 # nb_inst_branch_complete 0 2 +1 # size_depth [0] [nb_context] 30 30 +1 # size_address 1 4 *4 # size_inst_decod [0] [nb_decod_unit] -1 4 *4 # size_inst_commit [0] [nb_ooo_engine] +1 4 *4 # size_inst_commit 0 0 +1 # link_context_to_decod_unit [0] [nb_context] -0 0 +1 # link_decod_unit_to_ooo_engine [0] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/config_multi_context.cfg (revision 88) @@ -2,5 +2,4 @@ 8 8 +1 # nb_context 4 4 *4 # nb_decod_unit -2 2 *4 # nb_ooo_engine 2 2 *4 # nb_inst_branch_complete 4 4 +1 # size_depth [0] [nb_context] @@ -17,6 +16,5 @@ 2 2 *4 # size_inst_decod [2] [nb_decod_unit] 4 4 *4 # size_inst_decod [3] [nb_decod_unit] -8 8 *4 # size_inst_commit [0] [nb_ooo_engine] -2 2 *4 # size_inst_commit [1] [nb_ooo_engine] +8 8 *4 # size_inst_commit 0 0 +1 # link_context_to_decod_unit [0] [nb_context] 1 1 +1 # link_context_to_decod_unit [1] [nb_context] @@ -27,6 +25,2 @@ 2 2 +1 # link_context_to_decod_unit [6] [nb_context] 3 3 +1 # link_context_to_decod_unit [7] [nb_context] -0 0 +1 # link_decod_unit_to_ooo_engine [0] [nb_decod_unit] -1 1 +1 # link_decod_unit_to_ooo_engine [1] [nb_decod_unit] -0 0 +1 # link_decod_unit_to_ooo_engine [2] [nb_decod_unit] -1 1 +1 # link_decod_unit_to_ooo_engine [3] [nb_decod_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp (revision 88) @@ -16,12 +16,10 @@ err (_(" * nb_context (uint32_t)\n")); err (_(" * nb_decod_unit (uint32_t)\n")); - err (_(" * nb_ooo_engine (uint32_t)\n")); err (_(" * nb_inst_branch_complete (uint32_t)\n")); err (_(" * size_depth [nb_context] (uint32_t)\n")); err (_(" * size_address (uint32_t)\n")); err (_(" * size_inst_decod [nb_decod_unit] (uint32_t)\n")); - err (_(" * size_inst_commit [nb_ooo_engine] (uint32_t)\n")); + err (_(" * size_inst_commit (uint32_t)\n")); err (_(" * link_context_to_decod_unit [nb_context] (uint32_t)\n")); - err (_(" * link_decod_unit_to_ooo_engine [nb_decod_unit] (uint32_t)\n")); exit (1); @@ -45,8 +43,7 @@ uint32_t _nb_context = fromString(argv[x++]); uint32_t _nb_decod_unit = fromString(argv[x++]); - uint32_t _nb_ooo_engine = fromString(argv[x++]); uint32_t _nb_inst_branch_complete = fromString(argv[x++]); - if (argc != static_cast(2+NB_PARAMS+2*_nb_context+2*_nb_decod_unit+1*_nb_ooo_engine)) + if (argc != static_cast(2+NB_PARAMS+2*_nb_context+1*_nb_decod_unit)) usage (argc, argv); @@ -60,13 +57,8 @@ for (uint32_t i=0; i<_nb_decod_unit; i++) _size_inst_decod [i] = fromString(argv[x++]); - uint32_t * _size_inst_commit = new uint32_t [_nb_ooo_engine]; - for (uint32_t i=0; i<_nb_ooo_engine; i++) - _size_inst_commit [i] = fromString(argv[x++]); + uint32_t _size_inst_commit = fromString(argv[x++]); uint32_t * _link_context_to_decod_unit = new uint32_t [_nb_context]; for (uint32_t i=0; i<_nb_context; i++) _link_context_to_decod_unit [i] = fromString(argv[x++]); - uint32_t * _link_decod_unit_to_ooo_engine = new uint32_t [_nb_decod_unit]; - for (uint32_t i=0; i<_nb_decod_unit; i++) - _link_decod_unit_to_ooo_engine [i] = fromString(argv[x++]); int _return = EXIT_SUCCESS; @@ -76,5 +68,4 @@ (_nb_context , _nb_decod_unit , - _nb_ooo_engine , _nb_inst_branch_complete , _size_depth , @@ -83,5 +74,5 @@ _size_inst_commit , _link_context_to_decod_unit , - _link_decod_unit_to_ooo_engine + true ); @@ -98,7 +89,5 @@ delete [] _size_depth; delete [] _size_inst_decod; - delete [] _size_inst_commit; delete [] _link_context_to_decod_unit; - delete [] _link_decod_unit_to_ooo_engine; try Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 88) @@ -48,4 +48,12 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); + ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); +//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); +//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); +//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit); ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit); @@ -57,14 +65,14 @@ ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ,_param->_nb_ooo_engine); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -78,7 +86,7 @@ - ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_decod_unit); - ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context ); ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); @@ -89,16 +97,21 @@ ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_VAL ,"out_SPR_VAL ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL( in_SPR_ACK ," in_SPR_ACK ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_EPCR ,"out_SPR_EPCR ",Taddress_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_EEAR ,"out_SPR_EEAR ",Taddress_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_EEAR_WEN ,"out_SPR_EEAR_WEN ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_SR_DSX ,"out_SPR_SR_DSX ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL(out_SPR_SR_TO_ESR ,"out_SPR_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context ); ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context ); - ALLOC1_SC_SIGNAL( in_DEPTH_TAIL ," in_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context ); + + ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context ); + /******************************************************** * Instanciation @@ -110,9 +123,16 @@ (*(_Context_State->in_NRESET)) (*(in_NRESET)); + INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit); INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit); @@ -121,16 +141,16 @@ INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State,out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL ); + INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK ); if (_param->_have_port_context_id) - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine); - if (_param->_have_port_max_depth) - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID ); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); @@ -138,5 +158,5 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); @@ -145,7 +165,7 @@ INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); - INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_decod_unit); - INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_ooo_engine); - INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_ooo_engine); + INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context ); INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context ); @@ -156,17 +176,22 @@ INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_VAL ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_ACK ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EPCR ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EEAR ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EEAR_WEN ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_SR_DSX ,_param->_nb_context ); - INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_SR_TO_ESR ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context ); INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context ); for (uint32_t i=0; i<_param->_nb_context; i++) - if (_param->_have_port_depth [i]) - INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_TAIL [i]); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]); + + INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context ); + + INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -206,6 +231,5 @@ for (uint32_t i=0; i<_param->_nb_decod_unit; i++) in_DECOD_EVENT_VAL [i]->write(0); - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - in_COMMIT_EVENT_VAL [i]->write(0); + in_COMMIT_EVENT_VAL ->write(0); for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) in_BRANCH_COMPLETE_VAL [i]->write(0); @@ -213,6 +237,10 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - in_EVENT_ACK [i]->write(0); - in_SPR_ACK [i]->write(0); + in_BRANCH_EVENT_VAL [i]->write(0); + in_EVENT_ACK [i]->write(0); + in_SPR_EVENT_ACK [i]->write(0); + in_SPR_SR_IEE [i]->write(0); + in_SPR_SR_EPH [i]->write(0); + in_INTERRUPT_ENABLE [i]->write(0); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1); @@ -220,10 +248,8 @@ for (uint32_t i=0; i<_param->_nb_context; i++) - if (_param->_have_port_depth [i]) - in_DEPTH_TAIL [i]->write(i%_param->_size_depth[i]); + if (_param->_have_port_depth) + in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i])); uint32_t context = rand()%_param->_nb_context; - uint32_t decod_unit = _param->_link_context_to_decod_unit [context]; - uint32_t ooo_engine = _param->_link_decod_unit_to_ooo_engine [decod_unit]; if (1) @@ -232,7 +258,7 @@ LABEL("msync (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_decod_unit; @@ -242,6 +268,6 @@ in_DECOD_EVENT_ADDRESS [port]->write(0x100); in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC); @@ -263,7 +289,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -274,15 +300,15 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); SC_START(1); LABEL("msync (wait end)"); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - SC_START(3); - - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(1); + + SC_START(3); + + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); @@ -294,7 +320,7 @@ LABEL("psync (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_decod_unit; @@ -304,6 +330,6 @@ in_DECOD_EVENT_ADDRESS [port]->write(0x200); in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC); @@ -325,7 +351,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -361,7 +387,7 @@ LABEL("csync (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_decod_unit; @@ -371,6 +397,6 @@ in_DECOD_EVENT_ADDRESS [port]->write(0x200); in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC); @@ -392,7 +418,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -426,7 +452,7 @@ LABEL("spr (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_decod_unit; @@ -436,6 +462,6 @@ in_DECOD_EVENT_ADDRESS [port]->write(0x100); in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS); @@ -457,7 +483,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -468,15 +494,15 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); SC_START(1); LABEL("spr (wait end)"); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - - SC_START(3); - - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(1); + + SC_START(3); + + in_NB_INST_COMMIT_ALL [context]->write(0); SC_START(1); TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); @@ -488,13 +514,13 @@ LABEL("miss (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_inst_branch_complete; in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_BRANCH_COMPLETE_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); @@ -519,7 +545,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -558,13 +584,13 @@ LABEL("miss (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); uint32_t port = rand()%_param->_nb_inst_branch_complete; in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_BRANCH_COMPLETE_DEPTH [port]->write((context+1)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); @@ -589,7 +615,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -626,13 +652,13 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + uint32_t port = rand()%_param->_nb_decod_unit; in_DECOD_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0); @@ -657,7 +683,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -693,24 +719,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0x900); - //TEST(Taddress_t,out_SPR_EEAR [context]->read(),); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900); + //TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -720,13 +746,13 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + uint32_t port = rand()%_param->_nb_decod_unit; in_DECOD_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_DECOD_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); + if (_param->_have_port_depth) + in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1); @@ -751,7 +777,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -787,24 +813,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0x900); - //TEST(Taddress_t,out_SPR_EEAR [context]->read(),); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900); + //TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -814,31 +840,29 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; - - in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); - in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); - in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0); - in_COMMIT_EVENT_ADDRESS [port]->write(0xa00); - in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00); - in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00); - in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); - - SC_START(1); - } - while (not ( in_COMMIT_EVENT_VAL [port]->read() and - out_COMMIT_EVENT_ACK [port]->read())); - in_COMMIT_EVENT_VAL [port]->write(0); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + in_COMMIT_EVENT_CONTEXT_ID ->write(context); + if (_param->_have_port_depth) + in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); + in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); + in_COMMIT_EVENT_ADDRESS ->write(0xa00); + in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); + in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); + in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); + + SC_START(1); + } + while (not ( in_COMMIT_EVENT_VAL ->read() and + out_COMMIT_EVENT_ACK ->read())); + in_COMMIT_EVENT_VAL ->write(0); LABEL("exception (wait end)"); @@ -847,7 +871,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -883,24 +907,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xb00); - TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xc00); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00); + TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -910,31 +934,29 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; - - in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); - in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); - in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1); - in_COMMIT_EVENT_ADDRESS [port]->write(0xd00); - in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00); - in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00); - in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); - - SC_START(1); - } - while (not ( in_COMMIT_EVENT_VAL [port]->read() and - out_COMMIT_EVENT_ACK [port]->read())); - in_COMMIT_EVENT_VAL [port]->write(0); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + in_COMMIT_EVENT_CONTEXT_ID ->write(context); + if (_param->_have_port_depth) + in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); + in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); + in_COMMIT_EVENT_ADDRESS ->write(0xd00); + in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); + in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); + in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); + + SC_START(1); + } + while (not ( in_COMMIT_EVENT_VAL ->read() and + out_COMMIT_EVENT_ACK ->read())); + in_COMMIT_EVENT_VAL ->write(0); LABEL("exception (wait end)"); @@ -943,7 +965,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -979,24 +1001,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xe00); - TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xf00); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00); + TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -1006,31 +1028,29 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; - - in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); - in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); - in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0); - in_COMMIT_EVENT_ADDRESS [port]->write(0xa00); - in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00); - in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00); - in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); - - SC_START(1); - } - while (not ( in_COMMIT_EVENT_VAL [port]->read() and - out_COMMIT_EVENT_ACK [port]->read())); - in_COMMIT_EVENT_VAL [port]->write(0); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + in_COMMIT_EVENT_CONTEXT_ID ->write(context); + if (_param->_have_port_depth) + in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); + in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0); + in_COMMIT_EVENT_ADDRESS ->write(0xa00); + in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00); + in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00); + in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); + + SC_START(1); + } + while (not ( in_COMMIT_EVENT_VAL ->read() and + out_COMMIT_EVENT_ACK ->read())); + in_COMMIT_EVENT_VAL ->write(0); LABEL("exception (wait end)"); @@ -1039,7 +1059,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -1075,24 +1095,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xb00); - TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xc00); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),1); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00); + TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -1102,31 +1122,29 @@ LABEL("exception (begin)"); - in_NB_INST_DECOD_ALL [decod_unit]->write(1); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(1); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(1); - - uint32_t port = rand()%_param->_nb_ooo_engine; - - in_COMMIT_EVENT_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth [context]) - in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]); - in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION); - in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1); - in_COMMIT_EVENT_ADDRESS [port]->write(0xd00); - in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00); - in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00); - in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event); - - SC_START(1); - } - while (not ( in_COMMIT_EVENT_VAL [port]->read() and - out_COMMIT_EVENT_ACK [port]->read())); - in_COMMIT_EVENT_VAL [port]->write(0); + in_NB_INST_DECOD_ALL [context]->write(1); + in_NB_INST_COMMIT_ALL [context]->write(1); + in_NB_INST_COMMIT_MEM [context]->write(1); + + in_COMMIT_EVENT_CONTEXT_ID ->write(context); + if (_param->_have_port_depth) + in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context])); + in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION); + in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1); + in_COMMIT_EVENT_ADDRESS ->write(0xd00); + in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00); + in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00); + in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event); + + SC_START(1); + } + while (not ( in_COMMIT_EVENT_VAL ->read() and + out_COMMIT_EVENT_ACK ->read())); + in_COMMIT_EVENT_VAL ->write(0); LABEL("exception (wait end)"); @@ -1135,7 +1153,7 @@ SC_START(3); - in_NB_INST_DECOD_ALL [decod_unit]->write(0); - in_NB_INST_COMMIT_ALL [ooo_engine]->write(0); - in_NB_INST_COMMIT_MEM [ooo_engine]->write(0); + in_NB_INST_DECOD_ALL [context]->write(0); + in_NB_INST_COMMIT_ALL [context]->write(0); + in_NB_INST_COMMIT_MEM [context]->write(0); SC_START(1); @@ -1171,24 +1189,24 @@ do { - in_SPR_ACK [context]->write(rand()%percent_transaction_spr); - - SC_START(0); - - if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read()) - { - TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xe00); - TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xf00); - TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),1); - TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1); - TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1); - - find = true; - } - - SC_START(1); - } - while (not find); - - in_SPR_ACK [context]->write(0); + in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr); + + SC_START(0); + + if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read()) + { + TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00); + TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00); + TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1); + TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1); + TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1); + + find = true; + } + + SC_START(1); + } + while (not find); + + in_SPR_EVENT_ACK [context]->write(0); } @@ -1210,4 +1228,11 @@ delete in_NRESET; + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context); +//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); +//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); +//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit); @@ -1218,14 +1243,14 @@ DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit); DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); @@ -1236,7 +1261,7 @@ DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); - DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_decod_unit); - DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_ooo_engine); - DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_ooo_engine); + DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context ); DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context ); DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context ); @@ -1245,13 +1270,17 @@ DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_VAL ,_param->_nb_context ); - DELETE1_SC_SIGNAL( in_SPR_ACK ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_EPCR ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_EEAR ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_EEAR_WEN ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_SR_DSX ,_param->_nb_context ); - DELETE1_SC_SIGNAL(out_SPR_SR_TO_ESR ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context ); DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context ); - DELETE1_SC_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context ); + DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context ); + + DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context ); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 88) @@ -62,4 +62,13 @@ public : SC_CLOCK * in_CLOCK ; public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_ACK ;//[nb_context] +//public : SC_IN (Tcontext_t ) ** in_BRANCH_EVENT_CONTEXT_ID ;//[nb_context] +//public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context] +//public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context] + public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] + public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_DEST ;//[nb_context] // ~~~~~[ Interface : "decod_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -74,14 +83,14 @@ // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_VAL ;//[nb_ooo_engine] - public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_ACK ;//[nb_ooo_engine] - public : SC_IN (Tcontext_t ) ** in_COMMIT_EVENT_CONTEXT_ID ;//[nb_ooo_engine] - public : SC_IN (Tdepth_t ) ** in_COMMIT_EVENT_DEPTH ;//[nb_ooo_engine] - public : SC_IN (Tevent_type_t ) ** in_COMMIT_EVENT_TYPE ;//[nb_ooo_engine] - public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_IS_DELAY_SLOT ;//[nb_ooo_engine] - public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_ADDRESS ;//[nb_ooo_engine] - public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_ADDRESS_EPCR ;//[nb_ooo_engine] - public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_ADDRESS_EEAR_VAL ;//[nb_ooo_engine] - public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_ADDRESS_EEAR ;//[nb_ooo_engine] + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_VAL ; + public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ACK ; + public : SC_IN (Tcontext_t ) * in_COMMIT_EVENT_CONTEXT_ID ; + public : SC_IN (Tdepth_t ) * in_COMMIT_EVENT_DEPTH ; + public : SC_IN (Tevent_type_t ) * in_COMMIT_EVENT_TYPE ; + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_IS_DELAY_SLOT ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -96,7 +105,7 @@ // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcounter_t ) ** in_NB_INST_DECOD_ALL ;//[nb_decod_unit] - public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_ALL ;//[nb_ooo_engine] - public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_MEM ;//[nb_ooo_engine] + public : SC_IN (Tcounter_t ) ** in_NB_INST_DECOD_ALL ;//[nb_context] + public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_ALL ;//[nb_context] + public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_MEM ;//[nb_context] // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -108,12 +117,12 @@ public : SC_OUT(Tcontrol_t ) ** out_EVENT_IS_DS_TAKE ;//[nb_context] - // ~~~~~[ Interface "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_SPR_VAL ;//[nb_context] - public : SC_IN (Tcontrol_t ) ** in_SPR_ACK ;//[nb_context] - public : SC_OUT(Taddress_t ) ** out_SPR_EPCR ;//[nb_context] - public : SC_OUT(Taddress_t ) ** out_SPR_EEAR ;//[nb_context] - public : SC_OUT(Tcontrol_t ) ** out_SPR_EEAR_WEN ;//[nb_context] - public : SC_OUT(Tcontrol_t ) ** out_SPR_SR_DSX ;//[nb_context] - public : SC_OUT(Tcontrol_t ) ** out_SPR_SR_TO_ESR ;//[nb_context] + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_SPR_EVENT_ACK ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_SPR_EVENT_EPCR ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_SPR_EVENT_EEAR ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_EEAR_WEN ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_SR_DSX ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_SR_TO_ESR ;//[nb_context] // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -121,5 +130,12 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tdepth_t ) ** in_DEPTH_TAIL ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_MIN ;//[nb_context] + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_SPR_SR_IEE ;//[nb_context] - Interrupt Exception Enabled + public : SC_IN (Tcontrol_t ) ** in_SPR_SR_EPH ;//[nb_context] - Exception Prefix High + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_INTERRUPT_ENABLE ;//[nb_context] - Interrupt Exception // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -135,11 +151,13 @@ private : Tcontrol_t * reg_EVENT_IS_DS_TAKE ;//[nb_context] private : Tdepth_t * reg_EVENT_DEPTH ;//[nb_context] + private : Tcontrol_t * reg_INTERRUPT_ENABLE ;//[nb_context] // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tcontrol_t * internal_BRANCH_EVENT_ACK ;//[nb_context] private : Tcontrol_t * internal_DECOD_EVENT_ACK ;//[nb_decod_unit] - private : Tcontrol_t * internal_COMMIT_EVENT_ACK ;//[nb_ooo_engine] + private : Tcontrol_t internal_COMMIT_EVENT_ACK ; private : Tcontrol_t * internal_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] private : Tcontrol_t * internal_EVENT_VAL ;//[nb_context] - private : Tcontrol_t * internal_SPR_VAL ;//[nb_context] + private : Tcontrol_t * internal_SPR_EVENT_VAL ;//[nb_context] #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 88) @@ -26,33 +26,26 @@ public : uint32_t _nb_context ; public : uint32_t _nb_decod_unit ; - public : uint32_t _nb_ooo_engine ; public : uint32_t _nb_inst_branch_complete ; - public : uint32_t * _size_depth ; //[nb_context] - public : uint32_t _size_address ; - public : uint32_t * _size_inst_decod ; //[nb_decod_unit] - public : uint32_t * _size_inst_commit ; //[nb_ooo_engine] + public : uint32_t * _array_size_depth ; //[nb_context] +//public : uint32_t * _size_depth ; //[nb_context] +//public : uint32_t _size_address ; +//public : uint32_t * _size_nb_inst_decod ; //[nb_decod_unit] +//public : uint32_t _size_nb_inst_commit ; public : uint32_t * _link_context_to_decod_unit ; //[nb_context] - public : uint32_t * _link_decod_unit_to_ooo_engine; //[nb_decod_unit] - - public : uint32_t _size_context_id; - public : uint32_t _size_max_depth ; - - public : bool _have_port_context_id; - public : bool * _have_port_depth ; - public : bool _have_port_max_depth ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_context, uint32_t nb_decod_unit, - uint32_t nb_ooo_engine, uint32_t nb_inst_branch_complete, uint32_t * size_depth, uint32_t size_address, - uint32_t * size_inst_decod, - uint32_t * size_inst_commit, + uint32_t * size_nb_inst_decod, + uint32_t size_nb_inst_commit, uint32_t * link_context_to_decod_unit, - uint32_t * link_decod_unit_to_ooo_engine); + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State.cpp (revision 88) @@ -39,4 +39,10 @@ usage_environment(_usage); +#if DEBUG_Context_State == true + log_printf(INFO,Context_State,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Context_State,FUNCTION,_("Allocation")); @@ -69,5 +75,11 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - // Constant + // Constant + for (uint32_t i=0; i<_param->_nb_context; i++) + { + internal_BRANCH_EVENT_ACK [i] = 1; + PORT_WRITE(out_BRANCH_EVENT_ACK [i], internal_BRANCH_EVENT_ACK [i]); + } + for (uint32_t i=0; i<_param->_nb_decod_unit; i++) { @@ -76,9 +88,6 @@ } - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - { - internal_COMMIT_EVENT_ACK [i] = 1; - PORT_WRITE(out_COMMIT_EVENT_ACK [i], internal_COMMIT_EVENT_ACK [i]); - } + internal_COMMIT_EVENT_ACK = 1; + PORT_WRITE(out_COMMIT_EVENT_ACK, internal_COMMIT_EVENT_ACK); for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 88) @@ -56,4 +56,17 @@ } + // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); + + ALLOC1_VALACK_IN ( in_BRANCH_EVENT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_BRANCH_EVENT_ACK ,ACK); +// ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); +// ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); +// ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); + } + // ~~~~~[ Interface : "decod_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { @@ -63,25 +76,25 @@ ALLOC1_VALACK_OUT(out_DECOD_EVENT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_max_depth); + ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_DECOD_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); } // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("commit_event",IN ,EAST, _("Interface with the Re Order Buffer"), _param->_nb_ooo_engine); - - ALLOC1_VALACK_IN ( in_COMMIT_EVENT_VAL ,VAL); - ALLOC1_VALACK_OUT(out_COMMIT_EVENT_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_max_depth); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Taddress_t ,_param->_size_address); + ALLOC_INTERFACE("commit_event",IN ,EAST, _("Interface with the Re Order Buffer")); + + ALLOC_VALACK_IN ( in_COMMIT_EVENT_VAL ,VAL); + ALLOC_VALACK_OUT (out_COMMIT_EVENT_ACK ,ACK); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Taddress_t ,_param->_size_instruction_address); } @@ -93,25 +106,18 @@ ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_max_depth); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"miss_prediction",Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); } // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("nb_inst",IN ,EAST, _("Interface to count in fligt present instruction."), _param->_nb_decod_unit); - - ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_inst_decod [alloc_signal_it1]); -// ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_inst_commit [alloc_signal_it1]); -// ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_inst_commit [alloc_signal_it1]); - } - { - ALLOC1_INTERFACE("nb_inst",IN ,EAST, _("Interface to count in fligt present instruction."), _param->_nb_ooo_engine); - -// ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_inst_decod [alloc_signal_it1]); - ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_inst_commit [alloc_signal_it1]); - ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_inst_commit [alloc_signal_it1]); + ALLOC1_INTERFACE("nb_inst",IN ,EAST, _("Interface to count in fligt present instruction."),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_NB_INST_DECOD_ALL ,"decod_all" ,Tcounter_t ,_param->_size_nb_inst_decod); + ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit); + ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit); } @@ -122,21 +128,21 @@ ALLOC1_VALACK_OUT(out_EVENT_VAL ,VAL); ALLOC1_VALACK_IN ( in_EVENT_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT ,"address_next" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t ,1); } - // ~~~~~[ Interface "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - ALLOC1_INTERFACE("spr",OUT,WEST, _("An exception occure : write \"exception PC\"."), _param->_nb_context); - - ALLOC1_VALACK_OUT(out_SPR_VAL ,VAL); - ALLOC1_VALACK_IN ( in_SPR_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_SPR_EPCR ,"epcr" ,Taddress_t, _param->_size_address); - ALLOC1_SIGNAL_OUT(out_SPR_EEAR ,"eear" ,Taddress_t, _param->_size_address); - ALLOC1_SIGNAL_OUT(out_SPR_EEAR_WEN ,"eear_wen" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_SPR_SR_DSX ,"sr_dsx" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_SPR_SR_TO_ESR ,"sr_to_esr",Tcontrol_t,1); + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr_event",OUT,WEST, _("An exception occure : write \"exception PC\"."), _param->_nb_context); + + ALLOC1_VALACK_OUT(out_SPR_EVENT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_SPR_EVENT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_SPR_EVENT_EPCR ,"epcr" ,Taddress_t, _param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_SPR_EVENT_EEAR ,"eear" ,Taddress_t, _param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_SPR_EVENT_EEAR_WEN ,"eear_wen" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_SPR_EVENT_SR_DSX ,"sr_dsx" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_SPR_EVENT_SR_TO_ESR ,"sr_to_esr",Tcontrol_t,1); } @@ -152,26 +158,46 @@ ALLOC1_INTERFACE("depth",IN ,NORTH, _("From prediction_unit."), _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_DEPTH_TAIL ,"tail",Tdepth_t,_param->_size_depth [alloc_signal_it1]); - } - - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - reg_STATE = new context_state_t [_param->_nb_context]; - reg_EVENT_ADDRESS = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EPCR = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EPCR_VAL = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EEAR = new Taddress_t [_param->_nb_context]; - reg_EVENT_ADDRESS_EEAR_VAL = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_IS_DS_TAKE = new Tcontrol_t [_param->_nb_context]; - reg_EVENT_DEPTH = new Tdepth_t [_param->_nb_context]; - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_DECOD_EVENT_ACK = new Tcontrol_t [_param->_nb_decod_unit]; - internal_COMMIT_EVENT_ACK = new Tcontrol_t [_param->_nb_ooo_engine]; - internal_BRANCH_COMPLETE_ACK = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; - internal_SPR_VAL = new Tcontrol_t [_param->_nb_context]; - + ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); + } + + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_SPR_SR_IEE ,"SR_IEE",Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_SPR_SR_EPH ,"SR_EPH",Tcontrol_t,1); + } + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"ENABLE",Tcontrol_t,1); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + reg_STATE = new context_state_t [_param->_nb_context]; + reg_EVENT_ADDRESS = new Taddress_t [_param->_nb_context]; + reg_EVENT_ADDRESS_EPCR = new Taddress_t [_param->_nb_context]; + reg_EVENT_ADDRESS_EPCR_VAL = new Tcontrol_t [_param->_nb_context]; + reg_EVENT_ADDRESS_EEAR = new Taddress_t [_param->_nb_context]; + reg_EVENT_ADDRESS_EEAR_VAL = new Tcontrol_t [_param->_nb_context]; + reg_EVENT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; + reg_EVENT_IS_DS_TAKE = new Tcontrol_t [_param->_nb_context]; + reg_EVENT_DEPTH = new Tdepth_t [_param->_nb_context]; + reg_INTERRUPT_ENABLE = new Tcontrol_t [_param->_nb_context]; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + internal_BRANCH_EVENT_ACK = new Tcontrol_t [_param->_nb_context]; + internal_DECOD_EVENT_ACK = new Tcontrol_t [_param->_nb_decod_unit]; + internal_BRANCH_COMPLETE_ACK = new Tcontrol_t [_param->_nb_inst_branch_complete]; + internal_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; + internal_SPR_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 88) @@ -28,77 +28,88 @@ delete in_NRESET; + DELETE1_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context,1); +// DELETE1_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); +// DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); +// DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); + DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit,1); DELETE1_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit,1); DELETE1_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_size_context_id); - DELETE1_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit,_param->_size_max_depth); + DELETE1_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit,_param->_size_depth); DELETE1_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit,_param->_size_event_type); DELETE1_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit,1); - DELETE1_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit,_param->_size_address); - DELETE1_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit,_param->_size_address); + DELETE1_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit,_param->_size_instruction_address); - DELETE1_SIGNAL( in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine,1); - DELETE1_SIGNAL(out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine,1); - DELETE1_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine,_param->_size_context_id); - DELETE1_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine,_param->_size_max_depth); - DELETE1_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine,_param->_size_event_type); - DELETE1_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine,1); - DELETE1_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine,_param->_size_address); - DELETE1_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine,_param->_size_address); - DELETE1_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine,_param->_size_address); - DELETE1_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine,1); + DELETE_SIGNAL ( in_COMMIT_EVENT_VAL ,1); + DELETE_SIGNAL (out_COMMIT_EVENT_ACK ,1); + DELETE_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); + DELETE_SIGNAL ( in_COMMIT_EVENT_DEPTH ,_param->_size_depth); + DELETE_SIGNAL ( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); + DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_size_instruction_address); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ,1); DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_max_depth); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_address); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_address); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); - DELETE1_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_decod_unit,_param->_size_inst_decod [alloc_signal_it1]); -// DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_decod_unit,_param->_size_inst_commit [alloc_signal_it1]); -// DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_decod_unit,_param->_size_inst_commit [alloc_signal_it1]); -// DELETE1_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_ooo_engine,_param->_size_inst_decod [alloc_signal_it1]); - DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_ooo_engine,_param->_size_inst_commit [alloc_signal_it1]); - DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_ooo_engine,_param->_size_inst_commit [alloc_signal_it1]); + DELETE1_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); + DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context,_param->_size_nb_inst_commit); + DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context,_param->_size_nb_inst_commit); DELETE1_SIGNAL(out_EVENT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL( in_EVENT_ACK ,_param->_nb_context,1); - DELETE1_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context,_param->_size_address); - DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context,_param->_size_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1); - DELETE1_SIGNAL(out_SPR_VAL ,_param->_nb_context,1); - DELETE1_SIGNAL( in_SPR_ACK ,_param->_nb_context,1); - DELETE1_SIGNAL(out_SPR_EPCR ,_param->_nb_context,_param->_size_address); - DELETE1_SIGNAL(out_SPR_EEAR ,_param->_nb_context,_param->_size_address); - DELETE1_SIGNAL(out_SPR_EEAR_WEN ,_param->_nb_context,1); - DELETE1_SIGNAL(out_SPR_SR_DSX ,_param->_nb_context,1); - DELETE1_SIGNAL(out_SPR_SR_TO_ESR ,_param->_nb_context,1); + DELETE1_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context,1); + DELETE1_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context,1); + DELETE1_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context,1); + DELETE1_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context,1); DELETE1_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context,1); - DELETE1_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth [alloc_signal_it1]); + DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + + DELETE1_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context,1); + DELETE1_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context,1); + + DELETE1_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context,1); + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] reg_STATE ; + delete [] reg_EVENT_ADDRESS ; + delete [] reg_EVENT_ADDRESS_EPCR ; + delete [] reg_EVENT_ADDRESS_EPCR_VAL; + delete [] reg_EVENT_ADDRESS_EEAR ; + delete [] reg_EVENT_ADDRESS_EEAR_VAL; + delete [] reg_EVENT_IS_DELAY_SLOT ; + delete [] reg_EVENT_IS_DS_TAKE ; + delete [] reg_EVENT_DEPTH ; + delete [] reg_INTERRUPT_ENABLE ; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_BRANCH_EVENT_ACK ; + delete [] internal_DECOD_EVENT_ACK ; + delete [] internal_EVENT_VAL ; + delete [] internal_SPR_EVENT_VAL ; } - - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] reg_STATE ; - delete [] reg_EVENT_ADDRESS ; - delete [] reg_EVENT_ADDRESS_EPCR ; - delete [] reg_EVENT_ADDRESS_EPCR_VAL; - delete [] reg_EVENT_ADDRESS_EEAR ; - delete [] reg_EVENT_ADDRESS_EEAR_VAL; - delete [] reg_EVENT_IS_DELAY_SLOT ; - delete [] reg_EVENT_IS_DS_TAKE ; - delete [] reg_EVENT_DEPTH ; - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_DECOD_EVENT_ACK ; - delete [] internal_COMMIT_EVENT_ACK ; - delete [] internal_EVENT_VAL ; - delete [] internal_SPR_VAL ; - + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 88) @@ -22,4 +22,5 @@ { log_begin(Context_State,FUNCTION); + log_function(Context_State,FUNCTION,_name.c_str()); // ------------------------------------------------------------------- @@ -30,22 +31,36 @@ context_state_t state = reg_STATE [i]; - internal_EVENT_VAL [i] = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or - (state == CONTEXT_STATE_KO_MISS_ADDR ) or - (state == CONTEXT_STATE_KO_PSYNC_ADDR) or - (state == CONTEXT_STATE_KO_CSYNC_ADDR)); - + Tcontrol_t val = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or + (state == CONTEXT_STATE_KO_MISS_ADDR ) or + (state == CONTEXT_STATE_KO_PSYNC_ADDR) or + (state == CONTEXT_STATE_KO_CSYNC_ADDR)); + + // SR can't change in this cycle + // Exception Prefix High + Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); + Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; + Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); + Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); // excep : address exception // miss : address delay_slot, and address dest // psync : address next // csync : address next - PORT_WRITE(out_EVENT_VAL [i], internal_EVENT_VAL [i]); - PORT_WRITE(out_EVENT_ADDRESS [i], reg_EVENT_ADDRESS [i]); - PORT_WRITE(out_EVENT_ADDRESS_NEXT [i], reg_EVENT_ADDRESS_EPCR [i]); - PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i])); - PORT_WRITE(out_EVENT_IS_DS_TAKE [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i])); + internal_EVENT_VAL [i] = val; + PORT_WRITE(out_EVENT_VAL [i], val); + PORT_WRITE(out_EVENT_ADDRESS [i], address); + PORT_WRITE(out_EVENT_ADDRESS_NEXT [i], address_next); + PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); + PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); + + log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); + log_printf(TRACE,Context_State,FUNCTION," * VAL : %d", val); + log_printf(TRACE,Context_State,FUNCTION," * ADDRESS : %.8x (%.8x)", address , address <<2); + log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)", address_next, address_next<<2); + log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); + log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); } // ------------------------------------------------------------------- - // -----[ SPR ]------------------------------------------------------- + // -----[ SPR_EVENT ]------------------------------------------------- // ------------------------------------------------------------------- for (uint32_t i=0; i<_param->_nb_context; i++) @@ -53,12 +68,12 @@ context_state_t state = reg_STATE [i]; - internal_SPR_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR ); + internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR ); - PORT_WRITE(out_SPR_VAL [i], internal_SPR_VAL [i]); - PORT_WRITE(out_SPR_EPCR [i], reg_EVENT_ADDRESS_EPCR [i]); - PORT_WRITE(out_SPR_EEAR [i], reg_EVENT_ADDRESS_EEAR [i]); - PORT_WRITE(out_SPR_EEAR_WEN [i], reg_EVENT_ADDRESS_EEAR_VAL [i]); - PORT_WRITE(out_SPR_SR_DSX [i], reg_EVENT_IS_DELAY_SLOT [i]); - PORT_WRITE(out_SPR_SR_TO_ESR [i], 1); + PORT_WRITE(out_SPR_EVENT_VAL [i], internal_SPR_EVENT_VAL [i]); + PORT_WRITE(out_SPR_EVENT_EPCR [i], reg_EVENT_ADDRESS_EPCR [i]); + PORT_WRITE(out_SPR_EVENT_EEAR [i], reg_EVENT_ADDRESS_EEAR [i]); + PORT_WRITE(out_SPR_EVENT_EEAR_WEN [i], reg_EVENT_ADDRESS_EEAR_VAL [i]); + PORT_WRITE(out_SPR_EVENT_SR_DSX [i], reg_EVENT_IS_DELAY_SLOT [i]); + PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 88) @@ -22,408 +22,472 @@ { log_begin(Context_State,FUNCTION); + log_function(Context_State,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) { - for (uint32_t i=0; i<_param->_nb_context; i++) - reg_STATE [i] = CONTEXT_STATE_OK; + for (uint32_t i=0; i<_param->_nb_context; i++) + { + reg_STATE [i] = CONTEXT_STATE_OK; + reg_INTERRUPT_ENABLE [i] = 0; + } } else { - // ------------------------------------------------------------------- - // -----[ DECOD_EVENT ]----------------------------------------------- - // ------------------------------------------------------------------- - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) - { - Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; - Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; - Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; - Tdepth_t depth_max = _param->_size_depth [context]; - - Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); - Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); - - context_state_t state = reg_STATE [context]; - Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); - - // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); - uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; - - // is_valid = can modify local information - // if context_state_ok : yes - // if context_state_ko : test the depth, and the priority of envent - - bool is_valid = ((state == CONTEXT_STATE_OK) or - (depth1< depth0) or - ((depth1==depth0) and (priority1>priority0))); - - if (is_valid) - { - // decod : - // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) - context_state_t state_next = state; - Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); - Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); - - switch (type) - { - case EVENT_TYPE_EXCEPTION : - { - state_next = CONTEXT_STATE_KO_EXCEP; - break; - } - case EVENT_TYPE_SPR_ACCESS : - { - state_next = CONTEXT_STATE_KO_SPR ; - address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); - break; - } - case EVENT_TYPE_MSYNC : - { - state_next = CONTEXT_STATE_KO_MSYNC; - address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); - break; - } - case EVENT_TYPE_PSYNC : - { - state_next = CONTEXT_STATE_KO_PSYNC; - address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); - break; - } - case EVENT_TYPE_CSYNC : - { - state_next = CONTEXT_STATE_KO_CSYNC; - address++; // take next address - if (is_delay_slot) - throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); - break; - } - case EVENT_TYPE_NONE : - case EVENT_TYPE_MISS_SPECULATION : - case EVENT_TYPE_BRANCH_NO_ACCURATE : - default : - { - throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); - } - } - - reg_STATE [context] = state_next; - reg_EVENT_ADDRESS [context] = address; - reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); - reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; - //reg_EVENT_ADDRESS_EEAR [context] - reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; - reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; - //reg_EVENT_IS_DS_TAKE [context] = 0; - reg_EVENT_DEPTH [context] = depth; - } - } - - // ------------------------------------------------------------------- - // -----[ COMMIT_EVENT ]---------------------------------------------- - // ------------------------------------------------------------------- - - for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) - if (PORT_READ(in_COMMIT_EVENT_VAL [i]) and internal_COMMIT_EVENT_ACK [i]) - { - Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH [i]):0; - Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; - Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; - Tdepth_t depth_max = _param->_size_depth [context]; - - Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); - Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); - - context_state_t state = reg_STATE [context]; - Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE [i]); - - // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); - uint8_t priority1 = 1; - - // is_valid = can modify local information - // if context_state_ok : yes - // if context_state_ko : test the depth, and the priority of envent - - bool is_valid = ((state == CONTEXT_STATE_OK) or - (depth1< depth0) or - ((depth1==depth0) and (priority1>priority0))); - - if (is_valid) - { - // commit - // type : exception - context_state_t state_next = state; - switch (type) - { - case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} - case EVENT_TYPE_SPR_ACCESS : - case EVENT_TYPE_MSYNC : - case EVENT_TYPE_PSYNC : - case EVENT_TYPE_CSYNC : - case EVENT_TYPE_NONE : - case EVENT_TYPE_MISS_SPECULATION : - case EVENT_TYPE_BRANCH_NO_ACCURATE : - default : - { - throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); - } - } - reg_STATE [context] = state_next; - reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS [i]); - reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR [i]); - reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; - reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR [i]); - reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL [i]); - reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT [i]); - //reg_EVENT_IS_DS_TAKE [context] = 0; - reg_EVENT_DEPTH [context] = depth; - } - } - - // ------------------------------------------------------------------- - // -----[ BRANCH_COMPLETE ]------------------------------------------- - // ------------------------------------------------------------------- - - for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) - if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) - { - if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) - { - Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; - Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; - Tdepth_t depth_base = (_param->_have_port_depth [context])?PORT_READ(in_DEPTH_TAIL [context]):0; - Tdepth_t depth_max = _param->_size_depth [context]; - - Tdepth_t depth0 = (depth_cur>=depth_base)?(depth_cur-depth_base):((depth_cur+depth_max-depth_base)); - Tdepth_t depth1 = (depth >=depth_base)?(depth -depth_base):((depth +depth_max-depth_base)); - - context_state_t state = reg_STATE [context]; - - // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); - uint8_t priority1 = 2; - - // is_valid = can modify local information - // if context_state_ok : yes - // if context_state_ko : test the depth, and the priority of envent - - bool is_valid = ((state == CONTEXT_STATE_OK) or - (depth1< depth0) or - ((depth1==depth0) and (priority1>priority0))); - - if (is_valid) - { - // commit - Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); - reg_STATE [context] = CONTEXT_STATE_KO_MISS; - reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT - reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); - reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence - //reg_EVENT_ADDRESS_EEAR [context]; - //reg_EVENT_ADDRESS_EEAR_VAL [context]; - reg_EVENT_IS_DELAY_SLOT [context] = take; - reg_EVENT_IS_DS_TAKE [context] = take; - reg_EVENT_DEPTH [context] = depth; - } - } - } - - // ------------------------------------------------------------------- - // -----[ EVENT ]----------------------------------------------------- - // ------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_context; i++) - if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) - { - // Write pc - context_state_t state = reg_STATE [i]; - - switch (state) - { - case CONTEXT_STATE_KO_EXCEP_ADDR : - { - reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; - break; - } - case CONTEXT_STATE_KO_MISS_ADDR : - case CONTEXT_STATE_KO_PSYNC_ADDR : - case CONTEXT_STATE_KO_CSYNC_ADDR : - { - reg_STATE [i] = CONTEXT_STATE_OK; - break; - } - default : - { + // ------------------------------------------------------------------- + // -----[ BRANCH_EVENT ]---------------------------------------------- + // ------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_context; ++i) + if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) + { +// throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); + + context_state_t state = reg_STATE [i]; + + Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): + 0; + Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; + Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; + Tdepth_t depth_max = _param->_array_size_depth [i]; + +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); + Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + + // priority : miss > excep > spr/sync + uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == EVENT_TYPE_EXCEPTION)?1:0); + uint8_t priority1 = 2; // miss + + // is_valid = can modify local information + // if context_state_ok : yes + // if context_state_ko : test the depth, and the priority of envent + + bool is_valid = ((state == CONTEXT_STATE_OK) or + (depth1< depth0) or + ((depth1==depth0) and (priority1>priority0))); + + if (is_valid) + { + reg_STATE [i] = CONTEXT_STATE_KO_MISS; + reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot + reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST[i]); // address_next + reg_EVENT_ADDRESS_EPCR_VAL [i] = 1; // address_dest is valid + //reg_EVENT_ADDRESS_EEAR [i] = 0; + reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; + reg_EVENT_IS_DELAY_SLOT [i] = 1; + reg_EVENT_IS_DS_TAKE [i] = 0;// ?? + reg_EVENT_DEPTH [i] = depth; + } + } + + // ------------------------------------------------------------------- + // -----[ DECOD_EVENT ]----------------------------------------------- + // ------------------------------------------------------------------- + + for (uint32_t i=0; i<_param->_nb_decod_unit; i++) + if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) + { + Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; + Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; + Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; + Tdepth_t depth_max = _param->_array_size_depth [context]; + +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); + Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + + context_state_t state = reg_STATE [context]; + Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]); + + // miss > excep > spr/sync + uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0; + + // is_valid = can modify local information + // if context_state_ok : yes + // if context_state_ko : test the depth, and the priority of envent + + bool is_valid = ((state == CONTEXT_STATE_OK) or + (depth1< depth0) or + ((depth1==depth0) and (priority1>priority0))); + + if (is_valid) + { + // decod : + // type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys) + context_state_t state_next = state; + Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]); + Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]); + + switch (type) + { + case EVENT_TYPE_EXCEPTION : + { + state_next = CONTEXT_STATE_KO_EXCEP; + + break; + } + case EVENT_TYPE_SPR_ACCESS : + { + state_next = CONTEXT_STATE_KO_SPR ; + address++; // take next address + if (is_delay_slot) + throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + break; + } + case EVENT_TYPE_MSYNC : + { + state_next = CONTEXT_STATE_KO_MSYNC; + address++; // take next address + if (is_delay_slot) + throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + break; + } + case EVENT_TYPE_PSYNC : + { + state_next = CONTEXT_STATE_KO_PSYNC; + address++; // take next address + if (is_delay_slot) + throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + break; + } + case EVENT_TYPE_CSYNC : + { + state_next = CONTEXT_STATE_KO_CSYNC; + address++; // take next address + if (is_delay_slot) + throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n"); + break; + } + case EVENT_TYPE_NONE : + case EVENT_TYPE_MISS_SPECULATION : + case EVENT_TYPE_BRANCH_NO_ACCURATE : + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str())); + } + } + + reg_STATE [context] = state_next; + reg_EVENT_ADDRESS [context] = address; + reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]); + reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; + //reg_EVENT_ADDRESS_EEAR [context] + reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; + reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot; + //reg_EVENT_IS_DS_TAKE [context] = 0; + reg_EVENT_DEPTH [context] = depth; + } + } + + // ------------------------------------------------------------------- + // -----[ COMMIT_EVENT ]---------------------------------------------- + // ------------------------------------------------------------------- + + if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) + { + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; + Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; + Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; + Tdepth_t depth_max = _param->_array_size_depth [context]; + +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); + Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + + context_state_t state = reg_STATE [context]; + Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE ); + + // miss > excep > spr/sync + uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority1 = 1; // exception + + // is_valid = can modify local information + // if context_state_ok : yes + // if context_state_ko : test the depth, and the priority of envent + + bool is_valid = ((state == CONTEXT_STATE_OK) or + (depth1< depth0) or + ((depth1==depth0) and (priority1>priority0))); + + if (is_valid) + { + // commit + // type : exception + context_state_t state_next = state; + switch (type) + { + case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;} + case EVENT_TYPE_SPR_ACCESS : + case EVENT_TYPE_MSYNC : + case EVENT_TYPE_PSYNC : + case EVENT_TYPE_CSYNC : + case EVENT_TYPE_NONE : + case EVENT_TYPE_MISS_SPECULATION : + case EVENT_TYPE_BRANCH_NO_ACCURATE : + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str())); + } + } + reg_STATE [context] = state_next; + reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS ); + reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR ); + reg_EVENT_ADDRESS_EPCR_VAL [context] = 1; + reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR ); + reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT ); + //reg_EVENT_IS_DS_TAKE [context] = 0; + reg_EVENT_DEPTH [context] = depth; + } + } + + // ------------------------------------------------------------------- + // -----[ BRANCH_COMPLETE ]------------------------------------------- + // ------------------------------------------------------------------- + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) + if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) + { + if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) + { + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; + Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; + Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; + Tdepth_t depth_max = _param->_array_size_depth [context]; + +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); + Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); + Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); + + context_state_t state = reg_STATE [context]; + + // miss > excep > spr/sync + uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); + uint8_t priority1 = 2; // miss + + // is_valid = can modify local information + // if context_state_ok : yes + // if context_state_ko : test the depth, and the priority of envent + + bool is_valid = ((state == CONTEXT_STATE_OK) or + (depth1< depth0) or + ((depth1==depth0) and (priority1>priority0))); + + if (is_valid) + { + // commit + Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); + reg_STATE [context] = CONTEXT_STATE_KO_MISS; + reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT + reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); + reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence + //reg_EVENT_ADDRESS_EEAR [context]; + reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; + reg_EVENT_IS_DELAY_SLOT [context] = take; + reg_EVENT_IS_DS_TAKE [context] = take; + reg_EVENT_DEPTH [context] = depth; + } + } + } + + // ------------------------------------------------------------------- + // -----[ EVENT ]----------------------------------------------------- + // ------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_context; i++) + if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) + { + // Write pc + context_state_t state = reg_STATE [i]; + + switch (state) + { + case CONTEXT_STATE_KO_EXCEP_ADDR : + { + reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR; + break; + } + case CONTEXT_STATE_KO_MISS_ADDR : + case CONTEXT_STATE_KO_PSYNC_ADDR : + case CONTEXT_STATE_KO_CSYNC_ADDR : + { + reg_STATE [i] = CONTEXT_STATE_OK; + break; + } + default : + { #ifdef DEBUG_TEST - throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); + throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); #endif - break; - } - } - } - - // ------------------------------------------------------------------- - // -----[ SPR ]------------------------------------------------------- - // ------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_context; i++) - if (internal_SPR_VAL [i] and PORT_READ(in_SPR_ACK [i])) - { - // Write spr + break; + } + } + } + + // ------------------------------------------------------------------- + // -----[ SPR_EVENT ]------------------------------------------------- + // ------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_context; i++) + if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) + { + // Write spr #ifdef DEBUG_TEST - context_state_t state = reg_STATE [i]; - - if (state != CONTEXT_STATE_KO_EXCEP_SPR) - throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str())); + context_state_t state = reg_STATE [i]; + + if (state != CONTEXT_STATE_KO_EXCEP_SPR) + throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str())); #endif - - reg_STATE [i] = CONTEXT_STATE_OK; - } - - // ------------------------------------------------------------------- - // -----[ next state ]------------------------------------------------ - // ------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_context; i++) - { - uint32_t x = _param->_link_context_to_decod_unit [i]; - uint32_t y = _param->_link_decod_unit_to_ooo_engine [x]; - - Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL [y]) + PORT_READ(in_NB_INST_DECOD_ALL [x]); - Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM [y]) + PORT_READ(in_NB_INST_DECOD_ALL [x]); - - context_state_t state = reg_STATE [i]; - - switch (state) - { - case CONTEXT_STATE_OK : - { - // nothing, wait an event - break; - } - case CONTEXT_STATE_KO_EXCEP : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_EXCEP_ADDR; - break; - } - case CONTEXT_STATE_KO_MISS : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_MISS_ADDR; - break; - } - case CONTEXT_STATE_KO_EXCEP_ADDR : - { - // nothing, wait the update of internal register (pc) - break; - } - case CONTEXT_STATE_KO_EXCEP_SPR : - { - // nothing, wait the update of internal register (epcr, eear, sr, esr) - break; - } - case CONTEXT_STATE_KO_MISS_ADDR : - { - // nothing, wait the update of internal register (pc) - break; - } - case CONTEXT_STATE_KO_PSYNC : - { - // Wait end of all instruction - if (inst_all == 0) -// state = CONTEXT_STATE_KO_PSYNC_FLUSH; - state = CONTEXT_STATE_KO_PSYNC_ADDR ; - break; - } -// case CONTEXT_STATE_KO_PSYNC_FLUSH : -// { -// // nothing, wait end of flush (ifetch) -// break; -// } - case CONTEXT_STATE_KO_PSYNC_ADDR : - { - // nothing, wait the pc write - break; - } - case CONTEXT_STATE_KO_CSYNC : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_CSYNC_ADDR ; -// state = CONTEXT_STATE_KO_CSYNC_FLUSH; - break; - } -// case CONTEXT_STATE_KO_CSYNC_FLUSH : -// { -// // nothing, wait end of flush (all internal structure) -// break; -// } - case CONTEXT_STATE_KO_CSYNC_ADDR : - { - // nothing, wait the pc write - break; - } - case CONTEXT_STATE_KO_MSYNC : - { - // Wait end of memory instruction - if (inst_mem == 0) - state = CONTEXT_STATE_KO_MSYNC_ISSUE; - break; - } - case CONTEXT_STATE_KO_MSYNC_ISSUE : - { - // Wait the msync issue - if (inst_mem != 0) - state = CONTEXT_STATE_KO_MSYNC_EXEC; - break; - } - case CONTEXT_STATE_KO_MSYNC_EXEC : - { - // Wait the end of msync - if (inst_mem == 0) - state = CONTEXT_STATE_OK; - break; - } - case CONTEXT_STATE_KO_SPR : - { - // Wait end of all instruction - if (inst_all == 0) - state = CONTEXT_STATE_KO_SPR_ISSUE; - break; - } - case CONTEXT_STATE_KO_SPR_ISSUE : - { - // Wait the spr_access issue - if (inst_all != 0) - state = CONTEXT_STATE_KO_SPR_EXEC; - break; - } - case CONTEXT_STATE_KO_SPR_EXEC : - { - // Wait the spr_access execution - if (inst_all == 0) - state = CONTEXT_STATE_OK; - break; - } - - default : - { - throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); - } - } - reg_STATE [i] = state; - } + + reg_STATE [i] = CONTEXT_STATE_OK; + } + + // ------------------------------------------------------------------- + // -----[ next state ]------------------------------------------------ + // ------------------------------------------------------------------- + for (uint32_t i=0; i<_param->_nb_context; i++) + { +// uint32_t x = _param->_link_context_to_decod_unit [i]; + + Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); + Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]); + + context_state_t state = reg_STATE [i]; + + switch (state) + { + case CONTEXT_STATE_OK : + { + // nothing, wait an event + break; + } + case CONTEXT_STATE_KO_EXCEP : + { + // Wait end of all instruction + if (inst_all == 0) + state = CONTEXT_STATE_KO_EXCEP_ADDR; + break; + } + case CONTEXT_STATE_KO_MISS : + { + // Wait end of all instruction + if (inst_all == 0) + state = CONTEXT_STATE_KO_MISS_ADDR; + break; + } + case CONTEXT_STATE_KO_EXCEP_ADDR : + { + // nothing, wait the update of internal register (pc) + break; + } + case CONTEXT_STATE_KO_EXCEP_SPR : + { + // nothing, wait the update of internal register (epcr, eear, sr, esr) + break; + } + case CONTEXT_STATE_KO_MISS_ADDR : + { + // nothing, wait the update of internal register (pc) + break; + } + case CONTEXT_STATE_KO_PSYNC : + { + // Wait end of all instruction + if (inst_all == 0) +// state = CONTEXT_STATE_KO_PSYNC_FLUSH; + state = CONTEXT_STATE_KO_PSYNC_ADDR ; + break; + } +// case CONTEXT_STATE_KO_PSYNC_FLUSH : +// { +// // nothing, wait end of flush (ifetch) +// break; +// } + case CONTEXT_STATE_KO_PSYNC_ADDR : + { + // nothing, wait the pc write + break; + } + case CONTEXT_STATE_KO_CSYNC : + { + // Wait end of all instruction + if (inst_all == 0) + state = CONTEXT_STATE_KO_CSYNC_ADDR ; +// state = CONTEXT_STATE_KO_CSYNC_FLUSH; + break; + } +// case CONTEXT_STATE_KO_CSYNC_FLUSH : +// { +// // nothing, wait end of flush (all internal structure) +// break; +// } + case CONTEXT_STATE_KO_CSYNC_ADDR : + { + // nothing, wait the pc write + break; + } + case CONTEXT_STATE_KO_MSYNC : + { + // Wait end of memory instruction + if (inst_mem == 0) + state = CONTEXT_STATE_KO_MSYNC_ISSUE; + break; + } + case CONTEXT_STATE_KO_MSYNC_ISSUE : + { + // Wait the msync issue + if (inst_mem != 0) + state = CONTEXT_STATE_KO_MSYNC_EXEC; + break; + } + case CONTEXT_STATE_KO_MSYNC_EXEC : + { + // Wait the end of msync + if (inst_mem == 0) + state = CONTEXT_STATE_OK; + break; + } + case CONTEXT_STATE_KO_SPR : + { + // Wait end of all instruction + if (inst_all == 0) + state = CONTEXT_STATE_KO_SPR_ISSUE; + break; + } + case CONTEXT_STATE_KO_SPR_ISSUE : + { + // Wait the spr_access issue + if (inst_all != 0) + state = CONTEXT_STATE_KO_SPR_EXEC; + break; + } + case CONTEXT_STATE_KO_SPR_EXEC : + { + // Wait the spr_access execution + if (inst_all == 0) + state = CONTEXT_STATE_OK; + break; + } + + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str())); + } + } + reg_STATE [i] = state; + } + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]); + + if (reg_INTERRUPT_ENABLE [i]) + throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i)); + } } @@ -431,14 +495,14 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - log_printf(TRACE,Context_State,FUNCTION,"Context State [%d]",i); - log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x",reg_EVENT_ADDRESS [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x",reg_EVENT_ADDRESS_EPCR [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x",reg_EVENT_ADDRESS_EEAR [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); - log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); + log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i); + log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str()); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]); + log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 88) @@ -21,12 +21,11 @@ Parameters::Parameters (uint32_t nb_context, uint32_t nb_decod_unit, - uint32_t nb_ooo_engine, uint32_t nb_inst_branch_complete, uint32_t * size_depth, uint32_t size_address, - uint32_t * size_inst_decod, - uint32_t * size_inst_commit, + uint32_t * size_nb_inst_decod, + uint32_t size_nb_inst_commit, uint32_t * link_context_to_decod_unit, - uint32_t * link_decod_unit_to_ooo_engine) + bool is_toplevel) { log_begin(Context_State,FUNCTION); @@ -34,23 +33,27 @@ _nb_context = nb_context ; _nb_decod_unit = nb_decod_unit ; - _nb_ooo_engine = nb_ooo_engine ; _nb_inst_branch_complete = nb_inst_branch_complete ; - _size_depth = size_depth ; - _size_address = size_address ; - _size_inst_decod = size_inst_decod ; - _size_inst_commit = size_inst_commit ; + _array_size_depth = size_depth ; +// _size_address = size_address ; +// _size_nb_inst_decod = size_nb_inst_decod ; +// _size_nb_inst_commit = size_nb_inst_commit ; _link_context_to_decod_unit = link_context_to_decod_unit ; - _link_decod_unit_to_ooo_engine = link_decod_unit_to_ooo_engine; + + test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context); + _size_depth = log2(max(size_depth,_nb_context)); + _size_instruction_address = size_address; + _size_nb_inst_decod = max(size_nb_inst_decod,_nb_decod_unit); + _size_nb_inst_commit = size_nb_inst_commit; + + _have_port_context_id = (_size_context_id>0); + _have_port_depth = (_size_depth > 0); + + copy (); + } - _size_context_id = log2(_nb_context); - _size_max_depth = max(_size_depth,_nb_context); - - _have_port_context_id = (_size_context_id>0); - _have_port_max_depth = (_size_max_depth >0); - _have_port_depth = new bool [_nb_context]; - for (uint32_t i=0; i<_nb_context; i++) - _have_port_depth [i] = (_size_depth [i] >0); - - test(); log_end(Context_State,FUNCTION); }; @@ -70,5 +73,12 @@ { log_begin(Context_State,FUNCTION); - delete [] _have_port_depth; + log_end(Context_State,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Context_State::copy" + void Parameters::copy (void) + { + log_begin(Context_State,FUNCTION); log_end(Context_State,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_msg_error.cpp (revision 88) @@ -41,20 +41,4 @@ test.error(toString(_("The decod_unit [%d] have none context as source."),i)); - bool _is_link_ooo_engine_from_decod_unit [_nb_ooo_engine]; - for (uint32_t i=0; i<_nb_ooo_engine; i++) - _is_link_ooo_engine_from_decod_unit [i] = false; - - for (uint32_t i=0; i<_nb_decod_unit; i++) - { - if (_link_decod_unit_to_ooo_engine [i] < _nb_ooo_engine) - _is_link_ooo_engine_from_decod_unit [_link_decod_unit_to_ooo_engine[i]] = true; - else - test.error(toString(_("The decod_unit [%d] is linked with invalid ooo_engine."),i)); - } - - for (uint32_t i=0; i<_nb_ooo_engine; i++) - if (_is_link_ooo_engine_from_decod_unit [i] == false) - test.error(toString(_("The ooo_engine [%d] have none decod_unit as source."),i)); - log_end(Context_State,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters_print.cpp (revision 88) @@ -27,8 +27,8 @@ xml.balise_open("context_state"); xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); - xml.singleton_begin("nb_decod_unit "); xml.attribut("value",toString(_nb_decod_unit )); xml.singleton_end(); - xml.singleton_begin("nb_ooo_engine "); xml.attribut("value",toString(_nb_ooo_engine )); xml.singleton_end(); +// xml.singleton_begin("nb_decod_unit "); xml.attribut("value",toString(_nb_decod_unit )); xml.singleton_end(); xml.singleton_begin("nb_inst_branch_complete "); xml.attribut("value",toString(_nb_inst_branch_complete )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_inst_commit "); xml.attribut("value",toString(_size_inst_commit )); xml.singleton_end(); for (uint32_t i=0;i<_nb_context; i++) @@ -38,5 +38,5 @@ xml. attribut("id" ,toString(i)); xml. balise_open_end(); - xml. singleton_begin("size_depth "); xml.attribut("value",toString(_size_depth [i])); xml.singleton_end(); +// xml. singleton_begin("size_depth "); xml.attribut("value",toString(_size_depth [i])); xml.singleton_end(); xml. singleton_begin("link_context_to_decod_unit "); xml.attribut("value",toString(_link_context_to_decod_unit [i])); xml.singleton_end(); xml. balise_close(); @@ -49,16 +49,5 @@ xml. attribut("id" ,toString(i)); xml. balise_open_end(); - xml. singleton_begin("size_inst_decod "); xml.attribut("value",toString(_size_inst_decod [i])); xml.singleton_end(); - xml. singleton_begin("link_decod_unit_to_ooo_engine"); xml.attribut("value",toString(_link_decod_unit_to_ooo_engine[i])); xml.singleton_end(); - xml. balise_close(); - } - - for (uint32_t i=0;i<_nb_ooo_engine; i++) - { - xml. balise_open_begin("component"); - xml. attribut("type","ooo_engine"); - xml. attribut("id" ,toString(i)); - xml. balise_open_end(); - xml. singleton_begin("size_inst_commit "); xml.attribut("value",toString(_size_inst_commit [i])); xml.singleton_end(); +// xml. singleton_begin("size_inst_decod "); xml.attribut("value",toString(_size_inst_decod [i])); xml.singleton_end(); xml. balise_close(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Types.h (revision 88) @@ -39,4 +39,5 @@ Ttype_t _type ; Toperation_t _operation ; + Tcontrol_t _no_execute ; Tcontrol_t _has_immediat ; Tgeneral_data_t _immediat ; @@ -52,4 +53,5 @@ Tspecial_address_t _num_reg_re ; Texception_t _exception_use ; + Texception_t _exception ; Tbranch_condition_t _branch_condition ; // Tcontrol_t _branch_stack_write; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 88) @@ -14,4 +14,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h" #include "Behavioural/include/Constants.h" +#include "Behavioural/include/Operation.h" namespace morpheo { @@ -124,4 +125,5 @@ inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION; + inst->_exception = EXCEPTION_ILLEGAL_INSTRUCTION; if (inst->_is_delay_slot) @@ -138,16 +140,16 @@ uint32_t opcod = range(inst->_instruction,31,26); - - inst->_type = TYPE_CUSTOM; + switch (opcod) { - case OPCOD_L_CUST1 : {inst->_operation = OPERATION_CUSTOM_L_1; break;} - case OPCOD_L_CUST2 : {inst->_operation = OPERATION_CUSTOM_L_2; break;} - case OPCOD_L_CUST3 : {inst->_operation = OPERATION_CUSTOM_L_3; break;} - case OPCOD_L_CUST4 : {inst->_operation = OPERATION_CUSTOM_L_4; break;} - case OPCOD_L_CUST5 : {inst->_operation = OPERATION_CUSTOM_L_5; break;} - case OPCOD_L_CUST6 : {inst->_operation = OPERATION_CUSTOM_L_6; break;} - case OPCOD_L_CUST7 : {inst->_operation = OPERATION_CUSTOM_L_7; break;} - case OPCOD_L_CUST8 : {inst->_operation = OPERATION_CUSTOM_L_8; break;} + case OPCOD_L_CUST1 : {inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation; break;} + case OPCOD_L_CUST2 : {inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation; break;} + case OPCOD_L_CUST3 : {inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation; break;} + case OPCOD_L_CUST4 : {inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation; break;} + case OPCOD_L_CUST5 : {inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation; break;} + case OPCOD_L_CUST6 : {inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation; break;} + case OPCOD_L_CUST7 : {inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation; break;} + case OPCOD_L_CUST8 : {inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation; break;} + default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));} } @@ -164,9 +166,8 @@ uint32_t opcod = range(inst->_instruction, 7, 0); - inst->_type = TYPE_CUSTOM; switch (opcod) { -// case OPCOD_LF_CUST1_D : {inst->_operation = OPERATION_CUSTOM_LF_1_D; break;} -// case OPCOD_LF_CUST1_S : {inst->_operation = OPERATION_CUSTOM_LF_1_S; break;} +// case OPCOD_LF_CUST1_D : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation; break;} +// case OPCOD_LF_CUST1_S : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation; break;} default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));} } @@ -183,11 +184,10 @@ uint32_t opcod = range(inst->_instruction, 7, 0); - inst->_type = TYPE_CUSTOM; switch (opcod) { -// case OPCOD_LV_CUST1 : {inst->_operation = OPERATION_CUSTOM_LV_1; break;} -// case OPCOD_LV_CUST2 : {inst->_operation = OPERATION_CUSTOM_LV_2; break;} -// case OPCOD_LV_CUST3 : {inst->_operation = OPERATION_CUSTOM_LV_3; break;} -// case OPCOD_LV_CUST4 : {inst->_operation = OPERATION_CUSTOM_LV_4; break;} +// case OPCOD_LV_CUST1 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation; break;} +// case OPCOD_LV_CUST2 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation; break;} +// case OPCOD_LV_CUST3 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation; break;} +// case OPCOD_LV_CUST4 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation; break;} default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));} } @@ -252,6 +252,6 @@ { log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_ADD; + inst->_type = instruction_information(INSTRUCTION_L_ADD)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 0; // inst->_immediat = ; @@ -267,8 +267,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -278,6 +280,6 @@ log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_ADD; + inst->_type = instruction_information(INSTRUCTION_L_ADDC)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 0; // inst->_immediat = ; @@ -293,8 +295,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -304,6 +308,6 @@ log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_ADD; + inst->_type = instruction_information(INSTRUCTION_L_ADDI)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -319,8 +323,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -330,6 +336,6 @@ log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_ADD; + inst->_type = instruction_information(INSTRUCTION_L_ADDIC)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -345,8 +351,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -356,23 +364,25 @@ log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_AND; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_AND)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -382,6 +392,6 @@ log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_AND; + inst->_type = instruction_information(INSTRUCTION_L_ANDI)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -397,8 +407,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -408,8 +420,9 @@ log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf"); - Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); - - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_L_TEST_F; + Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 + ); + + inst->_type = instruction_information(INSTRUCTION_L_BF)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F; inst->_has_immediat = 1; inst->_immediat = address_next; @@ -425,4 +438,5 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; inst->_branch_condition = BRANCH_CONDITION_FLAG_SET; // inst->_branch_stack_write = 0; @@ -430,4 +444,5 @@ inst->_branch_direction = range(inst->_instruction,25,25); inst->_address_next = address_next; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -437,8 +452,9 @@ log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf"); - Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); - - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_L_TEST_NF; + Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 + ); + + inst->_type = instruction_information(INSTRUCTION_L_BNF)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF; inst->_has_immediat = 1; inst->_immediat = address_next; @@ -454,8 +470,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET; // inst->_branch_stack_write = 0; inst->_branch_direction = range(inst->_instruction,25,25); inst->_address_next = address_next; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -465,6 +483,6 @@ log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov"); - inst->_type = TYPE_MOVE; - inst->_operation = OPERATION_MOVE_L_CMOV; + inst->_type = instruction_information(INSTRUCTION_L_CMOV)._type ; //TYPE_MOVE; + inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; inst->_has_immediat = 0; // inst->_immediat = ; @@ -480,8 +498,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -497,6 +517,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_CSYNC; + inst->_type = instruction_information(INSTRUCTION_L_CSYNC)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; inst->_has_immediat = 0; // inst->_immediat = ; @@ -512,8 +532,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_CSYNC; } @@ -533,6 +555,6 @@ log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div"); - inst->_type = TYPE_MUL_DIV; - inst->_operation = OPERATION_MUL_DIV_L_DIV; + inst->_type = instruction_information(INSTRUCTION_L_DIV)._type ; //TYPE_DIV; + inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; inst->_has_immediat = 0; // inst->_immediat = ; @@ -548,8 +570,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -559,6 +583,6 @@ log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu"); - inst->_type = TYPE_MUL_DIV; - inst->_operation = OPERATION_MUL_DIV_L_DIVU; + inst->_type = instruction_information(INSTRUCTION_L_DIVU)._type ; //TYPE_DIV; + inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -574,8 +598,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -585,6 +611,6 @@ log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_S; + inst->_type = instruction_information(INSTRUCTION_L_EXTBS)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S; inst->_has_immediat = 1; inst->_immediat = 8; @@ -600,8 +626,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -611,6 +639,6 @@ log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; + inst->_type = instruction_information(INSTRUCTION_L_EXTBZ)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; inst->_has_immediat = 1; inst->_immediat = 8; @@ -626,8 +654,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -637,6 +667,6 @@ log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_S; + inst->_type = instruction_information(INSTRUCTION_L_EXTHS)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S; inst->_has_immediat = 1; inst->_immediat = 16; @@ -652,8 +682,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -663,6 +695,6 @@ log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; + inst->_type = instruction_information(INSTRUCTION_L_EXTHZ)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; inst->_has_immediat = 1; inst->_immediat = 16; @@ -678,8 +710,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -689,6 +723,6 @@ log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_S; + inst->_type = instruction_information(INSTRUCTION_L_EXTWS)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S; inst->_has_immediat = 1; inst->_immediat = 32; @@ -704,8 +738,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -715,6 +751,6 @@ log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz"); - inst->_type = TYPE_EXTEND; - inst->_operation = OPERATION_EXTEND_L_EXTEND_Z; + inst->_type = instruction_information(INSTRUCTION_L_EXTWZ)._type ; //TYPE_EXTEND; + inst->_operation = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; inst->_has_immediat = 1; inst->_immediat = 32; @@ -730,8 +766,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -741,23 +779,25 @@ log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1"); - inst->_type = TYPE_FIND; - inst->_operation = OPERATION_FIND_L_FF1; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_FF1)._type ; //TYPE_FIND; + inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 0; +// inst->_num_reg_rb = ; + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -767,23 +807,25 @@ log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1"); - inst->_type = TYPE_FIND; - inst->_operation = OPERATION_FIND_L_FL1; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_FL1)._type ; //TYPE_FIND; + inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 0; +// inst->_num_reg_rb = ; + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -793,6 +835,6 @@ log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j"); - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_NONE; + inst->_type = instruction_information(INSTRUCTION_L_J)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; inst->_has_immediat = 0; // inst->_immediat = ; @@ -808,8 +850,11 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK; // inst->_branch_stack_write = 0; inst->_branch_direction = 1; - inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); + inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 + ); + inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; } @@ -819,6 +864,6 @@ log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal"); - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_L_JALR; + inst->_type = instruction_information(INSTRUCTION_L_JAL)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR; inst->_has_immediat = 1; inst->_immediat = inst->_address_next+1; @@ -834,8 +879,11 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump // inst->_branch_stack_write = 1; inst->_branch_direction = 1; - inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); + inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 + ); + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -853,6 +901,6 @@ else { - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_L_JALR; + inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; inst->_has_immediat = 0; // inst->_immediat = ; @@ -868,4 +916,5 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER; inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK; @@ -873,4 +922,5 @@ inst->_branch_direction = 1; // inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -881,6 +931,6 @@ log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr"); - inst->_type = TYPE_BRANCH; - inst->_operation = OPERATION_BRANCH_L_JALR; + inst->_type = instruction_information(INSTRUCTION_L_JR)._type ; //TYPE_BRANCH; + inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; inst->_has_immediat = 0; // inst->_immediat = ; @@ -896,8 +946,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK; // inst->_branch_stack_write = 0; inst->_branch_direction = 1; // inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -907,6 +959,6 @@ log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_8_S; + inst->_type = instruction_information(INSTRUCTION_L_LBS)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -922,8 +974,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -933,6 +987,6 @@ log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_8_Z; + inst->_type = instruction_information(INSTRUCTION_L_LBZ)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -948,8 +1002,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -959,6 +1015,6 @@ log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_64_S; + inst->_type = instruction_information(INSTRUCTION_L_LD)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -974,8 +1030,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -985,6 +1043,6 @@ log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_16_S; + inst->_type = instruction_information(INSTRUCTION_L_LHS)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1000,8 +1058,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1011,6 +1071,6 @@ log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_16_Z; + inst->_type = instruction_information(INSTRUCTION_L_LHZ)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1026,8 +1086,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1037,6 +1099,6 @@ log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_32_S; + inst->_type = instruction_information(INSTRUCTION_L_LWS)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1052,8 +1114,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1063,6 +1127,6 @@ log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_LOAD_32_Z; + inst->_type = instruction_information(INSTRUCTION_L_LWZ)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1078,8 +1142,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1089,23 +1155,25 @@ log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MAC; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; + inst->_type = instruction_information(INSTRUCTION_L_MAC)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 0; +// inst->_num_reg_rd = ; + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1115,6 +1183,6 @@ log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MAC; + inst->_type = instruction_information(INSTRUCTION_L_MACI)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC; inst->_has_immediat = 1; inst->_immediat = EXTENDS(((range(inst->_instruction,25,21)<<11)| @@ -1131,8 +1199,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1148,6 +1218,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MACRC; + inst->_type = instruction_information(INSTRUCTION_L_MACRC)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1163,8 +1233,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1175,6 +1247,6 @@ log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MFSPR; + inst->_type = instruction_information(INSTRUCTION_L_MFSPR)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -1190,8 +1262,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1201,6 +1275,6 @@ log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi"); - inst->_type = TYPE_MOVE; - inst->_operation = OPERATION_MOVE_L_MOVHI; + inst->_type = instruction_information(INSTRUCTION_L_MOVHI)._type ; //TYPE_MOVE; + inst->_operation = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -1216,8 +1290,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1227,23 +1303,25 @@ log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MSB; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; + inst->_type = instruction_information(INSTRUCTION_L_MSB)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 0; +// inst->_num_reg_rd = ; + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1259,6 +1337,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MSYNC; + inst->_type = instruction_information(INSTRUCTION_L_MSYNC)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1274,8 +1352,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_MSYNC; } @@ -1286,6 +1366,6 @@ log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_MTSPR; + inst->_type = instruction_information(INSTRUCTION_L_MTSPR)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(((range(inst->_instruction,25,21)<<11)| @@ -1302,8 +1382,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; } @@ -1313,6 +1395,6 @@ log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul"); - inst->_type = TYPE_MUL_DIV; - inst->_operation = OPERATION_MUL_DIV_L_MUL; + inst->_type = instruction_information(INSTRUCTION_L_MUL)._type ; //TYPE_MUL; + inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1328,8 +1410,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1339,6 +1423,6 @@ log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli"); - inst->_type = TYPE_MUL_DIV; - inst->_operation = OPERATION_MUL_DIV_L_MUL; + inst->_type = instruction_information(INSTRUCTION_L_MULI)._type ; //TYPE_MUL; + inst->_operation = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1354,8 +1438,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1365,6 +1451,6 @@ log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu"); - inst->_type = TYPE_MUL_DIV; - inst->_operation = OPERATION_MUL_DIV_L_MULU; + inst->_type = instruction_information(INSTRUCTION_L_MULU)._type ; //TYPE_MUL; + inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1380,8 +1466,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1391,6 +1479,6 @@ log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_NOP; + inst->_type = instruction_information(INSTRUCTION_L_NOP)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP; // inst->_has_immediat = 1; // inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -1408,8 +1496,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; } @@ -1419,23 +1509,25 @@ log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_OR; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_OR)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1445,6 +1537,6 @@ log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_OR; + inst->_type = instruction_information(INSTRUCTION_L_ORI)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -1460,8 +1552,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1477,6 +1571,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_PSYNC; + inst->_type = instruction_information(INSTRUCTION_L_PSYNC)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1492,8 +1586,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_PSYNC; } @@ -1504,6 +1600,6 @@ log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe"); - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_RFE; + inst->_type = instruction_information(INSTRUCTION_L_RFE)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1519,8 +1615,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; // inst->_branch_condition = ; // inst->_branch_stack_write = ; // inst->_branch_direction = ; // inst->_address_next = ; // don't change + inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage } @@ -1530,23 +1628,25 @@ log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_ROR; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_ROR)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1556,6 +1656,6 @@ log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_ROR; + inst->_type = instruction_information(INSTRUCTION_L_RORI)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR; inst->_has_immediat = 1; inst->_immediat = range(inst->_instruction, 5, 0); @@ -1571,8 +1671,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1582,6 +1684,6 @@ log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_STORE_8; + inst->_type = instruction_information(INSTRUCTION_L_SB)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8; inst->_has_immediat = 1; inst->_immediat = EXTENDS(((range(inst->_instruction,25,21)<<11)| @@ -1598,8 +1700,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1609,6 +1713,6 @@ log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_STORE_64; + inst->_type = instruction_information(INSTRUCTION_L_SD)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64; inst->_has_immediat = 1; inst->_immediat = EXTENDS(((range(inst->_instruction,25,21)<<11)| @@ -1625,8 +1729,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1636,6 +1742,6 @@ log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFEQ; + inst->_type = instruction_information(INSTRUCTION_L_SFEQ)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1651,8 +1757,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1662,6 +1770,6 @@ log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFEQ; + inst->_type = instruction_information(INSTRUCTION_L_SFEQI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1677,8 +1785,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1688,6 +1798,6 @@ log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGES; + inst->_type = instruction_information(INSTRUCTION_L_SFGES)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1703,8 +1813,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1714,6 +1826,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGES; + inst->_type = instruction_information(INSTRUCTION_L_SFGESI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1729,8 +1841,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1740,6 +1854,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGEU; + inst->_type = instruction_information(INSTRUCTION_L_SFGEU)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1755,8 +1869,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1766,6 +1882,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGEU; + inst->_type = instruction_information(INSTRUCTION_L_SFGEUI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1781,8 +1897,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1792,6 +1910,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGTS; + inst->_type = instruction_information(INSTRUCTION_L_SFGTS)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1807,8 +1925,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1818,6 +1938,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGTS; + inst->_type = instruction_information(INSTRUCTION_L_SFGTSI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1833,8 +1953,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1844,6 +1966,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGTU; + inst->_type = instruction_information(INSTRUCTION_L_SFGTU)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1859,8 +1981,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1870,6 +1994,6 @@ log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFGTU; + inst->_type = instruction_information(INSTRUCTION_L_SFGTUI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1885,8 +2009,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1896,6 +2022,6 @@ log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLES; + inst->_type = instruction_information(INSTRUCTION_L_SFLES)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1911,8 +2037,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1922,6 +2050,6 @@ log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLES; + inst->_type = instruction_information(INSTRUCTION_L_SFLESI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1937,8 +2065,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1948,6 +2078,6 @@ log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLEU; + inst->_type = instruction_information(INSTRUCTION_L_SFLEU)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -1963,8 +2093,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -1974,6 +2106,6 @@ log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLEU; + inst->_type = instruction_information(INSTRUCTION_L_SFLEUI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -1989,8 +2121,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2000,6 +2134,6 @@ log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLTS; + inst->_type = instruction_information(INSTRUCTION_L_SFLTS)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; inst->_has_immediat = 0; // inst->_immediat = ; @@ -2015,8 +2149,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2026,6 +2162,6 @@ log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLTS; + inst->_type = instruction_information(INSTRUCTION_L_SFLTSI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -2041,8 +2177,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2052,6 +2190,6 @@ log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLTU; + inst->_type = instruction_information(INSTRUCTION_L_SFLTU)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; inst->_has_immediat = 0; // inst->_immediat = ; @@ -2067,8 +2205,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2078,6 +2218,6 @@ log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFLTU; + inst->_type = instruction_information(INSTRUCTION_L_SFLTUI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -2093,8 +2233,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2104,6 +2246,6 @@ log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFNE; + inst->_type = instruction_information(INSTRUCTION_L_SFNE)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; inst->_has_immediat = 0; // inst->_immediat = ; @@ -2119,8 +2261,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2130,6 +2274,6 @@ log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei"); - inst->_type = TYPE_TEST; - inst->_operation = OPERATION_TEST_L_SFNE; + inst->_type = instruction_information(INSTRUCTION_L_SFNEI)._type ; //TYPE_TEST; + inst->_operation = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -2145,8 +2289,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_F; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2156,6 +2302,6 @@ log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_STORE_16; + inst->_type = instruction_information(INSTRUCTION_L_SH)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16; inst->_has_immediat = 1; inst->_immediat = EXTENDS(((range(inst->_instruction,25,21)<<11)| @@ -2172,8 +2318,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2183,23 +2331,25 @@ log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SLL; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_SLL)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2209,6 +2359,6 @@ log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SLL; + inst->_type = instruction_information(INSTRUCTION_L_SLLI)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL; inst->_has_immediat = 1; inst->_immediat = range(inst->_instruction, 5, 0); @@ -2224,8 +2374,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2235,23 +2387,25 @@ log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SRA; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_SRA)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2261,6 +2415,6 @@ log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SRA; + inst->_type = instruction_information(INSTRUCTION_L_SRAI)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA; inst->_has_immediat = 1; inst->_immediat = range(inst->_instruction, 5, 0); @@ -2276,8 +2430,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2287,23 +2443,25 @@ log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SRL; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_SRL)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2313,6 +2471,6 @@ log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli"); - inst->_type = TYPE_SHIFT; - inst->_operation = OPERATION_SHIFT_L_SRL; + inst->_type = instruction_information(INSTRUCTION_L_SRLI)._type ; //TYPE_SHIFT; + inst->_operation = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL; inst->_has_immediat = 1; inst->_immediat = range(inst->_instruction, 5, 0); @@ -2328,8 +2486,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2339,6 +2499,6 @@ log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_SUB; + inst->_type = instruction_information(INSTRUCTION_L_SUB)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; inst->_has_immediat = 0; // inst->_immediat = ; @@ -2354,8 +2514,10 @@ inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; inst->_exception_use = EXCEPTION_USE_RANGE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2365,6 +2527,6 @@ log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw"); - inst->_type = TYPE_MEMORY; - inst->_operation = OPERATION_MEMORY_STORE_32; + inst->_type = instruction_information(INSTRUCTION_L_SW)._type ; //TYPE_MEMORY; + inst->_operation = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32; inst->_has_immediat = 1; inst->_immediat = EXTENDS(((range(inst->_instruction,25,21)<<11)| @@ -2381,8 +2543,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2398,6 +2562,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_SYS; + inst->_type = instruction_information(INSTRUCTION_L_SYS)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS; // inst->_has_immediat = 1; // inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -2415,4 +2579,5 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_SYSCALL; + inst->_exception = EXCEPTION_SYSCALL; // inst->_branch_condition = ; // inst->_branch_stack_write = ; @@ -2426,4 +2591,5 @@ // inst->_address_next = ; // don't change + inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_EXCEPTION; } @@ -2440,6 +2606,6 @@ else { - inst->_type = TYPE_SPECIAL; - inst->_operation = OPERATION_SPECIAL_L_TRAP; + inst->_type = instruction_information(INSTRUCTION_L_TRAP)._type ; //TYPE_SPECIAL; + inst->_operation = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP; inst->_has_immediat = 1; inst->_immediat = EXTENDZ(inst->_instruction,16); @@ -2455,8 +2621,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_TRAP; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; } @@ -2467,23 +2635,25 @@ log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_XOR; - inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_type = instruction_information(INSTRUCTION_L_XOR)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; + inst->_has_immediat = 0; +// inst->_immediat = ; + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; +// inst->_num_reg_rc = ; + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; +// inst->_num_reg_re = ; + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } @@ -2493,6 +2663,6 @@ log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori"); - inst->_type = TYPE_ALU; - inst->_operation = OPERATION_ALU_L_XOR; + inst->_type = instruction_information(INSTRUCTION_L_XORI)._type ; //TYPE_ALU; + inst->_operation = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR; inst->_has_immediat = 1; inst->_immediat = EXTENDS(inst->_instruction,16); @@ -2508,8 +2678,10 @@ // inst->_num_reg_re = ; inst->_exception_use = EXCEPTION_USE_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; + inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Makefile.deps (revision 88) @@ -13,4 +13,7 @@ include $(DIR_MORPHEO)/Behavioural/Makefile.deps endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif ifndef Custom include $(DIR_MORPHEO)/Behavioural/Custom/Makefile.deps @@ -25,8 +28,10 @@ Decod_LIBRARY = -lDecod \ $(Custom_LIBRARY) \ + $(Priority_LIBRARY) \ $(Behavioural_LIBRARY) -Decod_DIR_LIBRARY = -L$(Decod_DIR)/lib \ +Decod_DIR_LIBRARY = -L$(Decod_DIR)/lib \ $(Custom_DIR_LIBRARY) \ + $(Priority_DIR_LIBRARY) \ $(Behavioural_DIR_LIBRARY) @@ -36,4 +41,5 @@ @\ $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ $(MAKE) Custom_library; \ $(MAKE) --directory=$(Decod_DIR) --makefile=Makefile; @@ -42,4 +48,5 @@ @\ $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ $(MAKE) Custom_library_clean; \ $(MAKE) --directory=$(Decod_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Decod_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_min.cfg (revision 88) @@ -1,8 +1,7 @@ Decod 1 1 *4 # nb_context -1 1 *4 # nb_inst_fetch [0] [nb_context] +1 1 *4 # nb_inst_fetch [0] [nb_context] 1 1 *4 # nb_inst_decod -1 1 *2 # nb_branch_speculated -0 0 +1 # size_branch_update_prediction +1 1 *2 # nb_branch_speculated [0] [nb_context] 1 1 *2 # nb_context_select 32 32 *2 # size_general_data Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_mono_context.cfg (revision 88) @@ -1,8 +1,7 @@ Decod 1 1 *4 # nb_context -4 16 *4 # nb_inst_fetch [0] [nb_context] -1 4 *4 # nb_inst_decod -1 1 *2 # nb_branch_speculated -0 2 +1 # size_branch_update_prediction +4 16 *4 # nb_inst_fetch [0] [nb_context] +1 4 *4 # nb_inst_decod +1 1 *2 # nb_branch_speculated [0] [nb_context] 1 1 *2 # nb_context_select 32 32 *2 # size_general_data Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/config_multi_context.cfg (revision 88) @@ -1,11 +1,13 @@ Decod 4 4 *4 # nb_context -1 1 *4 # nb_inst_fetch [0] [nb_context] -2 2 *4 # nb_inst_fetch [1] [nb_context] -4 4 *4 # nb_inst_fetch [2] [nb_context] -8 8 *4 # nb_inst_fetch [3] [nb_context] +1 1 *4 # nb_inst_fetch [0] [nb_context] +2 2 *4 # nb_inst_fetch [1] [nb_context] +4 4 *4 # nb_inst_fetch [2] [nb_context] +8 8 *4 # nb_inst_fetch [3] [nb_context] 1 8 *2 # nb_inst_decod -1 1 *2 # nb_branch_speculated -2 2 *2 # size_branch_update_prediction +1 1 *2 # nb_branch_speculated [0] [nb_context] +0 0 *2 # nb_branch_speculated [1] [nb_context] +1 1 *2 # nb_branch_speculated [2] [nb_context] +2 2 *2 # nb_branch_speculated [3] [nb_context] 1 4 *2 # nb_context_select 32 32 *2 # size_general_data Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 88) @@ -32,4 +32,5 @@ public : Ttype_t _type ; public : Toperation_t _operation ; + public : Tcontrol_t _no_execute ; public : Tcontrol_t _is_delay_slot ; public : Tcontrol_t _has_immediat ; @@ -46,4 +47,6 @@ public : Tspecial_address_t _num_reg_re ; public : Texception_t _exception_use ; + public : Texception_t _exception_ifetch ; + public : Texception_t _exception_decod ; public : Tevent_type_t _context_event_type ; @@ -64,4 +67,5 @@ Ttype_t type , Toperation_t operation , +// Tcontrol_t no_execute , Tcontrol_t is_delay_slot , Tcontrol_t has_immediat , @@ -78,4 +82,6 @@ Tspecial_address_t num_reg_re , Texception_t exception_use , +// Texception_t exception_ifetch , +// Texception_t exception_decod , Tevent_type_t context_event_type ) { @@ -110,4 +116,8 @@ _exception_use = exception_use ; _context_event_type = context_event_type ; + + _no_execute = 0 ; + _exception_ifetch = EXCEPTION_IFETCH_NONE ; + _exception_decod = EXCEPTION_DECOD_NONE ; } }; @@ -246,5 +256,5 @@ 0xe3caa309,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIV,false, + 0,TYPE_DIV,OPERATION_DIV_L_DIV,false, 0,0x0,1,10,1,20,0,0 ,1,30,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -265,5 +275,5 @@ 0xe3caa30a,x,y,z, BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0, - 0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIVU,true, + 0,TYPE_DIV,OPERATION_DIV_L_DIVU,true, 0,0x0,1,10,1,20,0,0 ,1,30,1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -622,5 +632,5 @@ 0xe3caa306,x,y,z, 0,0,0,0,0,0, - TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false, + TYPE_MUL,OPERATION_MUL_L_MUL,false, 0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -631,5 +641,5 @@ 0xb3ca03fa,x,y,z, 0,0,0,0,0,0, - TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false, + TYPE_MUL,OPERATION_MUL_L_MUL,false, 1,0x3fa, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -640,5 +650,5 @@ 0xb3cafc06,x,y,z, 0,0,0,0,0,0, - TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false, + TYPE_MUL,OPERATION_MUL_L_MUL,false, 1,0xfffffc06, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); @@ -649,5 +659,5 @@ 0xe3caa30b,x,y,z, 0,0,0,0,0,0, - TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MULU,false, + TYPE_MUL,OPERATION_MUL_L_MULU,false, 0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV, EXCEPTION_USE_RANGE,EVENT_TYPE_NONE)); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/main.cpp (revision 88) @@ -9,5 +9,5 @@ #include "Behavioural/Custom/include/Custom_example.h" -#define NB_PARAMS 8 +#define NB_PARAMS 6 void usage (int argc, char * argv[]) @@ -15,13 +15,12 @@ err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); - err (_(" * nb_context (uint32_t )\n")); - err (_(" * nb_inst_fetch [nb_context] (uint32_t )\n")); - err (_(" * nb_inst_decod (uint32_t )\n")); - err (_(" * nb_branch_speculated (uint32_t )\n")); - err (_(" * size_branch_update_prediction (uint32_t )\n")); - err (_(" * nb_context_select (uint32_t )\n")); - err (_(" * size_general_data (uint32_t )\n")); - err (_(" * priority (Tpriority_t )\n")); - err (_(" * load_balancing (Tload_balancing_t)\n")); + err (_(" * nb_context (uint32_t )\n")); + err (_(" * nb_inst_fetch [nb_context] (uint32_t )\n")); + err (_(" * nb_inst_decod (uint32_t )\n")); + err (_(" * nb_branch_speculated [nb_context] (uint32_t )\n")); + err (_(" * nb_context_select (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); exit (1); @@ -42,14 +41,21 @@ uint32_t _nb_context = fromString(argv[x++]); - if (argc != static_cast(2+NB_PARAMS+_nb_context)) + if (argc != static_cast(2+NB_PARAMS+2*_nb_context)) usage (argc, argv); - uint32_t * _nb_inst_fetch = new uint32_t [_nb_context]; + uint32_t * _nb_inst_fetch = new uint32_t [_nb_context]; for (uint32_t i=0;i<_nb_context; i++) _nb_inst_fetch [i] = fromString(argv[x++]); uint32_t _nb_inst_decod = fromString(argv[x++]); - uint32_t _nb_branch_speculated = fromString(argv[x++]); - uint32_t _size_branch_update_prediction= fromString(argv[x++]); + + uint32_t * _nb_branch_speculated = new uint32_t [_nb_context]; + for (uint32_t i=0;i<_nb_context; i++) + _nb_branch_speculated [i] = fromString(argv[x++]); + +// uint32_t * _size_branch_update_prediction= new uint32_t [_nb_context]; +// for (uint32_t i=0;i<_nb_context; i++) +// _size_branch_update_prediction[i] = fromString(argv[x++]); + uint32_t _nb_context_select = fromString(argv[x++]); uint32_t _size_general_data = fromString(argv[x++]); @@ -63,5 +69,5 @@ for (uint32_t j=0; jprint(1).c_str()); @@ -100,4 +107,7 @@ delete _nb_inst_fetch; delete _instruction_implemeted; + delete _nb_branch_speculated; +// delete _size_branch_update_prediction; + return (_return); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp (revision 88) @@ -22,6 +22,16 @@ #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Decod * _Decod = new Decod @@ -31,5 +41,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -42,7 +52,7 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); + ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context); @@ -51,4 +61,6 @@ ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); @@ -57,4 +69,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); @@ -72,4 +85,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod); @@ -89,4 +103,5 @@ ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); @@ -103,16 +118,23 @@ (*(_Decod->in_NRESET)) (*(in_NRESET)); - INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context); // INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); - if (_param->_have_port_inst_ifetch_ptr) - INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context); - if (_param->_have_port_branch_update_prediction_id) - INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; i++) + { + if (_param->_have_port_inst_ifetch_ptr) + INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); +// if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); + } + INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod); @@ -123,4 +145,5 @@ INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); @@ -138,4 +161,5 @@ INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod); @@ -144,5 +168,6 @@ INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); - if (_param->_have_port_branch_update_prediction_id) +// if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); @@ -153,10 +178,13 @@ // INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); - if (_param->_have_port_depth) - INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH ,_param->_nb_context); + for (uint32_t i=0; i<_param->_nb_context; i++) + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL ); INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK ); if (_param->_have_port_context_id) INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); @@ -236,4 +264,5 @@ if (_param->_have_port_inst_ifetch_ptr) in_IFETCH_INST_IFETCH_PTR [i]->write(0); + in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE); // Alignement @@ -336,5 +365,6 @@ TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0); TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state ); - if (_param->_have_port_branch_update_prediction_id) +// if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id); TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition ); @@ -358,4 +388,6 @@ if (_param->_have_port_context_id) TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context); + if (_param->_have_port_depth ) + TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth ); TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type); TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot); @@ -403,4 +435,5 @@ delete [] in_IFETCH_BRANCH_STATE ; delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; + delete [] in_IFETCH_EXCEPTION ; delete [] out_DECOD_VAL ; @@ -410,4 +443,5 @@ delete [] out_DECOD_TYPE ; delete [] out_DECOD_OPERATION ; + delete [] out_DECOD_NO_EXECUTE ; delete [] out_DECOD_IS_DELAY_SLOT ; delete [] out_DECOD_ADDRESS ; @@ -425,4 +459,5 @@ delete [] out_DECOD_NUM_REG_RE ; delete [] out_DECOD_EXCEPTION_USE ; + delete [] out_DECOD_EXCEPTION ; delete [] out_PREDICT_VAL ; @@ -445,4 +480,5 @@ delete in_CONTEXT_EVENT_ACK ; delete out_CONTEXT_EVENT_CONTEXT_ID ; + delete out_CONTEXT_EVENT_DEPTH ; delete out_CONTEXT_EVENT_TYPE ; delete out_CONTEXT_EVENT_IS_DELAY_SLOT ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h (revision 88) @@ -13,6 +13,4 @@ #endif -#include -#include #include "Common/include/ToString.h" #include "Common/include/Debug.h" @@ -29,4 +27,9 @@ #endif #include "Behavioural/include/Usage.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + +#include +#include namespace morpheo { @@ -75,5 +78,5 @@ public : SC_IN (Tbranch_state_t ) ** in_IFETCH_BRANCH_STATE ;//[nb_context] public : SC_IN (Tprediction_ptr_t ) ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context] - + public : SC_IN (Texception_t ) ** in_IFETCH_EXCEPTION ;//[nb_context] // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : SC_OUT(Tcontrol_t ) ** out_DECOD_VAL ;//[nb_inst_decod] @@ -83,4 +86,5 @@ public : SC_OUT(Ttype_t ) ** out_DECOD_TYPE ;//[nb_inst_decod] public : SC_OUT(Toperation_t ) ** out_DECOD_OPERATION ;//[nb_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] @@ -98,4 +102,5 @@ public : SC_OUT(Tspecial_address_t ) ** out_DECOD_NUM_REG_RE ;//[nb_inst_decod] public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION_USE ;//[nb_inst_decod] + public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION ;//[nb_inst_decod] // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -121,4 +126,5 @@ public : SC_IN (Tcontrol_t ) * in_CONTEXT_EVENT_ACK ; public : SC_OUT(Tcontext_t ) * out_CONTEXT_EVENT_CONTEXT_ID ; + public : SC_OUT(Tdepth_t ) * out_CONTEXT_EVENT_DEPTH ; public : SC_OUT(Tevent_type_t ) * out_CONTEXT_EVENT_TYPE ; public : SC_OUT(Tcontrol_t ) * out_CONTEXT_EVENT_IS_DELAY_SLOT ; @@ -127,7 +133,7 @@ // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority; // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : uint32_t reg_CONTEXT_PRIORITY; private : Tgeneral_data_t * reg_CONTEXT_ADDRESS_PREVIOUS ; //[nb_context] private : Tcontrol_t * reg_CONTEXT_IS_DELAY_SLOT ; //[nb_context] @@ -136,4 +142,5 @@ private : Tcontrol_t * internal_CONTEXT_IS_DELAY_SLOT ; //[nb_context] + private : Tcontrol_t * internal_DECOD_VAL ; //[nb_inst_decod] // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ private : decod_instruction_t * _decod_instruction; @@ -141,5 +148,4 @@ private : function_decod_t **** _function_decod ; //[nb_context][type][opcod] private : function_decod_t **** _function_custom ; //[nb_context][type][opcod] - private : std::list select; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Parameters.h (revision 88) @@ -29,24 +29,15 @@ public : uint32_t * _nb_inst_fetch ; //[nb_context] public : uint32_t _nb_inst_decod ; - public : uint32_t _size_general_data ; - public : uint32_t _nb_branch_speculated ; - public : uint32_t _size_branch_update_prediction; +//public : uint32_t _size_general_data ; + public : uint32_t * _nb_branch_speculated ; //[nb_context] +//public : uint32_t * _size_branch_update_prediction; //[nb_context] public : uint32_t _nb_context_select ; public : Tpriority_t _priority ; public : Tload_balancing_t _load_balancing ; public : bool ** _instruction_implemeted ; //[nb_context][nb_instruction] - public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t); + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); - public : uint32_t _max_nb_inst_fetch ; - - public : uint32_t _size_address_inst ; - public : uint32_t _size_context_id ; - public : uint32_t _size_depth ; - public : uint32_t _size_inst_ifetch_ptr ; - - public : bool _have_port_context_id ; - public : bool _have_port_depth ; - public : bool _have_port_branch_update_prediction_id; - public : bool _have_port_inst_ifetch_ptr ; + public : uint32_t _max_nb_inst_fetch; +//public : uint32_t _size_address_inst; //-----[ methods ]----------------------------------------------------------- @@ -55,15 +46,19 @@ uint32_t * nb_inst_fetch , uint32_t nb_inst_decod , + uint32_t * nb_branch_speculated , +// uint32_t * size_branch_update_prediction, + uint32_t nb_context_select , uint32_t size_general_data , - uint32_t nb_branch_speculated , - uint32_t size_branch_update_prediction, - uint32_t nb_context_select , Tpriority_t priority , Tload_balancing_t load_balancing , bool ** instruction_implemeted , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)); + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Types.h (revision 88) @@ -19,17 +19,4 @@ namespace decod { - class select_t - { - public : uint32_t _context ; - public : uint32_t _inst_fetch; - - public : select_t (uint32_t context, - uint32_t inst_fetch) - { - _context = context ; - _inst_fetch = inst_fetch; - } - }; - }; // end namespace decod Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Decod,FUNCTION,"Begin"); +#if DEBUG_Decod == true + log_printf(INFO,Decod,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Decod,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Decod,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Decod,FUNCTION,"Method - transition"); @@ -95,5 +101,5 @@ if (_param->_have_port_context_id) sensitive << (*(in_IFETCH_CONTEXT_ID [i])); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) sensitive << (*(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i])); if (_param->_have_port_depth) @@ -110,4 +116,5 @@ # ifdef SYSTEMCASS_SPECIFIC + /* // List dependency information @@ -162,8 +169,9 @@ } - if (_param->_have_port_depth) - { - for (uint32_t x=0; x<_param->_nb_context; x++) - { + for (uint32_t x=0; x<_param->_nb_context; x++) + { + if (_param->_have_port_depth[i]) + { + (*(out_DECOD_DEPTH [i])) (*(in_CONTEXT_DECOD_ENABLE [x])); (*(out_DECOD_DEPTH [i])) (*(in_CONTEXT_DEPTH [x])); @@ -402,5 +410,5 @@ if (_param->_have_port_context_id) (*(out_PREDICT_MATCH_INST_IFETCH_PTR [i])) (*(in_IFETCH_CONTEXT_ID [x])); - if (_param->_have_port_inst_ifetch_ptr) + if (_param->_have_port_inst_ifetch_ptr[i]) (*(out_PREDICT_MATCH_INST_IFETCH_PTR [i])) (*(in_IFETCH_INST_IFETCH_PTR [x])); for (uint32_t y=0; y<_param->_nb_inst_fetch [x]; y++) @@ -601,5 +609,5 @@ } } - + */ # endif @@ -617,5 +625,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 88) @@ -1,4 +1,4 @@ /* - * $Id$ + * $id: Decod_allocation.cpp 86 2008-05-14 17:08:56Z rosiere $ * * [ Description ] @@ -58,20 +58,21 @@ // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[alloc_interface_it1]); + ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[it1]); - _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); + _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); + _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); + _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); } { ALLOC1_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context); - ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_address_inst ); -// ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_address_inst ); - ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ); - ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); + ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address ); +// ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ); + ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); } @@ -86,6 +87,7 @@ ALLOC1_SIGNAL_OUT(out_DECOD_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_DECOD_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_address_inst ); + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -101,4 +103,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic); ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION_USE,"exception_use",Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); } @@ -109,14 +112,14 @@ ALLOC1_VALACK_OUT(out_PREDICT_VAL ,VAL); ALLOC1_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition ); -// ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE ,"branch_stack_write" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address_inst ); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address_inst ); -// ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition); +// ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE ,"branch_stack_write" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); +// ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); } @@ -136,12 +139,15 @@ ALLOC_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_address_inst); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_address_inst); - } - - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); + } + + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { reg_CONTEXT_ADDRESS_PREVIOUS = new Tgeneral_data_t [_param->_nb_context]; reg_CONTEXT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; @@ -150,4 +156,17 @@ internal_CONTEXT_ADDRESS_PREVIOUS = new Tgeneral_data_t [_param->_nb_context]; internal_CONTEXT_IS_DELAY_SLOT = new Tcontrol_t [_param->_nb_context]; + +#ifdef STATISTICS + internal_DECOD_VAL = new Tcontrol_t [_param->_nb_inst_decod]; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority = new generic::priority::Priority (_name+"_priority" , + _param->_priority , + _param->_load_balancing, + _param->_nb_context , + _param->_nb_inst_fetch , + _param->_nb_context_select); const uint32_t nb_opcod_type = 14; @@ -415,18 +434,18 @@ // if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_decod [i][ 2][OPCOD_LV_CUST4 ] = &(instruction_lv_custom); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_custom[i][ 0][OPCOD_L_CUST1 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_1 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_custom[i][ 0][OPCOD_L_CUST2 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_2 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_custom[i][ 0][OPCOD_L_CUST3 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_3 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_custom[i][ 0][OPCOD_L_CUST4 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_4 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_custom[i][ 0][OPCOD_L_CUST5 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_5 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_custom[i][ 0][OPCOD_L_CUST6 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_6 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_custom[i][ 0][OPCOD_L_CUST7 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_7 ); - if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_custom[i][ 0][OPCOD_L_CUST8 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_L_8 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LF_1_D); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LF_1_S); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_custom[i][ 2][OPCOD_LV_CUST1 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_1 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_custom[i][ 2][OPCOD_LV_CUST2 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_2 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_custom[i][ 2][OPCOD_LV_CUST3 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_3 ); -// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_custom[i][ 2][OPCOD_LV_CUST4 ] = _param->_get_custom_information(i)._get_custom_decod(OPERATION_CUSTOM_LV_4 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST1 ]) _function_custom[i][ 0][OPCOD_L_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_1 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST2 ]) _function_custom[i][ 0][OPCOD_L_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_2 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST3 ]) _function_custom[i][ 0][OPCOD_L_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_3 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST4 ]) _function_custom[i][ 0][OPCOD_L_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_4 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST5 ]) _function_custom[i][ 0][OPCOD_L_CUST5 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_5 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST6 ]) _function_custom[i][ 0][OPCOD_L_CUST6 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_6 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST7 ]) _function_custom[i][ 0][OPCOD_L_CUST7 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_7 ); + if (_param->_instruction_implemeted[i][INSTRUCTION_L_CUST8 ]) _function_custom[i][ 0][OPCOD_L_CUST8 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_L_8 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_D ]) _function_custom[i][ 1][OPCOD_LF_CUST1_D ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_D); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LF_CUST1_S ]) _function_custom[i][ 1][OPCOD_LF_CUST1_S ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LF_1_S); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST1 ]) _function_custom[i][ 2][OPCOD_LV_CUST1 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_1 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST2 ]) _function_custom[i][ 2][OPCOD_LV_CUST2 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_2 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST3 ]) _function_custom[i][ 2][OPCOD_LV_CUST3 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_3 ); +// if (_param->_instruction_implemeted[i][INSTRUCTION_LV_CUST4 ]) _function_custom[i][ 2][OPCOD_LV_CUST4 ] = _param->_get_custom_information()._get_custom_decod(OPERATION_CUSTOM_LV_4 ); } @@ -440,5 +459,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -27,78 +28,83 @@ delete in_CLOCK ; delete in_NRESET; + + DELETE2_SIGNAL( in_IFETCH_VAL , _param->_nb_context, _param->_nb_inst_fetch[it1],1); + DELETE2_SIGNAL(out_IFETCH_ACK , _param->_nb_context, _param->_nb_inst_fetch[it1],1); + DELETE2_SIGNAL( in_IFETCH_INSTRUCTION, _param->_nb_context, _param->_nb_inst_fetch[it1],_param->_size_instruction); + + DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID , _param->_nb_context,_param->_size_context_id ); + DELETE1_SIGNAL(in_IFETCH_ADDRESS , _param->_nb_context,_param->_size_instruction_address ); +// DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT , _param->_nb_context,_param->_size_instruction_address ); + DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR , _param->_nb_context,_param->_size_inst_ifetch_ptr ); + DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE , _param->_nb_context,_param->_size_branch_state ); + DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID, _param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(in_IFETCH_EXCEPTION , _param->_nb_context,_param->_size_exception_ifetch); - delete [] in_IFETCH_VAL ; - delete [] out_IFETCH_ACK ; - delete [] in_IFETCH_INSTRUCTION ; - if (_param->_have_port_context_id) - delete [] in_IFETCH_CONTEXT_ID ; - delete [] in_IFETCH_ADDRESS ; -// delete [] in_IFETCH_ADDRESS_NEXT ; - if (_param->_have_port_inst_ifetch_ptr) - delete [] in_IFETCH_INST_IFETCH_PTR ; - delete [] in_IFETCH_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) - delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; + DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id ); + DELETE1_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod,_param->_size_depth ); + DELETE1_SIGNAL(out_DECOD_TYPE ,_param->_nb_inst_decod,_param->_size_type ); + DELETE1_SIGNAL(out_DECOD_OPERATION ,_param->_nb_inst_decod,_param->_size_operation ); + DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod,_param->_size_general_data ); + DELETE1_SIGNAL(out_DECOD_READ_RA ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_READ_RB ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_READ_RC ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_DECOD_WRITE_RD ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_WRITE_RE ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_DECOD_EXCEPTION_USE,_param->_nb_inst_decod,_param->_size_exception_use ); + DELETE1_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_inst_decod,_param->_size_exception_decod ); - delete [] out_DECOD_VAL ; - delete [] in_DECOD_ACK ; - if (_param->_have_port_context_id) - delete [] out_DECOD_CONTEXT_ID ; - if (_param->_have_port_depth) - delete [] out_DECOD_DEPTH ; - delete [] out_DECOD_TYPE ; - delete [] out_DECOD_OPERATION ; - delete [] out_DECOD_IS_DELAY_SLOT ; - delete [] out_DECOD_ADDRESS ; - delete [] out_DECOD_HAS_IMMEDIAT ; - delete [] out_DECOD_IMMEDIAT ; - delete [] out_DECOD_READ_RA ; - delete [] out_DECOD_NUM_REG_RA ; - delete [] out_DECOD_READ_RB ; - delete [] out_DECOD_NUM_REG_RB ; - delete [] out_DECOD_READ_RC ; - delete [] out_DECOD_NUM_REG_RC ; - delete [] out_DECOD_WRITE_RD ; - delete [] out_DECOD_NUM_REG_RD ; - delete [] out_DECOD_WRITE_RE ; - delete [] out_DECOD_NUM_REG_RE ; - delete [] out_DECOD_EXCEPTION_USE ; + DELETE1_SIGNAL(out_PREDICT_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_PREDICT_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id ); + DELETE1_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod,_param->_size_branch_state ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); +// DELETE1_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_instruction_address ); +// DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); - delete [] out_PREDICT_VAL ; - delete [] in_PREDICT_ACK ; - if (_param->_have_port_context_id) - delete [] out_PREDICT_CONTEXT_ID ; - delete [] out_PREDICT_BRANCH_STATE ; - delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ; - if (_param->_have_port_branch_update_prediction_id) - delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID; - delete [] out_PREDICT_BRANCH_CONDITION ; -// delete [] out_PREDICT_BRANCH_STACK_WRITE ; - delete [] out_PREDICT_BRANCH_DIRECTION ; - delete [] out_PREDICT_ADDRESS_SRC ; - delete [] out_PREDICT_ADDRESS_DEST ; -// delete [] in_PREDICT_CAN_CONTINUE ; + DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE, _param->_nb_context,1); + DELETE1_SIGNAL(in_CONTEXT_DEPTH , _param->_nb_context,_param->_size_depth); - delete [] in_CONTEXT_DECOD_ENABLE ; - if (_param->_have_port_depth) - delete [] in_CONTEXT_DEPTH ; + DELETE_SIGNAL (out_CONTEXT_EVENT_VAL ,1); + DELETE_SIGNAL ( in_CONTEXT_EVENT_ACK ,1); + DELETE_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE_SIGNAL (out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); + DELETE_SIGNAL (out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); + DELETE_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT,1 ); + DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,_param->_size_instruction_address); + DELETE_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address); - delete out_CONTEXT_EVENT_VAL ; - delete in_CONTEXT_EVENT_ACK ; - if (_param->_have_port_context_id) - delete out_CONTEXT_EVENT_CONTEXT_ID ; - delete out_CONTEXT_EVENT_TYPE ; - delete out_CONTEXT_EVENT_IS_DELAY_SLOT ; - delete out_CONTEXT_EVENT_ADDRESS ; - delete out_CONTEXT_EVENT_ADDRESS_EPCR ; + + + delete reg_CONTEXT_ADDRESS_PREVIOUS ; + delete [] reg_CONTEXT_IS_DELAY_SLOT ; + + delete [] internal_CONTEXT_HAVE_TRANSACTION ; + delete [] internal_CONTEXT_ADDRESS_PREVIOUS ; + delete [] internal_CONTEXT_IS_DELAY_SLOT ; + +#ifdef STATISTICS + delete [] internal_DECOD_VAL; +#endif } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete reg_CONTEXT_ADDRESS_PREVIOUS ; - delete reg_CONTEXT_IS_DELAY_SLOT ; + delete _priority; - delete internal_CONTEXT_HAVE_TRANSACTION ; - delete internal_CONTEXT_ADDRESS_PREVIOUS ; - delete internal_CONTEXT_IS_DELAY_SLOT ; const uint32_t nb_opcod_type = 14; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp (revision 88) @@ -22,5 +22,6 @@ void Decod::genMealy (void) { - log_printf(TRACE,Decod,FUNCTION,"Begin"); + log_begin(Decod,FUNCTION); + log_function(Decod,FUNCTION,_name.c_str()); //----------------------------------- @@ -38,4 +39,5 @@ { decod_val [i] = false; + predict_val [i] = false; } @@ -57,18 +59,16 @@ //----------------------------------- // scan all decod "slot_out" - log_printf(TRACE,Decod,FUNCTION,"KANE LIVE"); - std::list::iterator it=select.begin(); + std::list * select = _priority->select(); + std::list::iterator it=select->begin(); for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { - while ((it != select.end()) and // have a no scanned "slot_in" ? + while ((it != select->end()) and // have a no scanned "slot_in" ? (decod_val [i] == false) and // have not a previous selected entry? (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) { - log_printf(TRACE,Decod,FUNCTION,"loop"); - predict_val [i] = false; - Tcontext_t x = it->_context ; - uint32_t y = it->_inst_fetch; + Tcontext_t x = it->grp; + uint32_t y = it->elt; // Test if this instruction is valid @@ -76,5 +76,7 @@ (can_continue [x] == 1)) // context can decod instruction (have not a previous event) { - can_continue [x] = can_continue_next [x]; + log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y); + + can_continue [x] = can_continue_next [x]; decod_val [i] = true; // fetch_val and decod_enable @@ -90,21 +92,47 @@ _decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x]; - // Decod ! - log_printf(TRACE,Decod,FUNCTION,"DECOD [%d]",i); - log_printf(TRACE,Decod,FUNCTION," * context : %d",x); - log_printf(TRACE,Decod,FUNCTION," * fetch : %d",y); - log_printf(TRACE,Decod,FUNCTION," * address : %.8x",addr); - log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); - - instruction_decod (_decod_instruction, _decod_param[x]); - - Ttype_t type = _decod_instruction->_type; + // Test IFetch exception + Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x]); + + if (ifetch_exception == EXCEPTION_IFETCH_NONE) + { + // Decod ! + log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i); + log_printf(TRACE,Decod,FUNCTION," * context : %d",x); + log_printf(TRACE,Decod,FUNCTION," * fetch : %d",y); + log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2)); + log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); + + instruction_decod (_decod_instruction, _decod_param[x]); + } + else + { + // No decod : nop + instruction_l_nop (_decod_instruction, _decod_param[x]); + + _decod_instruction->_exception_use = EXCEPTION_USE_NONE; + _decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception); + + // INSTRUCTION_TLB + // INSTRUCTION_PAGE + // BUS_ERROR + if (_decod_instruction->_is_delay_slot) + _decod_instruction->_address_next = _decod_instruction->_address_previous; + else + _decod_instruction->_address_next = _decod_instruction->_address; + + _decod_instruction->_event_type = EVENT_TYPE_EXCEPTION; + } + + Ttype_t type = _decod_instruction->_type; + Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT if (_param->_have_port_context_id) PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); if (_param->_have_port_depth) - PORT_WRITE(out_DECOD_DEPTH [i], PORT_READ(in_CONTEXT_DEPTH [x])); + PORT_WRITE(out_DECOD_DEPTH [i], depth); PORT_WRITE(out_DECOD_TYPE [i], type); PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); + PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute ); PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); PORT_WRITE(out_DECOD_ADDRESS [i], addr); @@ -122,8 +150,11 @@ PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re ); PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use ); +// PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception ); if (type == TYPE_BRANCH) { - log_printf(TRACE,Decod,FUNCTION," * type is branch"); + log_printf(TRACE,Decod,FUNCTION," * type is branch"); + log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2); + log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2); predict_val [i] = ifetch_ack [x][y] // and decod_val [i] @@ -136,6 +167,6 @@ PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); - if (_param->_have_port_branch_update_prediction_id) - PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); + if (_param->_have_port_depth) + PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); @@ -145,5 +176,5 @@ //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) - can_continue_next [x] = false; // one branch per context + can_continue_next [x] = false; // one branch per context, the DS don't execute } @@ -160,4 +191,6 @@ if (_param->_have_port_context_id) PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , x); + if (_param->_have_port_depth) + PORT_WRITE(out_CONTEXT_EVENT_DEPTH , depth); PORT_WRITE(out_CONTEXT_EVENT_TYPE , _decod_instruction->_event_type ); PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot ); @@ -184,9 +217,9 @@ } - log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y); - log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]); - log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val ); - log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] ); - log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] ); + log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y); + log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]); + log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val ); + log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] ); + log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] ); it ++; @@ -207,7 +240,11 @@ PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]); PORT_WRITE(out_DECOD_VAL [i], decod_val [i]); - } - - log_printf(FUNC,Decod,FUNCTION,"End"); + +#ifdef STATISTICS + internal_DECOD_VAL [i] = decod_val [i]; +#endif + } + + log_end(Decod,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_statistics_allocation.cpp (revision 88) @@ -27,11 +27,12 @@ "Decod", param_statistics); - - _stat_sum_inst_decod = _stat->create_variable ("sum_inst_decod" // ,"", "Sum of decod instruction" - ); + _stat_sum_inst_decod = _stat->create_variable("sum_inst_decod"); + + + _stat->create_expr_average_by_cycle ("average_nb_inst_decod","sum_inst_decod","","Average of decod instruction by cycle"); + _stat->create_expr_percent ("percent_nb_inst_decod","average_nb_inst_decod", toString(_param->_nb_inst_decod), "Percent of decod instruction by cycle"); + - _stat->create_expr_average_by_cycle ("average_sum_inst_decod","sum_inst_decod","","Average of decod instruction by cycle"); - _stat->create_expr_percent ("percent_sum_inst_decod","average_sum_inst_decod", toString(_param->_nb_inst_decod), "Percent of decod instruction by cycle"); log_printf(FUNC,Decod,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_transition.cpp (revision 88) @@ -22,9 +22,9 @@ void Decod::transition (void) { - log_printf(FUNC,Decod,FUNCTION,"Begin"); + log_begin(Decod,FUNCTION); if (PORT_READ(in_NRESET) == 0) { - reg_CONTEXT_PRIORITY = 0; + _priority->reset(); for (uint32_t i=0; i<_param->_nb_context; i++) @@ -36,60 +36,5 @@ else { - switch (_param->_priority) - { -// case PRIORITY_STATIC : -// { -// reg_CONTEXT_PRIORITY = (reg_CONTEXT_PRIORITY+_param->_nb_context_select)%_param->_nb_context; -// break; -// } - case PRIORITY_ROUND_ROBIN : - { - reg_CONTEXT_PRIORITY = (reg_CONTEXT_PRIORITY+1 )%_param->_nb_context; - break; - } - default: - { - break; - } - } - - // flush list - select.clear(); - - // Compute next scan order !!! - switch (_param->_load_balancing) - { -// case LOAD_BALANCING_BALANCE : -// { -// for (uint32_t j=0; j<_param->_max_nb_inst_fetch; j++) -// for (uint32_t i=0; i<_param->_nb_context_select; i++) -// { -// uint32_t x=(reg_CONTEXT_PRIORITY+i)%_param->_nb_context; - -// // Test valid inst_fetch -// if (j < _param->_nb_inst_fetch[x]) -// select.push_back(select_t(x,j)); -// } - -// break; -// } - case LOAD_BALANCING_MAXIMUM_FOR_PRIORITY : - { - - for (uint32_t i=0; i<_param->_nb_context_select; i++) - { - uint32_t x=(reg_CONTEXT_PRIORITY+i)%_param->_nb_context; - - for (uint32_t j=0; j<_param->_nb_inst_fetch[x]; j++) - select.push_back(select_t(x,j)); - } - - break; - } - default : - { - break; - } - } + _priority->transition(); // Compute "next previous" address @@ -97,8 +42,4 @@ if (internal_CONTEXT_HAVE_TRANSACTION[i]) { -#ifdef STATISTICS - (*_stat_sum_inst_decod) ++; -#endif - reg_CONTEXT_ADDRESS_PREVIOUS [i] = internal_CONTEXT_ADDRESS_PREVIOUS [i]; reg_CONTEXT_IS_DELAY_SLOT [i] = internal_CONTEXT_IS_DELAY_SLOT [i]; @@ -107,4 +48,11 @@ // for (uint32_t i=0; i<_param->_nb_context; i++) // log_printf(TRACE,Decod,FUNCTION,"[%d] %.8x %d",i,reg_CONTEXT_ADDRESS_PREVIOUS [i], reg_CONTEXT_IS_DELAY_SLOT [i]); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_inst_decod; i++) + if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) + (*_stat_sum_inst_decod) ++; +#endif } @@ -113,5 +61,5 @@ #endif - log_printf(FUNC,Decod,FUNCTION,"End"); + log_end(Decod,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters.cpp (revision 88) @@ -1,4 +1,3 @@ /* - * $Id$ * @@ -24,6 +23,6 @@ uint32_t * nb_inst_fetch , uint32_t nb_inst_decod , - uint32_t nb_branch_speculated , - uint32_t size_branch_update_prediction, + uint32_t * nb_branch_speculated , +// uint32_t * size_branch_update_prediction, uint32_t nb_context_select , uint32_t size_general_data , @@ -31,5 +30,7 @@ Tload_balancing_t load_balancing , bool ** instruction_implemeted , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)) + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel + ) { log_printf(FUNC,Decod,FUNCTION,"Begin"); @@ -40,6 +41,6 @@ _nb_branch_speculated = nb_branch_speculated ; _nb_context_select = nb_context_select ; - _size_branch_update_prediction = size_branch_update_prediction; - _size_general_data = size_general_data ; +// _size_branch_update_prediction = size_branch_update_prediction; +// _size_general_data = size_general_data ; _priority = priority ; _load_balancing = load_balancing ; @@ -52,17 +53,27 @@ - _max_nb_inst_fetch = max(nb_inst_fetch,nb_context); + _max_nb_inst_fetch = max(nb_inst_fetch,nb_context); + +// _size_address_inst = size_general_data-2; - _size_address_inst = size_general_data-2; - _size_context_id = log2(nb_context ); - _size_depth = log2(nb_branch_speculated); - _size_inst_ifetch_ptr = log2(_max_nb_inst_fetch ); + test(); - _have_port_context_id = _size_context_id > 0; - _have_port_depth = _size_depth > 0; - _have_port_branch_update_prediction_id = _size_branch_update_prediction > 0; - _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; - - test(); + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_depth = log2(max(_nb_branch_speculated,_nb_context)); +// _size_branch_update_prediction_id = max(_size_branch_update_prediction,_nb_context); + _size_inst_ifetch_ptr = log2(_max_nb_inst_fetch ); + _size_instruction_address = size_general_data-2; + _size_general_data = size_general_data; + + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; +// _have_port_branch_update_prediction_id= _size_branch_update_prediction_id > 0; + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + + copy (); + } + log_printf(FUNC,Decod,FUNCTION,"End"); }; @@ -82,4 +93,14 @@ { log_printf(FUNC,Decod,FUNCTION,"Begin"); + + log_printf(FUNC,Decod,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Decod::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Decod,FUNCTION,"Begin"); + log_printf(FUNC,Decod,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_msg_error.cpp (revision 88) @@ -31,11 +31,11 @@ test.error(_("nb_inst_decod must be > 0.\n")); - if ((_size_general_data != 32) and - (_size_general_data != 64)) - test.error(_("size_general_data must be equal at 32 or 64 bits.\n")); +// if ((_size_general_data != 32) and +// (_size_general_data != 64)) +// test.error(_("size_general_data must be equal at 32 or 64 bits.\n")); - if ((_nb_branch_speculated == 0) or - (_nb_branch_speculated > _nb_context)) - test.error(_("nb_branch_speculated must be in [1:nb_context].\n")); +// if ((_nb_branch_speculated == 0) or +// (_nb_branch_speculated > _nb_context)) +// test.error(_("nb_branch_speculated must be in [1:nb_context].\n")); if ((_nb_context_select == 0) or @@ -48,5 +48,5 @@ if (sum_inst_fetch < _nb_inst_decod) - test.error(_("The sum of the _nb_context_select most nb_inst_fetch must be greater that _nb_inst_decod")); + test.error(_("The sum of the _nb_context_select most nb_inst_fetch must be greater that _nb_inst_decod\n")); if ((_priority != PRIORITY_ROUND_ROBIN)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Parameters_print.cpp (revision 88) @@ -30,5 +30,5 @@ xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); xml.singleton_begin("nb_branch_speculated "); xml.attribut("value",toString(_nb_branch_speculated )); xml.singleton_end(); - xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); +// xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); xml.singleton_begin("nb_context_select "); xml.attribut("value",toString(_nb_context_select )); xml.singleton_end(); xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Decod_queue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/main.cpp (revision 88) @@ -55,5 +55,7 @@ _size_queue , _size_general_data, - _nb_branch_speculated); + _nb_branch_speculated, + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/SelfTest/src/test.cpp (revision 88) @@ -58,4 +58,5 @@ ALLOC1_SC_SIGNAL( in_DECOD_IN_TYPE ," in_DECOD_IN_TYPE ",Ttype_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_OPERATION ," in_DECOD_IN_OPERATION ",Toperation_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ," in_DECOD_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ," in_DECOD_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_ADDRESS ," in_DECOD_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); @@ -73,4 +74,5 @@ ALLOC1_SC_SIGNAL( in_DECOD_IN_NUM_REG_RE ," in_DECOD_IN_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_IN_EXCEPTION_USE ," in_DECOD_IN_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL( in_DECOD_IN_EXCEPTION ," in_DECOD_IN_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_VAL ,"out_DECOD_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); @@ -80,4 +82,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_OUT_TYPE ,"out_DECOD_OUT_TYPE ",Ttype_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_OPERATION ,"out_DECOD_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,"out_DECOD_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,"out_DECOD_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,"out_DECOD_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); @@ -95,7 +98,8 @@ ALLOC1_SC_SIGNAL(out_DECOD_OUT_NUM_REG_RE ,"out_DECOD_OUT_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OUT_EXCEPTION_USE ,"out_DECOD_OUT_EXCEPTION_USE",Texception_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_OUT_EXCEPTION ,"out_DECOD_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); - ALLOC1_SC_SIGNAL( in_DEPTH_TAIL ," in_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_DEPTH_NB_BRANCH ," in_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_NB_INST_ALL ,"out_NB_INST_ALL ",Tcounter_t ,_param->_nb_context); @@ -118,4 +122,5 @@ INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_TYPE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_OPERATION ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); @@ -133,5 +138,6 @@ INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_NUM_REG_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_EXCEPTION_USE ,_param->_nb_inst_decod); - + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_IN_EXCEPTION ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue, in_DECOD_OUT_ACK ,_param->_nb_inst_decod); @@ -142,4 +148,5 @@ INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_TYPE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_OPERATION ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); @@ -157,10 +164,10 @@ INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_NUM_REG_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_EXCEPTION_USE ,_param->_nb_inst_decod); - - if (_param->_have_port_depth) - { - INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_TAIL ,_param->_nb_context); - INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_NB_BRANCH ,_param->_nb_context); - } + INSTANCE1_SC_SIGNAL(_Decod_queue,out_DECOD_OUT_EXCEPTION ,_param->_nb_inst_decod); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Decod_queue, in_DEPTH_MIN [i]); + INSTANCE1_SC_SIGNAL(_Decod_queue, in_DEPTH_MAX ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_queue,out_NB_INST_ALL ,_param->_nb_context); @@ -293,4 +300,5 @@ DELETE1_SC_SIGNAL( in_DECOD_IN_TYPE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_OPERATION ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod); @@ -308,4 +316,5 @@ DELETE1_SC_SIGNAL( in_DECOD_IN_NUM_REG_RE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL( in_DECOD_IN_EXCEPTION_USE ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_IN_EXCEPTION ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_VAL ,_param->_nb_inst_decod); @@ -315,4 +324,5 @@ DELETE1_SC_SIGNAL(out_DECOD_OUT_TYPE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_OPERATION ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod); @@ -330,7 +340,8 @@ DELETE1_SC_SIGNAL(out_DECOD_OUT_NUM_REG_RE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OUT_EXCEPTION_USE ,_param->_nb_inst_decod); - - DELETE1_SC_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context); - DELETE1_SC_SIGNAL( in_DEPTH_NB_BRANCH ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DECOD_OUT_EXCEPTION ,_param->_nb_inst_decod); + + DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context); DELETE1_SC_SIGNAL(out_NB_INST_ALL ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h (revision 88) @@ -54,4 +54,5 @@ public : Stat * _stat; private : counter_t ** _stat_nb_inst; + private : counter_t * _stat_use_queue; #endif @@ -72,4 +73,5 @@ public : SC_IN (Ttype_t ) ** in_DECOD_IN_TYPE ;//[nb_inst_decod] public : SC_IN (Toperation_t ) ** in_DECOD_IN_OPERATION ;//[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_NO_EXECUTE ;//[nb_inst_decod] public : SC_IN (Tcontrol_t ) ** in_DECOD_IN_IS_DELAY_SLOT ;//[nb_inst_decod] public : SC_IN (Tgeneral_data_t ) ** in_DECOD_IN_ADDRESS ;//[nb_inst_decod] @@ -87,4 +89,5 @@ public : SC_IN (Tspecial_address_t ) ** in_DECOD_IN_NUM_REG_RE ;//[nb_inst_decod] public : SC_IN (Texception_t ) ** in_DECOD_IN_EXCEPTION_USE ;//[nb_inst_decod] + public : SC_IN (Texception_t ) ** in_DECOD_IN_EXCEPTION ;//[nb_inst_decod] // ~~~~~[ Interface : "decod_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -95,4 +98,5 @@ public : SC_OUT(Ttype_t ) ** out_DECOD_OUT_TYPE ;//[nb_inst_decod] public : SC_OUT(Toperation_t ) ** out_DECOD_OUT_OPERATION ;//[nb_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_OUT_IS_DELAY_SLOT ;//[nb_inst_decod] public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_OUT_ADDRESS ;//[nb_inst_decod] @@ -110,8 +114,9 @@ public : SC_OUT(Tspecial_address_t ) ** out_DECOD_OUT_NUM_REG_RE ;//[nb_inst_decod] public : SC_OUT(Texception_t ) ** out_DECOD_OUT_EXCEPTION_USE ;//[nb_inst_decod] + public : SC_OUT(Texception_t ) ** out_DECOD_OUT_EXCEPTION ;//[nb_inst_decod] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tdepth_t ) ** in_DEPTH_TAIL ;//[nb_context] - public : SC_IN (Tdepth_t ) ** in_DEPTH_NB_BRANCH ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_MIN ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_MAX ;//[nb_context] // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Parameters.h (revision 88) @@ -27,16 +27,9 @@ public : uint32_t _nb_inst_decod ; public : uint32_t _size_queue ; - public : uint32_t _size_general_data ; +//public : uint32_t _size_general_data ; public : uint32_t * _nb_branch_speculated ; //[nb_context] public : uint32_t _nb_bank ; public : uint32_t _size_bank ; - - public : uint32_t _size_context_id ; - public : uint32_t _size_depth ; - public : uint32_t _size_nb_inst ; - - public : bool _have_port_context_id ; - public : bool _have_port_depth ; //-----[ methods ]----------------------------------------------------------- @@ -45,7 +38,10 @@ uint32_t size_queue , uint32_t size_general_data , - uint32_t * nb_branch_speculated); + uint32_t * nb_branch_speculated, + bool is_toplevel=false ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Types.h (revision 88) @@ -28,4 +28,5 @@ public : Ttype_t * _type ; public : Toperation_t * _operation ; + public : Tcontrol_t * _no_execute ; public : Tcontrol_t * _is_delay_slot ; public : Tgeneral_data_t * _address ; @@ -43,4 +44,5 @@ public : Tspecial_address_t * _num_reg_re ; public : Texception_t * _exception_use ; + public : Texception_t * _exception ; public : decod_queue_entry_t (uint32_t nb_inst): @@ -52,4 +54,5 @@ _type = new Ttype_t [_nb_inst]; _operation = new Toperation_t [_nb_inst]; + _no_execute = new Tcontrol_t [_nb_inst]; _is_delay_slot = new Tcontrol_t [_nb_inst]; _address = new Tgeneral_data_t [_nb_inst]; @@ -67,4 +70,5 @@ _num_reg_re = new Tspecial_address_t [_nb_inst]; _exception_use = new Texception_t [_nb_inst]; + _exception = new Texception_t [_nb_inst]; for (uint32_t i=0; i<_nb_inst; i++) @@ -79,4 +83,5 @@ delete [] _type ; delete [] _operation ; + delete [] _no_execute ; delete [] _is_delay_slot ; delete [] _address ; @@ -94,4 +99,5 @@ delete [] _num_reg_re ; delete [] _exception_use ; + delete [] _exception ; } }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue.cpp (revision 88) @@ -39,4 +39,10 @@ usage_environment(_usage); + +#if DEBUG_Decod_queue == true + log_printf(INFO,Decod_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif log_printf(INFO,Decod_queue,FUNCTION,_("Allocation")); @@ -98,8 +104,10 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) sensitive << (*(in_DECOD_OUT_ACK [i])); - if (_param->_have_port_depth) for (uint32_t i=0; i<_param->_nb_context; i++) - sensitive << (*(in_DEPTH_TAIL [i])) - << (*(in_DEPTH_NB_BRANCH [i])); + { + if (_param->_have_port_depth) + sensitive << (*(in_DEPTH_MIN [i])); + sensitive << (*(in_DEPTH_MAX [i])); + } # ifdef SYSTEMCASS_SPECIFIC @@ -108,10 +116,10 @@ { (*(out_DECOD_OUT_VAL [i])) (*(in_DECOD_OUT_ACK [i])); - if (_param->_have_port_depth) - for (uint32_t j=0; j<_param->_nb_context; j++) - { - (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_TAIL [j])); - (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_NB_BRANCH [j])); - } + for (uint32_t j=0; j<_param->_nb_context; j++) + { + if (_param->_have_port_depth) + (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MIN [j])); + (*(out_DECOD_OUT_VAL [i])) (*(in_DEPTH_MAX [j])); + } } # endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 88) @@ -65,4 +65,5 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -80,4 +81,5 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t ,_param->_size_special_register_logic); ALLOC1_SIGNAL_IN ( in_DECOD_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_IN ( in_DECOD_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); } @@ -92,4 +94,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -107,4 +110,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t ,_param->_size_special_register_logic); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_OUT(out_DECOD_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); } @@ -113,16 +117,17 @@ ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_DEPTH_TAIL ,"tail" ,Tdepth_t ,_param->_size_depth ); - if (_param->_have_port_depth) - ALLOC1_SIGNAL_IN ( in_DEPTH_NB_BRANCH,"nb_branch",Tdepth_t ,_param->_size_depth+1); + ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1); } - // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE("nb_inst",OUT,NORTH,"Instruction's number", _param->_nb_context); - ALLOC1_SIGNAL_OUT(out_NB_INST_ALL ,"all" ,Tcontext_t ,_param->_size_nb_inst+1); + ALLOC1_SIGNAL_OUT(out_NB_INST_ALL ,"all" ,Tcontext_t ,_param->_size_nb_inst_decod); } + if (usage_is_set(_usage,USE_SYSTEMC)) + { // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ reg_QUEUE = new std::list; @@ -133,4 +138,5 @@ internal_DECOD_OUT_VAL = new Tcontrol_t [_param->_nb_inst_decod]; internal_DECOD_OUT_ACK = new Tcontrol_t [_param->_nb_inst_decod]; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_deallocation.cpp (revision 88) @@ -35,4 +35,5 @@ DELETE1_SIGNAL( in_DECOD_IN_TYPE ,_param->_nb_inst_decod,_param->_size_type ); DELETE1_SIGNAL( in_DECOD_IN_OPERATION ,_param->_nb_inst_decod,_param->_size_operation ); + DELETE1_SIGNAL( in_DECOD_IN_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL( in_DECOD_IN_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL( in_DECOD_IN_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data ); @@ -50,4 +51,5 @@ DELETE1_SIGNAL( in_DECOD_IN_NUM_REG_RE ,_param->_nb_inst_decod,_param->_size_special_register_logic); DELETE1_SIGNAL( in_DECOD_IN_EXCEPTION_USE ,_param->_nb_inst_decod,_param->_size_exception_use ); + DELETE1_SIGNAL( in_DECOD_IN_EXCEPTION ,_param->_nb_inst_decod,_param->_size_exception ); DELETE1_SIGNAL(out_DECOD_OUT_VAL ,_param->_nb_inst_decod,1); @@ -57,4 +59,5 @@ DELETE1_SIGNAL(out_DECOD_OUT_TYPE ,_param->_nb_inst_decod,_param->_size_type ); DELETE1_SIGNAL(out_DECOD_OUT_OPERATION ,_param->_nb_inst_decod,_param->_size_operation ); + DELETE1_SIGNAL(out_DECOD_OUT_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_OUT_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_OUT_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data ); @@ -72,19 +75,20 @@ DELETE1_SIGNAL(out_DECOD_OUT_NUM_REG_RE ,_param->_nb_inst_decod,_param->_size_special_register_logic); DELETE1_SIGNAL(out_DECOD_OUT_EXCEPTION_USE ,_param->_nb_inst_decod,_param->_size_exception_use ); + DELETE1_SIGNAL(out_DECOD_OUT_EXCEPTION ,_param->_nb_inst_decod,_param->_size_exception ); - DELETE1_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth ); - if (_param->_have_port_depth) - DELETE1_SIGNAL( in_DEPTH_NB_BRANCH,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); - DELETE1_SIGNAL(out_NB_INST_ALL ,_param->_nb_context,_param->_size_nb_inst+1); + DELETE1_SIGNAL(out_NB_INST_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete reg_QUEUE; + delete [] reg_NB_INST; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_DECOD_IN_ACK ; + delete [] internal_DECOD_OUT_VAL; + delete [] internal_DECOD_OUT_ACK; } - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete reg_QUEUE; - delete [] reg_NB_INST; - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_DECOD_IN_ACK ; - delete [] internal_DECOD_OUT_VAL; - delete [] internal_DECOD_OUT_ACK; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMealy_decod_out.cpp (revision 88) @@ -23,4 +23,5 @@ { log_begin(Decod_queue,FUNCTION); + log_function(Decod_queue,FUNCTION,_name.c_str()); Tcontrol_t val [_param->_nb_inst_decod]; @@ -36,17 +37,32 @@ if (reg_QUEUE->front()->_val [i]) { - log_printf(TRACE,Decod_queue,FUNCTION,_("Queue is not empty, slot [%d] is valid."),i); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * Queue is not empty, slot [%d] is valid."),i); Tcontext_t context = reg_QUEUE->front()->_context_id [i]; Tdepth_t depth = reg_QUEUE->front()->_depth [i]; - Tdepth_t depth_base = (_param->_have_port_depth)?PORT_READ(in_DEPTH_TAIL [context]):0; - Tdepth_t depth_offset = (_param->_have_port_depth)?PORT_READ(in_DEPTH_NB_BRANCH [context]):0; - Tdepth_t depth_max = depth_base + depth_offset; + Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context]):0; + Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[context]); // is a valid instruction ? - // * depth must be lower that depth max - Tcontrol_t is_valid = depth <= ((depth>depth_base)?(depth_max):(depth_max%_param->_nb_branch_speculated [context])); + // If DEPTH_CURRENT : + // equal at DEPTH_MIN -> not speculative + // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative - log_printf(TRACE,Decod_queue,FUNCTION,_(" * is_valid : %d"),is_valid); + // All case + // ....... min ...X... max ....... OK + // ....... min ....... max ...X... KO + // ...X... min ....... max ....... KO + // ....... max ....... min ...X... OK + // ...X... max ....... min ....... OK + // ....... max ...X... min ....... KO + + Tcontrol_t is_valid = ((depth == depth_min) or + ((depth_min < depth_max)? + (depth depth_min) or (depth < depth_max)))); +// Tcontrol_t is_valid = depth <= depth_max; + + log_printf(TRACE,Decod_queue,FUNCTION,_(" * is_valid : %d"),is_valid); internal_DECOD_OUT_VAL [i] = 1; // in all case, val is set (entry is not empty, and instruction is valid) @@ -65,4 +81,6 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { + log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_OUT_VAL : %d"),val [i]); + PORT_WRITE(out_DECOD_OUT_VAL [i],val [i]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_genMoore.cpp (revision 88) @@ -23,4 +23,5 @@ { log_begin(Decod_queue,FUNCTION); + log_function(Decod_queue,FUNCTION,_name.c_str()); //-------------------------------------------------------------------- @@ -49,4 +50,5 @@ PORT_WRITE(out_DECOD_OUT_TYPE [i],reg_QUEUE->front()->_type [i]); PORT_WRITE(out_DECOD_OUT_OPERATION [i],reg_QUEUE->front()->_operation [i]); + PORT_WRITE(out_DECOD_OUT_NO_EXECUTE [i],reg_QUEUE->front()->_no_execute [i]); PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [i]); PORT_WRITE(out_DECOD_OUT_ADDRESS [i],reg_QUEUE->front()->_address [i]); @@ -64,4 +66,5 @@ PORT_WRITE(out_DECOD_OUT_NUM_REG_RE [i],reg_QUEUE->front()->_num_reg_re [i]); PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [i]); + PORT_WRITE(out_DECOD_OUT_EXCEPTION [i],reg_QUEUE->front()->_exception [i]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_statistics_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_statistics_allocation.cpp (revision 88) @@ -29,5 +29,6 @@ param_statistics); - _stat_nb_inst = new counter_t * [_param->_nb_context]; + _stat_use_queue = _stat->create_variable ("use_queue"); + _stat_nb_inst = new counter_t * [_param->_nb_context]; std::string expr_average_inst = ""; @@ -35,17 +36,20 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - _stat_nb_inst [i] = _stat->create_variable("nb_inst_"+toString(i)); - - _stat->create_expr_average_by_cycle("average_inst_"+toString(i), "nb_inst_"+toString(i), "", toString(_("Average instruction by cycle (context %d)"),i)); - _stat->create_expr_percent ("percent_use_inst_"+toString(i) , "average_inst_"+toString(i), toString(_param->_size_queue), toString(_("Percent instruction by cycle (context %d)"),i)); - - if (i == 0) - expr_average_inst = "nb_inst_"+toString(i); + _stat_nb_inst [i] = _stat->create_variable("nb_inst_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_inst_"+toString(i), "nb_inst_"+toString(i), "", toString(_("Average instruction number in decod_queue by cycle (context %d)"),i)); + _stat->create_expr_percent ("percent_use_inst_"+toString(i) , "average_inst_"+toString(i), toString(_param->_size_queue), toString(_("Percent decod_queue's occupation (context %d)"),i)); + + if (i == 0) + expr_average_inst = "nb_inst_"+toString(i); else expr_average_inst = "+ nb_inst_"+toString(i) + " " +expr_average_inst; } - _stat->create_expr_average_by_cycle("average_inst", expr_average_inst, "", _("Average instruction by cycle (all context)")); - _stat->create_expr_percent ("percent_use_inst" , "average_inst", toString(_param->_size_queue), _("Percent instruction by cycle (all context)")); + _stat->create_expr_average_by_cycle("average_inst", expr_average_inst, "", _("Average instruction number in decod_queue by cycle (all context)")); + _stat->create_expr_percent ("percent_use_inst" , "average_inst", toString(_param->_size_queue), _("Percent decod_queue's occupation (all context)")); + + _stat->create_expr_average_by_cycle("average_use_queue", "use_queue", "", _("Average slot decod_queue occupation by cycle.")); + _stat->create_expr_percent ("percent_use_queue", "average_use_queue", toString(_param->_size_queue), _("Percent slot decod_queue occupation.")); log_end(Decod_queue,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_transition.cpp (revision 88) @@ -23,4 +23,5 @@ { log_begin(Decod_queue,FUNCTION); + log_function(Decod_queue,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -35,18 +36,22 @@ //-------------------------------------------------------------------- //-----[ DECOD_IN ]--------------------------------------------------- - //-------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_inst_decod; i++) + //-------------------------------------------------------------------- + decod_queue_entry_t * entry = NULL; + for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { - decod_queue_entry_t * entry = NULL; if (PORT_READ(in_DECOD_IN_VAL [i]) and internal_DECOD_IN_ACK[i]) { - log_printf(TRACE,Decod_queue,FUNCTION,_("DECOD_IN [%d]"),i); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_IN [%d]"),i); if (entry == NULL) - entry = new decod_queue_entry_t (_param->_nb_inst_decod); + { + // Once creation and insert in queue + entry = new decod_queue_entry_t (_param->_nb_inst_decod); + reg_QUEUE->push_back(entry); + } Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_IN_CONTEXT_ID [i]):0; - log_printf(TRACE,Decod_queue,FUNCTION,_(" * context : %d"),context); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * context : %d"),context); entry->_val [i] = 1; @@ -55,4 +60,5 @@ entry->_type [i] = PORT_READ(in_DECOD_IN_TYPE [i]); entry->_operation [i] = PORT_READ(in_DECOD_IN_OPERATION [i]); + entry->_no_execute [i] = PORT_READ(in_DECOD_IN_NO_EXECUTE [i]); entry->_is_delay_slot [i] = PORT_READ(in_DECOD_IN_IS_DELAY_SLOT [i]); entry->_address [i] = PORT_READ(in_DECOD_IN_ADDRESS [i]); @@ -70,10 +76,10 @@ entry->_num_reg_re [i] = PORT_READ(in_DECOD_IN_NUM_REG_RE [i]); entry->_exception_use [i] = PORT_READ(in_DECOD_IN_EXCEPTION_USE [i]); + entry->_exception [i] = PORT_READ(in_DECOD_IN_EXCEPTION [i]); reg_NB_INST [context] ++; - reg_QUEUE->push_back(entry); - log_printf(TRACE,Decod_queue,FUNCTION,_(" * nb_inst : %d"),reg_NB_INST [context]); - log_printf(TRACE,Decod_queue,FUNCTION,_(" * PUSH queue")); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * nb_inst : %d"),reg_NB_INST [context]); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * PUSH queue")); } } @@ -91,13 +97,13 @@ if (internal_DECOD_OUT_VAL [i] and internal_DECOD_OUT_ACK[i]) { - log_printf(TRACE,Decod_queue,FUNCTION,_("DECOD_OUT [%d]"),i); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * DECOD_OUT [%d]"),i); reg_QUEUE->front()->_val [i] = 0; Tcontext_t context = reg_QUEUE->front()->_context_id [i]; - log_printf(TRACE,Decod_queue,FUNCTION,_(" * context : %d"),context); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * context : %d"),context); reg_NB_INST [context] --; - log_printf(TRACE,Decod_queue,FUNCTION,_(" * nb_inst : %d"),reg_NB_INST [context]); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * nb_inst : %d"),reg_NB_INST [context]); } // Test if slot is (again) valid, if yes, then have less one instruction in the entry @@ -108,5 +114,5 @@ if (not find) // no valid instruction in current slot { - log_printf(TRACE,Decod_queue,FUNCTION,_(" * POP queue")); + log_printf(TRACE,Decod_queue,FUNCTION,_(" * POP queue")); // can pop the slot @@ -117,5 +123,6 @@ } -#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Decod_queue) +#if defined(DEBUG) and defined(DEBUG_Decod_queue) and (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Decod_queue,FUNCTION," * Dump decod_queue"); uint32_t x=0; for (std::list::iterator it=reg_QUEUE->begin(); @@ -123,10 +130,10 @@ it++) { - log_printf(TRACE,Decod_queue,FUNCTION,"[%d] ",x); + log_printf(TRACE,Decod_queue,FUNCTION," * [%d] ",x); for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { if ((*it)->_val [i]) - log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d, %d %d, %d %d %d, 0x%x, %d 0x%x, %d %d, %d %d, %d %d, %d %d, %d %d, %d " + log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d, %d %d, %d %d %d %d, 0x%x, %d 0x%x, %d %d, %d %d, %d %d, %d %d, %d %d, %d %d" ,i ,(*it)->_val [i] @@ -135,4 +142,5 @@ ,(*it)->_type [i] ,(*it)->_operation [i] + ,(*it)->_no_execute [i] ,(*it)->_is_delay_slot [i] ,(*it)->_address [i] @@ -150,7 +158,8 @@ ,(*it)->_num_reg_re [i] ,(*it)->_exception_use [i] + ,(*it)->_exception [i] ); else - log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d" + log_printf(TRACE,Decod_queue,FUNCTION," * [%d] %d" ,i ,(*it)->_val [i] @@ -163,6 +172,10 @@ #ifdef STATISTICS - for (uint32_t i=0; i<_param->_nb_context; i++) - *(_stat_nb_inst [i]) += reg_NB_INST [i]; + if (usage_is_set(_usage,USE_STATISTICS)) + { + *(_stat_use_queue) += reg_QUEUE->size(); + for (uint32_t i=0; i<_param->_nb_context; i++) + *(_stat_nb_inst [i]) += reg_NB_INST [i]; + } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp (revision 88) @@ -10,5 +10,5 @@ namespace morpheo { -namespace behavioural { + namespace behavioural { namespace core { namespace multi_front_end { @@ -24,5 +24,6 @@ uint32_t size_queue , uint32_t size_general_data , - uint32_t * nb_branch_speculated) + uint32_t * nb_branch_speculated, + bool is_toplevel ) { log_begin(Decod_queue,FUNCTION); @@ -31,5 +32,5 @@ _nb_inst_decod = nb_inst_decod ; _size_queue = size_queue ; - _size_general_data = size_general_data ; +// _size_general_data = size_general_data ; _nb_branch_speculated = nb_branch_speculated; @@ -37,12 +38,19 @@ _size_bank = _size_queue / _nb_bank; - _size_context_id = log2(nb_context); - _size_depth = log2(max(_nb_branch_speculated,_nb_context)); - _size_nb_inst = log2(_size_queue); + test(); - _have_port_context_id = (_size_context_id > 0); - _have_port_depth = (_size_depth > 0); - - test(); + if (is_toplevel) + { + _size_context_id = log2(nb_context); + _size_nb_inst_decod = log2(_size_queue)+1; + _size_depth = log2(max(_nb_branch_speculated,_nb_context)); + _size_general_data = size_general_data; + + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; + + copy (); + } + log_end(Decod_queue,FUNCTION); }; @@ -62,4 +70,14 @@ { log_begin(Decod_queue,FUNCTION); + + log_end(Decod_queue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Decod_queue::copy" + void Parameters::copy (void) + { + log_begin(Decod_queue,FUNCTION); + log_end(Decod_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Decod_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_min.cfg (revision 88) @@ -6,5 +6,4 @@ 32 32 +1 # size_general_data 1 1 +1 # nb_branch_speculated [0][nb_context] -1 1 +1 # size_branch_update_prediction 1 1 +1 # nb_context_select 1 1 +1 # select_priority Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_mono_context.cfg (revision 88) @@ -6,5 +6,4 @@ 32 32 +1 # size_general_data 1 1 *4 # nb_branch_speculated [0][nb_context] -0 1 +1 # size_branch_update_prediction 1 1 +1 # nb_context_select 1 1 +1 # select_priority Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/config_multi_context.cfg (revision 88) @@ -2,15 +2,14 @@ 4 4 +1 # nb_context 4 4 *4 # nb_inst_fetch [0][nb_context] -2 2 *4 # nb_inst_fetch [1][nb_context] -1 1 *4 # nb_inst_fetch [2][nb_context] -8 8 *4 # nb_inst_fetch [3][nb_context] -1 8 *4 # nb_inst_decod -16 16 *4 # size_queue -32 32 +1 # size_general_data -1 1 *4 # nb_branch_speculated [0][nb_context] -2 2 *4 # nb_branch_speculated [1][nb_context] -1 1 *4 # nb_branch_speculated [2][nb_context] -4 4 *4 # nb_branch_speculated [3][nb_context] -2 2 +1 # size_branch_update_prediction +2 2 *4 # nb_inst_fetch [1][nb_context] +1 1 *4 # nb_inst_fetch [2][nb_context] +8 8 *4 # nb_inst_fetch [3][nb_context] +1 8 *4 # nb_inst_decod +16 16 *4 # size_queue +32 32 +1 # size_general_data +1 1 *4 # nb_branch_speculated [0][nb_context] +2 2 *4 # nb_branch_speculated [1][nb_context] +1 1 *4 # nb_branch_speculated [2][nb_context] +4 4 *4 # nb_branch_speculated [3][nb_context] 1 4 *4 # nb_context_select 1 1 +1 # select_priority Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/main.cpp (revision 88) @@ -9,5 +9,5 @@ #include "Behavioural/Custom/include/Custom_example.h" -#define NB_PARAMS 8 +#define NB_PARAMS 7 void usage (int argc, char * argv[]) @@ -21,5 +21,4 @@ err (_(" * size_general_data (uint32_t )\n")); err (_(" * nb_branch_speculated [nb_context] (uint32_t )\n")); - err (_(" * size_branch_update_prediction (uint32_t )\n")); err (_(" * nb_context_select (uint32_t )\n")); err (_(" * select_priority (Tpriority_t )\n")); @@ -56,5 +55,4 @@ for (uint32_t i=0; i<_nb_context; i++) _nb_branch_speculated [i] = fromString(argv[x++]); - uint32_t _size_branch_update_prediction= fromString(argv[x++]); uint32_t _nb_context_select = fromString(argv[x++]); Tpriority_t _select_priority = fromString(argv[x++]); @@ -81,10 +79,10 @@ _size_general_data , _nb_branch_speculated , - _size_branch_update_prediction, _nb_context_select , _select_priority , _select_load_balancing , _instruction_implemeted , - &(morpheo::behavioural::custom::example_get_custom_information) + &(morpheo::behavioural::custom::example_get_custom_information), + true ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp (revision 88) @@ -53,7 +53,7 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); + ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]); ALLOC1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,"in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); @@ -63,4 +63,5 @@ ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,"in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,"in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(in_IFETCH_EXCEPTION ,"in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); @@ -70,4 +71,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); @@ -85,4 +87,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); @@ -99,6 +102,6 @@ //ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); - ALLOC1_SC_SIGNAL( in_DEPTH_TAIL ," in_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_DEPTH_NB_BRANCH ," in_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context); @@ -110,4 +113,5 @@ ALLOC_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); ALLOC_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); @@ -124,16 +128,22 @@ (*(_Decod_unit->in_NRESET)) (*(in_NRESET)); - INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Decod_unit,out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + INSTANCE2_SC_SIGNAL(_Decod_unit,out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_CONTEXT_ID ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS ,_param->_nb_context); //INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); - if (_param->_have_port_inst_ifetch_ptr) - INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + if (_param->_have_port_inst_ifetch_ptr) + INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR[i]); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); + } + INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_STATE ,_param->_nb_context); - if (_param->_have_port_branch_update_prediction_id) - INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_EXCEPTION ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_VAL ,_param->_nb_inst_decod); @@ -145,4 +155,5 @@ INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_TYPE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_OPERATION ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS ,_param->_nb_inst_decod); @@ -160,4 +171,5 @@ INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_VAL ,_param->_nb_inst_decod); @@ -167,5 +179,5 @@ INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); @@ -176,15 +188,16 @@ //INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); - if (_param->_have_port_depth) - { - INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_TAIL ,_param->_nb_context); - INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_NB_BRANCH ,_param->_nb_context); - } + INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MAX ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit,out_NB_INST_DECOD_ALL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); - if (_param->_have_port_depth) - INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH ,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + if (_param->_have_port_depth) + { + INSTANCE_SC_SIGNAL(_Decod_unit, in_DEPTH_MIN [i]); + INSTANCE_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH [i]); + } INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL ); @@ -192,9 +205,10 @@ if (_param->_have_port_context_id) INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_CONTEXT_ID ); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_DEPTH ); INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_TYPE ); INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_IS_DELAY_SLOT ); INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS ); INSTANCE_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS_EPCR ); - msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -247,6 +261,6 @@ delay_slot_next [i] = false; - in_DEPTH_TAIL [i]->write(0); - in_DEPTH_NB_BRANCH [i]->write(0); + in_DEPTH_MIN [i]->write(0); + in_DEPTH_MAX [i]->write(0); in_CONTEXT_DEPTH [i]->write(0); } @@ -285,4 +299,5 @@ in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state); in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id); + in_IFETCH_EXCEPTION [i]->write(it->_exception_ifetch); if ((it->_is_delay_slot) or @@ -350,5 +365,5 @@ TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [x]->read(),((entry._address)%_param->_nb_inst_fetch[i]) == 0); TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [x]->read(), entry._branch_state ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x]->read(), entry._branch_update_prediction_id); TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [x]->read(), entry._branch_condition ); @@ -367,5 +382,7 @@ if (_param->_have_port_context_id) - TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), i); + TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), i); + if (_param->_have_port_depth) + TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), entry._depth); TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), entry._context_event_type); TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), entry._is_delay_slot); @@ -396,4 +413,5 @@ TEST(Ttype_t , out_DECOD_TYPE [i]->read(), respons [context].front()._type ); TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), respons [context].front()._operation ); +// TEST(Tcontrol_t , out_DECOD_NO_EXECUTE [i]->read(), respons [context].front()._no_execute ); TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), respons [context].front()._is_delay_slot); TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), respons [context].front()._address ); @@ -417,4 +435,5 @@ TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), respons [context].front()._num_reg_re ); TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), respons [context].front()._exception_use); +// TEST(Texception_t , out_DECOD_EXCEPTION [i]->read(), respons [context].front()._exception ); respons [context].pop_front(); @@ -446,7 +465,7 @@ delete in_NRESET; - DELETE2_SC_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - DELETE2_SC_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); + DELETE2_SC_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + DELETE2_SC_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]); + DELETE2_SC_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]); DELETE1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context); DELETE1_SC_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context); @@ -455,4 +474,5 @@ DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context); DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context); + DELETE1_SC_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod); @@ -462,4 +482,5 @@ DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod); @@ -477,4 +498,5 @@ DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_inst_decod); DELETE1_SC_SIGNAL(out_PREDICT_VAL ,_param->_nb_inst_decod); @@ -491,6 +513,6 @@ //DELETE1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); - DELETE1_SC_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context); - DELETE1_SC_SIGNAL( in_DEPTH_NB_BRANCH ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context); DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context); @@ -502,4 +524,5 @@ DELETE_SC_SIGNAL( in_CONTEXT_EVENT_ACK ); DELETE_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ); + DELETE_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ); DELETE_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ); DELETE_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h (revision 88) @@ -76,4 +76,5 @@ public : SC_IN (Tbranch_state_t ) ** in_IFETCH_BRANCH_STATE ;//[nb_context] public : SC_IN (Tprediction_ptr_t ) ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context] + public : SC_IN (Texception_t ) ** in_IFETCH_EXCEPTION ;//[nb_context] // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -84,4 +85,5 @@ public : SC_OUT(Ttype_t ) ** out_DECOD_TYPE ;//[nb_inst_decod] public : SC_OUT(Toperation_t ) ** out_DECOD_OPERATION ;//[nb_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[nb_inst_decod] @@ -99,4 +101,5 @@ public : SC_OUT(Tspecial_address_t ) ** out_DECOD_NUM_REG_RE ;//[nb_inst_decod] public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION_USE ;//[nb_inst_decod] + public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION ;//[nb_inst_decod] // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -115,9 +118,9 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tdepth_t ) ** in_DEPTH_TAIL ;//[nb_context] - public : SC_IN (Tdepth_t ) ** in_DEPTH_NB_BRANCH ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_MIN ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_MAX ;//[nb_context] // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] + public : SC_OUT(Tcounter_t ) ** out_NB_INST_DECOD_ALL ;//[nb_context] // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -129,4 +132,5 @@ public : SC_IN (Tcontrol_t ) * in_CONTEXT_EVENT_ACK ; public : SC_OUT(Tcontext_t ) * out_CONTEXT_EVENT_CONTEXT_ID ; + public : SC_OUT(Tcontext_t ) * out_CONTEXT_EVENT_DEPTH ; public : SC_OUT(Tevent_type_t ) * out_CONTEXT_EVENT_TYPE ; public : SC_OUT(Tcontrol_t ) * out_CONTEXT_EVENT_IS_DELAY_SLOT ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Parameters.h (revision 88) @@ -30,25 +30,15 @@ public : uint32_t _nb_inst_decod ; public : uint32_t _size_queue ; - public : uint32_t _size_general_data ; +//public : uint32_t _size_general_data ; public : uint32_t * _nb_branch_speculated ; //[nb_context] - public : uint32_t _size_branch_update_prediction; +//public : uint32_t * _size_branch_update_prediction; //[nb_context] public : uint32_t _nb_context_select ; public : Tpriority_t _select_priority ; public : Tload_balancing_t _select_load_balancing ; public : bool ** _instruction_implemeted ; //[nb_context][nb_instruction] - public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (uint32_t); + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); - public : uint32_t _size_nb_inst_decod ; - public : uint32_t _max_nb_inst_fetch ; - - public : uint32_t _size_address_inst ; - public : uint32_t _size_context_id ; - public : uint32_t _size_depth ; - public : uint32_t _size_inst_ifetch_ptr ; - - public : bool _have_port_context_id ; - public : bool _have_port_depth ; - public : bool _have_port_branch_update_prediction_id; - public : bool _have_port_inst_ifetch_ptr ; +//public : uint32_t _size_address_inst; + public : uint32_t _max_nb_inst_fetch; public : morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod ::Parameters * _param_decod; @@ -62,12 +52,16 @@ uint32_t size_general_data , uint32_t * nb_branch_speculated , - uint32_t size_branch_update_prediction, +// uint32_t * size_branch_update_prediction, uint32_t nb_context_select , Tpriority_t select_priority , Tload_balancing_t select_load_balancing , bool ** instruction_implemeted , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)); + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit.cpp (revision 88) @@ -38,4 +38,10 @@ usage_environment(_usage); + +#if DEBUG_Decod_unit == true + log_printf(INFO,Decod_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif log_printf(INFO,Decod_unit,FUNCTION,_("Allocation")); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_allocation.cpp (revision 88) @@ -58,20 +58,21 @@ // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[alloc_interface_it1]); - - - _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1]); + ALLOC2_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context, _param->_nb_inst_fetch[it1]); + + + _ALLOC2_VALACK_IN ( in_IFETCH_VAL ,VAL, _param->_nb_context, _param->_nb_inst_fetch[it1]); + _ALLOC2_VALACK_OUT(out_IFETCH_ACK ,ACK, _param->_nb_context, _param->_nb_inst_fetch[it1]); + _ALLOC2_SIGNAL_IN ( in_IFETCH_INSTRUCTION,"instruction", Tinstruction_t, _param->_size_instruction,_param->_nb_context, _param->_nb_inst_fetch[it1]); } { ALLOC1_INTERFACE("ifetch", IN, WEST, "Instruction's bundle", _param->_nb_context); - ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_address_inst ); -// ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_address_inst ); - ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ); - ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); + ALLOC1_SIGNAL_IN (in_IFETCH_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS ,"address" ,Tgeneral_address_t ,_param->_size_instruction_address ); +// ALLOC1_SIGNAL_IN (in_IFETCH_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_IN (in_IFETCH_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr ); + ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC1_SIGNAL_IN (in_IFETCH_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN (in_IFETCH_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); } @@ -86,6 +87,7 @@ ALLOC1_SIGNAL_OUT(out_DECOD_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_DECOD_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_address_inst ); + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -101,4 +103,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic); ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION_USE,"exception_use",Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_decod ); } @@ -109,14 +112,14 @@ ALLOC1_VALACK_OUT(out_PREDICT_VAL ,VAL); ALLOC1_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition ); -// ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE ,"branch_stack_write" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address_inst ); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address_inst ); -// ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_PREDICT_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition); +// ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STACK_WRITE ,"branch_stack_write" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address ); +// ALLOC1_SIGNAL_IN ( in_PREDICT_CAN_CONTINUE ,"can_continue" ,Tcontrol_t ,1 ); } @@ -125,14 +128,13 @@ ALLOC1_INTERFACE("depth",IN ,NORTH,"Depth", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_DEPTH_TAIL ,"tail" ,Tdepth_t ,_param->_size_depth ); - if (_param->_have_port_depth) - ALLOC1_SIGNAL_IN ( in_DEPTH_NB_BRANCH,"nb_branch",Tdepth_t ,_param->_size_depth+1); - } - - // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ALLOC1_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { ALLOC1_INTERFACE("nb_inst",OUT,NORTH,"Instruction's number", _param->_nb_context); - ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"decod_all" ,Tcontext_t ,_param->_size_nb_inst_decod+1); + ALLOC1_SIGNAL_OUT(out_NB_INST_DECOD_ALL ,"decod_all" ,Tcontext_t ,_param->_size_nb_inst_decod); } @@ -152,8 +154,9 @@ ALLOC_VALACK_IN ( in_CONTEXT_EVENT_ACK ,ACK); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_address_inst); - ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_address_inst); + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_CONTEXT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Tgeneral_data_t,_param->_size_instruction_address); } @@ -254,7 +257,9 @@ PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_BRANCH_STATE" , dest, "in_IFETCH_"+toString(i)+"_BRANCH_STATE" ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID", dest, "in_IFETCH_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); + PORT_MAP(_component,src , "in_IFETCH_"+toString(i)+"_EXCEPTION" , + dest, "in_IFETCH_"+toString(i)+"_EXCEPTION" ); } @@ -282,4 +287,6 @@ COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_OPERATION" , dest, "in_DECOD_IN_"+toString(i)+"_OPERATION" ); + COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_NO_EXECUTE" , + dest, "in_DECOD_IN_"+toString(i)+"_NO_EXECUTE" ); COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT", dest, "in_DECOD_IN_"+toString(i)+"_IS_DELAY_SLOT"); @@ -312,4 +319,6 @@ COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_EXCEPTION_USE", dest, "in_DECOD_IN_"+toString(i)+"_EXCEPTION_USE"); + COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(i)+"_EXCEPTION" , + dest, "in_DECOD_IN_"+toString(i)+"_EXCEPTION" ); } @@ -334,5 +343,5 @@ PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_BRANCH_STATE" , dest,"out_PREDICT_"+toString(i)+"_BRANCH_STATE" ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID", dest,"out_PREDICT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); @@ -382,4 +391,7 @@ PORT_MAP(_component,src ,"out_CONTEXT_EVENT_CONTEXT_ID" , dest,"out_CONTEXT_EVENT_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_CONTEXT_EVENT_DEPTH" , + dest,"out_CONTEXT_EVENT_DEPTH" ); PORT_MAP(_component,src ,"out_CONTEXT_EVENT_TYPE" , dest,"out_CONTEXT_EVENT_TYPE" ); @@ -417,4 +429,5 @@ // in_DECOD_IN_TYPE - component decod // in_DECOD_IN_OPERATION - component decod + // in_DECOD_IN_NO_EXECUTE - component decod // in_DECOD_IN_IS_DELAY_SLOT - component decod // in_DECOD_IN_ADDRESS - component decod @@ -432,4 +445,5 @@ // in_DECOD_IN_NUM_REG_RE - component decod // in_DECOD_IN_EXCEPTION_USE - component decod + // in_DECOD_IN_EXCEPTION - component decod for (uint32_t i=0; i<_param->_nb_inst_decod; i++) @@ -456,4 +470,6 @@ PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_OPERATION" , dest,"out_DECOD_" +toString(i)+"_OPERATION" ); + PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_NO_EXECUTE" , + dest,"out_DECOD_" +toString(i)+"_NO_EXECUTE" ); PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_IS_DELAY_SLOT", dest,"out_DECOD_" +toString(i)+"_IS_DELAY_SLOT"); @@ -486,7 +502,8 @@ PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_EXCEPTION_USE", dest,"out_DECOD_" +toString(i)+"_EXCEPTION_USE"); - } - - if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_DECOD_OUT_"+toString(i)+"_EXCEPTION" , + dest,"out_DECOD_" +toString(i)+"_EXCEPTION" ); + } + for (uint32_t i=0; i<_param->_nb_context; i++) { @@ -498,8 +515,9 @@ #endif - PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_TAIL" , - dest, "in_DEPTH_"+toString(i)+"_TAIL" ); - PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_NB_BRANCH", - dest, "in_DEPTH_"+toString(i)+"_NB_BRANCH"); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_MIN", + dest, "in_DEPTH_"+toString(i)+"_MIN"); + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_MAX", + dest, "in_DEPTH_"+toString(i)+"_MAX"); } @@ -518,7 +536,8 @@ } // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (DEBUG_Decod_unit == true) +#if DEBUG_Decod_unit == true _component->test_map(); - +#endif + #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Decod_unit_deallocation.cpp (revision 88) @@ -28,14 +28,15 @@ delete in_NRESET; - DELETE2_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1],1); - DELETE2_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1],1); - DELETE2_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[alloc_signal_it1],_param->_size_instruction); + DELETE2_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1],1); + DELETE2_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1],1); + DELETE2_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1],_param->_size_instruction); - DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id ); - DELETE1_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_size_general_data ); -// DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_size_general_data ); - DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr ); - DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_size_branch_state ); - DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context,_param->_size_branch_update_prediction); + DELETE1_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id ); + DELETE1_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context,_param->_size_general_data ); +// DELETE1_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context,_param->_size_general_data ); + DELETE1_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr ); + DELETE1_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context,_param->_size_branch_state ); + DELETE1_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context,_param->_size_exception_ifetch); DELETE1_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod,1); @@ -45,4 +46,5 @@ DELETE1_SIGNAL(out_DECOD_TYPE ,_param->_nb_inst_decod,_param->_size_type ); DELETE1_SIGNAL(out_DECOD_OPERATION ,_param->_nb_inst_decod,_param->_size_operation ); + DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod,1 ); DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod,_param->_size_general_data ); @@ -60,23 +62,23 @@ DELETE1_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod,_param->_size_special_register_logic); DELETE1_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod,_param->_size_exception_use ); + DELETE1_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_inst_decod,_param->_size_exception_decod ); DELETE1_SIGNAL(out_PREDICT_VAL ,_param->_nb_inst_decod,1); DELETE1_SIGNAL( in_PREDICT_ACK ,_param->_nb_inst_decod,1); - DELETE1_SIGNAL(out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id ); - DELETE1_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod,1 ); - DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod,_param->_size_branch_state ); - DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_branch_update_prediction); - DELETE1_SIGNAL(out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition ); -// DELETE1_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod,1 ); - DELETE1_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod,1 ); - DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_general_data ); - DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_general_data ); -// DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id ); + DELETE1_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod,_param->_size_branch_state ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod,_param->_size_depth ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod,_param->_size_branch_condition); +// DELETE1_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod,1 ); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod,_param->_size_general_data ); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod,_param->_size_general_data ); +// DELETE1_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod,1 ); - DELETE1_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth ); - if (_param->_have_port_depth) - DELETE1_SIGNAL( in_DEPTH_NB_BRANCH ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL( in_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL( in_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); - DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod+1); + DELETE1_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context,_param->_size_nb_inst_decod); DELETE1_SIGNAL(in_CONTEXT_DECOD_ENABLE ,_param->_nb_context,1); @@ -86,4 +88,5 @@ DELETE_SIGNAL( in_CONTEXT_EVENT_ACK ,1); DELETE_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE_SIGNAL(out_CONTEXT_EVENT_DEPTH ,_param->_size_depth ); DELETE_SIGNAL(out_CONTEXT_EVENT_TYPE ,_param->_size_event_type ); DELETE_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters.cpp (revision 88) @@ -25,10 +25,12 @@ uint32_t size_general_data , uint32_t * nb_branch_speculated , - uint32_t size_branch_update_prediction, +// uint32_t * size_branch_update_prediction, uint32_t nb_context_select , Tpriority_t select_priority , Tload_balancing_t select_load_balancing , bool ** instruction_implemeted , - morpheo::behavioural::custom::custom_information_t (*get_custom_information) (uint32_t)) + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + bool is_toplevel + ) { log_begin(Decod_unit,FUNCTION); @@ -38,7 +40,7 @@ _nb_inst_decod = nb_inst_decod ; _size_queue = size_queue ; - _size_general_data = size_general_data ; +// _size_general_data = size_general_data ; _nb_branch_speculated = nb_branch_speculated ; - _size_branch_update_prediction = size_branch_update_prediction; +// _size_branch_update_prediction = size_branch_update_prediction; _nb_context_select = nb_context_select ; _select_priority = select_priority ; @@ -48,15 +50,6 @@ _max_nb_inst_fetch = max(_nb_inst_fetch,_nb_context); +// _size_address_inst = size_general_data-2; - _size_address_inst = size_general_data-2; - _size_context_id = log2(nb_context ); - _size_depth = log2(max(_nb_branch_speculated,_nb_context)); - _size_inst_ifetch_ptr = log2(_max_nb_inst_fetch ); - - _have_port_context_id = (_size_context_id > 0); - _have_port_depth = (_size_depth > 0); - _have_port_branch_update_prediction_id = (_size_branch_update_prediction > 0); - _have_port_inst_ifetch_ptr = (_size_inst_ifetch_ptr > 0); - test(); @@ -65,8 +58,8 @@ _nb_inst_fetch , _nb_inst_decod , - max(_nb_branch_speculated,_nb_context), - _size_branch_update_prediction, + _nb_branch_speculated, +// _size_branch_update_prediction, _nb_context_select , - _size_general_data , + size_general_data , _select_priority , _select_load_balancing , @@ -78,9 +71,26 @@ _nb_inst_decod , _size_queue , - _size_general_data , + size_general_data , _nb_branch_speculated); - _size_nb_inst_decod = _param_decod_queue->_size_nb_inst; - + if (is_toplevel) + { + _size_context_id = log2(_nb_context); + _size_depth = max(_nb_branch_speculated,_nb_context); +// _size_branch_update_prediction_id = max(_size_branch_update_prediction,_nb_context); + _size_inst_ifetch_ptr = log2(max(_nb_inst_fetch,_nb_context)); + _size_nb_inst_decod = log2(_size_queue)+1; + + _size_instruction_address = size_general_data-2; + _size_general_data = size_general_data; + + _have_port_context_id = _size_context_id > 0; + _have_port_depth = (_size_depth > 0); +// _have_port_branch_update_prediction_id = (_size_branch_update_prediction_id > 0); + _have_port_inst_ifetch_ptr = (_size_inst_ifetch_ptr > 0); + + copy (); + } + log_end(Decod_unit,FUNCTION); }; @@ -101,6 +111,19 @@ log_begin(Decod_unit,FUNCTION); - delete _param_decod; - delete _param_decod_queue; + delete _param_decod; + delete _param_decod_queue; + + log_end(Decod_unit,FUNCTION); + }; + + +#undef FUNCTION +#define FUNCTION "Decod_unit::copy" + void Parameters::copy (void) + { + log_begin(Decod_unit,FUNCTION); + + COPY(_param_decod ); + COPY(_param_decod_queue); log_end(Decod_unit,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/src/Parameters_print.cpp (revision 88) @@ -30,5 +30,4 @@ xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); - xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); xml.singleton_begin("nb_context_select "); xml.attribut("value",toString(_nb_context_select )); xml.singleton_end(); xml.singleton_begin("select_priority "); xml.attribut("value",toString(_select_priority )); xml.singleton_end(); @@ -43,5 +42,5 @@ xml. singleton_begin("nb_inst_fetch "); xml.attribut("value",toString(_nb_inst_fetch [i])); xml.singleton_end(); xml. singleton_begin("nb_branch_speculated "); xml.attribut("value",toString(_nb_branch_speculated [i])); xml.singleton_end(); - +// xml. singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction[i])); xml.singleton_end(); xml. balise_close(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libFront_end_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.deps (revision 88) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Front_end_Glue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Front_end_Glue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue + +#-----[ Library ]------------------------------------------ + +Front_end_Glue_LIBRARY = -lFront_end_Glue \ + $(Behavioural_LIBRARY) + +Front_end_Glue_DIR_LIBRARY = -L$(Front_end_Glue_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Front_end_Glue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Front_end_Glue_DIR) --makefile=Makefile; + +Front_end_Glue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Front_end_Glue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Front_end_Glue_LIBRARY) + +DIR_LIBRARY = $(Front_end_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Front_end_Glue_library + +library_clean : Front_end_Glue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_1-decod_unit_1.cfg (revision 88) @@ -0,0 +1,9 @@ +Front_end_Glue +1 1 +1 # nb_context +1 1 +1 # nb_decod_unit +1 1 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +30 30 +1 # size_address +2 2 +1 # size_depth [0] [nb_context] +4 4 +1 # nb_branch_speculated [0] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_1.cfg (revision 88) @@ -0,0 +1,18 @@ +Front_end_Glue +4 4 +1 # nb_context +1 1 +1 # nb_decod_unit +1 1 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [1] [nb_context] +0 0 +1 # link_context_to_decod_unit [2] [nb_context] +0 0 +1 # link_context_to_decod_unit [3] [nb_context] +30 30 +1 # size_address +2 2 +1 # size_depth [0] [nb_context] +0 0 +1 # size_depth [1] [nb_context] +1 1 +1 # size_depth [2] [nb_context] +3 3 +1 # size_depth [3] [nb_context] +4 4 +1 # nb_branch_speculated [0] [nb_context] +1 1 +1 # nb_branch_speculated [1] [nb_context] +2 2 +1 # nb_branch_speculated [2] [nb_context] +8 8 +1 # nb_branch_speculated [3] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 88) @@ -0,0 +1,19 @@ +Front_end_Glue +4 4 +1 # nb_context +2 2 +1 # nb_decod_unit +4 4 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_inst_decod [1] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +1 1 +1 # link_context_to_decod_unit [1] [nb_context] +0 0 +1 # link_context_to_decod_unit [2] [nb_context] +1 1 +1 # link_context_to_decod_unit [3] [nb_context] +30 30 +1 # size_address +2 2 +1 # size_depth [0] [nb_context] +0 0 +1 # size_depth [1] [nb_context] +1 1 +1 # size_depth [2] [nb_context] +3 3 +1 # size_depth [3] [nb_context] +4 4 +1 # nb_branch_speculated [0] [nb_context] +1 1 +1 # nb_branch_speculated [1] [nb_context] +2 2 +1 # nb_branch_speculated [2] [nb_context] +8 8 +1 # nb_branch_speculated [3] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 88) @@ -0,0 +1,19 @@ +Front_end_Glue +4 4 +1 # nb_context +2 2 +1 # nb_decod_unit +4 4 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_inst_decod [1] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +1 1 +1 # link_context_to_decod_unit [1] [nb_context] +1 1 +1 # link_context_to_decod_unit [2] [nb_context] +1 1 +1 # link_context_to_decod_unit [3] [nb_context] +30 30 +1 # size_address +2 2 +1 # size_depth [0] [nb_context] +0 0 +1 # size_depth [1] [nb_context] +1 1 +1 # size_depth [2] [nb_context] +3 3 +1 # size_depth [3] [nb_context] +4 4 +1 # nb_branch_speculated [0] [nb_context] +1 1 +1 # nb_branch_speculated [1] [nb_context] +2 2 +1 # nb_branch_speculated [2] [nb_context] +8 8 +1 # nb_branch_speculated [3] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-context_4-decod_unit_4.cfg (revision 88) @@ -0,0 +1,21 @@ +Front_end_Glue +4 4 +1 # nb_context +4 4 +1 # nb_decod_unit +2 2 +1 # nb_inst_decod [0] [nb_decod_unit] +4 4 +1 # nb_inst_decod [1] [nb_decod_unit] +1 1 +1 # nb_inst_decod [2] [nb_decod_unit] +8 8 +1 # nb_inst_decod [3] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +1 1 +1 # link_context_to_decod_unit [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [1] [nb_context] +3 3 +1 # link_context_to_decod_unit [2] [nb_context] +2 2 +1 # link_context_to_decod_unit [3] [nb_context] +30 30 +1 # size_address +2 2 +1 # size_depth [0] [nb_context] +0 0 +1 # size_depth [1] [nb_context] +1 1 +1 # size_depth [2] [nb_context] +3 3 +1 # size_depth [3] [nb_context] +4 4 +1 # nb_branch_speculated [0] [nb_context] +1 1 +1 # nb_branch_speculated [1] [nb_context] +2 2 +1 # nb_branch_speculated [2] [nb_context] +8 8 +1 # nb_branch_speculated [3] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,9 @@ +Front_end_Glue +1 1 +1 # nb_context +1 1 +1 # nb_decod_unit +1 1 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_complete +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +30 30 +1 # size_address +0 0 +1 # size_depth [0] [nb_context] +1 1 +1 # nb_branch_speculated [0] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_front_end; +using namespace morpheo::behavioural::core::multi_front_end::front_end; + +using namespace morpheo::behavioural::core::multi_front_end::front_end::front_end_glue; + +void test (string name, + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,120 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 4 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_context (uint32_t)\n")); + err (_(" * nb_decod_unit (uint32_t)\n")); + err (_(" * nb_inst_decod [nb_decod_unit] (uint32_t)\n")); + err (_(" * nb_inst_branch_complete (uint32_t)\n")); + err (_(" * link_context_to_decod_unit [nb_context] (uint32_t)\n")); + err (_(" * size_address (uint32_t)\n")); + err (_(" * size_depth [nb_context] (uint32_t)\n")); + err (_(" * nb_branch_speculated [nb_context] (uint32_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + for (int32_t i=0; i(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_context = fromString(argv[x++]); + uint32_t _nb_decod_unit = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+3*_nb_context+1*_nb_decod_unit)) + usage (argc, argv); + + uint32_t * _nb_inst_decod = new uint32_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _nb_inst_decod [i] = fromString(argv[x++]); + + uint32_t _nb_inst_branch_complete = fromString(argv[x++]); + + uint32_t * _link_context_to_decod_unit = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _link_context_to_decod_unit [i] = fromString(argv[x++]); + + uint32_t _size_address = fromString(argv[x++]); + + uint32_t * _size_depth = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _size_depth [i] = fromString(argv[x++]); + + uint32_t * _nb_branch_speculated = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _nb_branch_speculated [i] = fromString(argv[x++]); + + std::vector * _translate_context_id_from_decod_unit = new std::vector [_nb_decod_unit]; + + for (uint32_t i=0; i<_nb_context; ++i) + _translate_context_id_from_decod_unit [_link_context_to_decod_unit[i]].push_back(i); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters + (_nb_context , + _nb_decod_unit , + _nb_inst_decod , + _nb_inst_branch_complete , + _link_context_to_decod_unit , + _translate_context_id_from_decod_unit , + _size_address , + _size_depth , + _nb_branch_speculated , + true // is_toplevel + ); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("%s"),error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Front_end_Glue : no error"); + else + TEST_KO("Front_end_Glue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _translate_context_id_from_decod_unit; + delete [] _nb_branch_speculated ; + delete [] _size_depth ; + delete [] _link_context_to_decod_unit ; + delete [] _nb_inst_decod ; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,257 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Front_end_Glue * _Front_end_Glue = new Front_end_Glue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL(out_IFETCH_DECOD_UNIT_CONTEXT_ID ,"out_IFETCH_DECOD_UNIT_CONTEXT_ID ",Tcontext_t,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_DECOD_UNIT_CONTEXT_ID ," in_DECOD_DECOD_UNIT_CONTEXT_ID ",Tcontext_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ,"out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ," in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION," in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ,"out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ," in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ",Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ",Tcontrol_t,_param->_nb_inst_branch_complete); + + ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_VAL ,"out_EVENT_IFETCH_UNIT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_IFETCH_UNIT_ACK ," in_EVENT_IFETCH_UNIT_ACK ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS ,"out_EVENT_IFETCH_UNIT_ADDRESS ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"out_EVENT_IFETCH_UNIT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ," in_EVENT_CONTEXT_STATE_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,"out_EVENT_CONTEXT_STATE_ACK ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS ," in_EVENT_CONTEXT_STATE_ADDRESS ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ",Taddress_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ," in_EVENT_CONTEXT_STATE_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); + + ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ," in_DEPTH_PREDICTION_UNIT_CURRENT ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ," in_DEPTH_PREDICTION_UNIT_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ," in_DEPTH_PREDICTION_UNIT_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,"out_DEPTH_CONTEXT_STATE_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,"out_DEPTH_DECOD_UNIT_MIN ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + ALLOC2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,"out_DEPTH_DECOD_UNIT_MAX ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + ALLOC2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,"out_CONTEXT_DECOD_UNIT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Front_end_Glue.\n"),name.c_str()); + + (*(_Front_end_Glue->in_CLOCK)) (*(in_CLOCK)); + (*(_Front_end_Glue->in_NRESET)) (*(in_NRESET)); + + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_IFETCH_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Front_end_Glue, in_DECOD_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_ADDRESS ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_ADDRESS_NEXT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IS_DS_TAKE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_IFETCH_UNIT_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + if (_param->_have_port_depth) + { + INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_MIN [i]); + INSTANCE_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_CURRENT [i]); + INSTANCE_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_MIN [i]); + INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_CONTEXT_STATE_MIN [i]); + } + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_DEPTH_MAX ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context); + INSTANCE2_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_decod_unit_nb_context [i]; ++j) + if (_param->_have_port_depth) + { + INSTANCE_SC_SIGNAL(_Front_end_Glue,out_DEPTH_DECOD_UNIT_MIN [i][j]); + INSTANCE_SC_SIGNAL(_Front_end_Glue,out_CONTEXT_DECOD_UNIT_DEPTH [i][j]); + } + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL(out_IFETCH_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + DELETE2_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + + DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_IFETCH_UNIT_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); + + DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context); + + DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + DELETE2_SC_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + DELETE2_SC_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + } +#endif + + delete _Front_end_Glue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Front_end_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Front_end_Glue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Front_end_Glue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Front_end_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 88) @@ -0,0 +1,192 @@ +#ifndef morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Front_end_Glue_h +#define morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Front_end_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + + class Front_end_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontext_t ) *** out_IFETCH_DECOD_UNIT_CONTEXT_ID ;//[nb_decod_unit][nb_decod_unit_context] + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontext_t ) *** out_DECOD_CONTEXT_ID ;//[nb_decod_unit][nb_inst_decod] + public : SC_IN (Tcontext_t ) *** in_DECOD_DECOD_UNIT_CONTEXT_ID ;//[nb_decod_unit][nb_inst_decod] + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] + + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION ;//[nb_inst_branch_complete] + + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ;//[nb_inst_branch_complete] + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_EVENT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_ACK ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_ADDRESS ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_ADDRESS_NEXT ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_ADDRESS_NEXT_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_IS_DS_TAKE ;//[nb_context] + + public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_IFETCH_UNIT_ACK ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_IS_DS_TAKE ;//[nb_context] + + public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_CONTEXT_STATE_ACK ;//[nb_context] + public : SC_IN (Taddress_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS ;//[nb_context] + public : SC_IN (Taddress_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_IS_DS_TAKE ;//[nb_context] + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ;//[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ;//[nb_context] + + public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_CURRENT ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_MIN ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_DEPTH_PREDICTION_UNIT_MAX ;//[nb_context] + +//public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_CURRENT ;//[nb_decod_unit][nb_decod_unit_context] + public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_MIN ;//[nb_decod_unit][nb_decod_unit_context] + public : SC_OUT(Tdepth_t ) *** out_DEPTH_DECOD_UNIT_MAX ;//[nb_decod_unit][nb_decod_unit_context] + + public : SC_OUT(Tdepth_t ) ** out_DEPTH_CONTEXT_STATE_MIN ;//[nb_context] + + // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tdepth_t ) *** out_CONTEXT_DECOD_UNIT_DEPTH ;//[nb_decod_unit][nb_decod_unit_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Front_end_Glue); +#endif + public : Front_end_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Front_end_Glue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_decod (void); + public : void genMealy_branch_complete (void); + public : void genMealy_event (void); + public : void genMealy_depth (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h (revision 88) @@ -0,0 +1,77 @@ +#ifndef morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Parameters_h +#define morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_context ; + public : uint32_t _nb_decod_unit ; + public : uint32_t * _nb_inst_decod ;//[nb_decod_unit] + public : uint32_t _nb_inst_branch_complete ; + public : uint32_t * _link_context_to_decod_unit ;//[nb_context] + public : std::vector * _translate_context_id_from_decod_unit ;//[nb_decod_unit]{decod_unit_nb_context} -> nb_context +//public : uint32_t _size_address ; +//public : uint32_t * _size_depth ;//[nb_context] + public : uint32_t * _nb_branch_speculated ;//[nb_context] + + public : uint32_t * _decod_unit_nb_context ;//[nb_decod_unit] +//public : uint32_t * _size_decod_unit_context_id ;//[nb_decod_unit] +//public : uint32_t _size_context_id ; +//public : uint32_t _max_size_depth ; + +//public : bool * _have_port_decod_unit_context_id ;//[nb_decod_unit] +//public : bool _have_port_context_id ; +//public : bool * _have_port_depth ;//[nb_context] +//public : bool _have_port_max_depth ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_context , + uint32_t nb_decod_unit , + uint32_t * nb_inst_decod , + uint32_t nb_inst_branch_complete , + uint32_t * link_context_to_decod_unit , + std::vector * translate_context_id_from_decod_unit , + uint32_t size_address , + uint32_t * size_depth , + uint32_t * nb_branch_speculated , + uint32_t is_toplevel=false); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters & x); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Types.h (revision 88) @@ -0,0 +1,29 @@ +#ifndef morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Types_h +#define morpheo_behavioural_core_multi_front_end_front_end_front_end_glue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 88) @@ -0,0 +1,201 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::Front_end_Glue" + Front_end_Glue::Front_end_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Front_end_Glue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Front_end_Glue == true + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Constant + if (_param->_have_port_context_id) + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + PORT_WRITE(out_IFETCH_DECOD_UNIT_CONTEXT_ID [i][j],j); + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + if (_param->_have_port_context_id) + { + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_decod"),_name.c_str()); + + SC_METHOD (genMealy_decod); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + sensitive << (*( in_DECOD_DECOD_UNIT_CONTEXT_ID [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + } + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_branch_complete"),_name.c_str()); + + SC_METHOD (genMealy_branch_complete); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + sensitive << (*( in_BRANCH_COMPLETE_VAL [i])) + << (*( in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK [i])) + << (*( in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION [i])) + << (*( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK [i])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_event"),_name.c_str()); + + SC_METHOD (genMealy_event); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_context; ++i) + sensitive << (*( in_EVENT_ACK [i])) + << (*( in_EVENT_IFETCH_UNIT_ACK [i])) + << (*( in_EVENT_CONTEXT_STATE_VAL [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) + << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Method - genMealy_depth"),_name.c_str()); + + SC_METHOD (genMealy_depth); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + if (_param->_have_port_depth) + sensitive << (*( in_DEPTH_PREDICTION_UNIT_CURRENT [i])) + << (*( in_DEPTH_PREDICTION_UNIT_MIN [i])); + + sensitive << (*( in_DEPTH_PREDICTION_UNIT_MAX [i])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + +#endif + } + log_end(Front_end_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::~Front_end_Glue" + Front_end_Glue::~Front_end_Glue (void) + { + log_begin(Front_end_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 88) @@ -0,0 +1,161 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::allocation" + void Front_end_Glue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Front_end_Glue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Front_end_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("ifetch",OUT,SOUTH,_("ifetch"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + + _ALLOC2_SIGNAL_OUT(out_IFETCH_DECOD_UNIT_CONTEXT_ID ,"DECOD_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + } + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("decod",OUT,EAST,_("decod"),_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + _ALLOC2_SIGNAL_OUT(out_DECOD_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_DECOD_UNIT_CONTEXT_ID ,"DECOD_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("branch_complete",IN,EAST,_("branch_complete"),_param->_nb_inst_branch_complete); + + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_VAL ,"VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1); + + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ,"PREDICTION_UNIT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ,"PREDICTION_UNIT_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION ,"PREDICTION_UNIT_MISS_PREDICTION",Tcontrol_t ,1); + + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ,"CONTEXT_STATE_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ,"CONTEXT_STATE_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,"CONTEXT_STATE_MISS_PREDICTION" ,Tcontrol_t ,1); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("event",OUT,EAST,_("event"),_param->_nb_context); + + ALLOC1_SIGNAL_OUT (out_EVENT_VAL ,"VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1); + + ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_VAL ,"IFETCH_UNIT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_IFETCH_UNIT_ACK ,"IFETCH_UNIT_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS ,"IFETCH_UNIT_ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ,"IFETCH_UNIT_ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"IFETCH_UNIT_ADDRESS_NEXT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"IFETCH_UNIT_IS_DS_TAKE" ,Tcontrol_t ,1); + + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_VAL ,"CONTEXT_STATE_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_CONTEXT_STATE_ACK ,"CONTEXT_STATE_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS ,"CONTEXT_STATE_ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ,"CONTEXT_STATE_ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,"CONTEXT_STATE_ADDRESS_NEXT_VAL",Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,"CONTEXT_STATE_IS_DS_TAKE" ,Tcontrol_t ,1); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("depth",OUT,EAST,_("depth"),_param->_nb_context); + +// ALLOC1_SIGNAL_OUT (out_DEPTH_CURRENT ,"CURRENT" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1); + + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_CURRENT ,"PREDICTION_UNIT_CURRENT" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_MIN ,"PREDICTION_UNIT_MIN" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_DEPTH_PREDICTION_UNIT_MAX ,"PREDICTION_UNIT_MAX" ,Tdepth_t ,_param->_size_depth+1); + + ALLOC1_SIGNAL_OUT (out_DEPTH_CONTEXT_STATE_MIN ,"CONTEXT_STATE_MIN" ,Tdepth_t ,_param->_size_depth ); + } + { + ALLOC2_INTERFACE("depth",OUT,EAST,_("depth"),_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + +// _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_CURRENT ,"DECOD_UNIT_CURRENT" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MIN ,"DECOD_UNIT_MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + _ALLOC2_SIGNAL_OUT(out_DEPTH_DECOD_UNIT_MAX ,"DECOD_UNIT_MAX" ,Tdepth_t ,_param->_size_depth+1,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + } + + // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("context",OUT,EAST,_("context"),_param->_nb_decod_unit,_param->_translate_context_id_from_decod_unit[it1].size()); + + _ALLOC2_SIGNAL_OUT(out_CONTEXT_DECOD_UNIT_DEPTH ,"DECOD_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 88) @@ -0,0 +1,90 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::deallocation" + void Front_end_Glue::deallocation (void) + { + log_begin(Front_end_Glue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL(out_IFETCH_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_context_id); + + DELETE2_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_context_id); + DELETE2_SIGNAL( in_DECOD_DECOD_UNIT_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_context_id); + + DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_VAL ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_STATE_ACK ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1); + + DELETE1_SIGNAL(out_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_ACK ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_IFETCH_UNIT_ACK ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context,1); + + DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_CURRENT ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL( in_DEPTH_PREDICTION_UNIT_MAX ,_param->_nb_context,_param->_size_depth+1); + DELETE1_SIGNAL(out_DEPTH_CONTEXT_STATE_MIN ,_param->_nb_context,_param->_size_depth ); + +// DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_CURRENT ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth ); + DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MIN ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth ); + DELETE2_SIGNAL(out_DEPTH_DECOD_UNIT_MAX ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth+1); + + DELETE2_SIGNAL(out_CONTEXT_DECOD_UNIT_DEPTH ,_param->_nb_decod_unit,_param->_decod_unit_nb_context [it1],_param->_size_depth); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::end_cycle" +void Front_end_Glue::end_cycle () + { + log_begin(Front_end_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_branch_complete.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_branch_complete.cpp (revision 88) @@ -0,0 +1,49 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::genMealy_branch_complete" + void Front_end_Glue::genMealy_branch_complete (void) + { + log_begin(Front_end_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + Tcontrol_t miss_prediction = PORT_READ(in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION [i]); + PORT_WRITE(out_BRANCH_COMPLETE_MISS_PREDICTION [i],miss_prediction); + PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION [i],miss_prediction); + + Tcontrol_t val = PORT_READ(in_BRANCH_COMPLETE_VAL [i]); + PORT_WRITE(out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL [i],val); + PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_STATE_VAL [i],val); + + Tcontrol_t ack = (PORT_READ(in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK [i]) and + PORT_READ(in_BRANCH_COMPLETE_CONTEXT_STATE_ACK [i])); + PORT_WRITE(out_BRANCH_COMPLETE_ACK [i],ack); + } + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_decod.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_decod.cpp (revision 88) @@ -0,0 +1,40 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::genMealy_decod" + void Front_end_Glue::genMealy_decod (void) + { + log_begin(Front_end_Glue,FUNCTION); + + // Warning : this function is an sc_method if _have_port_context_id + + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + PORT_WRITE(out_DECOD_CONTEXT_ID [i][j],_param->_translate_context_id_from_decod_unit[i][PORT_READ(in_DECOD_DECOD_UNIT_CONTEXT_ID [i][j])]); + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_depth.cpp (revision 88) @@ -0,0 +1,59 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::genMealy_depth" + void Front_end_Glue::genMealy_depth (void) + { + log_begin(Front_end_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + if (_param->_have_port_depth) + { + Tdepth_t min = PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [i]); + PORT_WRITE(out_DEPTH_CONTEXT_STATE_MIN [i],min); + PORT_WRITE(out_DEPTH_MIN [i],min); + } + + PORT_WRITE(out_DEPTH_MAX [i], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [i])); + } + + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + { + uint32_t num_context = _param->_translate_context_id_from_decod_unit[i][j]; + + if (_param->_have_port_depth) + { + PORT_WRITE(out_CONTEXT_DECOD_UNIT_DEPTH [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_CURRENT [num_context])); + PORT_WRITE(out_DEPTH_DECOD_UNIT_MIN [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MIN [num_context])); + } + PORT_WRITE(out_DEPTH_DECOD_UNIT_MAX [i][j], PORT_READ(in_DEPTH_PREDICTION_UNIT_MAX [num_context])); + } + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp (revision 88) @@ -0,0 +1,76 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::genMealy_event" + void Front_end_Glue::genMealy_event (void) + { + log_begin(Front_end_Glue,FUNCTION); + log_function(Front_end_Glue,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]); + PORT_WRITE(out_EVENT_ADDRESS [i],address); + PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS [i],address); + + Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]); + PORT_WRITE(out_EVENT_ADDRESS_NEXT [i],address_next); + PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT [i],address_next); + + Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]); + PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i],address_next_val); + PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL [i],address_next_val); + + Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]); + PORT_WRITE(out_EVENT_IS_DS_TAKE [i],is_ds_take); + PORT_WRITE(out_EVENT_IFETCH_UNIT_IS_DS_TAKE [i],is_ds_take); + + Tcontrol_t val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); + PORT_WRITE(out_EVENT_VAL [i],val); + PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i],val); + + Tcontrol_t ack = (PORT_READ(in_EVENT_ACK [i]) and + PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i])); + PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i],ack); + +#ifdef DEBUG + log_printf(TRACE,Front_end_Glue,FUNCTION," * EVENT Context [%d]",i); + if (val and ack) + { + log_printf(TRACE,Front_end_Glue,FUNCTION," * have event"); + log_printf(TRACE,Front_end_Glue,FUNCTION," * address : %.8x (%.8x)",address ,address <<2); + log_printf(TRACE,Front_end_Glue,FUNCTION," * address_next : %.8x (%.8x)",address_next,address_next<<2); + log_printf(TRACE,Front_end_Glue,FUNCTION," * address_next_val : %d",address_next_val); + log_printf(TRACE,Front_end_Glue,FUNCTION," * is_ds_take : %d",is_ds_take ); + } + else + log_printf(TRACE,Front_end_Glue,FUNCTION," * have not event"); +#endif + } + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::statistics_allocation" + void Front_end_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Front_end_Glue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Front_end_Glue", + param_statistics); + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::statistics_deallocation" + void Front_end_Glue::statistics_deallocation (void) + { + log_begin(Front_end_Glue,FUNCTION); + + log_printf(INFO,Front_end_Glue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_transition.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::transition" + void Front_end_Glue::transition (void) + { + log_begin(Front_end_Glue,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::vhdl" + void Front_end_Glue::vhdl (void) + { + log_begin(Front_end_Glue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::vhdl_body" + void Front_end_Glue::vhdl_body (Vhdl * & vhdl) + { + log_begin(Front_end_Glue,FUNCTION); + vhdl->set_body (""); + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::vhdl_declaration" + void Front_end_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Front_end_Glue,FUNCTION); + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters.cpp (revision 88) @@ -0,0 +1,102 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::Parameters" + Parameters::Parameters (uint32_t nb_context , + uint32_t nb_decod_unit , + uint32_t * nb_inst_decod , + uint32_t nb_inst_branch_complete , + uint32_t * link_context_to_decod_unit , + std::vector * translate_context_id_from_decod_unit , + uint32_t size_address , + uint32_t * size_depth , + uint32_t * nb_branch_speculated , + uint32_t is_toplevel): + morpheo::behavioural::Parameters() + { + log_begin(Front_end_Glue,FUNCTION); + + _nb_context = nb_context ; + _nb_decod_unit = nb_decod_unit ; + _nb_inst_decod = nb_inst_decod ; + _nb_inst_branch_complete = nb_inst_branch_complete ; + _link_context_to_decod_unit = link_context_to_decod_unit ; + _translate_context_id_from_decod_unit = translate_context_id_from_decod_unit; + _nb_branch_speculated = nb_branch_speculated ; + + _decod_unit_nb_context = new uint32_t [_nb_decod_unit]; + + for (uint32_t i=0; i<_nb_decod_unit; i++) + { + _decod_unit_nb_context [i] = translate_context_id_from_decod_unit[i].size(); + } + + test(); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context); + _size_instruction_address = size_address; + _size_depth = max(size_depth,_nb_context); + + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; + + copy (); + } + + log_end(Front_end_Glue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Front_end_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Front_end_Glue,FUNCTION); +// test(); +// log_end(Front_end_Glue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::~Parameters" + Parameters::~Parameters () + { + log_begin(Front_end_Glue,FUNCTION); + + delete [] _decod_unit_nb_context; + + log_end(Front_end_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::copy" + void Parameters::copy (void) + { + log_begin(Front_end_Glue,FUNCTION); + + log_end(Front_end_Glue,FUNCTION); + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,53 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Front_end_Glue,FUNCTION); + + Parameters_test test ("Front_end_Glue"); + + std::vector translate_context_from_decod_unit [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_context; ++i) + { + uint32_t x = _link_context_to_decod_unit[i]; + if (x < _nb_decod_unit) + translate_context_from_decod_unit [x].push_back(i); + else + test.error(toString(_("context[%d] is linked with an invalid decod_unit.\n"),i)); + } + + for (uint32_t i=0; i<_nb_decod_unit; ++i) + if (translate_context_from_decod_unit [i].size() == 0) + test.error(toString(_("decod_unit[%d] is not linked with a ifetch_unit.\n"),i)); + + log_end(Front_end_Glue,FUNCTION); + + return test; + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,56 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { +namespace front_end_glue { + + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Front_end_Glue,FUNCTION); + + XML xml ("front_end_glue"); + + xml.balise_open("front_end_glue"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Front_end_Glue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Front_end_Glue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Parameters & x) + { + log_begin(Front_end_Glue,FUNCTION); + + output_stream << x.print(0); + + log_end(Front_end_Glue,FUNCTION); + + return output_stream; + }; + +}; // end namespace front_end_glue +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Address_management_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/main.cpp (revision 88) @@ -44,5 +44,7 @@ (_nb_instruction , _size_address , - _size_branch_update_prediction); + _size_branch_update_prediction, + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp (revision 88) @@ -24,4 +24,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Address_management * _Address_management = new Address_management (name.c_str(), @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -62,4 +72,7 @@ ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); + ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); + ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); /******************************************************** @@ -76,8 +89,8 @@ INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); @@ -89,12 +102,15 @@ INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL ); INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK ); INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); + INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); + INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -143,7 +159,7 @@ Tcontrol_t nn_val = false; - Tgeneral_data_t c_addr = 0x100; - Tgeneral_data_t n_addr = 0x100; - Tgeneral_data_t nn_addr = 0x100; + Tgeneral_data_t c_addr = 0x100>>2; + Tgeneral_data_t n_addr = 0x100>>2; + Tgeneral_data_t nn_addr = 0x100>>2; Tcontrol_t c_enable [_param->_nb_instruction]; @@ -159,11 +175,14 @@ LABEL("Send Reset"); - do - { - in_EVENT_VAL ->write(1); - in_EVENT_ADDRESS->write(n_addr); - SC_START(1); - } while (out_EVENT_ACK->read() == false); - in_EVENT_VAL ->write(0); +// do +// { +// in_EVENT_VAL ->write(1); +// in_EVENT_ADDRESS ->write(n_addr); +// in_EVENT_ADDRESS_NEXT ->write(nn_addr); +// in_EVENT_ADDRESS_NEXT_VAL->write(0); +// in_EVENT_IS_DS_TAKE ->write(0); +// SC_START(1); +// } while (out_EVENT_ACK->read() == false); +// in_EVENT_VAL ->write(0); n_val = 1; @@ -206,6 +225,10 @@ } - in_EVENT_VAL ->write((rand()%100)write(0x100); + in_EVENT_VAL ->write((rand()%100)write(0x77); + in_EVENT_ADDRESS_NEXT ->write(0x171); + Tcontrol_t next_val = rand()%2; + in_EVENT_ADDRESS_NEXT_VAL->write(next_val); + in_EVENT_IS_DS_TAKE ->write(next_val); //------------------------------------------------- @@ -238,8 +261,8 @@ for (uint32_t i=0; i<_param->_nb_instruction; i++) TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); @@ -272,14 +295,17 @@ LABEL("EVENT : Transaction accepted"); - c_val = false; - n_val = true; - nn_val = false; - - n_addr = in_EVENT_ADDRESS->read(); - n_is_ds_take = 0; + c_val = false; + n_val = true; + n_addr = in_EVENT_ADDRESS ->read(); + n_is_ds_take = in_EVENT_IS_DS_TAKE ->read(); + nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); + nn_addr = in_EVENT_ADDRESS_NEXT ->read(); + nn_is_ds_take= false; +// nn_val = false; +// n_is_ds_take = 0; n_enable [0] = 1; - for (uint32_t i=1; i<_param->_nb_instruction; i++) - n_enable [i] = 0; + for (uint32_t i=1; i<_param->_nb_instruction; i++) + n_enable [i] = 0; } @@ -347,4 +373,7 @@ delete out_EVENT_ACK ; delete in_EVENT_ADDRESS ; + delete in_EVENT_ADDRESS_NEXT ; + delete in_EVENT_ADDRESS_NEXT_VAL ; + delete in_EVENT_IS_DS_TAKE ; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h (revision 88) @@ -91,4 +91,7 @@ public : SC_OUT(Tcontrol_t ) * out_EVENT_ACK ; public : SC_IN (Tgeneral_address_t) * in_EVENT_ADDRESS ; + public : SC_IN (Tgeneral_address_t) * in_EVENT_ADDRESS_NEXT ; + public : SC_IN (Tcontrol_t ) * in_EVENT_ADDRESS_NEXT_VAL ; + public : SC_IN (Tcontrol_t ) * in_EVENT_IS_DS_TAKE ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Parameters.h (revision 88) @@ -24,19 +24,22 @@ //-----[ fields ]------------------------------------------------------------ public : uint32_t _nb_instruction ; - public : uint32_t _size_address ; - public : uint32_t _size_branch_update_prediction; +//public : uint32_t _size_address ; +//public : uint32_t _size_branch_update_prediction; - public : uint32_t _size_instruction_ptr ; - - public : bool _have_port_instruction_ptr ; - public : bool _have_port_branch_update_prediction_id; +//public : uint32_t _size_instruction_ptr ; +// +//public : bool _have_port_instruction_ptr ; +//public : bool _have_port_branch_update_prediction_id; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_instruction, uint32_t size_address , - uint32_t size_branch_update_prediction); + uint32_t size_branch_update_prediction, + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Address_management,FUNCTION,"Begin"); +#if DEBUG_Address_management == true + log_printf(INFO,Address_management,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Address_management,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Address_management,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { // Affect output constant @@ -94,4 +100,5 @@ #endif } + log_printf(FUNC,Address_management,FUNCTION,"End"); }; @@ -104,5 +111,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp (revision 88) @@ -62,8 +62,8 @@ ALLOC_VALACK_OUT (out_ADDRESS_VAL ,VAL); ALLOC_VALACK_IN ( in_ADDRESS_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t,_param->_size_address ); - ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr ); + ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t,_param->_size_instruction_address ); + ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); + ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); } @@ -80,12 +80,12 @@ ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_address); + ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_address); + ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr); + ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); + ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); } { @@ -99,15 +99,23 @@ ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)"); - ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); - ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address); + ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1); + ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); } + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; + reg_PC_NEXT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; - reg_PC_NEXT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; - #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Address_management,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -32,8 +32,8 @@ delete out_ADDRESS_INSTRUCTION_ADDRESS ; delete [] out_ADDRESS_INSTRUCTION_ENABLE ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete out_ADDRESS_INST_IFETCH_PTR ; delete out_ADDRESS_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; delete out_PREDICT_VAL ; @@ -45,17 +45,24 @@ delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; delete [] in_PREDICT_INSTRUCTION_ENABLE ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete in_PREDICT_INST_IFETCH_PTR ; delete in_PREDICT_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; delete in_EVENT_VAL ; delete out_EVENT_ACK ; delete in_EVENT_ADDRESS ; + delete in_EVENT_ADDRESS_NEXT ; + delete in_EVENT_ADDRESS_NEXT_VAL ; + delete in_EVENT_IS_DS_TAKE ; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete reg_PC_CURRENT_INSTRUCTION_ENABLE; + delete reg_PC_NEXT_INSTRUCTION_ENABLE ; + } } - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete reg_PC_CURRENT_INSTRUCTION_ENABLE; - delete reg_PC_NEXT_INSTRUCTION_ENABLE ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_genMoore.cpp (revision 88) @@ -32,8 +32,8 @@ PORT_WRITE(out_ADDRESS_VAL ,internal_ADDRESS_VAL ); PORT_WRITE(out_ADDRESS_INSTRUCTION_ADDRESS ,reg_PC_CURRENT ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) PORT_WRITE(out_ADDRESS_INST_IFETCH_PTR ,reg_PC_CURRENT_INST_IFETCH_PTR ); PORT_WRITE(out_ADDRESS_BRANCH_STATE ,reg_PC_CURRENT_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_WRITE(out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 88) @@ -22,5 +22,6 @@ void Address_management::transition (void) { - log_printf(FUNC,Address_management,FUNCTION,"Begin"); + log_begin(Address_management,FUNCTION); + log_function(Address_management,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -28,5 +29,8 @@ // nothing is valid reg_PC_CURRENT_VAL = 0; - reg_PC_NEXT_VAL = 0; + + reg_PC_NEXT_VAL = 1; + reg_PC_NEXT = 0x100>>2; + reg_PC_NEXT_NEXT_VAL = 0; } @@ -40,8 +44,8 @@ for (uint32_t i=0; i<_param->_nb_instruction; i++) reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) reg_PC_NEXT_INST_IFETCH_PTR = PORT_READ(in_PREDICT_INST_IFETCH_PTR ); reg_PC_NEXT_BRANCH_STATE = PORT_READ(in_PREDICT_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); @@ -51,5 +55,6 @@ #ifdef STATISTICS - (*_stat_nb_transaction_predict) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_transaction_predict) ++; #endif } @@ -62,12 +67,13 @@ { #ifdef STATISTICS - if (reg_PC_CURRENT_VAL) - { - (*_stat_nb_transaction_address) ++; - - for (uint32_t i=0; i<_param->_nb_instruction; i++) - if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true) - (*_stat_sum_packet_size) ++; - } + if (usage_is_set(_usage,USE_STATISTICS)) + if (reg_PC_CURRENT_VAL) + { + (*_stat_nb_transaction_address) ++; + + for (uint32_t i=0; i<_param->_nb_instruction; i++) + if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true) + (*_stat_sum_packet_size) ++; + } #endif @@ -110,5 +116,9 @@ if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK) { - log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction"); + log_printf(TRACE,Address_management,FUNCTION," * EVENT : Transaction"); + log_printf(TRACE,Address_management,FUNCTION," * IS_DS_TAKE : %d" ,PORT_READ(in_EVENT_IS_DS_TAKE )); + log_printf(TRACE,Address_management,FUNCTION," * ADDRESS : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS ),PORT_READ(in_EVENT_ADDRESS )<<2); + log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT ),PORT_READ(in_EVENT_ADDRESS_NEXT )<<2); + log_printf(TRACE,Address_management,FUNCTION," * ADDRESS_NEXT_VAL : %d" ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL)); reg_PC_CURRENT_VAL = 0; reg_PC_NEXT_VAL = 1; @@ -118,26 +128,38 @@ // * load miss speculation : the load is execute, the event_address is the next address (also the destination of branch) // * exception : goto the first instruction of exception handler (also is not in delay slot). - reg_PC_NEXT_IS_DS_TAKE = 0; + + reg_PC_NEXT_IS_DS_TAKE = PORT_READ(in_EVENT_IS_DS_TAKE); // reg_PC_NEXT_INST_IFETCH_PTR = 0; // reg_PC_NEXT_BRANCH_STATE = BRANCH_STATE_NONE; // reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0; -// reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. -// for (uint32_t i=1; i<_param->_nb_instruction; i++) -// reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; + reg_PC_NEXT_INSTRUCTION_ENABLE [0] = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle. + for (uint32_t i=1; i<_param->_nb_instruction; i++) + reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0; - reg_PC_NEXT_NEXT_VAL = 0; // cancel all prediction (event is send at the predict unit) + reg_PC_NEXT_NEXT_VAL = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL); + reg_PC_NEXT_NEXT = PORT_READ(in_EVENT_ADDRESS_NEXT); + reg_PC_NEXT_NEXT_IS_DS_TAKE = 0;//?? + + // Note : is_ds_take = address_next_val + // Because, is not ds take, can continue in sequence + +#ifdef DEBUG_TEST + if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) + throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); +#endif #ifdef STATISTICS - (*_stat_nb_transaction_event) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_transaction_event) ++; #endif } } -#if DEBUG >= DEBUG_TRACE - log_printf(TRACE,Address_management,FUNCTION,"Address_Management : "); - log_printf(TRACE,Address_management,FUNCTION,"Current : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT); - log_printf(TRACE,Address_management,FUNCTION,"Next : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT); - log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT); +#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Address_management,FUNCTION," * Dump PC"); + log_printf(TRACE,Address_management,FUNCTION," * Current : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL , reg_PC_CURRENT_IS_DS_TAKE , reg_PC_CURRENT , reg_PC_CURRENT <<2); + log_printf(TRACE,Address_management,FUNCTION," * Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL , reg_PC_NEXT_IS_DS_TAKE , reg_PC_NEXT , reg_PC_NEXT <<2); + log_printf(TRACE,Address_management,FUNCTION," * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2); #endif @@ -145,6 +167,6 @@ end_cycle (); #endif - - log_printf(FUNC,Address_management,FUNCTION,"End"); + + log_end(Address_management,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters.cpp (revision 88) @@ -21,18 +21,25 @@ Parameters::Parameters (uint32_t nb_instruction, uint32_t size_address , - uint32_t size_branch_update_prediction) + uint32_t size_branch_update_prediction, + bool is_toplevel) { log_printf(FUNC,Address_management,FUNCTION,"Begin"); - _nb_instruction = nb_instruction ; - _size_address = size_address ; - _size_branch_update_prediction = size_branch_update_prediction; - - _size_instruction_ptr = log2(nb_instruction); - - _have_port_instruction_ptr = _size_instruction_ptr > 0; - _have_port_branch_update_prediction_id = size_branch_update_prediction > 0; + _nb_instruction = nb_instruction ; test(); + + if (is_toplevel) + { + _size_instruction_address = size_address ; + _size_depth = size_branch_update_prediction; + _size_inst_ifetch_ptr = log2(nb_instruction); + + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy(); + } + log_printf(FUNC,Address_management,FUNCTION,"End"); }; @@ -55,4 +62,12 @@ }; +#undef FUNCTION +#define FUNCTION "Address_management::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Address_management,FUNCTION,"Begin"); + log_printf(FUNC,Address_management,FUNCTION,"End"); + }; + }; // end namespace address_management }; // end namespace ifetch_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Parameters_print.cpp (revision 88) @@ -24,15 +24,19 @@ log_printf(FUNC,Address_management,FUNCTION,"Begin"); - XML xml ("address_management"); +// XML xml ("address_management"); - xml.balise_open("address_management"); - xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); - xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); - xml.balise_close(); +// xml.balise_open("address_management"); +// xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); +// // xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// // xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); +// xml.balise_close(); + +// return xml.get_body(depth); + + std::string str = ""; log_printf(FUNC,Address_management,FUNCTION,"End"); - - return xml.get_body(depth); + + return str; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Ifetch_queue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/main.cpp (revision 88) @@ -47,5 +47,7 @@ _nb_instruction , _size_branch_update_prediction , - _size_general_data ); + _size_general_data , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp (revision 88) @@ -41,4 +41,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Ifetch_queue * _Ifetch_queue = new Ifetch_queue (name.c_str(), @@ -47,5 +57,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -93,12 +103,12 @@ INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL ); INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK ); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction); @@ -106,13 +116,13 @@ INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction); INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION ); INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL ); INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK ); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); @@ -180,9 +190,9 @@ for (uint32_t i=0; i<_param->_nb_instruction; i++) in_ADDRESS_INSTRUCTION_ENABLE [i] ->write(i<=nb_inst_enable); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) in_ADDRESS_INST_IFETCH_PTR ->write(address%_param->_nb_instruction); in_ADDRESS_BRANCH_STATE ->write(address%SIZE_BRANCH_STATE); - if (_param->_have_port_branch_update_prediction_id) - in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_branch_update_prediction); + if (_param->_have_port_depth) + in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth); // ===== @@ -241,5 +251,5 @@ list_wait_decod.push_back(address); -// list_req_icache.insert(, entry_t((_param->_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); +// list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); uint32_t cycle = ((rand()%100)_have_port_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); + list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); LABEL(" * list_req_icache : %d",list_req_icache.size()); address += 4*_param->_nb_instruction; @@ -292,8 +302,8 @@ TEST(Tgeneral_data_t ,out_DECOD_ADDRESS ->read(), addr); TEST(Tbranch_state_t ,out_DECOD_BRANCH_STATE ->read(),addr%SIZE_BRANCH_STATE); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR ->read(),addr%_param->_nb_instruction); - if (_param->_have_port_branch_update_prediction_id) - TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_branch_update_prediction); + if (_param->_have_port_depth) + TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth); if ((addr % modulo_iberr) == 0) TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_BUS_ERROR); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Parameters.h (revision 88) @@ -26,21 +26,24 @@ public : uint32_t _size_queue ; public : uint32_t _nb_instruction ; - public : uint32_t _size_branch_update_prediction ; - public : uint32_t _size_general_data ; +//public : uint32_t _size_branch_update_prediction ; +//public : uint32_t _size_general_data ; - public : uint32_t _size_queue_ptr ; - public : uint32_t _size_instruction_ptr ; +//public : uint32_t _size_queue_ptr ; +//public : uint32_t _size_instruction_ptr ; - public : bool _have_port_queue_ptr ; - public : bool _have_port_instruction_ptr ; - public : bool _have_port_branch_update_prediction_id; +//public : bool _have_port_queue_ptr ; +//public : bool _have_port_instruction_ptr ; +//public : bool _have_port_branch_update_prediction_id; //-----[ methods ]----------------------------------------------------------- - public : Parameters (uint32_t _size_queue , - uint32_t _nb_instruction , - uint32_t _size_branch_update_prediction, - uint32_t _size_general_data ); + public : Parameters (uint32_t size_queue , + uint32_t nb_instruction , + uint32_t size_branch_update_prediction, + uint32_t size_general_data , + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue.cpp (revision 88) @@ -38,5 +38,11 @@ log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); - log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation"); +#if DEBUG_Ifetch_queue == true + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation"),_name.c_str()); allocation ( @@ -47,7 +53,7 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { - log_printf(INFO,Ifetch_queue,FUNCTION,"Allocation of statistics"); + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str()); statistics_allocation(param_statistics); @@ -56,8 +62,8 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl - log_printf(INFO,Ifetch_queue,FUNCTION,"Generate the vhdl"); + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str()); vhdl(); @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { // constant output @@ -75,5 +81,5 @@ PORT_WRITE(out_EVENT_RESET_ACK, internal_EVENT_RESET_ACK); - log_printf(INFO,Ifetch_queue,FUNCTION,"Method - transition"); + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - transition"),_name.c_str()); SC_METHOD (transition); @@ -85,5 +91,5 @@ # endif - log_printf(INFO,Ifetch_queue,FUNCTION,"Method - genMoore"); + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Method - genMoore"),_name.c_str()); SC_METHOD (genMoore); @@ -107,5 +113,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); @@ -113,5 +119,5 @@ #endif - log_printf(INFO,Ifetch_queue,FUNCTION,"Deallocation"); + log_printf(INFO,Ifetch_queue,FUNCTION,_("<%s> Deallocation"),_name.c_str()); deallocation (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_allocation.cpp (revision 88) @@ -62,9 +62,9 @@ ALLOC_VALACK_IN ( in_ADDRESS_VAL ,VAL); ALLOC_VALACK_OUT(out_ADDRESS_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_general_data ); - ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_instruction_ptr ); - ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); - ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_queue_ptr ); + ALLOC_SIGNAL_IN ( in_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_IN ( in_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); + ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC_SIGNAL_IN ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC_SIGNAL_OUT(out_ADDRESS_IFETCH_QUEUE_ID ,"ifetch_queue_id" ,Tifetch_queue_ptr_t,_param->_size_ifetch_queue_ptr); } @@ -86,9 +86,9 @@ ALLOC_INTERFACE("decod",OUT, EAST, "Send instruction bundle to the decod's stage."); - ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_general_data ); - ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr ); - ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); - ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); - ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch ); + ALLOC_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address ); + ALLOC_SIGNAL_OUT(out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); + ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); + ALLOC_SIGNAL_OUT(out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC_SIGNAL_OUT(out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); } @@ -99,5 +99,5 @@ ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); ALLOC_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_queue_ptr ); + ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr); ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t,_param->_size_icache_error); } @@ -117,14 +117,18 @@ // ~~~~~[ Internal ] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction]; - - _queue = new ifetch_queue_entry_t * [_param->_size_queue]; - for (uint32_t i=0;i<_param->_size_queue; i++) - _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction); + if (usage_is_set(_usage,USE_SYSTEMC)) + { + internal_DECOD_VAL = new Tcontrol_t [_param->_nb_instruction]; + + _queue = new ifetch_queue_entry_t * [_param->_size_queue]; + for (uint32_t i=0;i<_param->_size_queue; i++) + _queue [i] = new ifetch_queue_entry_t (_param->_nb_instruction); + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -30,12 +30,12 @@ delete in_ADDRESS_VAL ; delete out_ADDRESS_ACK ; - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) delete out_ADDRESS_IFETCH_QUEUE_ID ; delete [] in_ADDRESS_INSTRUCTION_ENABLE ; delete in_ADDRESS_INSTRUCTION_ADDRESS ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete in_ADDRESS_INST_IFETCH_PTR ; delete in_ADDRESS_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; delete [] out_DECOD_VAL ; @@ -43,13 +43,13 @@ delete [] out_DECOD_INSTRUCTION ; delete out_DECOD_ADDRESS ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete out_DECOD_INST_IFETCH_PTR ; delete out_DECOD_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; delete out_DECOD_EXCEPTION ; delete in_ICACHE_RSP_VAL ; delete out_ICACHE_RSP_ACK ; - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) delete in_ICACHE_RSP_PACKET_ID ; delete [] in_ICACHE_RSP_INSTRUCTION ; @@ -58,8 +58,13 @@ delete out_EVENT_RESET_ACK ; } + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete internal_DECOD_VAL; + delete [] _queue; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete internal_DECOD_VAL; - delete [] _queue; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_genMoore.cpp (revision 88) @@ -29,5 +29,5 @@ PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); @@ -45,8 +45,8 @@ PORT_WRITE(out_DECOD_ADDRESS , _queue[reg_PTR_READ]->_address ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) PORT_WRITE(out_DECOD_INST_IFETCH_PTR , _queue[reg_PTR_READ]->_inst_ifetch_ptr ); PORT_WRITE(out_DECOD_BRANCH_STATE , _queue[reg_PTR_READ]->_branch_state ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID, _queue[reg_PTR_READ]->_branch_update_prediction_id); PORT_WRITE(out_DECOD_EXCEPTION , _queue[reg_PTR_READ]->_exception ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Ifetch_queue_transition.cpp (revision 88) @@ -22,5 +22,5 @@ void Ifetch_queue::transition (void) { - log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); + log_begin(Ifetch_queue,FUNCTION); if (PORT_READ(in_NRESET) == 0) @@ -34,7 +34,4 @@ else { - log_printf(NONE,Ifetch_queue,FUNCTION," * KANE address : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS)); - - // ========================================================== // =====[ ADDRESS ]========================================== @@ -47,5 +44,6 @@ #ifdef STATISTICS - (*_sum_transaction_address) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_sum_transaction_address) ++; #endif @@ -54,5 +52,6 @@ Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); #ifdef STATISTICS - (*_sum_inst_enable) += enable; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_sum_inst_enable) += enable; #endif _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; @@ -60,7 +59,7 @@ _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS ); - _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_instruction_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; + _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE ); - _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_branch_update_prediction_id)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; + _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; @@ -95,5 +94,5 @@ if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) { - Tpacket_t ptr = (_param->_have_port_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; + Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; for (uint32_t i=0; i<_param->_nb_instruction; i++) @@ -137,35 +136,36 @@ } -#if DEBUG >= DEBUG_TRACE - log_printf(TRACE,Ifetch_queue,FUNCTION,"Dump ifetch_queue"); - log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); - log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); +#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); + log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); + log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); for (uint32_t i=0; i<_param->_size_queue; i++) { - log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); + log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] %s %.8x %d - %d %d %d", i, toString(_queue [i]->_state).c_str(), _queue [i]->_address,_queue [i]->_inst_ifetch_ptr,_queue [i]->_branch_state,_queue [i]->_branch_update_prediction_id,_queue [i]->_exception); for (uint32_t j=0; j<_param->_nb_instruction; j++) - log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); + log_printf(TRACE,Ifetch_queue,FUNCTION," * %d %.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); } #endif #ifdef STATISTICS - for (uint32_t i=0; i<_param->_size_queue; i++) - switch (_queue[i]->_state) - { - case IFETCH_QUEUE_STATE_EMPTY : break; - case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; - case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; - case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; - default : break; - } + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_size_queue; i++) + switch (_queue[i]->_state) + { + case IFETCH_QUEUE_STATE_EMPTY : break; + case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; + case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; + case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; + default : break; + } #endif } - + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); #endif - log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); + log_end(Ifetch_queue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters.cpp (revision 88) @@ -22,5 +22,6 @@ uint32_t nb_instruction , uint32_t size_branch_update_prediction, - uint32_t size_general_data ) + uint32_t size_general_data , + bool is_toplevel) { log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); @@ -28,15 +29,23 @@ _size_queue = size_queue ; _nb_instruction = nb_instruction ; - _size_branch_update_prediction = size_branch_update_prediction; - _size_general_data = size_general_data ; +// _size_branch_update_prediction = size_branch_update_prediction; +// _size_general_data = size_general_data ; - _size_queue_ptr = log2(size_queue); - _size_instruction_ptr = log2(nb_instruction); + test(); - _have_port_queue_ptr = _size_queue_ptr > 0; - _have_port_instruction_ptr = _size_instruction_ptr > 0; - _have_port_branch_update_prediction_id = size_branch_update_prediction > 0; - - test(); + if (is_toplevel) + { + _size_instruction_address = size_general_data; + _size_ifetch_queue_ptr = log2(size_queue); + _size_inst_ifetch_ptr = log2(nb_instruction); + _size_depth = size_branch_update_prediction; + + _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0; + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy (); + } + log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); }; @@ -59,4 +68,12 @@ }; +#undef FUNCTION +#define FUNCTION "Ifetch_queue::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Ifetch_queue,FUNCTION,"Begin"); + log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); + }; + }; // end namespace ifetch_queue }; // end namespace ifetch_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_msg_error.cpp (revision 88) @@ -28,15 +28,6 @@ if (_size_queue == 1) - test.warning("To best perfomance, size_queue must be > 1."); + test.warning("To best perfomance, size_queue must be > 1.\n"); -// if (not _have_port_queue_ptr) -// test.information("They have not port '..._QUEUE_PTR'."); - -// if (not _have_port_instruction_ptr) -// test.information("They have not port '..._INST_IFETCH_PTR'."); - -// if (not _have_port_branch_update_prediction_id) -// test.information("They have not port '..._BRANCH_UPDATE_PREDICTION_ID'."); - log_printf(FUNC,Ifetch_queue,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/src/Parameters_print.cpp (revision 88) @@ -29,6 +29,6 @@ xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); - xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); - xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); +// xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); +// xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Ifetch_unit_Glue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/main.cpp (revision 88) @@ -37,5 +37,7 @@ { morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Parameters - (_size_address); + (_size_address, + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Ifetch_unit_Glue * _Ifetch_unit_Glue = new Ifetch_unit_Glue (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/include/Parameters.h (revision 88) @@ -24,10 +24,13 @@ { //-----[ fields ]------------------------------------------------------------ - public : uint32_t _size_address; +//public : uint32_t _size_address; //-----[ methods ]----------------------------------------------------------- - public : Parameters (uint32_t size_address); + public : Parameters (uint32_t size_address, + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); +#if DEBUG_Ifetch_unit_Glue == true + log_printf(INFO,Ifetch_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,8 +72,9 @@ #ifdef SYSTEMC - PORT_WRITE(out_ICACHE_REQ_TYPE,ICACHE_TYPE_LOAD); + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Write constant + PORT_WRITE(out_ICACHE_REQ_TYPE,ICACHE_TYPE_LOAD); - if (_usage & USE_SYSTEMC) - { # if defined(STATISTICS) or defined(VHDL_TESTBENCH) log_printf(INFO,Ifetch_unit_Glue,FUNCTION,"Method - transition"); @@ -140,5 +147,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_allocation.cpp (revision 88) @@ -67,7 +67,7 @@ ALLOC_SIGNAL_IN ( in_ICACHE_REQ_QUEUE_ACK ,"queue_ack" ,Tcontrol_t,1); ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t,_param->_size_icache_type); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Taddress_t,_param->_size_address); - ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_address); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS ,"queue_address" ,Taddress_t,_param->_size_address); + ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_ICACHE_REQ_ADDRESS_ADDRESS,"address_address",Taddress_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_ICACHE_REQ_QUEUE_ADDRESS ,"queue_address" ,Taddress_t,_param->_size_instruction_address); } @@ -87,5 +87,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Ifetch_unit_Glue_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters.cpp (revision 88) @@ -19,11 +19,18 @@ #undef FUNCTION #define FUNCTION "Ifetch_unit_Glue::Parameters" - Parameters::Parameters (uint32_t size_address) + Parameters::Parameters (uint32_t size_address, + bool is_toplevel) { log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); - _size_address = size_address; + test(); - test(); + if (is_toplevel) + { + _size_instruction_address = size_address; + + copy (); + } + log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End"); }; @@ -46,4 +53,12 @@ }; +#undef FUNCTION +#define FUNCTION "Ifetch_unit_Glue::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"Begin"); + log_printf(FUNC,Ifetch_unit_Glue,FUNCTION,"End"); + }; + }; // end namespace ifetch_unit_glue }; // end namespace ifetch_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue/src/Parameters_print.cpp (revision 88) @@ -27,5 +27,5 @@ xml.balise_open("ifetch_unit_glue"); - xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end(); +// xml.singleton_begin("size_address"); xml.attribut("value",toString(_size_address)); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Ifetch_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/main.cpp (revision 88) @@ -47,5 +47,7 @@ _nb_instruction , _size_branch_update_prediction , - _size_general_data ); + _size_general_data , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/SelfTest/src/test.cpp (revision 88) @@ -7,5 +7,5 @@ */ -#define NB_ITERATION 128 +#define NB_ITERATION 1024 #define CYCLE_MAX (128*NB_ITERATION) @@ -40,4 +40,13 @@ #endif + Tusage_t _usage = USE_ALL; +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Ifetch_unit * _Ifetch_unit = new Ifetch_unit (name.c_str(), @@ -46,5 +55,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -92,4 +101,7 @@ ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t ); + ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t ); + ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); /******************************************************** @@ -105,5 +117,5 @@ INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_REQ_ACK ); //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_THREAD_ID ); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_PACKET_ID ); INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_REQ_ADDRESS ); @@ -112,5 +124,5 @@ INSTANCE_SC_SIGNAL (_Ifetch_unit,out_ICACHE_RSP_ACK ); //INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_THREAD_ID ); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) INSTANCE_SC_SIGNAL (_Ifetch_unit, in_ICACHE_RSP_PACKET_ID ); INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); @@ -124,8 +136,8 @@ INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_PC_NEXT_IS_DS_TAKE ); INSTANCE1_SC_SIGNAL(_Ifetch_unit, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Ifetch_unit, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); INSTANCE1_SC_SIGNAL(_Ifetch_unit,out_DECOD_VAL ,_param->_nb_instruction); @@ -134,8 +146,8 @@ //INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_CONTEXT_ID ); INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_ADDRESS ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_STATE ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); INSTANCE_SC_SIGNAL (_Ifetch_unit,out_DECOD_EXCEPTION ); @@ -143,4 +155,7 @@ INSTANCE_SC_SIGNAL (_Ifetch_unit,out_EVENT_ACK ); INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS ); + INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT ); + INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_ADDRESS_NEXT_VAL ); + INSTANCE_SC_SIGNAL (_Ifetch_unit, in_EVENT_IS_DS_TAKE ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -178,7 +193,7 @@ Tcontrol_t nn_val = false; - Tgeneral_data_t c_addr = 0x100; - Tgeneral_data_t n_addr = 0x100; - Tgeneral_data_t nn_addr = 0x100; + Tgeneral_data_t c_addr = 0x100>>2; + Tgeneral_data_t n_addr = 0x100>>2; + Tgeneral_data_t nn_addr = 0x100>>2; Tcontrol_t c_enable [_param->_nb_instruction]; @@ -218,12 +233,12 @@ TEST(Tcontrol_t,out_DECOD_VAL [i]->read(), 0); - LABEL("Send Reset"); - do - { - in_EVENT_VAL ->write(1); - in_EVENT_ADDRESS->write(n_addr); - SC_START(1); - } while (out_EVENT_ACK->read() == false); - in_EVENT_VAL ->write(0); +// LABEL("Send Reset"); +// do +// { +// in_EVENT_VAL ->write(1); +// in_EVENT_ADDRESS->write(n_addr); +// SC_START(1); +// } while (out_EVENT_ACK->read() == false); +// in_EVENT_VAL ->write(0); n_val = 1; @@ -270,6 +285,10 @@ // EVENT - in_EVENT_VAL ->write((rand()%100)write(0x100); + in_EVENT_VAL ->write((rand()%100)write(0x77); + in_EVENT_ADDRESS_NEXT ->write(0x171); + Tcontrol_t is_ds_take = rand(); + in_EVENT_ADDRESS_NEXT_VAL->write(is_ds_take); + in_EVENT_IS_DS_TAKE ->write(is_ds_take); // ICACHE_REQ @@ -305,5 +324,5 @@ LABEL("ICACHE_REQ : Transaction accepted"); - Tpacket_t packet = (_param->_have_port_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; + Tpacket_t packet = (_param->_have_port_ifetch_queue_ptr)?out_ICACHE_REQ_PACKET_ID->read():0; Taddress_t address = out_ICACHE_REQ_ADDRESS->read(); @@ -344,8 +363,8 @@ if (find) { - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) TEST(Tinst_ifetch_ptr_t, out_DECOD_INST_IFETCH_PTR ->read(), 0); TEST(Tbranch_state_t , out_DECOD_BRANCH_STATE ->read(), 0); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) TEST(Tprediction_ptr_t , out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(), 0); TEST(Texception_t , out_DECOD_EXCEPTION ->read(), 0); @@ -404,8 +423,10 @@ c_val = false; n_val = true; - nn_val = false; - - n_addr = in_EVENT_ADDRESS->read(); - n_is_ds_take = 0; + + n_addr = in_EVENT_ADDRESS->read(); + n_is_ds_take = in_EVENT_IS_DS_TAKE->read(); + nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); + nn_addr = in_EVENT_ADDRESS_NEXT ->read(); + nn_is_ds_take = 0; n_enable [0] = 1; @@ -496,4 +517,7 @@ delete out_EVENT_ACK ; delete in_EVENT_ADDRESS ; + delete in_EVENT_ADDRESS_NEXT ; + delete in_EVENT_ADDRESS_NEXT_VAL ; + delete in_EVENT_IS_DS_TAKE ; delete param_cache; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h (revision 88) @@ -109,4 +109,7 @@ public : SC_OUT(Tcontrol_t ) * out_EVENT_ACK ; public : SC_IN (Tgeneral_address_t) * in_EVENT_ADDRESS ; + public : SC_IN (Tgeneral_address_t) * in_EVENT_ADDRESS_NEXT ; + public : SC_IN (Tcontrol_t ) * in_EVENT_ADDRESS_NEXT_VAL ; + public : SC_IN (Tcontrol_t ) * in_EVENT_IS_DS_TAKE ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h (revision 88) @@ -28,13 +28,13 @@ public : uint32_t _size_queue ; public : uint32_t _nb_instruction ; - public : uint32_t _size_address ; - public : uint32_t _size_branch_update_prediction; - - public : uint32_t _size_queue_ptr ; - public : uint32_t _size_instruction_ptr ; - - public : bool _have_port_queue_ptr ; - public : bool _have_port_instruction_ptr ; - public : bool _have_port_branch_update_prediction_id; +//public : uint32_t _size_address ; +//public : uint32_t _size_branch_update_prediction; +// +//public : uint32_t _size_queue_ptr ; +//public : uint32_t _size_instruction_ptr ; +// +//public : bool _have_port_queue_ptr ; +//public : bool _have_port_instruction_ptr ; +//public : bool _have_port_branch_update_prediction_id; public :morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param_address_management; @@ -46,7 +46,11 @@ uint32_t nb_instruction , uint32_t size_branch_update_prediction, - uint32_t size_address ); + uint32_t size_address , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit.cpp (revision 88) @@ -37,4 +37,10 @@ log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); +#if DEBUG_Ifetch_unit == true + log_printf(INFO,Ifetch_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Ifetch_unit,FUNCTION,"Allocation"); @@ -46,5 +52,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Ifetch_unit,FUNCTION,"Allocation of statistics"); @@ -55,5 +61,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -65,5 +71,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Ifetch_unit,FUNCTION,"Method - transition"); @@ -89,5 +95,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp (revision 88) @@ -57,11 +57,11 @@ // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request."); + ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request.")); ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_queue_ptr ); - ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_address ); + ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); + ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); } @@ -69,14 +69,14 @@ // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons."); + ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons.")); ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); //ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_queue_ptr ); + ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); } { - ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction); + ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); @@ -85,19 +85,19 @@ // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons."); + ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc.")); ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_address); - ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_address); + ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_address); + ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr); + ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); - } - { - ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction); + ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + } + { + ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); @@ -106,15 +106,15 @@ // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit."); + ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit.")); //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_address); - ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_instruction_ptr); + ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_branch_update_prediction); + ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); } { - ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction); + ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); @@ -125,9 +125,12 @@ // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC_INTERFACE("event",IN , NORTH, "Event interface."); - - ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); - ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); - ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address); + ALLOC_INTERFACE("event",IN , NORTH, _("Event interface.")); + + ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); + ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); } @@ -137,5 +140,5 @@ { name = _name+"_address_management"; - std::cout << "Create : " << name << std::endl; + log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management @@ -156,5 +159,5 @@ { name = _name+"_ifetch_queue"; - std::cout << "Create : " << name << std::endl; + log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue @@ -175,5 +178,5 @@ { name = _name+"_ifetch_unit_glue"; - std::cout << "Create : " << name << std::endl; + log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue @@ -200,5 +203,5 @@ { src = _name+"_address_management"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -225,10 +228,10 @@ } - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" , dest, "in_ADDRESS_INST_IFETCH_PTR" ); COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" , dest, "in_ADDRESS_BRANCH_STATE" ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); @@ -281,10 +284,10 @@ PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE" ,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR" ,dest, "in_PREDICT_INST_IFETCH_PTR" ); PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE" ,dest, "in_PREDICT_BRANCH_STATE" ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID" ,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"); @@ -306,5 +309,8 @@ dest = _name; - PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS"); + PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" ); + PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" ); + PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" ); + PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" ); } } @@ -315,5 +321,5 @@ { src = _name+"_ifetch_queue"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -335,5 +341,5 @@ #endif - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , dest,"out_ICACHE_REQ_PACKET_ID" ); @@ -386,8 +392,8 @@ PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" ); - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" ); PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" ); - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID"); PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" ); @@ -404,5 +410,5 @@ PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" ); PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" ); - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID"); PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" ); @@ -437,5 +443,5 @@ { src = _name+"_ifetch_unit_glue"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -490,9 +496,11 @@ // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (DEBUG_Ifetch_unit == true) - _component->test_map(); - -#ifdef POSITION - _component->generate_file(); +#if DEBUG_Ifetch_unit == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_deallocation.cpp (revision 88) @@ -22,5 +22,5 @@ log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -30,5 +30,5 @@ delete in_ICACHE_REQ_ACK ; //delete out_ICACHE_REQ_THREAD_ID ; - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) delete out_ICACHE_REQ_PACKET_ID ; delete out_ICACHE_REQ_ADDRESS ; @@ -38,5 +38,5 @@ delete out_ICACHE_RSP_ACK ; //delete in_ICACHE_RSP_THREAD_ID ; - if (_param->_have_port_queue_ptr) + if (_param->_have_port_ifetch_queue_ptr) delete in_ICACHE_RSP_PACKET_ID ; delete [] in_ICACHE_RSP_INSTRUCTION ; @@ -51,8 +51,8 @@ delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; delete [] in_PREDICT_INSTRUCTION_ENABLE ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete in_PREDICT_INST_IFETCH_PTR ; delete in_PREDICT_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ; @@ -62,8 +62,8 @@ //delete out_DECOD_CONTEXT_ID ; delete out_DECOD_ADDRESS ; - if (_param->_have_port_instruction_ptr) + if (_param->_have_port_inst_ifetch_ptr) delete out_DECOD_INST_IFETCH_PTR ; delete out_DECOD_BRANCH_STATE ; - if (_param->_have_port_branch_update_prediction_id) + if (_param->_have_port_depth) delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; delete out_DECOD_EXCEPTION ; @@ -72,4 +72,7 @@ delete out_EVENT_ACK ; delete in_EVENT_ADDRESS ; + delete in_EVENT_ADDRESS_NEXT ; + delete in_EVENT_ADDRESS_NEXT_VAL ; + delete in_EVENT_IS_DS_TAKE ; } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_end_cycle.cpp (revision 88) @@ -24,5 +24,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -30,5 +31,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters.cpp (revision 88) @@ -21,5 +21,7 @@ uint32_t nb_instruction , uint32_t size_branch_update_prediction, - uint32_t size_address ) + uint32_t size_address , + bool is_toplevel + ) { log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); @@ -27,13 +29,6 @@ _size_queue = size_queue ; _nb_instruction = nb_instruction ; - _size_branch_update_prediction = size_branch_update_prediction; - _size_address = size_address ; - - _size_queue_ptr = log2(size_queue); - _size_instruction_ptr = log2(nb_instruction); - - _have_port_queue_ptr = _size_queue_ptr > 0; - _have_port_instruction_ptr = _size_instruction_ptr > 0; - _have_port_branch_update_prediction_id = size_branch_update_prediction > 0; +// _size_branch_update_prediction = size_branch_update_prediction; +// _size_address = size_address ; test(); @@ -50,5 +45,19 @@ _param_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue:: Parameters (size_address); - + + if (is_toplevel) + { + _size_instruction_address = size_address; + _size_ifetch_queue_ptr = log2(size_queue); + _size_inst_ifetch_ptr = log2(nb_instruction); + _size_depth = size_branch_update_prediction; + + _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0; + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy (); + } + log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); }; @@ -74,4 +83,17 @@ }; +#undef FUNCTION +#define FUNCTION "Ifetch_unit::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); + + COPY(_param_address_management); + COPY(_param_ifetch_queue ); + COPY(_param_ifetch_unit_glue ); + + log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); + }; + }; // end namespace ifetch_unit }; // end namespace front_end Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Parameters_print.cpp (revision 88) @@ -23,16 +23,21 @@ log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin"); - XML xml ("ifetch_unit"); +// XML xml ("ifetch_unit"); - xml.balise_open("ifetch_unit"); - xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); - xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); - xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); - xml.balise_close(); +// xml.balise_open("ifetch_unit"); +// xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); +// xml.singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction )); xml.singleton_end(); +// // xml.singleton_begin("size_branch_update_prediction"); xml.attribut("value",toString(_size_branch_update_prediction)); xml.singleton_end(); +// // xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.balise_close(); + +// return xml.get_body(depth); + + std::string str = ""; log_printf(FUNC,Ifetch_unit,FUNCTION,"End"); + + return str; - return xml.get_body(depth); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libFront_end.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Makefile.deps (revision 88) @@ -0,0 +1,73 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Front_end = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Ifetch_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Makefile.deps +endif +ifndef Prediction_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Makefile.deps +endif +ifndef Decod_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Makefile.deps +endif +ifndef Context_State +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Context_State/Makefile.deps +endif +ifndef Front_end_Glue +include $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Front_end_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end + +#-----[ Library ]------------------------------------------ + +Front_end_LIBRARY = -lFront_end \ + $(Ifetch_unit_LIBRARY) \ + $(Prediction_unit_LIBRARY) \ + $(Decod_unit_LIBRARY) \ + $(Context_State_LIBRARY) \ + $(Front_end_Glue_LIBRARY) \ + $(Behavioural_LIBRARY) + +Front_end_DIR_LIBRARY = -L$(Front_end_DIR)/lib \ + $(Ifetch_unit_DIR_LIBRARY) \ + $(Prediction_unit_DIR_LIBRARY) \ + $(Decod_unit_DIR_LIBRARY) \ + $(Context_State_DIR_LIBRARY) \ + $(Front_end_Glue_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Front_end_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Ifetch_unit_library; \ + $(MAKE) Prediction_unit_library; \ + $(MAKE) Decod_unit_library; \ + $(MAKE) Context_State_library; \ + $(MAKE) Front_end_Glue_library; \ + $(MAKE) --directory=$(Front_end_DIR) --makefile=Makefile; + +Front_end_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Ifetch_unit_library_clean; \ + $(MAKE) Prediction_unit_library_clean; \ + $(MAKE) Decod_unit_library_clean; \ + $(MAKE) Context_State_library_clean; \ + $(MAKE) Front_end_Glue_library_clean; \ + $(MAKE) --directory=$(Front_end_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Branch_Target_Buffer_Glue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/main.cpp (revision 88) @@ -55,5 +55,7 @@ _nb_inst_predict , _nb_inst_decod , - _nb_inst_update ); + _nb_inst_update , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Branch_Target_Buffer_Glue * _Branch_Target_Buffer_Glue = new Branch_Target_Buffer_Glue (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/include/Parameters.h (revision 88) @@ -29,5 +29,5 @@ public : uint32_t _size_buffer ; public : uint32_t _associativity ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t _nb_inst_predict ; public : uint32_t _nb_inst_decod ; @@ -51,7 +51,11 @@ uint32_t nb_inst_predict , uint32_t nb_inst_decod , - uint32_t nb_inst_update ); + uint32_t nb_inst_update , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); +#if DEBUG_Branch_Target_Buffer_Glue == true + log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { # if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -104,74 +110,74 @@ } -# ifdef SYSTEMCASS_SPECIFIC - // List dependency information - - for (uint32_t i=0; i<_param->_nb_inst_predict; i++) - { - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_HIT [i])) (*(in_PREDICT_REGISTER_HIT [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_HIT [i])) (*(in_PREDICT_SORT_INDEX [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_ADDRESS_SRC [i])) (*(in_PREDICT_REGISTER_ADDRESS_SRC [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_ADDRESS_SRC [i])) (*(in_PREDICT_SORT_INDEX [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_ADDRESS_DEST [i])) (*(in_PREDICT_REGISTER_ADDRESS_DEST [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_ADDRESS_DEST [i])) (*(in_PREDICT_SORT_INDEX [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_CONDITION [i])) (*(in_PREDICT_REGISTER_CONDITION [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_CONDITION [i])) (*(in_PREDICT_SORT_INDEX [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_LAST_TAKE [i])) (*(in_PREDICT_REGISTER_LAST_TAKE [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_LAST_TAKE [i])) (*(in_PREDICT_SORT_INDEX [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_IS_ACCURATE [i])) (*(in_PREDICT_REGISTER_IS_ACCURATE [i][j])); - if (_param->_have_port_victim) - (*(out_PREDICT_IS_ACCURATE [i])) (*(in_PREDICT_SORT_INDEX [i])); - - - (*(out_PREDICT_ACK [i])) (*(in_PREDICT_REGISTER_ACK [i])); - if (_param->_have_port_victim) - { - (*(out_PREDICT_ACK [i])) (*(in_PREDICT_SORT_VAL [i])); - (*(out_PREDICT_ACK [i])) (*(in_PREDICT_VICTIM_ACK [i])); - } - - (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_VAL [i])); - if (_param->_have_port_victim) - { - (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_SORT_VAL [i])); - (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_VICTIM_ACK [i])); - } - - if (_param->_have_port_victim) - { - (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_VAL [i])); - (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_REGISTER_ACK [i])); - (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_SORT_VAL [i])); - - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_VICTIM_HIT [i])) (*(in_PREDICT_REGISTER_HIT [i][j])); - (*(out_PREDICT_VICTIM_HIT [i])) (*(in_PREDICT_SORT_INDEX [i])); - - if (not _param->_is_full_associative) - { - for (uint32_t j=0; j<_param->_associativity; j++) - (*(out_PREDICT_VICTIM_ADDRESS [i])) (*(in_PREDICT_REGISTER_ADDRESS_SRC [i][j])); - (*(out_PREDICT_VICTIM_ADDRESS [i])) (*(in_PREDICT_SORT_INDEX [i])); - } - (*(out_PREDICT_VICTIM_INDEX [i])) (*(in_PREDICT_SORT_INDEX [i])); - } - } -# endif +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information + +// for (uint32_t i=0; i<_param->_nb_inst_predict; i++) +// { +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_HIT [i])) (*(in_PREDICT_REGISTER_HIT [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_HIT [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_ADDRESS_SRC [i])) (*(in_PREDICT_REGISTER_ADDRESS_SRC [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_ADDRESS_SRC [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_ADDRESS_DEST [i])) (*(in_PREDICT_REGISTER_ADDRESS_DEST [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_ADDRESS_DEST [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_CONDITION [i])) (*(in_PREDICT_REGISTER_CONDITION [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_CONDITION [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_LAST_TAKE [i])) (*(in_PREDICT_REGISTER_LAST_TAKE [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_LAST_TAKE [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_IS_ACCURATE [i])) (*(in_PREDICT_REGISTER_IS_ACCURATE [i][j])); +// if (_param->_have_port_victim) +// (*(out_PREDICT_IS_ACCURATE [i])) (*(in_PREDICT_SORT_INDEX [i])); + + +// (*(out_PREDICT_ACK [i])) (*(in_PREDICT_REGISTER_ACK [i])); +// if (_param->_have_port_victim) +// { +// (*(out_PREDICT_ACK [i])) (*(in_PREDICT_SORT_VAL [i])); +// (*(out_PREDICT_ACK [i])) (*(in_PREDICT_VICTIM_ACK [i])); +// } + +// (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_VAL [i])); +// if (_param->_have_port_victim) +// { +// (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_SORT_VAL [i])); +// (*(out_PREDICT_REGISTER_VAL [i])) (*(in_PREDICT_VICTIM_ACK [i])); +// } + +// if (_param->_have_port_victim) +// { +// (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_VAL [i])); +// (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_REGISTER_ACK [i])); +// (*(out_PREDICT_VICTIM_VAL [i])) (*(in_PREDICT_SORT_VAL [i])); + +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_VICTIM_HIT [i])) (*(in_PREDICT_REGISTER_HIT [i][j])); +// (*(out_PREDICT_VICTIM_HIT [i])) (*(in_PREDICT_SORT_INDEX [i])); + +// if (not _param->_is_full_associative) +// { +// for (uint32_t j=0; j<_param->_associativity; j++) +// (*(out_PREDICT_VICTIM_ADDRESS [i])) (*(in_PREDICT_REGISTER_ADDRESS_SRC [i][j])); +// (*(out_PREDICT_VICTIM_ADDRESS [i])) (*(in_PREDICT_SORT_INDEX [i])); +// } +// (*(out_PREDICT_VICTIM_INDEX [i])) (*(in_PREDICT_SORT_INDEX [i])); +// } +// } +// # endif log_printf(INFO,Branch_Target_Buffer_Glue,FUNCTION,"Method - genMealy_decod"); @@ -271,5 +277,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_allocation.cpp (revision 88) @@ -65,6 +65,6 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_ACK , "ack" ,Tcontrol_t , 1); ALLOC1_SIGNAL_OUT(out_PREDICT_HIT , "hit" ,Tcontrol_t , 1); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC , "address_src" ,Tgeneral_data_t , _param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST , "address_dest" ,Tgeneral_data_t , _param->_size_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC , "address_src" ,Tgeneral_data_t , _param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST , "address_dest" ,Tgeneral_data_t , _param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_PREDICT_CONDITION , "condition" ,Tbranch_condition_t, _param->_size_branch_condition); ALLOC1_SIGNAL_OUT(out_PREDICT_LAST_TAKE , "last_take" ,Tcontrol_t , 1); @@ -89,6 +89,6 @@ ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_HIT ,"register_hit" ,Tcontrol_t ,1); - ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_SRC ,"register_address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_DEST,"register_address_dest",Tgeneral_data_t ,_param->_size_address); + ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_SRC ,"register_address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_ADDRESS_DEST,"register_address_dest",Tgeneral_data_t ,_param->_size_instruction_address); ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_CONDITION ,"register_condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC2_SIGNAL_IN ( in_PREDICT_REGISTER_LAST_TAKE ,"register_last_take" ,Tcontrol_t ,1); @@ -104,5 +104,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_ACK ,"ack" ,Tcontrol_t ,1); if (not _param->_is_full_associative) - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_DECOD_REGISTER_VAL ,"register_val" ,Tcontrol_t ,1); @@ -124,5 +124,5 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t ,1); if (not _param->_is_full_associative) - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_UPDATE_REGISTER_VAL ,"register_val" ,Tcontrol_t ,1); @@ -140,5 +140,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp (revision 88) @@ -27,5 +27,6 @@ uint32_t nb_inst_predict , uint32_t nb_inst_decod , - uint32_t nb_inst_update ) + uint32_t nb_inst_update , + bool is_toplevel) { log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); @@ -34,5 +35,5 @@ _size_buffer = size_buffer ; _associativity = associativity ; - _size_address = size_address ; +// _size_address = size_address ; _nb_inst_predict = nb_inst_predict ; _nb_inst_decod = nb_inst_decod ; @@ -50,4 +51,12 @@ test(); + + if (is_toplevel) + { + _size_instruction_address = size_address; + + copy(); + } + log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); }; @@ -70,4 +79,12 @@ }; +#undef FUNCTION +#define FUNCTION "Branch_Target_Buffer_Glue::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); + log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); + }; + }; // end namespace branch_target_buffer_glue }; // end namespace branch_target_buffer Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters_print.cpp (revision 88) @@ -31,5 +31,5 @@ xml.singleton_begin("size_buffer "); xml.attribut("value",toString(_size_buffer )); xml.singleton_end(); xml.singleton_begin("associativity "); xml.attribut("value",toString(_associativity )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("nb_inst_predict "); xml.attribut("value",toString(_nb_inst_predict )); xml.singleton_end(); xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/Makefile.deps (revision 88) @@ -16,13 +16,13 @@ #-----[ Directory ]---------------------------------------- -Branch_Target_Buffer_Register_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register +Branch_Target_Buffer_Register_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register #-----[ Library ]------------------------------------------ Branch_Target_Buffer_Register_LIBRARY = -lBranch_Target_Buffer_Register \ - $(Behavioural_LIBRARY) + $(Behavioural_LIBRARY) -Branch_Target_Buffer_Register_DIR_LIBRARY = -L$(Branch_Target_Buffer_Register_DIR)/lib \ - $(Behavioural_DIR_LIBRARY) +Branch_Target_Buffer_Register_DIR_LIBRARY = -L$(Branch_Target_Buffer_Register_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) #-----[ Rules ]-------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Branch_Target_Buffer_Register_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_min.cfg (revision 88) @@ -4,5 +4,5 @@ 1 1 *4 # size_buffer 1 1 *4 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 1 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_mono_context.cfg (revision 88) @@ -4,5 +4,5 @@ 16 16 *4 # size_buffer 2 16 *4 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/config_multi_context.cfg (revision 88) @@ -7,5 +7,5 @@ 8 64 *4 # size_buffer 4 8 *2 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h (revision 88) @@ -0,0 +1,67 @@ +#ifndef test_BTB +#define test_BTB + + class entry_t + { + public : Tcontrol_t _val ; + public : Tcontext_t _context ; + public : Tcontrol_t _address_dest_val; + public : Tgeneral_data_t _address_src ; + public : Tgeneral_data_t _address_dest ; + public : Tbranch_condition_t _condition ; + public : Tcontrol_t _last_take ; + public : Tcounter_t _accurate ; + + public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, + Tgeneral_data_t addr_test, + Tcontext_t context) + { + Tgeneral_data_t addr_src_offset = (_address_src >> _param->_shift_offset)&_param->_mask_offset; + Tgeneral_data_t addr_src_index = (_address_src >> _param->_shift_bank )&_param->_mask_bank ; + Tgeneral_data_t addr_src_tag = (_address_src >> _param->_shift_tag ); + + Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset; + Tgeneral_data_t addr_test_index = (addr_test >> _param->_shift_bank )&_param->_mask_bank ; + Tgeneral_data_t addr_test_tag = (addr_test >> _param->_shift_tag ); + + bool is_hit = ( (_val == 1 ) and + (_context == context ) and + (addr_test_tag == addr_src_tag ) and + (addr_test_index == addr_src_index ) and + (addr_test_offset <= addr_src_offset )); + + LABEL("address_src (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset); + LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit); + return is_hit; + } + + public : void print (void) + { + LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", + _val , + _context , + _address_src , + _address_dest_val, + _address_dest , + _condition , + _last_take , + _accurate ); + } + + }; + +Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, + Tgeneral_data_t index) +{ + Tgeneral_data_t addr_tag = (rand()%(_param->_associativity)) << _param->_shift_tag ; + Tgeneral_data_t addr_index = (index &_param->_mask_bank ) << _param->_shift_bank ; + Tgeneral_data_t addr_offset = (rand()&_param->_mask_offset ) << _param->_shift_offset; + + LABEL("gen_addr (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset); + + return (addr_tag | + addr_index | + addr_offset ); +} + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/main.cpp (revision 88) @@ -67,5 +67,7 @@ _nb_inst_predict, _nb_inst_decod , - _nb_inst_commit ); + _nb_inst_commit , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/src/test.cpp (revision 88) @@ -14,71 +14,5 @@ #include "Common/include/BitManipulation.h" #include "Behavioural/include/Allocation.h" - - class entry_t - { - public : Tcontrol_t _val ; - public : Tcontext_t _context ; - public : Tcontrol_t _address_dest_val; - public : Tgeneral_data_t _address_src ; - public : Tgeneral_data_t _address_dest ; - public : Tbranch_condition_t _condition ; - public : Tcontrol_t _last_take ; - public : Tcounter_t _accurate ; - - public : bool hit (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, - Tgeneral_data_t addr_test, - Tcontext_t context) - { - Tgeneral_data_t addr_src_offset = (_address_src >> _param->_shift_offset)&_param->_mask_offset; - Tgeneral_data_t addr_src_index = (_address_src >> _param->_shift_bank )&_param->_mask_bank ; - Tgeneral_data_t addr_src_tag = (_address_src >> _param->_shift_tag ); - - Tgeneral_data_t addr_test_offset = (addr_test >> _param->_shift_offset)&_param->_mask_offset; - Tgeneral_data_t addr_test_index = (addr_test >> _param->_shift_bank )&_param->_mask_bank ; - Tgeneral_data_t addr_test_tag = (addr_test >> _param->_shift_tag ); - - bool is_hit = ( (_val == 1 ) and - (_context == context ) and - (addr_test_tag == addr_src_tag ) and - (addr_test_index == addr_src_index ) and - (addr_test_offset <= addr_src_offset )); - - LABEL("address_src (tag, index, offset) : %.8x %.8x %.8x",addr_src_tag, addr_src_index, addr_src_offset); - LABEL("address_test (tag, index, offset) : %.8x %.8x %.8x - hit : %d",addr_test_tag, addr_test_index, addr_test_offset, is_hit); - return is_hit; - } - - public : void print (void) - { - LABEL("%d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", - _val , - _context , - _address_src , - _address_dest_val, - _address_dest , - _condition , - _last_take , - _accurate ); - - } - - }; - - - -Tgeneral_data_t gen_addr (morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters * _param, - Tgeneral_data_t index) -{ - Tgeneral_data_t addr_tag = (rand()%(2*_param->_associativity)) << _param->_shift_tag ; - Tgeneral_data_t addr_index = (index &_param->_mask_bank ) << _param->_shift_bank ; - Tgeneral_data_t addr_offset = (rand()&_param->_mask_offset ) << _param->_shift_offset; - - LABEL("gen_addr (tag, index, offset) : %.8x %.8x %.8x",addr_tag, addr_index, addr_offset); - - return (addr_tag | - addr_index | - addr_offset ); -} - +#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h" void test (string name, @@ -90,4 +24,14 @@ morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Branch_Target_Buffer_Register * _Branch_Target_Buffer_Register = new Branch_Target_Buffer_Register @@ -97,5 +41,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -269,5 +213,5 @@ in_DECOD_VICTIM [i]->write(rand()%_param->_associativity); in_DECOD_CONTEXT_ID [i]->write(rand()%_param->_nb_context); - in_DECOD_ADDRESS_SRC [i]->write(addr); + in_DECOD_ADDRESS_SRC [i]->write( addr); in_DECOD_ADDRESS_DEST [i]->write(~addr); in_DECOD_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); @@ -284,5 +228,5 @@ in_UPDATE_VICTIM [i]->write(rand()%_param->_associativity); in_UPDATE_CONTEXT_ID [i]->write(rand()%_param->_nb_context); - in_UPDATE_ADDRESS_SRC [i]->write(addr); + in_UPDATE_ADDRESS_SRC [i]->write( addr); in_UPDATE_ADDRESS_DEST [i]->write(~addr); in_UPDATE_CONDITION [i]->write((addr&1)?BRANCH_CONDITION_FLAG_SET:BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); @@ -334,14 +278,19 @@ bool hit = false; - - for (uint32_t j=0; j<_param->_associativity; j++) - hit |= ((tab_old[j]._val == 1) and - (tab_old[j]._context == in_DECOD_CONTEXT_ID [i]->read()) and - (tab_old[j]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); + + Tptr_t k; + for (k=0; k<_param->_associativity; k++) + { + hit |= ((tab_old[k]._val == 1) and + (tab_old[k]._context == in_DECOD_CONTEXT_ID [i]->read()) and + (tab_old[k]._address_src == in_DECOD_ADDRESS_SRC [i]->read())); + + if (hit) + break; + } if (not hit) { - Tptr_t k = in_DECOD_VICTIM [i]->read(); - + k = in_DECOD_VICTIM [i]->read(); LABEL(" * miss"); LABEL(" * victim : %d",k); @@ -354,12 +303,17 @@ tab[k]._condition = in_DECOD_CONDITION [i]->read(); tab[k]._last_take = in_DECOD_LAST_TAKE [i]->read(); - //tab[k]._accurate = _param->_first_accurate_if_hit; + tab[k]._accurate =(in_DECOD_IS_ACCURATE [i]->read())?_param->_first_accurate_if_hit:_param->_first_accurate_if_miss; } else { - LABEL(" * miss"); - } - - TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); + LABEL(" * hit"); + } + + if (_param->_have_port_victim) + { + TEST(Tcontrol_t, out_DECOD_HIT [i]->read(), hit); + if (hit) + TEST(Tptr_t , out_DECOD_HIT_INDEX [i]->read(), k); + } } @@ -373,15 +327,12 @@ bool hit = false; - Tptr_t k = 0; - for (uint32_t j=0; j<_param->_associativity; j++) - { - hit |= ((tab_old[j]._val == 1) and - (tab_old[j]._context == in_UPDATE_CONTEXT_ID [i]->read()) and - (tab_old[j]._address_src == in_UPDATE_ADDRESS_SRC [i]->read())); + Tptr_t k; + for (k=0; k<_param->_associativity; k++) + { + hit |= ((tab_old[k]._val == 1) and + (tab_old[k]._context == in_UPDATE_CONTEXT_ID [i]->read()) and + (tab_old[k]._address_src == in_UPDATE_ADDRESS_SRC [i]->read())); if (hit) - { - k = j; - break; - } + break; } @@ -400,5 +351,5 @@ tab[k]._condition = in_UPDATE_CONDITION [i]->read(); tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); - //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; + tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; } else @@ -414,8 +365,26 @@ tab[k]._condition = in_UPDATE_CONDITION [i]->read(); tab[k]._last_take = in_UPDATE_LAST_TAKE [i]->read(); - //tab[k]._accurate = (in_UPDATE_MISS_PREDICTION [i]->read())?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; - } - - TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); + + + Tcounter_t accurate_old = tab[k]._accurate; + // hit : increase accurate + // miss : decrease accurate + Tcounter_t accurate_new = (in_UPDATE_MISS_PREDICTION [i]->read())?((accurate_old>0)?(accurate_old-1):accurate_old):((accurate_old<_param->_accurate_max)?(accurate_old+1):accurate_old); + + // test if accurate go to the threshold + if ((accurate_old >= _param->_accurate_limit) and + (accurate_new < _param->_accurate_limit)) + accurate_new = 0; + + + tab[k]._accurate = accurate_new; + } + + if (_param->_have_port_victim) + { + TEST(Tcontrol_t, out_UPDATE_HIT [i]->read(), hit); + if (hit) + TEST(Tptr_t , out_UPDATE_HIT_INDEX [i]->read(), k); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/include/Parameters.h (revision 88) @@ -31,5 +31,5 @@ public : uint32_t _size_buffer ; public : uint32_t _associativity ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t _size_counter ; public : uint32_t _nb_inst_predict; @@ -38,8 +38,8 @@ public : uint32_t _size_bank ; - public : uint32_t _size_context_id; +//public : uint32_t _size_context_id; public : uint32_t _size_victim ; - public : bool _have_port_context_id; +//public : bool _have_port_context_id; public : bool _have_port_victim ; @@ -65,7 +65,11 @@ uint32_t nb_inst_predict, uint32_t nb_inst_decod , - uint32_t nb_inst_update ); + uint32_t nb_inst_update , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); +#if DEBUG_Branch_Target_Buffer_Register == true + log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Branch_Target_Buffer_Register,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { // Constant @@ -108,34 +114,34 @@ } -# ifdef SYSTEMCASS_SPECIFIC - // List dependency information - for (uint32_t i=0; i<_param->_nb_inst_predict; i++) - for (uint32_t j=0; j<_param->_associativity; j++) - { - (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - - (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - - (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - - (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - - (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - - (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_ADDRESS [i])); - if (_param->_have_port_context_id) - (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); - } -# endif +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// for (uint32_t i=0; i<_param->_nb_inst_predict; i++) +// for (uint32_t j=0; j<_param->_associativity; j++) +// { +// (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_HIT [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); + +// (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_ADDRESS_SRC [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); + +// (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_ADDRESS_DEST [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); + +// (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_CONDITION [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); + +// (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_LAST_TAKE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); + +// (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_ADDRESS [i])); +// if (_param->_have_port_context_id) +// (*(out_PREDICT_IS_ACCURATE [i][j])) (*(in_PREDICT_CONTEXT_ID [i])); +// } +// # endif if (_param->_have_port_victim) @@ -215,5 +221,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_allocation.cpp (revision 88) @@ -64,5 +64,5 @@ ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); { @@ -70,6 +70,6 @@ ALLOC2_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); - ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_address); + ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC2_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); ALLOC2_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC2_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -91,6 +91,6 @@ } ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -112,6 +112,6 @@ } ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_state); ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -119,4 +119,6 @@ } + if (usage_is_set(_usage,USE_SYSTEMC)) + { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ reg_BTB = new btb_entry_t * [_param->_size_bank]; @@ -133,9 +135,11 @@ internal_UPDATE_NUM_BANK = new uint32_t [_param->_nb_inst_update]; internal_UPDATE_NUM_ENTRY = new uint32_t [_param->_nb_inst_update]; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -42,9 +42,10 @@ delete [] in_DECOD_VAL ; delete [] out_DECOD_ACK ; + if (_param->_have_port_victim) + { delete [] out_DECOD_HIT ; - if (_param->_have_port_victim) delete [] out_DECOD_HIT_INDEX ; - if (_param->_have_port_victim) delete [] in_DECOD_VICTIM ; + } if (_param->_have_port_context_id) delete [] in_DECOD_CONTEXT_ID ; @@ -57,9 +58,10 @@ delete [] in_UPDATE_VAL ; delete [] out_UPDATE_ACK ; + if (_param->_have_port_victim) + { delete [] out_UPDATE_HIT ; - if (_param->_have_port_victim) delete [] out_UPDATE_HIT_INDEX ; - if (_param->_have_port_victim) delete [] in_UPDATE_VICTIM ; + } if (_param->_have_port_context_id) delete [] in_UPDATE_CONTEXT_ID ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_decod.cpp (revision 88) @@ -22,5 +22,6 @@ void Branch_Target_Buffer_Register::genMealy_decod (void) { - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Register,FUNCTION); + log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_decod; i++) @@ -55,5 +56,5 @@ } - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Register,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_predict.cpp (revision 88) @@ -22,8 +22,10 @@ void Branch_Target_Buffer_Register::genMealy_predict (void) { - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); - + log_begin(Branch_Target_Buffer_Register,FUNCTION); + log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); + for (uint32_t i=0; i<_param->_nb_inst_predict; i++) { + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * PREDICT [%d]",i); Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; Tgeneral_data_t address = PORT_READ(in_PREDICT_ADDRESS [i]); @@ -33,5 +35,5 @@ Tgeneral_data_t address_offset = (address >> _param->_shift_offset)&_param->_mask_offset; -// log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_ (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset); + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * address_ (tag, bank, offset) : %.8x %.8x %.8x",address_tag,num_bank, address_offset); for (uint32_t j=0; j<_param->_associativity; j++) @@ -46,5 +48,5 @@ (address_src_offset >= address_offset)); -// log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit); + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * address_src (tag, bank, offset) : %.8x %.8x %.8x - hit : %d",address_src_tag,num_bank,address_src_offset, hit); // Hit : @@ -62,5 +64,5 @@ } - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Register,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_genMealy_update.cpp (revision 88) @@ -22,5 +22,6 @@ void Branch_Target_Buffer_Register::genMealy_update (void) { - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Register,FUNCTION); + log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_update; i++) @@ -55,5 +56,5 @@ } - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Register,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp (revision 88) @@ -22,5 +22,6 @@ void Branch_Target_Buffer_Register::transition (void) { - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Register,FUNCTION); + log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -83,4 +84,6 @@ if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) { + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * UPDATE [%d]",i); + bool hit = internal_UPDATE_HIT [i]; uint32_t num_bank = internal_UPDATE_NUM_BANK [i]; @@ -89,4 +92,8 @@ // detect new branch !!! insert in branch target buffer + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * hit : %d",hit); + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_bank : %d",num_bank ); + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * num_entry : %d",num_entry); + Tcounter_t accurate_new = 0; @@ -123,39 +130,52 @@ accurate_new = (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit; - reg_BTB[num_bank][num_entry]._val = 1; - reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; - reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); - reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); - reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); - } +// reg_BTB[num_bank][num_entry]._val = 1; +// reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; +// reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); +// reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); +// reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); + reg_BTB[num_bank][num_entry]._address_dest_val = 0; + } // =====[ All Case ] - if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) - { - reg_BTB[num_bank][num_entry]._address_dest_val = 1; - reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); - } +// if (reg_BTB[num_bank][num_entry]._address_dest_val == 0) +// { +// reg_BTB[num_bank][num_entry]._address_dest_val = 1; +// reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); +// } + reg_BTB[num_bank][num_entry]._val = 1; + reg_BTB[num_bank][num_entry]._context = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0; + reg_BTB[num_bank][num_entry]._address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); + reg_BTB[num_bank][num_entry]._condition = PORT_READ(in_UPDATE_CONDITION [i]); + reg_BTB[num_bank][num_entry]._last_take = PORT_READ(in_UPDATE_LAST_TAKE [i]); + reg_BTB[num_bank][num_entry]._address_dest_val = 1; + reg_BTB[num_bank][num_entry]._address_dest = PORT_READ(in_UPDATE_ADDRESS_DEST [i]); reg_BTB[num_bank][num_entry]._accurate = accurate_new; } +#if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," * Dump BTB"); for (uint32_t i=0; i<_param->_size_bank; i++) for (uint32_t j=0; j<_param->_associativity; j++) - log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"[%.4d][%.4d] %d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", + log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION," [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", i,j, reg_BTB [i][j]._val , reg_BTB [i][j]._context , reg_BTB [i][j]._address_src , + reg_BTB [i][j]._address_src <<2, reg_BTB [i][j]._address_dest_val, reg_BTB [i][j]._address_dest , + reg_BTB [i][j]._address_dest<<2 , reg_BTB [i][j]._condition , reg_BTB [i][j]._last_take , reg_BTB [i][j]._accurate ); +#endif } - + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); #endif - log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Register,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp (revision 88) @@ -30,5 +30,6 @@ uint32_t nb_inst_predict, uint32_t nb_inst_decod , - uint32_t nb_inst_update ) + uint32_t nb_inst_update , + bool is_toplevel) { log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); @@ -38,5 +39,4 @@ _size_buffer = size_buffer ; _associativity = associativity ; - _size_address = size_address ; _size_counter = size_counter ; _nb_inst_predict = nb_inst_predict; @@ -45,8 +45,6 @@ _size_bank = size_buffer/associativity; - _size_context_id = log2(nb_context); _size_victim = log2(associativity); - _have_port_context_id = (_size_context_id > 0); _have_port_victim = (_size_victim > 0); @@ -81,4 +79,13 @@ test(); + if (is_toplevel) + { + _size_instruction_address = size_address ; + _size_context_id = log2(nb_context); + _have_port_context_id = (_size_context_id > 0); + + copy (); + } + log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); }; @@ -101,4 +108,12 @@ }; +#undef FUNCTION +#define FUNCTION "Branch_Target_Buffer_Register::copy" + void Parameters::copy () + { + log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin"); + log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); + }; + }; // end namespace branch_target_buffer_register }; // end namespace branch_target_buffer Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_msg_error.cpp (revision 88) @@ -29,21 +29,21 @@ if (_size_counter < 2 ) - test.error("size_counter must be >= 2."); + test.error(_("size_counter must be >= 2.\n")); if ((_associativity == 0) or (_associativity > _size_buffer)) - test.error("associativity must be > 0 and <= size_buffer."); + test.error(_("associativity must be > 0 and <= size_buffer.\n")); if (_associativity == 1) // special case : full assoc and direct map ... also we print direct map - test.information("Branch Target Buffer is Direct Map"); + test.information(_("Branch Target Buffer is Direct Map.\n")); else if (_associativity == _size_buffer) - test.information("Branch Target Buffer is Full associative"); + test.information(_("Branch Target Buffer is Full associative.\n")); else - test.information("Branch Target Buffer is Semi associative"); + test.information(_("Branch Target Buffer is Semi associative.\n")); for (uint32_t i=0; i<_nb_context; i++) if (_associativity < (_nb_instruction[i]/2)) - test.error("associativity must be >= nb_instruction["+toString(i)+"]/2."); + test.error(toString(_("associativity must be >= nb_instruction[%d]/2.\n"),i)); log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters_print.cpp (revision 88) @@ -31,5 +31,5 @@ xml.singleton_begin("size_buffer "); xml.attribut("value",toString(_size_buffer )); xml.singleton_end(); xml.singleton_begin("associativity "); xml.attribut("value",toString(_associativity )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end(); xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Branch_Target_Buffer_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_min.cfg (revision 88) @@ -4,5 +4,5 @@ 1 1 *4 # size_buffer 1 1 *4 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 1 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_mono_context.cfg (revision 88) @@ -4,5 +4,5 @@ 16 16 *4 # size_buffer 2 16 *4 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/config_multi_context.cfg (revision 88) @@ -7,5 +7,5 @@ 8 64 *4 # size_buffer 4 8 *2 # associativity -32 32 *2 # size_address +30 30 *2 # size_address 2 2 +1 # size_counter 1 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/main.cpp (revision 88) @@ -70,5 +70,7 @@ _nb_inst_decod , _nb_inst_commit , - _victim_scheme ); + _victim_scheme , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp (revision 88) @@ -7,10 +7,11 @@ */ -#define NB_ITERATION 1024 -#define CYCLE_MAX (128*NB_ITERATION) +#define NB_ITERATION 1 +#define CYCLE_MAX (10000*NB_ITERATION) #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/include/test.h" #include "Common/include/Test.h" #include "Behavioural/include/Allocation.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h" void test (string name, @@ -20,6 +21,16 @@ #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); Branch_Target_Buffer * _Branch_Target_Buffer = new Branch_Target_Buffer @@ -29,6 +40,6 @@ #endif _param, - USE_ALL); - + _usage); + #ifdef SYSTEMC /********************************************************************* @@ -110,4 +121,15 @@ msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + // Initialisation + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const int32_t percent_transaction_decod = 75; + const int32_t percent_transaction_predict = 75; + + SC_START(0); + Time * _time = new Time(); @@ -116,27 +138,118 @@ ********************************************************/ - // Initialisation - - const uint32_t seed = 0; -//const uint32_t seed = static_cast(time(NULL)); - - srand(seed); - - SC_START(0); - LABEL("Initialisation"); - - LABEL("Reset"); - in_NRESET->write(0); - SC_START(5); - in_NRESET->write(1); - - LABEL("Loop of Test"); - - for (uint32_t iteration=0; iterationwrite(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + Taddress_t btb_address [_param->_associativity]; + Tcontext_t btb_context [_param->_associativity]; + + for (uint32_t iteration=0; iteration_associativity) + uint32_t nb_request; + uint32_t index = rand()&_param->_param_branch_target_buffer_register->_mask_bank; + Tcontext_t context = rand()&_param->_nb_context; + + for (uint32_t j=0; j<_param->_associativity; j++) +// btb_val [j] = false; + btb_address [j] = static_cast(-1); + + { + uint32_t associativity = 0; + + while (associativity < _param->_associativity) + { + for (uint32_t j=0; j<_param->_nb_inst_decod; j++) + { + Taddress_t address = ((associativity << _param->_param_branch_target_buffer_register->_shift_tag) | + (index << _param->_param_branch_target_buffer_register->_shift_bank)| + (0)); + + in_DECOD_VAL [j]->write(((rand()%100)_associativity)); + in_DECOD_CONTEXT_ID [j]->write(context); + in_DECOD_ADDRESS_SRC [j]->write( address ); + in_DECOD_ADDRESS_DEST [j]->write(~address ); + in_DECOD_CONDITION [j]->write(BRANCH_CONDITION_FLAG_SET); + in_DECOD_LAST_TAKE [j]->write(address&1); + in_DECOD_MISS_PREDICTION [j]->write(1); + in_DECOD_IS_ACCURATE [j]->write(1); + } + + SC_START(0); + + for (uint32_t j=0; j<_param->_nb_inst_decod; j++) + if (in_DECOD_VAL [j]->read() and out_DECOD_ACK [j]->read()) + { + LABEL("DECOD [%d] Transaction Accepted",j); + + Taddress_t address = in_DECOD_ADDRESS_SRC [j]->read(); + + btb_address[associativity] = address; + btb_context[associativity] = context; + associativity ++; + } + + SC_START(1); + } + } + + nb_request = 0; + + while (nb_request < NB_REQUEST) + { + for (uint32_t i=0; i<_param->_nb_inst_predict; i++) + { + in_PREDICT_VAL [i]->write(((rand()%100)write(rand()&_param->_nb_context); + in_PREDICT_ADDRESS [i]->write(gen_addr(_param->_param_branch_target_buffer_register,index)); + } + + SC_START(0); + + for (uint32_t i=0; i<_param->_nb_inst_predict; i++) + if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read()) + { + LABEL("PREDICT [%d] Transaction Accepted",i); + + Tcontrol_t hit = out_PREDICT_HIT [i]->read(); + Taddress_t address = in_PREDICT_ADDRESS [i]->read(); + Taddress_t address_src = out_PREDICT_ADDRESS_SRC [i]->read(); + Taddress_t address_dest = out_PREDICT_ADDRESS_DEST [i]->read(); + + Taddress_t tag = address >> _param->_param_branch_target_buffer_register->_shift_tag; + + Tcontrol_t my_hit = false; + Tcontrol_t my_addr; + + for (uint32_t i=0; i<_param->_associativity; i++) + { + Taddress_t btb_address [_param->_associativity]; + Tcontext_t btb_context [_param->_associativity]; + } + + if (hit) + { + TEST(Tbranch_condition_t,out_PREDICT_CONDITION [i]->read(),BRANCH_CONDITION_FLAG_SET); + TEST(Tcontrol_t ,out_PREDICT_LAST_TAKE [i]->read(),address_src&1); +// TEST(Tcontrol_t ,out_PREDICT_IS_ACCURATE [i]->read(), ); + } + + nb_request ++; + } + + SC_START(1); + } + } + } /******************************************************** Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/include/Parameters.h (revision 88) @@ -33,5 +33,5 @@ public : uint32_t _size_buffer ; public : uint32_t _associativity ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t _size_counter ; public : uint32_t _nb_inst_predict; @@ -41,8 +41,8 @@ public : uint32_t _size_bank ; - public : uint32_t _size_context_id; +//public : uint32_t _size_context_id; public : uint32_t _size_victim ; - public : bool _have_port_context_id; +//public : bool _have_port_context_id; public : bool _have_component_victim; public : bool _is_full_associative; @@ -63,7 +63,11 @@ uint32_t nb_inst_decod , uint32_t nb_inst_update , - Tvictim_t victim_scheme ); + Tvictim_t victim_scheme , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer.cpp (revision 88) @@ -40,4 +40,10 @@ log_printf(INFO,Branch_Target_Buffer,FUNCTION,"Allocation"); +#if DEBUG_Branch_Target_Buffer == true + log_printf(INFO,Branch_Target_Buffer,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + allocation ( #ifdef STATISTICS @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Branch_Target_Buffer,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,7 +72,7 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { - log_printf(INFO,Branch_Target_Buffer,FUNCTION,"Method - transition"); + log_printf(INFO,Branch_Target_Buffer,FUNCTION,_("Method - transition")); SC_METHOD (transition); @@ -90,5 +96,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_allocation.cpp (revision 88) @@ -64,8 +64,8 @@ ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_DEST,"address_dest",Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_PREDICT_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_OUT(out_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -80,6 +80,6 @@ ALLOC1_VALACK_OUT(out_DECOD_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_IN ( in_DECOD_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -95,6 +95,6 @@ ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_SRC ,"address_src" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS_DEST ,"address_dest" ,Tgeneral_data_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_IN ( in_UPDATE_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -590,8 +590,12 @@ } // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -// _component->test_map(); - -#ifdef POSITION - _component->generate_file(); + +#if DEBUG_Branch_Target_Buffer == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_allocation.cpp (revision 88) @@ -34,5 +34,6 @@ _stat->add_stat(_component_victim ->_stat); } - _stat->add_stat(_component_branch_target_buffer_glue ->_stat); + +// _stat->add_stat(_component_branch_target_buffer_glue ->_stat); _stat->add_stat(_component_branch_target_buffer_register->_stat); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Branch_Target_Buffer_statistics_deallocation.cpp (revision 88) @@ -1,2 +1,3 @@ + #ifdef STATISTICS /* Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters.cpp (revision 88) @@ -29,5 +29,6 @@ uint32_t nb_inst_decod , uint32_t nb_inst_update , - Tvictim_t victim_scheme ) + Tvictim_t victim_scheme , + bool is_toplevel) { log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"Begin"); @@ -37,5 +38,4 @@ _size_buffer = size_buffer ; _associativity = associativity ; - _size_address = size_address ; _size_counter = size_counter ; _nb_inst_predict = nb_inst_predict; @@ -45,11 +45,11 @@ _size_bank = size_buffer/associativity; - _size_context_id = log2(nb_context); _size_victim = log2(associativity); - _have_port_context_id = (_size_context_id > 0); _have_component_victim = (_size_victim > 0); _is_full_associative = _size_bank == 1; uint32_t nb_access = nb_inst_predict + nb_inst_decod + nb_inst_update; + + test(); if (_have_component_victim) @@ -78,9 +78,9 @@ _size_buffer , _associativity , - _size_address , + size_address , _nb_inst_predict , _nb_inst_decod , _nb_inst_update ); - + _param_branch_target_buffer_register = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer::branch_target_buffer_register::Parameters (_nb_context , @@ -88,5 +88,5 @@ _size_buffer , _associativity , - _size_address , + size_address , _size_counter , _nb_inst_predict, @@ -94,5 +94,13 @@ _nb_inst_update ); - test(); + if (is_toplevel) + { + _size_instruction_address = size_address ; + _size_context_id = log2(nb_context); + _have_port_context_id = (_size_context_id > 0); + + copy (); + } + log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"End"); }; @@ -125,4 +133,23 @@ }; + +#undef FUNCTION +#define FUNCTION "Branch_Target_Buffer::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"Begin"); + + if (_have_component_victim) + { + COPY(_param_sort); + COPY(_param_victim); + } + COPY(_param_branch_target_buffer_glue); + COPY(_param_branch_target_buffer_register); + + log_printf(FUNC,Branch_Target_Buffer,FUNCTION,"End"); + }; + + }; // end namespace branch_target_buffer }; // end namespace prediction_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/src/Parameters_print.cpp (revision 88) @@ -30,5 +30,5 @@ xml.singleton_begin("size_buffer "); xml.attribut("value",toString(_size_buffer )); xml.singleton_end(); xml.singleton_begin("associativity "); xml.attribut("value",toString(_associativity )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("size_counter "); xml.attribut("value",toString(_size_counter )); xml.singleton_end(); xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Direction_Glue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/main.cpp (revision 88) @@ -49,5 +49,7 @@ _nb_inst_update , _size_address , - _size_history ); + _size_history , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/SelfTest/src/test.cpp (revision 88) @@ -24,4 +24,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Direction_Glue * _Direction_Glue = new Direction_Glue (name.c_str(), @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -139,5 +149,5 @@ { in_PREDICT_VAL [i]->write(rand()%2); - in_PREDICT_ADDRESS_SRC [i]->write(range(rand(),_param->_size_address)); + in_PREDICT_ADDRESS_SRC [i]->write(range(rand(),_param->_size_instruction_address)); in_PREDICT_STATIC [i]->write(rand()%2); in_PREDICT_LAST_TAKE [i]->write(rand()%2); @@ -150,5 +160,5 @@ { in_UPDATE_VAL [i]->write(rand()%2); - in_UPDATE_ADDRESS [i]->write(range(rand(),_param->_size_address)); + in_UPDATE_ADDRESS [i]->write(range(rand(),_param->_size_instruction_address)); in_UPDATE_HISTORY [i]->write(range(rand(),_param->_size_history)); in_UPDATE_DIRECTION [i]->write(rand()%2); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/include/Parameters.h (revision 88) @@ -29,5 +29,5 @@ public : uint32_t _nb_inst_predict ; public : uint32_t _nb_inst_update ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t _size_history ; @@ -40,7 +40,11 @@ uint32_t nb_inst_update , uint32_t size_address , - uint32_t size_history ); + uint32_t size_history , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue.cpp (revision 88) @@ -39,4 +39,11 @@ log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); + +#if DEBUG_Direction_Glue == true + log_printf(INFO,Direction_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Direction_Glue,FUNCTION,"Allocation"); @@ -48,5 +55,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Direction_Glue,FUNCTION,"Allocation of statistics"); @@ -57,5 +64,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +74,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { bool need_genmealy_predict = true; @@ -238,5 +245,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_allocation.cpp (revision 88) @@ -63,5 +63,5 @@ ALLOC1_SIGNAL_IN ( in_PREDICT_VAL ,"val" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_PREDICT_ACK ,"ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_STATIC ,"static" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t,1); @@ -72,5 +72,5 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_PREDICTOR_ADDRESS_SRC,"predictor_address_src",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_PREDICTOR_ADDRESS_SRC,"predictor_address_src",Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_IN ( in_PREDICT_PREDICTOR_DIRECTION ,"predictor_direction" ,Tcontrol_t,1); @@ -84,5 +84,5 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_VAL ,"val" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_UPDATE_ACK ,"ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION ,"direction" ,Tcontrol_t,1); @@ -91,14 +91,15 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_VAL ,"predictor_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTOR_ACK ,"predictor_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_ADDRESS ,"predictor_address" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_HISTORY ,"predictor_history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_OUT(out_UPDATE_PREDICTOR_DIRECTION,"predictor_direction",Tcontrol_t,1); } } - + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Direction_Glue_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters.cpp (revision 88) @@ -23,5 +23,6 @@ uint32_t nb_inst_update , uint32_t size_address , - uint32_t size_history ) + uint32_t size_history , + bool is_toplevel ) { log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); @@ -30,5 +31,4 @@ _nb_inst_predict = nb_inst_predict ; _nb_inst_update = nb_inst_update ; - _size_address = size_address ; switch (predictor_scheme) @@ -58,4 +58,12 @@ test(); + + if (is_toplevel) + { + _size_instruction_address = size_address; + + copy(); + } + log_printf(FUNC,Direction_Glue,FUNCTION,"End"); }; @@ -78,4 +86,14 @@ }; +#undef FUNCTION +#define FUNCTION "Direction_Glue::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Direction_Glue,FUNCTION,"Begin"); + log_printf(FUNC,Direction_Glue,FUNCTION,"End"); + }; + + + }; // end namespace direction_glue }; // end namespace direction Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue/src/Parameters_print.cpp (revision 88) @@ -31,5 +31,5 @@ xml.singleton_begin("nb_inst_predict "); xml.attribut("value",toString(_nb_inst_predict )); xml.singleton_end(); xml.singleton_begin("nb_inst_update "); xml.attribut("value",toString(_nb_inst_update )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("size_history "); xml.attribut("value",toString(_size_history )); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Direction_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/main.cpp (revision 88) @@ -79,5 +79,7 @@ _pht_size_counter , _pht_nb_counter , - _pht_size_address_share); + _pht_size_address_share, + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/SelfTest/src/test.cpp (revision 88) @@ -24,4 +24,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Direction * _Direction = new Direction (name.c_str(), @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -110,5 +120,5 @@ { in_PREDICT_VAL [i]->write(rand()%2); - in_PREDICT_ADDRESS_SRC [i]->write(range(rand(),_param->_size_address)); + in_PREDICT_ADDRESS_SRC [i]->write(range(rand(),_param->_size_instruction_address)); in_PREDICT_STATIC [i]->write(rand()%2); in_PREDICT_LAST_TAKE [i]->write(rand()%2); @@ -118,5 +128,5 @@ { in_UPDATE_VAL [i]->write(rand()%2); - in_UPDATE_ADDRESS [i]->write(range(rand(),_param->_size_address)); + in_UPDATE_ADDRESS [i]->write(range(rand(),_param->_size_instruction_address)); in_UPDATE_HISTORY [i]->write(range(rand(),_param->_size_history)); in_UPDATE_DIRECTION [i]->write(rand()%2); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/include/Parameters.h (revision 88) @@ -30,5 +30,5 @@ public : uint32_t _nb_inst_predict ; public : uint32_t _nb_inst_update ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : bool _have_bht [3]; public : uint32_t _bht_size_shifter [3]; @@ -57,8 +57,12 @@ uint32_t pht_size_counter [3], uint32_t pht_nb_counter [3], - uint32_t pht_size_address_share [3]); + uint32_t pht_size_address_share [3], + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Direction,FUNCTION,"Begin"); +#if DEBUG_Direction == true + log_printf(INFO,Direction,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Direction,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Direction,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Direction,FUNCTION,"Method - transition"); @@ -90,5 +96,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_allocation.cpp (revision 88) @@ -63,5 +63,5 @@ ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_SRC,"address_src",Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_SRC,"address_src",Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_STATIC ,"static" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_PREDICT_LAST_TAKE ,"last_take" ,Tcontrol_t,1); @@ -76,5 +76,5 @@ ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_HISTORY ,"history" ,Thistory_t,_param->_size_history); ALLOC1_SIGNAL_IN ( in_UPDATE_DIRECTION,"direction",Tcontrol_t,1); @@ -182,5 +182,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Direction,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Direction_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters.cpp (revision 88) @@ -29,5 +29,6 @@ uint32_t pht_size_counter [3], uint32_t pht_nb_counter [3], - uint32_t pht_size_address_share [3]) + uint32_t pht_size_address_share [3], + bool is_toplevel) { log_printf(FUNC,Direction,FUNCTION,"Begin"); @@ -36,5 +37,5 @@ _nb_inst_predict = nb_inst_predict ; _nb_inst_update = nb_inst_update ; - _size_address = size_address ; +// _size_address = size_address ; for (uint32_t i=0; i<3; i++) @@ -141,13 +142,20 @@ _have_port_history = (_size_history > 0); + test(); + _param_glue = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::direction::direction_glue::Parameters (_predictor_scheme, _nb_inst_predict , _nb_inst_update , - _size_address , + size_address , _size_history ); - test(); - + if (is_toplevel) + { + _size_instruction_address = size_address; + + copy (); + } + log_printf(FUNC,Direction,FUNCTION,"End"); }; @@ -172,4 +180,15 @@ }; +#undef FUNCTION +#define FUNCTION "Direction::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Direction,FUNCTION,"Begin"); + + COPY(_param_glue); + + log_printf(FUNC,Direction,FUNCTION,"End"); + }; + }; // end namespace direction }; // end namespace prediction_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/src/Parameters_print.cpp (revision 88) @@ -30,5 +30,5 @@ xml.singleton_begin("nb_inst_predict "); xml.attribut("value",toString(_nb_inst_predict )); xml.singleton_end(); xml.singleton_begin("nb_inst_update "); xml.attribut("value",toString(_nb_inst_update )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.comment("predictor_scheme : "); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Prediction_unit_Glue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/main.cpp (revision 88) @@ -81,5 +81,7 @@ _nb_inst_branch_predict, _nb_inst_branch_decod , - _nb_inst_branch_update ); + _nb_inst_branch_update , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/SelfTest/src/test.cpp (revision 88) @@ -59,5 +59,5 @@ ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT ,"out_PREDICT_PC_NEXT ",Taddress_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"out_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); - ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[it1]); ALLOC1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,"out_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); @@ -91,4 +91,5 @@ ALLOC1_SC_SIGNAL( in_PREDICT_UPT_ACK ," in_PREDICT_UPT_ACK ",Tcontrol_t ,_param->_nb_inst_branch_predict); ALLOC1_SC_SIGNAL(out_PREDICT_UPT_CONTEXT_ID ,"out_PREDICT_UPT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_predict); + ALLOC1_SC_SIGNAL( in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID ,"out_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_SRC ,"out_PREDICT_UPT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_predict); ALLOC1_SC_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_DEST ,"out_PREDICT_UPT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_predict); @@ -99,19 +100,19 @@ ALLOC1_SC_SIGNAL(out_PREDICT_UPT_RAS_ADDRESS ,"out_PREDICT_UPT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_predict); //ALLOC1_SC_SIGNAL(out_PREDICT_UPT_RAS_INDEX ,"out_PREDICT_UPT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_branch_predict); - ALLOC1_SC_SIGNAL( in_DEPTH_UPT_NB_BRANCH ," in_DEPTH_UPT_NB_BRANCH ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_DEPTH_UPT_TAIL ," in_DEPTH_UPT_TAIL ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,"out_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL(out_DEPTH_TAIL ,"out_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); - - ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID," in_DECOD_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); +// ALLOC1_SC_SIGNAL( in_DEPTH_UPT_NB_BRANCH ," in_DEPTH_UPT_NB_BRANCH ",Tdepth_t ,_param->_nb_context); +// ALLOC1_SC_SIGNAL( in_DEPTH_UPT_TAIL ," in_DEPTH_UPT_TAIL ",Tdepth_t ,_param->_nb_context); +// ALLOC1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,"out_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); +// ALLOC1_SC_SIGNAL(out_DEPTH_TAIL ,"out_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); + + ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID," in_DECOD_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); ALLOC1_SC_SIGNAL(out_DECOD_BTB_VAL ,"out_DECOD_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_branch_decod); ALLOC1_SC_SIGNAL( in_DECOD_BTB_ACK ," in_DECOD_BTB_ACK ",Tcontrol_t ,_param->_nb_inst_branch_decod); @@ -144,4 +145,5 @@ ALLOC1_SC_SIGNAL(out_DECOD_UPT_MISS_DECOD ,"out_DECOD_UPT_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_branch_decod); ALLOC1_SC_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID ,"out_DECOD_UPT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_branch_decod); + ALLOC1_SC_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,"out_DECOD_UPT_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_branch_decod); ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_branch_update); @@ -199,11 +201,11 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_PC_NEXT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_STATE ,_param->_nb_context); for (uint32_t i=0; i<_param->_nb_context; i++) { - if (_param->_have_port_inst_ifetch_ptr [i]) - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]); - if (_param->_have_port_depth [i]) + if (_param->_have_port_inst_ifetch_ptr) + INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_INST_IFETCH_PTR [i]); + if (_param->_have_port_depth) INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]); } @@ -243,4 +245,6 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_UPT_CONTEXT_ID ,_param->_nb_inst_branch_predict); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue, in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_predict); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_predict); @@ -252,16 +256,16 @@ //INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_PREDICT_UPT_RAS_INDEX ,_param->_nb_inst_branch_predict); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); if (_param->_have_port_context_id) - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - if (_param->_have_port_max_depth) - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue, in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod); @@ -296,6 +300,7 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_MISS_IFETCH ,_param->_nb_inst_branch_decod); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_MISS_DECOD ,_param->_nb_inst_branch_decod); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_UPDATE_PREDICTION_ID ,_param->_nb_inst_branch_decod); + INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod); INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue,out_UPDATE_BTB_VAL ,_param->_nb_inst_branch_update); @@ -337,14 +342,14 @@ //INSTANCE1_SC_SIGNAL(_Prediction_unit_Glue, in_UPDATE_UPT_RAS_PREDICTION_IFETCH,_param->_nb_inst_branch_update); - for (uint32_t i=0; i<_param->_nb_context; i++) - { - if (_param->_have_port_depth [i]) - { - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]); - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]); - } - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]); - INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]); - } +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// if (_param->_have_port_depth) +// { +// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_TAIL [i]); +// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_TAIL [i]); +// } +// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue, in_DEPTH_UPT_NB_BRANCH [i]); +// INSTANCE_SC_SIGNAL(_Prediction_unit_Glue,out_DEPTH_NB_BRANCH [i]); +// } msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -583,5 +588,5 @@ { in_DECOD_VAL [decod_unit][i]->write((rand()%100)write(rand()%_param->_size_depth[context]); + in_DECOD_BRANCH_UPDATE_PREDICTION_ID [decod_unit][i]->write(rand()%_param->_array_size_depth[context]); in_DECOD_BTB_ACK[0]->write((rand()%100)write(0); in_DECOD_BRANCH_STATE [decod_unit][i]->write(BRANCH_STATE_SPEC_TAKE); - in_DECOD_BRANCH_UPDATE_PREDICTION_ID [decod_unit][i]->write(i%_param->_max_size_depth); + in_DECOD_BRANCH_UPDATE_PREDICTION_ID [decod_unit][i]->write(i%_param->_size_depth); in_DECOD_BRANCH_CONDITION [decod_unit][i]->write(BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK); in_DECOD_BRANCH_DIRECTION [decod_unit][i]->write(1); @@ -664,5 +669,5 @@ TEST(Tcontext_t ,out_DECOD_RAS_CONTEXT_ID [0]->read(),context); TEST(Tcontrol_t ,out_DECOD_RAS_PUSH [0]->read(),1); - TEST(Taddress_t ,out_DECOD_RAS_ADDRESS_PUSH [0]->read(),0x11061979+i); + TEST(Taddress_t ,out_DECOD_RAS_ADDRESS_PUSH [0]->read(),0xdeadbeef+i+2); TEST(Tcontrol_t ,out_DECOD_RAS_MISS_PREDICTION [0]->read(),1); TEST(Tcontext_t ,out_DECOD_UPT_CONTEXT_ID [0]->read(),context); @@ -674,5 +679,6 @@ TEST(Tcontrol_t ,out_DECOD_UPT_MISS_IFETCH [0]->read(),1); TEST(Tcontrol_t ,out_DECOD_UPT_MISS_DECOD [0]->read(),0); - TEST(Tprediction_ptr_t ,out_DECOD_UPT_UPDATE_PREDICTION_ID [0]->read(),i%_param->_max_size_depth); + TEST(Tprediction_ptr_t ,out_DECOD_UPT_UPDATE_PREDICTION_ID [0]->read(),i%_param->_size_depth); + TEST(Tcontrol_t ,out_DECOD_UPT_IS_ACCURATE [0]->read(),0); find = true; @@ -712,5 +718,5 @@ DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context); DELETE1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context); - DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); DELETE1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context); DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_context); @@ -743,4 +749,5 @@ DELETE1_SC_SIGNAL(out_PREDICT_UPT_VAL ,_param->_nb_inst_branch_predict); DELETE1_SC_SIGNAL( in_PREDICT_UPT_ACK ,_param->_nb_inst_branch_predict); + DELETE1_SC_SIGNAL( in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_predict); DELETE1_SC_SIGNAL(out_PREDICT_UPT_CONTEXT_ID ,_param->_nb_inst_branch_predict); DELETE1_SC_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict); @@ -752,19 +759,19 @@ DELETE1_SC_SIGNAL(out_PREDICT_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_predict); //DELETE1_SC_SIGNAL(out_PREDICT_UPT_RAS_INDEX ,_param->_nb_inst_branch_predict); - DELETE1_SC_SIGNAL( in_DEPTH_UPT_NB_BRANCH ,_param->_nb_context); - DELETE1_SC_SIGNAL( in_DEPTH_UPT_TAIL ,_param->_nb_context); - DELETE1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context); - DELETE1_SC_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context); - - DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); +// DELETE1_SC_SIGNAL( in_DEPTH_UPT_NB_BRANCH ,_param->_nb_context); +// DELETE1_SC_SIGNAL( in_DEPTH_UPT_TAIL ,_param->_nb_context); +// DELETE1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context); +// DELETE1_SC_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context); + + DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); DELETE1_SC_SIGNAL(out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod); DELETE1_SC_SIGNAL( in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod); @@ -797,4 +804,5 @@ DELETE1_SC_SIGNAL(out_DECOD_UPT_MISS_DECOD ,_param->_nb_inst_branch_decod); DELETE1_SC_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID ,_param->_nb_inst_branch_decod); + DELETE1_SC_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod); DELETE1_SC_SIGNAL(out_UPDATE_BTB_VAL ,_param->_nb_inst_branch_update); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Parameters.h (revision 88) @@ -27,7 +27,8 @@ public : uint32_t _nb_decod_unit ; //public : uint32_t _nb_ooo_engine ; - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t * _nb_instruction ;//[nb_context] - public : uint32_t * _size_depth ;//[nb_context] +//public : uint32_t * _size_depth ;//[nb_context] + public : uint32_t * _array_size_depth ;//[nb_context] public : uint32_t * _nb_inst_decod ;//[nb_decod_unit] //public : uint32_t * _nb_inst_update ;//[nb_ooo_engine] @@ -37,12 +38,12 @@ //public : uint32_t _nb_inst_branch_complete ; - public : uint32_t _size_context_id ; - public : uint32_t * _size_inst_ifetch_ptr ;//[nb_context] - public : uint32_t _max_size_depth ; +//public : uint32_t _size_context_id ; +//public : uint32_t * _size_inst_ifetch_ptr ;//[nb_context] +//public : uint32_t _max_size_depth ; - public : bool _have_port_context_id ; - public : bool _have_port_max_depth ; - public : bool * _have_port_depth ;//[nb_context] - public : bool * _have_port_inst_ifetch_ptr;//[nb_context] +//public : bool _have_port_context_id ; +//public : bool _have_port_max_depth ; +//public : bool * _have_port_depth ;//[nb_context] +//public : bool * _have_port_inst_ifetch_ptr;//[nb_context] //-----[ methods ]----------------------------------------------------------- @@ -50,5 +51,5 @@ uint32_t nb_decod_unit , // uint32_t nb_ooo_engine , - uint32_t size_address , + uint32_t size_address , uint32_t * nb_instruction , uint32_t * size_depth , @@ -57,7 +58,11 @@ uint32_t nb_inst_branch_predict, uint32_t nb_inst_branch_decod , - uint32_t nb_inst_branch_update ); + uint32_t nb_inst_branch_update , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/include/Prediction_unit_Glue.h (revision 88) @@ -106,4 +106,6 @@ public : SC_IN (Tcontrol_t ) ** in_PREDICT_UPT_ACK ; //[nb_inst_branch_predict] public : SC_OUT(Tcontext_t ) ** out_PREDICT_UPT_CONTEXT_ID ; //[nb_inst_branch_predict] + public : SC_IN (Tprediction_ptr_t ) ** in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID; //[nb_inst_branch_predict] + public : SC_OUT(Taddress_t ) ** out_PREDICT_UPT_BTB_ADDRESS_SRC ; //[nb_inst_branch_predict]* BTB.ADDRESS_SRC public : SC_OUT(Taddress_t ) ** out_PREDICT_UPT_BTB_ADDRESS_DEST ; //[nb_inst_branch_predict] @@ -159,4 +161,5 @@ public : SC_OUT(Tcontrol_t ) ** out_DECOD_UPT_MISS_DECOD ; //[nb_inst_branch_decod] public : SC_OUT(Tprediction_ptr_t ) ** out_DECOD_UPT_UPDATE_PREDICTION_ID ; //[nb_inst_branch_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_UPT_IS_ACCURATE ; //[nb_inst_branch_decod] // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -202,9 +205,9 @@ //public : SC_IN (Tcontrol_t ) ** in_UPDATE_UPT_RAS_PREDICTION_IFETCH ; //[nb_inst_branch_update] RAS.PREDICTION_IFETCH - // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tdepth_t ) ** in_DEPTH_UPT_NB_BRANCH ; //[nb_context] - public : SC_IN (Tdepth_t ) ** in_DEPTH_UPT_TAIL ; //[nb_context] - public : SC_OUT(Tdepth_t ) ** out_DEPTH_NB_BRANCH ; //[nb_context] - public : SC_OUT(Tdepth_t ) ** out_DEPTH_TAIL ; //[nb_context] +// // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +//public : SC_IN (Tdepth_t ) ** in_DEPTH_UPT_NB_BRANCH ; //[nb_context] +//public : SC_IN (Tdepth_t ) ** in_DEPTH_UPT_TAIL ; //[nb_context] +//public : SC_OUT(Tdepth_t ) ** out_DEPTH_NB_BRANCH ; //[nb_context] +//public : SC_OUT(Tdepth_t ) ** out_DEPTH_TAIL ; //[nb_context] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters.cpp (revision 88) @@ -30,37 +30,38 @@ uint32_t nb_inst_branch_predict, uint32_t nb_inst_branch_decod , - uint32_t nb_inst_branch_update ) + uint32_t nb_inst_branch_update , + bool is_toplevel + ) { log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); _nb_context = nb_context ; - _size_address = size_address ; _nb_instruction = nb_instruction ; - _size_depth = size_depth ; +// _size_depth = size_depth ; + _array_size_depth = size_depth ; _nb_decod_unit = nb_decod_unit ; _nb_inst_decod = nb_inst_decod ; -// _nb_ooo_engine = nb_ooo_engine ; -// _nb_inst_update = nb_inst_update ; +// _nb_ooo_engine = nb_ooo_engine ; +// _nb_inst_update = nb_inst_update ; _nb_inst_branch_predict = nb_inst_branch_predict; _nb_inst_branch_decod = nb_inst_branch_decod ; _nb_inst_branch_update = nb_inst_branch_update ; - _size_context_id = log2(_nb_context); - _size_inst_ifetch_ptr = new uint32_t [_nb_context]; - _max_size_depth = max(_size_depth,_nb_context); + test(); - _have_port_context_id = (_size_context_id>0); - _have_port_max_depth = (_max_size_depth>0); - _have_port_depth = new bool [_nb_context]; - _have_port_inst_ifetch_ptr = new bool [_nb_context]; + if (is_toplevel) + { + _size_instruction_address = size_address; + _size_context_id = log2(_nb_context); + _size_depth = max(size_depth,_nb_context); + _size_inst_ifetch_ptr = log2(max(_nb_instruction,_nb_context)); - for (uint32_t i=0; i<_nb_context; i++) - { - _size_inst_ifetch_ptr [i] = log2(_nb_instruction [i]); - _have_port_depth [i] = (_size_depth [i] > 0); - _have_port_inst_ifetch_ptr [i] = (_size_inst_ifetch_ptr [i] > 0); + _have_port_context_id = (_size_context_id > 0); + _have_port_depth = (_size_depth > 0); + _have_port_inst_ifetch_ptr = (_size_inst_ifetch_ptr > 0); + + copy (); } - test(); log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); }; @@ -80,7 +81,12 @@ { log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); - delete [] _size_inst_ifetch_ptr ; - delete [] _have_port_depth ; - delete [] _have_port_inst_ifetch_ptr; + log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Prediction_unit_Glue::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Parameters_print.cpp (revision 88) @@ -30,5 +30,5 @@ xml.singleton_begin("nb_decod_unit "); xml.attribut("value",toString(_nb_decod_unit )); xml.singleton_end(); // xml.singleton_begin("nb_ooo_engine "); xml.attribut("value",toString(_nb_ooo_engine )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("nb_inst_branch_predict"); xml.attribut("value",toString(_nb_inst_branch_predict)); xml.singleton_end(); xml.singleton_begin("nb_inst_branch_decod "); xml.attribut("value",toString(_nb_inst_branch_decod )); xml.singleton_end(); @@ -43,6 +43,6 @@ xml. attribut("id" ,toString(i)); xml. balise_open_end(); - xml. singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction [i])); xml.singleton_end(); - xml. singleton_begin("size_depth "); xml.attribut("value",toString(_size_depth [i])); xml.singleton_end(); + xml. singleton_begin("nb_instruction "); xml.attribut("value",toString(_nb_instruction [i])); xml.singleton_end(); +// xml. singleton_begin("size_depth "); xml.attribut("value",toString(_size_depth [i])); xml.singleton_end(); xml. balise_close(); } @@ -53,5 +53,5 @@ xml. attribut("id" ,toString(i)); xml. balise_open_end(); - xml. singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod [i])); xml.singleton_end(); + xml. singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod [i])); xml.singleton_end(); xml. balise_close(); } @@ -62,5 +62,5 @@ // xml. attribut("id" ,toString(i)); // xml. balise_open_end(); -// xml. singleton_begin("nb_inst_update "); xml.attribut("value",toString(_nb_inst_update [i])); xml.singleton_end(); +// xml. singleton_begin("nb_inst_update "); xml.attribut("value",toString(_nb_inst_update [i])); xml.singleton_end(); // xml. balise_close(); // } @@ -76,5 +76,5 @@ #define FUNCTION "Prediction_unit_Glue::operator<<" std::ostream& operator<< (std::ostream& output_stream , - morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::prediction_unit_glue::Parameters & x) + morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::prediction_unit_glue::Parameters & x) { log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue.cpp (revision 88) @@ -40,18 +40,24 @@ usage_environment(_usage); +#if DEBUG_Prediction_unit_Glue == true + log_printf(INFO,Prediction_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Allocation"); allocation ( #ifdef STATISTICS - param_statistics + param_statistics #endif - ); + ); #ifdef STATISTICS if (usage_is_set(_usage,USE_STATISTICS)) - { - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Allocation of statistics"); - - statistics_allocation(param_statistics); + { + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Allocation of statistics"); + + statistics_allocation(param_statistics); } #endif @@ -60,8 +66,8 @@ if (usage_is_set(_usage,USE_VHDL)) { - // generate the vhdl - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Generate the vhdl"); - - vhdl(); + // generate the vhdl + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Generate the vhdl"); + + vhdl(); } #endif @@ -70,1680 +76,1686 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - transition"); - - SC_METHOD (transition); - dont_initialize (); - sensitive << (*(in_CLOCK)).pos(); - + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - transition"); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + # ifdef SYSTEMCASS_SPECIFIC - // List dependency information + // List dependency information # endif - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_predict"); - - SC_METHOD (genMealy_predict); - dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); // use internal register - for (uint32_t i=0; i<_param->_nb_context; i++) - { - sensitive << (*( in_PREDICT_VAL [i])) - << (*( in_PREDICT_PC_PREVIOUS [i])) - << (*( in_PREDICT_PC_CURRENT [i])) - << (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - sensitive << (*( in_PREDICT_BTB_ACK [i])) - << (*( in_PREDICT_BTB_HIT [i])) - << (*( in_PREDICT_BTB_ADDRESS_SRC [i])) - << (*( in_PREDICT_BTB_ADDRESS_DEST [i])) - << (*( in_PREDICT_BTB_CONDITION [i])) -// << (*( in_PREDICT_BTB_LAST_TAKE [i])) - << (*( in_PREDICT_BTB_IS_ACCURATE [i])) - << (*( in_PREDICT_DIR_ACK [i])) -// << (*( in_PREDICT_DIR_HISTORY [i])) - << (*( in_PREDICT_DIR_DIRECTION [i])) - << (*( in_PREDICT_RAS_ACK [i])) - << (*( in_PREDICT_RAS_HIT [i])) - << (*( in_PREDICT_RAS_ADDRESS_POP [i])) -// << (*( in_PREDICT_RAS_INDEX [i])) - << (*( in_PREDICT_UPT_ACK [i])); - } - for (uint32_t i=0; i<_param->_nb_context; i++) - { - sensitive << (*(in_DEPTH_UPT_NB_BRANCH [i])); - if (_param->_have_port_depth[i]) - sensitive << (*(in_DEPTH_UPT_TAIL [i])); - } + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_predict"); + + SC_METHOD (genMealy_predict); + + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // use internal register + + for (uint32_t i=0; i<_param->_nb_context; i++) + { + sensitive << (*( in_PREDICT_VAL [i])) + << (*( in_PREDICT_PC_PREVIOUS [i])) + << (*( in_PREDICT_PC_CURRENT [i])) + << (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); + } + + for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) + { + sensitive << (*( in_PREDICT_BTB_ACK [i])) + << (*( in_PREDICT_BTB_HIT [i])) + << (*( in_PREDICT_BTB_ADDRESS_SRC [i])) + << (*( in_PREDICT_BTB_ADDRESS_DEST [i])) + << (*( in_PREDICT_BTB_CONDITION [i])) +// << (*( in_PREDICT_BTB_LAST_TAKE [i])) + << (*( in_PREDICT_BTB_IS_ACCURATE [i])) + << (*( in_PREDICT_DIR_ACK [i])) +// << (*( in_PREDICT_DIR_HISTORY [i])) + << (*( in_PREDICT_DIR_DIRECTION [i])) + << (*( in_PREDICT_RAS_ACK [i])) + << (*( in_PREDICT_RAS_HIT [i])) + << (*( in_PREDICT_RAS_ADDRESS_POP [i])) +// << (*( in_PREDICT_RAS_INDEX [i])) + << (*( in_PREDICT_UPT_ACK [i])); + if (_param->_have_port_depth) + sensitive << (*( in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); + } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// sensitive << (*(in_DEPTH_UPT_NB_BRANCH [i])); +// if (_param->_have_port_depth) +// sensitive << (*(in_DEPTH_UPT_TAIL [i])); +// } # ifdef SYSTEMCASS_SPECIFIC - // List dependency information - for (uint32_t x=0; x<_param->_nb_context; x++) - { - if (_param->_have_port_depth[x]) - { - (*(out_DEPTH_TAIL [x])) (*( in_DEPTH_UPT_TAIL [x])); - } - (*(out_DEPTH_NB_BRANCH [x])) (*( in_DEPTH_UPT_NB_BRANCH [x])); - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_ACK [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_ACK [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_ACK [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_PC_NEXT [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_PC_NEXT [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - if (_param->_have_port_inst_ifetch_ptr [x]) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_UPT_ACK [i])); - } - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_VAL [i])); - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_BRANCH_STATE [x]))(*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - if (_param->_have_port_depth [x]) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth [i]) - { - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_UPT_ACK [i])); - } - } - - for (uint32_t y=0; y<_param->_nb_instruction[x]; y++) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_UPT_ACK [i])); - } - } - } - - for (uint32_t x=0; x<_param->_nb_inst_branch_predict; x++) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_BTB_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_BTB_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); - } - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_DIR_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_DIR_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_DIR_STATIC [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_DIR_STATIC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_UPT_ACK [i])); - } - -// for (uint32_t i=0; i<_param->_nb_context; i++) -// { -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_VAL [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); -// if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) -// { -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); -// } -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); -// } -// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) -// { -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); -// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); -// (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); -// } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_RAS_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_RAS_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); - } - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_RAS_PUSH [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_RAS_PUSH [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); - } - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); - } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_UPT_ACK [i])); - } - -// for (uint32_t i=0; i<_param->_nb_context; i++) -// { -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_VAL [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_PREVIOUS [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_CURRENT [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); -// if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) -// { -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_DEPTH_UPT_TAIL [i])); -// } -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); -// } -// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) -// { -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ACK [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_HIT [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_ACK [i])); -// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_HISTORY [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_DIRECTION [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_ACK [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_HIT [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_INDEX [i])); -// (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_UPT_ACK [i])); -// } - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_VAL [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_PREVIOUS [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); - if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) - { - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_DEPTH_UPT_TAIL [i])); - } - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) - { - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ACK [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_HIT [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_ACK [i])); -// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_HISTORY [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_DIRECTION [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_ACK [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_HIT [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_INDEX [i])); - (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_UPT_ACK [i])); - } - -// for (uint32_t i=0; i<_param->_nb_context; i++) -// { -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_VAL [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_PREVIOUS [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_CURRENT [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); -// if (_param->_have_port_depth[x] and _param->_have_port_depth[i]) -// { -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_DEPTH_UPT_TAIL [i])); -// } -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); -// } -// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) -// { -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ACK [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_HIT [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_CONDITION [i])); -// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_ACK [i])); -// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_HISTORY [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_DIRECTION [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_ACK [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_HIT [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); -// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_INDEX [i])); -// (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_UPT_ACK [i])); -// } - } + // List dependency information +// for (uint32_t x=0; x<_param->_nb_context; x++) +// { +// // if (_param->_have_port_depth) +// // { +// // (*(out_DEPTH_TAIL [x])) (*( in_DEPTH_UPT_TAIL [x])); +// // } +// // (*(out_DEPTH_NB_BRANCH [x])) (*( in_DEPTH_UPT_NB_BRANCH [x])); + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_ACK [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_ACK [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_ACK [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_ACK [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_PC_NEXT [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_PC_NEXT [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_PC_NEXT [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_PC_NEXT_IS_DS_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// if (_param->_have_port_inst_ifetch_ptr) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_INST_IFETCH_PTR [x])) (*( in_PREDICT_UPT_ACK [i])); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_BRANCH_STATE [x]))(*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_BRANCH_STATE [x]))(*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_BRANCH_STATE [x]))(*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_BRANCH_STATE [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// // if (_param->_have_port_depth) +// // { +// // for (uint32_t i=0; i<_param->_nb_context; i++) +// // { +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_VAL [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth) +// // { +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// // } +// // for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// // { +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ACK [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_HIT [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// //// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_ACK [i])); +// //// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_ACK [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_HIT [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// //// (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); +// // (*(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x])) (*( in_PREDICT_UPT_ACK [i])); +// // } +// // } + +// for (uint32_t y=0; y<_param->_nb_instruction[x]; y++) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_INSTRUCTION_ENABLE [x][y])) (*( in_PREDICT_UPT_ACK [i])); +// } +// } +// } + +// for (uint32_t x=0; x<_param->_nb_inst_branch_predict; x++) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_BTB_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_BTB_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_BTB_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_BTB_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_BTB_ADDRESS [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_DIR_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_DIR_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_DIR_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_DIR_ADDRESS_SRC [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_DIR_STATIC [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_DIR_STATIC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_DIR_STATIC [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// // for (uint32_t i=0; i<_param->_nb_context; i++) +// // { +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_VAL [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// // } +// // for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// // { +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); +// // // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); +// // (*(out_PREDICT_DIR_LAST_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); +// // } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_RAS_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_RAS_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_RAS_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_RAS_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_RAS_PUSH [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_RAS_ADDRESS_PUSH [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_VAL [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_VAL [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_VAL [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_CONTEXT_ID [x])) (*( in_PREDICT_UPT_ACK [i])); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_SRC [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_BTB_ADDRESS_DEST [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_BTB_CONDITION [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_BTB_LAST_TAKE [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_BTB_IS_ACCURATE [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// // for (uint32_t i=0; i<_param->_nb_context; i++) +// // { +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_VAL [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_CURRENT [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// // } +// // for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// // { +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ACK [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_HIT [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_ACK [i])); +// // // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_ACK [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_HIT [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_RAS_INDEX [i])); +// // (*(out_PREDICT_UPT_DIR_HISTORY [x])) (*( in_PREDICT_UPT_ACK [i])); +// // } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_VAL [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// if (_param->_have_port_depth and _param->_have_port_depth) +// { +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_DEPTH_UPT_TAIL [i])); +// } +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// { +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ACK [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_HIT [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_ACK [i])); +// // (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_ACK [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_HIT [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_RAS_INDEX [i])); +// (*(out_PREDICT_UPT_RAS_ADDRESS [x])) (*( in_PREDICT_UPT_ACK [i])); +// } + +// // for (uint32_t i=0; i<_param->_nb_context; i++) +// // { +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_VAL [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_PREVIOUS [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_CURRENT [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_PC_CURRENT_IS_DS_TAKE [i])); +// // if (_param->_have_port_depth and _param->_have_port_depth) +// // { +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_DEPTH_UPT_TAIL [i])); +// // } +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_DEPTH_UPT_NB_BRANCH [i])); +// // } +// // for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) +// // { +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ACK [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_HIT [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ADDRESS_SRC [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_ADDRESS_DEST [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_CONDITION [i])); +// // // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_LAST_TAKE [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_BTB_IS_ACCURATE [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_ACK [i])); +// // // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_HISTORY [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_DIR_DIRECTION [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_ACK [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_HIT [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_ADDRESS_POP [i])); +// // // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_RAS_INDEX [i])); +// // (*(out_PREDICT_UPT_RAS_INDEX [x])) (*( in_PREDICT_UPT_ACK [i])); +// // } +// } # endif - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_decod"); - - SC_METHOD (genMealy_decod); - dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); // use internal register - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - sensitive << (*(in_DECOD_VAL [i][j])) - << (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])) - << (*(in_DECOD_BRANCH_STATE [i][j])) - << (*(in_DECOD_BRANCH_CONDITION [i][j])) - << (*(in_DECOD_BRANCH_DIRECTION [i][j])) - << (*(in_DECOD_ADDRESS_SRC [i][j])) - << (*(in_DECOD_ADDRESS_DEST [i][j])); - - if (_param->_have_port_context_id) - sensitive << (*(in_DECOD_CONTEXT_ID [i][j])); - if (_param->_have_port_max_depth) - sensitive << (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - sensitive << (*(in_DECOD_BTB_ACK [i] )) - << (*(in_DECOD_RAS_ACK [i] )) - << (*(in_DECOD_RAS_HIT [i] )) - << (*(in_DECOD_RAS_ADDRESS_POP [i] )) -// << (*(in_DECOD_RAS_INDEX [i] )) - << (*(in_DECOD_UPT_ACK [i] )) ; - } + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_decod"); + + SC_METHOD (genMealy_decod); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // use internal register + for (uint32_t i=0; i<_param->_nb_decod_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) + { + sensitive << (*(in_DECOD_VAL [i][j])) + << (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])) + << (*(in_DECOD_BRANCH_STATE [i][j])) + << (*(in_DECOD_BRANCH_CONDITION [i][j])) + << (*(in_DECOD_BRANCH_DIRECTION [i][j])) + << (*(in_DECOD_ADDRESS_SRC [i][j])) + << (*(in_DECOD_ADDRESS_DEST [i][j])); + + if (_param->_have_port_context_id) + sensitive << (*(in_DECOD_CONTEXT_ID [i][j])); + if (_param->_have_port_depth) + sensitive << (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); + } + for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) + { + sensitive << (*(in_DECOD_BTB_ACK [i] )) + << (*(in_DECOD_RAS_ACK [i] )) + << (*(in_DECOD_RAS_HIT [i] )) + << (*(in_DECOD_RAS_ADDRESS_POP [i] )) +// << (*(in_DECOD_RAS_INDEX [i] )) + << (*(in_DECOD_UPT_ACK [i] )) ; + } # ifdef SYSTEMCASS_SPECIFIC - // List dependency information - - for (uint32_t x=0; x<_param->_nb_decod_unit; x++) - for (uint32_t y=0; y<_param->_nb_inst_decod[x]; y++) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_ACK [x][y])) (*(in_DECOD_UPT_ACK [i] )); - } - } - - for (uint32_t x=0; x<_param->_nb_inst_branch_decod; x++) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); - } - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); - } - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - if (_param->_have_port_context_id) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); - } - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_UPT_ACK [i] )); - } - -// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) -// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) -// { -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_VAL [i][j])); -// if (_param->_have_port_context_id) -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_CONTEXT_ID [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_STATE [i][j])); -// if (_param->_have_port_max_depth) -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); -// } -// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) -// { -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BTB_ACK [i] )); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_ACK [i] )); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_HIT [i] )); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_INDEX [i] )); -// (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_UPT_ACK [i] )); -// } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - if (_param->_have_port_max_depth) - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_UPT_ACK [i] )); - } - - if (_param->_have_port_max_depth) - { - for (uint32_t i=0; i<_param->_nb_decod_unit; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - { - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_VAL [i][j])); - if (_param->_have_port_context_id) - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); - } - for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) - { - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BTB_ACK [i] )); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_ACK [i] )); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_HIT [i] )); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); -// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); - (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_UPT_ACK [i] )); - } - } - } +// // List dependency information + +// for (uint32_t x=0; x<_param->_nb_decod_unit; x++) +// for (uint32_t y=0; y<_param->_nb_inst_decod[x]; y++) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_ACK [x][y])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_ACK [x][y])) (*(in_DECOD_UPT_ACK [i] )); +// } +// } + +// for (uint32_t x=0; x<_param->_nb_inst_branch_decod; x++) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_ADDRESS_SRC [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_ADDRESS_DEST [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_CONDITION [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_LAST_TAKE [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_MISS_PREDICTION [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_BTB_IS_ACCURATE [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_RAS_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_RAS_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_RAS_PUSH [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_RAS_ADDRESS_PUSH [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_RAS_MISS_PREDICTION [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_VAL [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// if (_param->_have_port_context_id) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_VAL [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_CONTEXT_ID [x])) (*(in_DECOD_UPT_ACK [i] )); +// } +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_SRC [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_BTB_ADDRESS_DEST [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_BTB_CONDITION [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_BTB_LAST_TAKE [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_RAS_ADDRESS [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// // for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// // for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// // { +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_VAL [i][j])); +// // if (_param->_have_port_context_id) +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// // if (_param->_have_port_depth) +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// // } +// // for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// // { +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_BTB_ACK [i] )); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_ACK [i] )); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_HIT [i] )); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_RAS_INDEX [i] )); +// // (*(out_DECOD_UPT_RAS_INDEX [x])) (*(in_DECOD_UPT_ACK [i] )); +// // } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_MISS_IFETCH [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// if (_param->_have_port_depth) +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_MISS_DECOD [x])) (*(in_DECOD_UPT_ACK [i] )); +// } + +// if (_param->_have_port_depth) +// { +// for (uint32_t i=0; i<_param->_nb_decod_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) +// { +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_VAL [i][j])); +// if (_param->_have_port_context_id) +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_CONTEXT_ID [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_MATCH_INST_IFETCH_PTR [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_STATE [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_CONDITION [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BRANCH_DIRECTION [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_ADDRESS_SRC [i][j])); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_ADDRESS_DEST [i][j])); +// } +// for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) +// { +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_BTB_ACK [i] )); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_ACK [i] )); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_HIT [i] )); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_ADDRESS_POP [i] )); +// // (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_RAS_INDEX [i] )); +// (*(out_DECOD_UPT_UPDATE_PREDICTION_ID [x])) (*(in_DECOD_UPT_ACK [i] )); +// } +// } +// } # endif - log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_update"); - - SC_METHOD (genMealy_update); - dont_initialize (); -// sensitive << (*(in_CLOCK)).neg(); // don't use internal register - for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) - sensitive << (*(in_UPDATE_BTB_ACK [i])) - << (*(in_UPDATE_DIR_ACK [i])) - << (*(in_UPDATE_RAS_ACK [i])) - << (*(in_UPDATE_UPT_VAL [i])) - << (*(in_UPDATE_UPT_BTB_VAL [i])) - << (*(in_UPDATE_UPT_DIR_VAL [i])) - << (*(in_UPDATE_UPT_RAS_VAL [i])); + log_printf(INFO,Prediction_unit_Glue,FUNCTION,"Method - genMealy_update"); + + SC_METHOD (genMealy_update); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't use internal register + for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) + sensitive << (*(in_UPDATE_BTB_ACK [i])) + << (*(in_UPDATE_DIR_ACK [i])) + << (*(in_UPDATE_RAS_ACK [i])) + << (*(in_UPDATE_UPT_VAL [i])) + << (*(in_UPDATE_UPT_BTB_VAL [i])) + << (*(in_UPDATE_UPT_DIR_VAL [i])) + << (*(in_UPDATE_UPT_RAS_VAL [i])); # ifdef SYSTEMCASS_SPECIFIC - // List dependency information - for (uint32_t x=0; x<_param->_nb_inst_branch_update; x++) -// for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) - { - uint32_t i=x; - - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); - (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); - - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); - (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); - - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); - (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); - - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_BTB_ACK [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_DIR_ACK [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_RAS_ACK [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_VAL [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); - (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); - } +// // List dependency information +// for (uint32_t x=0; x<_param->_nb_inst_branch_update; x++) +// // for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) +// { +// uint32_t i=x; + +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); +// (*(out_UPDATE_BTB_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); + +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); +// (*(out_UPDATE_DIR_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); + +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_BTB_ACK [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_DIR_ACK [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_RAS_ACK [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_VAL [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); +// (*(out_UPDATE_RAS_VAL [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); + +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_BTB_ACK [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_DIR_ACK [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_RAS_ACK [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_VAL [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_BTB_VAL [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_DIR_VAL [i])); +// (*(out_UPDATE_UPT_ACK [x])) (*(in_UPDATE_UPT_RAS_VAL [i])); +// } # endif #endif @@ -1761,5 +1773,5 @@ if (usage_is_set(_usage,USE_STATISTICS)) { - statistics_deallocation(); + statistics_deallocation(); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 88) @@ -33,9 +33,9 @@ Entity * entity = _component->set_entity (_name - ,"Prediction_unit_Glue" + ,"Prediction_unit_Glue" #ifdef POSITION - ,COMBINATORY -#endif - ); + ,COMBINATORY +#endif + ); _interfaces = entity->set_interfaces(); @@ -45,9 +45,9 @@ Interface * interface = _interfaces->set_interface("" #ifdef POSITION - ,IN - ,SOUTH, - "Generalist interface" -#endif - ); + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); @@ -58,152 +58,154 @@ { { - ALLOC1_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context); - - ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); - ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_PREDICT_PC_PREVIOUS ,"pc_previous" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_PC_CURRENT ,"pc_current" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT ,"pc_next" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr [alloc_signal_it1]); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth [alloc_signal_it1]); - } - { - ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[alloc_interface_it1]); - _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); - } - - { - ALLOC1_INTERFACE("predict_btb",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); - - ALLOC1_VALACK_OUT(out_PREDICT_BTB_VAL ,VAL); - ALLOC1_VALACK_IN ( in_PREDICT_BTB_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_BTB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_OUT(out_PREDICT_BTB_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_HIT ,"hit" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST,"address_dest",Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); + ALLOC1_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context); + + ALLOC1_VALACK_IN ( in_PREDICT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_PREDICT_PC_PREVIOUS ,"pc_previous" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_PC_CURRENT ,"pc_current" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT ,"pc_next" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + } + { + ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); + _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); + } + + { + ALLOC1_INTERFACE("predict_btb",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_VALACK_OUT(out_PREDICT_BTB_VAL ,VAL); + ALLOC1_VALACK_IN ( in_PREDICT_BTB_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_PREDICT_BTB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_PREDICT_BTB_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_HIT ,"hit" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST,"address_dest",Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); // ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("predict_dir",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); - - ALLOC1_VALACK_OUT(out_PREDICT_DIR_VAL ,VAL); - ALLOC1_VALACK_IN ( in_PREDICT_DIR_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_DIR_ADDRESS_SRC,"address_src",Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_DIR_STATIC ,"static" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + } + + { + ALLOC1_INTERFACE("predict_dir",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_VALACK_OUT(out_PREDICT_DIR_VAL ,VAL); + ALLOC1_VALACK_IN ( in_PREDICT_DIR_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_PREDICT_DIR_ADDRESS_SRC,"address_src",Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_DIR_STATIC ,"static" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_OUT(out_PREDICT_DIR_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); - ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("predict_ras",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); - - ALLOC1_VALACK_OUT(out_PREDICT_RAS_VAL ,VAL); - ALLOC1_VALACK_IN ( in_PREDICT_RAS_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_HIT ,"hit" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_PUSH ,"push" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_ADDRESS_PUSH,"address_push",Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); + } + + { + ALLOC1_INTERFACE("predict_ras",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_VALACK_OUT(out_PREDICT_RAS_VAL ,VAL); + ALLOC1_VALACK_IN ( in_PREDICT_RAS_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_HIT ,"hit" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_PUSH ,"push" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_PREDICT_RAS_ADDRESS_PUSH,"address_push",Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); } { - ALLOC1_INTERFACE("predict_upt",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); - - ALLOC1_VALACK_OUT(out_PREDICT_UPT_VAL ,VAL); - ALLOC1_VALACK_IN ( in_PREDICT_UPT_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_ADDRESS_DEST,"btb_address_dest",Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_IS_ACCURATE ,"btb_is_accurate" ,Tcontrol_t ,1); + ALLOC1_INTERFACE("predict_upt",OUT,NORTH,"Interface with ifetch unit",_param->_nb_inst_branch_predict); + + ALLOC1_VALACK_OUT(out_PREDICT_UPT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_PREDICT_UPT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_ADDRESS_DEST,"btb_address_dest",Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_BTB_IS_ACCURATE ,"btb_is_accurate" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_DIR_HISTORY ,"dir_history" ,Thistory_t ,_param->_size_history); - ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_PREDICT_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); } } - // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - { - ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_interface_it1]); - - _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_DECOD_ACK ,ACK,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_max_size_depth ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - } - - { - ALLOC1_INTERFACE("decod_btb",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); - - ALLOC1_VALACK_OUT(out_DECOD_BTB_VAL ,VAL); - ALLOC1_VALACK_IN ( in_DECOD_BTB_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_DECOD_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); - } - - { - ALLOC1_INTERFACE("decod_ras",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); - - ALLOC1_VALACK_OUT(out_DECOD_RAS_VAL ,VAL); - ALLOC1_VALACK_IN ( in_DECOD_RAS_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_DECOD_RAS_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_DECOD_RAS_HIT ,"hit" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_DECOD_RAS_PUSH ,"push" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_DECOD_RAS_ADDRESS_PUSH ,"address_push" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_address); -// ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); - ALLOC1_SIGNAL_OUT(out_DECOD_RAS_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); - } - - { - ALLOC1_INTERFACE("decod_upt",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); - - ALLOC1_VALACK_OUT(out_DECOD_UPT_VAL ,VAL); - ALLOC1_VALACK_IN ( in_DECOD_UPT_ACK ,ACK); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); -// ALLOC1_SIGNAL_OUT(out_DECOD_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_MISS_IFETCH ,"miss_ifetch" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_MISS_DECOD ,"miss_decod" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_DECOD_UPT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_max_size_depth); - } - } - - // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - { - ALLOC1_INTERFACE("update_btb",OUT,SOUTH,"Interface with update unit",_param->_nb_inst_branch_update); + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + { + ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + + _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_VALACK_OUT(out_DECOD_ACK ,ACK,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + } + + { + ALLOC1_INTERFACE("decod_btb",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC1_VALACK_OUT(out_DECOD_BTB_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DECOD_BTB_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_DECOD_BTB_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + } + + { + ALLOC1_INTERFACE("decod_ras",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC1_VALACK_OUT(out_DECOD_RAS_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DECOD_RAS_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DECOD_RAS_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_DECOD_RAS_HIT ,"hit" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_DECOD_RAS_PUSH ,"push" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_DECOD_RAS_ADDRESS_PUSH ,"address_push" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_instruction_address); +// ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); + ALLOC1_SIGNAL_OUT(out_DECOD_RAS_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); + } + + { + ALLOC1_INTERFACE("decod_upt",OUT,NORTH,"Interface with decod unit",_param->_nb_inst_branch_decod); + + ALLOC1_VALACK_OUT(out_DECOD_UPT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DECOD_UPT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); +// ALLOC1_SIGNAL_OUT(out_DECOD_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_MISS_IFETCH ,"miss_ifetch" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_MISS_DECOD ,"miss_decod" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT(out_DECOD_UPT_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); + } + } + + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + { + ALLOC1_INTERFACE("update_btb",OUT,SOUTH,"Interface with update unit",_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_BTB_VAL ,VAL); ALLOC1_VALACK_IN ( in_UPDATE_BTB_ACK ,ACK); // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address); -// ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address); +// ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); +// ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_CONDITION ,"condition" ,Tbranch_condition_t,_param->_size_branch_condition); // ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_LAST_TAKE ,"last_take" ,Tcontrol_t ,1); @@ -212,9 +214,9 @@ { - ALLOC1_INTERFACE("update_dir",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + ALLOC1_INTERFACE("update_dir",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_DIR_VAL ,VAL); ALLOC1_VALACK_IN ( in_UPDATE_DIR_ACK ,ACK); -// ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); +// ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_HISTORY ,"history" ,Thistory_t ,_param->_size_history); // ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_DIRECTION ,"direction" ,Tcontrol_t ,1); @@ -222,5 +224,5 @@ { - ALLOC1_INTERFACE("update_ras",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + ALLOC1_INTERFACE("update_ras",OUT,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); ALLOC1_VALACK_OUT(out_UPDATE_RAS_VAL ,VAL); @@ -228,5 +230,5 @@ // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PUSH ,"push" ,Tcontrol_t ,1); -// ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"address" ,Taddress_t ,_param->_size_address); +// ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"index" ,Tptr_t ,_param->_size_ras_index); // ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); @@ -235,5 +237,5 @@ { - ALLOC1_INTERFACE("update_upt",IN ,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); + ALLOC1_INTERFACE("update_upt",IN ,NORTH,"Interface with update unit",_param->_nb_inst_branch_update); ALLOC1_VALACK_IN ( in_UPDATE_UPT_VAL ,VAL); @@ -242,7 +244,7 @@ // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); -// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); -// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); +// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); +// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_DIR_VAL ,"dir_val" ,Tcontrol_t ,1); @@ -250,5 +252,5 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_VAL ,"ras_val" ,Tcontrol_t ,1); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_PUSH ,"ras_push" ,Tcontrol_t ,1); -// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); +// ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_size_ras_index); // ALLOC1_SIGNAL_IN ( in_UPDATE_UPT_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); @@ -256,19 +258,22 @@ } - // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - { - ALLOC1_INTERFACE("depth",IN,NORTH,"Interface with depth",_param->_nb_context); - - ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_NB_BRANCH,"upt_nb_branch",Tdepth_t,_param->_size_depth[alloc_signal_it1]+1); - ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_TAIL ,"upt_tail" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]); - ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH ,"nb_branch" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]+1); - ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"tail" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]); - } +// // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// { +// ALLOC1_INTERFACE("depth",IN,NORTH,"Interface with depth",_param->_nb_context); +// +// ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_NB_BRANCH,"upt_nb_branch",Tdepth_t,_param->_size_depth+1); +// ALLOC1_SIGNAL_IN ( in_DEPTH_UPT_TAIL ,"upt_tail" ,Tdepth_t,_param->_size_depth); +// ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH ,"nb_branch" ,Tdepth_t,_param->_size_depth+1); +// ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"tail" ,Tdepth_t,_param->_size_depth); +// } // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifndef NO_INIT - reg_PREDICT_PRIORITY = 0; - reg_DECOD_PRIORITY = 0; +#ifndef REGISTER_INIT + if (usage_is_set(_usage,USE_SYSTEMC)) + { + reg_PREDICT_PRIORITY = 0; + reg_DECOD_PRIORITY = 0; + } #endif @@ -277,5 +282,5 @@ #ifdef POSITION if (usage_is_set(_usage,USE_POSITION)) - _component->generate_file(); + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_deallocation.cpp (revision 88) @@ -33,20 +33,20 @@ DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_context ,1); DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_context ,1); - DELETE1_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context ,_param->_size_address); - DELETE1_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context ,_param->_size_address); + DELETE1_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context ,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context ,_param->_size_instruction_address); DELETE1_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context ,1); - DELETE1_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context ,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context ,_param->_size_instruction_address); DELETE1_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context ,1); - DELETE1_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context ,_param->_size_inst_ifetch_ptr [alloc_signal_it1]); + DELETE1_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context ,_param->_size_inst_ifetch_ptr); DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_context ,_param->_size_branch_state); - DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context ,_param->_size_depth [alloc_signal_it1]); - DELETE2_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context ,_param->_nb_instruction[alloc_signal_it1],1); + DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context ,_param->_size_depth); + DELETE2_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context ,_param->_nb_instruction[it1],1); DELETE1_SIGNAL(out_PREDICT_BTB_VAL ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL( in_PREDICT_BTB_ACK ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL(out_PREDICT_BTB_CONTEXT_ID ,_param->_nb_inst_branch_predict,_param->_size_context_id); - DELETE1_SIGNAL(out_PREDICT_BTB_ADDRESS ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_BTB_ADDRESS ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); DELETE1_SIGNAL( in_PREDICT_BTB_HIT ,_param->_nb_inst_branch_predict,1); - DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_address); - DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); DELETE1_SIGNAL( in_PREDICT_BTB_CONDITION ,_param->_nb_inst_branch_predict,_param->_size_branch_condition); // DELETE1_SIGNAL( in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_branch_predict,1); @@ -54,5 +54,5 @@ DELETE1_SIGNAL(out_PREDICT_DIR_VAL ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL( in_PREDICT_DIR_ACK ,_param->_nb_inst_branch_predict,1); - DELETE1_SIGNAL(out_PREDICT_DIR_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_DIR_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); DELETE1_SIGNAL(out_PREDICT_DIR_STATIC ,_param->_nb_inst_branch_predict,1); // DELETE1_SIGNAL(out_PREDICT_DIR_LAST_TAKE ,_param->_nb_inst_branch_predict,1); @@ -64,35 +64,36 @@ DELETE1_SIGNAL( in_PREDICT_RAS_HIT ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL(out_PREDICT_RAS_PUSH ,_param->_nb_inst_branch_predict,1); - DELETE1_SIGNAL(out_PREDICT_RAS_ADDRESS_PUSH ,_param->_nb_inst_branch_predict,_param->_size_address); - DELETE1_SIGNAL( in_PREDICT_RAS_ADDRESS_POP ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_RAS_ADDRESS_PUSH ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_RAS_ADDRESS_POP ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); // DELETE1_SIGNAL( in_PREDICT_RAS_INDEX ,_param->_nb_inst_branch_predict,_param->_size_ras_index); DELETE1_SIGNAL(out_PREDICT_UPT_VAL ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL( in_PREDICT_UPT_ACK ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL(out_PREDICT_UPT_CONTEXT_ID ,_param->_nb_inst_branch_predict,_param->_size_context_id); - DELETE1_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_address); - DELETE1_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL( in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_predict,_param->_size_depth); + DELETE1_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); DELETE1_SIGNAL(out_PREDICT_UPT_BTB_CONDITION ,_param->_nb_inst_branch_predict,_param->_size_branch_condition); DELETE1_SIGNAL(out_PREDICT_UPT_BTB_LAST_TAKE ,_param->_nb_inst_branch_predict,1); DELETE1_SIGNAL(out_PREDICT_UPT_BTB_IS_ACCURATE ,_param->_nb_inst_branch_predict,1); // DELETE1_SIGNAL(out_PREDICT_UPT_DIR_HISTORY ,_param->_nb_inst_branch_predict,_param->_size_history); - DELETE1_SIGNAL(out_PREDICT_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_predict,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_predict,_param->_size_instruction_address); // DELETE1_SIGNAL(out_PREDICT_UPT_RAS_INDEX ,_param->_nb_inst_branch_predict,_param->_size_ras_index); // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - DELETE2_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1); - DELETE2_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1); - DELETE2_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_context_id ); - DELETE2_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1 ); - DELETE2_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_branch_state ); - DELETE2_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_max_size_depth ); - DELETE2_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_branch_condition); - DELETE2_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1 ); - DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_address ); - DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_address ); + DELETE2_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_branch_state ); + DELETE2_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_branch_condition); + DELETE2_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); + DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); DELETE1_SIGNAL(out_DECOD_BTB_VAL ,_param->_nb_inst_branch_decod,1); DELETE1_SIGNAL( in_DECOD_BTB_ACK ,_param->_nb_inst_branch_decod,1); DELETE1_SIGNAL(out_DECOD_BTB_CONTEXT_ID ,_param->_nb_inst_branch_decod,_param->_size_context_id); - DELETE1_SIGNAL(out_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_decod,_param->_size_address); - DELETE1_SIGNAL(out_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_decod,_param->_size_address); + DELETE1_SIGNAL(out_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); + DELETE1_SIGNAL(out_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); DELETE1_SIGNAL(out_DECOD_BTB_CONDITION ,_param->_nb_inst_branch_decod,_param->_size_branch_condition); DELETE1_SIGNAL(out_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_branch_decod,1); @@ -105,6 +106,6 @@ DELETE1_SIGNAL( in_DECOD_RAS_HIT ,_param->_nb_inst_branch_decod,1); DELETE1_SIGNAL(out_DECOD_RAS_PUSH ,_param->_nb_inst_branch_decod,1); - DELETE1_SIGNAL(out_DECOD_RAS_ADDRESS_PUSH ,_param->_nb_inst_branch_decod,_param->_size_address); - DELETE1_SIGNAL( in_DECOD_RAS_ADDRESS_POP ,_param->_nb_inst_branch_decod,_param->_size_address); + DELETE1_SIGNAL(out_DECOD_RAS_ADDRESS_PUSH ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); + DELETE1_SIGNAL( in_DECOD_RAS_ADDRESS_POP ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); // DELETE1_SIGNAL( in_DECOD_RAS_INDEX ,_param->_nb_inst_branch_decod,_param->_size_ras_index); DELETE1_SIGNAL(out_DECOD_RAS_MISS_PREDICTION,_param->_nb_inst_branch_decod,1); @@ -113,13 +114,14 @@ DELETE1_SIGNAL( in_DECOD_UPT_ACK ,_param->_nb_inst_branch_decod,1); DELETE1_SIGNAL(out_DECOD_UPT_CONTEXT_ID ,_param->_nb_inst_branch_decod,_param->_size_context_id); - DELETE1_SIGNAL(out_DECOD_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_decod,_param->_size_address); - DELETE1_SIGNAL(out_DECOD_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_decod,_param->_size_address); + DELETE1_SIGNAL(out_DECOD_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); + DELETE1_SIGNAL(out_DECOD_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); DELETE1_SIGNAL(out_DECOD_UPT_BTB_CONDITION ,_param->_nb_inst_branch_decod,_param->_size_branch_condition); DELETE1_SIGNAL(out_DECOD_UPT_BTB_LAST_TAKE ,_param->_nb_inst_branch_decod,1); - DELETE1_SIGNAL(out_DECOD_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_decod,_param->_size_address); + DELETE1_SIGNAL(out_DECOD_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_decod,_param->_size_instruction_address); // DELETE1_SIGNAL(out_DECOD_UPT_RAS_INDEX ,_param->_nb_inst_branch_decod,_param->_size_ras_index); DELETE1_SIGNAL(out_DECOD_UPT_MISS_IFETCH ,_param->_nb_inst_branch_decod,1); DELETE1_SIGNAL(out_DECOD_UPT_MISS_DECOD ,_param->_nb_inst_branch_decod,1); - DELETE1_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_decod,_param->_max_size_depth); + DELETE1_SIGNAL(out_DECOD_UPT_UPDATE_PREDICTION_ID,_param->_nb_inst_branch_decod,_param->_size_depth); + DELETE1_SIGNAL(out_DECOD_UPT_IS_ACCURATE ,_param->_nb_inst_branch_decod,1); // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -127,6 +129,6 @@ DELETE1_SIGNAL( in_UPDATE_BTB_ACK ,_param->_nb_inst_branch_update,1); // DELETE1_SIGNAL(out_UPDATE_BTB_CONTEXT_ID ,_param->_nb_inst_branch_update,_param->_size_context_id); -// DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_update,_param->_size_address); -// DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_update,_param->_size_address); +// DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_update,_param->_size_instruction_address); +// DELETE1_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_update,_param->_size_instruction_address); // DELETE1_SIGNAL(out_UPDATE_BTB_CONDITION ,_param->_nb_inst_branch_update,_param->_size_branch_condition); // DELETE1_SIGNAL(out_UPDATE_BTB_LAST_TAKE ,_param->_nb_inst_branch_update,1); @@ -135,5 +137,5 @@ DELETE1_SIGNAL(out_UPDATE_DIR_VAL ,_param->_nb_inst_branch_update,1); DELETE1_SIGNAL( in_UPDATE_DIR_ACK ,_param->_nb_inst_branch_update,1); -// DELETE1_SIGNAL(out_UPDATE_DIR_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_address); +// DELETE1_SIGNAL(out_UPDATE_DIR_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_instruction_address); // DELETE1_SIGNAL(out_UPDATE_DIR_HISTORY ,_param->_nb_inst_branch_update,_param->_size_history); // DELETE1_SIGNAL(out_UPDATE_DIR_DIRECTION ,_param->_nb_inst_branch_update,1); @@ -143,5 +145,5 @@ // DELETE1_SIGNAL(out_UPDATE_RAS_CONTEXT_ID ,_param->_nb_inst_branch_update,_param->_size_context_id); // DELETE1_SIGNAL(out_UPDATE_RAS_PUSH ,_param->_nb_inst_branch_update,1); -// DELETE1_SIGNAL(out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_address); +// DELETE1_SIGNAL(out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_instruction_address); // DELETE1_SIGNAL(out_UPDATE_RAS_INDEX ,_param->_nb_inst_branch_update,_param->_size_ras_index); // DELETE1_SIGNAL(out_UPDATE_RAS_MISS_PREDICTION ,_param->_nb_inst_branch_update,1); @@ -154,6 +156,6 @@ // DELETE1_SIGNAL( in_UPDATE_UPT_DIRECTION_GOOD ,_param->_nb_inst_branch_update,1); DELETE1_SIGNAL( in_UPDATE_UPT_BTB_VAL ,_param->_nb_inst_branch_update,1); -// DELETE1_SIGNAL( in_UPDATE_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_update,_param->_size_address); -// DELETE1_SIGNAL( in_UPDATE_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_update,_param->_size_address); +// DELETE1_SIGNAL( in_UPDATE_UPT_BTB_ADDRESS_SRC ,_param->_nb_inst_branch_update,_param->_size_instruction_address); +// DELETE1_SIGNAL( in_UPDATE_UPT_BTB_ADDRESS_DEST ,_param->_nb_inst_branch_update,_param->_size_instruction_address); // DELETE1_SIGNAL( in_UPDATE_UPT_BTB_CONDITION ,_param->_nb_inst_branch_update,_param->_size_branch_condition); DELETE1_SIGNAL( in_UPDATE_UPT_DIR_VAL ,_param->_nb_inst_branch_update,1); @@ -161,13 +163,13 @@ DELETE1_SIGNAL( in_UPDATE_UPT_RAS_VAL ,_param->_nb_inst_branch_update,1); // DELETE1_SIGNAL( in_UPDATE_UPT_RAS_PUSH ,_param->_nb_inst_branch_update,1); -// DELETE1_SIGNAL( in_UPDATE_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_address); +// DELETE1_SIGNAL( in_UPDATE_UPT_RAS_ADDRESS ,_param->_nb_inst_branch_update,_param->_size_instruction_address); // DELETE1_SIGNAL( in_UPDATE_UPT_RAS_INDEX ,_param->_nb_inst_branch_update,_param->_size_ras_index); // DELETE1_SIGNAL( in_UPDATE_UPT_RAS_PREDICTION_IFETCH,_param->_nb_inst_branch_update,1); - // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - DELETE1_SIGNAL( in_DEPTH_UPT_NB_BRANCH,_param->_nb_context,_param->_size_depth[alloc_signal_it1]+1); - DELETE1_SIGNAL( in_DEPTH_UPT_TAIL ,_param->_nb_context,_param->_size_depth[alloc_signal_it1]); - DELETE1_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context,_param->_size_depth[alloc_signal_it1]+1); - DELETE1_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth[alloc_signal_it1]); +// // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// DELETE1_SIGNAL( in_DEPTH_UPT_NB_BRANCH,_param->_nb_context,_param->_size_depth+1); +// DELETE1_SIGNAL( in_DEPTH_UPT_TAIL ,_param->_nb_context,_param->_size_depth); +// DELETE1_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context,_param->_size_depth+1); +// DELETE1_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp (revision 88) @@ -22,8 +22,10 @@ void Prediction_unit_Glue::genMealy_decod (void) { - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); - + log_begin(Prediction_unit_Glue,FUNCTION); + log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); + + // Init uint32_t decod_unit = reg_DECOD_PRIORITY; - + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * decod_unit : %d",decod_unit); @@ -49,5 +51,5 @@ if ((port>=_param->_nb_inst_branch_decod) or (PORT_READ(in_DECOD_VAL [decod_unit][i]) == 0)) - { + { log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD[%d][%d] : not valid",decod_unit,i); ack [i] = false; @@ -55,28 +57,33 @@ else { - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [decod_unit][i]):0; - Tbranch_state_t branch_state = PORT_READ(in_DECOD_BRANCH_STATE [decod_unit][i]); - Tcontrol_t match_inst_ifetch_ptr = PORT_READ(in_DECOD_MATCH_INST_IFETCH_PTR [decod_unit][i]); - Tprediction_ptr_t depth = (_param->_have_port_max_depth)?PORT_READ(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [decod_unit][i]):0; - Tcontrol_t use_btb = false; - Tcontrol_t use_ras = false; - Tcontrol_t use_upt = true ; - Tcontrol_t miss_ifetch = ( (branch_state == BRANCH_STATE_NONE) or // branch not detected - ((branch_state != BRANCH_STATE_NONE) and (match_inst_ifetch_ptr == 0))); // branch detected, but it's not the good - Tcontrol_t miss_decod; + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [decod_unit][i]):0; + Tbranch_state_t branch_state = PORT_READ(in_DECOD_BRANCH_STATE [decod_unit][i]); + Tcontrol_t match_inst_ifetch_ptr = PORT_READ(in_DECOD_MATCH_INST_IFETCH_PTR [decod_unit][i]); + Tprediction_ptr_t depth = (_param->_have_port_depth)?PORT_READ(in_DECOD_BRANCH_UPDATE_PREDICTION_ID [decod_unit][i]):0; + Tcontrol_t use_btb = false; + Tcontrol_t use_ras = false; + Tcontrol_t use_upt = true ; // always update upt. + + // Ifetch stage made an miss if : + // * branch is previously predict, but it's not the good + Tcontrol_t miss_ifetch = ((branch_state != BRANCH_STATE_NONE) and (match_inst_ifetch_ptr == 0)); + // Decod stage made an miss if : + // * branch was not detected + Tcontrol_t miss_decod = (branch_state == BRANCH_STATE_NONE); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * DECOD[%d][%d] : valid",decod_unit,i); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * depth [%d] : %d",i ,depth); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch_state : %d",branch_state); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * match_inst_ifetch_ptr : %d",match_inst_ifetch_ptr); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * depth : [%d] %d",i,depth); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * miss_ifetch : %d",miss_ifetch); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * miss_decod : %d",miss_decod); // Test if ifetch have detecte a branch is the packet - if (miss_ifetch) + if (miss_ifetch or miss_decod) { - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * miss_ifetch"); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * state : %d",branch_state); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * match : %d",match_inst_ifetch_ptr); - Tbranch_condition_t condition = PORT_READ(in_DECOD_BRANCH_CONDITION [decod_unit][i]); - Tcontrol_t direction = PORT_READ(in_DECOD_BRANCH_DIRECTION [decod_unit][i]); - Taddress_t address_src = PORT_READ(in_DECOD_ADDRESS_SRC [decod_unit][i]); - Taddress_t address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [decod_unit][i]); + Tbranch_condition_t condition = PORT_READ(in_DECOD_BRANCH_CONDITION [decod_unit][i]); + Tcontrol_t direction = PORT_READ(in_DECOD_BRANCH_DIRECTION [decod_unit][i]); + Taddress_t address_src = PORT_READ(in_DECOD_ADDRESS_SRC [decod_unit][i]); + Taddress_t address_dest = PORT_READ(in_DECOD_ADDRESS_DEST [decod_unit][i]); Tcontrol_t is_accurate; @@ -88,35 +95,38 @@ case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : { - // Write stack + // l.jal + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITH_WRITE_STACK"); + + is_accurate = true ;//PORT_READ(in_DECOD_RAS_HIT [port]); + use_ras = true ; + + PORT_WRITE(out_DECOD_RAS_PUSH [port],1); + PORT_WRITE(out_DECOD_RAS_ADDRESS_PUSH [port],address_src+2); + + break; + } + + case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : + { + // l.jalr + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK"); + + is_accurate = false; // address unknow : in a register + use_ras = true; + + PORT_WRITE(out_DECOD_RAS_PUSH [port],1); + PORT_WRITE(out_DECOD_RAS_ADDRESS_PUSH [port],address_src+2); + + break; + } + case BRANCH_CONDITION_READ_STACK : + { + // l.jr with rb=r9 + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_STACK"); + is_accurate = PORT_READ(in_DECOD_RAS_HIT [port]); - miss_decod = false; use_ras = true; - PORT_WRITE(out_DECOD_RAS_PUSH [port],1); - PORT_WRITE(out_DECOD_RAS_ADDRESS_PUSH [port],address_dest); - - break; - } - - case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : - { - // Write stack - is_accurate = false; - miss_decod = false; - use_ras = true; - - PORT_WRITE(out_DECOD_RAS_PUSH [port],1); - PORT_WRITE(out_DECOD_RAS_ADDRESS_PUSH [port],address_dest); - - break; - } - case BRANCH_CONDITION_READ_STACK : - { - // Read stack - is_accurate = PORT_READ(in_DECOD_RAS_HIT [port]); - miss_decod = false; - use_ras = true; - - PORT_WRITE(out_DECOD_RAS_PUSH [port],0); + PORT_WRITE(out_DECOD_RAS_PUSH [port],0); // POP address_dest = PORT_READ(in_DECOD_RAS_ADDRESS_POP [port]); @@ -125,7 +135,9 @@ case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : { + // l.jr with rb!=r9 + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK"); + // * READ_REGISTER_WITHOUT_WRITE_STACK : Take but destination is unknow - don't continue - is_accurate = PORT_READ(in_DECOD_RAS_HIT [port]); - miss_decod = true; + is_accurate = false; // address unknow : in a register break; @@ -135,8 +147,9 @@ case BRANCH_CONDITION_FLAG_SET : { - // No access at the flag + // l.bf, l.bnf // * FLAG : static direction and destination is know - is_accurate = PORT_READ(in_DECOD_RAS_HIT [port]); - miss_decod = false; + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_FLAG"); + + is_accurate = true; // address dest is know break; @@ -145,16 +158,11 @@ case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : { - // No access at the flag - // * NONE_WITHOUT_WRITE_STACK : take and destination is know - is_accurate = false; - miss_decod = false; - use_ras = true; - - PORT_WRITE(out_DECOD_RAS_PUSH [port],1); - PORT_WRITE(out_DECOD_RAS_ADDRESS_PUSH [port],address_dest); - - break; - } - + // l.j + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK"); + + is_accurate = true; + + break; + } } @@ -180,19 +188,21 @@ if (use_upt) { - PORT_WRITE(out_DECOD_UPT_BTB_ADDRESS_SRC [port],address_src); - PORT_WRITE(out_DECOD_UPT_BTB_ADDRESS_DEST [port],address_dest); - PORT_WRITE(out_DECOD_UPT_BTB_CONDITION [port],condition); - PORT_WRITE(out_DECOD_UPT_BTB_LAST_TAKE [port],direction); - PORT_WRITE(out_DECOD_UPT_RAS_ADDRESS [port],PORT_READ(in_DECOD_RAS_ADDRESS_POP [port])); + PORT_WRITE(out_DECOD_UPT_BTB_ADDRESS_SRC [port],address_src); + PORT_WRITE(out_DECOD_UPT_BTB_ADDRESS_DEST[port],address_dest); + PORT_WRITE(out_DECOD_UPT_BTB_CONDITION [port],condition); + PORT_WRITE(out_DECOD_UPT_BTB_LAST_TAKE [port],direction); + PORT_WRITE(out_DECOD_UPT_RAS_ADDRESS [port],PORT_READ(in_DECOD_RAS_ADDRESS_POP [port])); + PORT_WRITE(out_DECOD_UPT_IS_ACCURATE [port],is_accurate); } } - else - { - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit"); - - miss_decod = false; - // Hit speculation - } - +// else +// { +// log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit"); + +// miss_decod = false; +// // Hit speculation +// } + + // in all case log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * use_btb : %d",use_btb); @@ -231,5 +241,5 @@ PORT_WRITE(out_DECOD_UPT_MISS_IFETCH [port],miss_ifetch); PORT_WRITE(out_DECOD_UPT_MISS_DECOD [port],miss_decod ); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) PORT_WRITE(out_DECOD_UPT_UPDATE_PREDICTION_ID [port],depth); @@ -237,4 +247,6 @@ } + // Write output + for (uint32_t i=0; i<_param->_nb_inst_branch_decod; i++) { @@ -251,5 +263,5 @@ PORT_WRITE(out_DECOD_ACK [i][j], ack[j]); - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); + log_end(Prediction_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 88) @@ -22,293 +22,294 @@ void Prediction_unit_Glue::genMealy_predict (void) { - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); + log_begin(Prediction_unit_Glue,FUNCTION); + log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); Tcontrol_t ack [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) { - ack [i] = 0; - - if (_param->_have_port_depth[i]) - { - PORT_WRITE(out_DEPTH_TAIL [i],PORT_READ(in_DEPTH_UPT_TAIL [i])); - } - PORT_WRITE(out_DEPTH_NB_BRANCH [i],PORT_READ(in_DEPTH_UPT_NB_BRANCH [i])); + ack [i] = 0; + +// if (_param->_have_port_depth) +// { +// PORT_WRITE(out_DEPTH_TAIL [i],PORT_READ(in_DEPTH_UPT_TAIL [i])); +// } +// PORT_WRITE(out_DEPTH_NB_BRANCH [i],PORT_READ(in_DEPTH_UPT_NB_BRANCH [i])); } for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) { - log_printf(TRACE,Prediction_unit_Glue,FUNCTION,"PREDICT [%d]",i); - - Tcontrol_t btb_val; - Tcontrol_t dir_val; - Tcontrol_t ras_val; - Tcontrol_t upt_val; - - Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); - - ack [context] = 1; - - if (PORT_READ(in_PREDICT_VAL[context]) == 0) - { - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); - - btb_val = false; - dir_val = false; - ras_val = false; - upt_val = false; - } - else - { - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); - - Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); - Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); - Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); - - Taddress_t pc_next ; - Tcontrol_t pc_next_is_ds_take ; - Tbranch_state_t branch_state ; - Tprediction_ptr_t branch_update_prediction_id ; - Tinst_ifetch_ptr_t inst_ifetch_ptr ; - - // STEP (1) - Compute the address source - Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; - Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 - Taddress_t address_msb; - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%x",address); - - // STEP (2) - Test if branch (access at branch_target_buffer) - btb_val = true; - ack [context] &= PORT_READ(in_PREDICT_BTB_ACK [i]); - - if (_param->_have_port_context_id) - PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); - PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); - - // special case : - // if pc_current_is_ds, then pc_previous have branch, also hit must be set. - // else : a another branch have eject this branch : can't accurate - Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); - Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); - - // STEP (3) : Test if have branch in the packet - if (hit == 1) - { - // STEP (3a) : branch - test condition - - bool use_dir = false; - bool use_ras = false; - bool use_upt = false; - - Tbranch_condition_t cond = PORT_READ(in_PREDICT_BTB_CONDITION [i]); - Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); - Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); - Tcontrol_t push; - Tcontrol_t direction; - - switch (cond) - { - case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j - { - // use none unit (dir, upt and ras) - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_FLAG_UNSET : // l.bnf - case BRANCH_CONDITION_FLAG_SET : // l.bf - { - use_upt = true; - use_dir = true; - // Test direction - direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same - if (direction = 1) - { - branch_state = BRANCH_STATE_SPEC_TAKE; - pc_next = address_dest; - } - else - { - branch_state = BRANCH_STATE_SPEC_NTAKE; - pc_next = address_src+2; // +1 = delay slot - } - break; - } - case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_SPEC_TAKE; - break; - } - case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr - { - use_upt = true; - use_ras = true; - push = true; - direction = true; - pc_next = address_dest; - branch_state = BRANCH_STATE_NSPEC_TAKE; - break; - } - case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) - { - use_upt = true; - use_ras = true; - push = false; - direction = true; - pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); - branch_state = BRANCH_STATE_SPEC_TAKE; - break; - } - default : - { - ERRORMORPHEO(FUNCTION,"Unknow Condition"); - break; - } - } - - if (use_dir) - { - ack[context] &= PORT_READ(in_PREDICT_DIR_ACK [i]); - PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); - PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest_have_port_context_id) - PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); - PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); - PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); - - is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate - } - - if (use_upt) - { - ack[context] &= PORT_READ(in_PREDICT_UPT_ACK [i]); - - PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); - PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); - PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); - PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],cond); - PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); - PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); -// PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); - PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); -// PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); - } - - // ack = 1 if : - // * btb_ack - // * use_dir and dir_ack - // * use_ras and ras_ack - // * use_upt and upt_ack -// ack [context] = (PORT_READ(in_PREDICT_BTB_ACK [i]) and -// (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i])) and -// (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])) and -// (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i]))); - - dir_val = (use_dir and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i]))) and - (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); - - ras_val = (use_ras and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and - (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); - - upt_val = (use_upt and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and - (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])))); - -// pc_next - is previously computed -// branch_state - is previously computed - - Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); - if (address_src_lsb == (_param->_nb_instruction [context]-1)) - { - // branch is in the last slot of the packet - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); - - address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) - pc_next_is_ds_take = 1; - } - else - { - // branch is in the last slot of the packet - address_msb = (address_src_lsb+2); // +1 == delayed slot - pc_next_is_ds_take = 0; - } - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); - - inst_ifetch_ptr = address_src_lsb; - branch_update_prediction_id = (_param->_have_port_depth[context])?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_size_depth[context]):0; - } - else - { - // STEP (3b) : Sequential order : compute next paquet - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); - - pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial - pc_next_is_ds_take = 0; // no branch, also no delay slot - inst_ifetch_ptr = 0; - branch_state = BRANCH_STATE_NONE; - branch_update_prediction_id = 0; - - address_msb = _param->_nb_instruction [context]; - } - - PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); - PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); - - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0",address_lsb); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_lsb,((pc_current_is_ds_take)?1:address_msb)); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",((pc_current_is_ds_take)?1:address_msb),_param->_nb_instruction [context]); - - for (uint32_t j=0; j_nb_instruction [context]; j++) - PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid - if (_param->_have_port_inst_ifetch_ptr[context]) - PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); - PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); - if (_param->_have_port_depth[context]) - PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , branch_update_prediction_id); - } - - // Write output - PORT_WRITE(out_PREDICT_BTB_VAL [i], btb_val); - PORT_WRITE(out_PREDICT_DIR_VAL [i], dir_val); - PORT_WRITE(out_PREDICT_RAS_VAL [i], ras_val); - PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); + + Tcontrol_t btb_val; + Tcontrol_t dir_val; + Tcontrol_t ras_val; + Tcontrol_t upt_val; + + Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); + + ack [context] = 1; + + if (PORT_READ(in_PREDICT_VAL[context]) == 0) + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); + + btb_val = false; + dir_val = false; + ras_val = false; + upt_val = false; + } + else + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * valid ..."); + + Taddress_t pc_previous = PORT_READ(in_PREDICT_PC_PREVIOUS [context]); + Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); + Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); + + Taddress_t pc_next ; + Tcontrol_t pc_next_is_ds_take ; + Tbranch_state_t branch_state ; +// Tprediction_ptr_t branch_update_prediction_id ; + Tinst_ifetch_ptr_t inst_ifetch_ptr ; + + // STEP (1) - Compute the address source + Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; + Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 + Taddress_t address_msb; + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%x",address); + + // STEP (2) - Test if branch (access at branch_target_buffer) + btb_val = true; + ack [context] &= PORT_READ(in_PREDICT_BTB_ACK [i]); + + if (_param->_have_port_context_id) + PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); + PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); + + // special case : + // if pc_current_is_ds, then pc_previous have branch, also hit must be set. + // else : a another branch have eject this branch : can't accurate + Tcontrol_t hit = PORT_READ(in_PREDICT_BTB_HIT[i]); + Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); + + // STEP (3) : Test if have branch in the packet + if (hit == 1) + { + // STEP (3a) : branch - test condition + + bool use_dir = false; + bool use_ras = false; + bool use_upt = false; + + Tbranch_condition_t cond = PORT_READ(in_PREDICT_BTB_CONDITION [i]); + Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); + Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); + Tcontrol_t push; + Tcontrol_t direction; + + switch (cond) + { + case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j + { + // use none unit (dir, upt and ras) + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_NONE_WITH_WRITE_STACK : // l.jal + { + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_FLAG_UNSET : // l.bnf + case BRANCH_CONDITION_FLAG_SET : // l.bf + { + use_upt = true; + use_dir = true; + // Test direction + direction = PORT_READ(in_PREDICT_DIR_DIRECTION [i]); // Direction is not the "flag predict" ... also flag_unset and flag_set is the same + if (direction = 1) + { + branch_state = BRANCH_STATE_SPEC_TAKE; + pc_next = address_dest; + } + else + { + branch_state = BRANCH_STATE_SPEC_NTAKE; + pc_next = address_src+2; // +1 = delay slot + } + break; + } + case BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : // l.jr (rb!=9) + { + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_SPEC_TAKE; + break; + } + case BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : // l.jalr + { + use_upt = true; + use_ras = true; + push = true; + direction = true; + pc_next = address_dest; + branch_state = BRANCH_STATE_NSPEC_TAKE; + break; + } + case BRANCH_CONDITION_READ_STACK : // l.jr (rb==9) + { + use_upt = true; + use_ras = true; + push = false; + direction = true; + pc_next = PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i]); + branch_state = BRANCH_STATE_SPEC_TAKE; + break; + } + default : + { + ERRORMORPHEO(FUNCTION,"Unknow Condition"); + break; + } + } + + if (use_dir) + { + ack[context] &= PORT_READ(in_PREDICT_DIR_ACK [i]); + PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); + PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest_have_port_context_id) + PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); + PORT_WRITE(out_PREDICT_RAS_PUSH [i], push); + PORT_WRITE(out_PREDICT_RAS_ADDRESS_PUSH [i], address_src+2); + + is_accurate &= PORT_READ(in_PREDICT_RAS_HIT [i]); // if miss - prediction is not accurate + } + + if (use_upt) + { + ack[context] &= PORT_READ(in_PREDICT_UPT_ACK [i]); + + PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); + PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); + PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); + PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],cond); + PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); + PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); +// PORT_WRITE(out_PREDICT_UPT_DIR_HISTORY [i],PORT_READ(in_PREDICT_DIR_HISTORY [i])); + PORT_WRITE(out_PREDICT_UPT_RAS_ADDRESS [i],PORT_READ(in_PREDICT_RAS_ADDRESS_POP [i])); +// PORT_WRITE(out_PREDICT_UPT_RAS_INDEX [i],PORT_READ(in_PREDICT_RAS_INDEX [i])); + } + + // ack = 1 if : + // * btb_ack + // * use_dir and dir_ack + // * use_ras and ras_ack + // * use_upt and upt_ack +// ack [context] = (PORT_READ(in_PREDICT_BTB_ACK [i]) and +// (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i])) and +// (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])) and +// (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i]))); + + dir_val = (use_dir and + PORT_READ(in_PREDICT_BTB_ACK [i]) and + (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i]))) and + (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); + + ras_val = (use_ras and + PORT_READ(in_PREDICT_BTB_ACK [i]) and + (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and + (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); + + upt_val = (use_upt and + PORT_READ(in_PREDICT_BTB_ACK [i]) and + (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and + (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])))); + +// pc_next - is previously computed +// branch_state - is previously computed + + Taddress_t address_src_lsb = address_src%_param->_nb_instruction [context]; + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); + if (address_src_lsb == (_param->_nb_instruction [context]-1)) + { + // branch is in the last slot of the packet + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * branch is in the last slot of the packet"); + + address_msb = _param->_nb_instruction [context]; // == (address_src_lsb+1) + pc_next_is_ds_take = 1; + } + else + { + // branch is in the last slot of the packet + address_msb = (address_src_lsb+2); // +1 == delayed slot + pc_next_is_ds_take = 0; + } + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_msb : %d",address_msb); + + inst_ifetch_ptr = address_src_lsb; +// branch_update_prediction_id = (_param->_have_port_depth)?((PORT_READ(in_DEPTH_UPT_TAIL[context])+PORT_READ(in_DEPTH_UPT_NB_BRANCH [context]))%_param->_array_size_depth[context]):0; + } + else + { + // STEP (3b) : Sequential order : compute next paquet + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * BTB miss : sequential order"); + + pc_next = address-address_lsb+_param->_nb_instruction [context]; // sequencial + pc_next_is_ds_take = 0; // no branch, also no delay slot + inst_ifetch_ptr = 0; + branch_state = BRANCH_STATE_NONE; +// branch_update_prediction_id = 0; + + address_msb = _param->_nb_instruction [context]; + } + + PORT_WRITE(out_PREDICT_PC_NEXT [context] , pc_next ); + PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0",address_lsb); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_lsb,((pc_current_is_ds_take)?1:address_msb)); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",((pc_current_is_ds_take)?1:address_msb),_param->_nb_instruction [context]); + + for (uint32_t j=0; j_nb_instruction [context]; j++) + PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid + if (_param->_have_port_inst_ifetch_ptr) + PORT_WRITE(out_PREDICT_INST_IFETCH_PTR [context] , inst_ifetch_ptr ); + PORT_WRITE(out_PREDICT_BRANCH_STATE [context] , branch_state ); + if (_param->_have_port_depth) + PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [context] , PORT_READ(in_PREDICT_UPT_BRANCH_UPDATE_PREDICTION_ID [i])); + } + + // Write output + PORT_WRITE(out_PREDICT_BTB_VAL [i], btb_val); + PORT_WRITE(out_PREDICT_DIR_VAL [i], dir_val); + PORT_WRITE(out_PREDICT_RAS_VAL [i], ras_val); + PORT_WRITE(out_PREDICT_UPT_VAL [i], upt_val); } @@ -316,5 +317,5 @@ PORT_WRITE(out_PREDICT_ACK[i],ack[i]); - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); + log_end(Prediction_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp (revision 88) @@ -22,5 +22,5 @@ void Prediction_unit_Glue::genMealy_update (void) { - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); + log_begin(Prediction_unit_Glue,FUNCTION); // for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) @@ -52,5 +52,5 @@ // } - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); + log_end(Prediction_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_transition.cpp (revision 88) @@ -22,5 +22,5 @@ void Prediction_unit_Glue::transition (void) { - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"Begin"); + log_begin(Prediction_unit_Glue,FUNCTION); if (PORT_READ(in_NRESET) == 0) @@ -39,5 +39,5 @@ #endif - log_printf(FUNC,Prediction_unit_Glue,FUNCTION,"End"); + log_end(Prediction_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Return_Address_Stack_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_mono_context.cfg (revision 88) @@ -3,5 +3,5 @@ 2 4 *2 # size_queue [0] 32 32 *2 # size_address -1 1 +1 # nb_inst_predict -1 1 +1 # nb_inst_decod -1 1 +1 # nb_inst_update +1 4 *4 # nb_inst_predict +1 4 *4 # nb_inst_decod +1 4 *4 # nb_inst_update Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/config_multi_context.cfg (revision 88) @@ -4,7 +4,7 @@ 4 4 *2 # size_queue [1] 8 8 *2 # size_queue [2] -16 16 *2 # size_queue [3] +8 8 *2 # size_queue [3] 32 32 *2 # size_address -1 1 +1 # nb_inst_predict -1 1 +1 # nb_inst_decod -1 1 +1 # nb_inst_update +1 4 *4 # nb_inst_predict +1 4 *4 # nb_inst_decod +1 4 *4 # nb_inst_update Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/main.cpp (revision 88) @@ -60,5 +60,7 @@ _nb_inst_predict , _nb_inst_decod , - _nb_inst_update ); + _nb_inst_update , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Return_Address_Stack * _Return_Address_Stack = new Return_Address_Stack (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -403,6 +413,5 @@ in_DECOD_VAL [port1]->write(0); - - } + } } @@ -419,29 +428,31 @@ delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - delete [] in_PREDICT_CONTEXT_ID ; - delete [] out_PREDICT_HIT ; - delete [] in_PREDICT_PUSH ; - delete [] in_PREDICT_ADDRESS_PUSH ; - delete [] out_PREDICT_ADDRESS_POP ; - delete [] out_PREDICT_INDEX ; - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - delete [] in_DECOD_PUSH ; - delete [] in_DECOD_CONTEXT_ID ; - delete [] out_DECOD_HIT ; - delete [] in_DECOD_ADDRESS_PUSH ; - delete [] out_DECOD_ADDRESS_POP ; - delete [] out_DECOD_INDEX ; - delete [] in_DECOD_MISS_PREDICTION; - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - delete [] in_UPDATE_CONTEXT_ID ; - delete [] in_UPDATE_PUSH ; - delete [] in_UPDATE_INDEX ; - delete [] in_UPDATE_ADDRESS ; - delete [] in_UPDATE_MISS_PREDICTION; - delete [] in_UPDATE_PREDICTION_IFETCH; + DELETE1_SC_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL( in_PREDICT_PUSH ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL( in_PREDICT_ADDRESS_PUSH ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_POP ,_param->_nb_inst_predict); + DELETE1_SC_SIGNAL(out_PREDICT_INDEX ,_param->_nb_inst_predict); + + DELETE1_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_HIT ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_PUSH ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_ADDRESS_PUSH ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_POP ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_INDEX ,_param->_nb_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod); + + DELETE1_SC_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_PREDICTION_IFETCH,_param->_nb_inst_update); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Parameters.h (revision 88) @@ -26,13 +26,13 @@ public : uint32_t _nb_context ; public : uint32_t * _size_queue ;//[nb_context] - public : uint32_t _size_address ; +//public : uint32_t _size_address ; public : uint32_t _nb_inst_predict; public : uint32_t _nb_inst_decod ; public : uint32_t _nb_inst_update ; - public : uint32_t _size_context_id; +//public : uint32_t _size_context_id; public : uint32_t _size_index ; - public : uint32_t _have_port_context_id; +//public : uint32_t _have_port_context_id; //-----[ methods ]----------------------------------------------------------- @@ -42,7 +42,11 @@ uint32_t nb_inst_predict, uint32_t nb_inst_decod , - uint32_t nb_inst_update ); + uint32_t nb_inst_update , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp (revision 88) @@ -25,5 +25,7 @@ uint32_t nb_inst_predict, uint32_t nb_inst_decod , - uint32_t nb_inst_update ) + uint32_t nb_inst_update , + bool is_toplevel + ) { log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); @@ -31,15 +33,21 @@ _nb_context = nb_context ; _size_queue = size_queue ; - _size_address = size_address ; _nb_inst_predict = nb_inst_predict; _nb_inst_decod = nb_inst_decod ; _nb_inst_update = nb_inst_update ; - _size_context_id = log2(nb_context); _size_index = max(size_queue,nb_context); - _have_port_context_id = _size_context_id > 0; + test(); - test(); + if (is_toplevel) + { + _size_instruction_address = size_address ; + _size_context_id = log2(nb_context); + _have_port_context_id = _size_context_id > 0; + + copy (); + } + log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); }; @@ -62,4 +70,12 @@ }; +#undef FUNCTION +#define FUNCTION "Return_Address_Stack::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); + log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); + }; + }; // end namespace return_address_stack }; // end namespace prediction_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_msg_error.cpp (revision 88) @@ -29,5 +29,5 @@ for (uint32_t i=0; i<_nb_context; i++) if (_size_queue [i] < 2) - test.error("context \""+toString(i)+"\" : size_queue must be > 2"); + test.error(toString(_("context \"%d\" : size_queue must be >= 2\n"),i)); log_printf(FUNC,Return_Address_Stack,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters_print.cpp (revision 88) @@ -28,5 +28,5 @@ xml.balise_open("return_address_stack"); xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("nb_inst_predict"); xml.attribut("value",toString(_nb_inst_predict)); xml.singleton_end(); xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); +#if DEBUG_Return_Address_Stac == true + log_printf(INFO,Return_Address_Stac,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Return_Address_Stack,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Return_Address_Stack,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { for (uint32_t i=0; i<_param->_nb_inst_predict; i++) @@ -165,5 +171,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 88) @@ -17,15 +17,13 @@ namespace return_address_stack { - - #undef FUNCTION #define FUNCTION "Return_Address_Stack::allocation" void Return_Address_Stack::allocation ( #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * param_statistics + morpheo::behavioural::Parameters_Statistics * param_statistics #else - void + void #endif - ) + ) { log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); @@ -65,6 +63,6 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_HIT ,"hit" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_PREDICT_PUSH ,"push" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_PUSH,"address_push",Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_ADDRESS_PUSH,"address_push",Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_PREDICT_INDEX ,"index" ,Tptr_t ,_param->_size_index); } @@ -79,6 +77,6 @@ ALLOC1_SIGNAL_OUT(out_DECOD_HIT ,"hit" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_DECOD_PUSH ,"push" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_PUSH ,"address_push" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_ADDRESS_PUSH ,"address_push" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS_POP ,"address_pop" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_DECOD_INDEX ,"index" ,Tptr_t ,_param->_size_index); ALLOC1_SIGNAL_IN ( in_DECOD_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); @@ -89,14 +87,16 @@ ALLOC1_INTERFACE("update", IN, SOUTH, "update's interface", _param->_nb_inst_update); - ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); - ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); - ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_UPDATE_PUSH ,"push" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_UPDATE_INDEX ,"index" ,Tptr_t ,_param->_size_index); - ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); + ALLOC1_VALACK_IN ( in_UPDATE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_UPDATE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_UPDATE_PUSH ,"push" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_UPDATE_INDEX ,"index" ,Tptr_t ,_param->_size_index); + ALLOC1_SIGNAL_IN ( in_UPDATE_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_PREDICTION_IFETCH,"prediction_ifetch",Tcontrol_t,1); } + if (usage_is_set(_usage,USE_SYSTEMC)) + { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -118,9 +118,11 @@ internal_DECOD_HIT = new Tcontrol_t [_param->_nb_inst_decod ]; internal_UPDATE_ACK = new Tcontrol_t [_param->_nb_inst_update ]; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -23,54 +24,55 @@ log_printf(FUNC,Return_Address_Stack,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; delete in_NRESET; - delete [] in_PREDICT_VAL ; - delete [] out_PREDICT_ACK ; - if (_param->_have_port_context_id) - delete [] in_PREDICT_CONTEXT_ID ; - delete [] out_PREDICT_HIT ; - delete [] in_PREDICT_PUSH ; - delete [] in_PREDICT_ADDRESS_PUSH ; - delete [] out_PREDICT_ADDRESS_POP ; - delete [] out_PREDICT_INDEX ; - delete [] in_DECOD_VAL ; - delete [] out_DECOD_ACK ; - delete [] in_DECOD_PUSH ; - if (_param->_have_port_context_id) - delete [] in_DECOD_CONTEXT_ID ; - delete [] out_DECOD_HIT ; - delete [] in_DECOD_ADDRESS_PUSH ; - delete [] out_DECOD_ADDRESS_POP ; - delete [] out_DECOD_INDEX ; - delete [] in_DECOD_MISS_PREDICTION; - delete [] in_UPDATE_VAL ; - delete [] out_UPDATE_ACK ; - if (_param->_have_port_context_id) - delete [] in_UPDATE_CONTEXT_ID ; - delete [] in_UPDATE_PUSH ; - delete [] in_UPDATE_INDEX ; - delete [] in_UPDATE_ADDRESS ; - delete [] in_UPDATE_MISS_PREDICTION; - delete [] in_UPDATE_PREDICTION_IFETCH; + DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict,_param->_size_context_id); + DELETE1_SIGNAL(out_PREDICT_HIT ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_PUSH ,_param->_nb_inst_predict,1); + DELETE1_SIGNAL( in_PREDICT_ADDRESS_PUSH ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_ADDRESS_POP ,_param->_nb_inst_predict,_param->_size_instruction_address); + DELETE1_SIGNAL(out_PREDICT_INDEX ,_param->_nb_inst_predict,_param->_size_index); + + DELETE1_SIGNAL( in_DECOD_VAL ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL(out_DECOD_ACK ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod,_param->_size_context_id); + DELETE1_SIGNAL(out_DECOD_HIT ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_PUSH ,_param->_nb_inst_decod,1); + DELETE1_SIGNAL( in_DECOD_ADDRESS_PUSH ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL(out_DECOD_ADDRESS_POP ,_param->_nb_inst_decod,_param->_size_instruction_address); + DELETE1_SIGNAL(out_DECOD_INDEX ,_param->_nb_inst_decod,_param->_size_index); + DELETE1_SIGNAL( in_DECOD_MISS_PREDICTION ,_param->_nb_inst_decod,1); + + DELETE1_SIGNAL( in_UPDATE_VAL ,_param->_nb_inst_update,1); + DELETE1_SIGNAL(out_UPDATE_ACK ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); + DELETE1_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); + DELETE1_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update,_param->_size_index); + DELETE1_SIGNAL( in_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_PREDICTION_IFETCH,_param->_nb_inst_update,1); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + for (uint32_t i=0; i<_param->_nb_context; i++) + delete [] reg_stack [i]; + delete [] reg_stack; + delete [] reg_TOP; + delete [] reg_BOTTOM; + delete [] reg_NB_ELT; + delete [] reg_PREDICT_TOP; + delete [] reg_PREDICT_BOTTOM; + delete [] reg_PREDICT_NB_ELT; + + delete [] internal_PREDICT_ACK; + delete [] internal_PREDICT_HIT; + delete [] internal_DECOD_ACK; + delete [] internal_DECOD_HIT; + delete [] internal_UPDATE_ACK; } - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - delete [] reg_stack; - delete [] reg_TOP; - delete [] reg_BOTTOM; - delete [] reg_NB_ELT; - delete [] reg_PREDICT_TOP; - delete [] reg_PREDICT_BOTTOM; - delete [] reg_PREDICT_NB_ELT; - - delete [] internal_PREDICT_ACK; - delete [] internal_PREDICT_HIT; - delete [] internal_DECOD_ACK; - delete [] internal_DECOD_HIT; - delete [] internal_UPDATE_ACK; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 88) @@ -191,5 +191,5 @@ // Scan full assoc !!! - for (uint32_t j=0; j<_param->_size_queue [i]; j++) + for (uint32_t j=0; j<_param->_size_queue [context]; j++) // Test if this slot is tagged with "predict" : if true, tagged as miss if (reg_stack [context][j]._predict) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Prediction_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg (revision 88) @@ -36,3 +36,3 @@ 1 1 +1 # dir_pht_size_address_share [2] [3] 2 2 +1 # ras_size_queue [0] [nb_context] -1 1 +1 # upt_size_queue [0] [nb_context] +2 2 +1 # upt_size_queue [0] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg (revision 88) @@ -4,9 +4,9 @@ 30 30 +1 # size_address 1 4 *4 # nb_instruction [0] [nb_context] -1 1 +1 # nb_inst_decod [0] [nb_decod_unit] +1 4 *4 # nb_inst_decod [0] [nb_decod_unit] 1 1 +1 # nb_inst_branch_predict -1 1 +1 # nb_inst_branch_decod -1 1 +1 # nb_inst_branch_update -1 1 +1 # nb_inst_branch_complete +1 2 +1 # nb_inst_branch_decod +1 2 +1 # nb_inst_branch_update +1 2 +1 # nb_inst_branch_complete 2 8 *4 # btb_size_queue 2 2 +1 # btb_associativity @@ -36,3 +36,3 @@ 1 1 +1 # dir_pht_size_address_share [2] [3] 2 4 *2 # ras_size_queue [0] [nb_context] -1 4 *4 # upt_size_queue [0] [nb_context] +2 4 *2 # upt_size_queue [0] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg (revision 88) @@ -45,3 +45,3 @@ 4 4 *4 # upt_size_queue [1] [nb_context] 4 4 *4 # upt_size_queue [2] [nb_context] -1 1 *4 # upt_size_queue [3] [nb_context] +8 8 *4 # upt_size_queue [3] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp (revision 88) @@ -129,5 +129,6 @@ _dir_pht_size_address_share, _ras_size_queue , - _upt_size_queue + _upt_size_queue , + true // is_toplevel ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 88) @@ -8,5 +8,5 @@ #define NB_ITERATION 1 -#define CYCLE_MAX (128*NB_ITERATION) +#define CYCLE_MAX 1000000 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/include/test.h" @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Prediction_unit * _Prediction_unit = new Prediction_unit (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -48,19 +58,19 @@ ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT ,"out_PREDICT_PC_NEXT ",Taddress_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"out_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); - ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + ALLOC2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,"out_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_context,_param->_nb_instruction[it1]); ALLOC1_SC_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,"out_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_context); - ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID ," in_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + ALLOC2_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ," in_DECOD_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_STATE ," in_DECOD_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID ," in_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ," in_DECOD_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ," in_DECOD_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ," in_DECOD_ADDRESS_SRC ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ," in_DECOD_ADDRESS_DEST ",Taddress_t ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -83,6 +93,7 @@ ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,"out_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL(out_DEPTH_TAIL ,"out_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); /******************************************************** @@ -102,27 +113,22 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context); - INSTANCE2_SC_SIGNAL(_Prediction_unit,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit,out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_context); - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - if (_param->_have_port_inst_ifetch_ptr [i]) - INSTANCE_SC_SIGNAL(_Prediction_unit,out_PREDICT_INST_IFETCH_PTR [i]); - if (_param->_have_port_depth [i]) - INSTANCE_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]); - } - - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + if (_param->_have_port_inst_ifetch_ptr) + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit,out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); if (_param->_have_port_context_id) - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - if (_param->_have_port_max_depth) - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Prediction_unit, in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); @@ -130,5 +136,5 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); @@ -148,8 +154,10 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); - INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_NB_BRANCH ,_param->_nb_context); - for (uint32_t i=0; i<_param->_nb_context; i++) - if (_param->_have_port_depth[i]) - INSTANCE_SC_SIGNAL(_Prediction_unit,out_DEPTH_TAIL [i]); + if (_param->_have_port_depth) + { + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context); + } + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MAX ,_param->_nb_context); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -166,8 +174,33 @@ //const uint32_t seed = static_cast(time(NULL)); + const int32_t percent_transaction_predict = 80; + const int32_t percent_transaction_decod = 80; + const int32_t percent_transaction_branch_complete = 80; + const int32_t percent_transaction_branch_event = 80; + srand(seed); + + uint32_t test1 = 1024; // TEST 1 : instruction without branch + uint32_t test2 = 1024; // TEST 2 : sequence : 1 branch, 1 delayed slot SC_START(0); LABEL("Initialisation"); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + in_PREDICT_VAL [i]->write(0); + in_BRANCH_EVENT_ACK [i]->write(0); + } + + for (uint32_t i=0; i<_param->_nb_decod_unit;++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + { + in_DECOD_VAL [i][j]->write(0); + } + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + in_BRANCH_COMPLETE_VAL [i]->write(0); + } LABEL("Reset"); @@ -176,9 +209,91 @@ in_NRESET->write(1); + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request + TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); + } + + for (uint32_t i=0; i<_param->_nb_decod_unit;++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + { + TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction + } + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete + } + LABEL("Loop of Test"); + Taddress_t PC_PREVIOUS [_param->_nb_context]; + Taddress_t PC_CURRENT [_param->_nb_context]; + Tcontrol_t PC_CURRENT_IS_DS_TAKE [_param->_nb_context]; + for (uint32_t iteration=0; iteration_nb_context; ++i) + { + PC_CURRENT [i] = (0x100000>>2); + PC_CURRENT_IS_DS_TAKE [i] = 0; + PC_PREVIOUS [i] = PC_CURRENT[i]-1; + } + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + in_PREDICT_VAL [i]->write((rand()%100)write(PC_PREVIOUS [i]); + in_PREDICT_PC_CURRENT [i]->write(PC_CURRENT [i]); + in_PREDICT_PC_CURRENT_IS_DS_TAKE [i]->write(PC_CURRENT_IS_DS_TAKE[i]); + } + + SC_START(1); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + // Test if transaction + if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read()) + { + TEST(Taddress_t ,out_PREDICT_PC_NEXT [i]->read(),PC_CURRENT[i]+_param->_nb_instruction[i]); + TEST(Tcontrol_t ,out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read(),0); + for (uint32_t j=0; j<_param->_nb_instruction[i]; ++j) + TEST(Tcontrol_t ,out_PREDICT_INSTRUCTION_ENABLE [i][j]->read(),1); + TEST(Tinst_ifetch_ptr_t,out_PREDICT_INST_IFETCH_PTR [i]->read(),0); + TEST(Tbranch_state_t ,out_PREDICT_BRANCH_STATE [i]->read(),BRANCH_STATE_NONE); + TEST(Tprediction_ptr_t ,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(),0); + + PC_PREVIOUS [i] = PC_CURRENT [i]; + PC_CURRENT [i] = out_PREDICT_PC_NEXT [i]->read(); + PC_CURRENT_IS_DS_TAKE [i] = out_PREDICT_PC_NEXT_IS_DS_TAKE [i]->read(); + } + + // Test another output + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); + } + + for (uint32_t i=0; i<_param->_nb_decod_unit;++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + { + TEST(Tcontrol_t,out_DECOD_ACK [i][j]->read(),0); // No decod instruction + } + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),1); // Accept new branch_complete + } + } SC_START(1); @@ -208,15 +323,15 @@ DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context); - DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + DELETE2_SC_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1]); + DELETE2_SC_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); @@ -239,6 +354,7 @@ DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); - DELETE1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context); - DELETE1_SC_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Update_Prediction_Table_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_min.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_min.cfg (revision 88) @@ -1,5 +1,6 @@ Update_Prediction_Table 1 1 +1 # nb_context -1 4 *4 # size_queue [0] [nb_context] +1 1 *4 # size_upt_queue [0] [nb_context] +1 1 *4 # size_ufpt_queue [0] [nb_context] 32 32 *2 # size_address 1 1 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg (revision 88) @@ -1,5 +1,6 @@ Update_Prediction_Table 1 1 +1 # nb_context -1 4 *4 # size_queue [0] [nb_context] +4 8 *2 # size_upt_queue [0] [nb_context] +1 4 *2 # size_ufpt_queue [0] [nb_context] 32 32 *2 # size_address 4 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_multi_context.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_multi_context.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_multi_context.cfg (revision 88) @@ -1,8 +1,12 @@ Update_Prediction_Table 4 4 +1 # nb_context -4 4 *4 # size_queue [0] [nb_context] -1 1 *4 # size_queue [1] [nb_context] -8 8 *4 # size_queue [2] [nb_context] -2 2 *4 # size_queue [3] [nb_context] +4 4 *4 # size_upt_queue [0] [nb_context] +2 2 *4 # size_upt_queue [1] [nb_context] +8 8 *4 # size_upt_queue [2] [nb_context] +1 1 *4 # size_upt_queue [3] [nb_context] +4 4 *4 # size_ufpt_queue [0] [nb_context] +1 1 *4 # size_ufpt_queue [1] [nb_context] +2 2 *4 # size_ufpt_queue [2] [nb_context] +1 1 *4 # size_ufpt_queue [3] [nb_context] 32 32 *2 # size_address 4 4 *4 # nb_inst_predict Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/main.cpp (revision 88) @@ -15,5 +15,6 @@ err (_("list_params is :\n")); err (_(" * nb_context (uint32_t)\n")); - err (_(" * size_queue [nb_context] (uint32_t)\n")); + err (_(" * size_upt_queue [nb_context] (uint32_t)\n")); + err (_(" * size_ufpt_queue [nb_context] (uint32_t)\n")); err (_(" * size_address (uint32_t)\n")); err (_(" * nb_inst_predict (uint32_t)\n")); @@ -42,10 +43,13 @@ uint32_t _nb_context = fromString(argv[x++]); - if (argc != static_cast(2+NB_PARAMS+2*_nb_context)) + if (argc != static_cast(2+NB_PARAMS+3*_nb_context)) usage (argc, argv); - uint32_t * _size_queue = new uint32_t [_nb_context]; + uint32_t * _size_upt_queue = new uint32_t [_nb_context]; for (uint32_t i=0; i<_nb_context; i++) - _size_queue [i] = fromString(argv[x++]); + _size_upt_queue [i] = fromString(argv[x++]); + uint32_t * _size_ufpt_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; i++) + _size_ufpt_queue [i] = fromString(argv[x++]); uint32_t _size_address = fromString(argv[x++]); uint32_t _nb_inst_predict = fromString(argv[x++]); @@ -63,5 +67,6 @@ morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters (_nb_context , - _size_queue , + _size_upt_queue , + _size_ufpt_queue , _size_address , _nb_inst_predict , @@ -70,5 +75,7 @@ _nb_inst_update , _size_history , - _size_ras_index ); + _size_ras_index , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); @@ -89,5 +96,6 @@ delete [] _size_ras_index; - delete [] _size_queue; + delete [] _size_ufpt_queue; + delete [] _size_upt_queue; return (_return); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 88) @@ -1,4 +1,4 @@ /* - * $Id$ + * $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $ * * [ Description ] @@ -13,4 +13,26 @@ #include "Common/include/Test.h" #include "Behavioural/include/Allocation.h" + +typedef struct +{ + uint32_t ufpt_ptr ; + uint32_t upt_ptr ; + + Tcontext_t context ; + Taddress_t address_src ; + Taddress_t address_dest; + Taddress_t address_good; + Tbranch_condition_t condition ; + Tcontrol_t take ; + Tcontrol_t take_good ; + Tcontrol_t flag ; + Tcontrol_t is_accurate ; + Thistory_t history ; + Taddress_t ras_address ; + Tptr_t ras_index ; + Tcontrol_t miss_ifetch ; + Tcontrol_t miss_decod ; + Tcontrol_t miss_commit ; +} request_t; void test (string name, @@ -61,5 +83,5 @@ ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict); ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict); -//ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict); + ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict); ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); @@ -75,4 +97,5 @@ ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod); //ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); + ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -111,6 +134,7 @@ ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL(out_DEPTH_NB_BRANCH ,"out_DEPTH_NB_BRANCH ",Tdepth_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL(out_DEPTH_TAIL ,"out_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); /******************************************************** @@ -136,6 +160,6 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict); -//if (_param->_have_port_depth) -//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod); @@ -150,13 +174,14 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod); //if (_param->_have_port_depth) //INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); @@ -171,5 +196,5 @@ // if (_param->_have_port_context_id) // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -// if (_param->_have_port_max_depth) +// if (_param->_have_port_depth) // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); // INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ADDRESS ,_param->_nb_context); @@ -196,12 +221,10 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); - for (uint32_t i=0; i<_param->_nb_context; i++) + if (_param->_have_port_depth) { - if (_param->_have_port_depth[i]) - { - INSTANCE_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_TAIL [i]); - } - INSTANCE_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_NB_BRANCH [i]); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context); } + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -225,4 +248,9 @@ const int32_t percent_transaction_update = 75; + + + std::list ufpt; + std::list upt; + SC_START(0); LABEL("Initialisation"); @@ -233,145 +261,211 @@ in_NRESET->write(1); - for (uint32_t i=0; i<_param->_nb_context; i++) + Tdepth_t ufpt_bottom [_param->_nb_context]; + Tdepth_t ufpt_top [_param->_nb_context]; + + Tdepth_t upt_bottom [_param->_nb_context]; + Tdepth_t upt_top [_param->_nb_context]; + + for (uint32_t i=0; i<_param->_nb_context; ++i) { - PORT_WRITE(in_BRANCH_EVENT_ACK [i],1); + ufpt_bottom [i] = 0; + ufpt_top [i] = 0; + upt_bottom [i] = 0; + upt_top [i] = 0; } - LABEL("Loop of Test"); + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]); + TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]); + TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]); + } for (uint32_t iteration=0; iteration_nb_inst_predict; ++i) + in_PREDICT_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_inst_decod; ++i) + in_DECOD_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + in_BRANCH_COMPLETE_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_context; ++i) + in_BRANCH_EVENT_ACK [i]->write(0); + for (uint32_t i=0; i<_param->_nb_inst_update; ++i) + in_UPDATE_ACK [i]->write(0); + + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + // COMMON CASE + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + if (1) { uint32_t context = rand() % _param->_nb_context; - -// LABEL("KANE : %d",context); - - LABEL("PREDICT - fill the queue"); - + { + LABEL("PREDICT - fill the queue"); uint32_t port = rand() % _param->_nb_inst_predict; + + LABEL(" * context : %d",context); + LABEL(" * port : %d",port); - for (uint32_t i=0; i<_param->_size_queue[context]; i++) + for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) { - - bool find = false; + request_t request; + request.context = context; + request.address_src = 0xdeadbeef+i; + request.address_dest = 0x21071981+i; + request.address_good = request.address_dest; + request.condition = BRANCH_CONDITION_FLAG_SET; + request.take = 1; + request.take_good = 1; + request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.is_accurate = true; + request.miss_ifetch = false; + request.miss_decod = false; + request.miss_commit = false; + request.history = i; + request.ras_address = 0xdeaddead+i; + request.ras_index = (0x12345678+i)%_param->_size_ras_index[context]; + request.ufpt_ptr = ufpt_top [context]; +// request.upt_ptr; + + bool have_transaction = false; do { in_PREDICT_VAL [port]->write((rand()%100)write(context); - in_PREDICT_BTB_ADDRESS_SRC [port]->write(0xdeadbeef+i); - in_PREDICT_BTB_ADDRESS_DEST [port]->write(0x21071981+i); - in_PREDICT_BTB_CONDITION [port]->write(BRANCH_CONDITION_FLAG_SET); - in_PREDICT_BTB_LAST_TAKE [port]->write(1); - in_PREDICT_BTB_IS_ACCURATE [port]->write((rand()%100)write(i); - in_PREDICT_RAS_ADDRESS [port]->write(0xdeaddead+i); - in_PREDICT_RAS_INDEX [port]->write((0x12345678+i)%_param->_size_ras_index[context]); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), i); + in_PREDICT_CONTEXT_ID [port]->write(request.context ); + in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src ); + in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest); + in_PREDICT_BTB_CONDITION [port]->write(request.condition ); + in_PREDICT_BTB_LAST_TAKE [port]->write(request.take ); + in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate ); + in_PREDICT_DIR_HISTORY [port]->write(request.history ); + in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address ); + in_PREDICT_RAS_INDEX [port]->write(request.ras_index ); + + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); - SC_START(0); - - LABEL("PREDICT [%d] %d - %d (accurate : %d).",port,in_PREDICT_VAL [port]->read(),out_PREDICT_ACK [port]->read(), in_PREDICT_BTB_IS_ACCURATE [port]->read()); + SC_START(0); // fct melay + + LABEL("PREDICT [%d] %d - %d (accurate : %d).", + port, + in_PREDICT_VAL [port]->read(), + out_PREDICT_ACK [port]->read(), + in_PREDICT_BTB_IS_ACCURATE [port]->read()); if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) { LABEL("PREDICT [%d] - Transaction accepted",port); - find = true; + have_transaction = true; + + if (_param->_have_port_depth) + TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]); + + ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context]; } - SC_START(1); - - } while (not find); - in_PREDICT_VAL [port]->write(0); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), i+1); - + SC_START(1); // transition + + } while (not have_transaction); + + ufpt.push_back(request); + + in_PREDICT_VAL [port]->write(0); + + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); } } - LABEL("DECOD - hit ifetch"); - - { + { + LABEL("DECOD"); uint32_t port = rand() % _param->_nb_inst_decod; - - for (uint32_t i=0; i<_param->_size_queue[context]; i++) + + LABEL(" * context : %d",context); + LABEL(" * port : %d",port); + + for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) { - - bool find = false; + request_t request = ufpt.front(); + + bool have_transaction = false; do { in_DECOD_VAL [port]->write((rand()%100)write(context); - in_DECOD_BTB_ADDRESS_SRC [port]->write(0xdeadbeef+i); - in_DECOD_BTB_ADDRESS_DEST [port]->write(0x21071981+i); - in_DECOD_BTB_CONDITION [port]->write(BRANCH_CONDITION_FLAG_SET); - in_DECOD_BTB_LAST_TAKE [port]->write(1); - in_DECOD_RAS_ADDRESS [port]->write(0xdeaddead+i); - in_DECOD_RAS_INDEX [port]->write((0x12345678+i)%_param->_size_ras_index[context]); - in_DECOD_MISS_IFETCH [port]->write(false); - in_DECOD_MISS_DECOD [port]->write(false); - in_DECOD_UPDATE_PREDICTION_ID [port]->write(i); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); - - SC_START(0); - - LABEL("DECOD [%d] %d - %d.",port,in_DECOD_VAL [port]->read(),out_DECOD_ACK [port]->read()); + in_DECOD_CONTEXT_ID [port]->write(request.context ); + in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src ); + in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest); + in_DECOD_BTB_CONDITION [port]->write(request.condition ); + in_DECOD_BTB_LAST_TAKE [port]->write(request.take ); + in_DECOD_RAS_ADDRESS [port]->write(request.ras_address ); + in_DECOD_RAS_INDEX [port]->write(request.ras_index ); + in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr ); + in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch ); + in_DECOD_MISS_DECOD [port]->write(request.miss_decod ); + in_DECOD_IS_ACCURATE [port]->write(request.is_accurate ); + + SC_START(0); // fct melay + + LABEL("DECOD [%d] %d - %d", + port, + in_PREDICT_VAL [port]->read(), + out_PREDICT_ACK [port]->read()); if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) { - LABEL("DECOD [%d] - Transaction accepted",port); - find = true; + LABEL("DECOD [%d] - Transaction accepted",port); + have_transaction = true; + + request.upt_ptr = upt_top [context]; + upt.push_back(request); + ufpt.pop_front(); + + upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context]; } - - SC_START(1); - - } while (not find); + + SC_START(1); // transition + + } while (not have_transaction); + in_DECOD_VAL [port]->write(0); - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); - } - } + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } + } + + { + LABEL("BRANCH_COMPLETE - hit ifetch"); - LABEL("BRANCH_COMPLETE - hit ifetch"); + uint32_t port = rand() % _param->_nb_inst_branch_complete; - { - uint32_t port = rand() % _param->_nb_inst_branch_complete; - - for (uint32_t i=0; i<_param->_size_queue[context]; i++) + LABEL(" * port : %d",port); + + std::list::iterator it_upt = upt.begin(); + +// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) + for (uint32_t i=0; iwrite((rand()%100)write(context); - in_BRANCH_COMPLETE_DEPTH [port]->write(i); - in_BRANCH_COMPLETE_ADDRESS [port]->write(0xcacacaca+i); - in_BRANCH_COMPLETE_FLAG [port]->write(1); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); + in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)write(it_upt->context ); + in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); + in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); + in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); SC_START(0); @@ -382,296 +476,115 @@ { LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); - find = true; + have_transaction = true; - TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),0); - TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),1); - TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),0xdeadbeef+i); - TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),0x21071981+i); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good ); + TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); + TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good); + + it_upt ++; } SC_START(1); - - } while (not find); - in_BRANCH_COMPLETE_VAL [port]->write(0); + } while (not have_transaction); + + in_BRANCH_COMPLETE_VAL [port]->write(0); - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); } } + + { + LABEL("UPDATE - hit ifetch"); - LABEL("UPDATE - hit ifetch"); + uint32_t port = 0; - { - uint32_t port = 0; //rand() % _param->_nb_inst_update; - - for (uint32_t i=0; i<_param->_size_queue[context]; i++) + LABEL(" * port : %d",port); + std::list::iterator it_upt = upt.begin(); + +// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++) + for (uint32_t i=0; iread(),upt.size()); + + bool have_transaction = false; + do { + LABEL("Address_src (0) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); + in_UPDATE_ACK [port]->write((rand()%100)_have_port_depth) +// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); +// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + + LABEL("Address_src (1) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); SC_START(0); + LABEL("Address_src (2) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); + + LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read()); if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read()) { LABEL("UPDATE [%d] - Transaction accepted",port); - - find = true; - - TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(), context); - TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(), 0); - TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(), 1); - TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(), 1); - TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(), 0xdeadbeef+i); - TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(), 0x21071981+i); - TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(), BRANCH_CONDITION_FLAG_SET); - TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(), 1); - if (_param->_have_port_history) - TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(), i); - TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(), 0); - TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(), 0); - TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(), 0xdeaddead+i); - TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(), (0x12345678+i)%_param->_size_ras_index[context]); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(), 1); + have_transaction = true; + + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [i]->read(),it_upt->context); + TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [i]->read(),it_upt->miss_commit); + TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [i]->read(),it_upt->flag); + TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [i]->read(),update_btb(it_upt->condition)); + if (update_btb(it_upt->condition)) + { + TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [i]->read(),it_upt->address_src); + TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [i]->read(),it_upt->address_dest); + TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [i]->read(),it_upt->condition); + } + TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [i]->read(),update_dir(it_upt->condition)); + if (update_dir(it_upt->condition)) + if (_param->_have_port_history) + TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [i]->read(),it_upt->history); + TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [i]->read(),update_ras(it_upt->condition)); + if (update_ras(it_upt->condition)) + { + TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [i]->read(),push_ras (it_upt->condition)); + TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [i]->read(),it_upt->ras_address); + TEST(Tptr_t ,out_UPDATE_RAS_INDEX [i]->read(),it_upt->ras_index); + TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [i]->read(),not it_upt->miss_ifetch); + } + ++ it_upt; } - + SC_START(1); - - } while (not find); - in_UPDATE_ACK [port]->write(0); + LABEL("Address_src (3) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); + + } while (not have_transaction); + + LABEL("Address_src (4) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); + in_UPDATE_ACK [port]->write(0); + LABEL("Address_src (5) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read()); +// if (_param->_have_port_depth) +// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); +// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); } - - LABEL("Wait a moment"); - SC_START(2*_param->_size_queue[context]); - - // wait the garbage collector - while ((not (_param->_have_port_depth[context]) or (out_DEPTH_TAIL [context]->read() != 0)) and - (out_DEPTH_NB_BRANCH[context]->read() != 0)) - { - LABEL("DEPTH [%d] nb_branch : %d - tail : %d",context,out_DEPTH_NB_BRANCH[context]->read(), out_DEPTH_TAIL [context]->read()); - SC_START(1); - } + upt.clear(); } + + // Wait Garbage Collector + { + upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context]; +// upt_top [context] = (upt_top [context]); + + while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or + (upt_top [context] != out_DEPTH_MAX [context]->read())) + SC_START(1); + + } } - { - uint32_t context = rand() % _param->_nb_context; - -// LABEL("KANE : %d",context); - - LABEL("PREDICT - fill the queue"); - - { - uint32_t port = rand() % _param->_nb_inst_predict; - - for (uint32_t i=0; i<_param->_size_queue[context]; i++) - { - - bool find = false; - do - { - in_PREDICT_VAL [port]->write((rand()%100)write(context); - in_PREDICT_BTB_ADDRESS_SRC [port]->write(0xdeadbeef+i); - in_PREDICT_BTB_ADDRESS_DEST [port]->write(0x21071981+i); - in_PREDICT_BTB_CONDITION [port]->write(BRANCH_CONDITION_FLAG_SET); - in_PREDICT_BTB_LAST_TAKE [port]->write(1); - in_PREDICT_BTB_IS_ACCURATE [port]->write((rand()%100)write(i); - in_PREDICT_RAS_ADDRESS [port]->write(0xdeaddead+i); - in_PREDICT_RAS_INDEX [port]->write((0x12345678+i)%_param->_size_ras_index[context]); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), i); - - SC_START(0); - - LABEL("PREDICT [%d] %d - %d (accurate : %d).",port,in_PREDICT_VAL [port]->read(),out_PREDICT_ACK [port]->read(), in_PREDICT_BTB_IS_ACCURATE [port]->read()); - - if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read()) - { - LABEL("PREDICT [%d] - Transaction accepted",port); - find = true; - } - - SC_START(1); - - } while (not find); - in_PREDICT_VAL [port]->write(0); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), i+1); - } - } - - LABEL("DECOD - hit ifetch"); - - { - uint32_t port = rand() % _param->_nb_inst_decod; - - for (uint32_t i=0; i<_param->_size_queue[context]; i++) - { - - bool find = false; - do - { - in_DECOD_VAL [port]->write((rand()%100)write(context); - in_DECOD_BTB_ADDRESS_SRC [port]->write(0xdeadbeef+i); - in_DECOD_BTB_ADDRESS_DEST [port]->write(0x21071981+i); - in_DECOD_BTB_CONDITION [port]->write(BRANCH_CONDITION_FLAG_SET); - in_DECOD_BTB_LAST_TAKE [port]->write(1); - in_DECOD_RAS_ADDRESS [port]->write(0xdeaddead+i); - in_DECOD_RAS_INDEX [port]->write((0x12345678+i)%_param->_size_ras_index[context]); - in_DECOD_MISS_IFETCH [port]->write(false); - in_DECOD_MISS_DECOD [port]->write(false); - in_DECOD_UPDATE_PREDICTION_ID [port]->write(i); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); - - SC_START(0); - - LABEL("DECOD [%d] %d - %d.",port,in_DECOD_VAL [port]->read(),out_DECOD_ACK [port]->read()); - - if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) - { - LABEL("DECOD [%d] - Transaction accepted",port); - find = true; - } - - SC_START(1); - - } while (not find); - in_DECOD_VAL [port]->write(0); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); - } - } - - LABEL("BRANCH_COMPLETE - hit ifetch"); - - { - uint32_t port = rand() % _param->_nb_inst_branch_complete; - - { - uint32_t i=0; - bool find = false; - do - { - in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)write(context); - in_BRANCH_COMPLETE_DEPTH [port]->write(i); - in_BRANCH_COMPLETE_ADDRESS [port]->write(0xcacacaca+i); - in_BRANCH_COMPLETE_FLAG [port]->write(0); - - if (_param->_have_port_depth[context]) - { - TEST(Tdepth_t,out_DEPTH_TAIL [context]->read(), 0); - } - TEST(Tdepth_t,out_DEPTH_NB_BRANCH[context]->read(), _param->_size_queue[context]); - - SC_START(0); - - LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); - - if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) - { - LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); - find = true; - - TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),1); - TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),0); - TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),0xdeadbeef+i); - TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),0x21071981+i); - } - - SC_START(1); - - } while (not find); - in_BRANCH_COMPLETE_VAL [port]->write(0); - } - } - - LABEL("UPDATE - miss ifetch"); - - { - uint32_t port = 0; //rand() % _param->_nb_inst_update; - -// for (uint32_t i=0; i<_param->_size_queue[context]; i++) - { - uint32_t i=0; - - bool find = false; - do - { - in_UPDATE_ACK [port]->write((rand()%100)read() and in_UPDATE_ACK [port]->read()) - { - LABEL("UPDATE [%d] - Transaction accepted",port); - - find = true; - - TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(), context); - TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(), 1); - TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(), 0); - TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(), 1); - TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(), 0xdeadbeef+i); - TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(), 0x21071981+i); - TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(), BRANCH_CONDITION_FLAG_SET); - TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(), 1); - if (_param->_have_port_history) - TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(), i); - TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(), 0); - TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(), 0); - TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(), 0xdeaddead+i); - TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(), (0x12345678+i)%_param->_size_ras_index[context]); - TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(), 1); - } - - SC_START(1); - - } while (not find); - in_UPDATE_ACK [port]->write(0); - } - - LABEL("Wait a moment"); - SC_START(_param->_size_queue[context]); - - // wait the garbage collector - while (((not (_param->_have_port_depth[context])) or (out_DEPTH_TAIL [context]->read() != 0)) and - (out_DEPTH_NB_BRANCH[context]->read() != 0)) - { - LABEL("DEPTH [%d] nb_branch : %d - tail : %d",context,out_DEPTH_NB_BRANCH[context]->read(), out_DEPTH_TAIL [context]->read()); - SC_START(1); - } - } - } - - LABEL ("Yo1"); - SC_START(1); - LABEL ("Yo2"); - - } + }// ITERATION /******************************************************** @@ -699,5 +612,5 @@ delete [] in_PREDICT_RAS_ADDRESS ; delete [] in_PREDICT_RAS_INDEX ; -//delete [] out_PREDICT_UPDATE_PREDICTION_ID; + delete [] out_PREDICT_UPDATE_PREDICTION_ID; // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -715,4 +628,5 @@ delete [] in_DECOD_UPDATE_PREDICTION_ID ; //delete [] out_DECOD_DEPTH ; + delete [] in_DECOD_IS_ACCURATE ; // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -756,6 +670,7 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_DEPTH_NB_BRANCH; - delete [] out_DEPTH_TAIL; + delete [] out_DEPTH_CURRENT; + delete [] out_DEPTH_MIN; + delete [] out_DEPTH_MAX; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h (revision 88) @@ -24,27 +24,30 @@ { //-----[ fields ]------------------------------------------------------------ - public : uint32_t _nb_context ; - public : uint32_t * _size_queue ; // [nb_context] - public : uint32_t _size_address ; - public : uint32_t _nb_inst_predict ; - public : uint32_t _nb_inst_decod ; - public : uint32_t _nb_inst_branch_complete; - public : uint32_t _nb_inst_update ; - public : uint32_t _size_history ; - public : uint32_t * _size_ras_index ; // [nb_context] + public : uint32_t _nb_context ; + public : uint32_t * _size_upt_queue ; // [nb_context] + public : uint32_t * _size_ufpt_queue ; // [nb_context] +//public : uint32_t _size_address ; + public : uint32_t _nb_inst_predict ; + public : uint32_t _nb_inst_decod ; + public : uint32_t _nb_inst_branch_complete ; + public : uint32_t _nb_inst_update ; + public : uint32_t _size_history ; + public : uint32_t * _size_ras_index ; // [nb_context] + public : const bool _not_accurate_block_predict; - public : uint32_t _size_context_id ; - public : uint32_t * _size_depth ; // [nb_context] - public : uint32_t _max_size_depth ; - public : uint32_t _max_size_ras_index ; - - public : bool _have_port_context_id ; - public : bool * _have_port_depth ; // [nb_context] - public : bool _have_port_max_depth ; - public : bool _have_port_history ; +//public : uint32_t _size_context_id ; +//public : uint32_t * _size_depth ; // [nb_context] +//public : uint32_t _max_size_depth ; + public : uint32_t _max_size_ras_index ; + +//public : bool _have_port_context_id ; +//public : bool * _have_port_depth ; // [nb_context] +//public : bool _have_port_max_depth ; + public : bool _have_port_history ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_context , - uint32_t * size_queue , + uint32_t * size_upt_queue , + uint32_t * size_ufpt_queue , uint32_t size_address , uint32_t nb_inst_predict , @@ -53,7 +56,10 @@ uint32_t nb_inst_update , uint32_t size_history , - uint32_t * size_ras_index ); + uint32_t * size_ras_index , + bool is_toplevel=false); //public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 88) @@ -21,26 +21,85 @@ typedef enum { - UPDATE_PREDICTION_STATE_EMPTY , // Slot is empty - UPDATE_PREDICTION_STATE_WAIT_DECOD , // Fetch have access at the predictor - UPDATE_PREDICTION_STATE_WAITEND , // Have make a prediction, wait branch_complete - UPDATE_PREDICTION_STATE_EVENT , // have a event - must signal at the context_unit - UPDATE_PREDICTION_STATE_OK , // branch is complete and can update predictor - UPDATE_PREDICTION_STATE_KO , // have a event - must update predictor unit - UPDATE_PREDICTION_STATE_END // branch is updated - } state_t; + EVENT_STATE_OK , // Can predict + EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt + EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt + EVENT_STATE_FLUSH_UPT_RAS , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS + EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush + EVENT_STATE_UPDATE_CONTEXT // prediction unit is update, send signal to context manager + } event_state_t; - class entry_t + typedef enum + { + UPDATE_FETCH_PREDICTION_STATE_EMPTY , // Slot is empty + UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD , // Have make a prediction, wait decod + UPDATE_FETCH_PREDICTION_STATE_EVENT , // previous branch is a miss prediction + UPDATE_FETCH_PREDICTION_STATE_END // branch is updated + } ufpt_state_t; + + typedef enum + { + UPDATE_PREDICTION_STATE_EMPTY , // Slot is empty + UPDATE_PREDICTION_STATE_WAIT_END , // Have make a prediction, wait branch_complete + UPDATE_PREDICTION_STATE_OK , // this branch is a hit prediction + UPDATE_PREDICTION_STATE_KO , // this branch is a miss prediction + UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction + UPDATE_PREDICTION_STATE_END // branch is updated + } upt_state_t; + + class ufpt_entry_t { - public : state_t _state; - public : Tcontrol_t _ifetch_prediction; - public : Tbranch_condition_t _condition; - public : Taddress_t _address_src; - public : Taddress_t _address_dest; - public : Tcontrol_t _last_take; - public : Tcontrol_t _good_take; - public : Thistory_t _history; - public : Taddress_t _address_ras; - public : Tptr_t _index_ras; + public : ufpt_state_t _state ; + public : Tbranch_condition_t _condition ; + public : Taddress_t _address_src ; + public : Taddress_t _address_dest ; + public : Tcontrol_t _last_take ; +//public : Tcontrol_t _good_take ; + public : Tcontrol_t _is_accurate ; + public : Thistory_t _history ; + public : Taddress_t _address_ras ; + public : Tptr_t _index_ras ; +//public : Tcontrol_t _ifetch_prediction; }; + + class upt_entry_t + { + public : upt_state_t _state ; + public : Tbranch_condition_t _condition ; + public : Taddress_t _address_src ; + public : Taddress_t _address_dest ; + public : Tcontrol_t _last_take ; + public : Tcontrol_t _good_take ; // not in ufpt + public : Tcontrol_t _is_accurate ; + public : Thistory_t _history ; + public : Taddress_t _address_ras ; + public : Tptr_t _index_ras ; + public : Tcontrol_t _ifetch_prediction; // not in ufpt + }; + + +// BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK +// BRANCH_CONDITION_NONE_WITH_WRITE_STACK +// BRANCH_CONDITION_FLAG_UNSET +// BRANCH_CONDITION_FLAG_SET +// BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK +// BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK +// BRANCH_CONDITION_READ_STACK + + +#define update_btb(cond) true + +#define update_dir(cond) ((cond == BRANCH_CONDITION_FLAG_UNSET) or \ + (cond == BRANCH_CONDITION_FLAG_SET)) + +#define update_ras(cond) ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK ) or \ + (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or \ + (cond == BRANCH_CONDITION_READ_STACK )) + +#define push_ras(cond) ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK ) or \ + (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK)) + +#define pop_ras(cond) ((cond == BRANCH_CONDITION_READ_STACK )) + +#define need_update(cond) update_ras(cond) }; // end namespace update_prediction_table @@ -51,15 +110,39 @@ }; // end namespace behavioural + template<> inline std::string toString(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::event_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT_RAS : return "flush_upt_ras" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT : return "flush_upt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; + default : return "" ; break; + } + }; - template<> inline std::string toString(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::state_t& x) + template<> inline std::string toString(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::ufpt_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_FETCH_PREDICTION_STATE_EMPTY : return "empty" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD : return "wait_decod"; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_FETCH_PREDICTION_STATE_EVENT : return "event" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_FETCH_PREDICTION_STATE_END : return "end" ; break; + default : return "" ; break; + } + }; + + template<> inline std::string toString(const morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::upt_state_t& x) { switch (x) { case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EMPTY : return "empty" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_WAIT_DECOD : return "wait_decod"; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_WAITEND : return "waitend" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_WAIT_END : return "wait_end" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_OK : return "ok" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_KO : return "ko" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END : return "end" ; break; default : return "" ; break; @@ -67,5 +150,4 @@ }; - }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 88) @@ -51,4 +51,12 @@ #ifdef STATISTICS public : Stat * _stat; + + private : counter_t ** _stat_nb_branch_hit ; //[nb_context] + private : counter_t ** _stat_nb_branch_miss ; //[nb_context] + private : counter_t ** _stat_nb_branch_unused ; //[nb_context] + private : counter_t ** _stat_queue_nb_cycle_empty; //[nb_context] + private : counter_t ** _stat_queue_nb_cycle_full ; //[nb_context] + private : counter_t ** _stat_queue_nb_elt ; //[nb_context] + #endif @@ -59,37 +67,37 @@ // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_CLOCK * in_CLOCK ; - public : SC_IN (Tcontrol_t) * in_NRESET ; + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_PREDICT_VAL ; //[nb_inst_predict] - public : SC_OUT(Tcontrol_t ) ** out_PREDICT_ACK ; //[nb_inst_predict] - public : SC_IN (Tcontext_t ) ** in_PREDICT_CONTEXT_ID ; //[nb_inst_predict] - public : SC_IN (Taddress_t ) ** in_PREDICT_BTB_ADDRESS_SRC ; //[nb_inst_predict] - public : SC_IN (Taddress_t ) ** in_PREDICT_BTB_ADDRESS_DEST ; //[nb_inst_predict] - public : SC_IN (Tbranch_condition_t) ** in_PREDICT_BTB_CONDITION ; //[nb_inst_predict] - public : SC_IN (Tcontrol_t ) ** in_PREDICT_BTB_LAST_TAKE ; //[nb_inst_predict] - public : SC_IN (Tcontrol_t ) ** in_PREDICT_BTB_IS_ACCURATE ; //[nb_inst_predict] - public : SC_IN (Thistory_t ) ** in_PREDICT_DIR_HISTORY ; //[nb_inst_predict] - public : SC_IN (Taddress_t ) ** in_PREDICT_RAS_ADDRESS ; //[nb_inst_predict] - public : SC_IN (Tptr_t ) ** in_PREDICT_RAS_INDEX ; //[nb_inst_predict] -//public : SC_OUT(Tprediction_ptr_t ) ** out_PREDICT_UPDATE_PREDICTION_ID; //[nb_inst_predict] + public : SC_IN (Tcontrol_t ) ** in_PREDICT_VAL ; //[nb_inst_predict] + public : SC_OUT(Tcontrol_t ) ** out_PREDICT_ACK ; //[nb_inst_predict] + public : SC_IN (Tcontext_t ) ** in_PREDICT_CONTEXT_ID ; //[nb_inst_predict] + public : SC_IN (Taddress_t ) ** in_PREDICT_BTB_ADDRESS_SRC ; //[nb_inst_predict] + public : SC_IN (Taddress_t ) ** in_PREDICT_BTB_ADDRESS_DEST ; //[nb_inst_predict] + public : SC_IN (Tbranch_condition_t) ** in_PREDICT_BTB_CONDITION ; //[nb_inst_predict] + public : SC_IN (Tcontrol_t ) ** in_PREDICT_BTB_LAST_TAKE ; //[nb_inst_predict] + public : SC_IN (Tcontrol_t ) ** in_PREDICT_BTB_IS_ACCURATE ; //[nb_inst_predict] + public : SC_IN (Thistory_t ) ** in_PREDICT_DIR_HISTORY ; //[nb_inst_predict] + public : SC_IN (Taddress_t ) ** in_PREDICT_RAS_ADDRESS ; //[nb_inst_predict] + public : SC_IN (Tptr_t ) ** in_PREDICT_RAS_INDEX ; //[nb_inst_predict] + public : SC_OUT(Tprediction_ptr_t ) ** out_PREDICT_UPDATE_PREDICTION_ID ; //[nb_inst_predict] // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t ) ** in_DECOD_VAL ; //[nb_inst_decod] - public : SC_OUT(Tcontrol_t ) ** out_DECOD_ACK ; //[nb_inst_decod] - public : SC_IN (Tcontext_t ) ** in_DECOD_CONTEXT_ID ; //[nb_inst_decod] - public : SC_IN (Taddress_t ) ** in_DECOD_BTB_ADDRESS_SRC ; //[nb_inst_decod] - public : SC_IN (Taddress_t ) ** in_DECOD_BTB_ADDRESS_DEST ; //[nb_inst_decod] - public : SC_IN (Tbranch_condition_t) ** in_DECOD_BTB_CONDITION ; //[nb_inst_decod] - public : SC_IN (Tcontrol_t ) ** in_DECOD_BTB_LAST_TAKE ; //[nb_inst_decod] -//public : SC_IN (Tcontrol_t ) ** in_DECOD_BTB_IS_ACCURATE ; //[nb_inst_decod] -//public : SC_IN (Thistory_t ) ** in_DECOD_DIR_HISTORY ; //[nb_inst_decod] // if ifetch prediction is miss -> miss btb -> make a static state - public : SC_IN (Taddress_t ) ** in_DECOD_RAS_ADDRESS ; //[nb_inst_decod] - public : SC_IN (Tptr_t ) ** in_DECOD_RAS_INDEX ; //[nb_inst_decod] - public : SC_IN (Tcontrol_t ) ** in_DECOD_MISS_IFETCH ; //[nb_inst_decod] - public : SC_IN (Tcontrol_t ) ** in_DECOD_MISS_DECOD ; //[nb_inst_decod] - public : SC_IN (Tprediction_ptr_t ) ** in_DECOD_UPDATE_PREDICTION_ID ; //[nb_inst_decod] -//public : SC_OUT(Tdepth_t ) ** out_DECOD_DEPTH ; //[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_VAL ; //[nb_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_ACK ; //[nb_inst_decod] + public : SC_IN (Tcontext_t ) ** in_DECOD_CONTEXT_ID ; //[nb_inst_decod] + public : SC_IN (Taddress_t ) ** in_DECOD_BTB_ADDRESS_SRC ; //[nb_inst_decod] + public : SC_IN (Taddress_t ) ** in_DECOD_BTB_ADDRESS_DEST ; //[nb_inst_decod] + public : SC_IN (Tbranch_condition_t) ** in_DECOD_BTB_CONDITION ; //[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_BTB_LAST_TAKE ; //[nb_inst_decod] +//public : SC_IN (Thistory_t ) ** in_DECOD_DIR_HISTORY ; //[nb_inst_decod] // if ifetch prediction is miss -> miss btb -> make a static state + public : SC_IN (Taddress_t ) ** in_DECOD_RAS_ADDRESS ; //[nb_inst_decod] + public : SC_IN (Tptr_t ) ** in_DECOD_RAS_INDEX ; //[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_MISS_IFETCH ; //[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_MISS_DECOD ; //[nb_inst_decod] + public : SC_IN (Tprediction_ptr_t ) ** in_DECOD_UPDATE_PREDICTION_ID ; //[nb_inst_decod] +//public : SC_OUT(Tdepth_t ) ** out_DECOD_DEPTH ; //[nb_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_IS_ACCURATE ; //[nb_inst_decod] // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -106,48 +114,69 @@ // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_VAL ; //[nb_context] - public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] -//public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] -//public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] -//public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION; //[nb_context] is always miss prediction - public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] - public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_DEST ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_VAL ; //[nb_context] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] +//public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] +//public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] +//public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] is always miss prediction + public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] + public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_DEST ; //[nb_context] // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_VAL ; //[nb_inst_update] - public : SC_IN (Tcontrol_t ) ** in_UPDATE_ACK ; //[nb_inst_update] - public : SC_OUT(Tcontext_t ) ** out_UPDATE_CONTEXT_ID ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_MISS_PREDICTION ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIRECTION_GOOD ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_BTB_VAL ; //[nb_inst_update] - public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_SRC ; //[nb_inst_update] - public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_DEST ; //[nb_inst_update] - public : SC_OUT(Tbranch_condition_t) ** out_UPDATE_BTB_CONDITION ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIR_VAL ; //[nb_inst_update] - public : SC_OUT(Thistory_t ) ** out_UPDATE_DIR_HISTORY ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_VAL ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PUSH ; //[nb_inst_update] - public : SC_OUT(Taddress_t ) ** out_UPDATE_RAS_ADDRESS ; //[nb_inst_update] - public : SC_OUT(Tptr_t ) ** out_UPDATE_RAS_INDEX ; //[nb_inst_update] - public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PREDICTION_IFETCH; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_VAL ; //[nb_inst_update] + public : SC_IN (Tcontrol_t ) ** in_UPDATE_ACK ; //[nb_inst_update] + public : SC_OUT(Tcontext_t ) ** out_UPDATE_CONTEXT_ID ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_MISS_PREDICTION ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIRECTION_GOOD ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_BTB_VAL ; //[nb_inst_update] + public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_SRC ; //[nb_inst_update] + public : SC_OUT(Taddress_t ) ** out_UPDATE_BTB_ADDRESS_DEST ; //[nb_inst_update] + public : SC_OUT(Tbranch_condition_t) ** out_UPDATE_BTB_CONDITION ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_DIR_VAL ; //[nb_inst_update] + public : SC_OUT(Thistory_t ) ** out_UPDATE_DIR_HISTORY ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_VAL ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PUSH ; //[nb_inst_update] + public : SC_OUT(Taddress_t ) ** out_UPDATE_RAS_ADDRESS ; //[nb_inst_update] + public : SC_OUT(Tptr_t ) ** out_UPDATE_RAS_INDEX ; //[nb_inst_update] + public : SC_OUT(Tcontrol_t ) ** out_UPDATE_RAS_PREDICTION_IFETCH ; //[nb_inst_update] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tdepth_t ) ** out_DEPTH_NB_BRANCH; //[nb_context] - public : SC_OUT(Tdepth_t ) ** out_DEPTH_TAIL; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_CURRENT ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ; //[nb_context] + // If DEPTH_CURRENT : + // equal at DEPTH_MIN -> not speculative + // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : uint32_t * reg_TOP ; //[nb_context] - private : uint32_t * reg_BOTTOM ; //[nb_context] - private : uint32_t * reg_NB_ELT ; //[nb_context] - private : uint32_t * reg_NB_ELT_UPDATE ; //[nb_context] - private : uint32_t * reg_NB_ELT_NEED_UPDATE ; //[nb_context] - private : entry_t ** reg_UPDATE_PREDICTION_TABLE; //[nb_context][size_queue] - private : uint32_t reg_UPDATE_PRIORITY ; + private : uint32_t reg_UPDATE_PRIORITY ; + + private : ufpt_entry_t ** reg_UPDATE_FETCH_PREDICTION_TABLE ; //[nb_context][size_ufpt_queue] + private : uint32_t * reg_UFPT_BOTTOM ; //[nb_context] + private : uint32_t * reg_UFPT_TOP ; //[nb_context] + private : uint32_t * reg_UFPT_UPDATE ; //[nb_context] + private : uint32_t * reg_UFPT_NB_NEED_UPDATE ; //[nb_context] + + private : upt_entry_t ** reg_UPDATE_PREDICTION_TABLE ; //[nb_context][size_upt_queue] + private : uint32_t * reg_UPT_BOTTOM ; //[nb_context] + private : uint32_t * reg_UPT_TOP ; //[nb_context] + private : uint32_t * reg_UPT_UPDATE ; //[nb_context] + private : uint32_t * reg_UPT_NB_NEED_UPDATE ; //[nb_context] + + private : bool * reg_IS_ACCURATE ; //[nb_context] + + private : event_state_t * reg_EVENT_STATE ; //[nb_context] + private : Tcontrol_t * reg_EVENT_RAS_CORRUPTED ; //[nb_context] // RAS must be flush + private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch + private : Tcontrol_t * reg_EVENT_ADDRESS_SRC_VAL ; //[nb_context] // if miss ifetch, decod issue branch, dest must be reload + private : Taddress_t * reg_EVENT_ADDRESS_DEST ; //[nb_context] // Address dest // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ private : Tcontrol_t * internal_PREDICT_ACK ; //[nb_inst_predict] + private : Tdepth_t * internal_PREDICT_UPDATE_PREDICTION_ID ; //[nb_inst_predict] private : Tcontrol_t * internal_DECOD_ACK ; //[nb_inst_decod] + private : uint32_t * internal_DECOD_UPT_PTR_WRITE ; //[nb_inst_decod] private : Tcontrol_t * internal_BRANCH_COMPLETE_ACK ; //[nb_inst_branch_complete] private : Tcontrol_t * internal_BRANCH_COMPLETE_MISS_PREDICTION; //[nb_inst_branch_complete] @@ -157,6 +186,10 @@ private : Tdepth_t * internal_BRANCH_EVENT_DEPTH ; //[nb_context] private : Tcontrol_t * internal_UPDATE_VAL ; //[nb_inst_update] + private : Tcontrol_t * internal_UPDATE_VAL_WITHOUT_ACK ; //[nb_inst_update] private : Tcontext_t * internal_UPDATE_CONTEXT_ID ; //[nb_inst_update] + private : bool * internal_UPDATE_FROM_UFPT ; //[nb_inst_update] private : Tdepth_t * internal_UPDATE_DEPTH ; //[nb_inst_update] + private : bool * internal_UPDATE_RAS ; //[nb_inst_update] + #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters.cpp (revision 88) @@ -21,5 +21,6 @@ #define FUNCTION "Update_Prediction_Table::Parameters" Parameters::Parameters (uint32_t nb_context , - uint32_t * size_queue , + uint32_t * size_upt_queue , + uint32_t * size_ufpt_queue , uint32_t size_address , uint32_t nb_inst_predict , @@ -28,11 +29,14 @@ uint32_t nb_inst_update , uint32_t size_history , - uint32_t * size_ras_index ) + uint32_t * size_ras_index , + bool is_toplevel): + _not_accurate_block_predict (false) { log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); _nb_context = nb_context ; - _size_queue = size_queue ; - _size_address = size_address ; + _size_upt_queue = size_upt_queue ; + _size_ufpt_queue = size_ufpt_queue ; +// _size_address = size_address ; _nb_inst_predict = nb_inst_predict ; _nb_inst_decod = nb_inst_decod ; @@ -42,20 +46,22 @@ _size_ras_index = size_ras_index ; - _size_context_id = log2(nb_context); - _size_depth = new uint32_t[_nb_context]; - _have_port_depth = new bool [_nb_context]; - for (uint32_t i=0; i<_nb_context; i++) - { - _size_depth [i] = log2(_size_queue[i]); - _have_port_depth [i] = (_size_depth [i] > 0); - } - _max_size_depth = max(_size_depth,_nb_context); _max_size_ras_index = max(_size_ras_index,nb_context); - _have_port_context_id = _size_context_id> 0; - _have_port_max_depth = _max_size_depth > 0; _have_port_history = _size_history > 0; + + test(); + + if (is_toplevel) + { + _size_instruction_address = size_address; + _size_context_id = log2(nb_context); + _size_depth = log2(max(_size_upt_queue,_nb_context)); + + _have_port_context_id = _size_context_id> 0; + _have_port_depth = _size_depth > 0; + + copy (); + } - test(); log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); }; @@ -75,6 +81,14 @@ { log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); - delete [] _size_depth ; - delete [] _have_port_depth; +// delete [] _size_depth ; +// delete [] _have_port_depth; + log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Update_Prediction_Table::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_msg_error.cpp (revision 88) @@ -8,4 +8,5 @@ #include "Behavioural/include/Types.h" #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Parameters.h" +#include "Common/include/Max.h" #include @@ -27,7 +28,8 @@ Parameters_test test ("Update_Prediction_Table"); - if (morpheo::behavioural::test(_max_size_depth) == false) - test.error("type \"Tdepth_t\" is too small."); - + for (uint32_t i=0; i<_nb_context; i++) + if (_size_ufpt_queue [i] > _size_upt_queue [i]) + test.error(toString(_("context \"%d\" : size_upt_queue must be >= at size_ufpt_queue\n"),i)); + log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Parameters_print.cpp (revision 88) @@ -28,5 +28,5 @@ xml.balise_open("update_prediction_table"); xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); - xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); +// xml.singleton_begin("size_address "); xml.attribut("value",toString(_size_address )); xml.singleton_end(); xml.singleton_begin("nb_inst_predict "); xml.attribut("value",toString(_nb_inst_predict )); xml.singleton_end(); xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod )); xml.singleton_end(); @@ -40,5 +40,6 @@ xml. attribut("id" ,toString(i)); xml. balise_open_end(); - xml. singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue [i])); xml.singleton_end(); + xml. singleton_begin("size_upt_queue "); xml.attribut("value",toString(_size_upt_queue [i])); xml.singleton_end(); + xml. singleton_begin("size_ufpt_queue "); xml.attribut("value",toString(_size_ufpt_queue [i])); xml.singleton_end(); xml. singleton_begin("size_ras_index "); xml.attribut("value",toString(_size_ras_index [i])); xml.singleton_end(); xml. balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 88) @@ -40,4 +40,10 @@ usage_environment(_usage); +#if DEBUG_Update_Prediction_Table == true + log_printf(INFO,Update_Prediction_Table,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Update_Prediction_Table,FUNCTION,"Allocation"); @@ -49,5 +55,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Update_Prediction_Table,FUNCTION,"Allocation of statistics"); @@ -58,5 +64,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -68,5 +74,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { @@ -91,5 +97,5 @@ SC_METHOD (genMoore); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // use internal register # ifdef SYSTEMCASS_SPECIFIC @@ -106,5 +112,5 @@ if (_param->_have_port_context_id) sensitive << (*(in_PREDICT_CONTEXT_ID [i])); - sensitive << (*(in_PREDICT_BTB_IS_ACCURATE [i])); +// sensitive << (*(in_PREDICT_BTB_IS_ACCURATE [i])); } @@ -128,6 +134,4 @@ if (_param->_have_port_context_id) sensitive << (*(in_DECOD_CONTEXT_ID [i])); - sensitive << (*(in_DECOD_MISS_IFETCH [i])) - << (*(in_DECOD_MISS_DECOD [i])); } @@ -136,6 +140,4 @@ for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { - (*(out_DECOD_ACK [i])) (*(in_DECOD_MISS_IFETCH [i])); - (*(out_DECOD_ACK [i])) (*(in_DECOD_MISS_DECOD [i])); if (_param->_have_port_context_id) (*(out_DECOD_ACK [i])) (*(in_DECOD_CONTEXT_ID [i])); @@ -152,5 +154,5 @@ if (_param->_have_port_context_id) sensitive << (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) sensitive << (*(in_BRANCH_COMPLETE_DEPTH [i])); sensitive << (*(in_BRANCH_COMPLETE_FLAG [i])) @@ -164,5 +166,5 @@ if (_param->_have_port_context_id) (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); @@ -171,5 +173,5 @@ if (_param->_have_port_context_id) (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); @@ -177,10 +179,10 @@ if (_param->_have_port_context_id) (*(out_BRANCH_COMPLETE_ADDRESS_SRC [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_ADDRESS_SRC [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); if (_param->_have_port_context_id) (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_CONTEXT_ID [i])); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); (*(out_BRANCH_COMPLETE_ADDRESS_DEST [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); @@ -200,5 +202,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 88) @@ -63,32 +63,33 @@ ALLOC1_VALACK_OUT(out_PREDICT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_PREDICT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_PREDICT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_PREDICT_BTB_IS_ACCURATE ,"btb_is_accurate" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_PREDICT_DIR_HISTORY ,"dir_history" ,Thistory_t ,_param->_size_history); - ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_PREDICT_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); -// ALLOC1_SIGNAL_OUT(out_PREDICT_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); } // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC1_INTERFACE("decod", IN,SOUTH, "decod", _param->_nb_inst_predict); + ALLOC1_INTERFACE("decod", IN,SOUTH, "decod", _param->_nb_inst_decod); ALLOC1_VALACK_IN ( in_DECOD_VAL ,VAL); ALLOC1_VALACK_OUT(out_DECOD_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_DECOD_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_IN ( in_DECOD_BTB_LAST_TAKE ,"btb_last_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_DECOD_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_DECOD_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); ALLOC1_SIGNAL_IN ( in_DECOD_MISS_IFETCH ,"miss_ifetch" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_DECOD_MISS_DECOD ,"miss_decod" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_DECOD_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_max_size_depth); + ALLOC1_SIGNAL_IN ( in_DECOD_UPDATE_PREDICTION_ID,"update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); // ALLOC1_SIGNAL_OUT(out_DECOD_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_DECOD_IS_ACCURATE ,"is_accurate" ,Tcontrol_t ,1); } @@ -100,11 +101,11 @@ ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_max_size_depth); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); } @@ -116,8 +117,8 @@ ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_max_size_depth); +// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_instruction_address); } @@ -132,6 +133,6 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_DIRECTION_GOOD ,"direction_good" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_VAL ,"btb_val" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_SRC ,"btb_address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_ADDRESS_DEST ,"btb_address_dest" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_UPDATE_BTB_CONDITION ,"btb_condition" ,Tbranch_condition_t,_param->_size_branch_condition); ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_VAL ,"dir_val" ,Tcontrol_t ,1); @@ -139,5 +140,5 @@ ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_VAL ,"ras_val" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PUSH ,"ras_push" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS ,"ras_address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX ,"ras_index" ,Tptr_t ,_param->_max_size_ras_index); ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t ,1); @@ -147,40 +148,57 @@ { ALLOC1_INTERFACE("depth",OUT,SOUTH, "depth", _param->_nb_context); - - ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"TAIL" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]); - ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH,"NB_BRANCH",Tdepth_t,_param->_size_depth[alloc_signal_it1]+1); - } - + ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT,"CURRENT",Tdepth_t,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"MIN" ,Tdepth_t,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"MAX" ,Tdepth_t,_param->_size_depth+1); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - internal_PREDICT_ACK = new Tcontrol_t [_param->_nb_inst_predict]; - internal_DECOD_ACK = new Tcontrol_t [_param->_nb_inst_decod]; - internal_BRANCH_COMPLETE_ACK = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_BRANCH_COMPLETE_MISS_PREDICTION = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_BRANCH_COMPLETE_TAKE = new Tcontrol_t [_param->_nb_inst_branch_complete]; - internal_BRANCH_COMPLETE_ADDRESS_DEST = new Taddress_t [_param->_nb_inst_branch_complete]; - internal_BRANCH_EVENT_VAL = new Tcontrol_t [_param->_nb_context]; - internal_BRANCH_EVENT_DEPTH = new Tdepth_t [_param->_nb_context]; - internal_UPDATE_VAL = new Tcontrol_t [_param->_nb_inst_update]; - internal_UPDATE_CONTEXT_ID = new Tcontext_t [_param->_nb_inst_update]; - internal_UPDATE_DEPTH = new Tdepth_t [_param->_nb_inst_update]; + ALLOC1(internal_PREDICT_ACK ,Tcontrol_t,_param->_nb_inst_predict); + ALLOC1(internal_PREDICT_UPDATE_PREDICTION_ID ,Tdepth_t ,_param->_nb_inst_predict); + ALLOC1(internal_DECOD_ACK ,Tcontrol_t,_param->_nb_inst_decod); + ALLOC1(internal_DECOD_UPT_PTR_WRITE ,uint32_t ,_param->_nb_inst_decod); + ALLOC1(internal_BRANCH_COMPLETE_ACK ,Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_BRANCH_COMPLETE_MISS_PREDICTION ,Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_BRANCH_COMPLETE_TAKE ,Tcontrol_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_BRANCH_COMPLETE_ADDRESS_DEST ,Taddress_t,_param->_nb_inst_branch_complete); + ALLOC1(internal_BRANCH_EVENT_VAL ,Tcontrol_t,_param->_nb_context); + ALLOC1(internal_BRANCH_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); + ALLOC1(internal_UPDATE_VAL ,Tcontrol_t,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_VAL_WITHOUT_ACK ,Tcontrol_t,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_CONTEXT_ID ,Tcontext_t,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_FROM_UFPT ,bool ,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_DEPTH ,Tdepth_t ,_param->_nb_inst_update); + ALLOC1(internal_UPDATE_RAS ,bool ,_param->_nb_inst_update); // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - reg_TOP = new uint32_t [_param->_nb_context]; - reg_BOTTOM = new uint32_t [_param->_nb_context]; - reg_NB_ELT = new uint32_t [_param->_nb_context]; - reg_NB_ELT_UPDATE = new uint32_t [_param->_nb_context]; - reg_NB_ELT_NEED_UPDATE = new uint32_t [_param->_nb_context]; - reg_UPDATE_PREDICTION_TABLE = new entry_t * [_param->_nb_context]; - for (uint32_t i=0; i<_param->_nb_context; i++) - { -#ifndef NO_INIT - reg_TOP [i] = 0; -#endif - reg_UPDATE_PREDICTION_TABLE [i] = new entry_t [_param->_size_queue[i]]; + + ALLOC1(reg_IS_ACCURATE ,bool ,_param->_nb_context); + + ALLOC2(reg_UPDATE_FETCH_PREDICTION_TABLE,ufpt_entry_t ,_param->_nb_context,_param->_size_ufpt_queue[it1]); + ALLOC1(reg_UFPT_BOTTOM ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UFPT_TOP ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UFPT_UPDATE ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UFPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); + + ALLOC2(reg_UPDATE_PREDICTION_TABLE ,upt_entry_t ,_param->_nb_context,_param->_size_upt_queue[it1]); + ALLOC1(reg_UPT_BOTTOM ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UPT_TOP ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UPT_UPDATE ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UPT_NB_NEED_UPDATE ,uint32_t ,_param->_nb_context); + + ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); + ALLOC1(reg_EVENT_RAS_CORRUPTED ,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_SRC_VAL ,Tcontrol_t ,_param->_nb_context); + ALLOC1(reg_EVENT_ADDRESS_DEST ,Taddress_t ,_param->_nb_context); } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -42,6 +43,6 @@ delete [] in_PREDICT_RAS_ADDRESS ; delete [] in_PREDICT_RAS_INDEX ; -// if (_param->_have_port_depth) -// delete [] out_PREDICT_UPDATE_PREDICTION_ID; + if (_param->_have_port_depth) + delete [] out_PREDICT_UPDATE_PREDICTION_ID; // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -58,8 +59,9 @@ delete [] in_DECOD_MISS_IFETCH ; delete [] in_DECOD_MISS_DECOD ; - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) delete [] in_DECOD_UPDATE_PREDICTION_ID ; // if (_param->_have_port_depth) // delete [] out_DECOD_DEPTH ; + delete [] in_DECOD_IS_ACCURATE ; // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -68,5 +70,5 @@ if (_param->_have_port_context_id) delete [] in_BRANCH_COMPLETE_CONTEXT_ID ; - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) delete [] in_BRANCH_COMPLETE_DEPTH ; delete [] in_BRANCH_COMPLETE_ADDRESS ; @@ -82,5 +84,5 @@ // if (_param->_have_port_context_id) // delete [] in_BRANCH_EVENT_CONTEXT_ID ; -// if (_param->_have_port_max_depth) +// if (_param->_have_port_depth) // delete [] in_BRANCH_EVENT_DEPTH ; // delete [] out_BRANCH_EVENT_MISS_PREDICTION; @@ -109,33 +111,50 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) { - delete [] out_DEPTH_NB_BRANCH; - delete [] out_DEPTH_TAIL; + delete [] out_DEPTH_CURRENT; + delete [] out_DEPTH_MIN; } - } - - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_PREDICT_ACK ; - delete [] internal_DECOD_ACK ; - delete [] internal_BRANCH_COMPLETE_ACK ; - delete [] internal_BRANCH_COMPLETE_MISS_PREDICTION ; - delete [] internal_BRANCH_COMPLETE_TAKE ; - delete [] internal_BRANCH_COMPLETE_ADDRESS_DEST ; - delete [] internal_BRANCH_EVENT_VAL ; - delete [] internal_BRANCH_EVENT_DEPTH ; - delete [] internal_UPDATE_VAL ; - delete [] internal_UPDATE_CONTEXT_ID ; - delete [] internal_UPDATE_DEPTH ; - - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] reg_TOP; - delete [] reg_BOTTOM; - delete [] reg_NB_ELT; - delete [] reg_NB_ELT_UPDATE; - delete [] reg_NB_ELT_NEED_UPDATE; - for (uint32_t i=0; i<_param->_nb_context; i++) - delete [] reg_UPDATE_PREDICTION_TABLE [i]; - delete [] reg_UPDATE_PREDICTION_TABLE; + delete [] out_DEPTH_MAX; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); + DELETE1(internal_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict); + DELETE1(internal_DECOD_ACK ,_param->_nb_inst_decod); + DELETE1(internal_DECOD_UPT_PTR_WRITE ,_param->_nb_inst_decod); + DELETE1(internal_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + DELETE1(internal_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); + DELETE1(internal_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); + DELETE1(internal_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); + DELETE1(internal_BRANCH_EVENT_VAL ,_param->_nb_context); + DELETE1(internal_BRANCH_EVENT_DEPTH ,_param->_nb_context); + DELETE1(internal_UPDATE_VAL ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_VAL_WITHOUT_ACK ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_CONTEXT_ID ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_FROM_UFPT ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_DEPTH ,_param->_nb_inst_update); + DELETE1(internal_UPDATE_RAS ,_param->_nb_inst_update); + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + DELETE1(reg_IS_ACCURATE ,_param->_nb_context); + + DELETE2(reg_UPDATE_FETCH_PREDICTION_TABLE,_param->_nb_context,_param->_size_ufpt_queue[it1]); + DELETE1(reg_UFPT_BOTTOM ,_param->_nb_context); + DELETE1(reg_UFPT_TOP ,_param->_nb_context); + DELETE1(reg_UFPT_UPDATE ,_param->_nb_context); + DELETE1(reg_UFPT_NB_NEED_UPDATE ,_param->_nb_context); + + DELETE2(reg_UPDATE_PREDICTION_TABLE ,_param->_nb_context,_param->_size_upt_queue[it1]); + DELETE1(reg_UPT_BOTTOM ,_param->_nb_context); + DELETE1(reg_UPT_TOP ,_param->_nb_context); + DELETE1(reg_UPT_UPDATE ,_param->_nb_context); + DELETE1(reg_UPT_NB_NEED_UPDATE ,_param->_nb_context); + + DELETE1(reg_EVENT_STATE ,_param->_nb_context); + DELETE1(reg_EVENT_RAS_CORRUPTED ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_SRC_VAL ,_param->_nb_context); + DELETE1(reg_EVENT_ADDRESS_DEST ,_param->_nb_context); + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,4 +32,5 @@ // Evaluation before read the ouput signal // sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 88) @@ -22,14 +22,35 @@ void Update_Prediction_Table::genMealy_branch_complete (void) { - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); + log_begin(Update_Prediction_Table,FUNCTION); + log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) +#ifdef DEBUG_TEST + // just to don't have exception in not transaction + if (PORT_READ(in_BRANCH_COMPLETE_VAL [i])) +#endif { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE [%d]",i); + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; Tcontrol_t miss = false; Tcontrol_t take = reg_UPDATE_PREDICTION_TABLE [context][depth]._last_take ; Taddress_t addr_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition ; + + Tcontrol_t flag = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]); + Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",flag); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_good : %.8x",addr_good); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * (before)"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_dest : %.8x",addr_dest); switch (condition) @@ -39,28 +60,45 @@ { //miss : always hit - //addr_dest : know in decod stage + //addr_dest : compute in decod stage + +#ifdef DEBUG_TEST + if (take != 1) + throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); + if (addr_dest != addr_good) + throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +#endif + break; } case BRANCH_CONDITION_FLAG_UNSET : // l.bnf { - Tcontrol_t take_good = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]) == 0; + //addr_dest : compute in decod stage + //miss if the direction is bad + Tcontrol_t take_good = not flag; // flag set = not take + miss = (take != take_good); take = take_good; - //addr_dest : know in decod stage + +#ifdef DEBUG_TEST + if (addr_dest != addr_good) + throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +#endif + break; } case BRANCH_CONDITION_FLAG_SET : // l.bf { -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG_SET"); - - Tcontrol_t take_good = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]) == 1; + //addr_dest : compute in decod stage + //miss if the direction is bad + Tcontrol_t take_good = flag; // flag set = take + miss = (take != take_good); take = take_good; -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",PORT_READ(in_BRANCH_COMPLETE_FLAG [i])); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take_good : %d",take_good); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); - - //addr_dest : know in decod stage +#ifdef DEBUG_TEST + if (addr_dest != addr_good) + throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +#endif + break; } @@ -69,21 +107,26 @@ case BRANCH_CONDITION_READ_STACK : // l.jr (rb==r9) { - Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); - miss = ((take == 1) and - (addr_dest = addr_good)); - take = 1; + // miss if destination address is bad + miss = (addr_dest != addr_good); addr_dest = addr_good; + +#ifdef DEBUG_TEST + if (take != 1) + throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); +#endif + break; } } -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address : %x",addr_dest); - + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * (after)"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * take : %d",take); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_dest : %.8x",addr_dest); + internal_BRANCH_COMPLETE_MISS_PREDICTION [i] = miss ; internal_BRANCH_COMPLETE_TAKE [i] = take ; internal_BRANCH_COMPLETE_ADDRESS_DEST [i] = addr_dest; - + PORT_WRITE(out_BRANCH_COMPLETE_MISS_PREDICTION [i], internal_BRANCH_COMPLETE_MISS_PREDICTION [i]); PORT_WRITE(out_BRANCH_COMPLETE_TAKE [i], internal_BRANCH_COMPLETE_TAKE [i]); @@ -92,5 +135,5 @@ } - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); + log_end(Update_Prediction_Table,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp (revision 88) @@ -22,26 +22,42 @@ void Update_Prediction_Table::genMealy_decod (void) { - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); + log_begin(Update_Prediction_Table,FUNCTION); + log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); + // WARNING : One branch per context per cycle for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { - Tcontrol_t miss = PORT_READ(in_DECOD_MISS_DECOD [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD [%d]",i); - if (miss) - { - // miss : need a empty slot. - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; - uint32_t top = reg_TOP[context]; - internal_DECOD_ACK [i] = (reg_UPDATE_PREDICTION_TABLE [context][top]._state == UPDATE_PREDICTION_STATE_EMPTY); - } - else - { - internal_DECOD_ACK [i] = true; - } + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; + bool is_accurate = reg_IS_ACCURATE [context]; + event_state_t event_state = reg_EVENT_STATE [context]; + uint32_t ptr_write = reg_UPT_TOP [context]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_state : %s",toString(event_state).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ptr_write : %d",ptr_write ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_state : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state).c_str()); + + // ack : + // * in all case (miss or hit), need empty slot + // * is_accurate + // * event_state : don't update upt + internal_DECOD_ACK [i] = ((reg_UPDATE_PREDICTION_TABLE [context][ptr_write]._state == UPDATE_PREDICTION_STATE_EMPTY) and + is_accurate and +// ( + (event_state == EVENT_STATE_OK )// or +// (event_state == EVENT_STATE_FLUSH_UFPT ) or +// (event_state == EVENT_STATE_UPDATE_CONTEXT)) + ); + internal_DECOD_UPT_PTR_WRITE [i] = ptr_write; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ack : %d",internal_DECOD_ACK [i]); PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); } - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); + log_end(Update_Prediction_Table,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_predict.cpp (revision 88) @@ -22,31 +22,46 @@ void Update_Prediction_Table::genMealy_predict (void) { - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); - + log_begin(Update_Prediction_Table,FUNCTION); + log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); + + if (PORT_READ(in_NRESET) != 0) + { + for (uint32_t i=0; i<_param->_nb_inst_predict; i++) { Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; - uint32_t top = reg_TOP[context]; + uint32_t top = reg_UFPT_TOP[context]; -// log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT [%d] (genMealy)",i); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(reg_UPDATE_PREDICTION_TABLE [context][top]._state).c_str()); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is accurate : %d",PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])); + log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT [%d] (genMealy)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is accurate : %d",PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])); // log_printf(TRACE,Update_Prediction_Table,FUNCTION," * need update : %d",reg_NB_ELT_NEED_UPDATE [context]); - // Not Full, accurate and no previous miss - // Optimisation to restart faster : - // don't counter nb_elt_ko, but just nb_elt that need a update (change branch structure) - internal_PREDICT_ACK [i] = ((reg_UPDATE_PREDICTION_TABLE [context][top]._state == UPDATE_PREDICTION_STATE_EMPTY) and - PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and - (reg_NB_ELT_NEED_UPDATE [context] == 0)); + internal_PREDICT_UPDATE_PREDICTION_ID [i] = top; -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ACK : %d",internal_PREDICT_ACK [i]); + if (_param->_have_port_depth) + PORT_WRITE(out_PREDICT_UPDATE_PREDICTION_ID [i], internal_PREDICT_UPDATE_PREDICTION_ID [i]); + bool is_accurate = not _param->_not_accurate_block_predict or reg_IS_ACCURATE[context]; + + // Ack if : + // * slot is empty + // * no previous miss + // * is_accurate + internal_PREDICT_ACK [i] = ((reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state == UPDATE_FETCH_PREDICTION_STATE_EMPTY) and +// PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and + (reg_EVENT_STATE [context] == EVENT_STATE_OK) and + is_accurate); + + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ACK : %d",internal_PREDICT_ACK [i]); PORT_WRITE(out_PREDICT_ACK [i], internal_PREDICT_ACK [i]); } - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); + }//don't reset + + log_end(Update_Prediction_Table,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 88) @@ -22,5 +22,10 @@ void Update_Prediction_Table::genMoore (void) { - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); + log_begin(Update_Prediction_Table,FUNCTION); + log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); + log_printf(NONE,Update_Prediction_Table,FUNCTION,FUNCTION); + + if (PORT_READ(in_NRESET) == 1) + { // =================================================================== @@ -30,99 +35,234 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - if (_param->_have_port_depth [i]) - { - PORT_WRITE(out_DEPTH_TAIL [i], reg_BOTTOM [i]); - } - PORT_WRITE(out_DEPTH_NB_BRANCH [i], reg_NB_ELT [i]); - } + if (_param->_have_port_depth) + { + PORT_WRITE(out_DEPTH_CURRENT [i], reg_UPT_TOP [i]); + PORT_WRITE(out_DEPTH_MIN [i], reg_UPT_BOTTOM [i]); + } + PORT_WRITE(out_DEPTH_MAX [i], reg_UPT_TOP [i]); + } + // =================================================================== // =====[ UPDATE ]==================================================== // =================================================================== - Tdepth_t tab_depth [_param->_nb_context]; + bool retire_ras_from_ufpt [_param->_nb_context]; // event ufpt -> restore RAS, else update upt + bool retire_ras_from_upt [_param->_nb_context]; // event upt -> restore RAS, else restore others structure + bool ufpt_update [_param->_nb_context]; + bool upt_update [_param->_nb_context]; + Tdepth_t tab_ufpt_depth [_param->_nb_context]; + Tdepth_t tab_upt_depth [_param->_nb_context]; + for (uint32_t i=0; i<_param->_nb_context; i++) - tab_depth [i] = reg_BOTTOM [i]; + { + event_state_t event_state = reg_EVENT_STATE [i]; + + retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or + (event_state == EVENT_STATE_FLUSH_UFPT_AND_UPT)); + retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT_RAS); + + ufpt_update [i] = true; + upt_update [i] = true; + tab_ufpt_depth [i] = reg_UFPT_UPDATE [i]; + tab_upt_depth [i] = reg_UPT_UPDATE [i]; + } for (uint32_t i=0; i<_param->_nb_inst_update; i++) { - uint32_t context = (reg_UPDATE_PRIORITY+i)%_param->_nb_context; - Tdepth_t depth = tab_depth[context]; - state_t state = reg_UPDATE_PREDICTION_TABLE [context][depth]._state; + Tcontext_t context = (reg_UPDATE_PRIORITY+i)%_param->_nb_context; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE [%d] (genMoore)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * event_state : %s",toString(reg_EVENT_STATE [context]).c_str()); + + Tcontrol_t val = false; + Tcontrol_t val_without_ack = false; + Tcontrol_t miss_prediction ; + Tcontrol_t direction_good ; + Tcontrol_t btb_val ; + Taddress_t btb_address_src ; + Taddress_t btb_address_dest ; + Tbranch_condition_t btb_condition ; + Tcontrol_t dir_val ; + Thistory_t dir_history ; + Tcontrol_t ras_val ; + Tcontrol_t ras_push ; + Taddress_t ras_address ; + Tptr_t ras_index ; + Tcontrol_t ras_prediction_ifetch; + + // Test if update fetch prediction table need update port + if (retire_ras_from_ufpt [context]) + { + if (ufpt_update [context]) + { + // Update Fetch Prediction Table + // An update of ufpt is to previous miss. Just restore Return Address Stack + + Tdepth_t depth = tab_ufpt_depth[context]; + ufpt_state_t state = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state; + Tbranch_condition_t condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state ).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); + + val = (state == UPDATE_FETCH_PREDICTION_STATE_EVENT); + miss_prediction = 1; +// direction_good = ; + btb_val = 0; // don't update btb (is update by the event branch) +// btb_address_src = ; +// btb_address_dest = ; +// btb_condition = ; + dir_val = 0; // don't update btb (is update by the event branch (if conditionnal branch)) +// dir_history = ; + ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras + ras_push = push_ras(condition); + ras_address = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras; + ras_index = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._index_ras; + ras_prediction_ifetch = 1; + + internal_UPDATE_FROM_UFPT [i] = true; + internal_UPDATE_DEPTH [i] = depth; + internal_UPDATE_RAS [i] = false; + + // Warning : don't update same entry + if (depth == reg_UFPT_BOTTOM[context]) + ufpt_update [context] = false; + + tab_ufpt_depth[context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1); + } + } + else + { + if (upt_update [context]) + { + // Update Prediction Table + + Tdepth_t depth = tab_upt_depth[context]; + upt_state_t state = reg_UPDATE_PREDICTION_TABLE [context][depth]._state; + Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; + Tcontrol_t ifetch = reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state ).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); + + Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK) or + (state == UPDATE_PREDICTION_STATE_KO)); + Tcontrol_t state_is_event = (state == UPDATE_PREDICTION_STATE_EVENT); + Tcontrol_t state_is_event_update = state_is_event and need_update(condition); + Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); + + if (retire_ras_from_upt [context]) + { + val = state_is_event_update; + val_without_ack = state_is_event_no_update; + } + else + { + val = state_is_ok_ko; + val_without_ack = false; + } + + miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); + direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; + btb_val = update_btb(condition); + btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; + btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; + btb_condition = condition; + dir_val = update_dir(condition) and ifetch; // if not ifetch, then static prediction + dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; + ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras + ras_push = push_ras(condition); + ras_address = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras; + ras_index = reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras; + ras_prediction_ifetch = ifetch; + + internal_UPDATE_FROM_UFPT [i] = false; + internal_UPDATE_DEPTH [i] = depth; + internal_UPDATE_RAS [i] = retire_ras_from_upt [context]; + + // Warning : don't update same entry + if (retire_ras_from_upt [context]) + { + // Restore RAS. + if ((depth == reg_UPT_BOTTOM[context]) or not (val or val_without_ack)) + upt_update [context] = false; + + tab_upt_depth[context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1); + } + else + { + if ((depth == reg_UPT_TOP [context]) or not (val or val_without_ack)) + upt_update [context] = false; + + tab_upt_depth[context] = (depth+1)%_param->_size_upt_queue[context]; + } + } + } + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val ); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val_without_ack : %d",val_without_ack); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * btb_val : %d",btb_val); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * dir_val : %d",dir_val); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ras_val : %d",ras_val); + + internal_UPDATE_VAL [i] = val; + internal_UPDATE_VAL_WITHOUT_ACK [i] = val_without_ack; + internal_UPDATE_CONTEXT_ID [i] = context; + + PORT_WRITE(out_UPDATE_VAL [i],internal_UPDATE_VAL [i]); + if (val) + { + if (_param->_have_port_context_id) + PORT_WRITE(out_UPDATE_CONTEXT_ID [i],context ); + PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],miss_prediction ); + PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],direction_good ); + PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val ); + PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],btb_address_src ); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_src : %.8x",btb_address_src); + + PORT_WRITE(out_UPDATE_BTB_ADDRESS_DEST [i],btb_address_dest ); + PORT_WRITE(out_UPDATE_BTB_CONDITION [i],btb_condition ); + PORT_WRITE(out_UPDATE_DIR_VAL [i],dir_val ); + if (_param->_have_port_history) + PORT_WRITE(out_UPDATE_DIR_HISTORY [i],dir_history ); + PORT_WRITE(out_UPDATE_RAS_VAL [i],ras_val ); + PORT_WRITE(out_UPDATE_RAS_PUSH [i],ras_push ); + PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],ras_address ); + PORT_WRITE(out_UPDATE_RAS_INDEX [i],ras_index ); + PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ras_prediction_ifetch); + } + } + +// // =================================================================== +// // =====[ BRANCH_EVENT ]============================================== +// // =================================================================== +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// Tdepth_t depth = (reg_BOTTOM [i] + reg_NB_ELT_UPDATE [i])%_param->_size_queue [i]; +// state_t state = reg_UPDATE_PREDICTION_TABLE [i][depth]._state; - Tcontrol_t val = ((state == UPDATE_PREDICTION_STATE_OK) or - (state == UPDATE_PREDICTION_STATE_KO)); - -// log_printf(TRACE,Update_Prediction_Table,FUNCTION,"UPDATE [%d] (genMoore)",i); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : %s",toString(state).c_str()); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * addr_src : %x",reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ); -// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * addr_dest : %x",reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest); - - if (val) - { - Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; - - Tcontrol_t ifetch = reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction; - Tcontrol_t btb_val = true; - Tcontrol_t dir_val = (ifetch and // not ifetch == static prediction - ((cond == BRANCH_CONDITION_FLAG_UNSET) or - (cond == BRANCH_CONDITION_FLAG_SET))); - Tcontrol_t ras_val = ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_STACK)); - - Tcontrol_t push = ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK)); - - if (_param->_have_port_context_id) - PORT_WRITE(out_UPDATE_CONTEXT_ID [i],context); - PORT_WRITE(out_UPDATE_MISS_PREDICTION [i],(state == UPDATE_PREDICTION_STATE_KO)); - PORT_WRITE(out_UPDATE_DIRECTION_GOOD [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ); - PORT_WRITE(out_UPDATE_BTB_VAL [i],btb_val); - PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ); - PORT_WRITE(out_UPDATE_BTB_ADDRESS_DEST [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest); - PORT_WRITE(out_UPDATE_BTB_CONDITION [i],cond); - PORT_WRITE(out_UPDATE_DIR_VAL [i],dir_val); - if (_param->_have_port_history) - PORT_WRITE(out_UPDATE_DIR_HISTORY [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._history ); - PORT_WRITE(out_UPDATE_RAS_VAL [i],ras_val); - PORT_WRITE(out_UPDATE_RAS_PUSH [i],push); - PORT_WRITE(out_UPDATE_RAS_ADDRESS [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras ); - PORT_WRITE(out_UPDATE_RAS_INDEX [i],reg_UPDATE_PREDICTION_TABLE [context][depth]._index_ras ); - PORT_WRITE(out_UPDATE_RAS_PREDICTION_IFETCH [i],ifetch); - - internal_UPDATE_CONTEXT_ID [i] = context; - internal_UPDATE_DEPTH [i] = depth; - - tab_depth[context] = (depth+1)%_param->_size_queue[context]; - } - - internal_UPDATE_VAL [i] = val; - PORT_WRITE(out_UPDATE_VAL [i], internal_UPDATE_VAL [i]); - } - - // =================================================================== - // =====[ BRANCH_EVENT ]============================================== - // =================================================================== - for (uint32_t i=0; i<_param->_nb_context; i++) - { - Tdepth_t depth = (reg_BOTTOM [i] + reg_NB_ELT_UPDATE [i])%_param->_size_queue [i]; - state_t state = reg_UPDATE_PREDICTION_TABLE [i][depth]._state; - - Tcontrol_t val = (state == UPDATE_PREDICTION_STATE_EVENT); - - if (val) - { - PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_src ); - PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_dest); - internal_BRANCH_EVENT_DEPTH [i] = depth; - } - - internal_BRANCH_EVENT_VAL [i] = val; - PORT_WRITE(out_BRANCH_EVENT_VAL [i], internal_BRANCH_EVENT_VAL [i]); - } - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); +// Tcontrol_t val = ((state == UPDATE_PREDICTION_STATE_EVENT) or +// (state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT)); + +// if (val) +// { +// // breakpoint ("UPT : have an branch_event (depth %d)",depth); +// PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_src ); +// PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_dest); +// internal_BRANCH_EVENT_DEPTH [i] = depth; +// } + +// internal_BRANCH_EVENT_VAL [i] = val; +// PORT_WRITE(out_BRANCH_EVENT_VAL [i], internal_BRANCH_EVENT_VAL [i]); +// } + + } + log_end(Update_Prediction_Table,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp (revision 88) @@ -27,4 +27,21 @@ "Update_Prediction_Table", param_statistics); + +// _stat_nb_branch_hit = new counter_t * [_param->_nb_context]; +// _stat_nb_branch_miss = new counter_t * [_param->_nb_context]; +// _stat_nb_branch_unused = new counter_t * [_param->_nb_context]; +// _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context]; +// _stat_queue_nb_cycle_full = new counter_t * [_param->_nb_context]; +// _stat_queue_nb_elt = new counter_t * [_param->_nb_context]; + +// for (uint32_t i=0; i<_param->_nb_context; ++i) +// { +// _stat_nb_branch_hit [i] = _stat->create_counter("nb_branch_hit_" +toString(i),"",toString(_("Branch hit speculation (context %d)"),i)); +// _stat_nb_branch_miss [i] = _stat->create_counter("nb_branch_miss_" +toString(i),"",toString(_("Branch miss speculation (context %d)"),i)); +// _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i)); +// _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i)); +// _stat_queue_nb_cycle_full [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i)); +// _stat_queue_nb_elt [i] = _stat->create_counter("queue_nb_elt_" +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); +// } log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp (revision 88) @@ -26,5 +26,11 @@ log_printf(INFO,Update_Prediction_Table,FUNCTION,"Generate Statistics file"); - delete _stat; + delete _stat; +// delete [] _stat_nb_branch_hit ; +// delete [] _stat_nb_branch_miss ; +// delete [] _stat_nb_branch_unused ; +// delete [] _stat_queue_nb_cycle_empty; +// delete [] _stat_queue_nb_cycle_full ; +// delete [] _stat_queue_nb_elt ; log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 88) @@ -17,54 +17,128 @@ namespace update_prediction_table { - #undef FUNCTION #define FUNCTION "Update_Prediction_Table::transition" void Update_Prediction_Table::transition (void) { - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"Begin"); + log_begin(Update_Prediction_Table,FUNCTION); + log_function(Update_Prediction_Table,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) { + // Initialisation + + reg_UPDATE_PRIORITY = 0; + + // All pointer is set at 0 for (uint32_t i=0; i<_param->_nb_context; i++) { - reg_TOP [i] = 0; - reg_BOTTOM [i] = 0; - reg_NB_ELT [i] = 0; - reg_NB_ELT_UPDATE [i] = 0; - reg_NB_ELT_NEED_UPDATE [i] = 0; - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; - } - reg_UPDATE_PRIORITY = 0; + for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j) + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; + reg_UFPT_BOTTOM [i] = 0; + reg_UFPT_TOP [i] = 0; + reg_UFPT_UPDATE [i] = 0; + reg_UFPT_NB_NEED_UPDATE [i] = 0; + + for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j) + reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY; + reg_UPT_BOTTOM [i] = 0; + reg_UPT_TOP [i] = 0; + reg_UPT_UPDATE [i] = 0; + reg_UPT_NB_NEED_UPDATE [i] = 0; + + reg_IS_ACCURATE [i] = true; + + reg_EVENT_STATE [i] = EVENT_STATE_OK; + } } else { // =================================================================== + // =====[ GARBAGE COLLECTOR ]========================================= + // =================================================================== + + // Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot + // * Update state -> new status is "empty" + // * Update pointer (bottom and accurate) + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR"); + for (uint32_t i=0; i<_param->_nb_context; i++) + { + // UPDATE_FETCH_PREDICTION_TABLE + { + uint32_t bottom = reg_UFPT_BOTTOM [i]; + + // Test if state is end + if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom); + + // Free slot + reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; + // Update pointer + reg_UFPT_BOTTOM [i] = (bottom+1)%_param->_size_ufpt_queue[i]; + } + } + + // UPDATE_PREDICTION_TABLE + { + uint32_t bottom = reg_UPT_BOTTOM [i]; + + // Test if state is end + if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom); + + // Free slot + reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; + // Update pointer + reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; + } + } + } + + // =================================================================== // =====[ PREDICT ]=================================================== // =================================================================== + + // An ifetch_unit compute next cycle and have an branch : predict_val is set + // * Alloc new entry -> new status is "wait decod" + // * Save input (to restore in miss or error) + // * Update pointer + for (uint32_t i=0; i<_param->_nb_inst_predict; i++) if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i]) { Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0; - uint32_t top = reg_TOP [context]; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"PREDICT[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); - - reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAIT_DECOD; - reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = true; - reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); - //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take - reg_UPDATE_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; - reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); - - reg_TOP [context] = (top+1)%_param->_size_queue [context]; - reg_NB_ELT [context] ++; + uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); + +#ifdef DEBUG_TEST + if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) + throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD; + + Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); + + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition; + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0; + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]); + + reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context]; +// reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; + if (need_update(condition)) + reg_UFPT_NB_NEED_UPDATE [context] ++; } @@ -72,75 +146,139 @@ // =====[ DECOD ]===================================================== // =================================================================== + + + // An decod is detected by decod stage + // 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch + // * Update state, wait_decod -> wait_end + // * Pop ufpt -> push upt + // * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod + // 2) Miss : The instruction bundle have a branch but it is not predicted + // * Flush ufpt + // * decod information is write in upt + for (uint32_t i=0; i<_param->_nb_inst_decod; i++) if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i]) { - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; - Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); - Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); - - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"DECOD[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0; + Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]); + Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]); + uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i]; + Tbranch_condition_t condition ; + Tcontrol_t is_accurate; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write); - // Test if miss ifetch - // miss ifetch = decod a branch and the predict unit have not predict this branch ... gloup :P - if (miss_ifetch or miss_decod) + if (miss_ifetch or miss_decod) { - Tdepth_t depth = (_param->_have_port_max_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; - Tdepth_t top = reg_TOP [context]; - - reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_WAITEND; - reg_UPDATE_PREDICTION_TABLE [context][top]._ifetch_prediction = false; // static prediction - reg_UPDATE_PREDICTION_TABLE [context][top]._condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); - //reg_UPDATE_PREDICTION_TABLE [context][top]._good_take - //reg_UPDATE_PREDICTION_TABLE [context][top]._history - reg_UPDATE_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); - reg_UPDATE_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); - - // Invalid all previous "ifetch" prediction - // (ifetch prediction = prediction make in fetch stage and not again comming in decod stage) - uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; - uint32_t nb_elt_need_update = 0; - for (uint32_t j=0; j_size_queue[context]; - - // Ifetch have make a prediction and it's a miss - // When ifetch predict : - // * btb is not change -> needn't update - // * direction is not change -> needn't update - // * ras have change -> need update - - Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; - if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_STACK)) - { - nb_elt_need_update ++; - reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; - } - else - { - reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; - } - } - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; // rewrite - - reg_TOP [context] = (depth+1)%_param->_size_queue [context]; - reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; - reg_NB_ELT [context] ++; + // Have a miss !!! + + // Flush UPFT + + // It's to accelerate miss speculation + if (reg_UFPT_NB_NEED_UPDATE [context] == 0) + { + // No entry need prediction, flush all entry -> Reset + for (uint32_t j=0; j<_param->_size_ufpt_queue[context]; ++j) + reg_UPDATE_FETCH_PREDICTION_TABLE [context][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY; + reg_UFPT_BOTTOM [context] = 0; + reg_UFPT_TOP [context] = 0; +// reg_UFPT_UPDATE [context] = 0; + } + else + { + reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context]; + +#ifdef DEBUG_TEST + if (reg_EVENT_STATE [context] == EVENT_STATE_OK) + throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state.")); +#endif + + // Change state + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss)",context); + + reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT; + } + + // Push upt (from decod interface) + condition = PORT_READ(in_DECOD_BTB_CONDITION [i]); + is_accurate = PORT_READ(in_DECOD_IS_ACCURATE [i]); + + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]); + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]); + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]); +// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; +// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]); + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]); + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction } else { // Normal case : branch is previous predicated, change state of branch - Tdepth_t depth = (_param->_have_port_max_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; - - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; + uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read); + +#ifdef DEBUG_TEST + if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD) + throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state.")); +#endif + // Change state + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read); + reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END; + + // Push upt (from Pop ufpt) + condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition; + is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate; + + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ; +// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ; + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true; // prediction from ifetch + + // Update pointer + if (need_update(condition)) + { + reg_UFPT_NB_NEED_UPDATE [context] --; + } } + + // All case !!! + +#ifdef DEBUG_TEST + if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY) + throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state.")); +#endif + + // Change state + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write); + reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END; + + // Write new accurate +#ifdef DEBUG_TEST + if (not reg_IS_ACCURATE [context] and not is_accurate) + throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag.")); +#endif + reg_IS_ACCURATE [context] = is_accurate; + + // Update pointer + reg_UPT_TOP [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context]; +// reg_UPT_UPDATE [context] = reg_UPT_TOP [context]; + if (need_update(condition)) + { + reg_UPT_NB_NEED_UPDATE [context] ++; + } } @@ -148,67 +286,83 @@ // =====[ BRANCH_COMPLETE ]=========================================== // =================================================================== + + // The branch is complete + // * Hit prediction : + // * update status + // * Miss prediction : for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) { Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_max_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"BRANCH_COMPLETE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * nb_elt : %d",reg_NB_ELT[context]); + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",internal_BRANCH_COMPLETE_MISS_PREDICTION [i]); if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i]) { // Miss case - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; - - // Another prediction (prediction with depth higer) - Tdepth_t top = reg_TOP [context]; - uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; - uint32_t nb_elt_need_update = 1; - for (uint32_t j=1; j_size_queue[context]; +// // breakpoint("Branch_complete and miss ..."); + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_EVENT (branch_complete)",context,depth); +// reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT; + +// // Another prediction (prediction with depth higer) +// Tdepth_t top = reg_TOP [context]; +// uint32_t nb_elt_miss = ((top> depth)?top:(top+_param->_size_queue[context]))-depth; +// uint32_t nb_elt_need_update = 1; +// for (uint32_t j=1; j_size_queue[context]; - // Ifetch have make a prediction and it's a miss - // When ifetch predict : - // * btb is not change -> needn't update - // * direction is not change -> needn't update - // * ras have change -> need update - - Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; - if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or - (cond == BRANCH_CONDITION_READ_STACK)) - { - nb_elt_need_update ++; - reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; - } - else - { - reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; - } - } - reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; - - // Update pointer : - reg_TOP [context] = depth; - reg_NB_ELT [context] -= nb_elt_miss; +// // Ifetch have make a prediction and it's a miss +// // When ifetch predict : +// // * btb is not change -> needn't update +// // * direction is not change -> needn't update +// // * ras have change -> need update + +// Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition; +// if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or +// (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or +// (cond == BRANCH_CONDITION_READ_STACK)) +// { +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch miss, update ras)",context,k); + +// nb_elt_need_update ++; +// reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO; +// } +// else +// { +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_END (branch_complete, ifetch miss, don't update ras)",context,k); + +// reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END; +// } +// } +// reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update; + +// // Update pointer : +// reg_TOP [context] = depth; +// reg_NB_ELT [context] -= nb_elt_miss; +// reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; + } else { - // Hit case -#ifdef DEBUG_TEST - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAITEND) - ERRORMORPHEO(FUNCTION,"Branche complete : invalid state"); -#endif - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; + // Hit case + +#ifdef DEBUG_TEST + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END) + throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth); + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK; } - // In all case : update good_take and address_destination - reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i]; - reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i]; - } + // In all case : update good_take + reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i]; + } // =================================================================== @@ -216,17 +370,63 @@ // =================================================================== for (uint32_t i=0; i<_param->_nb_inst_update; i++) - if (internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) + if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or + (internal_UPDATE_VAL_WITHOUT_ACK [i])) { Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; Tdepth_t depth = internal_UPDATE_DEPTH [i]; - - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"UPDATE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) - reg_NB_ELT_NEED_UPDATE [context] --; - - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + + if (internal_UPDATE_FROM_UFPT [i]) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); + + // Change state +#ifdef DEBUG_TEST + if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) + throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); + + reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; + + // Update pointer + reg_UFPT_UPDATE [context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1); + + // Free a register that need update ? + if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) + reg_UFPT_NB_NEED_UPDATE [context] --; + } + else + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); + + // Change state +#ifdef DEBUG_TEST + if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and + (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) and + (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT)) + throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); + + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; + + // Update pointer + if (internal_UPDATE_RAS [i]) + reg_UPT_UPDATE [context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1); + else + reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; + + // Free a register that need update ? + if (need_update(reg_UPDATE_PREDICTION_TABLE [context][depth]._condition)) + reg_UPT_NB_NEED_UPDATE [context] --; + // Free the branch with no accurate ? + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) + reg_IS_ACCURATE [i] = true; + } } @@ -234,52 +434,83 @@ reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; - // =================================================================== - // =====[ BRANCH_EVENT ]============================================== - // =================================================================== - for (uint32_t i=0; i<_param->_nb_context; i++) - if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) - { - Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i]; - - reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO; - } - - // =================================================================== - // =====[ GARBAGE COLLECTOR ]========================================= - // =================================================================== - - for (uint32_t i=0; i<_param->_nb_context; i++) - { - uint32_t bottom = reg_BOTTOM [i]; - - // Test if the tail of queue is finish (ok or ko and update) - if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) - { - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"GARBAGE_COLLECTOR"); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom); - - reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; - reg_BOTTOM [i] = (bottom+1)%_param->_size_queue [i]; - if (reg_NB_ELT [i]>0) - reg_NB_ELT [i] --; - } - } - } +// // =================================================================== +// // =====[ BRANCH_EVENT ]============================================== +// // =================================================================== +// for (uint32_t i=0; i<_param->_nb_context; i++) +// if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) +// { +// Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i]; + +// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_EVENT) +// { +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_event)",i,depth); + +// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO; +// } +// else +// { +// #ifdef DEBUG_TEST +// if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT) +// throw ERRORMORPHEO(FUNCTION,_("Branche event : invalid state")); +// #endif + +// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state [%d][%d] <- UPDATE_PREDICTION_STATE_WAITEND (branch_event)",i,depth); + +// reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_WAITEND; +// } +// } #if (DEBUG >= DEBUG_TRACE) - log_printf(TRACE,Update_Prediction_Table,FUNCTION,"Dump Update_Prediction_Table"); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY); for (uint32_t i=0; i<_param->_nb_context; i++) { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_TOP : %d",reg_TOP [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_BOTTOM : %d",reg_BOTTOM [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT : %d",reg_NB_ELT [i]); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_NB_ELT_NEED_UPDATE : %d",reg_NB_ELT_NEED_UPDATE [i]); - for (uint32_t j=0; j<_param->_size_queue[i]; j++) - log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %s %x",j,toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str(),reg_UPDATE_PREDICTION_TABLE [i][j]._address_src); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_RAS_CORRUPTED : %d" ,reg_EVENT_RAS_CORRUPTED [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC_VAL : %d" ,reg_EVENT_ADDRESS_SRC_VAL [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x",reg_EVENT_ADDRESS_DEST [i]); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Fetch_Prediction_Table [%d]",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]); + for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) + log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d, %.8d %.8x %.4d - %s", + j, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras, + reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras, + toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str() + ); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update_Prediction_Table [%d]",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_NB_NEED_UPDATE : %d",reg_UPT_NB_NEED_UPDATE [i]); + for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) + log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s", + j, + reg_UPDATE_PREDICTION_TABLE [i][j]._condition, + reg_UPDATE_PREDICTION_TABLE [i][j]._address_src, + reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest, + reg_UPDATE_PREDICTION_TABLE [i][j]._last_take, + reg_UPDATE_PREDICTION_TABLE [i][j]._good_take, + reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate, + reg_UPDATE_PREDICTION_TABLE [i][j]._history, + reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras, + reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras, + toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str() + ); } #endif + } @@ -287,6 +518,6 @@ end_cycle (); #endif - - log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); + + log_end(Update_Prediction_Table,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h (revision 88) @@ -52,15 +52,15 @@ public : uint32_t * _upt_size_queue ;//[nb_context] - public : uint32_t _size_context_id ; - public : uint32_t * _size_depth ;//[nb_context] - public : uint32_t _max_size_depth ; - public : uint32_t * _size_inst_ifetch_ptr ;//[nb_context] +//public : uint32_t _size_context_id ; +//public : uint32_t _max_size_depth ; +//public : uint32_t * _size_inst_ifetch_ptr ;//[nb_context] + public : uint32_t * _array_size_depth ;//[nb_context] public : uint32_t _size_history ; public : uint32_t * _size_ras_index ;//[nb_context] - public : bool _have_port_context_id ; - public : bool _have_port_max_depth ; - public : bool * _have_port_depth ;//[nb_context] - public : bool * _have_port_inst_ifetch_ptr ;//[nb_context] +//public : bool _have_port_context_id ; +//public : bool _have_port_max_depth ; +//public : bool * _have_port_depth ;//[nb_context] +//public : bool * _have_port_inst_ifetch_ptr ;//[nb_context] public : bool _have_port_history ; public : bool * _have_port_ras_index ;//[nb_context] @@ -95,8 +95,11 @@ uint32_t dir_pht_size_address_share [3], uint32_t * ras_size_queue ,//[nb_context] - uint32_t * upt_size_queue //[nb_context] + uint32_t * upt_size_queue ,//[nb_context] + bool is_toplevel=false ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 88) @@ -114,6 +114,7 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_OUT(Tdepth_t ) ** out_DEPTH_NB_BRANCH ; //[nb_context] - public : SC_OUT(Tdepth_t ) ** out_DEPTH_TAIL ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_CURRENT ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ; //[nb_context] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp (revision 88) @@ -41,5 +41,6 @@ uint32_t dir_pht_size_address_share [3], uint32_t * ras_size_queue ,//[nb_context] - uint32_t * upt_size_queue //[nb_context] + uint32_t * upt_size_queue ,//[nb_context] + bool is_toplevel ) { @@ -72,20 +73,13 @@ _ras_size_queue = ras_size_queue ; _upt_size_queue = upt_size_queue ; - - _size_context_id = log2(_nb_context); -// public : uint32_t * _size_inst_ifetch_ptr ;//[nb_context] - - _size_depth = new uint32_t [_nb_context]; + + _array_size_depth = new uint32_t [_nb_context]; _size_ras_index = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; i++) { - _size_depth [i] = log2(_upt_size_queue [i]); - _size_ras_index [i] = log2(_ras_size_queue [i]); + _array_size_depth [i] = log2(_upt_size_queue [i]); + _size_ras_index [i] = log2(_ras_size_queue [i]); } - - _max_size_depth = max(_size_depth,_nb_context); - _have_port_context_id = (_size_context_id > 0); - _have_port_max_depth = (_max_size_depth > 0); -// public : bool * _have_port_inst_ifetch_ptr ;//[nb_context] _param_glue = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::prediction_unit_glue ::Parameters @@ -94,5 +88,5 @@ _size_address , _nb_instruction , - _size_depth , + _array_size_depth , _nb_inst_decod , _nb_inst_branch_predict, @@ -100,9 +94,4 @@ _nb_inst_branch_update ); - _size_inst_ifetch_ptr = _param_glue->_size_inst_ifetch_ptr ; - _have_port_depth = _param_glue->_have_port_depth; - _have_port_inst_ifetch_ptr = _param_glue->_have_port_inst_ifetch_ptr; - _have_port_history = (_size_history > 0); - _param_btb = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::branch_target_buffer ::Parameters (_nb_context , @@ -116,5 +105,5 @@ _nb_inst_branch_update , _btb_victim_scheme ); - + _param_dir = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::direction ::Parameters (_dir_predictor_scheme , @@ -130,5 +119,6 @@ _dir_pht_size_address_share); - _size_history = _param_dir->_size_history; + _size_history = _param_dir->_size_history; + _have_port_history = (_size_history > 0); _param_ras = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::return_address_stack ::Parameters @@ -150,4 +140,23 @@ _size_history , _size_ras_index ); + + + if (is_toplevel) + { + _size_context_id = log2(_nb_context); + _size_depth = max(_array_size_depth,_nb_context); + _size_inst_ifetch_ptr = log2(max(_nb_instruction,_nb_context)); + _size_instruction_address = size_address; +// _size_nb_inst_decod = ; +// _size_nb_inst_commit = ; +// _size_ifetch_queue_ptr = ; + + _have_port_context_id = (_size_context_id > 0); + _have_port_depth = (_size_depth > 0); + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; +// _have_port_ifetch_queue_ptr= _size_ifetch_queue_ptr > 0; + + copy (); + } test(); @@ -176,6 +185,21 @@ delete _param_glue; - delete [] _size_depth ; + delete [] _array_size_depth; delete [] _size_ras_index; + + log_printf(FUNC,Prediction_unit,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Prediction_unit::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Prediction_unit,FUNCTION,"Begin"); + + COPY(_param_btb ); + COPY(_param_dir ); + COPY(_param_ras ); + COPY(_param_upt ); + COPY(_param_glue); log_printf(FUNC,Prediction_unit,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit.cpp (revision 88) @@ -37,4 +37,10 @@ log_printf(FUNC,Prediction_unit,FUNCTION,"Begin"); +#if DEBUG_Prediction_unit == true + log_printf(INFO,Prediction_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Prediction_unit,FUNCTION,"Allocation"); @@ -46,5 +52,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Prediction_unit,FUNCTION,"Allocation of statistics"); @@ -55,5 +61,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -65,5 +71,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Prediction_unit,FUNCTION,"Method - transition"); @@ -89,5 +95,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 88) @@ -65,11 +65,11 @@ ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT ,"pc_next" ,Taddress_t ,_param->_size_address); ALLOC1_SIGNAL_OUT(out_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr [alloc_signal_it1]); + ALLOC1_SIGNAL_OUT(out_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t ,_param->_size_inst_ifetch_ptr); ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); - ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth [alloc_signal_it1]); + ALLOC1_SIGNAL_OUT(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); } { - ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[alloc_interface_it1]); - _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1]); + ALLOC2_INTERFACE("predict",IN,SOUTH,"Interface with ifetch unit",_param->_nb_context,_param->_nb_instruction[it1]); + _ALLOC2_SIGNAL_OUT(out_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1,_param->_nb_context,_param->_nb_instruction[it1]); } } @@ -78,16 +78,16 @@ { { - ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_interface_it1]); + ALLOC2_INTERFACE("decod",IN,SOUTH,"Interface with decod unit",_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); - _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_DECOD_ACK ,ACK,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_max_size_depth ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1]); + _ALLOC2_VALACK_IN ( in_DECOD_VAL ,VAL,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_VALACK_OUT(out_DECOD_ACK ,ACK,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_MATCH_INST_IFETCH_PTR ,"match_inst_ifetch_ptr" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_CONDITION ,"branch_condition" ,Tbranch_condition_t,_param->_size_branch_condition,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_BRANCH_DIRECTION ,"branch_direction" ,Tcontrol_t ,1 ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_DECOD_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_address ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1]); } } @@ -100,5 +100,5 @@ ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_max_size_depth); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t,1); @@ -116,5 +116,5 @@ ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_max_size_depth); +// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); @@ -126,6 +126,7 @@ ALLOC1_INTERFACE("depth",OUT,SOUTH,"Interface with depth",_param->_nb_context); - ALLOC1_SIGNAL_OUT(out_DEPTH_NB_BRANCH ,"nb_branch" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]+1); - ALLOC1_SIGNAL_OUT(out_DEPTH_TAIL ,"tail" ,Tdepth_t,_param->_size_depth[alloc_signal_it1]); + ALLOC1_SIGNAL_OUT(out_DEPTH_CURRENT ,"current" ,Tdepth_t,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t,_param->_size_depth+1); } @@ -551,4 +552,7 @@ COMPONENT_MAP(_component,src , "in_PREDICT_" +toString(i)+"_CONTEXT_ID" , dest,"out_PREDICT_UPT_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_PREDICT_" +toString(i)+ "_UPDATE_PREDICTION_ID", + dest, "in_PREDICT_UPT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); COMPONENT_MAP(_component,src , "in_PREDICT_" +toString(i)+"_BTB_ADDRESS_SRC" , dest,"out_PREDICT_UPT_"+toString(i)+"_BTB_ADDRESS_SRC" ); @@ -593,7 +597,9 @@ COMPONENT_MAP(_component,src , "in_DECOD_" +toString(i)+"_MISS_DECOD" , dest,"out_DECOD_UPT_"+toString(i)+"_MISS_DECOD" ); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) COMPONENT_MAP(_component,src , "in_DECOD_" +toString(i)+"_UPDATE_PREDICTION_ID", dest,"out_DECOD_UPT_"+toString(i)+"_UPDATE_PREDICTION_ID"); + COMPONENT_MAP(_component,src , "in_DECOD_" +toString(i)+"_IS_ACCURATE" , + dest,"out_DECOD_UPT_"+toString(i)+"_IS_ACCURATE" ); //out_DECOD_UPT_RAS_INDEX - component_map return_address_stack @@ -650,5 +656,5 @@ PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID" , dest, "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID" ); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" , dest, "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" ); @@ -684,6 +690,5 @@ for (uint32_t i=0; i<_param->_nb_context; i++) { - dest = _name+"_prediction_unit_glue"; - + dest = _name; #ifdef POSITION _component->interface_map (src ,"depth_"+toString(i), @@ -691,12 +696,31 @@ #endif - COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_NB_BRANCH", - dest, "in_DEPTH_"+toString(i)+"_UPT_NB_BRANCH"); - - if (_param->_have_port_depth[i]) - COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_TAIL" , - dest, "in_DEPTH_"+toString(i)+"_UPT_TAIL" ); - } - + if (_param->_have_port_depth) + { + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_CURRENT", + dest,"out_DEPTH_"+toString(i)+"_CURRENT"); + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MIN", + dest,"out_DEPTH_"+toString(i)+"_MIN"); + } + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MAX", + dest,"out_DEPTH_"+toString(i)+"_MAX"); + } + +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// dest = _name+"_prediction_unit_glue"; + +// #ifdef POSITION +// _component->interface_map (src ,"depth_"+toString(i), +// dest,"depth_"+toString(i)); +// #endif + +// COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_NB_BRANCH", +// dest, "in_DEPTH_"+toString(i)+"_UPT_NB_BRANCH"); + +// if (_param->_have_port_depth) +// COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_TAIL" , +// dest, "in_DEPTH_"+toString(i)+"_UPT_TAIL" ); +// } } @@ -741,10 +765,10 @@ PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_PC_NEXT_IS_DS_TAKE" , dest,"out_PREDICT_"+toString(i)+"_PC_NEXT_IS_DS_TAKE" ); - if (_param->_have_port_inst_ifetch_ptr [i]) + if (_param->_have_port_inst_ifetch_ptr) PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_INST_IFETCH_PTR" , dest,"out_PREDICT_"+toString(i)+"_INST_IFETCH_PTR" ); PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_BRANCH_STATE" , dest,"out_PREDICT_"+toString(i)+"_BRANCH_STATE" ); - if (_param->_have_port_depth [i]) + if (_param->_have_port_depth) PORT_MAP(_component,src ,"out_PREDICT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID", dest,"out_PREDICT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); @@ -783,5 +807,5 @@ PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_"+toString(j)+"_BRANCH_STATE" , dest, "in_DECOD_"+toString(i)+"_"+toString(j)+"_BRANCH_STATE" ); - if (_param->_have_port_max_depth) + if (_param->_have_port_depth) PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID", dest, "in_DECOD_"+toString(i)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID"); @@ -796,23 +820,26 @@ } - for (uint32_t i=0; i<_param->_nb_context; i++) - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"depth_"+toString(i), - dest,"depth_"+toString(i)); -#endif - - PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_NB_BRANCH",dest,"out_DEPTH_"+toString(i)+"_NB_BRANCH"); - if (_param->_have_port_depth[i]) - PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_TAIL" ,dest,"out_DEPTH_"+toString(i)+"_TAIL" ); - } +// for (uint32_t i=0; i<_param->_nb_context; i++) +// { +// dest = _name; +// #ifdef POSITION +// _component->interface_map (src ,"depth_"+toString(i), +// dest,"depth_"+toString(i)); +// #endif + +// PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_NB_BRANCH",dest,"out_DEPTH_"+toString(i)+"_NB_BRANCH"); +// if (_param->_have_port_depth) +// PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_TAIL" ,dest,"out_DEPTH_"+toString(i)+"_TAIL" ); +// } } // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _component->test_map(false); - -#ifdef POSITION - _component->generate_file(); +#if DEBUG_Prediction_unit == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Prediction_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -30,46 +30,47 @@ DELETE1_SIGNAL( in_PREDICT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_PREDICT_ACK ,_param->_nb_context,1); - DELETE1_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context,_param->_size_address); - DELETE1_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context,_param->_size_address); + DELETE1_SIGNAL( in_PREDICT_PC_PREVIOUS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_PREDICT_PC_CURRENT ,_param->_nb_context,_param->_size_instruction_address); DELETE1_SIGNAL( in_PREDICT_PC_CURRENT_IS_DS_TAKE ,_param->_nb_context,1); - DELETE1_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context,_param->_size_address); + DELETE1_SIGNAL(out_PREDICT_PC_NEXT ,_param->_nb_context,_param->_size_instruction_address); DELETE1_SIGNAL(out_PREDICT_PC_NEXT_IS_DS_TAKE ,_param->_nb_context,1); - DELETE1_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr [alloc_signal_it1]); + DELETE1_SIGNAL(out_PREDICT_INST_IFETCH_PTR ,_param->_nb_context,_param->_size_inst_ifetch_ptr); DELETE1_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_context,_param->_size_branch_state); - DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context,_param->_size_depth [alloc_signal_it1]); + DELETE1_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_context,_param->_size_depth ); - DELETE2_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[alloc_signal_it1],1); - DELETE2_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1); - DELETE2_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1); - DELETE2_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_context_id ); - DELETE2_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1 ); - DELETE2_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_branch_state ); - DELETE2_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_max_size_depth ); - DELETE2_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_branch_condition); - DELETE2_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],1 ); - DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_address ); - DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[alloc_signal_it1],_param->_size_address ); + DELETE2_SIGNAL(out_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_context,_param->_nb_instruction[it1],1); + DELETE2_SIGNAL( in_DECOD_VAL ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL(out_DECOD_ACK ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1); + DELETE2_SIGNAL( in_DECOD_CONTEXT_ID ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_DECOD_MATCH_INST_IFETCH_PTR ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_DECOD_BRANCH_STATE ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_branch_state ); + DELETE2_SIGNAL( in_DECOD_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_DECOD_BRANCH_CONDITION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_branch_condition); + DELETE2_SIGNAL( in_DECOD_BRANCH_DIRECTION ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_DECOD_ADDRESS_SRC ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); + DELETE2_SIGNAL( in_DECOD_ADDRESS_DEST ,_param->_nb_decod_unit,_param->_nb_inst_decod[it1],_param->_size_instruction_address ); DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_max_size_depth); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_address); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); DELETE1_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_address); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_address); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); -// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_max_size_depth); +// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context,1); - DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_address); - DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_address); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); - DELETE1_SIGNAL(out_DEPTH_NB_BRANCH ,_param->_nb_context,_param->_size_depth[alloc_signal_it1]+1); - DELETE1_SIGNAL(out_DEPTH_TAIL ,_param->_nb_context,_param->_size_depth[alloc_signal_it1]); + DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_end_cycle.cpp (revision 88) @@ -24,5 +24,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -30,5 +31,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_statistics_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_statistics_allocation.cpp (revision 88) @@ -26,5 +26,11 @@ "Prediction_unit", param_statistics); - + + _stat->add_stat(_component_btb ->_stat); + _stat->add_stat(_component_dir ->_stat); + _stat->add_stat(_component_ras ->_stat); + _stat->add_stat(_component_upt ->_stat); + _stat->add_stat(_component_glue->_stat); + log_printf(FUNC,Prediction_unit,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Front_end_LIBRARY) + +DIR_LIBRARY = $(Front_end_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Front_end_library + +library_clean : Front_end_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg (revision 88) @@ -0,0 +1,45 @@ +Front_end +1 1 +1 # nb_context +1 1 +1 # nb_decod_unit +32 32 +1 # size_general_data +4 4 +1 # size_ifetch_queue [0] [nb_context] +4 4 +1 # nb_inst_fetch [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +4 4 +1 # size_decod_queue [0] [nb_decod_unit] +4 4 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_context_select [0] [nb_decod_unit] +1 1 +1 # context_select_priority [0] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_predict +2 2 +1 # nb_inst_branch_decod +2 2 +1 # nb_inst_branch_update +2 2 +1 # nb_inst_branch_complete +32 32 +1 # btb_size_queue +4 4 +1 # btb_associativity +2 2 +1 # btb_size_counter +3 3 +1 # btb_victim_scheme +1 1 +1 # dir_predictor_scheme +1 1 +1 # dir_have_bht [0] [3] +1 1 +1 # dir_have_bht [1] [3] +1 1 +1 # dir_have_bht [2] [3] +1 1 +1 # dir_bht_size_shifter [0] [3] +1 1 +1 # dir_bht_size_shifter [1] [3] +1 1 +1 # dir_bht_size_shifter [2] [3] +1 1 +1 # dir_bht_nb_shifter [0] [3] +1 1 +1 # dir_bht_nb_shifter [1] [3] +1 1 +1 # dir_bht_nb_shifter [2] [3] +1 1 +1 # dir_have_pht [0] [3] +1 1 +1 # dir_have_pht [1] [3] +1 1 +1 # dir_have_pht [2] [3] +1 1 +1 # dir_pht_size_counter [0] [3] +1 1 +1 # dir_pht_size_counter [1] [3] +1 1 +1 # dir_pht_size_counter [2] [3] +1 1 +1 # dir_pht_nb_counter [0] [3] +1 1 +1 # dir_pht_nb_counter [1] [3] +1 1 +1 # dir_pht_nb_counter [2] [3] +1 1 +1 # dir_pht_size_address_share [0] [3] +1 1 +1 # dir_pht_size_address_share [1] [3] +1 1 +1 # dir_pht_size_address_share [2] [3] +8 8 +1 # ras_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # size_inst_commit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg (revision 88) @@ -0,0 +1,60 @@ +Front_end +4 4 +1 # nb_context +1 1 +1 # nb_decod_unit +32 32 +1 # size_general_data +4 4 +1 # size_ifetch_queue [0] [nb_context] +2 2 +1 # size_ifetch_queue [1] [nb_context] +1 1 +1 # size_ifetch_queue [2] [nb_context] +8 8 +1 # size_ifetch_queue [3] [nb_context] +4 4 +1 # nb_inst_fetch [0] [nb_context] +2 2 +1 # nb_inst_fetch [1] [nb_context] +16 16 +1 # nb_inst_fetch [2] [nb_context] +1 1 +1 # nb_inst_fetch [3] [nb_context] +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [1] [nb_context] +0 0 +1 # link_context_to_decod_unit [2] [nb_context] +0 0 +1 # link_context_to_decod_unit [3] [nb_context] +4 4 +1 # size_decod_queue [0] [nb_decod_unit] +4 4 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_context_select [0] [nb_decod_unit] +1 1 +1 # context_select_priority [0] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_predict +2 2 +1 # nb_inst_branch_decod +2 2 +1 # nb_inst_branch_update +2 2 +1 # nb_inst_branch_complete +64 64 +1 # btb_size_queue +8 8 +1 # btb_associativity +2 2 +1 # btb_size_counter +3 3 +1 # btb_victim_scheme +1 1 +1 # dir_predictor_scheme +1 1 +1 # dir_have_bht [0] [3] +1 1 +1 # dir_have_bht [1] [3] +1 1 +1 # dir_have_bht [2] [3] +1 1 +1 # dir_bht_size_shifter [0] [3] +1 1 +1 # dir_bht_size_shifter [1] [3] +1 1 +1 # dir_bht_size_shifter [2] [3] +1 1 +1 # dir_bht_nb_shifter [0] [3] +1 1 +1 # dir_bht_nb_shifter [1] [3] +1 1 +1 # dir_bht_nb_shifter [2] [3] +1 1 +1 # dir_have_pht [0] [3] +1 1 +1 # dir_have_pht [1] [3] +1 1 +1 # dir_have_pht [2] [3] +1 1 +1 # dir_pht_size_counter [0] [3] +1 1 +1 # dir_pht_size_counter [1] [3] +1 1 +1 # dir_pht_size_counter [2] [3] +1 1 +1 # dir_pht_nb_counter [0] [3] +1 1 +1 # dir_pht_nb_counter [1] [3] +1 1 +1 # dir_pht_nb_counter [2] [3] +1 1 +1 # dir_pht_size_address_share [0] [3] +1 1 +1 # dir_pht_size_address_share [1] [3] +1 1 +1 # dir_pht_size_address_share [2] [3] +8 8 +1 # ras_size_queue [0] [nb_context] +2 2 +1 # ras_size_queue [1] [nb_context] +4 4 +1 # ras_size_queue [2] [nb_context] +2 2 +1 # ras_size_queue [3] [nb_context] +16 16 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [1] [nb_context] +2 2 +1 # upt_size_queue [2] [nb_context] +8 8 +1 # upt_size_queue [3] [nb_context] +1 1 +1 # size_inst_commit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 88) @@ -0,0 +1,65 @@ +Front_end +4 4 +1 # nb_context +2 2 +1 # nb_decod_unit +32 32 +1 # size_general_data +4 4 +1 # size_ifetch_queue [0] [nb_context] +2 2 +1 # size_ifetch_queue [1] [nb_context] +1 1 +1 # size_ifetch_queue [2] [nb_context] +8 8 +1 # size_ifetch_queue [3] [nb_context] +4 4 +1 # nb_inst_fetch [0] [nb_context] +2 2 +1 # nb_inst_fetch [1] [nb_context] +16 16 +1 # nb_inst_fetch [2] [nb_context] +1 1 +1 # nb_inst_fetch [3] [nb_context] +1 1 +1 # link_context_to_decod_unit [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [1] [nb_context] +1 1 +1 # link_context_to_decod_unit [2] [nb_context] +1 1 +1 # link_context_to_decod_unit [3] [nb_context] +4 4 +1 # size_decod_queue [0] [nb_decod_unit] +12 12 +1 # size_decod_queue [1] [nb_decod_unit] +2 2 +1 # nb_inst_decod [0] [nb_decod_unit] +6 6 +1 # nb_inst_decod [1] [nb_decod_unit] +1 1 +1 # nb_context_select [0] [nb_decod_unit] +1 3 *3 # nb_context_select [1] [nb_decod_unit] +1 1 +1 # context_select_priority [0] [nb_decod_unit] +1 1 +1 # context_select_priority [1] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [0] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [1] [nb_decod_unit] +1 1 +1 # nb_inst_branch_predict +2 2 +1 # nb_inst_branch_decod +2 2 +1 # nb_inst_branch_update +2 2 +1 # nb_inst_branch_complete +64 64 +1 # btb_size_queue +8 8 +1 # btb_associativity +2 2 +1 # btb_size_counter +3 3 +1 # btb_victim_scheme +1 1 +1 # dir_predictor_scheme +1 1 +1 # dir_have_bht [0] [3] +1 1 +1 # dir_have_bht [1] [3] +1 1 +1 # dir_have_bht [2] [3] +1 1 +1 # dir_bht_size_shifter [0] [3] +1 1 +1 # dir_bht_size_shifter [1] [3] +1 1 +1 # dir_bht_size_shifter [2] [3] +1 1 +1 # dir_bht_nb_shifter [0] [3] +1 1 +1 # dir_bht_nb_shifter [1] [3] +1 1 +1 # dir_bht_nb_shifter [2] [3] +1 1 +1 # dir_have_pht [0] [3] +1 1 +1 # dir_have_pht [1] [3] +1 1 +1 # dir_have_pht [2] [3] +1 1 +1 # dir_pht_size_counter [0] [3] +1 1 +1 # dir_pht_size_counter [1] [3] +1 1 +1 # dir_pht_size_counter [2] [3] +1 1 +1 # dir_pht_nb_counter [0] [3] +1 1 +1 # dir_pht_nb_counter [1] [3] +1 1 +1 # dir_pht_nb_counter [2] [3] +1 1 +1 # dir_pht_size_address_share [0] [3] +1 1 +1 # dir_pht_size_address_share [1] [3] +1 1 +1 # dir_pht_size_address_share [2] [3] +8 8 +1 # ras_size_queue [0] [nb_context] +2 2 +1 # ras_size_queue [1] [nb_context] +4 4 +1 # ras_size_queue [2] [nb_context] +2 2 +1 # ras_size_queue [3] [nb_context] +16 16 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [1] [nb_context] +2 2 +1 # upt_size_queue [2] [nb_context] +8 8 +1 # upt_size_queue [3] [nb_context] +1 1 +1 # size_inst_commit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 88) @@ -0,0 +1,65 @@ +Front_end +4 4 +1 # nb_context +2 2 +1 # nb_decod_unit +32 32 +1 # size_general_data +4 4 +1 # size_ifetch_queue [0] [nb_context] +2 2 +1 # size_ifetch_queue [1] [nb_context] +1 1 +1 # size_ifetch_queue [2] [nb_context] +8 8 +1 # size_ifetch_queue [3] [nb_context] +4 4 +1 # nb_inst_fetch [0] [nb_context] +2 2 +1 # nb_inst_fetch [1] [nb_context] +16 16 +1 # nb_inst_fetch [2] [nb_context] +1 1 +1 # nb_inst_fetch [3] [nb_context] +1 1 +1 # link_context_to_decod_unit [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [1] [nb_context] +1 1 +1 # link_context_to_decod_unit [2] [nb_context] +1 1 +1 # link_context_to_decod_unit [3] [nb_context] +4 4 +1 # size_decod_queue [0] [nb_decod_unit] +12 12 +1 # size_decod_queue [1] [nb_decod_unit] +2 2 +1 # nb_inst_decod [0] [nb_decod_unit] +6 6 +1 # nb_inst_decod [1] [nb_decod_unit] +1 1 +1 # nb_context_select [0] [nb_decod_unit] +3 3 *3 # nb_context_select [1] [nb_decod_unit] +1 1 +1 # context_select_priority [0] [nb_decod_unit] +1 1 +1 # context_select_priority [1] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [0] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [1] [nb_decod_unit] +1 1 +1 # nb_inst_branch_predict +2 2 +1 # nb_inst_branch_decod +2 2 +1 # nb_inst_branch_update +2 2 +1 # nb_inst_branch_complete +64 64 +1 # btb_size_queue +8 8 +1 # btb_associativity +2 2 +1 # btb_size_counter +3 3 +1 # btb_victim_scheme +1 1 +1 # dir_predictor_scheme +1 1 +1 # dir_have_bht [0] [3] +1 1 +1 # dir_have_bht [1] [3] +1 1 +1 # dir_have_bht [2] [3] +1 1 +1 # dir_bht_size_shifter [0] [3] +1 1 +1 # dir_bht_size_shifter [1] [3] +1 1 +1 # dir_bht_size_shifter [2] [3] +1 1 +1 # dir_bht_nb_shifter [0] [3] +1 1 +1 # dir_bht_nb_shifter [1] [3] +1 1 +1 # dir_bht_nb_shifter [2] [3] +1 1 +1 # dir_have_pht [0] [3] +1 1 +1 # dir_have_pht [1] [3] +1 1 +1 # dir_have_pht [2] [3] +1 1 +1 # dir_pht_size_counter [0] [3] +1 1 +1 # dir_pht_size_counter [1] [3] +1 1 +1 # dir_pht_size_counter [2] [3] +1 1 +1 # dir_pht_nb_counter [0] [3] +1 1 +1 # dir_pht_nb_counter [1] [3] +1 1 +1 # dir_pht_nb_counter [2] [3] +1 1 +1 # dir_pht_size_address_share [0] [3] +1 1 +1 # dir_pht_size_address_share [1] [3] +1 1 +1 # dir_pht_size_address_share [2] [3] +8 8 +1 # ras_size_queue [0] [nb_context] +2 2 +1 # ras_size_queue [1] [nb_context] +4 4 +1 # ras_size_queue [2] [nb_context] +2 2 +1 # ras_size_queue [3] [nb_context] +16 16 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [1] [nb_context] +2 2 +1 # upt_size_queue [2] [nb_context] +8 8 +1 # upt_size_queue [3] [nb_context] +1 1 +1 # size_inst_commit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,45 @@ +Front_end +1 1 +1 # nb_context +1 1 +1 # nb_decod_unit +32 32 +1 # size_general_data +1 1 +1 # size_ifetch_queue [0] [nb_context] +1 1 +1 # nb_inst_fetch [0] [nb_context] +0 0 +1 # link_context_to_decod_unit [0] [nb_context] +1 1 +1 # size_decod_queue [0] [nb_decod_unit] +1 1 +1 # nb_inst_decod [0] [nb_decod_unit] +1 1 +1 # nb_context_select [0] [nb_decod_unit] +1 1 +1 # context_select_priority [0] [nb_decod_unit] +1 1 +1 # context_select_load_balancing [0] [nb_decod_unit] +1 1 +1 # nb_inst_branch_predict +1 1 +1 # nb_inst_branch_decod +1 1 +1 # nb_inst_branch_update +1 1 +1 # nb_inst_branch_complete +1 1 +1 # btb_size_queue +1 1 +1 # btb_associativity +2 2 +1 # btb_size_counter +1 1 +1 # btb_victim_scheme +1 1 +1 # dir_predictor_scheme +1 1 +1 # dir_have_bht [0] [3] +1 1 +1 # dir_have_bht [1] [3] +1 1 +1 # dir_have_bht [2] [3] +1 1 +1 # dir_bht_size_shifter [0] [3] +1 1 +1 # dir_bht_size_shifter [1] [3] +1 1 +1 # dir_bht_size_shifter [2] [3] +1 1 +1 # dir_bht_nb_shifter [0] [3] +1 1 +1 # dir_bht_nb_shifter [1] [3] +1 1 +1 # dir_bht_nb_shifter [2] [3] +1 1 +1 # dir_have_pht [0] [3] +1 1 +1 # dir_have_pht [1] [3] +1 1 +1 # dir_have_pht [2] [3] +1 1 +1 # dir_pht_size_counter [0] [3] +1 1 +1 # dir_pht_size_counter [1] [3] +1 1 +1 # dir_pht_size_counter [2] [3] +1 1 +1 # dir_pht_nb_counter [0] [3] +1 1 +1 # dir_pht_nb_counter [1] [3] +1 1 +1 # dir_pht_nb_counter [2] [3] +1 1 +1 # dir_pht_size_address_share [0] [3] +1 1 +1 # dir_pht_size_address_share [1] [3] +1 1 +1 # dir_pht_size_address_share [2] [3] +2 2 +1 # ras_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # size_inst_commit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h (revision 88) @@ -0,0 +1,33 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_front_end; + +using namespace morpheo::behavioural::core::multi_front_end::front_end; + +void test (string name, + morpheo::behavioural::core::multi_front_end::front_end::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,248 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h" +#include "Behavioural/Custom/include/Custom_example.h" + +#define NB_PARAMS 13+7*3 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_context (uint32_t )\n")); + err (_(" * nb_decod_unit (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_ifetch_queue [nb_context] (uint32_t )\n")); + err (_(" * nb_inst_fetch [nb_context] (uint32_t )\n")); + err (_(" * link_context_to_decod_unit [nb_context] (uint32_t )\n")); + err (_(" * size_decod_queue [nb_decod_unit] (uint32_t )\n")); + err (_(" * nb_inst_decod [nb_decod_unit] (uint32_t )\n")); + err (_(" * nb_context_select [nb_decod_unit] (uint32_t )\n")); + err (_(" * context_select_priority [nb_decod_unit] (Tpriority_t )\n")); + err (_(" * context_select_load_balancing [nb_decod_unit] (Tload_balancing_t)\n")); + err (_(" * nb_inst_branch_predict (uint32_t )\n")); + err (_(" * nb_inst_branch_decod (uint32_t )\n")); + err (_(" * nb_inst_branch_update (uint32_t )\n")); + err (_(" * nb_inst_branch_complete (uint32_t )\n")); + err (_(" * btb_size_queue (uint32_t )\n")); + err (_(" * btb_associativity (uint32_t )\n")); + err (_(" * btb_size_counter (uint32_t )\n")); + err (_(" * btb_victim_scheme (Tvictim_t )\n")); + err (_(" * dir_predictor_scheme (Tpredictor_t )\n")); + err (_(" * dir_have_bht [3] (bool )\n")); + err (_(" * dir_bht_size_shifter [3] (uint32_t )\n")); + err (_(" * dir_bht_nb_shifter [3] (uint32_t )\n")); + err (_(" * dir_have_pht [3] (bool )\n")); + err (_(" * dir_pht_size_counter [3] (uint32_t )\n")); + err (_(" * dir_pht_nb_counter [3] (uint32_t )\n")); + err (_(" * dir_pht_size_address_share [3] (uint32_t )\n")); + err (_(" * ras_size_queue [nb_context] (uint32_t )\n")); + err (_(" * upt_size_queue [nb_context] (uint32_t )\n")); + err (_(" * size_inst_commit (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + for (int32_t i=0; i(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_context = fromString(argv[x++]); + uint32_t _nb_decod_unit = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+5*_nb_context+5*_nb_decod_unit)) + { + msg("argc : %d\n",argc); + msg("all : %d\n",(2+NB_PARAMS+5*_nb_context+5*_nb_decod_unit)); + msg("_nb_context : %d\n",_nb_context); + msg("_nb_decod_unit : %d\n",_nb_decod_unit); + usage (argc, argv); + } + + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t * _size_ifetch_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _size_ifetch_queue [i] = fromString(argv[x++]); + + uint32_t * _nb_inst_fetch = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _nb_inst_fetch [i] = fromString(argv[x++]); + + bool ** _instruction_implemeted = new bool * [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + { + _instruction_implemeted [i] = new bool [NB_INSTRUCTION]; + for (uint32_t j=0; j(argv[x++]); + } + + uint32_t * _link_context_to_decod_unit = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _link_context_to_decod_unit [i] = fromString(argv[x++]); + + uint32_t * _size_decod_queue = new uint32_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _size_decod_queue [i] = fromString(argv[x++]); + + uint32_t * _nb_inst_decod = new uint32_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _nb_inst_decod [i] = fromString(argv[x++]); + + uint32_t * _nb_context_select = new uint32_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _nb_context_select [i] = fromString(argv[x++]); + + Tpriority_t * _context_select_priority = new Tpriority_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _context_select_priority [i] = fromString(argv[x++]); + + Tload_balancing_t * _context_select_load_balancing = new Tload_balancing_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + _context_select_load_balancing [i] = fromString(argv[x++]); + + uint32_t _nb_inst_branch_predict = fromString(argv[x++]); + uint32_t _nb_inst_branch_decod = fromString(argv[x++]); + uint32_t _nb_inst_branch_update = fromString(argv[x++]); + uint32_t _nb_inst_branch_complete = fromString(argv[x++]); + uint32_t _btb_size_queue = fromString(argv[x++]); + uint32_t _btb_associativity = fromString(argv[x++]); + uint32_t _btb_size_counter = fromString(argv[x++]); + Tvictim_t _btb_victim_scheme = fromString(argv[x++]); + Tpredictor_t _dir_predictor_scheme = fromString(argv[x++]); + bool * _dir_have_bht = new bool [3]; + uint32_t * _dir_bht_size_shifter = new uint32_t[3]; + uint32_t * _dir_bht_nb_shifter = new uint32_t[3]; + bool * _dir_have_pht = new bool [3]; + uint32_t * _dir_pht_size_counter = new uint32_t[3]; + uint32_t * _dir_pht_nb_counter = new uint32_t[3]; + uint32_t * _dir_pht_size_address_share = new uint32_t[3]; + + for (uint32_t i=0; i<3; i++) + _dir_have_bht [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_bht_size_shifter [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_bht_nb_shifter [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_have_pht [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_pht_size_counter [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_pht_nb_counter [i] = fromString(argv[x++]); + for (uint32_t i=0; i<3; i++) + _dir_pht_size_address_share [i] = fromString(argv[x++]); + + uint32_t * _ras_size_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _ras_size_queue [i] = fromString(argv[x++]); + + uint32_t * _upt_size_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _upt_size_queue [i] = fromString(argv[x++]); + + uint32_t _size_inst_commit = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_front_end::front_end::Parameters * param = new morpheo::behavioural::core::multi_front_end::front_end::Parameters + ( + _nb_context , + _nb_decod_unit , + _size_general_data , + &(morpheo::behavioural::custom::example_get_custom_information), + _size_ifetch_queue , + _nb_inst_fetch , + _instruction_implemeted , + _link_context_to_decod_unit , + _size_decod_queue , + _nb_inst_decod , + _nb_context_select , + _context_select_priority , + _context_select_load_balancing , + _nb_inst_branch_predict , + _nb_inst_branch_decod , + _nb_inst_branch_update , + _nb_inst_branch_complete , + _btb_size_queue , + _btb_associativity , + _btb_size_counter , + _btb_victim_scheme , + _dir_predictor_scheme , + _dir_have_bht , + _dir_bht_size_shifter , + _dir_bht_nb_shifter , + _dir_have_pht , + _dir_pht_size_counter , + _dir_pht_nb_counter , + _dir_pht_size_address_share , + _ras_size_queue , + _upt_size_queue , + _size_inst_commit , + true // is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("%s\n"),error.what()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Front_end : no error"); + else + TEST_KO("Front_end : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _dir_have_bht ; + delete [] _dir_bht_size_shifter ; + delete [] _dir_bht_nb_shifter ; + delete [] _dir_have_pht ; + delete [] _dir_pht_size_counter ; + delete [] _dir_pht_nb_counter ; + delete [] _dir_pht_size_address_share ; + delete [] _upt_size_queue ; + delete [] _ras_size_queue ; + delete [] _context_select_load_balancing ; + delete [] _context_select_priority ; + delete [] _nb_context_select ; + delete [] _nb_inst_decod ; + delete [] _size_decod_queue ; + delete [] _link_context_to_decod_unit ; + for (uint32_t i=0; i<_nb_context; ++i) + delete [] _instruction_implemeted [i]; + delete [] _instruction_implemeted ; + delete [] _nb_inst_fetch ; + delete [] _size_ifetch_queue ; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,371 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_front_end::front_end::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Front_end * _Front_end = new Front_end + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_context); +//ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_instruction_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_context); +//ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_context); + ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_context,_param->_nb_inst_fetch[it1]); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_sum_inst_decod); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); + ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Front_end.\n"),name.c_str()); + + (*(_Front_end->in_CLOCK)) (*(in_CLOCK)); + (*(_Front_end->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_REQ_ACK ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_THREAD_ID ,_param->_nb_context); + if (_param->_have_port_ifetch_queue_ptr) + INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_PACKET_ID ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_ADDRESS ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_REQ_TYPE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_ICACHE_RSP_ACK ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_THREAD_ID ,_param->_nb_context); + if (_param->_have_port_ifetch_queue_ptr) + INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_PACKET_ID ,_param->_nb_context); + INSTANCE2_SC_SIGNAL(_Front_end, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + INSTANCE1_SC_SIGNAL(_Front_end, in_ICACHE_RSP_ERROR ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_VAL ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end, in_DECOD_ACK ,_param->_sum_inst_decod); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_DEPTH ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_TYPE ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_OPERATION ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_ADDRESS ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RA ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RB ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_READ_RC ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RD ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_WRITE_RE ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end,out_DECOD_EXCEPTION ,_param->_sum_inst_decod); + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL ); + INSTANCE0_SC_SIGNAL(_Front_end,out_COMMIT_EVENT_ACK ); + if (_param->_have_port_context_id) + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_CONTEXT_ID ); + if (_param->_have_port_depth) + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_DEPTH ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_TYPE ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_IS_DELAY_SLOT ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EPCR ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_ADDRESS_EEAR ); + INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_EVENT_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_EVENT_IS_DS_TAKE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_EVENT_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EPCR ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_EEAR ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_DSX ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_ALL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_NB_INST_COMMIT_MEM ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MIN ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end,out_DEPTH_MAX ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_IEE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_SPR_SR_EPH ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end, in_INTERRUPT_ENABLE ,_param->_nb_context); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + in_ICACHE_REQ_ACK [i]->write(0); + in_ICACHE_RSP_VAL [i]->write(0); + in_EVENT_ACK [i]->write(0); + in_SPR_EVENT_ACK [i]->write(0); + in_NB_INST_COMMIT_ALL [i]->write(0); // no inst + in_NB_INST_COMMIT_MEM [i]->write(0); // no inst + in_SPR_SR_IEE [i]->write(0); // interrupt disable + in_SPR_SR_EPH [i]->write(0); // exception msb = 0 + in_INTERRUPT_ENABLE [i]->write(0); // no interrupt + } + for (uint32_t i=0; i<_param->_sum_inst_decod; ++i) + in_DECOD_ACK [i]->write(0); + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + in_BRANCH_COMPLETE_VAL [i]->write(0); + in_COMMIT_EVENT_VAL->write(0); + + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + TEST(Tcontrol_t,out_ICACHE_REQ_VAL [i]->read(),0); + TEST(Tcontrol_t,out_ICACHE_RSP_ACK [i]->read(),1); // Can accept a respons + TEST(Tcontrol_t,out_EVENT_VAL [i]->read(),0); + TEST(Tcontrol_t,out_SPR_EVENT_VAL [i]->read(),0); + TEST(Tdepth_t ,out_DEPTH_MIN [i]->read(),0); // no branch speculated + TEST(Tdepth_t ,out_DEPTH_MAX [i]->read(),0); // no branch speculated + } + for (uint32_t i=0; i<_param->_sum_inst_decod; ++i) + TEST(Tcontrol_t,out_DECOD_VAL [i]->read(),0); + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + TEST(Tcontrol_t,out_BRANCH_COMPLETE_ACK [i]->read(),0); // can't accept (interactive) + TEST(Tcontrol_t,out_COMMIT_EVENT_ACK ->read(),1); // can accept + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context); +//DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context); +//DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context); + DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL ); + DELETE0_SC_SIGNAL(out_COMMIT_EVENT_ACK ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_TYPE ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + DELETE0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ); + DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_DEPTH_MAX ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context); + } +#endif + + delete _Front_end; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Front_end.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Front_end.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Front_end.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Front_end} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 88) @@ -0,0 +1,232 @@ +#ifndef morpheo_behavioural_core_multi_front_end_front_end_Front_end_h +#define morpheo_behavioural_core_multi_front_end_front_end_Front_end_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" +#include "Behavioural/include/Types.h" + +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Decod_unit.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_front_end { +namespace front_end { + + + class Front_end +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t ) * in_NRESET ; + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_REQ_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_ICACHE_REQ_ACK ;//[nb_context] +//public : SC_OUT(Tcontext_t ) ** out_ICACHE_REQ_THREAD_ID ;//[nb_context] + public : SC_OUT(Tpacket_t ) ** out_ICACHE_REQ_PACKET_ID ;//[nb_context] + public : SC_OUT(Ticache_instruction_t) ** out_ICACHE_REQ_ADDRESS ;//[nb_context] + public : SC_OUT(Ticache_type_t ) ** out_ICACHE_REQ_TYPE ;//[nb_context] + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_ICACHE_RSP_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_RSP_ACK ;//[nb_context] +//public : SC_IN (Tcontext_t ) ** in_ICACHE_RSP_THREAD_ID ;//[nb_context] + public : SC_IN (Tpacket_t ) ** in_ICACHE_RSP_PACKET_ID ;//[nb_context] + public : SC_IN (Ticache_instruction_t)*** in_ICACHE_RSP_INSTRUCTION ;//[nb_context][nb_inst_fetch] + public : SC_IN (Ticache_error_t ) ** in_ICACHE_RSP_ERROR ;//[nb_context] + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DECOD_VAL ;//[sum_inst_decod] + public : SC_IN (Tcontrol_t ) ** in_DECOD_ACK ;//[sum_inst_decod] + public : SC_OUT(Tcontext_t ) ** out_DECOD_CONTEXT_ID ;//[sum_inst_decod] + public : SC_OUT(Tdepth_t ) ** out_DECOD_DEPTH ;//[sum_inst_decod] + public : SC_OUT(Ttype_t ) ** out_DECOD_TYPE ;//[sum_inst_decod] + public : SC_OUT(Toperation_t ) ** out_DECOD_OPERATION ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_NO_EXECUTE ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_IS_DELAY_SLOT ;//[sum_inst_decod] + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_ADDRESS ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_HAS_IMMEDIAT ;//[sum_inst_decod] + public : SC_OUT(Tgeneral_data_t ) ** out_DECOD_IMMEDIAT ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_READ_RA ;//[sum_inst_decod] + public : SC_OUT(Tgeneral_address_t ) ** out_DECOD_NUM_REG_RA ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_READ_RB ;//[sum_inst_decod] + public : SC_OUT(Tgeneral_address_t ) ** out_DECOD_NUM_REG_RB ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_READ_RC ;//[sum_inst_decod] + public : SC_OUT(Tspecial_address_t ) ** out_DECOD_NUM_REG_RC ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_WRITE_RD ;//[sum_inst_decod] + public : SC_OUT(Tgeneral_address_t ) ** out_DECOD_NUM_REG_RD ;//[sum_inst_decod] + public : SC_OUT(Tcontrol_t ) ** out_DECOD_WRITE_RE ;//[sum_inst_decod] + public : SC_OUT(Tspecial_address_t ) ** out_DECOD_NUM_REG_RE ;//[sum_inst_decod] + public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION_USE ;//[sum_inst_decod] + public : SC_OUT(Texception_t ) ** out_DECOD_EXCEPTION ;//[sum_inst_decod] + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] + public : SC_IN (Tcontext_t ) ** in_BRANCH_COMPLETE_CONTEXT_ID ;//[nb_inst_branch_complete] + public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] + public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_VAL ; + public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ACK ; + public : SC_IN (Tcontext_t ) * in_COMMIT_EVENT_CONTEXT_ID ; + public : SC_IN (Tdepth_t ) * in_COMMIT_EVENT_DEPTH ; + public : SC_IN (Tevent_type_t ) * in_COMMIT_EVENT_TYPE ; + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_IS_DELAY_SLOT ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; + public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_EVENT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_ACK ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_ADDRESS ;//[nb_context] + public : SC_OUT(Taddress_t ) ** out_EVENT_ADDRESS_NEXT ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_ADDRESS_NEXT_VAL ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_IS_DS_TAKE ;//[nb_context] + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_SPR_EVENT_ACK ;//[nb_context] + public : SC_OUT(Tspr_t ) ** out_SPR_EVENT_EPCR ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_EEAR_WEN ;//[nb_context] + public : SC_OUT(Tspr_t ) ** out_SPR_EVENT_EEAR ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_SR_DSX ;//[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_SPR_EVENT_SR_TO_ESR ;//[nb_context] + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_ALL ;//[nb_context] + public : SC_IN (Tcounter_t ) ** in_NB_INST_COMMIT_MEM ;//[nb_context] + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MIN ;//[nb_context] + public : SC_OUT(Tdepth_t ) ** out_DEPTH_MAX ;//[nb_context] + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_SPR_SR_IEE ;//[nb_context] - Interrupt Exception Enabled + public : SC_IN (Tcontrol_t ) ** in_SPR_SR_EPH ;//[nb_context] - Exception Prefix High + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_INTERRUPT_ENABLE ;//[nb_context] - Interrupt Exception + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : behavioural::core::multi_front_end::front_end::ifetch_unit ::Ifetch_unit ** _component_ifetch_unit ; + public : behavioural::core::multi_front_end::front_end::prediction_unit::Prediction_unit * _component_prediction_unit; + public : behavioural::core::multi_front_end::front_end::decod_unit ::Decod_unit ** _component_decod_unit ; + public : behavioural::core::multi_front_end::front_end::context_state ::Context_State * _component_context_state ; + public : behavioural::core::multi_front_end::front_end::front_end_glue ::Front_end_Glue * _component_glue ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Front_end); +#endif + public : Front_end + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Front_end (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +# endif +#endif + +#if VHDL + public : void vhdl (void); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 88) @@ -0,0 +1,157 @@ +#ifndef morpheo_behavioural_core_multi_front_end_front_end_Parameters_h +#define morpheo_behavioural_core_multi_front_end_front_end_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" +#include "Behavioural/include/Types.h" +#include "Behavioural/Custom/include/Custom.h" + +#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Parameters.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_context ; + public : uint32_t _nb_decod_unit ; +//public : uint32_t _size_general_data ; + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); + // ifetch_unit + public : uint32_t * _size_ifetch_queue ;//[nb_context] + public : uint32_t * _nb_inst_fetch ;//[nb_context] + public : bool ** _instruction_implemeted ;//[nb_context][nb_inst_fetch] + public : uint32_t * _link_context_to_decod_unit ;//[nb_context] + // decod_unit + public : uint32_t * _size_decod_queue ;//[nb_decod_unit] + public : uint32_t * _nb_inst_decod ;//[nb_decod_unit] + public : uint32_t * _nb_context_select ;//[nb_decod_unit] + public : Tpriority_t * _context_select_priority ;//[nb_decod_unit] + public : Tload_balancing_t * _context_select_load_balancing ;//[nb_decod_unit] + // prediction_unit + public : uint32_t _nb_inst_branch_predict ; + public : uint32_t _nb_inst_branch_decod ; + public : uint32_t _nb_inst_branch_update ; + public : uint32_t _nb_inst_branch_complete ; + public : uint32_t _btb_size_queue ; + public : uint32_t _btb_associativity ; + public : uint32_t _btb_size_counter ; + public : Tvictim_t _btb_victim_scheme ; + public : Tpredictor_t _dir_predictor_scheme ; + public : bool _dir_have_bht [3] ; + public : uint32_t _dir_bht_size_shifter [3] ; + public : uint32_t _dir_bht_nb_shifter [3] ; + public : bool _dir_have_pht [3] ; + public : uint32_t _dir_pht_size_counter [3] ; + public : uint32_t _dir_pht_nb_counter [3] ; + public : uint32_t _dir_pht_size_address_share [3] ; + public : uint32_t * _ras_size_queue ;//[nb_context] + public : uint32_t * _upt_size_queue ;//[nb_context] + // context_state +//public : uint32_t _size_nb_inst_commit ; + + public : std::vector * _translate_context_id_from_decod_unit ;//[nb_decod_unit] + public : uint32_t * _decod_unit_nb_context ;//[nb_decod_unit] + public : uint32_t ** _decod_unit_nb_inst_fetch ;//[nb_decod_unit][decod_unit_nb_context] + public : uint32_t ** _decod_unit_nb_branch_speculated ;//[nb_decod_unit][decod_unit_nb_context] +//public : uint32_t ** _decod_unit_depth ;//[nb_decod_unit][decod_unit_nb_context] + public : bool *** _decod_unit_instruction_implemeted ;//[nb_decod_unit][decod_unit_nb_context][nb_instruction] + public : uint32_t _sum_inst_decod ; + +//public : uint32_t _size_context_id ; +//public : uint32_t _size_address ; + public : uint32_t * _array_size_nb_inst_decod ;//[nb_decod_unit] + public : uint32_t * _array_size_depth ;//[nb_context] +//public : uint32_t _max_size_depth ; +//public : uint32_t * _size_ifetch_queue_ptr ;//[nb_context] + +//public : bool * _have_port_decod_unit_context_id ;//[nb_decod_unit] +//public : bool _have_port_context_id ; +//public : bool * _have_port_ifetch_queue_ptr ;//[nb_context] +//public : bool * _have_port_depth ;//[nb_context] +//public : bool _have_port_max_depth ; +//public : bool * _have_port_instruction_ptr ;//[nb_context] +//public : bool * _have_port_branch_update_prediction_id;//[nb_context] + + public : behavioural::core::multi_front_end::front_end::ifetch_unit:: Parameters ** _param_ifetch_unit ; + public : behavioural::core::multi_front_end::front_end::prediction_unit::Parameters * _param_prediction_unit; + public : behavioural::core::multi_front_end::front_end::decod_unit:: Parameters ** _param_decod_unit ; + public : behavioural::core::multi_front_end::front_end::context_state:: Parameters * _param_context_state ; + public : behavioural::core::multi_front_end::front_end::front_end_glue:: Parameters * _param_glue ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_context , + uint32_t nb_decod_unit , + uint32_t size_general_data , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + // ifetch_unit + uint32_t * size_ifetch_queue , + uint32_t * nb_inst_fetch , + bool ** instruction_implemeted , + uint32_t * link_context_to_decod_unit , + // decod_unit + uint32_t * size_decod_queue , + uint32_t * nb_inst_decod , + uint32_t * nb_context_select , + Tpriority_t * context_select_priority , + Tload_balancing_t * context_select_load_balancing , + // prediction_unit + uint32_t nb_inst_branch_predict , + uint32_t nb_inst_branch_decod , + uint32_t nb_inst_branch_update , + uint32_t nb_inst_branch_complete , + uint32_t btb_size_queue , + uint32_t btb_associativity , + uint32_t btb_size_counter , + Tvictim_t btb_victim_scheme , + Tpredictor_t dir_predictor_scheme , + bool * dir_have_bht ,//[3] + uint32_t * dir_bht_size_shifter ,//[3] + uint32_t * dir_bht_nb_shifter ,//[3] + bool * dir_have_pht ,//[3] + uint32_t * dir_pht_size_counter ,//[3] + uint32_t * dir_pht_nb_counter ,//[3] + uint32_t * dir_pht_size_address_share ,//[3] + uint32_t * ras_size_queue , + uint32_t * upt_size_queue , + // context_state + uint32_t size_nb_inst_commit , + + bool is_toplevel=false); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_front_end::front_end::Parameters & x); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end.cpp (revision 88) @@ -0,0 +1,115 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::Front_end" + Front_end::Front_end + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_front_end::front_end::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Front_end,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Front_end,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Front_end::~Front_end" + Front_end::~Front_end (void) + { + log_begin(Front_end,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 88) @@ -0,0 +1,1184 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + + +#undef FUNCTION +#define FUNCTION "Front_end::allocation" + void Front_end::allocation + ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Front_end,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Front_end" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request."),_param->_nb_context); + + ALLOC1_VALACK_OUT (out_ICACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); +// ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); + ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT (out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_context); + + ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); +// ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error ); + } + { + ALLOC2_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_context,_param->_nb_inst_fetch[it1]); + + _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction" ,Ticache_instruction_t,_param->_size_instruction ,_param->_nb_context,_param->_nb_inst_fetch[it1]); + } + + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("decod",OUT,EAST,_("Decoded instruction, send to ooo_engine"),_param->_sum_inst_decod); + + ALLOC1_VALACK_OUT (out_DECOD_VAL , VAL); + ALLOC1_VALACK_IN ( in_DECOD_ACK , ACK); + ALLOC1_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT (out_DECOD_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_DECOD_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT (out_DECOD_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT (out_DECOD_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT (out_DECOD_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT (out_DECOD_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t ,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT (out_DECOD_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t ,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT (out_DECOD_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t ,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT (out_DECOD_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t ,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT (out_DECOD_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_DECOD_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t ,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT (out_DECOD_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_OUT (out_DECOD_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("branch_complete",IN,EAST,_("Branch commit"),_param->_nb_inst_branch_complete); + + ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_VAL , VAL); + ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_ACK , ACK); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"FLAG" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); + } + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC_INTERFACE("commit_event",IN,EAST,_("Out Of Order engine have an event")); + + ALLOC_VALACK_IN ( in_COMMIT_EVENT_VAL , VAL); + ALLOC_VALACK_OUT (out_COMMIT_EVENT_ACK , ACK); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_instruction_address ); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("event",OUT,EAST,_("Event interface"),_param->_nb_context); + + ALLOC1_VALACK_OUT (out_EVENT_VAL , VAL); + ALLOC1_VALACK_IN ( in_EVENT_ACK , ACK); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT (out_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1 ); + } + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr_event",OUT,EAST,_("Event interface with the special registerFile"),_param->_nb_context); + + ALLOC1_VALACK_OUT (out_SPR_EVENT_VAL , VAL); + ALLOC1_VALACK_IN ( in_SPR_EVENT_ACK , ACK); + ALLOC1_SIGNAL_OUT (out_SPR_EVENT_EPCR ,"EPCR" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT (out_SPR_EVENT_EEAR_WEN ,"EEAR_WEN" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_SPR_EVENT_EEAR ,"EEAR" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT (out_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("nb_inst",IN,EAST,_("Instruction number"),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit); + ALLOC1_SIGNAL_IN ( in_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("depth",OUT,EAST,_("Interface depth"),_param->_nb_context); + + ALLOC1_SIGNAL_OUT (out_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1); + } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr",IN,EAST,_("Interface with the special registerFile"),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1); + } + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("interrupt",IN,NORTH,_("Interrupt Exception"),_param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"ENABLE" ,Tcontrol_t ,1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string name; + + _component_ifetch_unit = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::Ifetch_unit * [_param->_nb_context]; + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + name = _name+"_ifetch_unit_"+toString(i); + log_printf(TRACE,Front_end,FUNCTION,_("Create : %s"),name.c_str()); + + _component_ifetch_unit [i] = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::Ifetch_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_ifetch_unit [i] + ,_usage); + + _component->set_component (_component_ifetch_unit [i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_prediction_unit"; + log_printf(TRACE,Front_end,FUNCTION,_("Create : %s"),name.c_str()); + + _component_prediction_unit = new morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::Prediction_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_prediction_unit + ,_usage); + + _component->set_component (_component_prediction_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + _component_decod_unit = new morpheo::behavioural::core::multi_front_end::front_end::decod_unit::Decod_unit * [_param->_nb_decod_unit]; + + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + { + name = _name+"_decod_unit_"+toString(i); + log_printf(TRACE,Front_end,FUNCTION,_("Create : %s"),name.c_str()); + + _component_decod_unit [i] = new morpheo::behavioural::core::multi_front_end::front_end::decod_unit::Decod_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_decod_unit [i] + ,_usage); + + _component->set_component (_component_decod_unit [i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_context_state"; + log_printf(TRACE,Front_end,FUNCTION,_("Create : %s"),name.c_str()); + + _component_context_state = new morpheo::behavioural::core::multi_front_end::front_end::context_state::Context_State + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_context_state + ,_usage); + + _component->set_component (_component_context_state->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_glue"; + log_printf(TRACE,Front_end,FUNCTION,_("Create : %s"),name.c_str()); + + _component_glue = new morpheo::behavioural::core::multi_front_end::front_end::front_end_glue::Front_end_Glue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_glue + ,_usage); + + _component->set_component (_component_glue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + + // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string src,dest; + + // =================================================================== + // =====[ ifetch_unit ]=============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + src = _name+"_ifetch_unit_"+toString(i); + log_printf(TRACE,Front_end,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_req", + dest,"icache_req_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" ); + //PORT_MAP(_component,src ,"out_ICACHE_REQ_THREAD_ID",dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID"); + if (_param->_have_port_ifetch_queue_ptr) + PORT_MAP(_component,src ,"out_ICACHE_REQ_PACKET_ID",dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS" ,dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_rsp", + dest,"icache_rsp_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" ); +// PORT_MAP(_component,src , "in_ICACHE_RSP_THREAD_ID" ,dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID" ); + if (_param->_have_port_ifetch_queue_ptr) + PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID" ,dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID" ); + PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" ); + + for (uint32_t j=0; j<_param->_nb_inst_fetch [i]; ++j) + { +#ifdef POSITION + _component->interface_map (src ,"icache_rsp_"+toString(j), + dest,"icache_rsp_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(j)+"_INSTRUCTION",dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION"); + } + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name+"_prediction_unit"; +#ifdef POSITION + _component->interface_map (src ,"predict" + dest,"predict_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_PREDICT_VAL" ,dest, "in_PREDICT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_PREDICT_ACK" ,dest,"out_PREDICT_"+toString(i)+"_ACK" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS" ,dest, "in_PREDICT_"+toString(i)+"_PC_PREVIOUS" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_PC_CURRENT" ,dest, "in_PREDICT_"+toString(i)+"_PC_CURRENT" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" ,dest, "in_PREDICT_"+toString(i)+"_PC_CURRENT_IS_DS_TAKE" ); + COMPONENT_MAP(_component,src , "in_PREDICT_PC_NEXT" ,dest,"out_PREDICT_"+toString(i)+"_PC_NEXT" ); + COMPONENT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE" ,dest,"out_PREDICT_"+toString(i)+"_PC_NEXT_IS_DS_TAKE" ); + if (_param->_have_port_inst_ifetch_ptr) + COMPONENT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR" ,dest,"out_PREDICT_"+toString(i)+"_INST_IFETCH_PTR" ); + COMPONENT_MAP(_component,src , "in_PREDICT_BRANCH_STATE" ,dest,"out_PREDICT_"+toString(i)+"_BRANCH_STATE" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",dest,"out_PREDICT_"+toString(i)+"_BRANCH_UPDATE_PREDICTION_ID"); + + for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; ++j) + { +#ifdef POSITION + _component->interface_map (src ,"predict_"+toString(j) + dest,"predict_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_PREDICT_"+toString(j)+ "_INSTRUCTION_ENABLE", + dest,"out_PREDICT_"+toString(i)+"_"+toString(j)+"_INSTRUCTION_ENABLE"); + } + } + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + uint32_t num_decod_unit = _param->_link_context_to_decod_unit[i]; + uint32_t num_context; + + for (num_context=0; num_context<_param->_decod_unit_nb_context[num_decod_unit]; num_context ++) + if (_param->_translate_context_id_from_decod_unit [num_decod_unit][num_context] == i) + break; + + dest = _name+"_decod_unit_"+toString(num_decod_unit); +#ifdef POSITION + _component->interface_map (src ,"decod" + dest,"ifetch_"+toString(num_context)); +#endif + + ////out_DECOD_CONTEXT_ID + + COMPONENT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest, "in_IFETCH_"+toString(num_context)+"_ADDRESS" ); + if (_param->_have_port_inst_ifetch_ptr) + COMPONENT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest, "in_IFETCH_"+toString(num_context)+"_INST_IFETCH_PTR" ); + COMPONENT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest, "in_IFETCH_"+toString(num_context)+"_BRANCH_STATE" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest, "in_IFETCH_"+toString(num_context)+"_BRANCH_UPDATE_PREDICTION_ID"); + COMPONENT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest, "in_IFETCH_"+toString(num_context)+"_EXCEPTION" ); + + for (uint32_t j=0; j<_param->_nb_inst_fetch [i];++j) + { + dest = _name+"_decod_unit_"+toString(num_decod_unit); +#ifdef POSITION + _component->interface_map (src ,"decod_"+toString(j) + dest,"ifetch_"+toString(num_context)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j)+ "_VAL" , + dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_DECOD_" +toString(j)+ "_ACK" , + dest,"out_IFETCH_"+toString(num_context)+"_"+toString(j)+"_ACK" ); + COMPONENT_MAP(_component,src ,"out_DECOD_" +toString(j)+ "_INSTRUCTION", + dest, "in_IFETCH_"+toString(num_context)+"_"+toString(j)+"_INSTRUCTION"); + } + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"event", + dest,"event_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_EVENT_VAL" , + dest,"out_EVENT_"+toString(i)+"_IFETCH_UNIT_VAL" ); + COMPONENT_MAP(_component,src ,"out_EVENT_ACK" , + dest, "in_EVENT_"+toString(i)+"_IFETCH_UNIT_ACK" ); + COMPONENT_MAP(_component,src , "in_EVENT_ADDRESS" , + dest,"out_EVENT_"+toString(i)+"_IFETCH_UNIT_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" , + dest,"out_EVENT_"+toString(i)+"_IFETCH_UNIT_ADDRESS_NEXT" ); + COMPONENT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL", + dest,"out_EVENT_"+toString(i)+"_IFETCH_UNIT_ADDRESS_NEXT_VAL"); + COMPONENT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" , + dest,"out_EVENT_"+toString(i)+"_IFETCH_UNIT_IS_DS_TAKE" ); + } + } + + // =================================================================== + // =====[ prediction_unit ]=========================================== + // =================================================================== + { + src = _name+"_prediction_unit"; + log_printf(TRACE,Front_end,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_PREDICT_VAL - component_ifetch_unit + // out_PREDICT_ACK - component_ifetch_unit + // in_PREDICT_PC_PREVIOUS - component_ifetch_unit + // in_PREDICT_PC_CURRENT - component_ifetch_unit + // in_PREDICT_PC_CURRENT_IS_DS_TAKE - component_ifetch_unit + // out_PREDICT_PC_NEXT - component_ifetch_unit + // out_PREDICT_PC_NEXT_IS_DS_TAKE - component_ifetch_unit + // out_PREDICT_INSTRUCTION_ENABLE - component_ifetch_unit + // out_PREDICT_INST_IFETCH_PTR - component_ifetch_unit + // out_PREDICT_BRANCH_STATE - component_ifetch_unit + // out_PREDICT_BRANCH_UPDATE_PREDICTION_ID - component_ifetch_unit + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_DECOD_VAL - component_decod_unit + // out_DECOD_ACK - component_decod_unit + // in_DECOD_CONTEXT_ID - component_decod_unit + // in_DECOD_MATCH_INST_IFETCH_PTR - component_decod_unit + // in_DECOD_BRANCH_STATE - component_decod_unit + // in_DECOD_BRANCH_UPDATE_PREDICTION_ID - component_decod_unit + // in_DECOD_BRANCH_CONDITION - component_decod_unit + // in_DECOD_BRANCH_DIRECTION - component_decod_unit + // in_DECOD_ADDRESS_SRC - component_decod_unit + // in_DECOD_ADDRESS_DEST - component_decod_unit + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+ "_VAL" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_PREDICTION_UNIT_VAL" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+ "_ACK" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTION_UNIT_ACK" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+ "_MISS_PREDICTION", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_PREDICTION_UNIT_MISS_PREDICTION"); + + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID"); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" ); + + dest = _name+"_context_state"; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_TAKE" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_TAKE" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS_SRC" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS_SRC" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS_DEST", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS_DEST"); + } + + // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name+"_context_state"; +#ifdef POSITION + _component->interface_map (src ,"branch_event_"+toString(i), + dest,"branch_event_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" , + dest,"out_BRANCH_EVENT_"+toString(i)+"_ACK" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , +// dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , +// dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION", +// dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION"); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(i), + dest,"depth_"+toString(i)); +#endif + + if (_param->_have_port_depth) + { + COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_CURRENT", + dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_CURRENT"); + COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_MIN" , + dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_MIN" ); + } + COMPONENT_MAP(_component,src ,"out_DEPTH_"+toString(i)+ "_MAX" , + dest, "in_DEPTH_"+toString(i)+"_PREDICTION_UNIT_MAX" ); + } + } + + // =================================================================== + // =====[ decod_unit ]================================================ + // =================================================================== + { + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + { + src = _name+"_decod_unit_"+toString(i); + log_printf(TRACE,Front_end,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_IFETCH_VAL - component_ifetch_unit + // out_IFETCH_ACK - component_ifetch_unit + // in_IFETCH_INSTRUCTION - component_ifetch_unit + // in_IFETCH_CONTEXT_ID - component_ifetch_unit + // in_IFETCH_ADDRESS - component_ifetch_unit + //// in_IFETCH_ADDRESS_NEXT - component_ifetch_unit + // in_IFETCH_INST_IFETCH_PTR - component_ifetch_unit + // in_IFETCH_BRANCH_STATE - component_ifetch_unit + // in_IFETCH_BRANCH_UPDATE_PREDICTION_ID - component_ifetch_unit + // in_IFETCH_EXCEPTION - component_ifetch_unit + + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"ifetch_"+toString(j), + dest,"ifetch_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_IFETCH_"+toString(j) +"_CONTEXT_ID", + dest,"out_IFETCH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_CONTEXT_ID"); + } + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_inst_decod [i]; ++j) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"decod_"+toString(j), + dest,"decod_"+toString(x)); +#endif + + + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_VAL" , + dest,"out_DECOD_"+toString(x)+"_VAL" ); + PORT_MAP(_component,src , "in_DECOD_"+toString(j)+"_ACK" , + dest, "in_DECOD_"+toString(x)+"_ACK" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_DEPTH" , + dest,"out_DECOD_"+toString(x)+"_DEPTH" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_TYPE" , + dest,"out_DECOD_"+toString(x)+"_TYPE" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_OPERATION" , + dest,"out_DECOD_"+toString(x)+"_OPERATION" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NO_EXECUTE" , + dest,"out_DECOD_"+toString(x)+"_NO_EXECUTE" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IS_DELAY_SLOT", + dest,"out_DECOD_"+toString(x)+"_IS_DELAY_SLOT"); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_ADDRESS" , + dest,"out_DECOD_"+toString(x)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_HAS_IMMEDIAT" , + dest,"out_DECOD_"+toString(x)+"_HAS_IMMEDIAT" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_IMMEDIAT" , + dest,"out_DECOD_"+toString(x)+"_IMMEDIAT" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_READ_RA" , + dest,"out_DECOD_"+toString(x)+"_READ_RA" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NUM_REG_RA" , + dest,"out_DECOD_"+toString(x)+"_NUM_REG_RA" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_READ_RB" , + dest,"out_DECOD_"+toString(x)+"_READ_RB" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NUM_REG_RB" , + dest,"out_DECOD_"+toString(x)+"_NUM_REG_RB" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_READ_RC" , + dest,"out_DECOD_"+toString(x)+"_READ_RC" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NUM_REG_RC" , + dest,"out_DECOD_"+toString(x)+"_NUM_REG_RC" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_WRITE_RD" , + dest,"out_DECOD_"+toString(x)+"_WRITE_RD" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NUM_REG_RD" , + dest,"out_DECOD_"+toString(x)+"_NUM_REG_RD" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_WRITE_RE" , + dest,"out_DECOD_"+toString(x)+"_WRITE_RE" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_NUM_REG_RE" , + dest,"out_DECOD_"+toString(x)+"_NUM_REG_RE" ); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_EXCEPTION_USE", + dest,"out_DECOD_"+toString(x)+"_EXCEPTION_USE"); + PORT_MAP(_component,src ,"out_DECOD_"+toString(j)+"_EXCEPTION" , + dest,"out_DECOD_"+toString(x)+"_EXCEPTION" ); + + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"decod_"+toString(j), + dest,"decod_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_DECOD_"+toString(j)+ "_CONTEXT_ID" , + dest, "in_DECOD_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_CONTEXT_ID" ); + + x++; + } + + // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + { + dest = _name+"_prediction_unit"; +#ifdef POSITION + _component->interface_map (src ,"predict_"+toString(j), + dest,"decod_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_VAL" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_PREDICT_"+toString(j)+ "_ACK" , + dest,"out_DECOD_" +toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_CONTEXT_ID" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_MATCH_INST_IFETCH_PTR" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_MATCH_INST_IFETCH_PTR" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_BRANCH_STATE" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_BRANCH_STATE" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_BRANCH_UPDATE_PREDICTION_ID", + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_BRANCH_UPDATE_PREDICTION_ID"); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_BRANCH_CONDITION" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_BRANCH_CONDITION" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_BRANCH_DIRECTION" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_BRANCH_DIRECTION" ); +// COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_BRANCH_STACK_WRITE" , +// dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_BRANCH_STACK_WRITE" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_ADDRESS_SRC" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_ADDRESS_SRC" ); + COMPONENT_MAP(_component,src ,"out_PREDICT_"+toString(j)+ "_ADDRESS_DEST" , + dest, "in_DECOD_" +toString(i)+"_"+toString(j)+"_ADDRESS_DEST" ); +// COMPONENT_MAP(_component,src , "in_PREDICT_"+toString(j)+ "_CAN_CONTINUE" , +// dest,"out_DECOD_" +toString(i)+"_"+toString(j)+"_CAN_CONTINUE" ); + + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + { + // uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j]; + + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(j), + dest,"depth_"+toString(j)); +#endif + + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+ "_MIN", + dest,"out_DEPTH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_MIN"); + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+ "_MAX", + dest,"out_DEPTH_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_MAX"); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + { + uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j]; + + dest = _name+"_context_state"; +#ifdef POSITION + _component->interface_map (src ,"nb_inst_"+toString(j), + dest,"nb_inst_"+toString(y)); +#endif + + COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_DECOD_ALL", + dest, "in_NB_INST_"+toString(y)+"_DECOD_ALL"); + } + + // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_decod_unit_nb_context[i]; ++j) + { + uint32_t y=(_param->_translate_context_id_from_decod_unit[i])[j]; + + dest = _name+"_context_state"; +#ifdef POSITION + _component->interface_map (src ,"context_"+toString(j), + dest,"context_"+toString(y)); +#endif + + COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+"_DECOD_ENABLE", + dest,"out_CONTEXT_"+toString(y)+"_DECOD_ENABLE"); + + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"context_"+toString(j), + dest,"context_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_CONTEXT_"+toString(j)+ "_DEPTH", + dest,"out_CONTEXT_"+toString(i)+"_"+toString(j)+"_DECOD_UNIT_DEPTH"); + } + + + // ~~~~~[ Interface : "context_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name+"_context_state"; +#ifdef POSITION + _component->interface_map (src ,"context_event", + dest,"decod_event_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_VAL" ,dest, "in_DECOD_EVENT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_CONTEXT_EVENT_ACK" ,dest,"out_DECOD_EVENT_"+toString(i)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_CONTEXT_ID" ,dest, "in_DECOD_EVENT_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_DEPTH" ,dest, "in_DECOD_EVENT_"+toString(i)+"_DEPTH" ); + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_TYPE" ,dest, "in_DECOD_EVENT_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_IS_DELAY_SLOT",dest, "in_DECOD_EVENT_"+toString(i)+"_IS_DELAY_SLOT"); + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_ADDRESS" ,dest, "in_DECOD_EVENT_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_CONTEXT_EVENT_ADDRESS_EPCR" ,dest, "in_DECOD_EVENT_"+toString(i)+"_ADDRESS_EPCR" ); + } + } + } + + // =================================================================== + // =====[ context_state ]============================================= + // =================================================================== + { + src = _name+"_context_state"; + log_printf(TRACE,Front_end,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "decod_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_DECOD_EVENT_VAL - component_decod_unit + // out_DECOD_EVENT_ACK - component_decod_unit + // in_DECOD_EVENT_CONTEXT_ID - component_decod_unit + // in_DECOD_EVENT_DEPTH - component_decod_unit + // in_DECOD_EVENT_TYPE - component_decod_unit + // in_DECOD_EVENT_IS_DELAY_SLOT - component_decod_unit + // in_DECOD_EVENT_ADDRESS - component_decod_unit + // in_DECOD_EVENT_ADDRESS_EPCR - component_decod_unit + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"commit_event", + dest,"commit_event"); +#endif + + PORT_MAP(_component,src , "in_COMMIT_EVENT_VAL" , + dest, "in_COMMIT_EVENT_VAL" ); + PORT_MAP(_component,src ,"out_COMMIT_EVENT_ACK" , + dest,"out_COMMIT_EVENT_ACK" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_COMMIT_EVENT_CONTEXT_ID" , + dest, "in_COMMIT_EVENT_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_COMMIT_EVENT_DEPTH" , + dest, "in_COMMIT_EVENT_DEPTH" ); + PORT_MAP(_component,src , "in_COMMIT_EVENT_TYPE" , + dest, "in_COMMIT_EVENT_TYPE" ); + PORT_MAP(_component,src , "in_COMMIT_EVENT_IS_DELAY_SLOT" , + dest, "in_COMMIT_EVENT_IS_DELAY_SLOT" ); + PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS" , + dest, "in_COMMIT_EVENT_ADDRESS" ); + PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR" , + dest, "in_COMMIT_EVENT_ADDRESS_EPCR" ); + PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EEAR_VAL", + dest, "in_COMMIT_EVENT_ADDRESS_EEAR_VAL"); + PORT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EEAR" , + dest, "in_COMMIT_EVENT_ADDRESS_EEAR" ); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+ "_VAL" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_STATE_VAL" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+ "_ACK" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_STATE_ACK" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+ "_MISS_PREDICTION", + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_STATE_MISS_PREDICTION"); + + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID"); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" ); + + // in_BRANCH_COMPLETE_TAKE - component_prediction_unit + // in_BRANCH_COMPLETE_ADDRESS_SRC - component_prediction_unit + // in_BRANCH_COMPLETE_ADDRESS_DEST - component_prediction_unit + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_NB_INST_DECOD_ALL - component_decod_unit + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"nb_inst", + dest,"nb_inst"); +#endif + + PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_COMMIT_ALL", + dest, "in_NB_INST_"+toString(i)+"_COMMIT_ALL"); + PORT_MAP(_component,src , "in_NB_INST_"+toString(i)+"_COMMIT_MEM", + dest, "in_NB_INST_"+toString(i)+"_COMMIT_MEM"); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(i), + dest,"event_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_VAL" , + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_VAL" ); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_ACK" , + dest,"out_EVENT_"+toString(i)+"_CONTEXT_STATE_ACK" ); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ADDRESS", + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_ADDRESS"); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ADDRESS_NEXT" , + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_ADDRESS_NEXT" ); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ADDRESS_NEXT_VAL", + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_ADDRESS_NEXT_VAL"); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_IS_DS_TAKE" , + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_IS_DS_TAKE" ); + } + + // ~~~~~[ Interface "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"spr_event_"+toString(i), + dest,"spr_event_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_VAL" , + dest,"out_SPR_EVENT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_ACK" , + dest, "in_SPR_EVENT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_EPCR" , + dest,"out_SPR_EVENT_"+toString(i)+"_EPCR" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_EEAR" , + dest,"out_SPR_EVENT_"+toString(i)+"_EEAR" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_EEAR_WEN" , + dest,"out_SPR_EVENT_"+toString(i)+"_EEAR_WEN" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_SR_DSX" , + dest,"out_SPR_EVENT_"+toString(i)+"_SR_DSX" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_SR_TO_ESR", + dest,"out_SPR_EVENT_"+toString(i)+"_SR_TO_ESR"); + } + + // ~~~~~[ Interface : "context" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_CONTEXT_DECOD_ENABLE - component_decod_unit + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(i), + dest,"depth_"+toString(i)); +#endif + + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(i)+ "_MIN", + dest,"out_DEPTH_"+toString(i)+"_CONTEXT_STATE_MIN"); + } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"spr_"+toString(i), + dest,"spr_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_SPR_"+toString(i)+"_SR_IEE", + dest, "in_SPR_"+toString(i)+"_SR_IEE"); + PORT_MAP(_component,src , "in_SPR_"+toString(i)+"_SR_EPH", + dest, "in_SPR_"+toString(i)+"_SR_EPH"); + } + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"interrupt_"+toString(i), + dest,"interrupt_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE", + dest, "in_INTERRUPT_"+toString(i)+"_ENABLE"); + } + + } + + // =================================================================== + // =====[ glue ]====================================================== + // =================================================================== + { + src = _name+"_glue"; + log_printf(TRACE,Front_end,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "ifetch" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_IFETCH_DECOD_UNIT_CONTEXT_ID - component_decod_unit + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i];++j) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"decod_"+toString(i)+"_"+toString(j), + dest,"decod_"+toString(x)); +#endif + + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID", + dest,"out_DECOD_"+toString(x)+ "_CONTEXT_ID"); + x++; + } + // in_DECOD_DECOD_UNIT_CONTEXT_ID - component_decod_unit + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); + } + + // out_BRANCH_COMPLETE_PREDICTION_UNIT_VAL - component_prediction_unit + // in_BRANCH_COMPLETE_PREDICTION_UNIT_ACK - component_prediction_unit + // in_BRANCH_COMPLETE_PREDICTION_UNIT_MISS_PREDICTION - component_prediction_unit + // out_BRANCH_COMPLETE_CONTEXT_STATE_VAL - component_context_state + // in_BRANCH_COMPLETE_CONTEXT_STATE_ACK - component_context_state + // out_BRANCH_COMPLETE_CONTEXT_STATE_MISS_PREDICTION - component_context_state + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(i), + dest,"event_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_VAL" , + dest,"out_EVENT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_ACK" , + dest, "in_EVENT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ADDRESS" , + dest,"out_EVENT_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ADDRESS_NEXT" , + dest,"out_EVENT_"+toString(i)+"_ADDRESS_NEXT" ); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ADDRESS_NEXT_VAL", + dest,"out_EVENT_"+toString(i)+"_ADDRESS_NEXT_VAL"); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_IS_DS_TAKE" , + dest,"out_EVENT_"+toString(i)+"_IS_DS_TAKE" ); + } + + // out_EVENT_IFETCH_UNIT_VAL - component_ifetch_unit + // in_EVENT_IFETCH_UNIT_ACK - component_ifetch_unit + // out_EVENT_IFETCH_UNIT_ADDRESS - component_ifetch_unit + // in_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit + // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL - component_ifetch_unit + // in_EVENT_IFETCH_UNIT_IS_DS_TAKE - component_ifetch_unit + // in_EVENT_CONTEXT_STATE_VAL - component_context_state + // out_EVENT_CONTEXT_STATE_ACK - component_context_state + // in_EVENT_CONTEXT_STATE_ADDRESS - component_context_state + // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT - component_context_state + // out_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state + // in_EVENT_CONTEXT_STATE_IS_DS_TAKE - component_context_state + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(i), + dest,"depth_"+toString(i)); +#endif + + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MIN", + dest,"out_DEPTH_"+toString(i)+"_MIN"); + PORT_MAP(_component,src ,"out_DEPTH_"+toString(i)+"_MAX", + dest,"out_DEPTH_"+toString(i)+"_MAX"); + } + + // in_DEPTH_PREDICTION_UNIT_CURRENT - component_prediction_unit + // in_DEPTH_PREDICTION_UNIT_MIN - component_prediction_unit + // in_DEPTH_PREDICTION_UNIT_MAX - component_prediction_unit + // out_DEPTH_DECOD_UNIT_MIN - component_decod_unit + // out_DEPTH_DECOD_UNIT_MAX - component_decod_unit + // out_DEPTH_CONTEXT_STATE_MIN - component_context_state + + // ~~~~~[ Interface : "context"" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_CONTEXT_DECOD_UNIT_DEPTH - component_decod_unit + } + + // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#if DEBUG_Front_end == true + _component->test_map(false); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 88) @@ -0,0 +1,130 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::deallocation" + void Front_end::deallocation (void) + { + log_begin(Front_end,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_context,1); +// DELETE1_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_context,_param->_size_context_id ); + DELETE1_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_context,_param->_size_ifetch_queue_ptr ); + DELETE1_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_context,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_context,_param->_size_icache_type ); + + DELETE1_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_context,1); +// DELETE1_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_context,_param->_size_context_id ); + DELETE1_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_context,_param->_size_ifetch_queue_ptr ); + DELETE1_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_context,_param->_size_icache_error ); + DELETE2_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1],_param->_size_instruction ); + + DELETE1_SIGNAL(out_DECOD_VAL ,_param->_sum_inst_decod, 1); + DELETE1_SIGNAL( in_DECOD_ACK ,_param->_sum_inst_decod, 1); + DELETE1_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_sum_inst_decod,_param->_size_context_id ); + DELETE1_SIGNAL(out_DECOD_DEPTH ,_param->_sum_inst_decod,_param->_size_depth ); + DELETE1_SIGNAL(out_DECOD_TYPE ,_param->_sum_inst_decod,_param->_size_type ); + DELETE1_SIGNAL(out_DECOD_OPERATION ,_param->_sum_inst_decod,_param->_size_operation ); + DELETE1_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_ADDRESS ,_param->_sum_inst_decod,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_IMMEDIAT ,_param->_sum_inst_decod,_param->_size_general_data ); + DELETE1_SIGNAL(out_DECOD_READ_RA ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_sum_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_READ_RB ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_sum_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_READ_RC ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_sum_inst_decod,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_DECOD_WRITE_RD ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_sum_inst_decod,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_DECOD_WRITE_RE ,_param->_sum_inst_decod,1 ); + DELETE1_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_sum_inst_decod,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_sum_inst_decod,_param->_size_exception_use ); + DELETE1_SIGNAL(out_DECOD_EXCEPTION ,_param->_sum_inst_decod,_param->_size_exception ); + + DELETE1_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete, 1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete, 1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); + + DELETE_SIGNAL ( in_COMMIT_EVENT_VAL , 1); + DELETE_SIGNAL (out_COMMIT_EVENT_ACK , 1); + DELETE_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id); + DELETE_SIGNAL ( in_COMMIT_EVENT_DEPTH ,_param->_size_depth ); + DELETE_SIGNAL ( in_COMMIT_EVENT_TYPE ,_param->_size_event_type); + DELETE_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS ,_param->_size_instruction_address ); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_instruction_address ); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); + DELETE_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_instruction_address ); + + DELETE1_SIGNAL(out_EVENT_VAL ,_param->_nb_context, 1); + DELETE1_SIGNAL( in_EVENT_ACK ,_param->_nb_context, 1); + DELETE1_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1 ); + DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1 ); + + DELETE1_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context, 1); + DELETE1_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context, 1); + DELETE1_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context,_param->_size_spr); + DELETE1_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context,1 ); + DELETE1_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context,_param->_size_spr); + DELETE1_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context,1 ); + DELETE1_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context,1 ); + + DELETE1_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context,_param->_size_nb_inst_commit); + DELETE1_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context,_param->_size_nb_inst_commit); + + DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + + DELETE1_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context,1); + DELETE1_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context,1); + + DELETE1_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context,1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _component_glue ; + delete _component_context_state ; + delete [] _component_decod_unit ; + delete _component_prediction_unit; + delete [] _component_ifetch_unit ; + + delete _component; + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_end_cycle.cpp (revision 88) @@ -0,0 +1,45 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::end_cycle" +void Front_end::end_cycle () + { + log_begin(Front_end,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_allocation.cpp (revision 88) @@ -0,0 +1,46 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::statistics_allocation" + void Front_end::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Front_end,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Front_end", + param_statistics); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + _stat->add_stat(_component_ifetch_unit [i] ->_stat); + _stat->add_stat(_component_prediction_unit ->_stat); + _stat->add_stat(_component_context_state ->_stat); + for (uint32_t i=0; i<_param->_nb_decod_unit; ++i) + _stat->add_stat(_component_decod_unit [i] ->_stat); + _stat->add_stat(_component_glue ->_stat); + + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::statistics_deallocation" + void Front_end::statistics_deallocation (void) + { + log_begin(Front_end,FUNCTION); + + log_printf(INFO,Front_end,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_transition.cpp (revision 88) @@ -0,0 +1,39 @@ +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::transition" + void Front_end::transition (void) + { + log_begin(Front_end,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +# endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_vhdl.cpp (revision 88) @@ -0,0 +1,43 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::vhdl" + void Front_end::vhdl (void) + { + log_begin(Front_end,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 88) @@ -0,0 +1,335 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::Parameters" + Parameters::Parameters (uint32_t nb_context , + uint32_t nb_decod_unit , + uint32_t size_general_data , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + // ifetch_unit + uint32_t * size_ifetch_queue , + uint32_t * nb_inst_fetch , + bool ** instruction_implemeted , + uint32_t * link_context_to_decod_unit , + // decod_unit + uint32_t * size_decod_queue , + uint32_t * nb_inst_decod , + uint32_t * nb_context_select , + Tpriority_t * context_select_priority , + Tload_balancing_t * context_select_load_balancing , + // prediction_unit + uint32_t nb_inst_branch_predict , + uint32_t nb_inst_branch_decod , + uint32_t nb_inst_branch_update , + uint32_t nb_inst_branch_complete , + uint32_t btb_size_queue , + uint32_t btb_associativity , + uint32_t btb_size_counter , + Tvictim_t btb_victim_scheme , + Tpredictor_t dir_predictor_scheme , + bool * dir_have_bht ,//[3] + uint32_t * dir_bht_size_shifter ,//[3] + uint32_t * dir_bht_nb_shifter ,//[3] + bool * dir_have_pht ,//[3] + uint32_t * dir_pht_size_counter ,//[3] + uint32_t * dir_pht_nb_counter ,//[3] + uint32_t * dir_pht_size_address_share ,//[3] + uint32_t * ras_size_queue , + uint32_t * upt_size_queue , + // context_state + uint32_t size_nb_inst_commit , + bool is_toplevel): + morpheo::behavioural::Parameters() + { + log_begin(Front_end,FUNCTION); + + _nb_context = nb_context ; + _nb_decod_unit = nb_decod_unit ; +// _size_general_data = size_general_data ; + _get_custom_information = get_custom_information ; + _size_ifetch_queue = size_ifetch_queue ; + _nb_inst_fetch = nb_inst_fetch ; + _instruction_implemeted = instruction_implemeted ; + _link_context_to_decod_unit = link_context_to_decod_unit ; + _size_decod_queue = size_decod_queue ; + _nb_inst_decod = nb_inst_decod ; + _nb_context_select = nb_context_select ; + _context_select_priority = context_select_priority ; + _context_select_load_balancing = context_select_load_balancing ; + _nb_inst_branch_predict = nb_inst_branch_predict ; + _nb_inst_branch_decod = nb_inst_branch_decod ; + _nb_inst_branch_update = nb_inst_branch_update ; + _nb_inst_branch_complete = nb_inst_branch_complete ; + _btb_size_queue = btb_size_queue ; + _btb_associativity = btb_associativity ; + _btb_size_counter = btb_size_counter ; + _btb_victim_scheme = btb_victim_scheme ; + _dir_predictor_scheme = dir_predictor_scheme ; + for (uint32_t i=0; i<3; i++) + { + _dir_have_bht [i] = dir_have_bht [i]; + _dir_bht_size_shifter [i] = dir_bht_size_shifter [i]; + _dir_bht_nb_shifter [i] = dir_bht_nb_shifter [i]; + _dir_have_pht [i] = dir_have_pht [i]; + _dir_pht_size_counter [i] = dir_pht_size_counter [i]; + _dir_pht_nb_counter [i] = dir_pht_nb_counter [i]; + _dir_pht_size_address_share [i] = dir_pht_size_address_share [i]; + } + _ras_size_queue = ras_size_queue ; + _upt_size_queue = upt_size_queue ; + + test(); + +// _size_context_id = log2(_nb_context); + uint32_t size_instruction_address = size_general_data - 2; + + _array_size_depth = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; i++) + _array_size_depth [i] = log2(_upt_size_queue[i]); + + _array_size_nb_inst_decod = new uint32_t [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; i++) + _array_size_nb_inst_decod [i] = log2(_size_decod_queue[i]+1); + + _param_ifetch_unit = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters * [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + { + _param_ifetch_unit [i] = new behavioural::core::multi_front_end::front_end::ifetch_unit::Parameters + (_size_ifetch_queue [i] , + _nb_inst_fetch [i] , + log2(_upt_size_queue[i]) , + size_instruction_address ); + } + + _param_prediction_unit = new behavioural::core::multi_front_end::front_end::prediction_unit::Parameters + (_nb_context , + _nb_decod_unit , + size_instruction_address , + _nb_inst_fetch , + _nb_inst_decod , + _nb_inst_branch_predict , + _nb_inst_branch_decod , + _nb_inst_branch_update , + _nb_inst_branch_complete , + _btb_size_queue , + _btb_associativity , + _btb_size_counter , + _btb_victim_scheme , + _dir_predictor_scheme , + _dir_have_bht , + _dir_bht_size_shifter , + _dir_bht_nb_shifter , + _dir_have_pht , + _dir_pht_size_counter , + _dir_pht_nb_counter , + _dir_pht_size_address_share , + _ras_size_queue , + _upt_size_queue ); + + _translate_context_id_from_decod_unit= new std::vector [_nb_decod_unit]; + + for (uint32_t i=0; i<_nb_context; ++i) + _translate_context_id_from_decod_unit [_link_context_to_decod_unit[i]].push_back(i); + + _decod_unit_nb_context = new uint32_t [_nb_decod_unit]; + _decod_unit_nb_inst_fetch = new uint32_t * [_nb_decod_unit]; + _decod_unit_nb_branch_speculated = new uint32_t * [_nb_decod_unit]; +// _decod_unit_depth = new uint32_t * [_nb_decod_unit]; + _decod_unit_instruction_implemeted = new bool ** [_nb_decod_unit]; +// _have_port_decod_unit_context_id = new bool [_nb_decod_unit]; + _sum_inst_decod = 0; + + for (uint32_t i=0; i<_nb_decod_unit; ++i) + { + _sum_inst_decod += _nb_inst_decod [i]; + + uint32_t size = _translate_context_id_from_decod_unit [i].size(); + + _decod_unit_nb_context [i] = size; + _decod_unit_nb_inst_fetch [i] = new uint32_t [size]; +// _decod_unit_depth [i] = new uint32_t [size]; + _decod_unit_nb_branch_speculated [i] = new uint32_t [size]; + _decod_unit_instruction_implemeted [i] = new bool * [size]; +// _have_port_decod_unit_context_id [i] = size > 0; + + for (uint32_t j=0; j Decod_unit_Context [%d]"),j,(_translate_context_id_from_decod_unit [i])[j]); + log_printf(TRACE,Front_end,FUNCTION,_(" * decod_unit_nb_inst_fetch : %d"),_decod_unit_nb_inst_fetch [i][j]); + log_printf(TRACE,Front_end,FUNCTION,_(" * decod_unit_nb_branch_speculated : %d"),_decod_unit_nb_branch_speculated[i][j]); + } + } + + _param_decod_unit = new behavioural::core::multi_front_end::front_end::decod_unit::Parameters * [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_decod_unit; ++i) + { + _param_decod_unit [i] = new behavioural::core::multi_front_end::front_end::decod_unit::Parameters + (_decod_unit_nb_context [i], + _decod_unit_nb_inst_fetch [i], + _nb_inst_decod [i], + _size_decod_queue [i], + size_general_data , + _decod_unit_nb_branch_speculated [i], +// _decod_unit_depth [i], + _nb_context_select [i], + _context_select_priority [i], + _context_select_load_balancing [i], + _decod_unit_instruction_implemeted [i], + _get_custom_information ); + } + + _param_context_state = new behavioural::core::multi_front_end::front_end::context_state::Parameters + (_nb_context, + _nb_decod_unit, + _nb_inst_branch_complete, + _array_size_depth, + size_instruction_address, + _array_size_nb_inst_decod, + size_nb_inst_commit, + _link_context_to_decod_unit); + + _param_glue = new behavioural::core::multi_front_end::front_end::front_end_glue::Parameters + (_nb_context , + _nb_decod_unit , + _nb_inst_decod , + _nb_inst_branch_complete , + _link_context_to_decod_unit , + _translate_context_id_from_decod_unit , + size_instruction_address , + _array_size_depth , + _upt_size_queue //_nb_branch_speculated + ); + + if (is_toplevel) + { + _size_context_id = log2(_nb_context); + _size_instruction_address = size_instruction_address; + _size_general_data = size_general_data; + _size_nb_inst_decod = max(_array_size_nb_inst_decod,_nb_decod_unit); + _size_nb_inst_commit = size_nb_inst_commit; + _size_depth = max(_array_size_depth,_nb_context); + _size_ifetch_queue_ptr = log2(max(_size_ifetch_queue,_nb_context)); + _size_inst_ifetch_ptr = log2(max(_nb_inst_fetch ,_nb_context)); + + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; + _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr> 0; + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + + copy (); + } + + log_end(Front_end,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Front_end::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Front_end,FUNCTION); +// test(); +// log_end(Front_end,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Front_end::~Parameters" + Parameters::~Parameters () + { + log_begin(Front_end,FUNCTION); + + delete [] _param_glue ; + delete [] _param_context_state ; + for (uint32_t i=0; i<_nb_decod_unit; i++) + delete [] _param_decod_unit [i]; + delete [] _param_decod_unit ; + delete [] _param_prediction_unit; + for (uint32_t i=0; i<_nb_context; i++) + delete [] _param_ifetch_unit [i]; + delete [] _param_ifetch_unit ; + +// delete [] _size_ifetch_queue_ptr; +// delete [] _size_nb_inst_decod; + delete [] _array_size_depth; + for (uint32_t i=0; i<_nb_context; ++i) + { + for (uint32_t j=0; j<_translate_context_id_from_decod_unit [i].size(); ++j) + delete [] _decod_unit_instruction_implemeted [i][j]; + + delete [] _decod_unit_nb_inst_fetch [i]; +// delete [] _decod_unit_depth [i]; + delete [] _decod_unit_nb_branch_speculated [i]; + delete [] _decod_unit_instruction_implemeted [i]; + } + delete [] _decod_unit_nb_inst_fetch ; +// delete [] _decod_unit_depth ; + delete [] _decod_unit_nb_branch_speculated ; + delete [] _decod_unit_instruction_implemeted; + +// delete [] _have_port_decod_unit_context_id; + delete [] _decod_unit_nb_context ; + delete [] _translate_context_id_from_decod_unit; + + log_end(Front_end,FUNCTION); + }; + + +#undef FUNCTION +#define FUNCTION "Front_end::copy" + void Parameters::copy (void) + { + log_begin(Front_end,FUNCTION); + + COPY(_param_glue ); + COPY(_param_context_state ); + for (uint32_t i=0; i<_nb_decod_unit; i++) + { + COPY(_param_decod_unit [i]); + } + COPY(_param_prediction_unit); + for (uint32_t i=0; i<_nb_context; i++) + COPY(_param_ifetch_unit [i]); + + log_end(Front_end,FUNCTION); + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,51 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Front_end,FUNCTION); + + Parameters_test test ("Front_end"); + + std::vector translate_context_from_decod_unit [_nb_decod_unit]; + for (uint32_t i=0; i<_nb_context; ++i) + { + uint32_t x = _link_context_to_decod_unit[i]; + if (x < _nb_decod_unit) + translate_context_from_decod_unit [x].push_back(i); + else + test.error(toString(_("context[%d] is linked with an invalid decod_unit.\n"),i)); + } + + for (uint32_t i=0; i<_nb_decod_unit; ++i) + if (translate_context_from_decod_unit [i].size() == 0) + test.error(toString(_("decod_unit[%d] is not linked with a ifetch_unit.\n"),i)); + + log_end(Front_end,FUNCTION); + + return test; + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,58 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_front_end { +namespace front_end { + + +#undef FUNCTION +#define FUNCTION "Front_end::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Front_end,FUNCTION); + +// XML xml ("front_end"); + +// xml.balise_open("front_end"); +// // xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); +// xml.balise_close(); + +// return xml.get_body(depth); + + std::string str = ""; + + log_end(Front_end,FUNCTION); + + return str; + }; + +#undef FUNCTION +#define FUNCTION "Front_end::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_front_end::front_end::Parameters & x) + { + log_begin(Front_end,FUNCTION); + + output_stream << x.print(0); + + log_end(Front_end,FUNCTION); + + return output_stream; + }; + +}; // end namespace front_end +}; // end namespace multi_front_end +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libCommit_unit.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Commit_unit = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Commit_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit + +#-----[ Library ]------------------------------------------ + +Commit_unit_LIBRARY = -lCommit_unit \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Commit_unit_DIR_LIBRARY = -L$(Commit_unit_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Commit_unit_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Commit_unit_DIR) --makefile=Makefile; + +Commit_unit_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Commit_unit_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Commit_unit_LIBRARY) + +DIR_LIBRARY = $(Commit_unit_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Commit_unit_library + +library_clean : Commit_unit_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_min.cfg (revision 88) @@ -0,0 +1,20 @@ +Commit_unit +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_rename_unit +1 1 +1 # size_queue +1 1 +1 # nb_bank +1 1 +1 # nb_inst_insert [0] [nb_rename_unit] +1 1 +1 # nb_inst_retire [0] [nb_rename_unit] +1 1 +1 # nb_inst_commit +1 1 +1 # nb_inst_reexecute +1 1 +1 # nb_inst_branch_complete +0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +32 32 +1 # size_general_data +1 1 +1 # size_store_queue_ptr +0 0 +1 # size_load_queue_ptr +5 5 +1 # size_general_register +1 1 +1 # size_special_register +1 1 +1 # priority +1 1 +1 # load_balancing +1 1 +1 # nb_rename_unit_select Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/config_mono_rename_unit.cfg (revision 88) @@ -0,0 +1,20 @@ +Commit_unit +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_rename_unit +64 64 *2 # size_queue +4 8 *2 # nb_bank +1 4 *4 # nb_inst_insert [0] [nb_rename_unit] +1 4 *4 # nb_inst_retire [0] [nb_rename_unit] +1 4 *4 # nb_inst_commit +1 1 +1 # nb_inst_reexecute +1 1 +1 # nb_inst_branch_complete +0 0 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +32 32 +1 # size_general_data +1 1 +1 # size_store_queue_ptr +0 0 +1 # size_load_queue_ptr +5 5 +1 # size_general_register +1 1 +1 # size_special_register +1 1 +1 # priority +1 1 +1 # load_balancing +1 1 +1 # nb_rename_unit_select Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (10240*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,156 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" + +#define NB_PARAMS 15 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_rename_unit (uint32_t )\n")); + err (_(" * size_queue (uint32_t )\n")); + err (_(" * nb_bank (uint32_t )\n")); + err (_(" * nb_inst_insert [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_inst_retire [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_inst_commit (uint32_t )\n")); + err (_(" * nb_inst_reexecute (uint32_t )\n")); + err (_(" * nb_inst_branch_complete (uint32_t )\n")); + err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_store_queue_ptr (uint32_t )\n")); + err (_(" * size_load_queue_ptr (uint32_t )\n")); + err (_(" * size_general_register (uint32_t )\n")); + err (_(" * size_special_register (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + err (_(" * nb_rename_unit_select (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + + if (argc <= static_cast(2+NB_PARAMS+_nb_front_end)) + usage (argc, argv); + + uint32_t _sum_nb_context = 0; + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_context [i] = fromString(argv[x++]); + _sum_nb_context += _nb_context [i]; + } + uint32_t _nb_rename_unit = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+1*_nb_front_end+_sum_nb_context+2*_nb_rename_unit)) + usage (argc, argv); + + uint32_t _size_queue = fromString(argv[x++]); + uint32_t _nb_bank = fromString(argv[x++]); + uint32_t * _nb_inst_insert = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_inst_insert [i] = fromString(argv[x++]); + uint32_t * _nb_inst_retire = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_inst_retire [i] = fromString(argv[x++]); + uint32_t _nb_inst_commit = fromString(argv[x++]); + uint32_t _nb_inst_reexecute = fromString(argv[x++]); + uint32_t _nb_inst_branch_complete = fromString(argv[x++]); + uint32_t ** _nb_branch_speculated = new uint32_t * [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_branch_speculated [i] = new uint32_t [_nb_context [i]]; + for (uint32_t j=0; j<_nb_context [i]; j++) + _nb_branch_speculated [i][j] = fromString(argv[x++]); + } + + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_store_queue_ptr = fromString(argv[x++]); + uint32_t _size_load_queue_ptr = fromString(argv[x++]); + uint32_t _size_general_register = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + uint32_t _nb_rename_unit_select = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters + (_nb_front_end , + _nb_context , + _nb_rename_unit , + _size_queue , + _nb_bank , + _nb_inst_insert , + _nb_inst_retire , + _nb_inst_commit , + _nb_inst_reexecute , + _nb_inst_branch_complete , + _nb_branch_speculated , + _size_general_data , + _size_store_queue_ptr , + _size_load_queue_ptr , + _size_general_register , + _size_special_register , + _priority , + _load_balancing , + _nb_rename_unit_select , + true // is_toplevel + ); + +// msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("%s"),error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("No error"); + else + TEST_KO("A lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_context ; + delete [] _nb_inst_insert; + delete [] _nb_inst_retire; + for (uint32_t i=0; i<_nb_front_end; i++) + delete [] _nb_branch_speculated [i]; + delete [] _nb_branch_speculated; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,723 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +class rob_entry_t +{ +public: bool val; +public : Taddress_t address; +}; + + + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Commit_unit * _Commit_unit = new Commit_unit + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_FRONT_END_ID ," in_INSERT_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_CONTEXT_ID ," in_INSERT_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_PACKET_ID ,"out_INSERT_PACKET_ID ",Tpacket_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_ID ," in_INSERT_RENAME_UNIT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_DEPTH ," in_INSERT_DEPTH ",Tdepth_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_TYPE ," in_INSERT_TYPE ",Ttype_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_OPERATION ," in_INSERT_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Tgeneral_data_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ," in_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE ," in_INSERT_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ," in_INSERT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_READ_RA ," in_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RA_LOG ," in_INSERT_NUM_REG_RA_LOG ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RA_PHY ," in_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_READ_RB ," in_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RB_LOG ," in_INSERT_NUM_REG_RB_LOG ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RB_PHY ," in_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_READ_RC ," in_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RC_LOG ," in_INSERT_NUM_REG_RC_LOG ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RC_PHY ," in_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_WRITE_RD ," in_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RD_LOG ," in_INSERT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD ," in_INSERT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW ," in_INSERT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_WRITE_RE ," in_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RE_LOG ," in_INSERT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD ," in_INSERT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW ," in_INSERT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_VAL ,"out_RETIRE_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL( in_RETIRE_ACK ," in_RETIRE_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_FRONT_END_ID ,"out_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_CONTEXT_ID ,"out_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +//ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,"out_RETIRE_RENAME_UNIT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,"out_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,"out_RETIRE_USE_STORE_QUEUE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,"out_RETIRE_USE_LOAD_QUEUE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE ,"out_RETIRE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"out_RETIRE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_READ_RA ,"out_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY ,"out_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_READ_RB ,"out_RETIRE_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY ,"out_RETIRE_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_READ_RC ,"out_RETIRE_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY ,"out_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_WRITE_RD ,"out_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_LOG ,"out_RETIRE_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_OLD ,"out_RETIRE_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_NEW ,"out_RETIRE_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_WRITE_RE ,"out_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_LOG ,"out_RETIRE_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_OLD ,"out_RETIRE_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,"out_RETIRE_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + ALLOC1_SC_SIGNAL( in_COMMIT_VAL ," in_COMMIT_VAL ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_ACK ,"out_COMMIT_ACK ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_WEN ," in_COMMIT_WEN ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_PACKET_ID ," in_COMMIT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_commit); +//ALLOC1_SC_SIGNAL( in_COMMIT_OPERATION ," in_COMMIT_OPERATION ",Toperation_t ,_param->_nb_inst_commit); +//ALLOC1_SC_SIGNAL( in_COMMIT_TYPE ," in_COMMIT_TYPE ",Ttype_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_FLAGS ," in_COMMIT_FLAGS ",Tspecial_data_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_EXCEPTION ," in_COMMIT_EXCEPTION ",Texception_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_NO_SEQUENCE ," in_COMMIT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD ,"out_COMMIT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL ,"out_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ACK ," in_REEXECUTE_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_CONTEXT_ID ,"out_REEXECUTE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_FRONT_END_ID ,"out_REEXECUTE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_PACKET_ID ,"out_REEXECUTE_PACKET_ID ",Tpacket_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_OPERATION ,"out_REEXECUTE_OPERATION ",Toperation_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_TYPE ,"out_REEXECUTE_TYPE ",Ttype_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"out_REEXECUTE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,"out_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ," in_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,"out_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,"out_BRANCH_COMPLETE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,"out_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC_SC_SIGNAL (out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL (out_UPDATE_FRONT_END_ID ,"out_UPDATE_FRONT_END_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL (out_UPDATE_DEPTH ,"out_UPDATE_DEPTH ",Tdepth_t ); + ALLOC_SC_SIGNAL (out_UPDATE_TYPE ,"out_UPDATE_TYPE ",Tevent_type_t ); + ALLOC_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,"out_UPDATE_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS ,"out_UPDATE_ADDRESS ",Taddress_t ); + ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); + ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Taddress_t ); + + ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Taddress_t,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Taddress_t,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL," in_EVENT_ADDRESS_NEXT_VAL",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL( in_SPR_READ_SR_OVE ," in_SPR_READ_SR_OVE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_F_VAL ,"out_SPR_WRITE_SR_F_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_F ,"out_SPR_WRITE_SR_F ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_CY_VAL ,"out_SPR_WRITE_SR_CY_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_CY ,"out_SPR_WRITE_SR_CY ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_OV_VAL ,"out_SPR_WRITE_SR_OV_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_WRITE_SR_OV ,"out_SPR_WRITE_SR_OV ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Commit_unit.\n"),name.c_str()); + + (*(_Commit_unit->in_CLOCK)) (*(in_CLOCK)); + (*(_Commit_unit->in_NRESET)) (*(in_NRESET)); + + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_INSERT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Commit_unit,out_INSERT_PACKET_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RA_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RB_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RC_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_RETIRE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +//INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_VAL ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_ACK ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_WEN ,_param->_nb_inst_commit); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_PACKET_ID ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_OPERATION ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_TYPE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_FLAGS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_EXCEPTION ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_COMMIT_ADDRESS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL ); + INSTANCE_SC_SIGNAL (_Commit_unit, in_UPDATE_ACK ); + if (_param->_have_port_context_id) + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_CONTEXT_ID ); + if (_param->_have_port_front_end_id) + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_FRONT_END_ID ); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_DEPTH ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_TYPE ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_IS_DELAY_SLOT ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EPCR ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR_VAL ); + INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_ADDRESS_EEAR ); + + INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_ADDRESS ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_EVENT_IS_DS_TAKE ,_param->_nb_front_end, _param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_Commit_unit, in_SPR_READ_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit, in_SPR_WRITE_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_F_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_F ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_CY_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_CY ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Commit_unit,out_SPR_WRITE_SR_OV ,_param->_nb_front_end,_param->_nb_context[it1]); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_Commit_unit, in_DEPTH_MIN [i][j]); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + const int32_t percent_transaction_insert = 75; + const int32_t percent_transaction_retire = 75; + const int32_t percent_transaction_commit = 75; + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + for (uint32_t iteration=0; iteration_nb_rename_unit][max(_param->_nb_inst_insert,_param->_nb_rename_unit)]; + list tab_address_commit; + + uint32_t nb_transaction_insert = 0; + uint32_t nb_transaction_retire = 0; + uint32_t nb_transaction_commit = 0; + + + uint32_t packet_id_head_grp = 0; + uint32_t packet_id_head_elt = 0; + + uint32_t packet_id_tail_grp = 0; + uint32_t packet_id_tail_elt = 0; + + rob_entry_t rob [_param->_nb_bank*_param->_size_bank]; + + for (uint32_t i=0; i<_param->_nb_bank*_param->_size_bank; i++) + rob[i].val = false; + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + tab_address_insert [i][j] = address_insert_next ++; + +// while ((address_insert_next < address_insert_max) or +// (not tab_address_commit.empty()) or +// (nb_transaction_retire < (address_insert_max-address_insert_min))) + while (nb_transaction_retire < nb_transaction) + { + LABEL("Condition d'arrêt :"); + LABEL(" * total of transaction : %d",nb_transaction); + LABEL(" * nb_transaction_insert : %d",nb_transaction_insert); + LABEL(" * nb_transaction_commit : %d",nb_transaction_commit); + LABEL(" * nb_transaction_retire : %d",nb_transaction_retire); + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + bool val = ((rand()%100)_nb_inst_insert[i]); + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + Taddress_t addr = tab_address_insert [i][j]; + in_INSERT_VAL [i][j]->write(val and (i <= nb_val) and ((nb_transaction_insert+i*_param->_nb_rename_unit+j)write(0); + in_INSERT_CONTEXT_ID [i][j]->write(0); + in_INSERT_DEPTH [i][j]->write(0); + in_INSERT_TYPE [i][j]->write(0); + in_INSERT_OPERATION [i][j]->write(0); + in_INSERT_IS_DELAY_SLOT [i][j]->write(0); + in_INSERT_NO_EXECUTE [i][j]->write(0); + in_INSERT_ADDRESS [i][j]->write(addr); + in_INSERT_EXCEPTION [i][j]->write(0); + in_INSERT_EXCEPTION_USE [i][j]->write(0); + in_INSERT_STORE_QUEUE_PTR_WRITE [i][j]->write(0); + in_INSERT_LOAD_QUEUE_PTR_WRITE [i][j]->write(0); + in_INSERT_READ_RA [i][j]->write(0); + in_INSERT_NUM_REG_RA_LOG [i][j]->write(0); + in_INSERT_NUM_REG_RA_PHY [i][j]->write(0); + in_INSERT_READ_RB [i][j]->write(0); + in_INSERT_NUM_REG_RB_LOG [i][j]->write(0); + in_INSERT_NUM_REG_RB_PHY [i][j]->write(0); + in_INSERT_READ_RC [i][j]->write(0); + in_INSERT_NUM_REG_RC_LOG [i][j]->write(0); + in_INSERT_NUM_REG_RC_PHY [i][j]->write(0); + in_INSERT_WRITE_RD [i][j]->write(0); + in_INSERT_NUM_REG_RD_LOG [i][j]->write(0); + in_INSERT_NUM_REG_RD_PHY_OLD [i][j]->write(0); + in_INSERT_NUM_REG_RD_PHY_NEW [i][j]->write(0); + in_INSERT_WRITE_RE [i][j]->write(0); + in_INSERT_NUM_REG_RE_LOG [i][j]->write(0); + in_INSERT_NUM_REG_RE_PHY_OLD [i][j]->write(0); + in_INSERT_NUM_REG_RE_PHY_NEW [i][j]->write(0); + } + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + bool ack = ((rand()%100)_nb_inst_retire[i]; + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + { + in_RETIRE_ACK [i][j]->write(ack and (i <= nb_ack)); + + } + } + + { + list::iterator it=tab_address_commit.begin(); + + for (uint32_t j=0; j<_param->_nb_inst_commit; j++) + { + Tcontrol_t val = ((rand()%100)write(val); + + if (val) + { + Tpacket_t packet = *(it); + + in_COMMIT_WEN [j]->write(1); + in_COMMIT_PACKET_ID [j]->write(packet); + //in_COMMIT_OPERATION [j]->write(0); + //in_COMMIT_TYPE [j]->write(0); + in_COMMIT_FLAGS [j]->write(0); + in_COMMIT_EXCEPTION [j]->write(0); + in_COMMIT_NO_SEQUENCE [j]->write(0); + in_COMMIT_ADDRESS [j]->write(0); + } + + if (it != tab_address_commit.end()) + it++; + } + } + + SC_START(0); + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + LABEL("INSERT [%d][%d] - %d %d",i,j,in_INSERT_VAL [i][j]->read(),out_INSERT_ACK [i][j]->read()); + if ( in_INSERT_VAL [i][j]->read() and + out_INSERT_ACK [i][j]->read()) + { + LABEL("INSERT [%d][%d] Transaction Accepted",i,j); + LABEL(" * packet_id_tail_grp (old) : %d",packet_id_tail_grp); + LABEL(" * packet_id_tail_elt (old) : %d",packet_id_tail_elt); + + Tpacket_t packet = (_param->_have_port_rob_ptr )?out_INSERT_PACKET_ID [i][j]->read():0; + + TEST(Tpacket_t, packet, (packet_id_tail_grp << _param->_shift_num_bank) + packet_id_tail_elt); + + TEST(bool, rob[packet].val, false); + + rob[packet].val = true; + rob[packet].address = tab_address_insert [i][j]; + + tab_address_commit.push_back(packet); + tab_address_insert [i][j] = address_insert_next ++; + + packet_id_tail_grp ++; + + if (packet_id_tail_grp >= _param->_nb_bank) + { + packet_id_tail_grp = 0; + packet_id_tail_elt = (packet_id_tail_elt+1)%_param->_size_bank; + } + + LABEL(" * packet_id_tail_grp (new) : %d",packet_id_tail_grp); + LABEL(" * packet_id_tail_elt (new) : %d",packet_id_tail_elt); + + nb_transaction_insert ++; + } + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + { + LABEL("RETIRE [%d][%d] - %d %d",i,j,out_RETIRE_VAL [i][j]->read(),in_RETIRE_ACK [i][j]->read()); + if (out_RETIRE_VAL [i][j]->read() and + in_RETIRE_ACK [i][j]->read()) + { + LABEL("RETIRE [%d][%d] Transaction Accepted",i,j); + LABEL(" * packet_id_head_grp (old) : %d",packet_id_head_grp); + LABEL(" * packet_id_head_elt (old) : %d",packet_id_head_elt); + + Tpacket_t packet = ((packet_id_head_grp << _param->_shift_num_bank) + packet_id_head_elt); + + TEST(bool, rob[packet].val, true); + + rob[packet].val = false; + + packet_id_head_grp ++; + + if (packet_id_head_grp >= _param->_nb_bank) + { + packet_id_head_grp = 0; + packet_id_head_elt = (packet_id_head_elt+1)%_param->_size_bank; + } + + LABEL(" * packet_id_head_grp (new) : %d",packet_id_head_grp); + LABEL(" * packet_id_head_elt (new) : %d",packet_id_head_elt); + + nb_transaction_retire ++; + } + } + + LABEL("Dump tab_address_commit (before)"); + for (list::iterator it=tab_address_commit.begin(); + it!=tab_address_commit.end(); + ++it) + LABEL(" * %d",*it); + + { + list::iterator it=tab_address_commit.begin(); + + for (uint32_t j=0; j<_param->_nb_inst_commit; j++) + { + if ( in_COMMIT_VAL [j]->read() and + out_COMMIT_ACK [j]->read()) + { + LABEL("COMMIT [%d] Transaction Accepted",j); + + it = tab_address_commit.erase(it); + + nb_transaction_commit ++; + } + else + if (it != tab_address_commit.end()) + it++; + } + } + + LABEL("Dump tab_address_commit (after )"); + for (list::iterator it=tab_address_commit.begin(); + it!=tab_address_commit.end(); + ++it) + LABEL(" * %d",*it); + + + SC_START(1); + } + + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_INSERT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_PACKET_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RA_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RB_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RC_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL( in_RETIRE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +//DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE2_SC_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + DELETE1_SC_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_ACK ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_WEN ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_PACKET_ID ,_param->_nb_inst_commit); +//DELETE1_SC_SIGNAL( in_COMMIT_OPERATION ,_param->_nb_inst_commit); +//DELETE1_SC_SIGNAL( in_COMMIT_TYPE ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_FLAGS ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_EXCEPTION ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_ADDRESS ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); + DELETE_SC_SIGNAL (out_UPDATE_VAL ); + DELETE_SC_SIGNAL ( in_UPDATE_ACK ); + DELETE_SC_SIGNAL (out_UPDATE_CONTEXT_ID ); + DELETE_SC_SIGNAL (out_UPDATE_FRONT_END_ID ); + DELETE_SC_SIGNAL (out_UPDATE_DEPTH ); + DELETE_SC_SIGNAL (out_UPDATE_TYPE ); + DELETE_SC_SIGNAL (out_UPDATE_IS_DELAY_SLOT ); + DELETE_SC_SIGNAL (out_UPDATE_ADDRESS ); + DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ); + DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ); + DELETE_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ); + + DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end, _param->_nb_context[it1]); + + DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + + DELETE2_SC_SIGNAL( in_SPR_READ_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); + + DELETE2_SC_SIGNAL(out_SPR_WRITE_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_WRITE_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_F_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_F ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_CY_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_CY ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_WRITE_SR_OV ,_param->_nb_front_end,_param->_nb_context[it1]); + } +#endif + + delete _Commit_unit; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Commit_unit.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Commit_unit.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Commit_unit.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Commit\_unit} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 88) @@ -0,0 +1,309 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Commit_unit_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + + class Commit_unit +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; + public : counter_t ** _stat_nb_inst_insert; + public : counter_t * _stat_nb_inst_commit; + public : counter_t * _stat_nb_inst_commit_conflit_access; + public : counter_t ** _stat_nb_inst_retire; + public : counter_t ** _stat_bank_nb_inst;// [nb_bank] +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_INSERT_VAL ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ACK ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontext_t ) *** in_INSERT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontext_t ) *** in_INSERT_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tpacket_t ) *** out_INSERT_PACKET_ID ;//[nb_rename_unit][nb_inst_insert] +//public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tdepth_t ) *** in_INSERT_DEPTH ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Ttype_t ) *** in_INSERT_TYPE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Toperation_t ) *** in_INSERT_OPERATION ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_data_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RA ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_LOG ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RB ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_LOG ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_READ_RC ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_LOG ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_WRITE_RE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_VAL ;//[nb_rename_unit][nb_inst_retire] + public : SC_IN (Tcontrol_t ) *** in_RETIRE_ACK ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontext_t ) *** out_RETIRE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontext_t ) *** out_RETIRE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_retire] +//public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tevent_state_t ) *** out_RETIRE_EVENT_STATE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_STORE_QUEUE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_USE_LOAD_QUEUE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tlsq_ptr_t ) *** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RA ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RB ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_READ_RC ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RD ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_LOG ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tcontrol_t ) *** out_RETIRE_WRITE_RE ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_LOG ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] + public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] + + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_COMMIT_VAL ;//[nb_inst_commit] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_ACK ;//[nb_inst_commit] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_WEN ;//[nb_inst_commit] + public : SC_IN (Tpacket_t ) ** in_COMMIT_PACKET_ID ;//[nb_inst_commit] +//public : SC_IN (Toperation_t ) ** in_COMMIT_OPERATION ;//[nb_inst_commit] +//public : SC_IN (Ttype_t ) ** in_COMMIT_TYPE ;//[nb_inst_commit] + public : SC_IN (Tspecial_data_t ) ** in_COMMIT_FLAGS ;//[nb_inst_commit] + public : SC_IN (Texception_t ) ** in_COMMIT_EXCEPTION ;//[nb_inst_commit] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] + public : SC_IN (Tgeneral_data_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit] + public : SC_OUT(Tgeneral_address_t ) ** out_COMMIT_NUM_REG_RD ;//[nb_inst_commit] + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_VAL ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_ACK ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tpacket_t ) ** out_REEXECUTE_PACKET_ID ;//[nb_inst_reexecute] + public : SC_OUT(Toperation_t ) ** out_REEXECUTE_OPERATION ;//[nb_inst_reexecute] + public : SC_OUT(Ttype_t ) ** out_REEXECUTE_TYPE ;//[nb_inst_reexecute] + public : SC_OUT(Tlsq_ptr_t ) ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_CONTEXT_ID ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_FRONT_END_ID ;//[nb_inst_branch_complete] + public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] + public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] + + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ; + public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ; + public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ; + public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ; + public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ; + public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ; + public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; + public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; + public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; + public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EEAR ; + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS ;//[nb_front_end][nb_context] + public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS_NEXT ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_EVENT_ADDRESS_NEXT_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_EVENT_IS_DS_TAKE ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] + public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_SPR_READ_SR_OVE ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_WRITE_ACK ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_F ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_CY ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_WRITE_SR_OV ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority_insert ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : std::list * _rob ;//[nb_bank] + + private : uint32_t reg_NUM_BANK_HEAD ; + private : uint32_t reg_NUM_BANK_TAIL ; + private : uint32_t * reg_BANK_PTR ;//[nb_bank] + + private : Tcounter_t ** reg_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] + private : Tcounter_t ** reg_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tcontrol_t * internal_BANK_INSERT_VAL ;//[nb_bank] + private : uint32_t * internal_BANK_INSERT_NUM_RENAME_UNIT ;//[nb_bank] + private : uint32_t * internal_BANK_INSERT_NUM_INST ;//[nb_bank] + +#ifdef STATISTICS + private : uint32_t internal_BANK_COMMIT_CONFLIT_ACCESS ; +#endif + private : Tcontrol_t ** internal_BANK_COMMIT_VAL ;//[nb_bank][nb_bank_access_commit] + private : uint32_t ** internal_BANK_COMMIT_NUM_INST ;//[nb_bank][nb_bank_access_commit] + private : entry_t * ** internal_BANK_COMMIT_ENTRY ;//[nb_bank][nb_bank_access_commit] + + private : Tcontrol_t * internal_BANK_RETIRE_VAL ;//[nb_bank] + private : uint32_t * internal_BANK_RETIRE_NUM_RENAME_UNIT ;//[nb_bank] + private : uint32_t * internal_BANK_RETIRE_NUM_INST ;//[nb_bank] + + private : Tcontrol_t * internal_REEXECUTE_VAL ;//[nb_inst_reexecute] + private : uint32_t * internal_REEXECUTE_NUM_BANK ;//[nb_inst_reexecute] + + private : Tcontrol_t * internal_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] + private : uint32_t * internal_BRANCH_COMPLETE_NUM_BANK ;//[nb_inst_branch_complete] + + private : Tcontrol_t internal_UPDATE_VAL ; + private : uint32_t internal_UPDATE_NUM_BANK ; + + private : Tcontrol_t ** internal_EVENT_ACK ;//[nb_front_end][nb_context] +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Commit_unit); +#endif + public : Commit_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Commit_unit (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); + public : void genMoore (void); + public : void genMealy_insert (void); + public : void genMealy_retire (void); + public : void genMealy_commit (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h (revision 88) @@ -0,0 +1,113 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_rename_unit ; + public : uint32_t _size_queue ; + public : uint32_t _nb_bank ; + public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] + public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] + public : uint32_t _nb_inst_commit ; + public : uint32_t _nb_inst_reexecute ; + public : uint32_t _nb_inst_branch_complete ; + public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] +//public : uint32_t _size_general_data ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; + public : Tpriority_t _priority ; + public : Tload_balancing_t _load_balancing ; + public : uint32_t _nb_rename_unit_select ; + public : const uint32_t _nb_bank_access_commit ; + public : const retire_ooo_t _retire_ooo ; + + public : uint32_t _max_nb_context ; + public : uint32_t _max_nb_inst_insert ; + public : uint32_t _max_nb_inst_retire ; +//public : uint32_t _size_address ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; + public : uint32_t _size_rename_unit_id ; + public : uint32_t _size_bank ; +//public : uint32_t _size_nb_inst ; +//public : uint32_t _size_packet_id ; + public : uint32_t ** _array_size_depth ;//[nb_front_end][nb_context] +//public : uint32_t _max_size_depth ; + public : Tpacket_t _shift_num_bank ; + public : Tpacket_t _mask_size_bank ; + +//public : bool _have_port_front_end_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_packet_id ; + public : bool _have_port_rename_unit_id; +//public : bool _have_port_load_queue_ptr; +//public : bool _have_port_max_depth ; +//public : bool ** _have_port_depth ;//[nb_front_end][nb_context] + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_rename_unit , + uint32_t size_queue , + uint32_t nb_bank , + uint32_t * nb_inst_insert , + uint32_t * nb_inst_retire , + uint32_t nb_inst_commit , + uint32_t nb_inst_reexecute , + uint32_t nb_inst_branch_complete , + uint32_t ** nb_branch_speculated , + uint32_t size_general_data , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + uint32_t size_general_register , + uint32_t size_special_register , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t nb_rename_unit_select , + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters (void) ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters & x); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Types.h (revision 88) @@ -0,0 +1,184 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_commit_unit_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + typedef enum + { + RETIRE_IN_ORDER , + RETIRE_OOO_RENAME_UNIT, + RETIRE_OOO_CONTEXT + } retire_ooo_t; + + typedef enum + { + ROB_EMPTY , // + ROB_BRANCH_WAIT_END , // + ROB_BRANCH_COMPLETE , // + ROB_STORE_WAIT_HEAD_OK , // +// ROB_STORE_WAIT_HEAD_KO , // + ROB_STORE_HEAD_OK , // + ROB_STORE_HEAD_KO , // + ROB_OTHER_WAIT_END , // + ROB_MISS_WAIT_END , // + ROB_END_OK_SPECULATIVE , // + ROB_END_OK , // + ROB_END_KO_SPECULATIVE , // + ROB_END_KO , // + ROB_END_MISS , // + ROB_END_EXCEPTION_WAIT_HEAD , // + ROB_END_EXCEPTION // + } rob_state_t; + + class entry_t + { + public : rob_state_t state ; + public : uint32_t ptr ; + public : Tcontext_t front_end_id ; + public : Tcontext_t context_id ; + public : uint32_t rename_unit_id ; + public : Tdepth_t depth ; + public : Ttype_t type ; + public : Toperation_t operation ; + public : Tcontrol_t is_delay_slot ; + public : Tgeneral_data_t address ; + public : Tcontrol_t use_store_queue ; + public : Tcontrol_t use_load_queue ; + public : Tlsq_ptr_t store_queue_ptr_write ; + public : Tlsq_ptr_t load_queue_ptr_write ; + public : Tcontrol_t read_ra ; + public : Tgeneral_address_t num_reg_ra_log ; + public : Tgeneral_address_t num_reg_ra_phy ; + public : Tcontrol_t read_rb ; + public : Tgeneral_address_t num_reg_rb_log ; + public : Tgeneral_address_t num_reg_rb_phy ; + public : Tcontrol_t read_rc ; + public : Tspecial_address_t num_reg_rc_log ; + public : Tspecial_address_t num_reg_rc_phy ; + public : Tcontrol_t write_rd ; + public : Tgeneral_address_t num_reg_rd_log ; + public : Tgeneral_address_t num_reg_rd_phy_old ; + public : Tgeneral_address_t num_reg_rd_phy_new ; + public : Tcontrol_t write_re ; + public : Tspecial_address_t num_reg_re_log ; + public : Tspecial_address_t num_reg_re_phy_old ; + public : Tspecial_address_t num_reg_re_phy_new ; + + public : Tevent_state_t event_state ; + public : Texception_t exception ; + public : Texception_t exception_use ; + + public : Tspecial_data_t flags ; + public : Tcontrol_t no_sequence ; + public : Tgeneral_data_t data_commit ; // branch's destination + +// public : entry_t (uint32_t ptr , +// Tcontext_t front_end_id , +// Tcontext_t context_id , +// Tcontext_t rename_unit_id , +// Tdepth_t depth , +// Ttype_t type , +// Toperation_t operation , +// Tcontrol_t is_delay_slot , +// Tgeneral_data_t address , +// Texception_t exception , +// Texception_t exception_use , +// Tlsq_ptr_t store_queue_ptr_write , +// Tlsq_ptr_t load_queue_ptr_write , +// Tcontrol_t read_ra , +// Tgeneral_address_t num_reg_ra_log , +// Tgeneral_address_t num_reg_ra_phy , +// Tcontrol_t read_rb , +// Tgeneral_address_t num_reg_rb_log , +// Tgeneral_address_t num_reg_rb_phy , +// Tcontrol_t read_rc , +// Tspecial_address_t num_reg_rc_log , +// Tspecial_address_t num_reg_rc_phy , +// Tcontrol_t write_rd , +// Tgeneral_address_t num_reg_rd_log , +// Tgeneral_address_t num_reg_rd_phy_old , +// Tgeneral_address_t num_reg_rd_phy_new , +// Tcontrol_t write_re , +// Tspecial_address_t num_reg_re_log , +// Tspecial_address_t num_reg_re_phy_old , +// Tspecial_address_t num_reg_re_phy_new ) +// { +// this->ptr = ptr ; +// this->front_end_id = front_end_id ; +// this->context_id = context_id ; +// this->rename_unit_id = rename_unit_id ; +// this->depth = depth ; +// this->type = type ; +// this->operation = operation ; +// this->is_delay_slot = is_delay_slot ; +// this->address = address ; +// this->exception = exception ; +// this->exception_use = exception_use ; +// this->store_queue_ptr_write = store_queue_ptr_write ; +// this->load_queue_ptr_write = load_queue_ptr_write ; +// this->read_ra = read_ra ; +// this->num_reg_ra_log = num_reg_ra_log ; +// this->num_reg_ra_phy = num_reg_ra_phy ; +// this->read_rb = read_rb ; +// this->num_reg_rb_log = num_reg_rb_log ; +// this->num_reg_rb_phy = num_reg_rb_phy ; +// this->read_rc = read_rc ; +// this->num_reg_rc_log = num_reg_rc_log ; +// this->num_reg_rc_phy = num_reg_rc_phy ; +// this->write_rd = write_rd ; +// this->num_reg_rd_log = num_reg_rd_log ; +// this->num_reg_rd_phy_old = num_reg_rd_phy_old ; +// this->num_reg_rd_phy_new = num_reg_rd_phy_new ; +// this->write_re = write_re ; +// this->num_reg_re_log = num_reg_re_log ; +// this->num_reg_re_phy_old = num_reg_re_phy_old ; +// this->num_reg_re_phy_new = num_reg_re_phy_new ; +// } + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural + + template<> inline std::string toString(const morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::rob_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_EMPTY : return "empty" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_WAIT_END : return "branch_wait_end" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_BRANCH_COMPLETE : return "branch_complete" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_OK : return "store_wait_head_ok" ; break; +// case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_WAIT_HEAD_KO : return "store_wait_head_ko" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_OK : return "store_head_ok" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_STORE_HEAD_KO : return "store_head_ko" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_OTHER_WAIT_END : return "other_wait_end" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_MISS_WAIT_END : return "miss_wait_end" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK_SPECULATIVE : return "end_ok_speculative" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_OK : return "end_ok" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO_SPECULATIVE : return "end_ko_speculative" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_KO : return "end_ko" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION_WAIT_HEAD : return "end_exception_wait_head" ; break; + case morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::ROB_END_EXCEPTION : return "end_exception" ; break; + default : return "" ; break; + } + }; + +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit.cpp (revision 88) @@ -0,0 +1,290 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::Commit_unit" + Commit_unit::Commit_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Commit_unit,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Commit_unit == true + log_printf(TRACE,Commit_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Constant + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + internal_EVENT_ACK [i][j] = 1; + PORT_WRITE(out_EVENT_ACK [i][j], internal_EVENT_ACK [i][j]); + } + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Method - genMoore"),_name.c_str()); + + SC_METHOD (genMoore); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Method - genMealy_insert"),_name.c_str()); + + SC_METHOD (genMealy_insert); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register +// for (uint32_t i=0; i<_param->_nb_rename_unit; i++) +// for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) +// sensitive << (*(in_INSERT_VAL [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + for (uint32_t x=0; x<_param->_nb_rename_unit; x++) + for (uint32_t y=0; y<_param->_nb_inst_insert[x]; y++) + { + (*(out_INSERT_ACK [i][j])) (*(in_INSERT_VAL [x][y])); + if (_param->_have_port_rob_ptr) + (*(out_INSERT_PACKET_ID [i][j])) (*(in_INSERT_VAL [x][y])); + } +# endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Method - genMealy_retire"),_name.c_str()); + + SC_METHOD (genMealy_retire); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + sensitive << (*(in_RETIRE_ACK [i][j])); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + sensitive << (*(in_SPR_WRITE_ACK [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + { + for (uint32_t x=0; x<_param->_nb_rename_unit; x++) + for (uint32_t y=0; y<_param->_nb_inst_retire[x]; y++) + { + (*(out_RETIRE_VAL [i][j])) (*(in_RETIRE_ACK [x][y])); + if (_param->_have_port_front_end_id) + (*(out_RETIRE_FRONT_END_ID [i][j])) (*(in_RETIRE_ACK [x][y])); + if (_param->_have_port_context_id) + (*(out_RETIRE_CONTEXT_ID [i][j])) (*(in_RETIRE_ACK [x][y])); +// (*(out_RETIRE_RENAME_UNIT_ID [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_EVENT_STATE [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_USE_STORE_QUEUE [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_USE_LOAD_QUEUE [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_RETIRE_ACK [x][y])); + if (_param->_have_port_load_queue_ptr) + (*(out_RETIRE_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_READ_RA [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RA_PHY [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_READ_RB [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RB_PHY [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_READ_RC [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RC_PHY [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_WRITE_RD [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_LOG [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_PHY_OLD [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_PHY_NEW [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_WRITE_RE [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_LOG [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_PHY_OLD [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_PHY_NEW [i][j])) (*(in_RETIRE_ACK [x][y])); + } + + for (uint32_t x=0; x<_param->_nb_front_end; ++x) + for (uint32_t y=0; y<_param->_nb_context[x]; ++y) + { + (*(out_RETIRE_VAL [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + if (_param->_have_port_front_end_id) + (*(out_RETIRE_FRONT_END_ID [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + if (_param->_have_port_context_id) + (*(out_RETIRE_CONTEXT_ID [i][j])) (*(in_SPR_WRITE_ACK [x][y])); +// (*(out_RETIRE_RENAME_UNIT_ID [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_EVENT_STATE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_USE_STORE_QUEUE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_USE_LOAD_QUEUE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_STORE_QUEUE_PTR_WRITE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + if (_param->_have_port_load_queue_ptr) + (*(out_RETIRE_LOAD_QUEUE_PTR_WRITE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_READ_RA [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RA_PHY [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_READ_RB [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RB_PHY [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_READ_RC [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RC_PHY [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_WRITE_RD [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_LOG [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_PHY_OLD [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RD_PHY_NEW [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_WRITE_RE [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_LOG [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_PHY_OLD [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_RETIRE_NUM_REG_RE_PHY_NEW [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + } + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + for (uint32_t x=0; x<_param->_nb_rename_unit; x++) + for (uint32_t y=0; y<_param->_nb_inst_retire[x]; y++) + { + (*(out_SPR_WRITE_VAL [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_F_VAL [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_F [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_CY_VAL [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_CY [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_OV_VAL [i][j])) (*(in_RETIRE_ACK [x][y])); + (*(out_SPR_WRITE_SR_OV [i][j])) (*(in_RETIRE_ACK [x][y])); + } + + for (uint32_t x=0; x<_param->_nb_front_end; ++x) + for (uint32_t y=0; y<_param->_nb_context[x]; ++y) + { + (*(out_SPR_WRITE_VAL [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_F_VAL [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_F [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_CY_VAL [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_CY [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_OV_VAL [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + (*(out_SPR_WRITE_SR_OV [i][j])) (*(in_SPR_WRITE_ACK [x][y])); + } + } +# endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Method - genMealy_commit"),_name.c_str()); + + SC_METHOD (genMealy_commit); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t j=0; j<_param->_nb_inst_commit; j++) + { + sensitive << (*(in_COMMIT_VAL [j])); + if (_param->_have_port_rob_ptr) + sensitive << (*(in_COMMIT_PACKET_ID [j])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t j=0; j<_param->_nb_inst_commit; j++) + for (uint32_t y=0; y<_param->_nb_inst_commit; y++) + { + (*(out_COMMIT_ACK [j])) (*(in_COMMIT_VAL [y])); + if (_param->_have_port_rob_ptr) + (*(out_COMMIT_ACK [j])) (*(in_COMMIT_PACKET_ID [y])); + } +# endif + +#endif + } + log_end(Commit_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Commit_unit::~Commit_unit" + Commit_unit::~Commit_unit (void) + { + log_begin(Commit_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> Deallocation"),_name.c_str()); + deallocation (); + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 88) @@ -0,0 +1,309 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + + +#undef FUNCTION +#define FUNCTION "Commit_unit::allocation" + void Commit_unit::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Commit_unit,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Commit_unit" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("insert", IN, SOUTH, _("Interface with rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + _ALLOC2_VALACK_IN ( in_INSERT_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_VALACK_OUT(out_INSERT_ACK ,ACK,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +// _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + } + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("retire",OUT,SOUTH, _("Interface to update rename_unit."),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + _ALLOC2_VALACK_OUT(out_RETIRE_VAL ,VAL,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_VALACK_IN ( in_RETIRE_ACK ,ACK,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_ID ,"rename_unit_id" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + _ALLOC2_SIGNAL_OUT(out_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + } + + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("commit",IN,EAST,_("End of execute."),_param->_nb_inst_commit); + + ALLOC1_VALACK_IN ( in_COMMIT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_COMMIT_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_COMMIT_WEN ,"wen" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_COMMIT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC1_SIGNAL_IN ( in_COMMIT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC1_SIGNAL_IN ( in_COMMIT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_IN ( in_COMMIT_FLAGS ,"flags" ,Tspecial_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_IN ( in_COMMIT_NO_SEQUENCE ,"no_sequence",Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_COMMIT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); +// ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id); + ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + } + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("reexecute",OUT,EAST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_reexecute); + + ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_REEXECUTE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Interface to reexecute an instruction (store)"),_param->_nb_inst_branch_complete); + + ALLOC1_VALACK_OUT(out_BRANCH_COMPLETE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); + } + + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC_INTERFACE("update", OUT, WEST,_("Interface with to Context State.")); + + ALLOC_VALACK_OUT(out_UPDATE_VAL ,VAL); + ALLOC_VALACK_IN ( in_UPDATE_ACK ,ACK); + ALLOC_SIGNAL_OUT(out_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC_SIGNAL_OUT(out_UPDATE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC_SIGNAL_OUT(out_UPDATE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC_SIGNAL_OUT(out_UPDATE_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); + ALLOC_SIGNAL_OUT(out_UPDATE_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1); + ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); + ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Taddress_t ,_param->_size_instruction_address); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("event",IN,WEST,_("Interface with Context State (event)."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_EVENT_ACK , ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t,_param->_size_instruction_address,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t,_param->_size_instruction_address,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"ADDRESS_NEXT_VAL",Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("nb_inst",OUT,WEST,_("Interface with Context State (synchronization)."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"commit_all",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"commit_mem",Tcounter_t ,_param->_size_nb_inst_commit,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"min" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"max" ,Tdepth_t ,_param->_size_depth+1,_param->_nb_front_end, _param->_nb_context[it1]); + } + + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_read",IN ,EAST,_("Interface with special register file (read)."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR_OVE ,"sr_ove" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_write",OUT,EAST,_("Interface with special register file (write)."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_OUT(out_SPR_WRITE_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_IN ( in_SPR_WRITE_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_F_VAL ,"sr_f_val" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_F ,"sr_f" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_CY_VAL ,"sr_cy_val" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_CY ,"sr_cy" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_WRITE_SR_OV ,"sr_ov" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + internal_BANK_INSERT_VAL = new Tcontrol_t [_param->_nb_bank]; + internal_BANK_INSERT_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; + internal_BANK_INSERT_NUM_INST = new uint32_t [_param->_nb_bank]; + + internal_BANK_COMMIT_VAL = new Tcontrol_t * [_param->_nb_bank]; + internal_BANK_COMMIT_NUM_INST = new uint32_t * [_param->_nb_bank]; + internal_BANK_COMMIT_ENTRY = new entry_t ** [_param->_nb_bank]; + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + internal_BANK_COMMIT_VAL [i] = new Tcontrol_t [_param->_nb_bank_access_commit]; + internal_BANK_COMMIT_NUM_INST [i] = new uint32_t [_param->_nb_bank_access_commit]; + internal_BANK_COMMIT_ENTRY [i] = new entry_t * [_param->_nb_bank_access_commit]; + } + + internal_BANK_RETIRE_VAL = new Tcontrol_t [_param->_nb_bank]; + internal_BANK_RETIRE_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; + internal_BANK_RETIRE_NUM_INST = new uint32_t [_param->_nb_bank]; + + internal_REEXECUTE_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; + internal_REEXECUTE_NUM_BANK = new uint32_t [_param->_nb_inst_reexecute]; + + internal_BRANCH_COMPLETE_VAL = new Tcontrol_t [_param->_nb_inst_branch_complete]; + internal_BRANCH_COMPLETE_NUM_BANK = new uint32_t [_param->_nb_inst_branch_complete]; + + internal_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; + for (uint32_t i=0; i<_param->_nb_front_end; i++) + internal_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _rob = new std::list [_param->_nb_bank]; + + reg_BANK_PTR = new uint32_t [_param->_nb_bank]; + + reg_NB_INST_COMMIT_ALL = new Tcounter_t * [_param->_nb_front_end]; + reg_NB_INST_COMMIT_MEM = new Tcounter_t * [_param->_nb_front_end]; + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + reg_NB_INST_COMMIT_ALL [i] = new Tcounter_t [_param->_nb_context [i]]; + reg_NB_INST_COMMIT_MEM [i] = new Tcounter_t [_param->_nb_context [i]]; + } + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority_insert = new generic::priority::Priority (_name+"_priority_insert", + _param->_priority , + _param->_load_balancing, + _param->_nb_rename_unit, + _param->_nb_inst_insert, + _param->_nb_rename_unit_select); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 88) @@ -0,0 +1,207 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::deallocation" + void Commit_unit::deallocation (void) + { + log_begin(Commit_unit,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_INSERT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_INSERT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); + DELETE2_SIGNAL(out_INSERT_PACKET_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rob_ptr ); +// DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id ); + DELETE2_SIGNAL( in_INSERT_DEPTH ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_INSERT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); + DELETE2_SIGNAL( in_INSERT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_INSERT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_IS_DELAY_SLOT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_ADDRESS ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_instruction_address ); + DELETE2_SIGNAL( in_INSERT_EXCEPTION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); + DELETE2_SIGNAL( in_INSERT_EXCEPTION_USE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_exception ); + DELETE2_SIGNAL( in_INSERT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL( in_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL( in_INSERT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); + DELETE2_SIGNAL( in_INSERT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); + DELETE2_SIGNAL( in_INSERT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); + DELETE2_SIGNAL( in_INSERT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register ); + DELETE2_SIGNAL( in_INSERT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); + DELETE2_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register ); + + DELETE2_SIGNAL(out_RETIRE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL( in_RETIRE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL(out_RETIRE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_context_id ); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_rename_unit_id ); + DELETE2_SIGNAL(out_RETIRE_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_event_state ); + DELETE2_SIGNAL(out_RETIRE_USE_STORE_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_USE_LOAD_QUEUE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL(out_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL(out_RETIRE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); + DELETE2_SIGNAL(out_RETIRE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); + DELETE2_SIGNAL(out_RETIRE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register ); + DELETE2_SIGNAL(out_RETIRE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register ); + DELETE2_SIGNAL(out_RETIRE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RE_LOG ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register ); + DELETE2_SIGNAL(out_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register ); + + DELETE1_SIGNAL( in_COMMIT_VAL ,_param->_nb_inst_commit,1 ); + DELETE1_SIGNAL(out_COMMIT_ACK ,_param->_nb_inst_commit,1 ); + DELETE1_SIGNAL( in_COMMIT_WEN ,_param->_nb_inst_commit,1 ); + DELETE1_SIGNAL( in_COMMIT_PACKET_ID ,_param->_nb_inst_commit,_param->_size_rob_ptr ); +// DELETE1_SIGNAL( in_COMMIT_OPERATION ,_param->_nb_inst_commit,_param->_size_operation ); +// DELETE1_SIGNAL( in_COMMIT_TYPE ,_param->_nb_inst_commit,_param->_size_type ); + DELETE1_SIGNAL( in_COMMIT_FLAGS ,_param->_nb_inst_commit,_param->_size_general_data ); + DELETE1_SIGNAL( in_COMMIT_EXCEPTION ,_param->_nb_inst_commit,_param->_size_exception ); + DELETE1_SIGNAL( in_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit,1 ); + DELETE1_SIGNAL( in_COMMIT_ADDRESS ,_param->_nb_inst_commit,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit,_param->_size_general_register+_param->_size_rename_unit_id); + + DELETE1_SIGNAL(out_REEXECUTE_VAL ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_ACK ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute,_param->_size_context_id ); + DELETE1_SIGNAL(out_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute,_param->_size_rob_ptr ); + DELETE1_SIGNAL(out_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute,_param->_size_operation ); + DELETE1_SIGNAL(out_REEXECUTE_TYPE ,_param->_nb_inst_reexecute,_param->_size_type ); + DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr); + + DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete,_param->_size_front_end_id); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1 ); + + DELETE_SIGNAL (out_UPDATE_VAL ,1 ); + DELETE_SIGNAL ( in_UPDATE_ACK ,1 ); + DELETE_SIGNAL (out_UPDATE_CONTEXT_ID ,_param->_size_context_id ); + DELETE_SIGNAL (out_UPDATE_FRONT_END_ID ,_param->_size_front_end_id); + DELETE_SIGNAL (out_UPDATE_DEPTH ,_param->_size_depth ); + DELETE_SIGNAL (out_UPDATE_TYPE ,_param->_size_event_type ); + DELETE_SIGNAL (out_UPDATE_IS_DELAY_SLOT ,1 ); + DELETE_SIGNAL (out_UPDATE_ADDRESS ,_param->_size_instruction_address ); + DELETE_SIGNAL (out_UPDATE_ADDRESS_EPCR ,_param->_size_instruction_address ); + DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,1 ); + DELETE_SIGNAL (out_UPDATE_ADDRESS_EEAR ,_param->_size_instruction_address ); + + DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_instruction_address); + DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_instruction_address); + DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end, _param->_nb_context[it1],1 ); + + DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); + DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_nb_inst_commit); + + DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_depth+1); + + DELETE2_SIGNAL( in_SPR_READ_SR_OVE ,_param->_nb_front_end, _param->_nb_context[it1],1); + + DELETE2_SIGNAL(out_SPR_WRITE_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_WRITE_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_F ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_WRITE_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1],1); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_BANK_INSERT_VAL ; + delete [] internal_BANK_INSERT_NUM_RENAME_UNIT; + delete [] internal_BANK_INSERT_NUM_INST ; + + delete [] internal_BANK_COMMIT_VAL ; + delete [] internal_BANK_COMMIT_NUM_INST ; + delete [] internal_BANK_COMMIT_ENTRY ; + + delete [] internal_BANK_RETIRE_VAL ; + delete [] internal_BANK_RETIRE_NUM_RENAME_UNIT; + delete [] internal_BANK_RETIRE_NUM_INST ; + + delete [] internal_REEXECUTE_VAL ; + delete [] internal_REEXECUTE_NUM_BANK ; + + delete [] internal_BRANCH_COMPLETE_VAL ; + delete [] internal_BRANCH_COMPLETE_NUM_BANK ; + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + delete [] internal_EVENT_ACK [i]; + delete [] internal_EVENT_ACK; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + delete [] reg_NB_INST_COMMIT_ALL [i]; + delete [] reg_NB_INST_COMMIT_MEM [i]; + } + delete [] reg_NB_INST_COMMIT_ALL; + delete [] reg_NB_INST_COMMIT_MEM; + + delete [] reg_BANK_PTR; + + delete [] _rob; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _priority_insert; + + delete _component; + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::end_cycle" +void Commit_unit::end_cycle () + { + log_begin(Commit_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_commit.cpp (revision 88) @@ -0,0 +1,106 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::genMealy_commit" + void Commit_unit::genMealy_commit (void) + { + log_begin(Commit_unit,FUNCTION); + log_function(Commit_unit,FUNCTION,_name.c_str()); + +#ifdef STATISTICS + internal_BANK_COMMIT_CONFLIT_ACCESS = 0; +#endif + + uint32_t bank_nb_access [_param->_nb_bank]; + Tcontrol_t commit_ack [_param->_nb_inst_commit]; + // Initialisation + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + bank_nb_access [i] = 0; + for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) + internal_BANK_COMMIT_VAL [i][j] = false; + } + + // commit interface + for (uint32_t i=0; i<_param->_nb_inst_commit; i++) + { + commit_ack [i] = false; + + // Test if have instruction + if (PORT_READ(in_COMMIT_VAL [i])) + { + Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(in_COMMIT_PACKET_ID [i]):0; + uint32_t num_bank = packet >> _param->_shift_num_bank; + uint32_t num_bank_access = bank_nb_access [num_bank]; + + // test if bank is not busy (previous access) + if (num_bank_access < _param->_nb_bank_access_commit) + { + // find + bank_nb_access [num_bank] ++; + commit_ack [i] = true; + + internal_BANK_COMMIT_VAL [num_bank][num_bank_access] = true; + internal_BANK_COMMIT_NUM_INST [num_bank][num_bank_access] = i; + + Tpacket_t packet_id = packet & _param->_mask_size_bank; + + // find the good entry !!! + entry_t* entry = NULL; + for (std::list::iterator it=_rob[num_bank].begin(); + it!=_rob[num_bank].end(); + it++) + if ((*it)->ptr == packet_id) + { + entry = (*it); + break; + } + +#ifdef DEBUG_TEST + if (entry == NULL) + throw ERRORMORPHEO(FUNCTION,_("Commit : Packet_id miss match in the Re Order Buffer.\n")); +#endif + + internal_BANK_COMMIT_ENTRY [num_bank][num_bank_access] = entry; + +// PORT_WRITE(out_COMMIT_NUM_REG_RD [i],(entry->rename_unit_id << _param->_size_general_register)+entry->num_reg_rd_phy_new); + PORT_WRITE(out_COMMIT_NUM_REG_RD [i],entry->num_reg_rd_phy_new); + } +#ifdef STATISTICS + else + { + internal_BANK_COMMIT_CONFLIT_ACCESS ++; + } +#endif + } + } + + for (uint32_t i=0; i<_param->_nb_inst_commit; i++) + PORT_WRITE(out_COMMIT_ACK [i],commit_ack [i]); + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_insert.cpp (revision 88) @@ -0,0 +1,135 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::genMealy_insert" + void Commit_unit::genMealy_insert (void) + { + log_begin(Commit_unit,FUNCTION); + log_function(Commit_unit,FUNCTION,_name.c_str()); + + Tcontrol_t bank_full [_param->_nb_bank]; + Tcontrol_t insert_ack [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + Tpacket_t insert_packet_id [_param->_nb_rename_unit][_param->_max_nb_inst_insert]; +#endif + bool can_rename_select [_param->_nb_rename_unit]; + + // Initialisation + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + internal_BANK_INSERT_VAL [i] = false; + bank_full [i] = not (_rob[i].size() < _param->_size_bank); + } + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + can_rename_select [i] = true; + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + insert_ack [i][j] = false; +#ifdef SYSTEMC_VHDL_COMPATIBILITY + insert_packet_id [i][j] = false; +#endif + } + } + + // insert interface +// log_printf(TRACE,Commit_unit,FUNCTION," * reg_NUM_BANK_TAIL : %d",reg_NUM_BANK_TAIL); + + std::list * select_insert = _priority_insert ->select(); // same select for all insert + std::list::iterator it=select_insert ->begin(); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + // compute the bank number (num_bank_tail is the older write slot) + uint32_t num_bank = (reg_NUM_BANK_TAIL+i)%_param->_nb_bank; + +// log_printf(TRACE,Commit_unit,FUNCTION," * BANK : %d", num_bank); +// log_printf(TRACE,Commit_unit,FUNCTION," * val : %d", internal_BANK_INSERT_VAL [num_bank]); +// log_printf(TRACE,Commit_unit,FUNCTION," * full : %d", bank_full [num_bank]); + + while (it!=select_insert ->end()) + { + uint32_t num_rename_unit = it->grp; + uint32_t num_inst_insert = it->elt; + + it++; + + log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]", num_rename_unit,num_inst_insert); +// log_printf(TRACE,Commit_unit,FUNCTION," * INSERT_VAL : %d", PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert])); + log_printf(TRACE,Commit_unit,FUNCTION," * can_rename_select : %d", can_rename_select [num_rename_unit]); + + // Test if have instruction + // -> rename_unit_glue test the in-order insert !!!!! + if (can_rename_select [num_rename_unit] // and +// PORT_READ(in_INSERT_VAL [num_rename_unit][num_inst_insert]) + ) + { + log_printf(TRACE,Commit_unit,FUNCTION," * have instruction"); + log_printf(TRACE,Commit_unit,FUNCTION," * bank_full : %d",bank_full [num_bank]); + + // test if bank is not busy (full or previous access) + if (not bank_full [num_bank]) + { + // find + insert_ack [num_rename_unit][num_inst_insert] = true; + + Tpacket_t packet_id = ((num_bank << _param->_shift_num_bank) | reg_BANK_PTR [num_bank]); + +#ifdef SYSTEMC_VHDL_COMPATIBILITY + insert_packet_id [num_rename_unit][num_inst_insert] = packet_id; +#else + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_INSERT_PACKET_ID [num_rename_unit][num_inst_insert],packet_id); +#endif + internal_BANK_INSERT_VAL [num_bank] = true; + internal_BANK_INSERT_NUM_RENAME_UNIT [num_bank] = num_rename_unit; + internal_BANK_INSERT_NUM_INST [num_bank] = num_inst_insert; + + break; + } + } + + // is a valid instruction, but it's not send at a bank + // ... invalid this rename_unit (because, insert in_order) + can_rename_select [num_rename_unit] = false; + } + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + PORT_WRITE(out_INSERT_ACK [i][j],insert_ack [i][j]); + log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d] -> ack %d",i,j,insert_ack[i][j]); + +#ifdef SYSTEMC_VHDL_COMPATIBILITY + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_INSERT_PACKET_ID [i][j],insert_packet_id [i][j]); +#endif + } + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMealy_retire.cpp (revision 88) @@ -0,0 +1,193 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::genMealy_retire" + void Commit_unit::genMealy_retire (void) + { + log_begin(Commit_unit,FUNCTION); + log_function(Commit_unit,FUNCTION,_name.c_str()); + + Tcontrol_t retire_val [_param->_nb_rename_unit][_param->_max_nb_inst_retire]; + uint32_t num_inst_retire [_param->_nb_rename_unit]; + bool can_retire [_param->_nb_rename_unit]; + + Tcontrol_t spr_write_val [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_f_val [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_f [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_cy_val [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_cy [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_ov_val [_param->_nb_front_end][_param->_max_nb_context]; + Tcontrol_t spr_write_sr_ov [_param->_nb_front_end][_param->_max_nb_context]; + + + // Initialisation + for (uint32_t i=0; i<_param->_nb_bank; i++) + internal_BANK_RETIRE_VAL [i] = false; + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + num_inst_retire [i] = 0; + can_retire [i] = true ; + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + retire_val [i][j] = false; + } + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + spr_write_val [i][j] = 0; + + // Scan Top of each bank + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + uint32_t num_bank = (reg_NUM_BANK_HEAD+i)%_param->_nb_bank; + + if (not _rob[num_bank].empty()) + { + // Scan all instruction in windows and test if instruction is speculative + entry_t * entry = _rob [num_bank].front(); + uint32_t x = entry->rename_unit_id; + uint32_t y = num_inst_retire [x]; + + if (can_retire [x] and // in-order + (y < _param->_nb_inst_retire [x]) and + PORT_READ(in_RETIRE_ACK [x][y])) // not busy + { + rob_state_t state = entry->state; + + if ((state == ROB_END_OK ) or + (state == ROB_END_KO ) or + (state == ROB_END_MISS)// or +// (state == ROB_END_EXCEPTION) + ) + { + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id; + Tcontrol_t write_re = entry->write_re; + Tspecial_address_t num_reg_re_log = entry->num_reg_re_log; + + // if state is ok, when write flags in the SR regsiters + bool spr_write_ack = true; + + if ((state == ROB_END_OK ) and write_re) + { + spr_write_ack = PORT_READ(in_SPR_WRITE_ACK [front_end_id][context_id]); + + // retire_ack is set !!! + spr_write_val [front_end_id][context_id] = 1; + + Tspecial_data_t flags = entry->flags; + + switch (num_reg_re_log) + { + case SPR_LOGIC_SR_F : + { + spr_write_sr_f_val [front_end_id][context_id] = 1; + spr_write_sr_f [front_end_id][context_id] = (flags & FLAG_F )!=0; + + break; + } + case SPR_LOGIC_SR_CY_OV : + { + spr_write_sr_cy_val [front_end_id][context_id] = 1; + spr_write_sr_ov_val [front_end_id][context_id] = 1; + spr_write_sr_cy [front_end_id][context_id] = (flags & FLAG_CY)!=0; + spr_write_sr_ov [front_end_id][context_id] = (flags & FLAG_OV)!=0; + + break; + } + default : + { +#ifdef DEBUG_TEST + throw ERRORMORPHEO(FUNCTION,_("Invalid num_reg_re_log.\n")); +#endif + } + } + } + + // find an instruction can be retire, and in order + + if (spr_write_ack) + { + retire_val [x][y] = 1; + num_inst_retire [x] ++; + internal_BANK_RETIRE_VAL [num_bank] = true; + } + + internal_BANK_RETIRE_NUM_RENAME_UNIT [num_bank] = x; + internal_BANK_RETIRE_NUM_INST [num_bank] = y; + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_RETIRE_FRONT_END_ID [x][y], front_end_id ); + if (_param->_have_port_context_id) + PORT_WRITE(out_RETIRE_CONTEXT_ID [x][y], context_id ); +// PORT_WRITE(out_RETIRE_RENAME_UNIT_ID [x][y], entry->rename_unit_id ); + PORT_WRITE(out_RETIRE_EVENT_STATE [x][y], entry->event_state ); + PORT_WRITE(out_RETIRE_USE_STORE_QUEUE [x][y], entry->use_store_queue ); + PORT_WRITE(out_RETIRE_USE_LOAD_QUEUE [x][y], entry->use_load_queue ); + PORT_WRITE(out_RETIRE_STORE_QUEUE_PTR_WRITE [x][y], entry->store_queue_ptr_write); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_RETIRE_LOAD_QUEUE_PTR_WRITE [x][y], entry->load_queue_ptr_write ); + PORT_WRITE(out_RETIRE_READ_RA [x][y], entry->read_ra ); + PORT_WRITE(out_RETIRE_NUM_REG_RA_PHY [x][y], entry->num_reg_ra_phy ); + PORT_WRITE(out_RETIRE_READ_RB [x][y], entry->read_rb ); + PORT_WRITE(out_RETIRE_NUM_REG_RB_PHY [x][y], entry->num_reg_rb_phy ); + PORT_WRITE(out_RETIRE_READ_RC [x][y], entry->read_rc ); + PORT_WRITE(out_RETIRE_NUM_REG_RC_PHY [x][y], entry->num_reg_rc_phy ); + PORT_WRITE(out_RETIRE_WRITE_RD [x][y], entry->write_rd ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_LOG [x][y], entry->num_reg_rd_log ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_OLD [x][y], entry->num_reg_rd_phy_old ); + PORT_WRITE(out_RETIRE_NUM_REG_RD_PHY_NEW [x][y], entry->num_reg_rd_phy_new ); + PORT_WRITE(out_RETIRE_WRITE_RE [x][y], write_re ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_LOG [x][y], num_reg_re_log ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_OLD [x][y], entry->num_reg_re_phy_old ); + PORT_WRITE(out_RETIRE_NUM_REG_RE_PHY_NEW [x][y], entry->num_reg_re_phy_new ); + } + } + + // Retire "in-order" + can_retire [x] &= retire_val [x][y]; + } + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + PORT_WRITE(out_RETIRE_VAL [i][j],retire_val [i][j]); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + PORT_WRITE(out_SPR_WRITE_VAL [i][j], spr_write_val [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_F_VAL [i][j], spr_write_sr_f_val [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_F [i][j], spr_write_sr_f [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_CY_VAL [i][j], spr_write_sr_cy_val [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_CY [i][j], spr_write_sr_cy [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_OV_VAL [i][j], spr_write_sr_ov_val [i][j]); + PORT_WRITE(out_SPR_WRITE_SR_OV [i][j], spr_write_sr_ov [i][j]); + } + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 88) @@ -0,0 +1,158 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::genMoore" + void Commit_unit::genMoore (void) + { + log_begin(Commit_unit,FUNCTION); + log_function(Commit_unit,FUNCTION,_name.c_str()); + + // =================================================================== + // =====[ REEXECUTE ]================================================= + // =================================================================== + { + Tcontrol_t val = false; + + if (not _rob[reg_NUM_BANK_HEAD].empty()) + { + entry_t * entry = _rob [reg_NUM_BANK_HEAD].front(); + rob_state_t state = entry->state; + + val = ((state == ROB_STORE_HEAD_OK) or + (state == ROB_STORE_HEAD_KO)); + + if (val) + { + if (_param->_have_port_context_id) + PORT_WRITE(out_REEXECUTE_CONTEXT_ID [0], entry->context_id ); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_REEXECUTE_FRONT_END_ID [0], entry->front_end_id ); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_REEXECUTE_PACKET_ID [0], entry->ptr ); + PORT_WRITE(out_REEXECUTE_TYPE [0], entry->type ); + PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [0], entry->store_queue_ptr_write); + PORT_WRITE(out_REEXECUTE_OPERATION [0], (state == ROB_STORE_HEAD_OK)?OPERATION_MEMORY_STORE_HEAD_OK:OPERATION_MEMORY_STORE_HEAD_KO); + } + } + + internal_REEXECUTE_VAL [0] = val; + internal_REEXECUTE_NUM_BANK [0] = reg_NUM_BANK_HEAD; + + PORT_WRITE(out_REEXECUTE_VAL[0], internal_REEXECUTE_VAL [0]); + } + + // =================================================================== + // =====[ BRANCH_COMPLETE ]=========================================== + // =================================================================== + { + uint32_t nb_scan_bank = 0; + + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) + { + Tcontrol_t val = false; + + for (uint32_t j=nb_scan_bank; j<_param->_nb_bank; j++) + { + nb_scan_bank ++; + + uint32_t num_bank = (reg_NUM_BANK_HEAD+j)%_param->_nb_bank; + + if (not _rob [num_bank].empty()) + { + entry_t * entry = _rob [num_bank].front(); + rob_state_t state = entry->state; + + if (state == ROB_BRANCH_COMPLETE) + { + val = true; + + internal_BRANCH_COMPLETE_NUM_BANK [i] = num_bank; + + if (_param->_have_port_context_id) + PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); + if (_param->_have_port_depth) + PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); + PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->data_commit ); + PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i], (entry->flags&FLAG_F)!=0 ); + + break; + } + } + } + + internal_BRANCH_COMPLETE_VAL [i] = val; + PORT_WRITE(out_BRANCH_COMPLETE_VAL [i], internal_BRANCH_COMPLETE_VAL [i]); + } + } + + // =================================================================== + // =====[ UPDATE ]==================================================== + // =================================================================== + { + Tcontrol_t val = false; + + if (not _rob[reg_NUM_BANK_HEAD].empty()) + { + entry_t * entry = _rob [reg_NUM_BANK_HEAD].front(); + rob_state_t state = entry->state; + + val = (state == ROB_END_EXCEPTION); + + if (val) + { + throw ERRORMORPHEO(FUNCTION,_("Moore : exception is not yet supported (Coming Soon).\n")); + } + } + } + +// public : SC_OUT(Tcontrol_t ) * out_UPDATE_VAL ; +// public : SC_IN (Tcontrol_t ) * in_UPDATE_ACK ; +// public : SC_OUT(Tcontext_t ) * out_UPDATE_CONTEXT_ID ; +// public : SC_OUT(Tcontext_t ) * out_UPDATE_FRONT_END_ID ; +// public : SC_OUT(Tdepth_t ) * out_UPDATE_DEPTH ; +// public : SC_OUT(Tevent_type_t ) * out_UPDATE_TYPE ; +// public : SC_OUT(Tcontrol_t ) * out_UPDATE_IS_DELAY_SLOT ; +// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS ; +// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; +// public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; +// public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EEAR ; + + // =================================================================== + // =====[ NB_INST ]=================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + PORT_WRITE(out_NB_INST_COMMIT_ALL [i][j], reg_NB_INST_COMMIT_ALL [i][j]); + PORT_WRITE(out_NB_INST_COMMIT_MEM [i][j], reg_NB_INST_COMMIT_MEM [i][j]); + } + + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 88) @@ -0,0 +1,102 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::statistics_allocation" + void Commit_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Commit_unit,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Commit_unit", + param_statistics); + + _stat_nb_inst_insert = new counter_t * [_param->_nb_rename_unit]; + _stat_nb_inst_retire = new counter_t * [_param->_nb_rename_unit]; + _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; + + { + std::string sum_nb_inst_insert = ""; + std::string sum_nb_inst_retire = ""; + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_"+toString(i)); + _stat_nb_inst_retire [i] = _stat->create_variable("nb_inst_retire_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_use_interface_insert_"+toString(i), "nb_inst_insert_"+toString(i), "", toString(_("Average instruction by cycle on insert interface (rename_unit %d)"),i)); + _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "nb_inst_retire_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i)); + _stat->create_expr_percent ("percent_use_interface_insert_"+toString(i) , "average_use_interface_insert_"+toString(i), toString(_param->_nb_inst_insert [i]), toString(_("Percent usage of insert interface (rename_unit %d)"),i)); + _stat->create_expr_percent ("percent_use_interface_retire_"+toString(i) , "average_use_interface_retire_"+toString(i), toString(_param->_nb_inst_retire [i]), toString(_("Percent usage of retire interface (rename_unit %d)"),i)); + + if (i == 0) + { + sum_nb_inst_insert = "nb_inst_insert_"+toString(i); + sum_nb_inst_retire = "nb_inst_retire_"+toString(i); + } + else + { + sum_nb_inst_insert = "+ nb_inst_insert_"+toString(i) + " " +sum_nb_inst_insert; + sum_nb_inst_retire = "+ nb_inst_retire_"+toString(i) + " " +sum_nb_inst_retire; + } + } + + _stat->create_expr_average_by_cycle("average_inst_insert", sum_nb_inst_insert, "", _("Average instruction insert by cycle")); + _stat->create_expr_average_by_cycle("average_inst_retire", sum_nb_inst_retire, "", _("Average instruction retire by cycle")); + } + + _stat_nb_inst_commit = _stat->create_variable("nb_inst_commit"); + _stat->create_expr_average_by_cycle("average_use_interface_commit","nb_inst_commit", "", _("Average instruction by cycle on commit interface")); + _stat->create_expr_percent ("percent_use_interface_commit", "average_use_interface_commit", toString(_param->_nb_inst_commit), _("Percent usage of commit interface")); + + _stat_nb_inst_commit_conflit_access = _stat->create_variable("nb_inst_commit_conflit_access"); + _stat->create_expr_average_by_cycle("average_use_interface_commit_conflit_access","nb_inst_commit_conflit_access", "", _("Average access conflit by cycle on commit interface")); + _stat->create_expr_percent ("percent_use_interface_commit_conflit_access","average_use_interface_commit_conflit_access", "average_use_interface_commit", _("Percent access conflit on commit interface")); + + // bank/queue occupation + { + std::string sum_bank_nb_inst = ""; + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + _stat_bank_nb_inst [i] = _stat->create_variable("bank_nb_inst_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_occupation_bank_"+toString(i), "bank_nb_inst_"+toString(i), "", toString(_("Average instruction by cycle (bank %d)"),i)); + _stat->create_expr_percent ("percent_occupation_bank_"+toString(i), "average_occupation_bank_"+toString(i), toString(_param->_size_bank), toString(_("Percent occupation of bank (bank %d)"),i)); + + if (i == 0) + sum_bank_nb_inst = "bank_nb_inst_"+toString(i); + else + sum_bank_nb_inst = "+ bank_nb_inst_"+toString(i) + " " +sum_bank_nb_inst; + } + + _stat->create_expr_average_by_cycle("average_occupation_bank", sum_bank_nb_inst, "", _("Average instruction by cycle (all bank)")); + _stat->create_expr_percent ("percent_occupation_bank" , "average_occupation_bank", toString(_param->_size_queue), _("Percent occupation of Re-Order-Buffer (all bank)")); + } + + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,43 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::statistics_deallocation" + void Commit_unit::statistics_deallocation (void) + { + log_begin(Commit_unit,FUNCTION); + + log_printf(INFO,Commit_unit,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + delete [] _stat_nb_inst_insert; + delete [] _stat_nb_inst_retire; + delete [] _stat_bank_nb_inst; + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 88) @@ -0,0 +1,504 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::transition" + void Commit_unit::transition (void) + { + log_begin(Commit_unit,FUNCTION); + log_function(Commit_unit,FUNCTION,_name.c_str()); + + if (PORT_READ(in_NRESET) == 0) + { + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + _rob [i].clear(); + reg_BANK_PTR [i] = 0; + } + + reg_NUM_BANK_HEAD = 0; + reg_NUM_BANK_TAIL = 0; + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + reg_NB_INST_COMMIT_ALL [i][j] = 0; + reg_NB_INST_COMMIT_MEM [i][j] = 0; + } + + _priority_insert->reset(); + } + else + { + // next priority + _priority_insert->transition(); + + // =================================================================== + // =====[ INSERT ]==================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (internal_BANK_INSERT_VAL [i]) + { + uint32_t x = internal_BANK_INSERT_NUM_RENAME_UNIT [i]; + uint32_t y = internal_BANK_INSERT_NUM_INST [i]; + + if (PORT_READ(in_INSERT_VAL [x][y])) + { + log_printf(TRACE,Commit_unit,FUNCTION," * INSERT [%d][%d]",x,y); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_insert [x]) ++; +#endif + + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_FRONT_END_ID [x][y]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_INSERT_CONTEXT_ID [x][y]):0; + Ttype_t type = PORT_READ(in_INSERT_TYPE [x][y]); + Toperation_t operation = PORT_READ(in_INSERT_OPERATION [x][y]); + Texception_t exception = PORT_READ(in_INSERT_EXCEPTION [x][y]); + + log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); + log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString_type(type).c_str()); + log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); + log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); + + entry_t * entry = new entry_t; + + entry->ptr = reg_BANK_PTR [i]; + entry->front_end_id = front_end_id; + entry->context_id = context_id ; + entry->rename_unit_id = x; + entry->depth = (_param->_have_port_depth)?PORT_READ(in_INSERT_DEPTH [x][y]):0; + entry->type = type; + entry->operation = operation; + entry->is_delay_slot = PORT_READ(in_INSERT_IS_DELAY_SLOT [x][y]); + entry->address = PORT_READ(in_INSERT_ADDRESS [x][y]); + entry->exception = exception; + entry->exception_use = PORT_READ(in_INSERT_EXCEPTION_USE [x][y]); + entry->use_store_queue = (type == TYPE_MEMORY) and ( is_operation_memory_store(operation)); + entry->use_load_queue = (type == TYPE_MEMORY) and (not is_operation_memory_store(operation)); + entry->store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE [x][y]); + entry->load_queue_ptr_write = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE [x][y]):0; + entry->read_ra = PORT_READ(in_INSERT_READ_RA [x][y]); + entry->num_reg_ra_log = PORT_READ(in_INSERT_NUM_REG_RA_LOG [x][y]); + entry->num_reg_ra_phy = PORT_READ(in_INSERT_NUM_REG_RA_PHY [x][y]); + entry->read_rb = PORT_READ(in_INSERT_READ_RB [x][y]); + entry->num_reg_rb_log = PORT_READ(in_INSERT_NUM_REG_RB_LOG [x][y]); + entry->num_reg_rb_phy = PORT_READ(in_INSERT_NUM_REG_RB_PHY [x][y]); + entry->read_rc = PORT_READ(in_INSERT_READ_RC [x][y]); + entry->num_reg_rc_log = PORT_READ(in_INSERT_NUM_REG_RC_LOG [x][y]); + entry->num_reg_rc_phy = PORT_READ(in_INSERT_NUM_REG_RC_PHY [x][y]); + entry->write_rd = PORT_READ(in_INSERT_WRITE_RD [x][y]); + entry->num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [x][y]); + entry->num_reg_rd_phy_old = PORT_READ(in_INSERT_NUM_REG_RD_PHY_OLD [x][y]); + entry->num_reg_rd_phy_new = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [x][y]); + entry->write_re = PORT_READ(in_INSERT_WRITE_RE [x][y]); + entry->num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [x][y]); + entry->num_reg_re_phy_old = PORT_READ(in_INSERT_NUM_REG_RE_PHY_OLD [x][y]); + entry->num_reg_re_phy_new = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [x][y]); + + if (exception == EXCEPTION_NONE) + { + Tcontrol_t no_execute = PORT_READ(in_INSERT_NO_EXECUTE [x][y]); + // no_execute : l.j, l.nop, l.rfe + + log_printf(TRACE,Commit_unit,FUNCTION," * no_execute : %d",no_execute); + + switch (type) + { + case TYPE_BRANCH : {entry->state=(no_execute==1)?ROB_BRANCH_COMPLETE:ROB_BRANCH_WAIT_END; break;} + case TYPE_MEMORY : {entry->state=ROB_STORE_WAIT_HEAD_OK; break;} + default : {entry->state=(no_execute==1)?ROB_END_OK_SPECULATIVE:ROB_OTHER_WAIT_END; break;} + } + } + else + { + // in_INSERT_NO_EXECUTE [x][y] : l.sys, l.trap + + entry->state = ROB_END_EXCEPTION_WAIT_HEAD; + } + + _rob[i].push_back(entry); + + // Update nb_inst + reg_NB_INST_COMMIT_ALL [front_end_id][context_id] ++; + if (type == TYPE_MEMORY) + reg_NB_INST_COMMIT_MEM [front_end_id][context_id] ++; + + reg_NUM_BANK_TAIL = (reg_NUM_BANK_TAIL+1)%_param->_nb_bank; + reg_BANK_PTR [i] = (reg_BANK_PTR [i]+1)%_param->_size_bank; + } + } + + // =================================================================== + // =====[ COMMIT ]==================================================== + // =================================================================== + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_commit_conflit_access) += internal_BANK_COMMIT_CONFLIT_ACCESS; +#endif + + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_bank_access_commit; j++) + if (internal_BANK_COMMIT_VAL [i][j]) + { + uint32_t x = internal_BANK_COMMIT_NUM_INST [i][j]; + + if (PORT_READ(in_COMMIT_VAL [x]) and PORT_READ(in_COMMIT_WEN [x])) + { + log_printf(TRACE,Commit_unit,FUNCTION," * COMMIT [%d]",x); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_commit) ++; +#endif + +// Tpacket_t packet_id = (_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])&_param->_mask_size_bank):0; + + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank : %d",i); +// log_printf(TRACE,Commit_unit,FUNCTION," * packet_id : %d",(_param->_have_port_rob_ptr )?(PORT_READ(in_COMMIT_PACKET_ID [x])):0); +// log_printf(TRACE,Commit_unit,FUNCTION," * num_entry : %d",packet_id); + + // test pandex with ptr_write. +// Tpacket_t index = (packet_id_size_bank+reg_BANK_PTR [i]-packet_id); + + // find the good entry !!! + entry_t * entry = internal_BANK_COMMIT_ENTRY [i][j]; + + //Toperation_t operation = PORT_READ(in_COMMIT_OPERATION [x]); + //Ttype_t type = PORT_READ(in_COMMIT_TYPE [x]); + Texception_t exception = PORT_READ(in_COMMIT_EXCEPTION [x]); + + rob_state_t state = entry->state; + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id; + + // change state + // * test if exception : exception and mask + + bool have_exception = false; + + if (exception != EXCEPTION_NONE) + switch (entry->exception_use) + { + case EXCEPTION_USE_RANGE : {have_exception = ((exception == EXCEPTION_RANGE) and PORT_READ(in_SPR_READ_SR_OVE[front_end_id][context_id])); break;} + case EXCEPTION_USE_MEMORY_WITH_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or + (exception == EXCEPTION_DATA_TLB ) or + (exception == EXCEPTION_DATA_PAGE) or + (exception == EXCEPTION_ALIGNMENT)); break;}; + case EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT : {have_exception = ((exception == EXCEPTION_BUS_ERROR) or + (exception == EXCEPTION_DATA_TLB ) or + (exception == EXCEPTION_DATA_PAGE)); break;}; + case EXCEPTION_USE_CUSTOM_0 : {have_exception = (exception == EXCEPTION_CUSTOM_0); break;}; + case EXCEPTION_USE_CUSTOM_1 : {have_exception = (exception == EXCEPTION_CUSTOM_1); break;}; + case EXCEPTION_USE_CUSTOM_2 : {have_exception = (exception == EXCEPTION_CUSTOM_2); break;}; + case EXCEPTION_USE_CUSTOM_3 : {have_exception = (exception == EXCEPTION_CUSTOM_3); break;}; + case EXCEPTION_USE_CUSTOM_4 : {have_exception = (exception == EXCEPTION_CUSTOM_4); break;}; + case EXCEPTION_USE_CUSTOM_5 : {have_exception = (exception == EXCEPTION_CUSTOM_5); break;}; + case EXCEPTION_USE_CUSTOM_6 : {have_exception = (exception == EXCEPTION_CUSTOM_6); break;}; + case EXCEPTION_USE_TRAP : {have_exception = false; break;}; + case EXCEPTION_USE_NONE : {have_exception = false; break;}; + case EXCEPTION_USE_ILLEGAL_INSTRUCTION : {have_exception = false; break;}; + case EXCEPTION_USE_SYSCALL : {have_exception = false; break;}; + default : + { + throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception_use.\n")); + break; + } + } + + if (not have_exception) + { + switch (state) + { + case ROB_OTHER_WAIT_END : {state = ROB_END_OK_SPECULATIVE; break;} + case ROB_BRANCH_WAIT_END : {state = ROB_BRANCH_COMPLETE ; break;} + case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE; break;} + default : + { + throw ERRORMORPHEO(FUNCTION,toString(_("Commit : invalid state value (%s).\n"),toString(state).c_str())); + break; + } + } + // can have an exception, but this instruction is not sensible a this exception + exception = EXCEPTION_NONE; + } + else + { +#ifdef DEBUG_TEST + if ((entry->type == TYPE_MEMORY) and (exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE)) + throw ERRORMORPHEO(FUNCTION,_("Commit : invalid exception.\n")); +#endif + + switch (state) + { + case ROB_OTHER_WAIT_END : + case ROB_BRANCH_WAIT_END : {state = ROB_END_EXCEPTION_WAIT_HEAD; break;} + case ROB_MISS_WAIT_END : {state = ROB_END_KO_SPECULATIVE ; break;} + default : + { + throw ERRORMORPHEO(FUNCTION,_("Commit : invalid state value.\n")); + break; + } + } + } + + // update Re Order Buffer + entry->state = state; + entry->exception = exception; + entry->flags = PORT_READ(in_COMMIT_FLAGS [x]); + entry->no_sequence = PORT_READ(in_COMMIT_NO_SEQUENCE [x]); + entry->data_commit = PORT_READ(in_COMMIT_ADDRESS [x]); + } + } + + // =================================================================== + // =====[ RETIRE ]==================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (internal_BANK_RETIRE_VAL [i]) + { + uint32_t x = internal_BANK_RETIRE_NUM_RENAME_UNIT [i]; + uint32_t y = internal_BANK_RETIRE_NUM_INST [i]; + + log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_retire [x]) ++; +#endif + +#ifdef DEBUG_TEST + if (not PORT_READ(in_RETIRE_ACK [x][y])) + throw ERRORMORPHEO(FUNCTION,_("Retire : retire_ack must be set.\n")); +#endif + + + entry_t * entry = _rob [i].front(); + + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id ; + Ttype_t type = entry->type ; + + // Update nb_inst + reg_NB_INST_COMMIT_ALL [front_end_id][context_id] --; + if (type == TYPE_MEMORY) + reg_NB_INST_COMMIT_MEM [front_end_id][context_id] --; + + reg_NUM_BANK_HEAD = (reg_NUM_BANK_HEAD+1)%_param->_nb_bank; + + _rob [i].pop_front(); + delete entry; + } + + // =================================================================== + // =====[ REEXECUTE ]================================================= + // =================================================================== + if (internal_REEXECUTE_VAL [0] and PORT_READ(in_REEXECUTE_ACK [0])) + { + uint32_t num_bank = internal_REEXECUTE_NUM_BANK [0]; + + entry_t * entry = _rob [num_bank].front(); + rob_state_t state = entry->state; + + switch (state) + { + case ROB_STORE_HEAD_OK : {state = ROB_OTHER_WAIT_END; break; } + case ROB_STORE_HEAD_KO : {state = ROB_MISS_WAIT_END ; break; } + default : {throw ERRORMORPHEO(FUNCTION,_("Reexecute : invalid state value.\n"));} + } + + entry->state = state; + } + + // =================================================================== + // =====[ BRANCH_COMPLETE ]=========================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) + if (internal_BRANCH_COMPLETE_VAL [i] and PORT_READ(in_BRANCH_COMPLETE_ACK [i])) + { + uint32_t num_bank = internal_BRANCH_COMPLETE_NUM_BANK [i]; + + entry_t * entry = _rob [num_bank].front(); + +#ifdef DEBUG_TEST + rob_state_t state = entry->state; + if (state != ROB_BRANCH_COMPLETE) + throw ERRORMORPHEO(FUNCTION,_("Branch_complete : Invalid state value.\n")); +#endif + + entry->state = ROB_END_OK_SPECULATIVE; + } + + // =================================================================== + // =====[ EVENT ]===================================================== + // =================================================================== + + // =================================================================== + // =====[ DEPTH - HEAD ]============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (not _rob[i].empty()) + { + // Scan all instruction in windows and test if instruction is speculative + entry_t * entry = _rob [i].front(); + + Tcontext_t front_end_id = entry->front_end_id; + Tcontext_t context_id = entry->context_id ; + rob_state_t state = entry->state; + Tdepth_t depth = entry->depth; + + Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [front_end_id][context_id]):0; + Tdepth_t depth_max = PORT_READ(in_DEPTH_MAX[front_end_id][context_id]); + + // is a valid instruction ? + // If DEPTH_CURRENT : + // equal at DEPTH_MIN -> not speculative + // not include ]DEPTH_MIN:DEPTH_MAX[ -> previous branch miss + // include ]DEPTH_MIN:DEPTH_MAX[ -> speculative + + // All case + // ....... min ...X... max ....... OK + // ....... min ....... max ...X... KO + // ...X... min ....... max ....... KO + // ....... max ....... min ...X... OK + // ...X... max ....... min ....... OK + // ....... max ...X... min ....... KO + + Tcontrol_t is_valid = ((depth == depth_min) or + ((depth_min < depth_max)? + (depth depth_min) or (depth < depth_max)))); + + //------------------------------------------------------ + // test if instruction is miss speculative + //------------------------------------------------------ + if (not is_valid) + { + switch (state) + { + case ROB_BRANCH_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_BRANCH_COMPLETE : {state = ROB_END_MISS ; break;} + case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_KO; break;} + //case ROB_STORE_WAIT_HEAD_KO : {state = ; break;} + case ROB_OTHER_WAIT_END : {state = ROB_MISS_WAIT_END; break;} + case ROB_END_OK_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_KO_SPECULATIVE : {state = ROB_END_MISS ; break;} + case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_MISS ; break;} + + // don't change + case ROB_STORE_HEAD_KO : {break;} + case ROB_MISS_WAIT_END : {break;} + case ROB_END_MISS : {break;} + + // can't have miss speculation + case ROB_STORE_HEAD_OK : + case ROB_END_OK : + case ROB_END_KO : + case ROB_END_EXCEPTION : + default : + { + throw ERRORMORPHEO(FUNCTION,_("Miss Speculation : Invalide state.\n")); + break; + } + } + } + + //------------------------------------------------------ + // test if instruction is not speculative + //------------------------------------------------------ + if (entry->depth == depth_min) + { + switch (state) + { + case ROB_END_OK_SPECULATIVE : {state = ROB_END_OK ; break;} + case ROB_END_KO_SPECULATIVE : {state = ROB_END_KO ; break;} + default : {break;} + } + } + + //------------------------------------------------------ + // test if instruction is store and head + //------------------------------------------------------ + if (i == reg_NUM_BANK_HEAD) + { + switch (state) + { + case ROB_STORE_WAIT_HEAD_OK : {state = ROB_STORE_HEAD_OK; break;} + case ROB_END_EXCEPTION_WAIT_HEAD : {state = ROB_END_EXCEPTION; break;} + default : {break;} + } + } + + entry->state = state; + } + } + + // =================================================================== + // =====[ OTHER ]===================================================== + // =================================================================== + + log_printf(TRACE,Commit_unit,FUNCTION," * Dump ROB (Re-Order-Buffer)"); + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_head : %d",reg_NUM_BANK_HEAD); + log_printf(TRACE,Commit_unit,FUNCTION," * num_bank_tail : %d",reg_NUM_BANK_TAIL); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + log_printf(TRACE,Commit_unit,FUNCTION," * num_inst[%d][%d] all : %d, mem : %d",i,j,reg_NB_INST_COMMIT_ALL[i][j],reg_NB_INST_COMMIT_MEM[i][j]); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + log_printf(TRACE,Commit_unit,FUNCTION," * Bank[%d] size : %d, ptr : %d",i,(int)_rob[i].size(), reg_BANK_PTR [i]); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + *(_stat_bank_nb_inst [i]) += _rob[i].size(); +#endif + + uint32_t x=0; + for (std::list::iterator it=_rob[i].begin(); + it!=_rob[i].end(); + it++) + { + log_printf(TRACE,Commit_unit,FUNCTION," [%d] %.8x (%.8x) %s - ptr : %d", + x, + (*it)->address, + (*it)->address<<2, + toString((*it)->state).c_str(), + (*it)->ptr); + x++; + } + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::vhdl" + void Commit_unit::vhdl (void) + { + log_begin(Commit_unit,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::vhdl_body" + void Commit_unit::vhdl_body (Vhdl * & vhdl) + { + log_begin(Commit_unit,FUNCTION); + vhdl->set_body (""); + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::vhdl_declaration" + void Commit_unit::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Commit_unit,FUNCTION); + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters.cpp (revision 88) @@ -0,0 +1,146 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" +#include "Common/include/Max.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_rename_unit , + uint32_t size_queue , + uint32_t nb_bank , + uint32_t * nb_inst_insert , + uint32_t * nb_inst_retire , + uint32_t nb_inst_commit , + uint32_t nb_inst_reexecute , + uint32_t nb_inst_branch_complete , + uint32_t ** nb_branch_speculated , + uint32_t size_general_data , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + uint32_t size_general_register , + uint32_t size_special_register , + Tpriority_t priority , + Tload_balancing_t load_balancing , + uint32_t nb_rename_unit_select , + bool is_toplevel): + _nb_bank_access_commit (1 ), + _retire_ooo (RETIRE_IN_ORDER) + { + log_begin(Commit_unit,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_rename_unit = nb_rename_unit ; + _size_queue = size_queue ; + _nb_bank = nb_bank ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_retire = nb_inst_retire ; + _nb_inst_commit = nb_inst_commit ; + _nb_inst_reexecute = nb_inst_reexecute ; + _nb_inst_branch_complete = nb_inst_branch_complete; + _nb_branch_speculated = nb_branch_speculated ; + _priority = priority ; + _load_balancing = load_balancing ; + _nb_rename_unit_select = nb_rename_unit_select ; + + _size_rename_unit_id = log2(_nb_rename_unit); + _max_nb_context = max(_nb_context,_nb_front_end); + _max_nb_inst_insert = max(_nb_inst_insert,_nb_rename_unit); + _max_nb_inst_retire = max(_nb_inst_retire,_nb_rename_unit); + _size_bank = _size_queue/_nb_bank; + _shift_num_bank = log2(_size_bank); + _mask_size_bank = gen_mask(log2(_size_bank)); + + _have_port_rename_unit_id = _size_rename_unit_id > 0; + + _array_size_depth = new uint32_t * [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _array_size_depth [i] = new uint32_t [_nb_context [i]]; + for (uint32_t j=0; j<_nb_context [i]; j++) + _array_size_depth [i][j] = (_nb_branch_speculated [i][j] == 0)?0:log2(_nb_branch_speculated [i][j]); + } + + test(); + + if (is_toplevel) + { + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(_max_nb_context); + _size_rob_ptr = log2(_nb_bank)+log2(_size_bank); + _size_instruction_address = size_general_data-2; + _size_store_queue_ptr = size_store_queue_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + _size_general_data = size_general_data ; + _size_general_register = size_general_register ; + _size_special_register = size_special_register ; + _size_depth = max(_array_size_depth,_nb_front_end,_nb_context); + _size_nb_inst_commit = log2(_size_queue)+1; + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy(); + } + + log_end(Commit_unit,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Commit_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Commit_unit,FUNCTION); +// test(); +// log_end(Commit_unit,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Commit_unit::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Commit_unit,FUNCTION); + + for (uint32_t i=0; i<_nb_front_end; i++) + { + delete [] _array_size_depth [i]; + } + delete [] _array_size_depth; + + log_end(Commit_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Commit_unit::copy" + void Parameters::copy (void) + { + log_begin(Commit_unit,FUNCTION); + log_end(Commit_unit,FUNCTION); + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,61 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Commit_unit,FUNCTION); + + Parameters_test test ("Commit_unit"); + + for (uint32_t i=0; i<_nb_rename_unit; i++) + if (_nb_bank < _nb_inst_insert [i]) + test.error (toString(_("For the nb_rename_unit[%d] : nb_bank must be >= nb_inst_insert.\n"),i)); + + for (uint32_t i=0; i<_nb_rename_unit; i++) + if (_nb_bank < _nb_inst_retire [i]) + test.error (toString(_("For the nb_rename_unit[%d] : nb_bank must be >= nb_inst_retire.\n"),i)); + + if (_nb_rename_unit_select > _nb_rename_unit) + test.error("nb_rename_unit must be >= nb_rename_unit_select.\n"); + + if (not is_multiple(_size_queue, _nb_bank)) + test.error("nb_bank must be a multiple of size_queue.\n"); + + if (_nb_inst_reexecute != 1) + test.error("nb_inst_reexecute must be set at 1. Anothers value is unsupported.\n"); + + if (_size_queue == 1) + test.information ("Instructions are issued In-Order.\n"); + else + test.information ("Instructions are issued Out-Of-Order.\n"); + + log_end(Commit_unit,FUNCTION); + + return test; + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,135 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace commit_unit { + + +#undef FUNCTION +#define FUNCTION "Commit_unit::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Commit_unit,FUNCTION); + + std::string str = ""; + + str += toString(MSG_INFORMATION)+" * nb_front_end : "+toString(_nb_front_end )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + str += toString(MSG_INFORMATION)+" * nb_context ["+toString(i)+"] : "+toString(_nb_context [i])+"\n";//[nb_front_end] + str += toString(MSG_INFORMATION)+" * nb_rename_unit : "+toString(_nb_rename_unit )+"\n"; + str += toString(MSG_INFORMATION)+" * size_queue : "+toString(_size_queue )+"\n"; + str += toString(MSG_INFORMATION)+" * nb_bank : "+toString(_nb_bank )+"\n"; + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str += toString(MSG_INFORMATION)+" * nb_inst_insert ["+toString(i)+"] : "+toString(_nb_inst_insert[i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str += toString(MSG_INFORMATION)+" * nb_inst_retire ["+toString(i)+"] : "+toString(_nb_inst_retire[i])+"\n";//[nb_rename_unit] + str += toString(MSG_INFORMATION)+" * nb_inst_commit : "+toString(_nb_inst_commit )+"\n"; + str += toString(MSG_INFORMATION)+" * nb_inst_reexecute : "+toString(_nb_inst_reexecute )+"\n"; + str += toString(MSG_INFORMATION)+" * nb_inst_branch_complete : "+toString(_nb_inst_branch_complete)+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + str += toString(MSG_INFORMATION)+" * nb_branch_speculated ["+toString(i)+"]["+toString(j)+"] : "+toString(_nb_branch_speculated[i][j])+"\n";//[nb_front_end][nb_context] + str += toString(MSG_INFORMATION)+" * size_general_data : "+toString(_size_general_data )+"\n"; + str += toString(MSG_INFORMATION)+" * size_store_queue_ptr : "+toString(_size_store_queue_ptr )+"\n"; + str += toString(MSG_INFORMATION)+" * size_load_queue_ptr : "+toString(_size_load_queue_ptr )+"\n"; + str += toString(MSG_INFORMATION)+" * size_general_register : "+toString(_size_general_register )+"\n"; + str += toString(MSG_INFORMATION)+" * size_special_register : "+toString(_size_special_register )+"\n"; + str += toString(MSG_INFORMATION)+" * priority : "+toString(_priority )+"\n"; + str += toString(MSG_INFORMATION)+" * load_balancing : "+toString(_load_balancing )+"\n"; + str += toString(MSG_INFORMATION)+" * nb_rename_unit_select : "+toString(_nb_rename_unit_select )+"\n"; + str += toString(MSG_INFORMATION)+" * nb_bank_access_commit : "+toString(_nb_bank_access_commit )+"\n"; + str += toString(MSG_INFORMATION)+" * retire_ooo : "+toString(_retire_ooo )+"\n"; + + /* + XML xml ("commit_unit"); + + xml.balise_open("commit_unit"); + xml.singleton_begin("nb_front_end "); xml.attribut("value",toString(_nb_front_end )); xml.singleton_end(); + xml.singleton_begin("nb_rename_unit "); xml.attribut("value",toString(_nb_rename_unit )); xml.singleton_end(); + xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); + xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); + xml.singleton_begin("nb_inst_reexecute "); xml.attribut("value",toString(_nb_inst_reexecute )); xml.singleton_end(); + xml.singleton_begin("nb_inst_branch_complete"); xml.attribut("value",toString(_nb_inst_branch_complete)); xml.singleton_end(); + xml.singleton_begin("nb_inst_commit "); xml.attribut("value",toString(_nb_inst_commit )); xml.singleton_end(); + xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); + xml.singleton_begin("size_store_queue_ptr "); xml.attribut("value",toString(_size_store_queue_ptr )); xml.singleton_end(); + xml.singleton_begin("size_load_queue_ptr "); xml.attribut("value",toString(_size_load_queue_ptr )); xml.singleton_end(); + xml.singleton_begin("size_general_register "); xml.attribut("value",toString(_size_general_register )); xml.singleton_end(); + xml.singleton_begin("size_special_register "); xml.attribut("value",toString(_size_special_register )); xml.singleton_end(); + xml.singleton_begin("priority "); xml.attribut("value",toString(_priority )); xml.singleton_end(); + xml.singleton_begin("load_balancing "); xml.attribut("value",toString(_load_balancing )); xml.singleton_end(); + xml.singleton_begin("nb_rename_unit_select "); xml.attribut("value",toString(_nb_rename_unit_select )); xml.singleton_end(); + + for (uint32_t i=0;i<_nb_front_end; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","front_end"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context [i])); xml.singleton_end(); + + for (uint32_t j=0;j<_nb_context [i]; j++) + { + xml. balise_open_begin("component"); + xml. attribut("type","context"); + xml. attribut("id" ,toString(j)); + xml. balise_open_end(); + xml.singleton_begin("nb_branch_speculated "); xml.attribut("value",toString(_nb_branch_speculated [i][j])); xml.singleton_end(); + xml. balise_close(); + } + + xml. balise_close(); + } + + for (uint32_t i=0;i<_nb_rename_unit; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","rename_unit"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_inst_insert "); xml.attribut("value",toString(_nb_inst_insert [i])); xml.singleton_end(); + xml.singleton_begin("nb_inst_retire "); xml.attribut("value",toString(_nb_inst_retire [i])); xml.singleton_end(); + xml. balise_close(); + } + + xml.balise_close(); + */ + log_end(Commit_unit,FUNCTION); + + +// return xml.get_body(depth); + return str; + }; + +#undef FUNCTION +#define FUNCTION "Commit_unit::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters & x) + { + log_begin(Commit_unit,FUNCTION); + + output_stream << x.print(0); + + log_end(Commit_unit,FUNCTION); + + return output_stream; + }; + +}; // end namespace commit_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libIssue_queue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Issue_queue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Issue_queue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue + +#-----[ Library ]------------------------------------------ + +Issue_queue_LIBRARY = -lIssue_queue \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Issue_queue_DIR_LIBRARY = -L$(Issue_queue_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Issue_queue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Issue_queue_DIR) --makefile=Makefile; + +Issue_queue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Issue_queue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Issue_queue_LIBRARY) + +DIR_LIBRARY = $(Issue_queue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Issue_queue_library + +library_clean : Issue_queue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_min.cfg (revision 88) @@ -0,0 +1,32 @@ +Issue_queue +1 1 *2 # nb_context +1 1 *2 # nb_front_end +1 1 *2 # nb_rename_unit +1 1 *2 # size_queue +1 1 *2 # nb_bank +0 0 *2 # size_packet +32 32 *2 # size_general_data +2 2 *2 # size_special_data +5 5 *2 # size_general_register +2 2 *2 # size_special_register +1 1 *2 # size_store_queue_ptr +0 0 *2 # size_load_queue_ptr +1 1 *2 # nb_inst_issue +1 1 *2 # nb_inst_rename [0] [nb_rename_unit] +1 1 *2 # nb_inst_reexecute +1 1 *2 # nb_rename_unit_select +1 1 *2 # priority +1 1 *2 # load_balancing +1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_mono_rename_unit.cfg (revision 88) @@ -0,0 +1,45 @@ +Issue_queue +4 4 *2 # nb_context +4 4 *2 # nb_front_end +1 1 *2 # nb_rename_unit +16 32 *2 # size_queue +4 16 *2 # nb_bank +0 0 *2 # size_packet +32 32 *2 # size_general_data +2 2 *2 # size_special_data +5 5 *2 # size_general_register +2 2 *2 # size_special_register +1 1 *2 # size_store_queue_ptr +0 0 *2 # size_load_queue_ptr +2 2 *4 # nb_inst_issue +1 4 *4 # nb_inst_rename [0] [nb_rename_unit] +1 4 *4 # nb_inst_reexecute +1 1 *2 # nb_rename_unit_select +1 1 *2 # priority +1 1 *2 # load_balancing +1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [0][1] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_DIV ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [1][TYPE_EXTEND ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [1][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_BRANCH ] [nb_inst_issue][nb_type] +0 0 +1 # table_issue_type [1][TYPE_MEMORY ] [nb_inst_issue][nb_type] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/config_multi_rename_unit.cfg (revision 88) @@ -0,0 +1,86 @@ +Issue_queue +4 4 *2 # nb_context +4 4 *2 # nb_front_end +4 4 *2 # nb_rename_unit +64 64 *2 # size_queue +4 16 *2 # nb_bank +0 0 *2 # size_packet +32 32 *2 # size_general_data +2 2 *2 # size_special_data +5 5 *2 # size_general_register +2 2 *2 # size_special_register +1 1 *2 # size_store_queue_ptr +0 0 *2 # size_load_queue_ptr +4 4 *4 # nb_inst_issue +4 4 *4 # nb_inst_rename [0] [nb_rename_unit] +1 1 *4 # nb_inst_rename [1] [nb_rename_unit] +2 2 *4 # nb_inst_rename [2] [nb_rename_unit] +8 8 *4 # nb_inst_rename [3] [nb_rename_unit] +4 4 *4 # nb_inst_reexecute +1 4 +1 # nb_rename_unit_select +1 1 *2 # priority +1 1 *2 # load_balancing +1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [0][1] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [0][2] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [0][3] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [1][0] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [1][1] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [1][2] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [1][3] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [2][0] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [2][1] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [2][2] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [2][3] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [3][0] [nb_rename_unit][nb_inst_issue] +0 0 +1 # table_routing [3][1] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [3][2] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_routing [3][3] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [1][TYPE_MEMORY ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [2][TYPE_MEMORY ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [3][TYPE_MEMORY ] [nb_inst_issue][nb_type] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,180 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h" + +#define NB_PARAMS 17 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_context (uint32_t )\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_rename_unit (uint32_t )\n")); + err (_(" * size_queue (uint32_t )\n")); + err (_(" * nb_bank (uint32_t )\n")); + err (_(" * size_packet (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); + err (_(" * size_general_register (uint32_t )\n")); + err (_(" * size_special_register (uint32_t )\n")); + err (_(" * size_store_queue_ptr (uint32_t )\n")); + err (_(" * size_load_queue_ptr (uint32_t )\n")); + err (_(" * nb_inst_issue (uint32_t )\n")); + err (_(" * nb_inst_rename [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_inst_reexecute (uint32_t )\n")); + err (_(" * nb_rename_unit_select (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n")); + err (_(" * table_routing [nb_inst_issue][nb_type] (bool )\n")); + err (_(" * TYPE_ALU \n")); + err (_(" * TYPE_SHIFT \n")); + err (_(" * TYPE_MOVE \n")); + err (_(" * TYPE_TEST \n")); + err (_(" * TYPE_MUL \n")); + err (_(" * TYPE_DIV \n")); + err (_(" * TYPE_EXTEND \n")); + err (_(" * TYPE_FIND \n")); + err (_(" * TYPE_SPECIAL\n")); + err (_(" * TYPE_CUSTOM \n")); + err (_(" * TYPE_BRANCH \n")); + err (_(" * TYPE_MEMORY \n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_context = fromString(argv[x++]); + uint32_t _nb_front_end = fromString(argv[x++]); + uint32_t _nb_rename_unit = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+_nb_rename_unit)) + usage (argc, argv); + + uint32_t _size_queue = fromString(argv[x++]); + uint32_t _nb_bank = fromString(argv[x++]); + uint32_t _size_packet = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + uint32_t _size_general_register = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + uint32_t _size_store_queue_ptr = fromString(argv[x++]); + uint32_t _size_load_queue_ptr = fromString(argv[x++]); + uint32_t _nb_inst_issue = fromString(argv[x++]); + uint32_t * _nb_inst_rename = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_inst_rename [i] = fromString(argv[x++]); + uint32_t _nb_inst_reexecute = fromString(argv[x++]); + uint32_t _nb_rename_unit_select = fromString(argv[x++]); + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+_nb_rename_unit+(_nb_rename_unit+12)*_nb_inst_issue)) + usage (argc, argv); + + bool ** _table_routing = new bool * [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _table_routing [i] = new bool [_nb_inst_issue]; + for (uint32_t j=0; j<_nb_inst_issue; j++) + _table_routing [i][j] = fromString(argv[x++]); + } + + bool ** _table_issue_type = new bool * [_nb_inst_issue]; + for (uint32_t i=0; i<_nb_inst_issue; i++) + { + _table_issue_type [i] = new bool [_nb_inst_issue]; + + _table_issue_type [i][TYPE_ALU ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_SHIFT ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MOVE ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_TEST ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MUL ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_DIV ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_EXTEND ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_FIND ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_SPECIAL] = fromString(argv[x++]); + _table_issue_type [i][TYPE_CUSTOM ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_BRANCH ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MEMORY ] = fromString(argv[x++]); + } + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters + (_nb_context , + _nb_front_end , + _nb_rename_unit , + _size_queue , + _nb_bank , + _size_packet , + _size_general_data , + _size_special_data , + _size_general_register , + _size_special_register , + _size_store_queue_ptr , + _size_load_queue_ptr , + _nb_inst_issue , + _nb_inst_rename , + _nb_inst_reexecute , + _nb_rename_unit_select , + _priority , + _load_balancing , + _table_routing , + _table_issue_type , + true // is_toplevel + ); + + msg(_("%s"),param->print(1).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Issue_queue : no error"); + else + TEST_KO("Issue_queue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_inst_rename; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + delete [] _table_routing [i]; + delete [] _table_routing ; + for (uint32_t i=0; i<_nb_inst_issue; i++) + delete [] _table_issue_type [i]; + delete [] _table_issue_type; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,425 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" +#include + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Issue_queue * _Issue_queue = new Issue_queue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_ISSUE_IN_VAL ," in_ISSUE_IN_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL(out_ISSUE_IN_ACK ,"out_ISSUE_IN_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_CONTEXT_ID ," in_ISSUE_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_FRONT_END_ID ," in_ISSUE_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_PACKET_ID ," in_ISSUE_IN_PACKET_ID ",Tpacket_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_OPERATION ," in_ISSUE_IN_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_TYPE ," in_ISSUE_IN_TYPE ",Ttype_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ," in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ," in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT ," in_ISSUE_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_IMMEDIAT ," in_ISSUE_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_READ_RA ," in_ISSUE_IN_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RA ," in_ISSUE_IN_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_READ_RB ," in_ISSUE_IN_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RB ," in_ISSUE_IN_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_READ_RC ," in_ISSUE_IN_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RC ," in_ISSUE_IN_NUM_REG_RC ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_WRITE_RD ," in_ISSUE_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RD ," in_ISSUE_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_WRITE_RE ," in_ISSUE_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RE ," in_ISSUE_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_rename_unit,_param->_nb_inst_rename[it1]); + ALLOC1_SC_SIGNAL( in_REEXECUTE_VAL ," in_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_ACK ,"out_REEXECUTE_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_CONTEXT_ID ," in_REEXECUTE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_FRONT_END_ID ," in_REEXECUTE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_PACKET_ID ," in_REEXECUTE_PACKET_ID ",Tpacket_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_OPERATION ," in_REEXECUTE_OPERATION ",Toperation_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_TYPE ," in_REEXECUTE_TYPE ",Ttype_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE," in_REEXECUTE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ," in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT ," in_REEXECUTE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_IMMEDIAT ," in_REEXECUTE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_READ_RA ," in_REEXECUTE_READ_RA ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RA ," in_REEXECUTE_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_READ_RB ," in_REEXECUTE_READ_RB ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RB ," in_REEXECUTE_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_READ_RC ," in_REEXECUTE_READ_RC ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RC ," in_REEXECUTE_NUM_REG_RC ",Tspecial_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_WRITE_RD ," in_REEXECUTE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RD ," in_REEXECUTE_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_WRITE_RE ," in_REEXECUTE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RE ," in_REEXECUTE_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_VAL ,"out_ISSUE_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL( in_ISSUE_OUT_ACK ," in_ISSUE_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_CONTEXT_ID ,"out_ISSUE_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_FRONT_END_ID ,"out_ISSUE_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_PACKET_ID ,"out_ISSUE_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_OPERATION ,"out_ISSUE_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_TYPE ,"out_ISSUE_OUT_TYPE ",Ttype_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,"out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,"out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT ,"out_ISSUE_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_IMMEDIAT ,"out_ISSUE_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_READ_RA ,"out_ISSUE_OUT_READ_RA ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RA ,"out_ISSUE_OUT_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_READ_RB ,"out_ISSUE_OUT_READ_RB ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RB ,"out_ISSUE_OUT_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_READ_RC ,"out_ISSUE_OUT_READ_RC ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RC ,"out_ISSUE_OUT_NUM_REG_RC ",Tspecial_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_WRITE_RD ,"out_ISSUE_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RD ,"out_ISSUE_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_WRITE_RE ,"out_ISSUE_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RE ,"out_ISSUE_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_issue); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Issue_queue.\n"),name.c_str()); + + (*(_Issue_queue->in_CLOCK)) (*(in_CLOCK)); + (*(_Issue_queue->in_NRESET)) (*(in_NRESET)); + + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_VAL ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue,out_ISSUE_IN_ACK ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_CONTEXT_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_FRONT_END_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_PACKET_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_OPERATION ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_TYPE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_HAS_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_READ_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_NUM_REG_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_READ_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_NUM_REG_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_READ_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_NUM_REG_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_WRITE_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_NUM_REG_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_WRITE_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + INSTANCE2_SC_SIGNAL(_Issue_queue, in_ISSUE_IN_NUM_REG_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_HAS_IMMEDIAT ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_IMMEDIAT ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_READ_RA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_NUM_REG_RA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_READ_RB ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_NUM_REG_RB ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_READ_RC ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_NUM_REG_RC ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_WRITE_RD ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_NUM_REG_RD ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_WRITE_RE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_REEXECUTE_NUM_REG_RE ,_param->_nb_inst_reexecute); + + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_VAL ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue, in_ISSUE_OUT_ACK ,_param->_nb_inst_issue); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_CONTEXT_ID ,_param->_nb_inst_issue); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_FRONT_END_ID ,_param->_nb_inst_issue); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_PACKET_ID ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_OPERATION ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_TYPE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_HAS_IMMEDIAT ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_IMMEDIAT ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_READ_RA ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_NUM_REG_RA ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_READ_RB ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_NUM_REG_RB ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_READ_RC ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_NUM_REG_RC ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_WRITE_RD ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_NUM_REG_RD ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_WRITE_RE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_Issue_queue,out_ISSUE_OUT_NUM_REG_RE ,_param->_nb_inst_issue); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + // Initialisation + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + LABEL("Initialisation"); + + const int32_t percent_transaction_reexecute = 35; + const int32_t percent_transaction_issue_in = 65; + const int32_t percent_transaction_issue_out = 87; + + #define NB_TYPE 12 + + Ttype_t tab_type [] = {TYPE_ALU , + TYPE_SHIFT , + TYPE_MOVE , + TYPE_TEST , + TYPE_MUL , + TYPE_DIV , + TYPE_EXTEND , + TYPE_FIND , + TYPE_SPECIAL, + TYPE_CUSTOM , + TYPE_BRANCH , + TYPE_MEMORY }; + + set issue_queue; + + Tgeneral_data_t reexecute_immediat = 0xbeef; + Tgeneral_data_t reexecute_tab_immediat [_param->_nb_inst_reexecute]; + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + reexecute_tab_immediat [i] = reexecute_immediat++; + + Tgeneral_data_t issue_in_immediat = 0x1981; + Tgeneral_data_t issue_in_tab_immediat [_param->_nb_rename_unit][_param->_max_nb_inst_rename]; + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + issue_in_tab_immediat [i][j] = issue_in_immediat ++; + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_inst_reexecute; i++) + { + in_REEXECUTE_VAL [i]->write((rand()%100)write((imm<<1)|1); + in_REEXECUTE_TYPE [i]->write(tab_type[imm%NB_TYPE]); + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + { + in_ISSUE_IN_VAL [i][j]->write((rand()%100)write((imm<<1)|1); + in_ISSUE_IN_TYPE [i][j]->write(tab_type[imm%NB_TYPE]); + } + + for (uint32_t i=0; i<_param->_nb_inst_issue; i++) + { + in_ISSUE_OUT_ACK [i]->write((rand()%100)_nb_inst_issue; i++) + if (out_ISSUE_OUT_VAL [i]->read() and in_ISSUE_OUT_ACK [i]->read()) + { + LABEL("ISSUE_OUT [%d] - Transaction Accepted.",i); + + Tgeneral_data_t imm = out_ISSUE_OUT_IMMEDIAT[i]->read(); + + bool find = issue_queue.find(imm) != issue_queue.end(); + TEST(Tgeneral_data_t,imm, *issue_queue.find(imm)); + TEST(bool, find, true); + issue_queue.erase(imm); + + if (imm&1) + { + LABEL(" * REEXECUTE"); + } + else + { + LABEL(" * ISSUE_IN"); + } + + imm = imm>>1; + Ttype_t type = out_ISSUE_OUT_TYPE[i]->read(); + TEST(Ttype_t,type, tab_type[imm%NB_TYPE]); + TEST(bool ,_param->_table_issue_type[i][type],true); + } + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (in_REEXECUTE_VAL [i]->read() and out_REEXECUTE_ACK [i]->read()) + { + LABEL("REEXECUTE [%d] - Transaction Accepted.",i); + reexecute_tab_immediat [i] = reexecute_immediat; + reexecute_immediat ++; + + issue_queue.insert(in_REEXECUTE_IMMEDIAT [i]->read()); + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + if (in_ISSUE_IN_VAL [i][j]->read() and out_ISSUE_IN_ACK [i][j]->read()) + { + LABEL("ISSUE_IN [%d][%d] - Transaction Accepted.",i,j); + issue_in_tab_immediat [i][j] = issue_in_immediat; + issue_in_immediat ++; + + issue_queue.insert(in_ISSUE_IN_IMMEDIAT [i][j]->read()); + } + + bool test_size = issue_queue.size() <= _param->_size_queue; + TEST(bool,test_size,true); + + SC_START(1); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_ISSUE_IN_VAL ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL(out_ISSUE_IN_ACK ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_CONTEXT_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_FRONT_END_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_PACKET_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_OPERATION ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_TYPE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_READ_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_READ_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_READ_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_WRITE_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_WRITE_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + DELETE2_SC_SIGNAL( in_ISSUE_IN_NUM_REG_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + + DELETE1_SC_SIGNAL( in_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_IMMEDIAT ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_READ_RA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_READ_RB ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RB ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_READ_RC ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RC ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_WRITE_RD ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RD ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_WRITE_RE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_NUM_REG_RE ,_param->_nb_inst_reexecute); + + DELETE1_SC_SIGNAL(out_ISSUE_OUT_VAL ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL( in_ISSUE_OUT_ACK ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_CONTEXT_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_FRONT_END_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_PACKET_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_OPERATION ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_TYPE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_IMMEDIAT ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_READ_RA ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RA ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_READ_RB ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RB ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_READ_RC ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RC ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_WRITE_RD ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RD ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_WRITE_RE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OUT_NUM_REG_RE ,_param->_nb_inst_issue); + } +#endif + + delete _Issue_queue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Issue_queue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Issue_queue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Issue_queue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Issue_queue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h (revision 88) @@ -0,0 +1,215 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Issue_queue_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Issue_queue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + + class Issue_queue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; + private : counter_t ** _stat_bank_nb_inst; + private : counter_t * _stat_nb_inst_reexecute; + private : counter_t ** _stat_nb_inst_issue_in; + private : counter_t * _stat_nb_inst_issue_out; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "issue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_VAL ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_ISSUE_IN_ACK ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontext_t ) *** in_ISSUE_IN_CONTEXT_ID ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontext_t ) *** in_ISSUE_IN_FRONT_END_ID ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tpacket_t ) *** in_ISSUE_IN_PACKET_ID ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Toperation_t ) *** in_ISSUE_IN_OPERATION ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Ttype_t ) *** in_ISSUE_IN_TYPE ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tlsq_ptr_t ) *** in_ISSUE_IN_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tlsq_ptr_t ) *** in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_HAS_IMMEDIAT ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tgeneral_data_t ) *** in_ISSUE_IN_IMMEDIAT ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_READ_RA ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_IN_NUM_REG_RA ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_READ_RB ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_IN_NUM_REG_RB ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_READ_RC ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tspecial_address_t) *** in_ISSUE_IN_NUM_REG_RC ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_WRITE_RD ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tgeneral_address_t) *** in_ISSUE_IN_NUM_REG_RD ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_ISSUE_IN_WRITE_RE ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tspecial_address_t) *** in_ISSUE_IN_NUM_REG_RE ;//[nb_rename_unit][nb_inst_rename] + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_VAL ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_ACK ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_REEXECUTE_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_REEXECUTE_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_IN (Tpacket_t ) ** in_REEXECUTE_PACKET_ID ;//[nb_inst_reexecute] + public : SC_IN (Toperation_t ) ** in_REEXECUTE_OPERATION ;//[nb_inst_reexecute] + public : SC_IN (Ttype_t ) ** in_REEXECUTE_TYPE ;//[nb_inst_reexecute] + public : SC_IN (Tlsq_ptr_t ) ** in_REEXECUTE_STORE_QUEUE_PTR_WRITE;//[nb_inst_reexecute] + public : SC_IN (Tlsq_ptr_t ) ** in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_HAS_IMMEDIAT ;//[nb_inst_reexecute] + public : SC_IN (Tgeneral_data_t ) ** in_REEXECUTE_IMMEDIAT ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_READ_RA ;//[nb_inst_reexecute] + public : SC_IN (Tgeneral_address_t) ** in_REEXECUTE_NUM_REG_RA ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_READ_RB ;//[nb_inst_reexecute] + public : SC_IN (Tgeneral_address_t) ** in_REEXECUTE_NUM_REG_RB ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_READ_RC ;//[nb_inst_reexecute] + public : SC_IN (Tspecial_address_t) ** in_REEXECUTE_NUM_REG_RC ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_WRITE_RD ;//[nb_inst_reexecute] + public : SC_IN (Tgeneral_address_t) ** in_REEXECUTE_NUM_REG_RD ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_WRITE_RE ;//[nb_inst_reexecute] + public : SC_IN (Tspecial_address_t) ** in_REEXECUTE_NUM_REG_RE ;//[nb_inst_reexecute] + + // ~~~~~[ Interface : "issue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_VAL ;//[nb_inst_issue] + public : SC_IN (Tcontrol_t ) ** in_ISSUE_OUT_ACK ;//[nb_inst_issue] + public : SC_OUT(Tcontext_t ) ** out_ISSUE_OUT_CONTEXT_ID ;//[nb_inst_issue] + public : SC_OUT(Tcontext_t ) ** out_ISSUE_OUT_FRONT_END_ID ;//[nb_inst_issue] + public : SC_OUT(Tpacket_t ) ** out_ISSUE_OUT_PACKET_ID ;//[nb_inst_issue] + public : SC_OUT(Toperation_t ) ** out_ISSUE_OUT_OPERATION ;//[nb_inst_issue] + public : SC_OUT(Ttype_t ) ** out_ISSUE_OUT_TYPE ;//[nb_inst_issue] + public : SC_OUT(Tlsq_ptr_t ) ** out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE;//[nb_inst_issue] + public : SC_OUT(Tlsq_ptr_t ) ** out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_HAS_IMMEDIAT ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_data_t ) ** out_ISSUE_OUT_IMMEDIAT ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_READ_RA ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_OUT_NUM_REG_RA ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_READ_RB ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_OUT_NUM_REG_RB ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_READ_RC ;//[nb_inst_issue] + public : SC_OUT(Tspecial_address_t) ** out_ISSUE_OUT_NUM_REG_RC ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_WRITE_RD ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_OUT_NUM_REG_RD ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_OUT_WRITE_RE ;//[nb_inst_issue] + public : SC_OUT(Tspecial_address_t) ** out_ISSUE_OUT_NUM_REG_RE ;//[nb_inst_issue] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority_in ; + private : generic::priority::Priority * _priority_out; + private : generic::priority::Priority * _priority_reg; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : std::list * _issue_queue; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tcontrol_t * internal_BANK_IN_ACK ;//[nb_bank] + private : bool * internal_BANK_IN_IS_REEXECUTE ;//[nb_bank] + private : uint32_t * internal_BANK_IN_NUM_RENAME_UNIT ;//[nb_bank] + private : uint32_t * internal_BANK_IN_NUM_INST ;//[nb_bank] + + private : Tcontrol_t * internal_BANK_OUT_VAL ;//[nb_bank] + private : uint32_t * internal_BANK_OUT_NUM_INST ;//[nb_bank] +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Issue_queue); +#endif + public : Issue_queue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Issue_queue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); + public : void genMoore (void); + public : void genMealy (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h (revision 88) @@ -0,0 +1,103 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_context ; + public : uint32_t _nb_front_end ; + public : uint32_t _nb_rename_unit ; + public : uint32_t _size_queue ; + public : uint32_t _nb_bank ; +//public : uint32_t _size_packet ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; + public : uint32_t _nb_inst_issue ; + public : uint32_t * _nb_inst_rename ;//[nb_rename_unit] + public : uint32_t _nb_inst_reexecute ; + public : uint32_t _nb_rename_unit_select ; + public : Tpriority_t _priority ; + public : Tload_balancing_t _load_balancing ; + public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue] + public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type] + + public : uint32_t _nb_bank_select_out ; + public : uint32_t _max_nb_inst_rename ; + +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; + public : uint32_t _size_bank ; + +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_context , + uint32_t nb_front_end , + uint32_t nb_rename_unit , + uint32_t size_queue , + uint32_t nb_bank , + uint32_t size_packet , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + uint32_t nb_inst_issue , + uint32_t * nb_inst_rename , + uint32_t nb_inst_reexecute , + uint32_t nb_rename_unit_select , + Tpriority_t priority , + Tload_balancing_t load_balancing , + bool ** table_routing , + bool ** table_issue_type , + bool is_toplevel=false); + +// public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters & x); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Types.h (revision 88) @@ -0,0 +1,91 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_issue_queue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + class entry_t + { + public : Tcontext_t _context_id ; + public : Tcontext_t _front_end_id ; + public : Tpacket_t _packet_id ; + public : Toperation_t _operation ; + public : Ttype_t _type ; + public : Tlsq_ptr_t _store_queue_ptr_write ; + public : Tlsq_ptr_t _load_queue_ptr_write ; + public : Tcontrol_t _has_immediat ; + public : Tgeneral_data_t _immediat ; + public : Tcontrol_t _read_ra ; + public : Tgeneral_address_t _num_reg_ra ; + public : Tcontrol_t _read_rb ; + public : Tgeneral_address_t _num_reg_rb ; + public : Tcontrol_t _read_rc ; + public : Tspecial_address_t _num_reg_rc ; + public : Tcontrol_t _write_rd ; + public : Tgeneral_address_t _num_reg_rd ; + public : Tcontrol_t _write_re ; + public : Tspecial_address_t _num_reg_re ; + + public : entry_t (Tcontext_t context_id , + Tcontext_t front_end_id , + Tpacket_t packet_id , + Toperation_t operation , + Ttype_t type , + Tlsq_ptr_t store_queue_ptr_write , + Tlsq_ptr_t load_queue_ptr_write , + Tcontrol_t has_immediat , + Tgeneral_data_t immediat , + Tcontrol_t read_ra , + Tgeneral_address_t num_reg_ra , + Tcontrol_t read_rb , + Tgeneral_address_t num_reg_rb , + Tcontrol_t read_rc , + Tspecial_address_t num_reg_rc , + Tcontrol_t write_rd , + Tgeneral_address_t num_reg_rd , + Tcontrol_t write_re , + Tspecial_address_t num_reg_re ) + { + _context_id = context_id ; + _front_end_id = front_end_id ; + _packet_id = packet_id ; + _operation = operation ; + _type = type ; + _store_queue_ptr_write = store_queue_ptr_write; + _load_queue_ptr_write = load_queue_ptr_write ; + _has_immediat = has_immediat ; + _immediat = immediat ; + _read_ra = read_ra ; + _num_reg_ra = num_reg_ra ; + _read_rb = read_rb ; + _num_reg_rb = num_reg_rb ; + _read_rc = read_rc ; + _num_reg_rc = num_reg_rc ; + _write_rd = write_rd ; + _num_reg_rd = num_reg_rd ; + _write_re = write_re ; + _num_reg_re = num_reg_re ; + } + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue.cpp (revision 88) @@ -0,0 +1,168 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::Issue_queue" + Issue_queue::Issue_queue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Issue_queue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Issue_queue == true + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + + SC_METHOD (genMoore); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Method - genMealy"),_name.c_str()); + + SC_METHOD (genMealy); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + sensitive << (*(in_REEXECUTE_VAL [i])) + << (*(in_REEXECUTE_TYPE [i])); + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + sensitive // << (*(in_ISSUE_IN_VAL [i][j])) + << (*(in_ISSUE_IN_TYPE [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + for (uint32_t x=0; x<_param->_nb_inst_reexecute; x++) + { + (*(out_REEXECUTE_ACK [i])) (*(in_REEXECUTE_VAL [x])); + (*(out_REEXECUTE_ACK [i])) (*(in_REEXECUTE_TYPE [x])); + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + { + for (uint32_t x=0; x<_param->_nb_inst_reexecute; x++) + { + (*(out_ISSUE_IN_ACK [i][j])) (*(in_REEXECUTE_VAL [x])); + (*(out_ISSUE_IN_ACK [i][j])) (*(in_REEXECUTE_TYPE [x])); + } + + for (uint32_t x=0; x<_param->_nb_rename_unit; x++) + for (uint32_t y=0; y<_param->_nb_inst_rename[x]; y++) + { + (*(out_ISSUE_IN_ACK [i][j])) (*(in_ISSUE_IN_VAL [x][y])); + (*(out_ISSUE_IN_ACK [i][j])) (*(in_ISSUE_IN_TYPE [x][y])); + } + } +# endif + +#endif + } + log_end(Issue_queue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Issue_queue::~Issue_queue" + Issue_queue::~Issue_queue (void) + { + log_begin(Issue_queue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + + deallocation (); + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_allocation.cpp (revision 88) @@ -0,0 +1,188 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + + +#undef FUNCTION +#define FUNCTION "Issue_queue::allocation" + void Issue_queue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Issue_queue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Issue_queue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + + // ~~~~~[ Interface : "issue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("issue_in", IN, WEST, _("Rename_out / Insert Rob interface"),_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + + _ALLOC2_VALACK_IN ( in_ISSUE_IN_VAL ,VAL,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_VALACK_OUT(out_ISSUE_IN_ACK ,ACK,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + _ALLOC2_SIGNAL_IN ( in_ISSUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register,_param->_nb_rename_unit, _param->_nb_inst_rename[it1]); + } + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("reexecute", IN, NORTH, _("Instruction reexecute (store head/ spr access)"),_param->_nb_inst_reexecute); + + ALLOC1_VALACK_IN ( in_REEXECUTE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_REEXECUTE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + } + + // ~~~~~[ Interface : "issue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("issue_out",OUT, EAST, _("Go to issue network"),_param->_nb_inst_issue); + + ALLOC1_VALACK_OUT(out_ISSUE_OUT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_ISSUE_OUT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_ISSUE_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _issue_queue = new std::list [_param->_nb_bank]; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + internal_BANK_IN_ACK = new Tcontrol_t [_param->_nb_bank]; + internal_BANK_IN_IS_REEXECUTE = new bool [_param->_nb_bank]; + internal_BANK_IN_NUM_RENAME_UNIT = new uint32_t [_param->_nb_bank]; + internal_BANK_IN_NUM_INST = new uint32_t [_param->_nb_bank]; + + internal_BANK_OUT_VAL = new Tcontrol_t [_param->_nb_bank]; + internal_BANK_OUT_NUM_INST = new uint32_t [_param->_nb_bank]; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + _priority_in = new generic::priority::Priority (_name+"_priority_in" , + _param->_priority , + _param->_load_balancing, + _param->_nb_rename_unit, + _param->_nb_inst_rename, + _param->_nb_rename_unit_select); + + _priority_out = new generic::priority::Priority (_name+"_priority_out" , + _param->_priority , + _param->_nb_bank_select_out, + _param->_nb_bank_select_out); + + _priority_reg = new generic::priority::Priority (_name+"_priority_reg", + PRIORITY_ROUND_ROBIN , + _param->_nb_bank, + _param->_nb_bank); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_deallocation.cpp (revision 88) @@ -0,0 +1,125 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::deallocation" + void Issue_queue::deallocation (void) + { + log_begin(Issue_queue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_ISSUE_IN_VAL ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL(out_ISSUE_IN_ACK ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_CONTEXT_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_ISSUE_IN_FRONT_END_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_ISSUE_IN_PACKET_ID ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_rob_ptr ); + DELETE2_SIGNAL( in_ISSUE_IN_OPERATION ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_ISSUE_IN_TYPE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_type ); + DELETE2_SIGNAL( in_ISSUE_IN_STORE_QUEUE_PTR_WRITE,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL( in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL( in_ISSUE_IN_HAS_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_IMMEDIAT ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_ISSUE_IN_READ_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_NUM_REG_RA ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_IN_READ_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_NUM_REG_RB ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_IN_READ_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_NUM_REG_RC ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_special_register); + DELETE2_SIGNAL( in_ISSUE_IN_WRITE_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_NUM_REG_RD ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_ISSUE_IN_WRITE_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],1 ); + DELETE2_SIGNAL( in_ISSUE_IN_NUM_REG_RE ,_param->_nb_rename_unit, _param->_nb_inst_rename[it1],_param->_size_special_register); + + DELETE1_SIGNAL( in_REEXECUTE_VAL ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_ACK ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute,_param->_size_context_id ); + DELETE1_SIGNAL( in_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute,_param->_size_rob_ptr ); + DELETE1_SIGNAL( in_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute,_param->_size_operation ); + DELETE1_SIGNAL( in_REEXECUTE_TYPE ,_param->_nb_inst_reexecute,_param->_size_type ); + DELETE1_SIGNAL( in_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL( in_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL( in_REEXECUTE_HAS_IMMEDIAT ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_IMMEDIAT ,_param->_nb_inst_reexecute,_param->_size_general_data ); + DELETE1_SIGNAL( in_REEXECUTE_READ_RA ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_NUM_REG_RA ,_param->_nb_inst_reexecute,_param->_size_general_register); + DELETE1_SIGNAL( in_REEXECUTE_READ_RB ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_NUM_REG_RB ,_param->_nb_inst_reexecute,_param->_size_general_register); + DELETE1_SIGNAL( in_REEXECUTE_READ_RC ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_NUM_REG_RC ,_param->_nb_inst_reexecute,_param->_size_special_register); + DELETE1_SIGNAL( in_REEXECUTE_WRITE_RD ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_NUM_REG_RD ,_param->_nb_inst_reexecute,_param->_size_general_register); + DELETE1_SIGNAL( in_REEXECUTE_WRITE_RE ,_param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL( in_REEXECUTE_NUM_REG_RE ,_param->_nb_inst_reexecute,_param->_size_special_register); + + DELETE1_SIGNAL(out_ISSUE_OUT_VAL ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL( in_ISSUE_OUT_ACK ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_CONTEXT_ID ,_param->_nb_inst_issue,_param->_size_context_id ); + DELETE1_SIGNAL(out_ISSUE_OUT_FRONT_END_ID ,_param->_nb_inst_issue,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_ISSUE_OUT_PACKET_ID ,_param->_nb_inst_issue,_param->_size_rob_ptr ); + DELETE1_SIGNAL(out_ISSUE_OUT_OPERATION ,_param->_nb_inst_issue,_param->_size_operation ); + DELETE1_SIGNAL(out_ISSUE_OUT_TYPE ,_param->_nb_inst_issue,_param->_size_type ); + DELETE1_SIGNAL(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_issue,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL(out_ISSUE_OUT_HAS_IMMEDIAT ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_IMMEDIAT ,_param->_nb_inst_issue,_param->_size_general_data ); + DELETE1_SIGNAL(out_ISSUE_OUT_READ_RA ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_NUM_REG_RA ,_param->_nb_inst_issue,_param->_size_general_register); + DELETE1_SIGNAL(out_ISSUE_OUT_READ_RB ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_NUM_REG_RB ,_param->_nb_inst_issue,_param->_size_general_register); + DELETE1_SIGNAL(out_ISSUE_OUT_READ_RC ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_NUM_REG_RC ,_param->_nb_inst_issue,_param->_size_special_register); + DELETE1_SIGNAL(out_ISSUE_OUT_WRITE_RD ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_NUM_REG_RD ,_param->_nb_inst_issue,_param->_size_general_register); + DELETE1_SIGNAL(out_ISSUE_OUT_WRITE_RE ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_OUT_NUM_REG_RE ,_param->_nb_inst_issue,_param->_size_special_register); + + // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] _issue_queue; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_BANK_IN_ACK ; + delete [] internal_BANK_IN_IS_REEXECUTE ; + delete [] internal_BANK_IN_NUM_RENAME_UNIT; + delete [] internal_BANK_IN_NUM_INST ; + + delete [] internal_BANK_OUT_VAL ; + delete [] internal_BANK_OUT_NUM_INST ; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _priority_in ; + delete _priority_out; + delete _priority_reg; + delete _component; + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::end_cycle" +void Issue_queue::end_cycle () + { + log_begin(Issue_queue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMealy.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMealy.cpp (revision 88) @@ -0,0 +1,133 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::genMealy" + void Issue_queue::genMealy (void) + { + log_begin(Issue_queue,FUNCTION); + log_function(Issue_queue,FUNCTION,_name.c_str()); + + Tcontrol_t bank_full [_param->_nb_bank]; + Tcontrol_t issue_ack [_param->_nb_rename_unit][_param->_max_nb_inst_rename]; + Tcontrol_t reexecute_ack [_param->_nb_inst_reexecute]; + bool can_rename_select [_param->_nb_rename_unit]; + + // Initialisation + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + internal_BANK_IN_ACK [i] = false; + bank_full [i] = not (_issue_queue[i].size() < _param->_size_bank); + } + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + can_rename_select [i] = true; + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + issue_ack [i][j] = false; + } + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + reexecute_ack [i] = false; + + std::list * select_reg = _priority_reg->select(); // same select for all issue + + // Priority at the Reexecute instruction ! + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + // Test if have instruction + if (PORT_READ(in_REEXECUTE_VAL [i])) + { + Ttype_t type = PORT_READ(in_REEXECUTE_TYPE [i]); + + // scan all bank + for (std::list::iterator it=select_reg->begin(); + it!=select_reg->end(); + it++) + { + uint32_t num_bank = it->grp; + uint32_t num_issue = num_bank/_param->_nb_bank_select_out; + // test if bank is not busy (full or previous access) and if type match + if (not internal_BANK_IN_ACK [num_bank] and not bank_full [num_bank] and _param->_table_issue_type[num_issue][type]) + { + // find + reexecute_ack [i] = true; + internal_BANK_IN_ACK [num_bank] = true; + internal_BANK_IN_IS_REEXECUTE [num_bank] = 1; + internal_BANK_IN_NUM_INST [num_bank] = i; + break; + } + } + } + + // issue_in interface + std::list * select_in = _priority_in ->select(); // same select for all issue + for (std::list::iterator it=select_in ->begin(); + it!=select_in ->end(); + it++) + { + uint32_t num_rename_unit = it->grp; + uint32_t num_inst_rename = it->elt; + + // Test if have instruction + if (can_rename_select [num_rename_unit]// and +// PORT_READ(in_ISSUE_IN_VAL [num_rename_unit][num_inst_rename]) + ) + { + Ttype_t type = PORT_READ(in_ISSUE_IN_TYPE [num_rename_unit][num_inst_rename]); + + // scan all bank + for (std::list::iterator it=select_reg->begin(); + it!=select_reg->end(); + it++) + { + uint32_t num_bank = it->grp; + uint32_t num_issue = num_bank/_param->_nb_bank_select_out; + // test if bank is not busy (full or previous access) and if type match + if (not internal_BANK_IN_ACK [num_bank] and not bank_full [num_bank] and _param->_table_issue_type[num_issue][type]) + { + // find + issue_ack [num_rename_unit][num_inst_rename] = true; + internal_BANK_IN_ACK [num_bank] = true; + internal_BANK_IN_IS_REEXECUTE [num_bank] = 0; + internal_BANK_IN_NUM_RENAME_UNIT [num_bank] = num_rename_unit; + internal_BANK_IN_NUM_INST [num_bank] = num_inst_rename; + break; + } + } + + // is a valid instruction, but it's not send at a bank + // ... invalid this rename_unit (because, rename in_order) + can_rename_select [num_rename_unit] |= issue_ack [num_rename_unit][num_inst_rename]; + } + } + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + for (uint32_t j=0; j<_param->_nb_inst_rename[i]; j++) + PORT_WRITE(out_ISSUE_IN_ACK [i][j],issue_ack [i][j]); + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + PORT_WRITE(out_REEXECUTE_ACK [i],reexecute_ack [i]); + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMoore.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_genMoore.cpp (revision 88) @@ -0,0 +1,104 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::genMoore" + void Issue_queue::genMoore (void) + { + log_begin(Issue_queue,FUNCTION); + log_function(Issue_queue,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + internal_BANK_OUT_VAL [i] = false; + + std::list * select = _priority_out->select(); // same select for all issue + + uint32_t num_bank_offset = 0; + for (uint32_t i=0; i<_param->_nb_inst_issue; i++) + { +// log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT [%d]",i); + Tcontrol_t val = false; + uint32_t num_bank = 0; + + // find a non empty bank + for (std::list::iterator it=select->begin(); + it!=select->end(); + it++) + { + num_bank=num_bank_offset+it->grp; + +// log_printf(TRACE,Issue_queue,FUNCTION," * Bank [%d]",num_bank); + + if (not _issue_queue [num_bank].empty()) + { +// log_printf(TRACE,Issue_queue,FUNCTION," * Not Empty !!!"); + val = true; + + internal_BANK_OUT_NUM_INST [num_bank] = i; + break; // quit scearch loop + } + } + + PORT_WRITE(out_ISSUE_OUT_VAL [i], val); + + if (val) + { + // have find a bank with a data + internal_BANK_OUT_VAL [num_bank] = true; + + entry_t* entry = _issue_queue [num_bank].front(); + + if (_param->_have_port_context_id) + PORT_WRITE(out_ISSUE_OUT_CONTEXT_ID [i], entry->_context_id ); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_ISSUE_OUT_FRONT_END_ID [i], entry->_front_end_id ); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_ISSUE_OUT_PACKET_ID [i], entry->_packet_id ); + PORT_WRITE(out_ISSUE_OUT_OPERATION [i], entry->_operation ); + PORT_WRITE(out_ISSUE_OUT_TYPE [i], entry->_type ); + PORT_WRITE(out_ISSUE_OUT_STORE_QUEUE_PTR_WRITE [i], entry->_store_queue_ptr_write); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_ISSUE_OUT_LOAD_QUEUE_PTR_WRITE [i], entry->_load_queue_ptr_write ); + PORT_WRITE(out_ISSUE_OUT_HAS_IMMEDIAT [i], entry->_has_immediat ); + PORT_WRITE(out_ISSUE_OUT_IMMEDIAT [i], entry->_immediat ); + PORT_WRITE(out_ISSUE_OUT_READ_RA [i], entry->_read_ra ); + PORT_WRITE(out_ISSUE_OUT_NUM_REG_RA [i], entry->_num_reg_ra ); + PORT_WRITE(out_ISSUE_OUT_READ_RB [i], entry->_read_rb ); + PORT_WRITE(out_ISSUE_OUT_NUM_REG_RB [i], entry->_num_reg_rb ); + PORT_WRITE(out_ISSUE_OUT_READ_RC [i], entry->_read_rc ); + PORT_WRITE(out_ISSUE_OUT_NUM_REG_RC [i], entry->_num_reg_rc ); + PORT_WRITE(out_ISSUE_OUT_WRITE_RD [i], entry->_write_rd ); + PORT_WRITE(out_ISSUE_OUT_NUM_REG_RD [i], entry->_num_reg_rd ); + PORT_WRITE(out_ISSUE_OUT_WRITE_RE [i], entry->_write_re ); + PORT_WRITE(out_ISSUE_OUT_NUM_REG_RE [i], entry->_num_reg_re ); + } + + num_bank_offset += _param->_nb_bank_select_out; + } + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,103 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::statistics_allocation" + void Issue_queue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Issue_queue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Issue_queue", + param_statistics); + + _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; + _stat_nb_inst_issue_in = new counter_t * [_param->_nb_rename_unit]; + + // instruction + { + _stat_nb_inst_reexecute = _stat->create_variable("nb_inst_reexecute"); + + std::string sum_nb_inst_issue_in = ""; + std::string sum_average_use_interface_issue_in = ""; + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + { + _stat_nb_inst_issue_in [i] = _stat->create_variable("nb_inst_issue_in_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_use_interface_issue_in_"+toString(i), "nb_inst_issue_in_"+toString(i), "", toString(_("Average instruction by cycle on issue_in interface (rename_unit %d)"),i)); + _stat->create_expr_percent ("percent_use_interface_issue_in_"+toString(i) , "average_use_interface_issue_in_"+toString(i), toString(_param->_nb_inst_rename [i]), toString(_("Percent usage of issue_in interface (rename_unit %d)"),i)); + + if (i == 0) + { + sum_nb_inst_issue_in = "nb_inst_issue_in_"+toString(i); + sum_average_use_interface_issue_in = "average_use_interface_issue_in_"+toString(i); + } + else + { + sum_nb_inst_issue_in = "+ nb_inst_issue_in_"+toString(i) + " " +sum_nb_inst_issue_in; + sum_average_use_interface_issue_in = "+ average_use_interface_issue_in_"+toString(i)+ " "+sum_average_use_interface_issue_in; + } + } + + _stat->create_expr_average_by_cycle("average_use_interface_reexecute", "nb_inst_reexecute", "", _("Average instruction by cycle on reexecute interface")); + _stat->create_expr_percent ("percent_use_interface_reexecute" , "average_use_interface_reexecute", toString(_param->_nb_inst_reexecute), _("Percent usage of reexecute interface")); + + _stat->create_expr_average_by_cycle("average_inst_in", "+ nb_inst_reexecute " + sum_nb_inst_issue_in, "", _("Average instruction by cycle")); + _stat->create_expr_percent ("percent_inst_in" , "average_inst_in" , toString(_param->_nb_bank), _("Percent of instruction by cycle")); + _stat->create_expr_percent ("percent_inst_reexecute", "average_use_interface_reexecute" , "average_inst_in", _("Percent of instruction reexecute by cycle")); + _stat->create_expr_percent ("percent_inst_issue_in" , sum_average_use_interface_issue_in, "average_inst_in", _("Percent of instruction issue_in by cycle")); + } + + { + _stat_nb_inst_issue_out = _stat->create_variable("nb_inst_issue_out"); + + _stat->create_expr_average_by_cycle("average_use_interface_issue_out", "nb_inst_issue_out", "", _("Average instruction by cycle on issue_out interface")); + _stat->create_expr_percent ("percent_use_interface_issue_out" , "average_use_interface_issue_out", toString(_param->_nb_inst_issue), _("Percent usage of issue_out interface")); + } + + // bank/queue occupation + { + std::string sum_bank_nb_inst = ""; + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + _stat_bank_nb_inst [i] = _stat->create_variable("bank_nb_inst_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_occupation_bank_"+toString(i), "bank_nb_inst_"+toString(i), "", toString(_("Average instruction by cycle (bank %d)"),i)); + _stat->create_expr_percent ("percent_occupation_bank_"+toString(i), "average_occupation_bank_"+toString(i), toString(_param->_size_bank), toString(_("Percent occupation of bank (bank %d)"),i)); + + if (i == 0) + sum_bank_nb_inst = "bank_nb_inst_"+toString(i); + else + sum_bank_nb_inst = "+ bank_nb_inst_"+toString(i) + " " +sum_bank_nb_inst; + } + + _stat->create_expr_average_by_cycle("average_occupation_bank", sum_bank_nb_inst, "", _("Average instruction by cycle (all bank)")); + _stat->create_expr_percent ("percent_occupation_bank" , "average_occupation_bank", toString(_param->_size_queue), _("Percent occupation of issue_queue (all bank)")); + } + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,40 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::statistics_deallocation" + void Issue_queue::statistics_deallocation (void) + { + log_begin(Issue_queue,FUNCTION); + + log_printf(INFO,Issue_queue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + delete [] _stat_bank_nb_inst; + delete [] _stat_nb_inst_issue_in; + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_transition.cpp (revision 88) @@ -0,0 +1,174 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::transition" + void Issue_queue::transition (void) + { + log_begin(Issue_queue,FUNCTION); + log_function(Issue_queue,FUNCTION,_name.c_str()); + + if (PORT_READ(in_NRESET) == 0) + { + _priority_in ->reset(); + _priority_out->reset(); + _priority_reg->reset(); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + _issue_queue [i].clear(); + } + else + { + _priority_in ->transition(); + _priority_out->transition(); + _priority_reg->transition(); + + // =================================================================== + // =====[ ISSUE_IN ]================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (internal_BANK_IN_ACK [i]) + { + entry_t* entry = NULL; + + if (internal_BANK_IN_IS_REEXECUTE [i]) + { + uint32_t y = internal_BANK_IN_NUM_INST [i]; + + if (PORT_READ(in_REEXECUTE_VAL [y])) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_reexecute) ++; +#endif + entry = new entry_t + ( + (_param->_have_port_context_id )?PORT_READ(in_REEXECUTE_CONTEXT_ID [y]):0, + (_param->_have_port_front_end_id )?PORT_READ(in_REEXECUTE_FRONT_END_ID [y]):0, + (_param->_have_port_rob_ptr )?PORT_READ(in_REEXECUTE_PACKET_ID [y]):0, + PORT_READ(in_REEXECUTE_OPERATION [y]), + PORT_READ(in_REEXECUTE_TYPE [y]), + PORT_READ(in_REEXECUTE_STORE_QUEUE_PTR_WRITE [y]), + (_param->_have_port_load_queue_ptr)?PORT_READ(in_REEXECUTE_LOAD_QUEUE_PTR_WRITE [y]):0, + PORT_READ(in_REEXECUTE_HAS_IMMEDIAT [y]), + PORT_READ(in_REEXECUTE_IMMEDIAT [y]), + PORT_READ(in_REEXECUTE_READ_RA [y]), + PORT_READ(in_REEXECUTE_NUM_REG_RA [y]), + PORT_READ(in_REEXECUTE_READ_RB [y]), + PORT_READ(in_REEXECUTE_NUM_REG_RB [y]), + PORT_READ(in_REEXECUTE_READ_RC [y]), + PORT_READ(in_REEXECUTE_NUM_REG_RC [y]), + PORT_READ(in_REEXECUTE_WRITE_RD [y]), + PORT_READ(in_REEXECUTE_NUM_REG_RD [y]), + PORT_READ(in_REEXECUTE_WRITE_RE [y]), + PORT_READ(in_REEXECUTE_NUM_REG_RE [y]) + ); + } + } + else + { + uint32_t x = internal_BANK_IN_NUM_RENAME_UNIT [i]; + uint32_t y = internal_BANK_IN_NUM_INST [i]; + + if (PORT_READ(in_ISSUE_IN_VAL[x][y])) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_issue_in [x]) ++; +#endif + entry = new entry_t + ( + (_param->_have_port_context_id )?PORT_READ(in_ISSUE_IN_CONTEXT_ID [x][y]):0, + (_param->_have_port_front_end_id )?PORT_READ(in_ISSUE_IN_FRONT_END_ID [x][y]):0, + (_param->_have_port_rob_ptr )?PORT_READ(in_ISSUE_IN_PACKET_ID [x][y]):0, + PORT_READ(in_ISSUE_IN_OPERATION [x][y]), + PORT_READ(in_ISSUE_IN_TYPE [x][y]), + PORT_READ(in_ISSUE_IN_STORE_QUEUE_PTR_WRITE [x][y]), + (_param->_have_port_load_queue_ptr)?PORT_READ(in_ISSUE_IN_LOAD_QUEUE_PTR_WRITE [x][y]):0, + PORT_READ(in_ISSUE_IN_HAS_IMMEDIAT [x][y]), + PORT_READ(in_ISSUE_IN_IMMEDIAT [x][y]), + PORT_READ(in_ISSUE_IN_READ_RA [x][y]), + PORT_READ(in_ISSUE_IN_NUM_REG_RA [x][y]), + PORT_READ(in_ISSUE_IN_READ_RB [x][y]), + PORT_READ(in_ISSUE_IN_NUM_REG_RB [x][y]), + PORT_READ(in_ISSUE_IN_READ_RC [x][y]), + PORT_READ(in_ISSUE_IN_NUM_REG_RC [x][y]), + PORT_READ(in_ISSUE_IN_WRITE_RD [x][y]), + PORT_READ(in_ISSUE_IN_NUM_REG_RD [x][y]), + PORT_READ(in_ISSUE_IN_WRITE_RE [x][y]), + PORT_READ(in_ISSUE_IN_NUM_REG_RE [x][y]) + ); + } + } + + if (entry != NULL) + _issue_queue [i].push_back(entry); + } + + // =================================================================== + // =====[ ISSUE_OUT ]================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + { +// log_printf(TRACE,Issue_queue,FUNCTION," * internal_BANK_OUT [%d] val %d, num_inst %d",i,internal_BANK_OUT_VAL [i],internal_BANK_OUT_NUM_INST [i]); + + if (internal_BANK_OUT_VAL [i]) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_issue_out) ++; +#endif + + uint32_t x = internal_BANK_OUT_NUM_INST [i]; +// log_printf(TRACE,Issue_queue,FUNCTION," * ISSUE_OUT_ACK : %d",PORT_READ(in_ISSUE_OUT_ACK [x])); + + if (PORT_READ(in_ISSUE_OUT_ACK [x])) + { + entry_t * entry = _issue_queue [i].front(); + _issue_queue [i].pop_front(); + delete entry; + } + } + } + } + + log_printf(TRACE,Issue_queue,FUNCTION," * Info Issue_queue"); + for (uint32_t i=0; i<_param->_nb_bank; i++) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + *(_stat_bank_nb_inst [i]) += _issue_queue[i].size(); +#endif + log_printf(TRACE,Issue_queue,FUNCTION," * [%d] size : %d",i,(int)_issue_queue[i].size()); + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::vhdl" + void Issue_queue::vhdl (void) + { + log_begin(Issue_queue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::vhdl_body" + void Issue_queue::vhdl_body (Vhdl * & vhdl) + { + log_begin(Issue_queue,FUNCTION); + vhdl->set_body (""); + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Issue_queue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::vhdl_declaration" + void Issue_queue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Issue_queue,FUNCTION); + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters.cpp (revision 88) @@ -0,0 +1,120 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::Parameters" + Parameters::Parameters (uint32_t nb_context , + uint32_t nb_front_end , + uint32_t nb_rename_unit , + uint32_t size_queue , + uint32_t nb_bank , + uint32_t size_packet , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + uint32_t nb_inst_issue , + uint32_t * nb_inst_rename , + uint32_t nb_inst_reexecute , + uint32_t nb_rename_unit_select , + Tpriority_t priority , + Tload_balancing_t load_balancing , + bool ** table_routing , + bool ** table_issue_type , + bool is_toplevel ) + { + log_begin(Issue_queue,FUNCTION); + + _nb_context = nb_context ; + _nb_front_end = nb_front_end ; + _nb_rename_unit = nb_rename_unit ; + _size_queue = size_queue ; + _nb_bank = nb_bank ; + _nb_inst_issue = nb_inst_issue ; + _nb_inst_rename = nb_inst_rename ; + _nb_inst_reexecute = nb_inst_reexecute ; + _nb_rename_unit_select = nb_rename_unit_select; + _priority = priority ; + _load_balancing = load_balancing ; + _table_routing = table_routing ; + _table_issue_type = table_issue_type ; + + _max_nb_inst_rename = max(_nb_inst_rename,_nb_rename_unit); + _nb_bank_select_out = _nb_bank/nb_inst_issue; + + _size_bank = _size_queue / _nb_bank; + + test(); + + if (is_toplevel) + { + _size_context_id = log2(nb_context ); + _size_front_end_id = log2(nb_front_end); + _size_rob_ptr = size_packet ; + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_general_register = size_general_register; + _size_special_register = size_special_register; + _size_store_queue_ptr = size_store_queue_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + + _have_port_context_id = (_size_context_id > 0); + _have_port_front_end_id = (_size_front_end_id > 0); + _have_port_rob_ptr = (_size_rob_ptr > 0); + _have_port_load_queue_ptr = (_size_load_queue_ptr > 0); + + copy(); + } + + log_end(Issue_queue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Issue_queue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Issue_queue,FUNCTION); +// test(); +// log_end(Issue_queue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Issue_queue::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Issue_queue,FUNCTION); + log_end(Issue_queue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Issue_queue::copy" + void Parameters::copy (void) + { + log_begin(Issue_queue,FUNCTION); + log_end(Issue_queue,FUNCTION); + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,100 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Issue_queue,FUNCTION); + + Parameters_test test ("Issue_queue"); + + if (not is_multiple(_size_queue, _nb_bank)) + test.error(toString(_("nb_bank must be a multiple of size_queue.\n"))); + + if (not is_multiple(_nb_bank, _nb_inst_issue)) + test.error(toString(_("nb_inst_issue must be a multiple of nb_bank.\n"))); + + if (_nb_rename_unit_select > _nb_rename_unit) + test.error(toString(_("nb_rename_unit_select must be <= nb_rename_unit.\n"))); + + if (_size_bank == 1) + test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); + + bool type_valid [_nb_type]; + + for (uint32_t i=0; i<_nb_type; i++) + type_valid [i] = false; + + type_valid [TYPE_ALU ] = true; + type_valid [TYPE_SHIFT ] = true; + type_valid [TYPE_MOVE ] = true; + type_valid [TYPE_TEST ] = true; + type_valid [TYPE_MUL ] = true; + type_valid [TYPE_DIV ] = true; + type_valid [TYPE_EXTEND ] = true; + type_valid [TYPE_FIND ] = true; + type_valid [TYPE_SPECIAL] = true; + type_valid [TYPE_CUSTOM ] = true; + type_valid [TYPE_BRANCH ] = true; + type_valid [TYPE_MEMORY ] = true; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + bool type_present [_nb_type]; + + for (uint32_t j=0; j<_nb_type; j++) + type_present [j] = not type_valid [j]; + + bool find = false; + for (uint32_t j=0; j<_nb_inst_issue; j++) + if (_table_routing [i][j]) + { + find = true; + + for (uint32_t k=0; k<_nb_type; k++) + type_present [k] |= _table_issue_type [j][k]; + } + + if (not find) + test.error(toString(_("Rename_unit [%d] is not connected with a issue slot.\n"),i)); + else + for (uint32_t j=0; j<_nb_type; j++) + if (not type_present [j]) + test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString_type(j).c_str())); + } + + if ((_priority != PRIORITY_ROUND_ROBIN)) + test.error(toString(_("Unsupported priority scheme (Coming Soon). Supported scheme are : %s.\n"),toString(PRIORITY_ROUND_ROBIN).c_str())); + + if ((_load_balancing != LOAD_BALANCING_MAXIMUM_FOR_PRIORITY)) + test.error(toString(_("Unsupported load_balancing scheme (Coming Soon). Supported scheme are : %s.\n"),toString(LOAD_BALANCING_MAXIMUM_FOR_PRIORITY).c_str())); + + log_end(Issue_queue,FUNCTION); + + return test; + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,81 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace issue_queue { + + +#undef FUNCTION +#define FUNCTION "Issue_queue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Issue_queue,FUNCTION); + + XML xml ("issue_queue"); + + xml.balise_open("issue_queue"); + xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context )); xml.singleton_end(); + xml.singleton_begin("nb_front_end "); xml.attribut("value",toString(_nb_front_end )); xml.singleton_end(); + xml.singleton_begin("nb_rename_unit "); xml.attribut("value",toString(_nb_rename_unit )); xml.singleton_end(); + xml.singleton_begin("size_queue "); xml.attribut("value",toString(_size_queue )); xml.singleton_end(); + xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); +// xml.singleton_begin("size_packet "); xml.attribut("value",toString(_size_packet )); xml.singleton_end(); + xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); + xml.singleton_begin("size_special_data "); xml.attribut("value",toString(_size_special_data )); xml.singleton_end(); + xml.singleton_begin("size_general_register"); xml.attribut("value",toString(_size_general_register)); xml.singleton_end(); + xml.singleton_begin("size_special_register"); xml.attribut("value",toString(_size_special_register)); xml.singleton_end(); + xml.singleton_begin("size_store_queue_ptr "); xml.attribut("value",toString(_size_store_queue_ptr )); xml.singleton_end(); + xml.singleton_begin("size_load_queue_ptr "); xml.attribut("value",toString(_size_load_queue_ptr )); xml.singleton_end(); + xml.singleton_begin("nb_inst_issue "); xml.attribut("value",toString(_nb_inst_issue )); xml.singleton_end(); + xml.singleton_begin("nb_inst_reexecute "); xml.attribut("value",toString(_nb_inst_reexecute )); xml.singleton_end(); + xml.singleton_begin("nb_rename_unit_select"); xml.attribut("value",toString(_nb_rename_unit_select)); xml.singleton_end(); + xml.singleton_begin("priority "); xml.attribut("value",toString(_priority )); xml.singleton_end(); + xml.singleton_begin("load_balancing "); xml.attribut("value",toString(_load_balancing )); xml.singleton_end(); + for (uint32_t i=0;i<_nb_rename_unit; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","rename_unit"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_inst_rename "); xml.attribut("value",toString(_nb_inst_rename [i])); xml.singleton_end(); + xml. balise_close(); + } + xml.balise_close(); + + log_end(Issue_queue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Issue_queue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters & x) + { + log_begin(Issue_queue,FUNCTION); + + output_stream << x.print(0); + + log_end(Issue_queue,FUNCTION); + + return output_stream; + }; + +}; // end namespace issue_queue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libOOO_Engine.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Makefile.deps (revision 88) @@ -0,0 +1,80 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +OOO_Engine = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Commit_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/Makefile.deps +endif +ifndef Issue_queue +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/Makefile.deps +endif +ifndef Reexecute_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.deps +endif +ifndef Rename_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.deps +endif +ifndef Special_Register_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps +endif +ifndef OOO_Engine_Glue +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +OOO_Engine_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine + +#-----[ Library ]------------------------------------------ + +OOO_Engine_LIBRARY = -lOOO_Engine \ + $(Commit_unit_LIBRARY) \ + $(Issue_queue_LIBRARY) \ + $(Reexecute_unit_LIBRARY) \ + $(Rename_unit_LIBRARY) \ + $(Special_Register_unit_LIBRARY) \ + $(OOO_Engine_Glue_LIBRARY) \ + $(Behavioural_LIBRARY) + +OOO_Engine_DIR_LIBRARY = -L$(OOO_Engine_DIR)/lib \ + $(Commit_unit_DIR_LIBRARY) \ + $(Issue_queue_DIR_LIBRARY) \ + $(Reexecute_unit_DIR_LIBRARY) \ + $(Rename_unit_DIR_LIBRARY) \ + $(Special_Register_unit_DIR_LIBRARY) \ + $(OOO_Engine_Glue_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +OOO_Engine_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Commit_unit_library; \ + $(MAKE) Issue_queue_library; \ + $(MAKE) Reexecute_unit_library; \ + $(MAKE) Rename_unit_library; \ + $(MAKE) Special_Register_unit_library; \ + $(MAKE) OOO_Engine_Glue_library; \ + $(MAKE) --directory=$(OOO_Engine_DIR) --makefile=Makefile; + +OOO_Engine_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Commit_unit_library_clean; \ + $(MAKE) Issue_queue_library_clean; \ + $(MAKE) Reexecute_unit_library_clean; \ + $(MAKE) Rename_unit_library_clean; \ + $(MAKE) Special_Register_unit_library_clean; \ + $(MAKE) OOO_Engine_Glue_library_clean; \ + $(MAKE) --directory=$(OOO_Engine_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libOOO_Engine_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/Makefile.deps (revision 88) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +OOO_Engine_Glue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +OOO_Engine_Glue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue + +#-----[ Library ]------------------------------------------ + +OOO_Engine_Glue_LIBRARY = -lOOO_Engine_Glue \ + $(Behavioural_LIBRARY) + +OOO_Engine_Glue_DIR_LIBRARY = -L$(OOO_Engine_Glue_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +OOO_Engine_Glue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(OOO_Engine_Glue_DIR) --makefile=Makefile; + +OOO_Engine_Glue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(OOO_Engine_Glue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(OOO_Engine_Glue_LIBRARY) + +DIR_LIBRARY = $(OOO_Engine_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : OOO_Engine_Glue_library + +library_clean : OOO_Engine_Glue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_1.cfg (revision 88) @@ -0,0 +1,15 @@ +OOO_Engine_Glue +1 1 *2 # nb_front_end +1 1 *2 # nb_context [0] [nb_front_end] +1 1 *2 # nb_rename_unit +4 4 *2 # nb_inst_decod [0] [nb_front_end] +4 4 *2 # nb_inst_insert [0] [nb_rename_unit] +4 4 *2 # nb_inst_retire [0] [nb_rename_unit] +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 *2 # link_rename_unit_with_front_end [0] [nb_front_end] +2 2 *2 # size_packet_id +8 8 *2 # size_general_register +4 4 *2 # size_special_register +4 4 *2 # size_store_queue_ptr +4 4 *2 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_1-rename_unit_4.cfg (revision 88) @@ -0,0 +1,21 @@ +OOO_Engine_Glue +1 1 *2 # nb_front_end +1 1 *2 # nb_context [0] [nb_front_end] +4 4 *2 # nb_rename_unit +4 4 *2 # nb_inst_decod [0] [nb_front_end] +4 4 *2 # nb_inst_insert [0] [nb_rename_unit] +2 2 *2 # nb_inst_insert [1] [nb_rename_unit] +1 1 *2 # nb_inst_insert [2] [nb_rename_unit] +4 4 *2 # nb_inst_insert [3] [nb_rename_unit] +1 1 *2 # nb_inst_retire [0] [nb_rename_unit] +8 8 *2 # nb_inst_retire [1] [nb_rename_unit] +2 2 *2 # nb_inst_retire [2] [nb_rename_unit] +4 4 *2 # nb_inst_retire [3] [nb_rename_unit] +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 *2 # link_rename_unit_with_front_end [0] [nb_front_end] +2 2 *2 # size_packet_id +8 8 *2 # size_general_register +4 4 *2 # size_special_register +4 4 *2 # size_store_queue_ptr +4 4 *2 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_1.cfg (revision 88) @@ -0,0 +1,24 @@ +OOO_Engine_Glue +4 4 *2 # nb_front_end +4 4 *2 # nb_context [0] [nb_front_end] +1 1 *2 # nb_context [1] [nb_front_end] +2 2 *2 # nb_context [2] [nb_front_end] +8 8 *2 # nb_context [3] [nb_front_end] +1 1 *2 # nb_rename_unit +4 4 *2 # nb_inst_decod [0] [nb_front_end] +2 2 *2 # nb_inst_decod [1] [nb_front_end] +1 1 *2 # nb_inst_decod [2] [nb_front_end] +4 4 *2 # nb_inst_decod [3] [nb_front_end] +4 4 *2 # nb_inst_insert [0] [nb_rename_unit] +4 4 *2 # nb_inst_retire [0] [nb_rename_unit] +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 *2 # link_rename_unit_with_front_end [0] [nb_front_end] +0 0 *2 # link_rename_unit_with_front_end [1] [nb_front_end] +0 0 *2 # link_rename_unit_with_front_end [2] [nb_front_end] +0 0 *2 # link_rename_unit_with_front_end [3] [nb_front_end] +2 2 *2 # size_packet_id +8 8 *2 # size_general_register +4 4 *2 # size_special_register +4 4 *2 # size_store_queue_ptr +4 4 *2 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-front_end_4-rename_unit_4.cfg (revision 88) @@ -0,0 +1,30 @@ +OOO_Engine_Glue +4 4 *2 # nb_front_end +4 4 *2 # nb_context [0] [nb_front_end] +1 1 *2 # nb_context [1] [nb_front_end] +2 2 *2 # nb_context [2] [nb_front_end] +8 8 *2 # nb_context [3] [nb_front_end] +4 4 *2 # nb_rename_unit +4 4 *2 # nb_inst_decod [0] [nb_front_end] +2 2 *2 # nb_inst_decod [1] [nb_front_end] +1 1 *2 # nb_inst_decod [2] [nb_front_end] +4 4 *2 # nb_inst_decod [3] [nb_front_end] +4 4 *2 # nb_inst_insert [0] [nb_rename_unit] +2 2 *2 # nb_inst_insert [1] [nb_rename_unit] +1 1 *2 # nb_inst_insert [2] [nb_rename_unit] +4 4 *2 # nb_inst_insert [3] [nb_rename_unit] +1 1 *2 # nb_inst_retire [0] [nb_rename_unit] +8 8 *2 # nb_inst_retire [1] [nb_rename_unit] +2 2 *2 # nb_inst_retire [2] [nb_rename_unit] +4 4 *2 # nb_inst_retire [3] [nb_rename_unit] +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 *2 # link_rename_unit_with_front_end [0] [nb_front_end] +3 3 *2 # link_rename_unit_with_front_end [1] [nb_front_end] +1 1 *2 # link_rename_unit_with_front_end [2] [nb_front_end] +2 2 *2 # link_rename_unit_with_front_end [3] [nb_front_end] +2 2 *2 # size_packet_id +8 8 *2 # size_general_register +4 4 *2 # size_special_register +4 4 *2 # size_store_queue_ptr +4 4 *2 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,15 @@ +OOO_Engine_Glue +1 1 *2 # nb_front_end +1 1 *2 # nb_context [0] [nb_front_end] +1 1 *2 # nb_rename_unit +1 1 *2 # nb_inst_decod [0] [nb_front_end] +1 1 *2 # nb_inst_insert [0] [nb_rename_unit] +1 1 *2 # nb_inst_retire [0] [nb_rename_unit] +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 *2 # link_rename_unit_with_front_end [0] [nb_front_end] +0 0 *2 # size_packet_id +6 6 *2 # size_general_register +2 2 *2 # size_special_register +1 1 *2 # size_store_queue_ptr +0 0 *2 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,139 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 9 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t)\n")); + err (_(" * nb_context [nb_front_end] (uint32_t)\n")); + err (_(" * nb_rename_unit (uint32_t)\n")); + err (_(" * nb_inst_decod [nb_front_end] (uint32_t)\n")); + err (_(" * nb_inst_insert [nb_rename_unit] (uint32_t)\n")); + err (_(" * nb_inst_retire [nb_rename_unit] (uint32_t)\n")); + err (_(" * size_general_data (uint32_t)\n")); + err (_(" * size_special_data (uint32_t)\n")); + err (_(" * link_rename_unit_with_front_end [nb_front_end] (uint32_t)\n")); + err (_(" * size_packet_id (uint32_t)\n")); + err (_(" * size_general_register (uint32_t)\n")); + err (_(" * size_special_register (uint32_t)\n")); + err (_(" * size_store_queue_ptr (uint32_t)\n")); + err (_(" * size_load_queue_ptr (uint32_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end)) + usage (argc, argv); + + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; ++i) + _nb_context [i] = fromString(argv[x++]); + uint32_t _nb_rename_unit = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+3*_nb_front_end+2*_nb_rename_unit)) + usage (argc, argv); + + uint32_t * _nb_inst_decod = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; ++i) + _nb_inst_decod [i] = fromString(argv[x++]); + uint32_t * _nb_inst_insert = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; ++i) + _nb_inst_insert [i] = fromString(argv[x++]); + uint32_t * _nb_inst_retire = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; ++i) + _nb_inst_retire [i] = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + uint32_t * _link_rename_unit_with_front_end = new uint32_t [_nb_front_end]; + std::vector * _translate_front_end_id_from_rename_unit = new std::vector [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_front_end; ++i) + { + _link_rename_unit_with_front_end [i] = fromString(argv[x++]); + _translate_front_end_id_from_rename_unit[_link_rename_unit_with_front_end[i]].push_back(i); + } + + uint32_t _size_packet_id = fromString(argv[x++]); + uint32_t _size_general_register = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + uint32_t _size_store_queue_ptr = fromString(argv[x++]); + uint32_t _size_load_queue_ptr = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters + (_nb_front_end , + _nb_context , + _nb_rename_unit , + _nb_inst_decod , + _nb_inst_insert , + _nb_inst_retire , + _size_general_data , + _size_special_data , + _link_rename_unit_with_front_end , + _translate_front_end_id_from_rename_unit , + _size_packet_id , + _size_general_register , + _size_special_register , + _size_store_queue_ptr , + _size_load_queue_ptr , + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("OOO_Engine_Glue : no error"); + else + TEST_KO("OOO_Engine_Glue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _translate_front_end_id_from_rename_unit; + delete [] _link_rename_unit_with_front_end; + delete [] _nb_inst_retire ; + delete [] _nb_inst_insert ; + delete [] _nb_inst_decod ; + delete [] _nb_context ; + + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,502 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + OOO_Engine_Glue * _OOO_Engine_Glue = new OOO_Engine_Glue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_RENAME_FRONT_END_ID ," in_RENAME_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_RENAME_RENAME_UNIT_FRONT_END_ID ,"out_RENAME_RENAME_UNIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + ALLOC1_SC_SIGNAL(out_INSERT_VAL ,"out_INSERT_VAL ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_ACK ," in_INSERT_ACK ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RD_USE ,"out_INSERT_RD_USE ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RD_NUM_REG ,"out_INSERT_RD_NUM_REG ",Tgeneral_address_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RE_USE ,"out_INSERT_RE_USE ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,"out_INSERT_RE_NUM_REG ",Tspecial_address_t ,_param->_sum_inst_insert); + + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_VAL ," in_INSERT_RENAME_UNIT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_RENAME_UNIT_ACK ,"out_INSERT_RENAME_UNIT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_FRONT_END_ID ," in_INSERT_RENAME_UNIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_CONTEXT_ID ," in_INSERT_RENAME_UNIT_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_TYPE ," in_INSERT_RENAME_UNIT_TYPE ",Ttype_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_OPERATION ," in_INSERT_RENAME_UNIT_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NO_EXECUTE ," in_INSERT_RENAME_UNIT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ," in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT ," in_INSERT_RENAME_UNIT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE," in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ," in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA ," in_INSERT_RENAME_UNIT_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ," in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RB ," in_INSERT_RENAME_UNIT_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ," in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RC ," in_INSERT_RENAME_UNIT_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ," in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RD ," in_INSERT_RENAME_UNIT_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ," in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ," in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RE ," in_INSERT_RENAME_UNIT_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ," in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ," in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_VAL ,"out_INSERT_COMMIT_UNIT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_COMMIT_UNIT_ACK ," in_INSERT_COMMIT_UNIT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_FRONT_END_ID ,"out_INSERT_COMMIT_UNIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_CONTEXT_ID ,"out_INSERT_COMMIT_UNIT_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ,"out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_TYPE ,"out_INSERT_COMMIT_UNIT_TYPE ",Ttype_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_OPERATION ,"out_INSERT_COMMIT_UNIT_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE ,"out_INSERT_COMMIT_UNIT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE,"out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA ,"out_INSERT_COMMIT_UNIT_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ,"out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RB ,"out_INSERT_COMMIT_UNIT_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ,"out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RC ,"out_INSERT_COMMIT_UNIT_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ,"out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RD ,"out_INSERT_COMMIT_UNIT_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,"out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,"out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RE ,"out_INSERT_COMMIT_UNIT_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,"out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,"out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_VAL ,"out_INSERT_ISSUE_QUEUE_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ISSUE_QUEUE_ACK ," in_INSERT_ISSUE_QUEUE_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_CONTEXT_ID ,"out_INSERT_ISSUE_QUEUE_CONTEXT_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_FRONT_END_ID ,"out_INSERT_ISSUE_QUEUE_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_OPERATION ,"out_INSERT_ISSUE_QUEUE_OPERATION ",Toperation_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE ,"out_INSERT_ISSUE_QUEUE_TYPE ",Ttype_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE,"out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ,"out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_IMMEDIAT ,"out_INSERT_ISSUE_QUEUE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RA ,"out_INSERT_ISSUE_QUEUE_READ_RA ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RA ,"out_INSERT_ISSUE_QUEUE_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RB ,"out_INSERT_ISSUE_QUEUE_READ_RB ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RB ,"out_INSERT_ISSUE_QUEUE_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RC ,"out_INSERT_ISSUE_QUEUE_READ_RC ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RC ,"out_INSERT_ISSUE_QUEUE_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RD ,"out_INSERT_ISSUE_QUEUE_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RD ,"out_INSERT_ISSUE_QUEUE_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RE ,"out_INSERT_ISSUE_QUEUE_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,"out_INSERT_ISSUE_QUEUE_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + +// ALLOC1_SC_SIGNAL(out_RETIRE_VAL ,"out_RETIRE_VAL ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL( in_RETIRE_ACK ," in_RETIRE_ACK ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,"out_RETIRE_RD_OLD_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,"out_RETIRE_RD_OLD_NUM_REG ",Tgeneral_address_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,"out_RETIRE_RD_NEW_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,"out_RETIRE_RD_NEW_NUM_REG ",Tgeneral_address_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,"out_RETIRE_RE_OLD_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,"out_RETIRE_RE_OLD_NUM_REG ",Tspecial_address_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,"out_RETIRE_RE_NEW_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,"out_RETIRE_RE_NEW_NUM_REG ",Tspecial_address_t ,_param->_sum_inst_retire); + +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_VAL ,"out_RETIRE_RENAME_UNIT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_RENAME_UNIT_ACK ," in_RETIRE_RENAME_UNIT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_FRONT_END_ID ,"out_RETIRE_RENAME_UNIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RD ,"out_RETIRE_RENAME_UNIT_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,"out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,"out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RE ,"out_RETIRE_RENAME_UNIT_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,"out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,"out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_EVENT_STATE ,"out_RETIRE_RENAME_UNIT_EVENT_STATE ",Tevent_state_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_VAL ," in_RETIRE_COMMIT_UNIT_VAL ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL(out_RETIRE_COMMIT_UNIT_ACK ,"out_RETIRE_COMMIT_UNIT_ACK ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_FRONT_END_ID ," in_RETIRE_COMMIT_UNIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RD ," in_RETIRE_COMMIT_UNIT_WRITE_RD ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ," in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ," in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RE ," in_RETIRE_COMMIT_UNIT_WRITE_RE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ," in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ," in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// ALLOC2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_EVENT_STATE ," in_RETIRE_COMMIT_UNIT_EVENT_STATE ",Tevent_state_t ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + ALLOC2_SC_SIGNAL(out_SPR_SR_IEE ,"out_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_SR_EPH ,"out_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_RENAME_UNIT_SR ,"out_SPR_RENAME_UNIT_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_COMMIT_UNIT_SR_OVE ,"out_SPR_COMMIT_UNIT_SR_OVE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_SPECIAL_REGISTER_UNIT_SR ," in_SPR_SPECIAL_REGISTER_UNIT_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _OOO_Engine_Glue.\n"),name.c_str()); + + (*(_OOO_Engine_Glue->in_CLOCK)) (*(in_CLOCK)); + (*(_OOO_Engine_Glue->in_NRESET)) (*(in_NRESET)); + + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RENAME_RENAME_UNIT_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_VAL ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_ACK ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_RD_USE ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_RE_USE ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); + + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_INSERT_ISSUE_QUEUE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + if (_param->_have_port_load_queue_ptr) + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_NUM_REG_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_NUM_REG_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_NUM_REG_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_NUM_REG_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_VAL ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_ACK ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); + +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// if (_param->_have_port_front_end_id) +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_RENAME_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_RETIRE_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// if (_param->_have_port_front_end_id) +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_RETIRE_COMMIT_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_SPR_RENAME_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue,out_SPR_COMMIT_UNIT_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine_Glue, in_SPR_SPECIAL_REGISTER_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_rename_unit; ++i) +// for (uint32_t j=0; j<_param->_nb_inst_retire[i]; ++j) +// { + +// } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + in_SPR_SPECIAL_REGISTER_UNIT_SR [i][j]->write(rand()); + } + + SC_START(0); + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + Tspr_t sr = in_SPR_SPECIAL_REGISTER_UNIT_SR [i][j]->read(); + + TEST(Tspr_t ,out_SPR_RENAME_UNIT_SR [i][j]->read(),((sr|(1<<15))&0xf001ffff)); // with FO, and without reserved + TEST(Tcontrol_t,out_SPR_SR_IEE [i][j]->read(),(sr>> 2)&1); + TEST(Tcontrol_t,out_SPR_SR_EPH [i][j]->read(),(sr>>14)&1); + TEST(Tcontrol_t,out_SPR_COMMIT_UNIT_SR_OVE [i][j]->read(),(sr>>12)&1); + } + + SC_START(1); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_RENAME_RENAME_UNIT_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + DELETE1_SC_SIGNAL(out_INSERT_VAL ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_ACK ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RD_USE ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RE_USE ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); + + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +//DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL( in_INSERT_ISSUE_QUEUE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + DELETE2_SC_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + +// DELETE1_SC_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); + +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_RENAME_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL(out_RETIRE_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// DELETE2_SC_SIGNAL( in_RETIRE_COMMIT_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + + DELETE2_SC_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_RENAME_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_COMMIT_UNIT_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_SPECIAL_REGISTER_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + } +#endif + + delete _OOO_Engine_Glue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/OOO_Engine_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/OOO_Engine_Glue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/OOO_Engine_Glue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{OOO_Engine_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h (revision 88) @@ -0,0 +1,256 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_OOO_Engine_Glue_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_OOO_Engine_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + + class OOO_Engine_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontext_t ) *** in_RENAME_FRONT_END_ID ;//[nb_front_end][nb_inst_decod] + public : SC_OUT(Tcontext_t ) *** out_RENAME_RENAME_UNIT_FRONT_END_ID ;//[nb_front_end][nb_inst_decod] + + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_INSERT_VAL ;//[sum_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_ACK ;//[sum_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RD_USE ;//[sum_inst_insert] + public : SC_OUT(Tgeneral_address_t ) ** out_INSERT_RD_NUM_REG ;//[sum_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RE_USE ;//[sum_inst_insert] + public : SC_OUT(Tspecial_address_t ) ** out_INSERT_RE_NUM_REG ;//[sum_inst_insert] + + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_VAL ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_RENAME_UNIT_ACK ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontext_t ) *** in_INSERT_RENAME_UNIT_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Ttype_t ) *** in_INSERT_RENAME_UNIT_TYPE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Toperation_t ) *** in_INSERT_RENAME_UNIT_OPERATION ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_data_t ) *** in_INSERT_RENAME_UNIT_IMMEDIAT ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tlsq_ptr_t ) *** in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_READ_RA ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_READ_RB ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_READ_RC ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_WRITE_RD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tgeneral_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_RENAME_UNIT_WRITE_RE ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tspecial_address_t ) *** in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_VAL ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Tcontrol_t ) *** in_INSERT_COMMIT_UNIT_ACK ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontext_t ) *** out_INSERT_COMMIT_UNIT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontext_t ) *** out_INSERT_COMMIT_UNIT_CONTEXT_ID ;//[nb_rename_unit][nb_inst_insert] +//public : SC_OUT(Tcontext_t ) *** out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Ttype_t ) *** out_INSERT_COMMIT_UNIT_TYPE ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Toperation_t ) *** out_INSERT_COMMIT_UNIT_OPERATION ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_READ_RA ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_READ_RB ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_READ_RC ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tspecial_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_WRITE_RD ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_COMMIT_UNIT_WRITE_RE ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tspecial_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_insert] + public : SC_OUT(Tspecial_address_t ) *** out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_VAL ;//[nb_rename_unit][nb_inst_rename] + public : SC_IN (Tcontrol_t ) *** in_INSERT_ISSUE_QUEUE_ACK ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_CONTEXT_ID ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontext_t ) *** out_INSERT_ISSUE_QUEUE_FRONT_END_ID ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Toperation_t ) *** out_INSERT_ISSUE_QUEUE_OPERATION ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Ttype_t ) *** out_INSERT_ISSUE_QUEUE_TYPE ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tlsq_ptr_t ) *** out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tgeneral_data_t ) *** out_INSERT_ISSUE_QUEUE_IMMEDIAT ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RA ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RA ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RB ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RB ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_READ_RC ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RC ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RD ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tgeneral_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RD ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tcontrol_t ) *** out_INSERT_ISSUE_QUEUE_WRITE_RE ;//[nb_rename_unit][nb_inst_rename] + public : SC_OUT(Tspecial_address_t ) *** out_INSERT_ISSUE_QUEUE_NUM_REG_RE ;//[nb_rename_unit][nb_inst_rename] + +// // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_VAL ;//[sum_inst_retire] +// public : SC_IN (Tcontrol_t ) ** in_RETIRE_ACK ;//[sum_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RD_OLD_USE ;//[sum_inst_retire] +// public : SC_OUT(Tgeneral_address_t ) ** out_RETIRE_RD_OLD_NUM_REG ;//[sum_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RD_NEW_USE ;//[sum_inst_retire] +// public : SC_OUT(Tgeneral_address_t ) ** out_RETIRE_RD_NEW_NUM_REG ;//[sum_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RE_OLD_USE ;//[sum_inst_retire] +// public : SC_OUT(Tspecial_address_t ) ** out_RETIRE_RE_OLD_NUM_REG ;//[sum_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RE_NEW_USE ;//[sum_inst_retire] +// public : SC_OUT(Tspecial_address_t ) ** out_RETIRE_RE_NEW_NUM_REG ;//[sum_inst_retire] + +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RENAME_UNIT_VAL ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_RENAME_UNIT_ACK ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tcontext_t ) *** out_RETIRE_RENAME_UNIT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RENAME_UNIT_WRITE_RD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tgeneral_address_t ) *** out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_RENAME_UNIT_WRITE_RE ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tspecial_address_t ) *** out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tevent_state_t ) *** out_RETIRE_RENAME_UNIT_EVENT_STATE ;//[nb_rename_unit][nb_inst_retire] + +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_COMMIT_UNIT_VAL ;//[nb_rename_unit][nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) *** out_RETIRE_COMMIT_UNIT_ACK ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tcontext_t ) *** in_RETIRE_COMMIT_UNIT_FRONT_END_ID ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_COMMIT_UNIT_WRITE_RD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tgeneral_address_t ) *** in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tgeneral_address_t ) *** in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tcontrol_t ) *** in_RETIRE_COMMIT_UNIT_WRITE_RE ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tspecial_address_t ) *** in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tspecial_address_t ) *** in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ;//[nb_rename_unit][nb_inst_retire] +// public : SC_IN (Tevent_state_t ) *** in_RETIRE_COMMIT_UNIT_EVENT_STATE ;//[nb_rename_unit][nb_inst_retire] + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_SPR_SR_IEE ;//[nb_front_end][nb_context] - Interrupt Exception Enabled + public : SC_OUT(Tcontrol_t ) *** out_SPR_SR_EPH ;//[nb_front_end][nb_context] - Exception Prefix High + public : SC_OUT(Tspr_t ) *** out_SPR_RENAME_UNIT_SR ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_COMMIT_UNIT_SR_OVE ;//[nb_front_end][nb_context] + public : SC_IN (Tspr_t ) *** in_SPR_SPECIAL_REGISTER_UNIT_SR ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (OOO_Engine_Glue); +#endif + public : OOO_Engine_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~OOO_Engine_Glue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_rename (void); + public : void genMealy_insert_valack (void); + public : void genMealy_insert (void); + public : void genMealy_retire_valack (void); + public : void genMealy_retire (void); + public : void genMealy_spr (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h (revision 88) @@ -0,0 +1,100 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Types.h" +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + +// #define translateFrontEndIdToRenameUnit(front_end_id) _param->_translate_front_end_id_to_rename_unit[front_end_id] +// #define translateFrontEndIdFromRenameUnit(num_rename_unit,front_end_id) _param->_translate_front_end_id_from_rename_unit[num_rename_unit][front_end_id] + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_rename_unit ; + public : uint32_t * _nb_inst_decod ;//[nb_front_end] + public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] + public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t * _link_rename_unit_with_front_end ;//[nb_front_end] + public : std::vector * _translate_front_end_id_from_rename_unit;//[nb_rename_unit] +//public : uint32_t _size_packet_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; + +//public : uint32_t * _rename_unit_nb_front_end ;//[nb_rename_unit] +//public : uint32_t ** _rename_unit_nb_context ;//[nb_rename_unit][nb_front_end] +//public : uint32_t * _rename_unit_size_front_end_id ;//[nb_rename_unit] +//public : uint32_t * _rename_unit_size_context_id ;//[nb_rename_unit] +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; + public : uint32_t _size_rename_id ; + public : uint32_t _sum_inst_insert ; +//public : uint32_t _sum_inst_retire ; + public : uint32_t * _translate_front_end_id_to_rename_unit ;//[nb_front_end] + public : Tgeneral_address_t _mask_num_general_register ; + public : Tspecial_address_t _mask_num_special_register ; + +//public : bool _have_port_front_end_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_rename_unit , + uint32_t * nb_inst_decod , + uint32_t * nb_inst_insert , + uint32_t * nb_inst_retire , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t * link_rename_unit_with_front_end , + std::vector * translate_front_end_id_from_rename_unit, + uint32_t size_packet_id , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + bool is_toplevel=false); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters & x); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Types.h (revision 88) @@ -0,0 +1,29 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_ooo_engine_glue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue.cpp (revision 88) @@ -0,0 +1,259 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::OOO_Engine_Glue" + OOO_Engine_Glue::OOO_Engine_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_OOO_Engine_Glue == true + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + if (_param->_have_port_front_end_id) + { + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_rename"),_name.c_str()); + + SC_METHOD (genMealy_rename); + dont_initialize (); + //sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + sensitive << (*(in_RENAME_FRONT_END_ID [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + } + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_insert_valack"),_name.c_str()); + + SC_METHOD (genMealy_insert_valack); + dont_initialize (); + //sensitive << (*(in_CLOCK)).neg(); // don't need internal register + { + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) + sensitive << (*(in_INSERT_ACK [x++] )) + << (*(in_INSERT_RENAME_UNIT_VAL [i][j])) + << (*(in_INSERT_RENAME_UNIT_NO_EXECUTE [i][j])) + << (*(in_INSERT_COMMIT_UNIT_ACK [i][j])) + << (*(in_INSERT_ISSUE_QUEUE_ACK [i][j])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_insert"),_name.c_str()); + + SC_METHOD (genMealy_insert); + dont_initialize (); + //sensitive << (*(in_CLOCK)).neg(); // don't need internal register + + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i];++j) + { + if (_param->_have_port_front_end_id) + sensitive << (*(in_INSERT_RENAME_UNIT_FRONT_END_ID [i][j])); + if (_param->_have_port_context_id) + sensitive << (*(in_INSERT_RENAME_UNIT_CONTEXT_ID [i][j])); + if (_param->_have_port_load_queue_ptr) + sensitive << (*(in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE [i][j])); + sensitive << (*(in_INSERT_RENAME_UNIT_TYPE [i][j])) + << (*(in_INSERT_RENAME_UNIT_OPERATION [i][j])) + << (*(in_INSERT_RENAME_UNIT_NO_EXECUTE [i][j])) + << (*(in_INSERT_RENAME_UNIT_HAS_IMMEDIAT [i][j])) + << (*(in_INSERT_RENAME_UNIT_IMMEDIAT [i][j])) + << (*(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE [i][j])) + << (*(in_INSERT_RENAME_UNIT_READ_RA [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY [i][j])) + << (*(in_INSERT_RENAME_UNIT_READ_RB [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY [i][j])) + << (*(in_INSERT_RENAME_UNIT_READ_RC [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY [i][j])) + << (*(in_INSERT_RENAME_UNIT_WRITE_RD [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW [i][j])) + << (*(in_INSERT_RENAME_UNIT_WRITE_RE [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD [i][j])) + << (*(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW [i][j])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_retire_valack"),_name.c_str()); + +// SC_METHOD (genMealy_retire_valack); +// dont_initialize (); +// //sensitive << (*(in_CLOCK)).neg(); // don't need internal register +// { +// uint32_t x=0; +// for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) +// for (uint32_t j=0; j<_param->_nb_inst_retire[i]; ++j) +// sensitive +// << (*(in_RETIRE_ACK [x++])) +// << (*(in_RETIRE_RENAME_UNIT_ACK [i][j])) +// << (*(in_RETIRE_COMMIT_UNIT_VAL [i][j])); +// } + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + +// log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_retire"),_name.c_str()); + +// SC_METHOD (genMealy_retire); +// dont_initialize (); +// //sensitive << (*(in_CLOCK)).neg(); // don't need internal register +// for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) +// for (uint32_t j=0; j<_param->_nb_inst_retire[i]; ++j) +// { +// if (_param->_have_port_front_end_id) +// sensitive << (*( in_RETIRE_COMMIT_UNIT_FRONT_END_ID [i][j])); +// sensitive << (*( in_RETIRE_COMMIT_UNIT_WRITE_RD [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_WRITE_RE [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW [i][j])) +// << (*( in_RETIRE_COMMIT_UNIT_EVENT_STATE [i][j])); +// } + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Method - genMealy_spr"),_name.c_str()); + + SC_METHOD (genMealy_spr); + dont_initialize (); + //sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + sensitive << (*(in_SPR_SPECIAL_REGISTER_UNIT_SR [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + +#endif + } + log_end(OOO_Engine_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::~OOO_Engine_Glue" + OOO_Engine_Glue::~OOO_Engine_Glue (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 88) @@ -0,0 +1,219 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::allocation" + void OOO_Engine_Glue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"OOO_Engine_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("rename",IN, SOUTH,_("rename's interface"),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + _ALLOC2_SIGNAL_IN ( in_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_OUT(out_RENAME_RENAME_UNIT_FRONT_END_ID ,"RENAME_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + } + + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("insert",OUT, WEST,_("insert's interface"),_param->_sum_inst_insert); + + ALLOC1_SIGNAL_OUT (out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_INSERT_ACK ,"ACK" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_INSERT_RD_USE ,"RD_USE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_INSERT_RD_NUM_REG ,"RD_NUM_REG" ,Tgeneral_address_t ,_param->_size_general_register); + ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_general_register); + } + + { + ALLOC2_INTERFACE("insert",IN, EAST,_("insert's interface"),_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_RENAME_UNIT_ACK ,"RENAME_UNIT_ACK" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_FRONT_END_ID ,"RENAME_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_CONTEXT_ID ,"RENAME_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_TYPE ,"RENAME_UNIT_TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_OPERATION ,"RENAME_UNIT_OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NO_EXECUTE ,"RENAME_UNIT_NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ,"RENAME_UNIT_HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_IMMEDIAT ,"RENAME_UNIT_IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE ,"RENAME_UNIT_STORE_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ,"RENAME_UNIT_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_READ_RA ,"RENAME_UNIT_READ_RA" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ,"RENAME_UNIT_NUM_REG_RA_PHY" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_READ_RB ,"RENAME_UNIT_READ_RB" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ,"RENAME_UNIT_NUM_REG_RB_PHY" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_READ_RC ,"RENAME_UNIT_READ_RC" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ,"RENAME_UNIT_NUM_REG_RC_PHY" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_WRITE_RD ,"RENAME_UNIT_WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,"RENAME_UNIT_NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,"RENAME_UNIT_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_WRITE_RE ,"RENAME_UNIT_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,"RENAME_UNIT_NUM_REG_RE_PHY_OLD" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,"RENAME_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_VAL ,"COMMIT_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_COMMIT_UNIT_ACK ,"COMMIT_UNIT_ACK" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_FRONT_END_ID ,"COMMIT_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_CONTEXT_ID ,"COMMIT_UNIT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); +// _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ,"COMMIT_UNIT_RENAME_UNIT_ID" ,Tcontext_t ,_param->_size_rename_unit_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_TYPE ,"COMMIT_UNIT_TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_OPERATION ,"COMMIT_UNIT_OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NO_EXECUTE ,"COMMIT_UNIT_NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE ,"COMMIT_UNIT_STORE_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,"COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_READ_RA ,"COMMIT_UNIT_READ_RA" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ,"COMMIT_UNIT_NUM_REG_RA_PHY" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_READ_RB ,"COMMIT_UNIT_READ_RB" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ,"COMMIT_UNIT_NUM_REG_RB_PHY" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_READ_RC ,"COMMIT_UNIT_READ_RC" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ,"COMMIT_UNIT_NUM_REG_RC_PHY" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_WRITE_RD ,"COMMIT_UNIT_WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,"COMMIT_UNIT_NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_WRITE_RE ,"COMMIT_UNIT_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,"COMMIT_UNIT_NUM_REG_RE_PHY_OLD" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_VAL ,"ISSUE_QUEUE_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ISSUE_QUEUE_ACK ,"ISSUE_QUEUE_ACK" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_FRONT_END_ID ,"ISSUE_QUEUE_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_CONTEXT_ID ,"ISSUE_QUEUE_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_OPERATION ,"ISSUE_QUEUE_OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_TYPE ,"ISSUE_QUEUE_TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ,"ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,"ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ,"ISSUE_QUEUE_HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_IMMEDIAT ,"ISSUE_QUEUE_IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_READ_RA ,"ISSUE_QUEUE_READ_RA" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RA ,"ISSUE_QUEUE_NUM_REG_RA" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_READ_RB ,"ISSUE_QUEUE_READ_RB" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RB ,"ISSUE_QUEUE_NUM_REG_RB" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_READ_RC ,"ISSUE_QUEUE_READ_RC" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RC ,"ISSUE_QUEUE_NUM_REG_RC" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_WRITE_RD ,"ISSUE_QUEUE_WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RD ,"ISSUE_QUEUE_NUM_REG_RD" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_WRITE_RE ,"ISSUE_QUEUE_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_OUT(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,"ISSUE_QUEUE_NUM_REG_RE" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + } + +// // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// { +// ALLOC1_INTERFACE("retire",OUT, WEST,_("retire's interface"),_param->_sum_inst_retire); + +// ALLOC1_SIGNAL_OUT (out_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_IN ( in_RETIRE_ACK ,"ACK" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_OLD_USE ,"RD_OLD_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_OLD_NUM_REG ,"RD_OLD_NUM_REG" ,Tgeneral_address_t ,_param->_size_general_register); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_NEW_USE ,"RD_NEW_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_NEW_NUM_REG ,"RD_NEW_NUM_REG" ,Tgeneral_address_t ,_param->_size_general_register); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_OLD_USE ,"RE_OLD_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_OLD_NUM_REG ,"RE_OLD_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); +// } + +// { +// ALLOC2_INTERFACE("retire",IN, EAST,_("retire's interface"),_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_VAL ,"RENAME_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_RENAME_UNIT_ACK ,"RENAME_UNIT_ACK" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_FRONT_END_ID ,"RENAME_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_WRITE_RD ,"RENAME_UNIT_WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,"RENAME_UNIT_NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,"RENAME_UNIT_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_WRITE_RE ,"RENAME_UNIT_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,"RENAME_UNIT_NUM_REG_RE_PHY_OLD" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,"RENAME_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_RENAME_UNIT_EVENT_STATE ,"RENAME_UNIT_EVENT_STATE" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); + +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_VAL ,"COMMIT_UNIT_VAL" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_OUT(out_RETIRE_COMMIT_UNIT_ACK ,"COMMIT_UNIT_ACK" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_FRONT_END_ID ,"COMMIT_UNIT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_WRITE_RD ,"COMMIT_UNIT_WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,"COMMIT_UNIT_NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t ,_param->_size_general_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_WRITE_RE ,"COMMIT_UNIT_WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,"COMMIT_UNIT_NUM_REG_RE_PHY_OLD" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,"COMMIT_UNIT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t ,_param->_size_special_register,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// _ALLOC2_SIGNAL_IN ( in_RETIRE_COMMIT_UNIT_EVENT_STATE ,"COMMIT_UNIT_EVENT_STATE" ,Tevent_state_t ,_param->_size_event_state ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1]); +// } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr",IN, NORTH,_("spr's interface"),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_RENAME_UNIT_SR ,"RENAME_UNIT_SR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_COMMIT_UNIT_SR_OVE ,"COMMIT_UNIT_SR_OVE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_SPECIAL_REGISTER_UNIT_SR ,"SPECIAL_REGISTER_UNIT_SR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_deallocation.cpp (revision 88) @@ -0,0 +1,160 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::deallocation" + void OOO_Engine_Glue::deallocation (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL(out_RENAME_RENAME_UNIT_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_front_end_id ); + + DELETE1_SIGNAL(out_INSERT_VAL ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_ACK ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RD_USE ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert,_param->_size_general_register); + DELETE1_SIGNAL(out_INSERT_RE_USE ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert,_param->_size_general_register); + + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NO_EXECUTE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + DELETE2_SIGNAL( in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); +// DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_rename_unit_id ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + DELETE2_SIGNAL(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_VAL ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL( in_INSERT_ISSUE_QUEUE_ACK ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_CONTEXT_ID ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_context_id ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_OPERATION ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_operation ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_TYPE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_type ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_store_queue_ptr ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_load_queue_ptr ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_IMMEDIAT ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_data ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RA ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RB ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_READ_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RC ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RD ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_general_register); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],1 ); + DELETE2_SIGNAL(out_INSERT_ISSUE_QUEUE_NUM_REG_RE ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1],_param->_size_special_register); + +// DELETE1_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire,_param->_size_general_register); +// DELETE1_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_general_register); +// DELETE1_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register); +// DELETE1_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register); + +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_RENAME_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_front_end_id ); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register); +// DELETE2_SIGNAL(out_RETIRE_RENAME_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_event_state ); + +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_VAL ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL(out_RETIRE_COMMIT_UNIT_ACK ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_FRONT_END_ID ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_front_end_id ); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_general_register); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_WRITE_RE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],1 ); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_special_register); +// DELETE2_SIGNAL( in_RETIRE_COMMIT_UNIT_EVENT_STATE ,_param->_nb_rename_unit,_param->_nb_inst_retire[it1],_param->_size_event_state ); + + DELETE2_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_SPR_RENAME_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr ); + DELETE2_SIGNAL(out_SPR_COMMIT_UNIT_SR_OVE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_SPR_SPECIAL_REGISTER_UNIT_SR ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr ); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::end_cycle" +void OOO_Engine_Glue::end_cycle () + { + log_begin(OOO_Engine_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert.cpp (revision 88) @@ -0,0 +1,119 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_insert" + void OOO_Engine_Glue::genMealy_insert (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_function(OOO_Engine_Glue,FUNCTION,_name.c_str()); + + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) + { + Tcontext_t FRONT_END_ID = (_param->_have_port_front_end_id )?_param->_translate_front_end_id_from_rename_unit[i][PORT_READ(in_INSERT_RENAME_UNIT_FRONT_END_ID [i][j])]:0; + Tcontext_t CONTEXT_ID = (_param->_have_port_context_id )?PORT_READ(in_INSERT_RENAME_UNIT_CONTEXT_ID [i][j]):0; + Ttype_t TYPE = PORT_READ(in_INSERT_RENAME_UNIT_TYPE [i][j]); + Toperation_t OPERATION = PORT_READ(in_INSERT_RENAME_UNIT_OPERATION [i][j]); + Tcontrol_t NO_EXECUTE = PORT_READ(in_INSERT_RENAME_UNIT_NO_EXECUTE [i][j]); + Tcontrol_t HAS_IMMEDIAT = PORT_READ(in_INSERT_RENAME_UNIT_HAS_IMMEDIAT [i][j]); + Tgeneral_data_t IMMEDIAT = PORT_READ(in_INSERT_RENAME_UNIT_IMMEDIAT [i][j]); + Tlsq_ptr_t STORE_QUEUE_PTR_WRITE = PORT_READ(in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE [i][j]); + Tlsq_ptr_t LOAD_QUEUE_PTR_WRITE = (_param->_have_port_load_queue_ptr)?PORT_READ(in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE [i][j]):0; + Tcontrol_t READ_RA = PORT_READ(in_INSERT_RENAME_UNIT_READ_RA [i][j]); + Tgeneral_address_t NUM_REG_RA_PHY = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY [i][j]); + Tcontrol_t READ_RB = PORT_READ(in_INSERT_RENAME_UNIT_READ_RB [i][j]); + Tgeneral_address_t NUM_REG_RB_PHY = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY [i][j]); + Tcontrol_t READ_RC = PORT_READ(in_INSERT_RENAME_UNIT_READ_RC [i][j]); + Tspecial_address_t NUM_REG_RC_PHY = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY [i][j]); + Tcontrol_t WRITE_RD = PORT_READ(in_INSERT_RENAME_UNIT_WRITE_RD [i][j]); + Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD [i][j]); + Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW [i][j]); + Tcontrol_t WRITE_RE = PORT_READ(in_INSERT_RENAME_UNIT_WRITE_RE [i][j]); + Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD [i][j]); + Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW [i][j]); + + Tgeneral_address_t general_address_msb = FRONT_END_ID << _param->_size_general_register; + Tspecial_address_t special_address_msb = FRONT_END_ID << _param->_size_special_register; + + PORT_WRITE(out_INSERT_RD_USE [x] ,WRITE_RD); + PORT_WRITE(out_INSERT_RD_NUM_REG [x] ,general_address_msb | NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_INSERT_RE_USE [x] ,WRITE_RE); + PORT_WRITE(out_INSERT_RE_NUM_REG [x] ,special_address_msb | NUM_REG_RE_PHY_NEW); + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_INSERT_COMMIT_UNIT_FRONT_END_ID [i][j],FRONT_END_ID ); + if (_param->_have_port_context_id) + PORT_WRITE(out_INSERT_COMMIT_UNIT_CONTEXT_ID [i][j],CONTEXT_ID ); +// PORT_WRITE(out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID [i][j],RENAME_UNIT_ID ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_TYPE [i][j],TYPE ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_OPERATION [i][j],OPERATION ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NO_EXECUTE [i][j],NO_EXECUTE ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE [i][j],STORE_QUEUE_PTR_WRITE); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE [i][j],LOAD_QUEUE_PTR_WRITE ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_READ_RA [i][j],READ_RA ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY [i][j],NUM_REG_RA_PHY ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_READ_RB [i][j],READ_RB ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY [i][j],NUM_REG_RB_PHY ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_READ_RC [i][j],READ_RC ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY [i][j],NUM_REG_RC_PHY ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_WRITE_RD [i][j],WRITE_RD ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD [i][j],NUM_REG_RD_PHY_OLD ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW [i][j],NUM_REG_RD_PHY_NEW ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_WRITE_RE [i][j],WRITE_RE ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD [i][j],NUM_REG_RE_PHY_OLD ); + PORT_WRITE(out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW [i][j],NUM_REG_RE_PHY_NEW ); + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_INSERT_ISSUE_QUEUE_FRONT_END_ID [i][j],FRONT_END_ID ); + if (_param->_have_port_context_id) + PORT_WRITE(out_INSERT_ISSUE_QUEUE_CONTEXT_ID [i][j],CONTEXT_ID ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_TYPE [i][j],TYPE ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_OPERATION [i][j],OPERATION ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE [i][j],STORE_QUEUE_PTR_WRITE); + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE [i][j],LOAD_QUEUE_PTR_WRITE ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT [i][j],HAS_IMMEDIAT ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_IMMEDIAT [i][j],IMMEDIAT ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_READ_RA [i][j],READ_RA ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_NUM_REG_RA [i][j],general_address_msb | NUM_REG_RA_PHY); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_READ_RB [i][j],READ_RB ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_NUM_REG_RB [i][j],general_address_msb | NUM_REG_RB_PHY); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_READ_RC [i][j],READ_RC ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_NUM_REG_RC [i][j],special_address_msb | NUM_REG_RC_PHY); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_WRITE_RD [i][j],WRITE_RD ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_NUM_REG_RD [i][j],general_address_msb | NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_WRITE_RE [i][j],WRITE_RE ); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_NUM_REG_RE [i][j],special_address_msb | NUM_REG_RE_PHY_NEW); + + x ++; + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_insert_valack.cpp (revision 88) @@ -0,0 +1,102 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_insert_valack" + void OOO_Engine_Glue::genMealy_insert_valack (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_function(OOO_Engine_Glue,FUNCTION,_name.c_str()); + + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + { + // Transaction must be in-order +// Tcontrol_t previous_transaction = true; + + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; ++j) + { + Tcontrol_t ack = PORT_READ(in_INSERT_ACK [x] ); + Tcontrol_t rename_unit_val = PORT_READ(in_INSERT_RENAME_UNIT_VAL [i][j]); + Tcontrol_t rename_unit_no_execute = PORT_READ(in_INSERT_RENAME_UNIT_NO_EXECUTE [i][j]); + Tcontrol_t commit_unit_ack = PORT_READ(in_INSERT_COMMIT_UNIT_ACK [i][j]); + Tcontrol_t issue_queue_ack = PORT_READ(in_INSERT_ISSUE_QUEUE_ACK [i][j]); + + + + // if not execute -> don't route to issue_queue + + Tcontrol_t val = ( +// previous_transaction and + rename_unit_val and + commit_unit_ack and + (rename_unit_no_execute or + issue_queue_ack)); + Tcontrol_t rename_unit_ack = ( +// previous_transaction and + ack and + commit_unit_ack and + (rename_unit_no_execute or + issue_queue_ack)); + Tcontrol_t commit_unit_val = ( +// previous_transaction and + ack and + rename_unit_val and + (rename_unit_no_execute or + issue_queue_ack)); + Tcontrol_t issue_queue_val = ( +// previous_transaction and + ack and + rename_unit_val and + commit_unit_ack and + not rename_unit_no_execute); + + PORT_WRITE(out_INSERT_VAL [x] ,val ); + PORT_WRITE(out_INSERT_RENAME_UNIT_ACK [i][j],rename_unit_ack); + PORT_WRITE(out_INSERT_COMMIT_UNIT_VAL [i][j],commit_unit_val); + PORT_WRITE(out_INSERT_ISSUE_QUEUE_VAL [i][j],issue_queue_val); + + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * rename_unit [%d].inst_insert[%d] -> %d",i,j,x); +// log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * previous_transaction : %d",previous_transaction ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_val (w) : %d",val ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_ack (r) : %d",ack ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_val (r) : %d",rename_unit_val ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_ack (w) : %d",rename_unit_ack ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_rename_unit_no_execute (r) : %d",rename_unit_no_execute); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_commit_unit_val (w) : %d",commit_unit_val ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_commit_unit_ack (r) : %d",commit_unit_ack ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_issue_queue_val (w) : %d",issue_queue_val ); + log_printf(TRACE,OOO_Engine_Glue,FUNCTION," * insert_issue_queue_ack (r) : %d",issue_queue_ack ); + + +// previous_transaction = VAL and ACK; + x ++; + } + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_rename.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_rename.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_rename.cpp (revision 88) @@ -0,0 +1,41 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_rename" + void OOO_Engine_Glue::genMealy_rename (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_function(OOO_Engine_Glue,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; ++j) + // if have not front_end_id port, this function is not use + PORT_WRITE(out_RENAME_RENAME_UNIT_FRONT_END_ID [i][j],_param->_translate_front_end_id_to_rename_unit [PORT_READ(in_RENAME_FRONT_END_ID [i][j])]); + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire.cpp (revision 88) @@ -0,0 +1,75 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ +/* +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_retire" + void OOO_Engine_Glue::genMealy_retire (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_function(OOO_Engine_Glue,FUNCTION,_name.c_str()); + + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; ++j) + { + Tcontext_t FRONT_END_ID = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_COMMIT_UNIT_FRONT_END_ID [i][j]):0; + Tcontrol_t WRITE_RD = PORT_READ(in_RETIRE_COMMIT_UNIT_WRITE_RD [i][j]); + Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD [i][j]); + Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW [i][j]); + Tcontrol_t WRITE_RE = PORT_READ(in_RETIRE_COMMIT_UNIT_WRITE_RE [i][j]); + Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD [i][j]); + Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW [i][j]); + Tevent_state_t EVENT_STATE = PORT_READ(in_RETIRE_COMMIT_UNIT_EVENT_STATE [i][j]); + + Tgeneral_address_t general_address_msb= FRONT_END_ID << _param->_size_general_register; + Tspecial_address_t special_address_msb= FRONT_END_ID << _param->_size_special_register; + + PORT_WRITE(out_RETIRE_RD_OLD_USE [x],0); + PORT_WRITE(out_RETIRE_RD_OLD_NUM_REG [x],general_address_msb | NUM_REG_RD_PHY_OLD); + PORT_WRITE(out_RETIRE_RD_NEW_USE [x],WRITE_RD); + PORT_WRITE(out_RETIRE_RD_NEW_NUM_REG [x],general_address_msb | NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_RETIRE_RE_OLD_USE [x],0); + PORT_WRITE(out_RETIRE_RE_OLD_NUM_REG [x],special_address_msb | NUM_REG_RE_PHY_OLD); + PORT_WRITE(out_RETIRE_RE_NEW_USE [x],WRITE_RE); + PORT_WRITE(out_RETIRE_RE_NEW_NUM_REG [x],special_address_msb | NUM_REG_RE_PHY_NEW); + + if (_param->_have_port_front_end_id) + PORT_WRITE(out_RETIRE_RENAME_UNIT_FRONT_END_ID [i][j],_param->_translate_front_end_id_to_rename_unit [FRONT_END_ID]); + PORT_WRITE(out_RETIRE_RENAME_UNIT_WRITE_RD [i][j],WRITE_RD ); + PORT_WRITE(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD [i][j],NUM_REG_RD_PHY_OLD); + PORT_WRITE(out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW [i][j],NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_RETIRE_RENAME_UNIT_WRITE_RE [i][j],WRITE_RE ); + PORT_WRITE(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD [i][j],NUM_REG_RE_PHY_OLD); + PORT_WRITE(out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW [i][j],NUM_REG_RE_PHY_NEW); + PORT_WRITE(out_RETIRE_RENAME_UNIT_EVENT_STATE [i][j],EVENT_STATE ); + + x ++; + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +*/ +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire_valack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire_valack.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_retire_valack.cpp (revision 88) @@ -0,0 +1,61 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ +/* +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_retire_valack" + void OOO_Engine_Glue::genMealy_retire_valack (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_function(OOO_Engine_Glue,FUNCTION,_name.c_str()); + + uint32_t x=0; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; ++j) + { + Tcontrol_t ACK = PORT_READ(in_RETIRE_ACK [x] ); + Tcontrol_t RENAME_UNIT_ACK = PORT_READ(in_RETIRE_RENAME_UNIT_ACK [i][j]); + Tcontrol_t COMMIT_UNIT_VAL = PORT_READ(in_RETIRE_COMMIT_UNIT_VAL [i][j]); + + + + Tcontrol_t VAL = (RENAME_UNIT_ACK and + COMMIT_UNIT_VAL ); + Tcontrol_t RENAME_UNIT_VAL = (ACK and + COMMIT_UNIT_VAL ); + Tcontrol_t COMMIT_UNIT_ACK = (ACK and + RENAME_UNIT_ACK ); + + PORT_WRITE(out_RETIRE_VAL [x] , VAL ); + PORT_WRITE(out_RETIRE_RENAME_UNIT_VAL [i][j], RENAME_UNIT_VAL); + PORT_WRITE(out_RETIRE_COMMIT_UNIT_ACK [i][j], COMMIT_UNIT_ACK); + + x ++; + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +*/ +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_spr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_spr.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_genMealy_spr.cpp (revision 88) @@ -0,0 +1,51 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::genMealy_spr" + void OOO_Engine_Glue::genMealy_spr (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + special_register_unit::SR * sr = new special_register_unit::SR (i,j); + + sr->write(PORT_READ(in_SPR_SPECIAL_REGISTER_UNIT_SR [i][j])); + + PORT_WRITE(out_SPR_SR_IEE [i][j],sr->iee); + PORT_WRITE(out_SPR_SR_EPH [i][j],sr->eph); + PORT_WRITE(out_SPR_COMMIT_UNIT_SR_OVE [i][j],sr->ove); + PORT_WRITE(out_SPR_RENAME_UNIT_SR [i][j],sr->read()); + + delete sr; + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::statistics_allocation" + void OOO_Engine_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "OOO_Engine_Glue", + param_statistics); + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::statistics_deallocation" + void OOO_Engine_Glue::statistics_deallocation (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + log_printf(INFO,OOO_Engine_Glue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_transition.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::transition" + void OOO_Engine_Glue::transition (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::vhdl" + void OOO_Engine_Glue::vhdl (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::vhdl_body" + void OOO_Engine_Glue::vhdl_body (Vhdl * & vhdl) + { + log_begin(OOO_Engine_Glue,FUNCTION); + vhdl->set_body (""); + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::vhdl_declaration" + void OOO_Engine_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters.cpp (revision 88) @@ -0,0 +1,139 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h" +#include "Common/include/Max.h" +#include "Common/include/BitManipulation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_rename_unit , + uint32_t * nb_inst_decod , + uint32_t * nb_inst_insert , + uint32_t * nb_inst_retire , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t * link_rename_unit_with_front_end , + std::vector * translate_front_end_id_from_rename_unit, + uint32_t size_packet_id , + uint32_t size_general_register , + uint32_t size_special_register , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + bool is_toplevel ) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_rename_unit = nb_rename_unit ; + _nb_inst_decod = nb_inst_decod ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_retire = nb_inst_retire ; + _link_rename_unit_with_front_end = link_rename_unit_with_front_end ; + _translate_front_end_id_from_rename_unit= translate_front_end_id_from_rename_unit ; + +// _rename_unit_nb_front_end = rename_unit_nb_front_end ; +// _rename_unit_nb_context = rename_unit_nb_context ; +// _rename_unit_size_front_end_id = rename_unit_size_front_end_id ; +// _rename_unit_size_context_id = rename_unit_size_context_id ; + _size_rename_id = log2(_nb_rename_unit) ; + _sum_inst_insert = 0; +// _sum_inst_retire = 0; + + for (uint32_t i=0; i<_nb_rename_unit; ++i) + { + _sum_inst_insert += _nb_inst_insert[i]; +// _sum_inst_retire += _nb_inst_retire[i]; + } + + _translate_front_end_id_to_rename_unit = new uint32_t [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + _translate_front_end_id_to_rename_unit [i]=0; + + uint32_t x = _link_rename_unit_with_front_end [i]; + + for (uint32_t j=0; j<_translate_front_end_id_from_rename_unit [x].size(); ++j) + { + if (_translate_front_end_id_from_rename_unit [x][j] == i) + break; + _translate_front_end_id_to_rename_unit [i]++; + } + } + + _mask_num_general_register = gen_mask(size_general_register); + _mask_num_special_register = gen_mask(size_special_register); + + test(); + + if (is_toplevel) + { + _size_context_id = log2(max(_nb_context,_nb_front_end)); + _size_front_end_id = log2(_nb_front_end) ; + _size_rob_ptr = size_packet_id ; + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_general_register = size_general_register; + _size_special_register = size_special_register; + _size_store_queue_ptr = size_store_queue_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + + copy(); + } + + log_end(OOO_Engine_Glue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "OOO_Engine_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(OOO_Engine_Glue,FUNCTION); +// test(); +// log_end(OOO_Engine_Glue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::~Parameters" + Parameters::~Parameters (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + delete _translate_front_end_id_to_rename_unit; + log_end(OOO_Engine_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::copy" + void Parameters::copy (void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + log_end(OOO_Engine_Glue,FUNCTION); + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + Parameters_test test ("OOO_Engine_Glue"); + + log_end(OOO_Engine_Glue,FUNCTION); + + return test; + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,56 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace ooo_engine_glue { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + XML xml ("ooo_engine_glue"); + + xml.balise_open("ooo_engine_glue"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(OOO_Engine_Glue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine_Glue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters & x) + { + log_begin(OOO_Engine_Glue,FUNCTION); + + output_stream << x.print(0); + + log_end(OOO_Engine_Glue,FUNCTION); + + return output_stream; + }; + +}; // end namespace ooo_engine_glue +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libReexecute_unit.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/Makefile.deps (revision 88) @@ -0,0 +1,45 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Reexecute_unit = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Reexecute_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit + +#-----[ Library ]------------------------------------------ + +Reexecute_unit_LIBRARY = -lReexecute_unit \ + $(Priority_LIBRARY) \ + $(Behavioural_LIBRARY) + +Reexecute_unit_DIR_LIBRARY = -L$(Reexecute_unit_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Reexecute_unit_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ + $(MAKE) --directory=$(Reexecute_unit_DIR) --makefile=Makefile; + +Reexecute_unit_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ + $(MAKE) --directory=$(Reexecute_unit_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Reexecute_unit_LIBRARY) + +DIR_LIBRARY = $(Reexecute_unit_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Reexecute_unit_library + +library_clean : Reexecute_unit_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_1.cfg (revision 88) @@ -0,0 +1,18 @@ +Reexecute_unit +0 0 +1 # size_context_id +0 0 +1 # size_front_end_id +6 6 +1 # size_packet_id +4 4 +1 # size_queue +1 1 +1 # nb_execute_loop +4 4 +1 # nb_inst_execute [0] [nb_execute_loop] +2 2 +1 # nb_inst_commit +2 2 +1 # nb_inst_reexecute +1 1 +1 # nb_execute_loop_select +0 1 +1 # priority +0 1 +1 # load_balancing +5 5 +1 # size_general_register_id +1 1 +1 # size_special_register_id +32 32 +1 # size_general_data +5 5 +1 # size_special_data +2 2 +1 # size_store_queue_ptr +2 2 +1 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-execute_loop_4.cfg (revision 88) @@ -0,0 +1,21 @@ +Reexecute_unit +0 0 +1 # size_context_id +0 0 +1 # size_front_end_id +6 6 +1 # size_packet_id +8 8 +1 # size_queue +4 4 +1 # nb_execute_loop +4 4 +1 # nb_inst_execute [0] [nb_execute_loop] +1 1 +1 # nb_inst_execute [1] [nb_execute_loop] +3 3 +1 # nb_inst_execute [2] [nb_execute_loop] +8 8 +1 # nb_inst_execute [3] [nb_execute_loop] +4 4 +1 # nb_inst_commit +3 3 +1 # nb_inst_reexecute +1 4 +1 # nb_execute_loop_select +0 1 +1 # priority +0 1 +1 # load_balancing +5 5 +1 # size_general_register_id +1 1 +1 # size_special_register_id +32 32 +1 # size_general_data +5 5 +1 # size_special_data +2 2 +1 # size_store_queue_ptr +2 2 +1 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,18 @@ +Reexecute_unit +0 0 +1 # size_context_id +0 0 +1 # size_front_end_id +0 0 +1 # size_packet_id +1 1 +1 # size_queue +1 1 +1 # nb_execute_loop +1 1 +1 # nb_inst_execute [0] [nb_execute_loop] +1 1 +1 # nb_inst_commit +1 1 +1 # nb_inst_reexecute +1 1 +1 # nb_execute_loop_select +0 1 +1 # priority +0 1 +1 # load_balancing +5 5 +1 # size_general_register_id +1 1 +1 # size_special_register_id +32 32 +1 # size_general_data +5 5 +1 # size_special_data +1 1 +1 # size_store_queue_ptr +0 0 +1 # size_load_queue_ptr Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 32 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,126 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/include/test.h" + +#define NB_PARAMS 16 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * size_context_id (uint32_t )\n")); + err (_(" * size_front_end_id (uint32_t )\n")); + err (_(" * size_packet_id (uint32_t )\n")); + err (_(" * size_queue (uint32_t )\n")); + err (_(" * nb_execute_loop (uint32_t )\n")); + err (_(" * nb_inst_execute [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_inst_commit (uint32_t )\n")); + err (_(" * nb_inst_reexecute (uint32_t )\n")); + err (_(" * nb_inst_reexecute_commit (uint32_t )\n")); + err (_(" * nb_execute_loop_select (uint32_t )\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + err (_(" * size_general_register_id (uint32_t )\n")); + err (_(" * size_special_register_id (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); + err (_(" * size_store_queue_ptr (uint32_t )\n")); + err (_(" * size_load_queue_ptr (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + uint32_t _size_context_id = fromString(argv[x++]); + uint32_t _size_front_end_id = fromString(argv[x++]); + uint32_t _size_packet_id = fromString(argv[x++]); + uint32_t _size_queue = fromString(argv[x++]); + uint32_t _nb_execute_loop = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+_nb_execute_loop)) + usage (argc, argv); + + uint32_t * _nb_inst_execute = new uint32_t [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; i++) + _nb_inst_execute [i] = fromString(argv[x++]); + + uint32_t _nb_inst_commit = fromString(argv[x++]); + uint32_t _nb_inst_reexecute = fromString(argv[x++]); + uint32_t _nb_execute_loop_select = fromString(argv[x++]); + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + uint32_t _size_general_register_id = fromString(argv[x++]); + uint32_t _size_special_register_id = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + uint32_t _size_store_queue_ptr = fromString(argv[x++]); + uint32_t _size_load_queue_ptr = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters + ( + _size_context_id , + _size_front_end_id , + _size_packet_id , + _size_queue , + _nb_execute_loop , + _nb_inst_execute , + _nb_inst_commit , + _nb_inst_reexecute , + _nb_execute_loop_select , + _priority , + _load_balancing , + _size_general_register_id, + _size_special_register_id, + _size_general_data , + _size_special_data , + _size_store_queue_ptr , + _size_load_queue_ptr , + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Reexecute_unit : no error"); + else + TEST_KO("Reexecute_unit : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_inst_execute; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,590 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/BitManipulation.h" + +class request_t +{ +public : Tcontext_t context_id ; +public : Tcontext_t front_end_id ; +public : Tpacket_t packet_id ; +public : Tcontrol_t commit_wen ; +public : Tcontrol_t spr_access ; +public : Tcontrol_t spr_wen ; +public : Tcontrol_t spr_ren ; +public : Tcontrol_t reexecute ; +public : Ttype_t type ; +public : Toperation_t operation ; +public : Tgeneral_data_t num_group ; +public : Tgeneral_data_t num_reg ; +public : Tgeneral_data_t address ; +public : Tgeneral_data_t data ; +public : Tcontrol_t write_rd ; +public : Tgeneral_address_t num_reg_rd ; +public : Tspecial_data_t flags ; +public : Texception_t exception ; +public : Tcontrol_t no_sequence ; + +public : void init (morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters * _param, Tpacket_t _packet_id) + { + context_id = range(rand(),_param->_size_context_id ); + front_end_id = range(rand(),_param->_size_front_end_id ); + packet_id = _packet_id; + num_group = (rand()%2)?GROUP_DCACHE:GROUP_POWER_MANAGEMENT; + num_reg = packet_id; + data = range(rand(),_param->_size_general_data ); + num_reg_rd = range(rand(),_param->_size_special_register ); + flags = range(rand(),_param->_size_special_data ); + + switch (rand()%4) + { + case 0 : exception = EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE; break; + case 1 : exception = EXCEPTION_ALU_SPR_ACCESS_MUST_READ ; break; + default : exception = EXCEPTION_NONE; + } + + no_sequence = rand()%2; + + address = (num_group << 11)+num_reg; + + + spr_wen = (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE); + spr_ren = (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_READ ); + spr_access = spr_wen or spr_ren; + + reexecute = spr_ren or (spr_wen and ((num_group == GROUP_DCACHE) and + ((num_reg == SPR_DCBPR) or + (num_reg == SPR_DCBFR) or + (num_reg == SPR_DCBIR) or + (num_reg == SPR_DCBLR)))); + + commit_wen = not reexecute; + + if (not spr_access) + { + write_rd = 0; + type = TYPE_SHIFT; + operation = OPERATION_SHIFT_L_SRA; + } + else + if (spr_ren) + { + write_rd = 1; + type = TYPE_ALU; + operation = OPERATION_ALU_L_OR; + } + else + { + write_rd = 0; + type = TYPE_MEMORY; + switch (num_reg) + { + case SPR_DCBPR : {operation = OPERATION_MEMORY_PREFETCH ; break;} + case SPR_DCBFR : {operation = OPERATION_MEMORY_FLUSH ; break;} + case SPR_DCBIR : {operation = OPERATION_MEMORY_INVALIDATE; break;} + case SPR_DCBLR : {operation = OPERATION_MEMORY_LOCK ; break;} + default : break; + } + } + + } +}; + + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Reexecute_unit * _Reexecute_unit = new Reexecute_unit + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_VAL ," in_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_LOOP_ACK ,"out_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ," in_EXECUTE_LOOP_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ," in_EXECUTE_LOOP_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ," in_EXECUTE_LOOP_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_OPERATION ," in_EXECUTE_LOOP_OPERATION ",Toperation_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_TYPE ," in_EXECUTE_LOOP_TYPE ",Ttype_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_FLAGS ," in_EXECUTE_LOOP_FLAGS ",Tspecial_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ," in_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + ALLOC1_SC_SIGNAL(out_COMMIT_VAL ,"out_COMMIT_VAL ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_ACK ," in_COMMIT_ACK ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_WEN ,"out_COMMIT_WEN ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_CONTEXT_ID ,"out_COMMIT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_FRONT_END_ID ,"out_COMMIT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_PACKET_ID ,"out_COMMIT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_commit); +//ALLOC1_SC_SIGNAL(out_COMMIT_OPERATION ,"out_COMMIT_OPERATION ",Toperation_t ,_param->_nb_inst_commit); +//ALLOC1_SC_SIGNAL(out_COMMIT_TYPE ,"out_COMMIT_TYPE ",Ttype_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_FLAGS ,"out_COMMIT_FLAGS ",Tspecial_data_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_EXCEPTION ,"out_COMMIT_EXCEPTION ",Texception_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_NO_SEQUENCE ,"out_COMMIT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL(out_COMMIT_ADDRESS ,"out_COMMIT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_NUM_REG_RD ," in_COMMIT_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_commit); + + ALLOC1_SC_SIGNAL(out_SPR_VAL ,"out_SPR_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACK ," in_SPR_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_WEN ,"out_SPR_WEN ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_CONTEXT_ID ,"out_SPR_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_FRONT_END_ID ,"out_SPR_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_NUM_GROUP ,"out_SPR_NUM_GROUP ",Tspr_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_NUM_REG ,"out_SPR_NUM_REG ",Tspr_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_WDATA ,"out_SPR_WDATA ",Tspr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_RDATA ," in_SPR_RDATA ",Tspr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_INVALID ," in_SPR_INVALID ",Tcontrol_t ,_param->_nb_inst_reexecute); + + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_VAL ," in_REEXECUTE_ROB_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_ROB_ACK ,"out_REEXECUTE_ROB_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_CONTEXT_ID ," in_REEXECUTE_ROB_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_FRONT_END_ID ," in_REEXECUTE_ROB_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_PACKET_ID ," in_REEXECUTE_ROB_PACKET_ID ",Tpacket_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_OPERATION ," in_REEXECUTE_ROB_OPERATION ",Toperation_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_TYPE ," in_REEXECUTE_ROB_TYPE ",Ttype_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ," in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + + ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL ,"out_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_REEXECUTE_ACK ," in_REEXECUTE_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_CONTEXT_ID ,"out_REEXECUTE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_FRONT_END_ID ,"out_REEXECUTE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_PACKET_ID ,"out_REEXECUTE_PACKET_ID ",Tpacket_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_OPERATION ,"out_REEXECUTE_OPERATION ",Toperation_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_TYPE ,"out_REEXECUTE_TYPE ",Ttype_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE ,"out_REEXECUTE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT ,"out_REEXECUTE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_IMMEDIAT ,"out_REEXECUTE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_READ_RA ,"out_REEXECUTE_READ_RA ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RA ,"out_REEXECUTE_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_READ_RB ,"out_REEXECUTE_READ_RB ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RB ,"out_REEXECUTE_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_READ_RC ,"out_REEXECUTE_READ_RC ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RC ,"out_REEXECUTE_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_WRITE_RD ,"out_REEXECUTE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RD ,"out_REEXECUTE_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_WRITE_RE ,"out_REEXECUTE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RE ,"out_REEXECUTE_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_reexecute); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Reexecute_unit.\n"),name.c_str()); + + (*(_Reexecute_unit->in_CLOCK)) (*(in_CLOCK)); + (*(_Reexecute_unit->in_NRESET)) (*(in_NRESET)); + + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit,out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_rob_ptr ) + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_Reexecute_unit, in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_VAL ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_COMMIT_ACK ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_WEN ,_param->_nb_inst_commit); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_PACKET_ID ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_OPERATION ,_param->_nb_inst_commit); +//INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_TYPE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_FLAGS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_EXCEPTION ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_COMMIT_ADDRESS ,_param->_nb_inst_commit); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); + + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_SPR_ACK ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_WEN ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_CONTEXT_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_FRONT_END_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_NUM_GROUP ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_NUM_REG ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_SPR_WDATA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_SPR_RDATA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_SPR_INVALID ,_param->_nb_inst_reexecute); + + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_ROB_ACK ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_CONTEXT_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_FRONT_END_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_PACKET_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_OPERATION ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_TYPE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit, in_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_rob_ptr ) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_HAS_IMMEDIAT ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_IMMEDIAT ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_READ_RA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_NUM_REG_RA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_READ_RB ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_NUM_REG_RB ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_READ_RC ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_NUM_REG_RC ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_WRITE_RD ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_NUM_REG_RD ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_WRITE_RE ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Reexecute_unit,out_REEXECUTE_NUM_REG_RE ,_param->_nb_inst_reexecute); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const int32_t percent_transaction_execute_loop = 75; + const int32_t percent_transaction_commit = 75; + const int32_t percent_transaction_spr = 75; + const int32_t percent_transaction_reexecute = 75; + + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_size_rob_ptr; + uint32_t nb_request_in = 0; + uint32_t nb_request_out = 0; + + request_t request [nb_request]; + + uint32_t tab_request_in [_param->_nb_execute_loop][_param->_max_nb_inst_execute]; + bool tab_request_out [nb_request]; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + tab_request_in [i][j] = (nb_request_in < nb_request)?(nb_request_in++):nb_request; + for (uint32_t i=0; i_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + { + uint32_t x=tab_request_in [i][j]; + + in_EXECUTE_LOOP_VAL [i][j]->write(((rand()%100)write(request[x].context_id ); + in_EXECUTE_LOOP_FRONT_END_ID [i][j]->write(request[x].front_end_id); + in_EXECUTE_LOOP_PACKET_ID [i][j]->write(x); + //in_EXECUTE_LOOP_OPERATION [i][j]->write(0); + //in_EXECUTE_LOOP_TYPE [i][j]->write(0); + in_EXECUTE_LOOP_FLAGS [i][j]->write(request[x].flags ); + in_EXECUTE_LOOP_EXCEPTION [i][j]->write(request[x].exception ); + in_EXECUTE_LOOP_NO_SEQUENCE [i][j]->write(request[x].no_sequence ); + uint32_t num_group = request[x].num_group; + uint32_t num_reg = request[x].num_reg ; + in_EXECUTE_LOOP_ADDRESS [i][j]->write((num_group << 11) | num_reg); + in_EXECUTE_LOOP_DATA [i][j]->write(request[x].data ); + } + + SC_START(0); + for (uint32_t i=0; i<_param->_nb_inst_commit; ++i) + { + in_COMMIT_ACK [i]->write((rand()%100)_have_port_rob_ptr )?PORT_READ(out_COMMIT_PACKET_ID [i]):0; + in_COMMIT_NUM_REG_RD [i]->write(request[packet].num_reg_rd); + } + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + in_SPR_ACK [i]->write((rand()%100)write(~out_SPR_WDATA [i]->read()); + in_SPR_INVALID [i]->write(0); + } + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + in_REEXECUTE_ACK [i]->write((rand()%100)_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + if (in_EXECUTE_LOOP_VAL [i][j]->read() and out_EXECUTE_LOOP_ACK [i][j]->read()) + { + LABEL("EXECUTE_LOOP [%d][%d] : Transaction accepted",i,j); + + tab_request_in [i][j] = (nb_request_in < nb_request)?(nb_request_in++):nb_request; + } + + for (uint32_t i=0; i<_param->_nb_inst_commit; ++i) + if (out_COMMIT_VAL [i]->read() and in_COMMIT_ACK [i]->read()) + { + LABEL("COMMIT [%d] : Transaction accepted",i); + + Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(out_COMMIT_PACKET_ID [i]):0; + + LABEL(" * packet : %d",packet); + + TEST(bool, tab_request_out [packet], true); + + TEST(Tcontrol_t ,out_COMMIT_WEN [i]->read(),request[packet].commit_wen ); + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_COMMIT_CONTEXT_ID [i]->read(),request[packet].context_id ); + if (_param->_have_port_front_end_id) + TEST(Tcontext_t ,out_COMMIT_FRONT_END_ID [i]->read(),request[packet].front_end_id); +// TEST(Toperation_t ,out_COMMIT_OPERATION [i]->read(),request[packet].operation ); +// TEST(Ttype_t ,out_COMMIT_TYPE [i]->read(),request[packet].type ); + TEST(Tspecial_data_t,out_COMMIT_FLAGS [i]->read(),request[packet].flags ); + TEST(Texception_t ,out_COMMIT_EXCEPTION [i]->read(),request[packet].exception ); + TEST(Tcontrol_t ,out_COMMIT_NO_SEQUENCE [i]->read(),request[packet].no_sequence ); + TEST(Tgeneral_data_t,out_COMMIT_ADDRESS [i]->read(),request[packet].address ); + + tab_request_out [packet] = false; + if (not request[packet].spr_access) + nb_request_out++; + } + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (out_SPR_VAL[i]->read() and in_SPR_ACK[i]->read()) + { + LABEL("SPR [%d] : Transaction accepted",i); + + Tspr_address_t num_reg = out_SPR_NUM_REG [i]->read(); + TEST(Tcontrol_t ,out_SPR_WEN [i]->read(), request[num_reg].spr_wen); + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_SPR_CONTEXT_ID [i]->read(), request[num_reg].context_id); + if (_param->_have_port_front_end_id) + TEST(Tcontext_t ,out_SPR_FRONT_END_ID [i]->read(), request[num_reg].front_end_id); + TEST(Tspr_address_t,out_SPR_NUM_GROUP [i]->read(), request[num_reg].num_group); + TEST(Tspr_t ,out_SPR_WDATA [i]->read(), request[num_reg].data); + + if (request[num_reg].spr_ren) + request[num_reg].data = ~request[num_reg].data; + + if (not request[num_reg].reexecute) + nb_request_out++; + } + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (out_REEXECUTE_VAL[i]->read() and in_REEXECUTE_ACK[i]->read()) + { + LABEL("REEXECUTE [%d] : Transaction accepted",i); + + Tpacket_t packet = (_param->_have_port_rob_ptr )?PORT_READ(out_REEXECUTE_PACKET_ID [i]):0; + + LABEL(" * packet : %d",packet); + TEST(Tcontrol_t ,request [packet].reexecute, true); + + if (_param->_have_port_context_id) + TEST(Tcontext_t ,out_REEXECUTE_CONTEXT_ID [i]->read(), request[packet].context_id ); + if (_param->_have_port_front_end_id) + TEST(Tcontext_t ,out_REEXECUTE_FRONT_END_ID [i]->read(), request[packet].front_end_id); + TEST(Tgeneral_data_t ,out_REEXECUTE_IMMEDIAT [i]->read(), request[packet].data ); + TEST(Tcontrol_t ,out_REEXECUTE_WRITE_RD [i]->read(), request[packet].write_rd ); + TEST(Tgeneral_address_t,out_REEXECUTE_NUM_REG_RD [i]->read(), request[packet].num_reg_rd ); + + TEST(Ttype_t ,out_REEXECUTE_TYPE [i]->read(), request[packet].type ); + TEST(Toperation_t ,out_REEXECUTE_OPERATION [i]->read(), request[packet].operation ); + + TEST(Tcontrol_t ,out_REEXECUTE_HAS_IMMEDIAT [i]->read(), 1); + TEST(Tlsq_ptr_t ,out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i]->read(), 0); + TEST(Tlsq_ptr_t ,out_REEXECUTE_LOAD_QUEUE_PTR_WRITE [i]->read(), 0); + TEST(Tcontrol_t ,out_REEXECUTE_READ_RA [i]->read(), 0); + TEST(Tgeneral_address_t,out_REEXECUTE_NUM_REG_RA [i]->read(), 0); + TEST(Tcontrol_t ,out_REEXECUTE_READ_RB [i]->read(), 0); + TEST(Tgeneral_address_t,out_REEXECUTE_NUM_REG_RB [i]->read(), 0); + TEST(Tcontrol_t ,out_REEXECUTE_READ_RC [i]->read(), 0); + TEST(Tspecial_address_t,out_REEXECUTE_NUM_REG_RC [i]->read(), 0); + TEST(Tcontrol_t ,out_REEXECUTE_WRITE_RE [i]->read(), 0); + TEST(Tspecial_address_t,out_REEXECUTE_NUM_REG_RE [i]->read(), 0); + + nb_request_out++; + } + + SC_START(1); + } + + + TEST(uint32_t, nb_request_in ,nb_request); + TEST(uint32_t, nb_request_out ,nb_request); + +// for (uint32_t i=0; i : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + DELETE1_SC_SIGNAL(out_COMMIT_VAL ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_ACK ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_WEN ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_PACKET_ID ,_param->_nb_inst_commit); +//DELETE1_SC_SIGNAL(out_COMMIT_OPERATION ,_param->_nb_inst_commit); +//DELETE1_SC_SIGNAL(out_COMMIT_TYPE ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_FLAGS ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_EXCEPTION ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL(out_COMMIT_ADDRESS ,_param->_nb_inst_commit); + DELETE1_SC_SIGNAL( in_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit); + + DELETE1_SC_SIGNAL(out_SPR_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_WEN ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_NUM_GROUP ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_NUM_REG ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_WDATA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_RDATA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_INVALID ,_param->_nb_inst_reexecute); + + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_ROB_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_PACKET_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_OPERATION ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_TYPE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + + DELETE1_SC_SIGNAL(out_REEXECUTE_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_REEXECUTE_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_PACKET_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_OPERATION ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_TYPE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_IMMEDIAT ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_READ_RA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_READ_RB ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RB ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_READ_RC ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RC ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_WRITE_RD ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RD ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_WRITE_RE ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_REEXECUTE_NUM_REG_RE ,_param->_nb_inst_reexecute); + } +#endif + + delete _Reexecute_unit; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Reexecute_unit.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Reexecute_unit.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/Reexecute_unit.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Reexecute\_unit} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,11 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} + +A lot of instructions must be reissue in execute loop. +\begin{itemize} +\item Store : each store wait the top of Re Order Buffer. +\item SPR access +\end{itemize} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h (revision 88) @@ -0,0 +1,94 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ +//public : uint32_t _size_context_id ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_packet_id ; + public : uint32_t _size_queue ; + public : uint32_t _nb_execute_loop ; + public : uint32_t * _nb_inst_execute ;//[nb_execute_loop] + public : uint32_t _nb_inst_commit ; + public : uint32_t _nb_inst_reexecute ; + public : uint32_t _nb_execute_loop_select ; + public : Tpriority_t _priority_execute_loop ; + public : Tload_balancing_t _load_balancing ; +//public : uint32_t _size_general_register_id; +//public : uint32_t _size_special_register_id; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; + public : static const Tpriority_t _priority_queue_in = PRIORITY_ROUND_ROBIN; + + public : uint32_t _max_nb_inst_execute ; + public : uint32_t _nb_bank ; + public : uint32_t _size_bank ; + +//public : bool _have_port_context_id ; +//public : bool _have_port_front_end_id ; +//public : bool _have_port_packet_id ; +//public : bool _have_port_load_queue_ptr; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t size_context_id , + uint32_t size_front_end_id , + uint32_t size_packet_id , + uint32_t size_queue , + uint32_t nb_execute_loop , + uint32_t * nb_inst_execute , + uint32_t nb_inst_commit , + uint32_t nb_inst_reexecute , + uint32_t nb_execute_loop_select , + Tpriority_t priority_execute_loop , + Tload_balancing_t load_balancing , + uint32_t size_general_register_id, + uint32_t size_special_register_id, + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + bool is_toplevel=false); + +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters & x); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h (revision 88) @@ -0,0 +1,228 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Reexecute_unit_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Reexecute_unit_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + + class Reexecute_unit +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; + private : counter_t ** _stat_bank_nb_inst; + private : counter_t * _stat_nb_inst_commit; + private : counter_t * _stat_nb_inst_reexecute; + private : counter_t * _stat_nb_spr_access; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_VAL ;//[nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_LOOP_ACK ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_LOOP_CONTEXT_ID ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_LOOP_FRONT_END_ID ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tpacket_t ) *** in_EXECUTE_LOOP_PACKET_ID ;//[nb_execute_loop][nb_inst_execute] +//public : SC_IN (Toperation_t ) *** in_EXECUTE_LOOP_OPERATION ;//[nb_execute_loop][nb_inst_execute] +//public : SC_IN (Ttype_t ) *** in_EXECUTE_LOOP_TYPE ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tspecial_data_t ) *** in_EXECUTE_LOOP_FLAGS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] + + // ~~~~~[ Interface "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_VAL ;//[nb_inst_commit] + public : SC_IN (Tcontrol_t ) ** in_COMMIT_ACK ;//[nb_inst_commit] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_WEN ;//[nb_inst_commit] + public : SC_OUT(Tcontext_t ) ** out_COMMIT_CONTEXT_ID ;//[nb_inst_commit] + public : SC_OUT(Tcontext_t ) ** out_COMMIT_FRONT_END_ID ;//[nb_inst_commit] + public : SC_OUT(Tpacket_t ) ** out_COMMIT_PACKET_ID ;//[nb_inst_commit] +//public : SC_OUT(Toperation_t ) ** out_COMMIT_OPERATION ;//[nb_inst_commit] +//public : SC_OUT(Ttype_t ) ** out_COMMIT_TYPE ;//[nb_inst_commit] + public : SC_OUT(Tspecial_data_t ) ** out_COMMIT_FLAGS ;//[nb_inst_commit] + public : SC_OUT(Texception_t ) ** out_COMMIT_EXCEPTION ;//[nb_inst_commit] + public : SC_OUT(Tcontrol_t ) ** out_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] + public : SC_OUT(Tgeneral_data_t ) ** out_COMMIT_ADDRESS ;//[nb_inst_commit] + public : SC_IN (Tgeneral_address_t ) ** in_COMMIT_NUM_REG_RD ;//[nb_inst_commit] + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_SPR_VAL ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_SPR_ACK ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_SPR_WEN ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_SPR_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_SPR_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tspr_address_t ) ** out_SPR_NUM_GROUP ;//[nb_inst_reexecute] + public : SC_OUT(Tspr_address_t ) ** out_SPR_NUM_REG ;//[nb_inst_reexecute] + public : SC_OUT(Tspr_t ) ** out_SPR_WDATA ;//[nb_inst_reexecute] + public : SC_IN (Tspr_t ) ** in_SPR_RDATA ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_SPR_INVALID ;//[nb_inst_reexecute] + + // ~~~~~[ Interface : "reexecute_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_ROB_VAL ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_ROB_ACK ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_REEXECUTE_ROB_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_REEXECUTE_ROB_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_IN (Tpacket_t ) ** in_REEXECUTE_ROB_PACKET_ID ;//[nb_inst_reexecute] + public : SC_IN (Toperation_t ) ** in_REEXECUTE_ROB_OPERATION ;//[nb_inst_reexecute] + public : SC_IN (Ttype_t ) ** in_REEXECUTE_ROB_TYPE ;//[nb_inst_reexecute] + public : SC_IN (Tlsq_ptr_t ) ** in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_VAL ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_REEXECUTE_ACK ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tcontext_t ) ** out_REEXECUTE_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_OUT(Tpacket_t ) ** out_REEXECUTE_PACKET_ID ;//[nb_inst_reexecute] + public : SC_OUT(Toperation_t ) ** out_REEXECUTE_OPERATION ;//[nb_inst_reexecute] + public : SC_OUT(Ttype_t ) ** out_REEXECUTE_TYPE ;//[nb_inst_reexecute] + public : SC_OUT(Tlsq_ptr_t ) ** out_REEXECUTE_STORE_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] + public : SC_OUT(Tlsq_ptr_t ) ** out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_reexecute] //* + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_HAS_IMMEDIAT ;//[nb_inst_reexecute] + public : SC_OUT(Tgeneral_data_t ) ** out_REEXECUTE_IMMEDIAT ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_READ_RA ;//[nb_inst_reexecute] //* + public : SC_OUT(Tgeneral_address_t ) ** out_REEXECUTE_NUM_REG_RA ;//[nb_inst_reexecute] //* + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_READ_RB ;//[nb_inst_reexecute] //* + public : SC_OUT(Tgeneral_address_t ) ** out_REEXECUTE_NUM_REG_RB ;//[nb_inst_reexecute] //* + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_READ_RC ;//[nb_inst_reexecute] //* + public : SC_OUT(Tspecial_address_t ) ** out_REEXECUTE_NUM_REG_RC ;//[nb_inst_reexecute] //* + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_WRITE_RD ;//[nb_inst_reexecute] + public : SC_OUT(Tgeneral_address_t ) ** out_REEXECUTE_NUM_REG_RD ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_REEXECUTE_WRITE_RE ;//[nb_inst_reexecute] //* + public : SC_OUT(Tspecial_address_t ) ** out_REEXECUTE_NUM_REG_RE ;//[nb_inst_reexecute] //* + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority_execute_loop; + private : generic::priority::Priority * _priority_queue_in ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : std::list * _reexecute_queue ;//[nb_bank] + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : Tcontrol_t * internal_QUEUE_PUSH ;//[nb_bank] + public : uint32_t * internal_QUEUE_NUM_EXECUTE_LOOP ;//[nb_bank] + public : uint32_t * internal_QUEUE_NUM_INST_EXECUTE ;//[nb_bank] + public : uint32_t * internal_QUEUE_NUM_INST_COMMIT ;//[nb_bank] + public : info_t * internal_QUEUE_INFO ;//[nb_bank] + public : Tcontrol_t * internal_SPR_VAL ;//[nb_inst_reexecute] + public : Tcontrol_t * internal_REEXECUTE_ROB_ACK ;//[nb_inst_reexecute] + public : Tcontrol_t * internal_REEXECUTE_VAL ;//[nb_inst_reexecute] +#ifdef STATISTICS + public : Tcontrol_t * internal_COMMIT_VAL ;//[nb_inst_commit] +#endif + +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Reexecute_unit); +#endif + public : Reexecute_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Reexecute_unit (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + private : bool must_reexecute (Tspr_address_t address, info_t & info); + + public : void transition (void); + public : void genMoore (void); + public : void genMealy_reexecute (void); + public : void genMealy_commit (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Types.h (revision 88) @@ -0,0 +1,61 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_reexecute_unit_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + typedef enum + { + STATE_EMPTY , + STATE_SPR_ACCESS, + STATE_REEXECUTE + } state_t; + + typedef struct + { + state_t state ; + Tcontext_t context_id ; + Tcontext_t front_end_id ; + Tpacket_t packet_id ; + Tcontrol_t spr_wen ; + Tcontrol_t reexecute ; + Ttype_t type ; + Toperation_t operation ; + Tgeneral_data_t address ; + Tgeneral_data_t data ; + Tcontrol_t write_rd ; + Tgeneral_address_t num_reg_rd ; + } entry_t; + + typedef struct + { + Tcontrol_t spr_wen ; + Tcontrol_t reexecute ; + Ttype_t type ; + Toperation_t operation ; + Tcontrol_t write_rd ; + } info_t; + + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp (revision 88) @@ -0,0 +1,125 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::Parameters" + Parameters::Parameters (uint32_t size_context_id , + uint32_t size_front_end_id , + uint32_t size_packet_id , + uint32_t size_queue , + uint32_t nb_execute_loop , + uint32_t * nb_inst_execute , + uint32_t nb_inst_commit , + uint32_t nb_inst_reexecute , + uint32_t nb_execute_loop_select , + Tpriority_t priority_execute_loop , + Tload_balancing_t load_balancing , + uint32_t size_general_register_id, + uint32_t size_special_register_id, + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t size_store_queue_ptr , + uint32_t size_load_queue_ptr , + bool is_toplevel) + { + log_begin(Reexecute_unit,FUNCTION); + +// _size_context_id = size_context_id ; +// _size_front_end_id = size_front_end_id ; +// _size_packet_id = size_packet_id ; + _size_queue = size_queue ; + _nb_execute_loop = nb_execute_loop ; + _nb_inst_execute = nb_inst_execute ; + _nb_inst_commit = nb_inst_commit ; + _nb_inst_reexecute = nb_inst_reexecute ; + _nb_execute_loop_select = nb_execute_loop_select ; + _priority_execute_loop = priority_execute_loop ; + _load_balancing = load_balancing ; +// _size_general_register_id = size_general_register_id; +// _size_special_register_id = size_special_register_id; +// _size_general_data = size_general_data ; +// _size_special_data = size_special_data ; +// _size_store_queue_ptr = size_store_queue_ptr ; +// _size_load_queue_ptr = size_load_queue_ptr ; + + _max_nb_inst_execute = max(_nb_inst_execute, _nb_execute_loop); + _nb_bank = _nb_inst_reexecute; + _size_bank = _size_queue / _nb_bank; + +// _have_port_context_id = _size_context_id > 0; +// _have_port_front_end_id = _size_front_end_id > 0; +// _have_port_packet_id = _size_packet_id > 0; +// _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + + test(); + + if (is_toplevel) + { + _size_context_id = size_context_id ; + _size_front_end_id = size_front_end_id ; + _size_rob_ptr = size_packet_id ; + _size_general_register = size_general_register_id; + _size_special_register = size_special_register_id; + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _size_store_queue_ptr = size_store_queue_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + + copy(); + } + + log_end(Reexecute_unit,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Reexecute_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Reexecute_unit,FUNCTION); +// test(); +// log_end(Reexecute_unit,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Reexecute_unit,FUNCTION); + log_end(Reexecute_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::copy" + void Parameters::copy (void) + { + log_begin(Reexecute_unit,FUNCTION); + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,48 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Reexecute_unit,FUNCTION); + + Parameters_test test ("Reexecute_unit"); + + if (_size_queue < _nb_inst_reexecute) + test.error(_("size_queue must be >= nb_inst_reexecute_commit.\n")); + + if (_nb_execute_loop_select > _nb_execute_loop) + test.error(toString(_("nb_execute_loop_select must be <= nb_execute_loop.\n"))); + + if (_size_bank == 1) + test.warning(_("For better performance, the bank's size (size_queue/nb_bank) must be > 1.\n")); + + log_end(Reexecute_unit,FUNCTION); + + return test; + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,56 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Reexecute_unit,FUNCTION); + + XML xml ("reexecute_unit"); + + xml.balise_open("reexecute_unit"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Reexecute_unit,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters & x) + { + log_begin(Reexecute_unit,FUNCTION); + + output_stream << x.print(0); + + log_end(Reexecute_unit,FUNCTION); + + return output_stream; + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit.cpp (revision 88) @@ -0,0 +1,197 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::Reexecute_unit" + Reexecute_unit::Reexecute_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Reexecute_unit,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Reexecute_unit == true + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Constant + for (uint32_t i=0; i<_param->_nb_inst_reexecute; ++i) + { + if (_param->_have_port_load_queue_ptr) + PORT_WRITE(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE [i],0); + PORT_WRITE(out_REEXECUTE_READ_RA [i],0); + PORT_WRITE(out_REEXECUTE_NUM_REG_RA [i],0); + PORT_WRITE(out_REEXECUTE_READ_RB [i],0); + PORT_WRITE(out_REEXECUTE_NUM_REG_RB [i],0); + PORT_WRITE(out_REEXECUTE_READ_RC [i],0); + PORT_WRITE(out_REEXECUTE_NUM_REG_RC [i],0); + PORT_WRITE(out_REEXECUTE_WRITE_RE [i],0); + PORT_WRITE(out_REEXECUTE_NUM_REG_RE [i],0); + } + + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + + SC_METHOD (genMoore); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Method - genMealy_reexecute"),_name.c_str()); + + SC_METHOD (genMealy_reexecute); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + if (_param->_have_port_context_id) + sensitive << (*(in_REEXECUTE_ROB_CONTEXT_ID [i])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_REEXECUTE_ROB_FRONT_END_ID [i])); + if (_param->_have_port_rob_ptr ) + sensitive << (*(in_REEXECUTE_ROB_PACKET_ID [i])); + sensitive << (*(in_REEXECUTE_ROB_OPERATION [i])) + << (*(in_REEXECUTE_ROB_TYPE [i])) + << (*(in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE [i])); + } + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Method - genMealy_commit"),_name.c_str()); + + SC_METHOD (genMealy_commit); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + { + if (_param->_have_port_context_id) + sensitive << (*(in_EXECUTE_LOOP_CONTEXT_ID [i][j])); + if (_param->_have_port_front_end_id) + sensitive << (*(in_EXECUTE_LOOP_FRONT_END_ID [i][j])); + if (_param->_have_port_rob_ptr ) + sensitive << (*(in_EXECUTE_LOOP_PACKET_ID [i][j])); + sensitive << (*(in_EXECUTE_LOOP_VAL [i][j])) +// << (*(in_EXECUTE_LOOP_OPERATION [i][j])) +// << (*(in_EXECUTE_LOOP_TYPE [i][j])) + << (*(in_EXECUTE_LOOP_FLAGS [i][j])) + << (*(in_EXECUTE_LOOP_EXCEPTION [i][j])) + << (*(in_EXECUTE_LOOP_NO_SEQUENCE [i][j])) + << (*(in_EXECUTE_LOOP_ADDRESS [i][j])) + << (*(in_EXECUTE_LOOP_DATA [i][j])); + } + for (uint32_t i=0; i<_param->_nb_inst_commit; ++i) + sensitive << (*(in_COMMIT_ACK [i])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Reexecute_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::~Reexecute_unit" + Reexecute_unit::~Reexecute_unit (void) + { + log_begin(Reexecute_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 88) @@ -0,0 +1,197 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::allocation" + void Reexecute_unit::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Reexecute_unit,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Reexecute_unit" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("execute_loop", IN, EAST, _("Instruction executed from execute_loop"),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL ,VAL,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_VALACK_OUT(out_EXECUTE_LOOP_ACK ,ACK,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_TYPE ,"type" ,Ttype_t ,_param->_size_type ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_FLAGS ,"flags" ,Tspecial_data_t ,_param->_size_special_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + } + + // ~~~~~[ Interface "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("commit",OUT,WEST, _("Instruction executed to Re Order Buffer"),_param->_nb_inst_commit); + + ALLOC1_VALACK_OUT(out_COMMIT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_COMMIT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_COMMIT_WEN ,"wen" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_COMMIT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_COMMIT_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_COMMIT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); +// ALLOC1_SIGNAL_OUT(out_COMMIT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); +// ALLOC1_SIGNAL_OUT(out_COMMIT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_COMMIT_FLAGS ,"flags" ,Tspecial_data_t ,_param->_size_special_data); + ALLOC1_SIGNAL_OUT(out_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_OUT(out_COMMIT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_IN ( in_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t ,_param->_size_general_register); + } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr",OUT,EAST, _("Access to Special Register"), _param->_nb_inst_reexecute); + + ALLOC1_VALACK_OUT(out_SPR_VAL ,VAL); + ALLOC1_VALACK_IN ( in_SPR_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_SPR_WEN ,"wen" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_SPR_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_SPR_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_SPR_NUM_GROUP ,"num_group" ,Tspr_address_t ,_param->_size_special_address_group ); + ALLOC1_SIGNAL_OUT(out_SPR_NUM_REG ,"num_reg" ,Tspr_address_t ,_param->_size_special_address_register); + ALLOC1_SIGNAL_OUT(out_SPR_WDATA ,"wdata" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_IN ( in_SPR_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_IN ( in_SPR_INVALID ,"invalid" ,Tcontrol_t ,1); + } + + // ~~~~~[ Interface : "reexecute_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("reexecute_rob", IN,EAST, _("Instruction reexecuted by the Re Order Buffer (Store head)"), _param->_nb_inst_reexecute); + + ALLOC1_VALACK_IN ( in_REEXECUTE_ROB_VAL ,VAL); + ALLOC1_VALACK_OUT(out_REEXECUTE_ROB_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_TYPE ,"type" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_IN ( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE ,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); + } + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("reexecute",OUT,SOUTH, _("Instruction reexecute, send at the issue_queue"), _param->_nb_inst_reexecute); + + ALLOC1_VALACK_OUT(out_REEXECUTE_VAL ,VAL); + ALLOC1_VALACK_IN ( in_REEXECUTE_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_REEXECUTE_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _reexecute_queue = new std::list [_param->_nb_bank]; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + internal_QUEUE_PUSH = new Tcontrol_t [_param->_nb_bank]; + internal_QUEUE_NUM_EXECUTE_LOOP = new uint32_t [_param->_nb_bank]; + internal_QUEUE_NUM_INST_EXECUTE = new uint32_t [_param->_nb_bank]; + internal_QUEUE_NUM_INST_COMMIT = new uint32_t [_param->_nb_bank]; + internal_QUEUE_INFO = new info_t [_param->_nb_bank]; + internal_SPR_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; + internal_REEXECUTE_ROB_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; + internal_REEXECUTE_VAL = new Tcontrol_t [_param->_nb_inst_reexecute]; +#ifdef STATISTICS + internal_COMMIT_VAL = new Tcontrol_t [_param->_nb_inst_commit]; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority_execute_loop = new generic::priority::Priority (_name+"_priority_execute_loop", + _param->_priority_execute_loop, + _param->_load_balancing , + _param->_nb_execute_loop, + _param->_nb_inst_execute, + _param->_nb_execute_loop_select); + + _priority_queue_in = new generic::priority::Priority (_name+"_priority_queue_in", + _param->_priority_queue_in, + _param->_nb_bank); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_deallocation.cpp (revision 88) @@ -0,0 +1,139 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::deallocation" + void Reexecute_unit::deallocation (void) + { + log_begin(Reexecute_unit,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1); + DELETE2_SIGNAL(out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1); + DELETE2_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_front_end_id); + DELETE2_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_rob_ptr ); +// DELETE2_SIGNAL( in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_operation ); +// DELETE2_SIGNAL( in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_type ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_special_data); + DELETE2_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_exception ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data); + DELETE2_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data); + + DELETE1_SIGNAL(out_COMMIT_VAL ,_param->_nb_inst_commit,1); + DELETE1_SIGNAL( in_COMMIT_ACK ,_param->_nb_inst_commit,1); + DELETE1_SIGNAL(out_COMMIT_WEN ,_param->_nb_inst_commit,1); + DELETE1_SIGNAL(out_COMMIT_CONTEXT_ID ,_param->_nb_inst_commit,_param->_size_context_id ); + DELETE1_SIGNAL(out_COMMIT_FRONT_END_ID ,_param->_nb_inst_commit,_param->_size_front_end_id); + DELETE1_SIGNAL(out_COMMIT_PACKET_ID ,_param->_nb_inst_commit,_param->_size_rob_ptr ); +// DELETE1_SIGNAL(out_COMMIT_OPERATION ,_param->_nb_inst_commit,_param->_size_operation ); +// DELETE1_SIGNAL(out_COMMIT_TYPE ,_param->_nb_inst_commit,_param->_size_type ); + DELETE1_SIGNAL(out_COMMIT_FLAGS ,_param->_nb_inst_commit,_param->_size_special_data); + DELETE1_SIGNAL(out_COMMIT_EXCEPTION ,_param->_nb_inst_commit,_param->_size_exception ); + DELETE1_SIGNAL(out_COMMIT_NO_SEQUENCE ,_param->_nb_inst_commit,1 ); + DELETE1_SIGNAL(out_COMMIT_ADDRESS ,_param->_nb_inst_commit,_param->_size_general_data); + DELETE1_SIGNAL( in_COMMIT_NUM_REG_RD ,_param->_nb_inst_commit,_param->_size_general_register ); + + DELETE1_SIGNAL(out_SPR_VAL , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL( in_SPR_ACK , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL(out_SPR_WEN , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL(out_SPR_CONTEXT_ID , _param->_nb_inst_reexecute,_param->_size_context_id ); + DELETE1_SIGNAL(out_SPR_FRONT_END_ID , _param->_nb_inst_reexecute,_param->_size_front_end_id); + DELETE1_SIGNAL(out_SPR_NUM_GROUP , _param->_nb_inst_reexecute,_param->_size_special_address_group ); + DELETE1_SIGNAL(out_SPR_NUM_REG , _param->_nb_inst_reexecute,_param->_size_special_address_register); + DELETE1_SIGNAL(out_SPR_WDATA , _param->_nb_inst_reexecute,_param->_size_spr); + DELETE1_SIGNAL( in_SPR_RDATA , _param->_nb_inst_reexecute,_param->_size_spr); + DELETE1_SIGNAL( in_SPR_INVALID , _param->_nb_inst_reexecute,1); + + DELETE1_SIGNAL( in_REEXECUTE_ROB_VAL , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL(out_REEXECUTE_ROB_ACK , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL( in_REEXECUTE_ROB_CONTEXT_ID , _param->_nb_inst_reexecute,_param->_size_context_id); + DELETE1_SIGNAL( in_REEXECUTE_ROB_FRONT_END_ID , _param->_nb_inst_reexecute,_param->_size_front_end_id); + DELETE1_SIGNAL( in_REEXECUTE_ROB_PACKET_ID , _param->_nb_inst_reexecute,_param->_size_rob_ptr ); + DELETE1_SIGNAL( in_REEXECUTE_ROB_OPERATION , _param->_nb_inst_reexecute,_param->_size_operation); + DELETE1_SIGNAL( in_REEXECUTE_ROB_TYPE , _param->_nb_inst_reexecute,_param->_size_type); + DELETE1_SIGNAL( in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE , _param->_nb_inst_reexecute,_param->_size_store_queue_ptr); + + DELETE1_SIGNAL(out_REEXECUTE_VAL , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL( in_REEXECUTE_ACK , _param->_nb_inst_reexecute,1); + DELETE1_SIGNAL(out_REEXECUTE_CONTEXT_ID , _param->_nb_inst_reexecute,_param->_size_context_id ); + DELETE1_SIGNAL(out_REEXECUTE_FRONT_END_ID , _param->_nb_inst_reexecute,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_REEXECUTE_PACKET_ID , _param->_nb_inst_reexecute,_param->_size_rob_ptr ); + DELETE1_SIGNAL(out_REEXECUTE_OPERATION , _param->_nb_inst_reexecute,_param->_size_operation ); + DELETE1_SIGNAL(out_REEXECUTE_TYPE , _param->_nb_inst_reexecute,_param->_size_type ); + DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE , _param->_nb_inst_reexecute,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL(out_REEXECUTE_LOAD_QUEUE_PTR_WRITE , _param->_nb_inst_reexecute,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL(out_REEXECUTE_HAS_IMMEDIAT , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_IMMEDIAT , _param->_nb_inst_reexecute,_param->_size_general_data ); + DELETE1_SIGNAL(out_REEXECUTE_READ_RA , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_NUM_REG_RA , _param->_nb_inst_reexecute,_param->_size_general_register ); + DELETE1_SIGNAL(out_REEXECUTE_READ_RB , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_NUM_REG_RB , _param->_nb_inst_reexecute,_param->_size_general_register ); + DELETE1_SIGNAL(out_REEXECUTE_READ_RC , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_NUM_REG_RC , _param->_nb_inst_reexecute,_param->_size_special_register ); + DELETE1_SIGNAL(out_REEXECUTE_WRITE_RD , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_NUM_REG_RD , _param->_nb_inst_reexecute,_param->_size_general_register ); + DELETE1_SIGNAL(out_REEXECUTE_WRITE_RE , _param->_nb_inst_reexecute,1 ); + DELETE1_SIGNAL(out_REEXECUTE_NUM_REG_RE , _param->_nb_inst_reexecute,_param->_size_special_register ); + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (not _reexecute_queue [i].empty() and (_reexecute_queue [i].front()->state == STATE_EMPTY)) + { + entry_t * entry = _reexecute_queue [i].front(); + _reexecute_queue [i].pop_front(); + delete entry; + } + delete [] _reexecute_queue; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_QUEUE_PUSH ; + delete [] internal_QUEUE_NUM_EXECUTE_LOOP; + delete [] internal_QUEUE_NUM_INST_EXECUTE; + delete [] internal_QUEUE_NUM_INST_COMMIT ; + delete [] internal_QUEUE_INFO ; + delete [] internal_SPR_VAL ; + delete [] internal_REEXECUTE_ROB_ACK ; + delete [] internal_REEXECUTE_VAL ; +#ifdef STATISTICS + delete [] internal_COMMIT_VAL ; +#endif + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _priority_execute_loop; + delete _priority_queue_in ; + + delete _component; + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::end_cycle" +void Reexecute_unit::end_cycle () + { + log_begin(Reexecute_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 88) @@ -0,0 +1,140 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::genMealy_commit" + void Reexecute_unit::genMealy_commit (void) + { + log_begin(Reexecute_unit,FUNCTION); + + // Initialisation + Tcontrol_t execute_loop_ack [_param->_nb_execute_loop][_param->_max_nb_inst_execute]; + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + execute_loop_ack [i][j] = false; + + for (uint32_t i=0; i<_param->_nb_bank; i++) + internal_QUEUE_PUSH [i] = 0; + + // execute_loop interface + std::list * select_queue_in = _priority_queue_in ->select(); + std::list::iterator it_queue_in = select_queue_in ->begin(); + + std::list * select_execute_loop = _priority_execute_loop ->select(); + std::list::iterator it_execute_loop= select_execute_loop ->begin(); + + // For each nb_inst + for (uint32_t i=0; i<_param->_nb_inst_commit; ++i) + { + Tcontrol_t commit_val = false; + + // find a executed instruction + for (; + (it_execute_loop!=select_execute_loop->end()) and (commit_val == false); + ++it_execute_loop) + { + // take num_execute_loop and num_inst_execute + uint32_t x = it_execute_loop->grp; + uint32_t y = it_execute_loop->elt; + + // test id instruction is valid + if (PORT_READ(in_EXECUTE_LOOP_VAL [x][y])) + { + // Need spr_acces / reexecute ? + Texception_t exception = PORT_READ(in_EXECUTE_LOOP_EXCEPTION [x][y]); + Tgeneral_data_t address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); + Tcontrol_t spr_access = ((exception == EXCEPTION_ALU_SPR_ACCESS_MUST_READ ) or + (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE)); + if (spr_access) + { + // find a not full bank + bool find = false; + for (; + (it_queue_in!=select_queue_in->end()) and (find == false); + ++it_queue_in) + { + uint32_t num_bank = it_queue_in->grp; + if (_reexecute_queue [num_bank].size() < _param->_size_queue) + { + find = true; + + // this instruction don't need spr access. send at the re order buffer + commit_val = 1; // in_EXECUTE_LOOP_VAL = 1 + execute_loop_ack [x][y] = PORT_READ(in_COMMIT_ACK [i]); + + internal_QUEUE_PUSH [num_bank] = execute_loop_ack [x][y]; // in_EXECUTE_LOOP_VAL = 1 + internal_QUEUE_NUM_EXECUTE_LOOP [num_bank] = x; + internal_QUEUE_NUM_INST_EXECUTE [num_bank] = y; + internal_QUEUE_NUM_INST_COMMIT [num_bank] = i; + internal_QUEUE_INFO [num_bank].spr_wen = (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE); + + // if reexecute, don't commit, just read instruction information (num_reg_rd) + PORT_WRITE(out_COMMIT_WEN [i], not must_reexecute(address & 0xffff, internal_QUEUE_INFO[num_bank])); + } + } + } + else + { + // this instruction don't need spr access. send at the re order buffer + commit_val = 1; // in_EXECUTE_LOOP_VAL = 1 + execute_loop_ack [x][y] = PORT_READ(in_COMMIT_ACK [i]); + + PORT_WRITE(out_COMMIT_WEN [i], 1); + } + + if (commit_val) + { + if (_param->_have_port_context_id) + PORT_WRITE(out_COMMIT_CONTEXT_ID [i], PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y])); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_COMMIT_FRONT_END_ID [i], PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y])); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_COMMIT_PACKET_ID [i], PORT_READ(in_EXECUTE_LOOP_PACKET_ID [x][y])); + //PORT_WRITE(out_COMMIT_OPERATION [i], PORT_READ(in_EXECUTE_LOOP_OPERATION [x][y])); + //PORT_WRITE(out_COMMIT_TYPE [i], PORT_READ(in_EXECUTE_LOOP_TYPE [x][y])); + PORT_WRITE(out_COMMIT_FLAGS [i], PORT_READ(in_EXECUTE_LOOP_FLAGS [x][y])); + PORT_WRITE(out_COMMIT_EXCEPTION [i], exception); + PORT_WRITE(out_COMMIT_NO_SEQUENCE [i], PORT_READ(in_EXECUTE_LOOP_NO_SEQUENCE [x][y])); + PORT_WRITE(out_COMMIT_ADDRESS [i], address); + } + } + } + +#ifdef STATISTICS + internal_COMMIT_VAL [i] = commit_val; +#endif + PORT_WRITE(out_COMMIT_VAL [i], commit_val); + } + + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_nb_inst_execute [i]; ++j) + PORT_WRITE(out_EXECUTE_LOOP_ACK [i][j], execute_loop_ack [i][j]); + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif + + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp (revision 88) @@ -0,0 +1,93 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::genMealy_reexecute" + void Reexecute_unit::genMealy_reexecute (void) + { + log_begin(Reexecute_unit,FUNCTION); + + // =================================================================== + // =====[ REEXECUTE ]================================================= + // =================================================================== + // Between reexecute_rob and rexecute_queue, reexecute_queue is most priotary + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + Tcontrol_t val; + Tcontrol_t ack; + + if (not _reexecute_queue [i].empty() and (_reexecute_queue [i].front()->state == STATE_REEXECUTE)) + { + val = true ; + ack = false; + + entry_t * entry = _reexecute_queue [i].front(); + + if (_param->_have_port_context_id) + PORT_WRITE(out_REEXECUTE_CONTEXT_ID [i],entry->context_id ); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_REEXECUTE_FRONT_END_ID [i],entry->front_end_id ); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_REEXECUTE_PACKET_ID [i],entry->packet_id ); + PORT_WRITE(out_REEXECUTE_OPERATION [i],entry->operation ); + PORT_WRITE(out_REEXECUTE_TYPE [i],entry->type ); + PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i],0); + PORT_WRITE(out_REEXECUTE_HAS_IMMEDIAT [i],1); + PORT_WRITE(out_REEXECUTE_IMMEDIAT [i],entry->data ); + PORT_WRITE(out_REEXECUTE_WRITE_RD [i],entry->write_rd ); + PORT_WRITE(out_REEXECUTE_NUM_REG_RD [i],entry->num_reg_rd ); + } + else + { + val = PORT_READ(in_REEXECUTE_ROB_VAL [i]); + ack = PORT_READ(in_REEXECUTE_ACK [i]); + + if (_param->_have_port_context_id) + PORT_WRITE(out_REEXECUTE_CONTEXT_ID [i], PORT_READ(in_REEXECUTE_ROB_CONTEXT_ID [i])); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_REEXECUTE_FRONT_END_ID [i], PORT_READ(in_REEXECUTE_ROB_FRONT_END_ID [i])); + if (_param->_have_port_rob_ptr ) + PORT_WRITE(out_REEXECUTE_PACKET_ID [i], PORT_READ(in_REEXECUTE_ROB_PACKET_ID [i])); + PORT_WRITE(out_REEXECUTE_OPERATION [i], PORT_READ(in_REEXECUTE_ROB_OPERATION [i])); + PORT_WRITE(out_REEXECUTE_TYPE [i], PORT_READ(in_REEXECUTE_ROB_TYPE [i])); + PORT_WRITE(out_REEXECUTE_STORE_QUEUE_PTR_WRITE [i], PORT_READ(in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE [i])); + PORT_WRITE(out_REEXECUTE_HAS_IMMEDIAT [i], 0); + PORT_WRITE(out_REEXECUTE_IMMEDIAT [i], 0); + PORT_WRITE(out_REEXECUTE_WRITE_RD [i], 0); + PORT_WRITE(out_REEXECUTE_NUM_REG_RD [i], 0); + } + + internal_REEXECUTE_VAL [i] = val; + internal_REEXECUTE_ROB_ACK [i] = ack; + + PORT_WRITE(out_REEXECUTE_VAL [i], internal_REEXECUTE_VAL [i]); + PORT_WRITE(out_REEXECUTE_ROB_ACK [i], internal_REEXECUTE_ROB_ACK [i]); + } + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp (revision 88) @@ -0,0 +1,61 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::genMoore" + void Reexecute_unit::genMoore (void) + { + log_begin(Reexecute_unit,FUNCTION); + + // =================================================================== + // =====[ SPR ]======================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + Tcontrol_t val = (not _reexecute_queue [i].empty() and + (_reexecute_queue [i].front()->state == STATE_SPR_ACCESS)); + + if (val) + { + entry_t * entry = _reexecute_queue [i].front(); + + PORT_WRITE(out_SPR_WEN [i],entry->spr_wen); + if (_param->_have_port_context_id) + PORT_WRITE(out_SPR_CONTEXT_ID [i],entry->context_id); + if (_param->_have_port_front_end_id) + PORT_WRITE(out_SPR_FRONT_END_ID [i],entry->front_end_id); + PORT_WRITE(out_SPR_NUM_GROUP [i],(entry->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group); + PORT_WRITE(out_SPR_NUM_REG [i],(entry->address ) & _param->_mask_spr_num_reg ); + PORT_WRITE(out_SPR_WDATA [i],entry->data); + } + + internal_SPR_VAL [i] = val; + PORT_WRITE(out_SPR_VAL [i], internal_SPR_VAL [i]); + } + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_must_reexecute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_must_reexecute.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_must_reexecute.cpp (revision 88) @@ -0,0 +1,86 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::must_reexecute" + bool Reexecute_unit::must_reexecute (Tspr_address_t address, info_t & info) + { + log_begin(Reexecute_unit,FUNCTION); + + // Test if need reexecute + if (info.spr_wen) + { + // ***** SPR WRITE ***** + + Tspr_address_t num_group = (address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group; + Tspr_address_t num_reg = (address ) & _param->_mask_spr_num_reg ; + + switch (num_group) + { + case GROUP_DCACHE : + { + info.type = TYPE_MEMORY; + info.write_rd = 0; + + switch (num_reg) + { + case SPR_DCBPR : {info.reexecute = true; info.operation = OPERATION_MEMORY_PREFETCH ; break;} + case SPR_DCBFR : {info.reexecute = true; info.operation = OPERATION_MEMORY_FLUSH ; break;} + case SPR_DCBIR : {info.reexecute = true; info.operation = OPERATION_MEMORY_INVALIDATE; break;} +// case SPR_DCBWR : {info.reexecute = true; info.operation = OPERATION_MEMORY_FLUSH ; break;} + case SPR_DCBLR : {info.reexecute = true; info.operation = OPERATION_MEMORY_LOCK ; break;} + default : + { + info.reexecute = false; + break; + } + } + + break; + } + default : + { + info.reexecute = false; + break; + } + } + } + else + { + // ***** SPR READ ***** + info.reexecute = true; + info.type = TYPE_ALU; + info.operation = OPERATION_ALU_L_OR; + info.write_rd = 1; + } + + log_end(Reexecute_unit,FUNCTION); + + return info.reexecute; + } + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif + + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_allocation.cpp (revision 88) @@ -0,0 +1,74 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::statistics_allocation" + void Reexecute_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Reexecute_unit,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Reexecute_unit", + param_statistics); + + _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; + + // bank/queue occupation + { + std::string sum_bank_nb_inst = ""; + for (uint32_t i=0; i<_param->_nb_bank; i++) + { + _stat_bank_nb_inst [i] = _stat->create_variable("bank_nb_inst_"+toString(i)); + + _stat->create_expr_average_by_cycle("average_occupation_bank_"+toString(i), "bank_nb_inst_"+toString(i), "", toString(_("Average instruction by cycle (bank %d)"),i)); + _stat->create_expr_percent ("percent_occupation_bank_"+toString(i), "average_occupation_bank_"+toString(i), toString(_param->_size_bank), toString(_("Percent occupation of bank (bank %d)"),i)); + + if (i == 0) + sum_bank_nb_inst = "bank_nb_inst_"+toString(i); + else + sum_bank_nb_inst = "+ bank_nb_inst_"+toString(i) + " " +sum_bank_nb_inst; + } + + _stat->create_expr_average_by_cycle("average_occupation_bank", sum_bank_nb_inst, "", _("Average instruction by cycle (all bank)")); + _stat->create_expr_percent ("percent_occupation_bank" , "average_occupation_bank", toString(_param->_size_queue), _("Percent occupation of reexecute_queue (all bank)")); + } + + + _stat_nb_inst_reexecute = _stat->create_variable("nb_inst_reexecute"); + _stat_nb_inst_commit = _stat->create_variable("nb_inst_commit"); + _stat_nb_spr_access = _stat->create_variable("nb_spr_access"); + + _stat->create_expr_average_by_cycle("average_inst_commit" , "nb_inst_commit" , "", _("Average instruction commited by cycle")); + _stat->create_expr_average_by_cycle("average_inst_reexecute", "nb_inst_reexecute", "", _("Average instruction reexecuted by cycle")); + _stat->create_expr_average_by_cycle("average_spr_access" , "nb_spr_access" , "", _("Average spr access by cycle")); + + _stat->create_expr_percent ("percent_use_interface_commit" , "average_inst_commit" , toString(_param->_nb_inst_commit ), _("Percent usage of commit interface")); + _stat->create_expr_percent ("percent_use_interface_reexecute" , "average_inst_reexecute", toString(_param->_nb_inst_reexecute), _("Percent usage of reexecute interface")); + _stat->create_expr_percent ("percent_use_interface_spr" , "average_spr_access" , toString(_param->_nb_inst_reexecute), _("Percent usage of spr interface")); + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,40 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::statistics_deallocation" + void Reexecute_unit::statistics_deallocation (void) + { + log_begin(Reexecute_unit,FUNCTION); + + log_printf(INFO,Reexecute_unit,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + delete [] _stat_bank_nb_inst; + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 88) @@ -0,0 +1,151 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::transition" + void Reexecute_unit::transition (void) + { + log_begin(Reexecute_unit,FUNCTION); + + if (PORT_READ(in_NRESET) == 0) + { + _priority_execute_loop->reset(); + _priority_queue_in ->reset(); + + for (uint32_t i=0; i<_param->_nb_bank; i++) + _reexecute_queue [i].clear(); + } + else + { + _priority_execute_loop->transition(); + _priority_queue_in ->transition(); + + // =================================================================== + // =====[ EXECUTE_LOOP / COMMIT ]===================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; ++i) + if (internal_QUEUE_PUSH [i]) + { + entry_t * entry = new entry_t; + _reexecute_queue [i].push_back(entry); + + uint32_t x = internal_QUEUE_NUM_EXECUTE_LOOP [i]; + uint32_t y = internal_QUEUE_NUM_INST_EXECUTE [i]; + uint32_t z = internal_QUEUE_NUM_INST_COMMIT [i]; + + entry->state = STATE_SPR_ACCESS; + entry->context_id = (_param->_have_port_context_id )?PORT_READ(in_EXECUTE_LOOP_CONTEXT_ID [x][y]):0; + entry->front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_EXECUTE_LOOP_FRONT_END_ID [x][y]):0; + entry->packet_id = (_param->_have_port_rob_ptr )?PORT_READ(in_EXECUTE_LOOP_PACKET_ID [x][y]):0; + entry->address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); + entry->data = PORT_READ(in_EXECUTE_LOOP_DATA [x][y]); + entry->num_reg_rd = PORT_READ(in_COMMIT_NUM_REG_RD [z]); + entry->spr_wen = internal_QUEUE_INFO [i].spr_wen ; + entry->reexecute = internal_QUEUE_INFO [i].reexecute; + entry->type = internal_QUEUE_INFO [i].type ; + entry->operation = internal_QUEUE_INFO [i].operation; + entry->write_rd = internal_QUEUE_INFO [i].write_rd ; + } + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_inst_commit; i++) + if (internal_COMMIT_VAL [i] and PORT_READ(in_COMMIT_ACK[i])) + (*_stat_nb_inst_commit) ++; +#endif + + // =================================================================== + // =====[ SPR ]======================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (internal_SPR_VAL [i] and PORT_READ(in_SPR_ACK [i])) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_spr_access) ++; +#endif + entry_t * entry = _reexecute_queue [i].front(); + + if (not entry->spr_wen) + { + entry->data = PORT_READ(in_SPR_RDATA [i]); + entry->write_rd = not PORT_READ(in_SPR_INVALID [i]); + } + + if (entry->reexecute) + entry->state = STATE_REEXECUTE; + else + entry->state = STATE_EMPTY; + } + + // =================================================================== + // =====[ REEXECUTE ]================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (internal_REEXECUTE_VAL [i] and PORT_READ(in_REEXECUTE_ACK [i])) + // test source + if (not internal_REEXECUTE_ROB_ACK [i]) + { +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_inst_reexecute) ++; +#endif + + // invalid entry + _reexecute_queue [i].front()->state = STATE_EMPTY; + } +#ifdef DEBUG_TEST + else + { + if (not PORT_READ(in_REEXECUTE_ROB_VAL [i])) + throw ERRORMORPHEO(FUNCTION,toString(_("in_REEXECUTE_ROB_VAL [%d] must be = 1.\n"),i)); + } +#endif + + // =================================================================== + // =====[ End cycle ]================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_bank; i++) + if (not _reexecute_queue [i].empty() and (_reexecute_queue [i].front()->state == STATE_EMPTY)) + { + entry_t * entry = _reexecute_queue [i].front(); + _reexecute_queue [i].pop_front(); + delete entry; + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*(_stat_bank_nb_inst [i])) += _reexecute_queue [i].size(); +#endif + } + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::vhdl" + void Reexecute_unit::vhdl (void) + { + log_begin(Reexecute_unit,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::vhdl_body" + void Reexecute_unit::vhdl_body (Vhdl * & vhdl) + { + log_begin(Reexecute_unit,FUNCTION); + vhdl->set_body (""); + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace reexecute_unit { + + +#undef FUNCTION +#define FUNCTION "Reexecute_unit::vhdl_declaration" + void Reexecute_unit::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Reexecute_unit,FUNCTION); + log_end(Reexecute_unit,FUNCTION); + }; + +}; // end namespace reexecute_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Load_Store_pointer_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/main.cpp (revision 88) @@ -51,5 +51,5 @@ } - uint32_t _nb_load_store_queue = atoi(argv[x++]); + uint32_t _nb_load_store_queue = fromString(argv[x++]); if (argc != static_cast(2+NB_PARAMS+_nb_front_end+2*_nb_load_store_queue+nb_thread)) @@ -86,5 +86,7 @@ _link_load_store_unit_with_thread, _nb_inst_insert , - _nb_inst_retire ); + _nb_inst_retire , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/SelfTest/src/test.cpp (revision 88) @@ -50,4 +50,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Load_Store_pointer_unit * _Load_Store_pointer_unit = new Load_Store_pointer_unit (name.c_str(), @@ -56,5 +66,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -79,6 +89,8 @@ ALLOC1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ," in_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ," in_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); - ALLOC1_SC_SIGNAL( in_RETIRE_TYPE ," in_RETIRE_TYPE ",Ttype_t ,_param->_nb_inst_retire); - ALLOC1_SC_SIGNAL( in_RETIRE_OPERATION ," in_RETIRE_OPERATION ",Toperation_t,_param->_nb_inst_retire); +// ALLOC1_SC_SIGNAL( in_RETIRE_TYPE ," in_RETIRE_TYPE ",Ttype_t ,_param->_nb_inst_retire); +// ALLOC1_SC_SIGNAL( in_RETIRE_OPERATION ," in_RETIRE_OPERATION ",Toperation_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_USE_STORE_QUEUE ," in_RETIRE_USE_STORE_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ," in_RETIRE_USE_LOAD_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE," in_RETIRE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ," in_RETIRE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_retire); @@ -111,6 +123,8 @@ if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_TYPE ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_OPERATION ,_param->_nb_inst_retire); +// INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_TYPE ,_param->_nb_inst_retire); +// INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_OPERATION ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Load_Store_pointer_unit, in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire); if (_param->_have_port_load_queue_ptr) @@ -197,6 +211,8 @@ in_RETIRE_FRONT_END_ID [i]->write(it->_front_end_id ); in_RETIRE_CONTEXT_ID [i]->write(it->_context_id ); - in_RETIRE_TYPE [i]->write(it->_type ); - in_RETIRE_OPERATION [i]->write(it->_operation ); +// in_RETIRE_TYPE [i]->write(it->_type ); +// in_RETIRE_OPERATION [i]->write(it->_operation ); + in_RETIRE_USE_STORE_QUEUE [i]->write((it->_type == TYPE_MEMORY) and is_operation_memory_store(it->_operation)); + in_RETIRE_USE_LOAD_QUEUE [i]->write((it->_type == TYPE_MEMORY) and not is_operation_memory_store(it->_operation)); in_RETIRE_STORE_QUEUE_PTR_WRITE [i]->write(it->_store_queue_ptr_write); in_RETIRE_LOAD_QUEUE_PTR_WRITE [i]->write(it->_load_queue_ptr_write ); @@ -214,5 +230,6 @@ if (in_RETIRE_VAL[i]->read()) { - if (in_RETIRE_TYPE [i]->read() != TYPE_MEMORY) + if (not (in_RETIRE_USE_STORE_QUEUE [i]->read() or + in_RETIRE_USE_LOAD_QUEUE [i]->read())) TEST(Tcontrol_t, out_RETIRE_ACK[i]->read(),true); @@ -366,6 +383,8 @@ delete [] in_RETIRE_FRONT_END_ID ; delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_TYPE ; - delete [] in_RETIRE_OPERATION ; +// delete [] in_RETIRE_TYPE ; +// delete [] in_RETIRE_OPERATION ; + delete [] in_RETIRE_USE_STORE_QUEUE ; + delete [] in_RETIRE_USE_LOAD_QUEUE ; delete [] in_RETIRE_STORE_QUEUE_PTR_WRITE; delete [] in_RETIRE_LOAD_QUEUE_PTR_WRITE ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h (revision 88) @@ -77,6 +77,8 @@ public : SC_IN (Tcontext_t ) ** in_RETIRE_FRONT_END_ID ; // [nb_inst_retire] public : SC_IN (Tcontext_t ) ** in_RETIRE_CONTEXT_ID ; // [nb_inst_retire] - public : SC_IN (Ttype_t ) ** in_RETIRE_TYPE ; // [nb_inst_retire] - public : SC_IN (Toperation_t ) ** in_RETIRE_OPERATION ; // [nb_inst_retire] +//public : SC_IN (Ttype_t ) ** in_RETIRE_TYPE ; // [nb_inst_retire] +//public : SC_IN (Toperation_t ) ** in_RETIRE_OPERATION ; // [nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_USE_STORE_QUEUE ; // [nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_USE_LOAD_QUEUE ; // [nb_inst_retire] public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_STORE_QUEUE_PTR_WRITE; // [nb_inst_retire] public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_LOAD_QUEUE_PTR_WRITE ; // [nb_inst_retire] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Parameters.h (revision 88) @@ -33,16 +33,18 @@ public : uint32_t _nb_inst_retire ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_context_id ; - public : uint32_t _size_store_queue_ptr ; - public : uint32_t _size_load_queue_ptr ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; - public : uint32_t _have_port_front_end_id ; - public : uint32_t _have_port_context_id ; - public : uint32_t _have_port_load_queue_ptr ; +//public : uint32_t _have_port_front_end_id ; +//public : uint32_t _have_port_context_id ; +//public : uint32_t _have_port_load_queue_ptr ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_front_end , uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , uint32_t nb_load_store_queue , uint32_t * size_store_queue , @@ -50,8 +52,12 @@ uint32_t ** link_load_store_unit_with_thread, uint32_t nb_inst_insert , - uint32_t nb_inst_retire ); + uint32_t nb_inst_retire , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); +#if DEBUG_Load_Store_pointer_unit == true + log_printf(INFO,Load_Store_pointer_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Method - transition"); @@ -141,6 +147,8 @@ sensitive << (*(in_RETIRE_LOAD_QUEUE_PTR_WRITE [i])); sensitive << (*(in_RETIRE_VAL [i])) - << (*(in_RETIRE_TYPE [i])) - << (*(in_RETIRE_OPERATION [i])) +// << (*(in_RETIRE_TYPE [i])) +// << (*(in_RETIRE_OPERATION [i])) + << (*(in_RETIRE_USE_STORE_QUEUE [i])) + << (*(in_RETIRE_USE_LOAD_QUEUE [i])) << (*(in_RETIRE_STORE_QUEUE_PTR_WRITE [i]));; } @@ -155,6 +163,8 @@ if (_param->_have_port_context_id) (*(out_RETIRE_ACK [i])) (*( in_RETIRE_CONTEXT_ID [i])); - (*(out_RETIRE_ACK [i])) (*( in_RETIRE_TYPE [i])); - (*(out_RETIRE_ACK [i])) (*( in_RETIRE_OPERATION [i])); +// (*(out_RETIRE_ACK [i])) (*( in_RETIRE_TYPE [i])); +// (*(out_RETIRE_ACK [i])) (*( in_RETIRE_OPERATION [i])); + (*(out_RETIRE_ACK [i])) (*( in_RETIRE_USE_STORE_QUEUE [i])); + (*(out_RETIRE_ACK [i])) (*( in_RETIRE_USE_LOAD_QUEUE [i])); if (_param->_have_port_load_queue_ptr) (*(out_RETIRE_ACK [i])) (*( in_RETIRE_LOAD_QUEUE_PTR_WRITE [i])); @@ -175,5 +185,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Load_Store_pointer_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 88) @@ -78,11 +78,14 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); - ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); - ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION ,"operation" ,Toperation_t,_param->_size_operation ); +// ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); +// ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION ,"operation" ,Toperation_t,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,_param->_size_operation ); ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { reg_STORE_QUEUE_PTR_WRITE = new Tlsq_ptr_t [_param->_nb_load_store_queue]; reg_STORE_QUEUE_USE = new bool * [_param->_nb_load_store_queue]; @@ -106,7 +109,10 @@ internal_RETIRE_LSQ = new uint32_t [_param->_nb_inst_retire]; internal_RETIRE_PTR = new Tlsq_ptr_t [_param->_nb_inst_retire]; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -48,25 +48,26 @@ if (_param->_have_port_context_id) delete [] in_RETIRE_CONTEXT_ID ; - delete [] in_RETIRE_TYPE ; - delete [] in_RETIRE_OPERATION ; +// delete [] in_RETIRE_TYPE ; +// delete [] in_RETIRE_OPERATION ; + delete [] in_RETIRE_USE_STORE_QUEUE ; + delete [] in_RETIRE_USE_LOAD_QUEUE ; delete [] in_RETIRE_STORE_QUEUE_PTR_WRITE; if (_param->_have_port_load_queue_ptr) delete [] in_RETIRE_LOAD_QUEUE_PTR_WRITE ; + delete [] reg_STORE_QUEUE_PTR_WRITE ; + delete [] reg_STORE_QUEUE_USE ; + delete [] reg_STORE_QUEUE_NB_USE ; + delete [] reg_LOAD_QUEUE_PTR_WRITE ; + delete [] reg_LOAD_QUEUE_USE ; + delete [] internal_INSERT_ACK ; + delete [] internal_INSERT_OPERATION_USE; + delete [] internal_INSERT_LSQ ; + delete [] internal_INSERT_PTR ; + delete [] internal_RETIRE_ACK ; + delete [] internal_RETIRE_OPERATION_USE; + delete [] internal_RETIRE_LSQ ; + delete [] internal_RETIRE_PTR ; } - - delete [] reg_STORE_QUEUE_PTR_WRITE ; - delete [] reg_STORE_QUEUE_USE ; - delete [] reg_STORE_QUEUE_NB_USE ; - delete [] reg_LOAD_QUEUE_PTR_WRITE ; - delete [] reg_LOAD_QUEUE_USE ; - delete [] internal_INSERT_ACK ; - delete [] internal_INSERT_OPERATION_USE; - delete [] internal_INSERT_LSQ ; - delete [] internal_INSERT_PTR ; - delete [] internal_RETIRE_ACK ; - delete [] internal_RETIRE_OPERATION_USE; - delete [] internal_RETIRE_LSQ ; - delete [] internal_RETIRE_PTR ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_retire.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_genMealy_retire.cpp (revision 88) @@ -31,7 +31,8 @@ { Tcontrol_t ack = false; - - if ( (PORT_READ(in_RETIRE_VAL [i]) == true ) and - (PORT_READ(in_RETIRE_TYPE [i]) == TYPE_MEMORY)) + Tcontrol_t use_sq = PORT_READ(in_RETIRE_USE_STORE_QUEUE [i]); + Tcontrol_t use_lq = PORT_READ(in_RETIRE_USE_LOAD_QUEUE [i]); + if ( (PORT_READ(in_RETIRE_VAL [i]) == true) and (use_sq or use_lq)) +// (PORT_READ(in_RETIRE_TYPE [i]) == TYPE_MEMORY)) { Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; @@ -49,5 +50,6 @@ // operation became of decod_stage. Also operation is != store_head_ok and store_head_ko - if (is_operation_memory_store(PORT_READ(in_RETIRE_OPERATION [i]))) +// if (is_operation_memory_store(PORT_READ(in_RETIRE_OPERATION [i]))) + if (use_sq) { internal_RETIRE_OPERATION_USE [i] = OPERATION_USE_STORE_QUEUE; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters.cpp (revision 88) @@ -22,4 +22,6 @@ Parameters::Parameters (uint32_t nb_front_end , uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , uint32_t nb_load_store_queue , uint32_t * size_store_queue , @@ -27,5 +29,7 @@ uint32_t ** link_load_store_unit_with_thread, uint32_t nb_inst_insert , - uint32_t nb_inst_retire ) + uint32_t nb_inst_retire , + bool is_toplevel + ) { log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); @@ -40,17 +44,20 @@ _nb_inst_retire = nb_inst_retire ; - uint32_t max_nb_context = max(nb_context, nb_front_end); - uint32_t max_size_store_queue = max(size_store_queue, nb_load_store_queue); - uint32_t max_size_load_queue = max(size_load_queue, nb_load_store_queue); + test(); - _size_front_end_id = log2(nb_front_end ); - _size_context_id = log2(max_nb_context ); - _size_store_queue_ptr = log2(max_size_store_queue); - _size_load_queue_ptr = log2(max_size_load_queue ); - _have_port_front_end_id = (_size_front_end_id > 0); - _have_port_context_id = (_size_context_id > 0); - _have_port_load_queue_ptr = (_size_load_queue_ptr > 0); + if (is_toplevel) + { + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(max(_nb_context,_nb_front_end)); + _size_store_queue_ptr = log2(max(size_store_queue, nb_load_store_queue)); + _size_load_queue_ptr = log2(max(size_load_queue, nb_load_store_queue)); + + _have_port_front_end_id = (_size_front_end_id > 0); + _have_port_context_id = (_size_context_id > 0); + _have_port_load_queue_ptr = (_size_load_queue_ptr > 0); - test(); + copy(); + } + log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End"); }; @@ -67,5 +74,13 @@ #undef FUNCTION #define FUNCTION "Load_Store_pointer_unit::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); + log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Load_Store_pointer_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Parameters_msg_error.cpp (revision 88) @@ -49,7 +49,7 @@ test.error(toString(_("The load store unit [%d] is not linked with a thread.\n"),i)); + log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End"); + return test; - - log_printf(FUNC,Load_Store_pointer_unit,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libRename_unit.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Makefile.deps (revision 88) @@ -0,0 +1,69 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Rename_unit = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif +ifndef Load_Store_pointer_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/Makefile.deps +endif +ifndef Register_translation_unit +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Makefile.deps +endif +ifndef Rename_select +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/Makefile.deps +endif +ifndef Rename_unit_Glue +include $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.deps +endif + + +#-----[ Directory ]---------------------------------------- + +Rename_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit + +#-----[ Library ]------------------------------------------ + + + +Rename_unit_LIBRARY = -lRename_unit \ + $(Load_Store_pointer_unit_LIBRARY) \ + $(Register_translation_unit_LIBRARY) \ + $(Rename_select_LIBRARY) \ + $(Rename_unit_Glue_LIBRARY) \ + $(Behavioural_LIBRARY) + +Rename_unit_DIR_LIBRARY = -L$(Rename_unit_DIR)/lib \ + $(Load_Store_pointer_unit_DIR_LIBRARY) \ + $(Register_translation_unit_DIR_LIBRARY) \ + $(Rename_select_DIR_LIBRARY) \ + $(Rename_unit_Glue_DIR_LIBRARY) \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Rename_unit_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) Load_Store_pointer_unit_library; \ + $(MAKE) Register_translation_unit_library; \ + $(MAKE) Rename_select_library; \ + $(MAKE) Rename_unit_Glue_library; \ + $(MAKE) --directory=$(Rename_unit_DIR) --makefile=Makefile; + +Rename_unit_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) Load_Store_pointer_unit_library_clean; \ + $(MAKE) Register_translation_unit_library_clean;\ + $(MAKE) Rename_select_library_clean; \ + $(MAKE) Rename_unit_Glue_library_clean; \ + $(MAKE) --directory=$(Rename_unit_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Dependency_checking_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/main.cpp (revision 88) @@ -48,5 +48,7 @@ _nb_general_register, _nb_special_register, - _nb_inst_insert ); + _nb_inst_insert , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/SelfTest/src/test.cpp (revision 88) @@ -24,4 +24,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Dependency_checking_unit * _Dependency_checking_unit = new Dependency_checking_unit (name.c_str(), @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/include/Parameters.h (revision 88) @@ -31,11 +31,11 @@ public : uint32_t _nb_inst_insert ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_context_id ; - public : uint32_t _size_general_register ; - public : uint32_t _size_special_register ; - - public : uint32_t _have_port_context_id ; - public : uint32_t _have_port_front_end_id; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; + +//public : uint32_t _have_port_context_id ; +//public : uint32_t _have_port_front_end_id; //-----[ methods ]----------------------------------------------------------- @@ -44,9 +44,13 @@ uint32_t nb_general_register , uint32_t nb_special_register , - uint32_t nb_inst_insert ); + uint32_t nb_inst_insert , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; public : Parameters_test msg_error (void); + + public : void copy (void); public : std::string print (uint32_t depth); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); +#if DEBUG_Dependency_checking_unit == true + log_printf(INFO,Dependency_checking_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Dependency_checking_unit,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Dependency_checking_unit,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { # if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -86,5 +92,5 @@ SC_METHOD (genMealy); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register for (uint32_t i=0;i<_param->_nb_inst_insert; i++) { @@ -221,5 +227,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Dependency_checking_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_allocation.cpp (revision 88) @@ -113,5 +113,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Dependency_checking_unit_genMealy.cpp (revision 88) @@ -23,5 +23,6 @@ void Dependency_checking_unit::genMealy (void) { - log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); + log_begin(Dependency_checking_unit,FUNCTION); + log_function(Dependency_checking_unit,FUNCTION,_name.c_str()); // Tcontrol_t val [_param->_nb_inst_insert]; @@ -77,4 +78,26 @@ num_reg_re_phy_new [i] = PORT_READ(in_RENAME_IN_NUM_REG_RE_PHY_NEW [i]); + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (before) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d", + i, + front_end_id [i], + context_id [i], + read_ra [i], + num_reg_ra_log [i], + num_reg_ra_phy [i], + read_rb [i], + num_reg_rb_log [i], + num_reg_rb_phy [i], + read_rc [i], + num_reg_rc_log [i], + num_reg_rc_phy [i], + write_rd [i], + num_reg_rd_log [i], + num_reg_rd_phy_old [i], + num_reg_rd_phy_new [i], + write_re [i], + num_reg_re_log [i], + num_reg_re_phy_old [i], + num_reg_re_phy_new [i]); + // ================================================================ // =====[ Write after Write ]====================================== @@ -88,4 +111,5 @@ (context_id [j] == context_id [i]) ) { + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RD : WAW dependency with inst[%d].RD",j); num_reg_rd_phy_old [i] = num_reg_rd_phy_new [j]; break; // find the most recently dependency @@ -100,4 +124,5 @@ (context_id [j] == context_id [i]) ) { + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RE : WAW dependency with inst[%d].RE",j); num_reg_re_phy_old [i] = num_reg_re_phy_new [j]; break; // find the most recently dependency @@ -114,4 +139,5 @@ (context_id [j] == context_id [i]) ) { + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RA : RAW dependency with inst[%d].RD",j); num_reg_ra_phy [i] = num_reg_rd_phy_new [j]; break; // find the most recently dependency @@ -126,4 +152,5 @@ (context_id [j] == context_id [i]) ) { + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RB : RAW dependency with inst[%d].RD",j); num_reg_rb_phy [i] = num_reg_rd_phy_new [j]; break; // find the most recently dependency @@ -138,7 +165,30 @@ (context_id [j] == context_id [i]) ) { + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * RC : RAW dependency with inst[%d].RE",j); num_reg_rc_phy [i] = num_reg_re_phy_new [j]; break; // find the most recently dependency } + + log_printf(TRACE,Dependency_checking_unit,FUNCTION," * (after ) [%d] %.2d %.2d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d, %.1d %.2d %.5d -> %.5d, %.1d %.2d %.5d -> %.5d", + i, + front_end_id [i], + context_id [i], + read_ra [i], + num_reg_ra_log [i], + num_reg_ra_phy [i], + read_rb [i], + num_reg_rb_log [i], + num_reg_rb_phy [i], + read_rc [i], + num_reg_rc_log [i], + num_reg_rc_phy [i], + write_rd [i], + num_reg_rd_log [i], + num_reg_rd_phy_old [i], + num_reg_rd_phy_new [i], + write_re [i], + num_reg_re_log [i], + num_reg_re_phy_old [i], + num_reg_re_phy_new [i]); // =====[ Output ]================================================= @@ -168,5 +218,5 @@ } - log_printf(FUNC,Dependency_checking_unit,FUNCTION,"End"); + log_end(Dependency_checking_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit/src/Parameters.cpp (revision 88) @@ -24,5 +24,6 @@ uint32_t nb_general_register , uint32_t nb_special_register , - uint32_t nb_inst_insert ) + uint32_t nb_inst_insert , + bool is_toplevel ) { log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); @@ -34,13 +35,19 @@ _nb_inst_insert = nb_inst_insert ; - _size_front_end_id = log2(nb_front_end ); - _size_context_id = log2(max_nb_context ); - _size_general_register = log2(nb_general_register); - _size_special_register = log2(nb_special_register); - - _have_port_front_end_id = _size_front_end_id>0; - _have_port_context_id = _size_context_id >0; + test(); - test(); + if (is_toplevel) + { + _size_front_end_id = log2(nb_front_end ); + _size_context_id = log2(max_nb_context ); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); + + _have_port_front_end_id = _size_front_end_id>0; + _have_port_context_id = _size_context_id >0; + + copy(); + } + log_printf(FUNC,Dependency_checking_unit,FUNCTION,"End"); }; @@ -57,5 +64,13 @@ #undef FUNCTION #define FUNCTION "Dependency_checking_unit::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); + log_printf(FUNC,Dependency_checking_unit,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Dependency_checking_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Dependency_checking_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Free_List_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/main.cpp (revision 88) @@ -57,5 +57,7 @@ _nb_pop , _nb_push , - _priority ); + _priority , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Free_List_unit * _Free_List_unit = new Free_List_unit (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/include/Parameters.h (revision 88) @@ -34,6 +34,6 @@ public : Tpriority_t _priority ; - public : uint32_t _size_general_register; - public : uint32_t _size_special_register; +//public : uint32_t _size_general_register; +//public : uint32_t _size_special_register; public : uint32_t _nb_bank_by_pop ; @@ -52,9 +52,12 @@ uint32_t nb_pop , uint32_t nb_push , - Tpriority_t priority ); + Tpriority_t priority , + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; public : Parameters_test msg_error (void); + + public : void copy (void); public : std::string print (uint32_t depth); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); +#if DEBUG_Free_List_unit == true + log_printf(INFO,Free_List_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Free_List_unit,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Free_List_unit,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Free_List_unit,FUNCTION,"Method - transition"); @@ -83,5 +89,5 @@ SC_METHOD (genMealy_pop); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register for (uint32_t i=0; i<_param->_nb_pop; i++) sensitive << (*(in_POP_GPR_VAL[i])) @@ -104,5 +110,5 @@ SC_METHOD (genMealy_push_gpr); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register for (uint32_t i=0; i<_param->_nb_push; i++) sensitive << (*(in_PUSH_GPR_VAL [i])) @@ -123,5 +129,5 @@ SC_METHOD (genMealy_push_spr); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register for (uint32_t i=0; i<_param->_nb_push; i++) sensitive << (*(in_PUSH_SPR_VAL [i])) @@ -150,5 +156,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Free_List_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_allocation.cpp (revision 88) @@ -86,5 +86,6 @@ } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { _gpr_list = new std::list [_param->_nb_bank]; _spr_list = new std::list [_param->_nb_bank]; @@ -98,7 +99,10 @@ internal_PUSH_GPR_BANK = new uint32_t [_param->_nb_push]; internal_PUSH_SPR_BANK = new uint32_t [_param->_nb_push]; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -43,17 +43,19 @@ delete [] out_PUSH_SPR_ACK ; delete [] in_PUSH_SPR_NUM_REG; + + delete [] _gpr_list; + delete [] _spr_list; + + delete [] internal_POP_ACK ; + delete [] internal_POP_GPR_BANK; + delete [] internal_POP_SPR_BANK; + + delete [] internal_PUSH_GPR_ACK ; + delete [] internal_PUSH_SPR_ACK ; + delete [] internal_PUSH_GPR_BANK; + delete [] internal_PUSH_SPR_BANK; } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] _gpr_list; - delete [] _spr_list; - - delete [] internal_POP_ACK ; - delete [] internal_POP_GPR_BANK; - delete [] internal_POP_SPR_BANK; - - delete [] internal_PUSH_GPR_ACK ; - delete [] internal_PUSH_SPR_ACK ; - delete [] internal_PUSH_GPR_BANK; - delete [] internal_PUSH_SPR_BANK; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_pop.cpp (revision 88) @@ -23,5 +23,6 @@ void Free_List_unit::genMealy_pop (void) { - log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); + log_begin(Free_List_unit,FUNCTION); + log_function(Free_List_unit,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_pop; i++) @@ -77,5 +78,5 @@ - log_printf(FUNC,Free_List_unit,FUNCTION,"End"); + log_end(Free_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_gpr.cpp (revision 88) @@ -23,5 +23,6 @@ void Free_List_unit::genMealy_push_gpr (void) { - log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); + log_begin(Free_List_unit,FUNCTION); + log_function(Free_List_unit,FUNCTION,_name.c_str()); bool bank_use [_param->_nb_bank]; @@ -51,5 +52,5 @@ } - log_printf(FUNC,Free_List_unit,FUNCTION,"End"); + log_end(Free_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_genMealy_push_spr.cpp (revision 88) @@ -23,5 +23,6 @@ void Free_List_unit::genMealy_push_spr (void) { - log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); + log_begin(Free_List_unit,FUNCTION); + log_function(Free_List_unit,FUNCTION,_name.c_str()); bool bank_use [_param->_nb_bank]; @@ -51,5 +52,5 @@ } - log_printf(FUNC,Free_List_unit,FUNCTION,"End"); + log_end(Free_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Free_List_unit_transition.cpp (revision 88) @@ -23,5 +23,6 @@ void Free_List_unit::transition (void) { - log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); + log_begin(Free_List_unit,FUNCTION); + log_function(Free_List_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -39,8 +40,9 @@ // =====[ POP ]====================================== // ================================================== -// log_printf(TRACE,Free_List_unit,FUNCTION,"Test transaction POP"); for (uint32_t i=0; i<_param->_nb_pop; i++) if (PORT_READ(in_POP_VAL[i]) and internal_POP_ACK [i]) { + log_printf(TRACE,Free_List_unit,FUNCTION," * POP [%d]",i); + if (PORT_READ(in_POP_GPR_VAL [i])) _gpr_list [internal_POP_GPR_BANK[i]].pop_front(); @@ -53,21 +55,54 @@ // =====[ PUSH_GPR ]================================= // ================================================== -// log_printf(TRACE,Free_List_unit,FUNCTION,"Test transaction PUSH_GPR"); for (uint32_t i=0; i<_param->_nb_push; i++) if (PORT_READ(in_PUSH_GPR_VAL[i]) and internal_PUSH_GPR_ACK [i]) - _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(//_param->_mask_gpr & - PORT_READ(in_PUSH_GPR_NUM_REG [i])); + { + log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_GPR[%d]",i); + _gpr_list [internal_PUSH_GPR_BANK[i]].push_back(//_param->_mask_gpr & + PORT_READ(in_PUSH_GPR_NUM_REG [i])); + } // ================================================== // =====[ PUSH_SPR ]================================= // ================================================== -// log_printf(TRACE,Free_List_unit,FUNCTION,"Test transaction PUSH_SPR"); for (uint32_t i=0; i<_param->_nb_push; i++) if (PORT_READ(in_PUSH_SPR_VAL[i]) and internal_PUSH_SPR_ACK [i]) - _spr_list [internal_PUSH_SPR_BANK[i]].push_back(//_param->_mask_spr & - PORT_READ(in_PUSH_SPR_NUM_REG [i])); + { + log_printf(TRACE,Free_List_unit,FUNCTION," * PUSH_SPR[%d]",i); + + _spr_list [internal_PUSH_SPR_BANK[i]].push_back(//_param->_mask_spr & + PORT_READ(in_PUSH_SPR_NUM_REG [i])); + } if (_param->_priority == PRIORITY_ROUND_ROBIN) internal_BANK_PRIORITY = (internal_BANK_PRIORITY+1)%_param->_nb_bank_by_pop; + +#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Free_List_unit == true) + log_printf(TRACE,Free_List_unit,FUNCTION," * Dump Free List"); + + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + uint32_t j=0; + for (std::list::iterator it=_gpr_list->begin(); + it!=_gpr_list->end(); + ++it) + { + log_printf(TRACE,Free_List_unit,FUNCTION," * GPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); + ++j; + } + } + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + uint32_t j=0; + for (std::list::iterator it=_spr_list->begin(); + it!=_spr_list->end(); + ++it) + { + log_printf(TRACE,Free_List_unit,FUNCTION," * SPR_LIST[%.5d][%.5d] : %.5d",i,j,*it); + ++j; + } + } + +#endif } @@ -76,5 +111,5 @@ #endif - log_printf(FUNC,Free_List_unit,FUNCTION,"End"); + log_end(Free_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters.cpp (revision 88) @@ -27,5 +27,6 @@ uint32_t nb_pop , uint32_t nb_push , - Tpriority_t priority ) + Tpriority_t priority , + bool is_toplevel ) { log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); @@ -41,6 +42,6 @@ test(); - _size_general_register = log2(nb_general_register); - _size_special_register = log2(nb_special_register); + uint32_t size_general_register = log2(nb_general_register); + uint32_t size_special_register = log2(nb_special_register); _nb_bank_by_pop = _nb_bank / _nb_pop; @@ -49,5 +50,5 @@ _bank_gpr_nb_slot = gpr_nb_slot/nb_bank; - _bank_gpr_size_slot = _size_general_register-log2(nb_bank); + _bank_gpr_size_slot = size_general_register-log2(nb_bank); _mask_gpr = gen_mask (_bank_gpr_size_slot); @@ -56,7 +57,15 @@ _bank_spr_nb_slot = spr_nb_slot/nb_bank; - _bank_spr_size_slot = _size_special_register-log2(nb_bank); + _bank_spr_size_slot = size_special_register-log2(nb_bank); _mask_spr = gen_mask (_bank_spr_size_slot); + + if (is_toplevel) + { + _size_general_register = size_general_register; + _size_special_register = size_special_register; + + copy(); + } log_printf(FUNC,Free_List_unit,FUNCTION,"End"); @@ -74,5 +83,13 @@ #undef FUNCTION #define FUNCTION "Free_List_unit::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); + log_printf(FUNC,Free_List_unit,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Free_List_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Free_List_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit/src/Parameters_msg_error.cpp (revision 88) @@ -29,11 +29,15 @@ if (_nb_general_register <= _nb_thread*_nb_general_register_logic) - test.error(_("The number of physical general register is insufficient.\n")); + test.error(toString(_("The number of physical general register is insufficient. (Minimum : %d)\n"),_nb_thread*_nb_general_register_logic+1)); if (_nb_special_register <= _nb_thread*_nb_special_register_logic) - test.error(_("The number of physical special register is insufficient.\n")); + test.error(toString(_("The number of physical special register is insufficient. (Minimum : %d)\n"),_nb_thread*_nb_special_register_logic+1)); if (not is_multiple (_nb_bank, _nb_pop)) test.error(_("Number of pop must be a multiple of number of bank.\n")); if (not is_power2 (_nb_bank)) test.error(_("Number of bank must be a power of 2.\n")); + if (_nb_general_register < _nb_bank) + test.error(_("The number of physical general register must be >= nb_bank.\n")); + if (_nb_special_register < _nb_bank) + test.error(_("The number of physical special register must be >= nb_bank.\n")); if ((_priority != PRIORITY_STATIC) and Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Register_Address_Translation_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/main.cpp (revision 88) @@ -60,5 +60,7 @@ _nb_special_register , _nb_inst_insert , - _nb_inst_retire ); + _nb_inst_retire , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/SelfTest/src/test.cpp (revision 88) @@ -24,4 +24,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Register_Address_Translation_unit * _Register_Address_Translation_unit = new Register_Address_Translation_unit (name.c_str(), @@ -30,5 +40,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -78,4 +88,6 @@ ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RD_PHY_OLD,"out_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_RESTORE_RE_PHY_OLD,"out_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); /******************************************************** @@ -131,4 +143,6 @@ INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_Address_Translation_unit,out_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -226,8 +240,14 @@ } + uint32_t retire_max = _param->_nb_inst_retire; for (uint32_t i=0; i<_param->_nb_inst_retire; i++) { - Tcontrol_t val = (rand()%100)_nb_front_end; @@ -259,4 +279,11 @@ } } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + TEST(Tcontrol_t,out_RETIRE_RESTORE_RD_PHY_OLD[i]->read(), 0); + TEST(Tcontrol_t,out_RETIRE_RESTORE_RE_PHY_OLD[i]->read(), 0); + } + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) { @@ -320,4 +347,6 @@ SC_START(1); + // EVENT !!!!!!!! + nb_request = 32; while (nb_request > 1) @@ -347,7 +376,14 @@ } + uint32_t retire_max = _param->_nb_inst_retire; for (uint32_t i=0; i<_param->_nb_inst_retire; i++) { - Tcontrol_t val = (rand()%100)write(val); in_RETIRE_FRONT_END_ID [i]->write(retire_front_end_id [i]); @@ -362,5 +398,5 @@ } - SC_START(1); + SC_START(0); @@ -380,10 +416,21 @@ for (uint32_t i=0; i<_param->_nb_inst_retire; i++) { + LABEL("RETIRE[%d]",i); + Tcontext_t front_end_id = in_RETIRE_FRONT_END_ID [i]->read(); Tcontext_t context_id = in_RETIRE_CONTEXT_ID [i]->read(); + + LABEL(" * front_end_id : %d",front_end_id); + LABEL(" * context_id : %d",context_id ); + if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) { if (in_RETIRE_WRITE_RD [i]->read() == 1) { +// LABEL(" * transaction and write rd"); +// LABEL(" * rd_log : %d",in_RETIRE_NUM_REG_RD_LOG[i]->read()); +// LABEL(" * rat_gpr_updt : %d",rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()]); + TEST(Tcontrol_t,out_RETIRE_RESTORE_RD_PHY_OLD[i]->read(), (rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] == false)); + if (rat_gpr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] == false) rat_gpr[front_end_id][context_id][in_RETIRE_NUM_REG_RD_LOG[i]->read()] = in_RETIRE_NUM_REG_RD_PHY_OLD[i]->read(); @@ -392,4 +439,6 @@ if (in_RETIRE_WRITE_RE [i]->read() == 1) { + TEST(Tcontrol_t,out_RETIRE_RESTORE_RE_PHY_OLD[i]->read(), (rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] == false)); + if (rat_spr_updt [front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] == false) rat_spr[front_end_id][context_id][in_RETIRE_NUM_REG_RE_LOG[i]->read()] = in_RETIRE_NUM_REG_RE_PHY_OLD[i]->read(); @@ -398,4 +447,7 @@ } } + + SC_START(1); + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) { @@ -412,6 +464,6 @@ TEST(Tspecial_address_t,out_RENAME_NUM_REG_RE_PHY_OLD[i]->read(), rat_spr[front_end_id][context_id][in_RENAME_NUM_REG_RE_LOG[i]->read()]); } - - } + } + } } @@ -472,4 +524,6 @@ delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; + delete [] out_RETIRE_RESTORE_RD_PHY_OLD; + delete [] out_RETIRE_RESTORE_RE_PHY_OLD; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Parameters.h (revision 88) @@ -32,11 +32,11 @@ public : uint32_t _nb_inst_retire ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_context_id ; - public : uint32_t _size_general_register ; - public : uint32_t _size_special_register ; - - public : uint32_t _have_port_context_id ; - public : uint32_t _have_port_front_end_id; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +// +//public : uint32_t _have_port_context_id ; +//public : uint32_t _have_port_front_end_id; //-----[ methods ]----------------------------------------------------------- @@ -46,8 +46,11 @@ uint32_t nb_special_register, uint32_t nb_inst_insert , - uint32_t nb_inst_retire + uint32_t nb_inst_retire , + bool is_toplevel=false ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h (revision 88) @@ -103,8 +103,14 @@ public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_PHY_OLD;//[nb_inst_retire] public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_OLD;//[nb_inst_retire] + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tgeneral_address_t *** rat_gpr; //[nb_front_end][nb_context][nb_general_register_logic] + private : bool *** rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] + private : Tspecial_address_t *** rat_spr; //[nb_front_end][nb_context][nb_special_register_logic] + private : bool *** rat_spr_update_table; //[nb_front_end][nb_context][nb_special_register_logic] // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -113,8 +119,6 @@ private : Tcontrol_t * internal_RETIRE_ACK; //[nb_inst_retire] - private : Tgeneral_address_t *** rat_gpr; //[nb_front_end][nb_context][nb_general_register_logic] - private : bool *** rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] - private : Tspecial_address_t *** rat_spr; //[nb_front_end][nb_context][nb_special_register_logic] - private : bool *** rat_spr_update_table; //[nb_front_end][nb_context][nb_special_register_logic] + private : bool *** internal_rat_gpr_update_table; //[nb_front_end][nb_context][nb_general_register_logic] + private : bool *** internal_rat_spr_update_table; //[nb_front_end][nb_context][nb_special_register_logic] #endif @@ -150,5 +154,6 @@ #ifdef SYSTEMC public : void transition (void); - public : void genMoore (void); + public : void genMealy_rename (void); + public : void genMealy_retire (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Parameters.cpp (revision 88) @@ -25,5 +25,6 @@ uint32_t nb_special_register, uint32_t nb_inst_insert , - uint32_t nb_inst_retire ) + uint32_t nb_inst_retire , + bool is_toplevel) { log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); @@ -36,13 +37,18 @@ _nb_inst_retire = nb_inst_retire ; - _size_front_end_id = log2(nb_front_end ); - _size_context_id = log2(max(nb_context, nb_front_end)); - _size_general_register = log2(nb_general_register); - _size_special_register = log2(nb_special_register); + test(); + + if (is_toplevel) + { + _size_front_end_id = log2(nb_front_end ); + _size_context_id = log2(max(nb_context, nb_front_end)); + _size_general_register = log2(nb_general_register); + _size_special_register = log2(nb_special_register); - _have_port_front_end_id = _size_front_end_id>0; - _have_port_context_id = _size_context_id >0; - - test(); + _have_port_front_end_id = _size_front_end_id>0; + _have_port_context_id = _size_context_id >0; + + copy(); + } log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"End"); @@ -60,5 +66,13 @@ #undef FUNCTION #define FUNCTION "Register_Address_Translation_unit::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); + log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Register_Address_Translation_unit::copy" + void Parameters::copy (void) { log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); +#if DEBUG_Register_Address_Translation_unit == true + log_printf(INFO,Register_Address_Translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { // Constant : accepted already transaction @@ -95,9 +101,46 @@ # endif - log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Method - genMoore"); + log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Method - genMealy_rename"); - SC_METHOD (genMoore); + SC_METHOD (genMealy_rename); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + if (_param->_have_port_front_end_id) + sensitive << (*(in_RENAME_FRONT_END_ID [i])); + if (_param->_have_port_context_id ) + sensitive << (*(in_RENAME_CONTEXT_ID [i])); + + sensitive << (*(in_RENAME_NUM_REG_RA_LOG [i])) + << (*(in_RENAME_NUM_REG_RB_LOG [i])) + << (*(in_RENAME_NUM_REG_RC_LOG [i])) + << (*(in_RENAME_NUM_REG_RD_LOG [i])) + << (*(in_RENAME_NUM_REG_RE_LOG [i])); + } + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Method - genMealy_retire"); + + SC_METHOD (genMealy_retire); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + for (uint32_t i=0; i<_param->_nb_inst_retire; ++i) + { + if (param->_have_port_front_end_id) + sensitive << (*(in_RETIRE_FRONT_END_ID [i])); + if (param->_have_port_context_id) + sensitive << (*(in_RETIRE_CONTEXT_ID [i])); + + sensitive << (*(in_RETIRE_EVENT_STATE [i])) + << (*(in_RETIRE_WRITE_RD [i])) + << (*(in_RETIRE_WRITE_RE [i])) + << (*(in_RETIRE_NUM_REG_RD_LOG [i])) + << (*(in_RETIRE_NUM_REG_RE_LOG [i])); + } # ifdef SYSTEMCASS_SPECIFIC @@ -117,5 +160,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_Address_Translation_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_allocation.cpp (revision 88) @@ -107,34 +107,47 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RD_PHY_OLD,"restore_rd_phy_old",Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_RESTORE_RE_PHY_OLD,"restore_re_phy_old",Tcontrol_t ,1); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { internal_RENAME_ACK = new Tcontrol_t [_param->_nb_inst_insert]; internal_INSERT_ACK = new Tcontrol_t [_param->_nb_inst_insert]; internal_RETIRE_ACK = new Tcontrol_t [_param->_nb_inst_retire]; - rat_gpr = new Tgeneral_address_t ** [_param->_nb_front_end]; - rat_gpr_update_table = new bool ** [_param->_nb_front_end]; - rat_spr = new Tspecial_address_t ** [_param->_nb_front_end]; - rat_spr_update_table = new bool ** [_param->_nb_front_end]; + rat_gpr = new Tgeneral_address_t ** [_param->_nb_front_end]; + rat_spr = new Tspecial_address_t ** [_param->_nb_front_end]; + rat_gpr_update_table = new bool ** [_param->_nb_front_end]; + rat_spr_update_table = new bool ** [_param->_nb_front_end]; + internal_rat_gpr_update_table = new bool ** [_param->_nb_front_end]; + internal_rat_spr_update_table = new bool ** [_param->_nb_front_end]; for (uint32_t i=0; i<_param->_nb_front_end; i++) { - rat_gpr [i] = new Tgeneral_address_t * [_param->_nb_context[i]]; - rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; - rat_spr [i] = new Tspecial_address_t * [_param->_nb_context[i]]; - rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; + rat_gpr [i] = new Tgeneral_address_t * [_param->_nb_context[i]]; + rat_spr [i] = new Tspecial_address_t * [_param->_nb_context[i]]; + rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; + rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; + internal_rat_gpr_update_table [i] = new bool * [_param->_nb_context[i]]; + internal_rat_spr_update_table [i] = new bool * [_param->_nb_context[i]]; for (uint32_t j=0; j<_param->_nb_context[i]; j++) { - rat_gpr [i][j] = new Tgeneral_address_t [_param->_nb_general_register_logic]; - rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; - rat_spr [i][j] = new Tspecial_address_t [_param->_nb_special_register_logic]; - rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; + rat_gpr [i][j] = new Tgeneral_address_t [_param->_nb_general_register_logic]; + rat_spr [i][j] = new Tspecial_address_t [_param->_nb_special_register_logic]; + rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; + rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; + internal_rat_gpr_update_table [i][j] = new bool [_param->_nb_general_register_logic]; + internal_rat_spr_update_table [i][j] = new bool [_param->_nb_special_register_logic]; } } + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -72,14 +72,20 @@ delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; + delete [] out_RETIRE_RESTORE_RD_PHY_OLD; + delete [] out_RETIRE_RESTORE_RE_PHY_OLD; + + delete [] internal_RENAME_ACK; + delete [] internal_INSERT_ACK; + delete [] internal_RETIRE_ACK; + + delete [] rat_gpr ; + delete [] rat_spr ; + delete [] rat_gpr_update_table; + delete [] rat_spr_update_table; + delete [] internal_rat_gpr_update_table; + delete [] internal_rat_spr_update_table; } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] internal_RENAME_ACK; - delete [] internal_INSERT_ACK; - delete [] internal_RETIRE_ACK; - - delete [] rat_gpr ; - delete [] rat_gpr_update_table; - delete [] rat_spr ; - delete [] rat_spr_update_table; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 88) @@ -0,0 +1,52 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace register_translation_unit { +namespace register_address_translation_unit { + + +#undef FUNCTION +#define FUNCTION "Register_Address_Translation_unit::genMealy_rename" + void Register_Address_Translation_unit::genMealy_rename (void) + { + log_begin(Register_Address_Translation_unit,FUNCTION); + log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; + + PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RA_LOG [i])]); + PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RB_LOG [i])]); + PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RC_LOG [i])]); + PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RD_LOG [i])]); + PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RE_LOG [i])]); + } + + log_end(Register_Address_Translation_unit,FUNCTION); + }; + +}; // end namespace register_address_translation_unit +}; // end namespace register_translation_unit +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_retire.cpp (revision 88) @@ -0,0 +1,110 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace register_translation_unit { +namespace register_address_translation_unit { + + +#undef FUNCTION +#define FUNCTION "Register_Address_Translation_unit::genMealy_retire" + void Register_Address_Translation_unit::genMealy_retire (void) + { + log_begin(Register_Address_Translation_unit,FUNCTION); + log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); + + // Init internal update table + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) + internal_rat_gpr_update_table [i][j][k] = rat_gpr_update_table [i][j][k]; + for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) + internal_rat_spr_update_table [i][j][k] = rat_spr_update_table [i][j][k]; + } + + + // RETIRE is in order -> also don't need test if an instruction is valid + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * inst_retire [%d]",i); + + // init -> need't restore old value + Tcontrol_t retire_restore_rd_phy_old = false; + Tcontrol_t retire_restore_re_phy_old = false; + Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [i]); + + // Test if event -> need restore ? + if (event_state != EVENT_STATE_NO_EVENT) + { + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Have event"); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); + + // Test if event have just occure -> reset update_table + if (event_state == EVENT_STATE_EVENT) + { + // Reset update_table + for (uint32_t j=0; j<_param->_nb_general_register_logic; j++) + internal_rat_gpr_update_table[front_end_id][context_id][j] = 0; + for (uint32_t j=0; j<_param->_nb_special_register_logic; j++) + internal_rat_spr_update_table[front_end_id][context_id][j] = 0; + } + + // Test and update update table + if (PORT_READ(in_RETIRE_WRITE_RD [i])) + { + Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); + retire_restore_rd_phy_old = (internal_rat_gpr_update_table[front_end_id][context_id][rd_log] == 0); + +// log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd"); +// log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log); +// log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rat_gpr_update : %d",internal_rat_gpr_update_table[front_end_id][context_id][rd_log]); + + internal_rat_gpr_update_table[front_end_id][context_id][rd_log] = 1; + } + if (PORT_READ(in_RETIRE_WRITE_RE [i])) + { +// log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re"); + + Tgeneral_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); + retire_restore_re_phy_old = (internal_rat_spr_update_table[front_end_id][context_id][re_log] == 0); + internal_rat_spr_update_table[front_end_id][context_id][re_log] = 1; + } + + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_rd_phy_old : %d",retire_restore_rd_phy_old); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re_phy_old : %d",retire_restore_re_phy_old); + } + + PORT_WRITE(out_RETIRE_RESTORE_RD_PHY_OLD[i], retire_restore_rd_phy_old); + PORT_WRITE(out_RETIRE_RESTORE_RE_PHY_OLD[i], retire_restore_re_phy_old); + } + + log_end(Register_Address_Translation_unit,FUNCTION); + }; + +}; // end namespace register_address_translation_unit +}; // end namespace register_translation_unit +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMoore.cpp (revision 87) +++ (revision ) @@ -1,51 +1,0 @@ -#ifdef SYSTEMC -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" - -namespace morpheo { -namespace behavioural { -namespace core { -namespace multi_ooo_engine { -namespace ooo_engine { -namespace rename_unit { -namespace register_translation_unit { -namespace register_address_translation_unit { - - -#undef FUNCTION -#define FUNCTION "Register_Address_Translation_unit::genMoore" - void Register_Address_Translation_unit::genMoore (void) - { - log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); - - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; - Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; - - PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RA_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RB_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RC_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RD_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RE_LOG [i])]); - } - - log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"End"); - }; - -}; // end namespace register_address_translation_unit -}; // end namespace register_translation_unit -}; // end namespace rename_unit -}; // end namespace ooo_engine -}; // end namespace multi_ooo_engine -}; // end namespace core - -}; // end namespace behavioural -}; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 88) @@ -23,5 +23,6 @@ void Register_Address_Translation_unit::transition (void) { - log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin"); + log_begin(Register_Address_Translation_unit,FUNCTION); + log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -90,15 +91,15 @@ } - - // Test if write and have not a previous update + // Test if write and have not a previous update if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) { Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); - log_printf(NONE,Register_Address_Translation_unit,FUNCTION,"retire[%d]",i); - log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); - log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); - log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire[%d]",i); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log ); +// if (RETIRE_RESTORE_RD_PHY_OLD [i]) if (rat_gpr_update_table[front_end_id][context_id][rd_log] == 0) { @@ -112,4 +113,5 @@ Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); +// if (RETIRE_RESTORE_RE_PHY_OLD [i]) if (rat_spr_update_table[front_end_id][context_id][re_log] == 0) { @@ -122,9 +124,24 @@ } +#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); + + for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.2d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); + + for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.2d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); + } +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); #endif - log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"End"); + log_end(Register_Address_Translation_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Register_translation_unit_Glue_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/configuration.cfg (revision 88) @@ -2,2 +2,4 @@ 1 4 *2 # nb_inst_insert 1 4 *2 # nb_inst_retire +5 5 *2 # size_general_register +2 2 *2 # size_special_register Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/main.cpp (revision 88) @@ -8,5 +8,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/include/test.h" -#define NB_PARAMS 2 +#define NB_PARAMS 4 void usage (int argc, char * argv[]) @@ -14,6 +14,8 @@ err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); - err (_(" * nb_inst_insert (uint32_t)\n")); - err (_(" * nb_inst_retire (uint32_t)\n")); + err (_(" * nb_inst_insert (uint32_t)\n")); + err (_(" * nb_inst_retire (uint32_t)\n")); + err (_(" * size_general_register (uint32_t)\n")); + err (_(" * size_special_register (uint32_t)\n")); exit (1); @@ -32,6 +34,9 @@ string name = argv[x++]; - uint32_t _nb_inst_insert = atoi(argv[x++]); - uint32_t _nb_inst_retire = atoi(argv[x++]); + uint32_t _nb_inst_insert = fromString(argv[x++]); + uint32_t _nb_inst_retire = fromString(argv[x++]); + uint32_t _size_general_register = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + int _return = EXIT_SUCCESS; @@ -40,5 +45,9 @@ morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Parameters (_nb_inst_insert, - _nb_inst_retire); + _nb_inst_retire, + _size_general_register, + _size_special_register, + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Register_translation_unit_Glue * _Register_translation_unit_Glue = new Register_translation_unit_Glue (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -51,4 +61,53 @@ ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); + + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ," in_INSERT_DEPENDENCY_CHECKING_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RB ," in_INSERT_DEPENDENCY_CHECKING_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RC ," in_INSERT_DEPENDENCY_CHECKING_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ," in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ," in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert); + + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,"out_INSERT_STAT_LIST_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,"out_INSERT_STAT_LIST_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,"out_INSERT_STAT_LIST_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,"out_INSERT_STAT_LIST_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,"out_INSERT_STAT_LIST_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); + + ALLOC1_SC_SIGNAL(out_INSERT_RAT_WRITE_RD ,"out_INSERT_RAT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_LOG ,"out_INSERT_RAT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,"out_INSERT_RAT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_WRITE_RE ,"out_INSERT_RAT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_LOG ,"out_INSERT_RAT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,"out_INSERT_RAT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); + + ALLOC1_SC_SIGNAL(out_INSERT_READ_RA ,"out_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,"out_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_READ_RB ,"out_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,"out_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_READ_RC ,"out_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,"out_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RD ,"out_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,"out_INSERT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,"out_INSERT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,"out_INSERT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RE ,"out_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,"out_INSERT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,"out_INSERT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,"out_INSERT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t,_param->_nb_inst_retire); @@ -78,10 +137,59 @@ INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_VAL ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_ACK ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_RAT_VAL ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_RAT_ACK ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_STAT_LIST_VAL ,_param->_nb_inst_retire); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_STAT_LIST_ACK ,_param->_nb_inst_retire); + + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RB ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RC ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_WRITE_RD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_WRITE_RE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RA ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RB ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RC ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_WRITE_RD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_WRITE_RE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_ACK ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_RAT_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_RAT_ACK ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_STAT_LIST_VAL,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -187,21 +295,70 @@ delete in_NRESET; - delete [] in_INSERT_RENAME_VAL ; - delete [] out_INSERT_RENAME_ACK ; - delete [] out_INSERT_INSERT_VAL ; - delete [] in_INSERT_INSERT_ACK ; - delete [] out_INSERT_RAT_INSERT_VAL; - delete [] in_INSERT_RAT_RENAME_ACK; - delete [] in_INSERT_RAT_INSERT_ACK; - delete [] out_INSERT_FREE_LIST_VAL ; - delete [] in_INSERT_FREE_LIST_ACK ; - delete [] out_INSERT_STAT_LIST_VAL ; - delete [] in_INSERT_STAT_LIST_ACK ; - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - delete [] out_RETIRE_RAT_VAL ; - delete [] in_RETIRE_RAT_ACK ; - delete [] out_RETIRE_STAT_LIST_VAL ; - delete [] in_RETIRE_STAT_LIST_ACK ; + DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RB ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RC ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL(out_INSERT_RAT_WRITE_RD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_WRITE_RE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_RAT_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_RAT_ACK ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_STAT_LIST_VAL,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Parameters.h (revision 88) @@ -27,11 +27,19 @@ public : uint32_t _nb_inst_insert; public : uint32_t _nb_inst_retire; +//public : uint32_t _size_general_register; +//public : uint32_t _size_special_register; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_inst_insert, - uint32_t nb_inst_retire); + uint32_t nb_inst_retire, + uint32_t size_general_register, + uint32_t size_special_register, + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h (revision 88) @@ -64,15 +64,63 @@ // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tcontrol_t) ** in_INSERT_RENAME_VAL ;//[nb_inst_insert] - public : SC_OUT(Tcontrol_t) ** out_INSERT_RENAME_ACK ;//[nb_inst_insert] - public : SC_OUT(Tcontrol_t) ** out_INSERT_INSERT_VAL ;//[nb_inst_insert] - public : SC_IN (Tcontrol_t) ** in_INSERT_INSERT_ACK ;//[nb_inst_insert] - public : SC_OUT(Tcontrol_t) ** out_INSERT_RAT_INSERT_VAL;//[nb_inst_insert] - public : SC_IN (Tcontrol_t) ** in_INSERT_RAT_RENAME_ACK;//[nb_inst_insert] - public : SC_IN (Tcontrol_t) ** in_INSERT_RAT_INSERT_ACK;//[nb_inst_insert] - public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_VAL ;//[nb_inst_insert] - public : SC_IN (Tcontrol_t) ** in_INSERT_FREE_LIST_ACK ;//[nb_inst_insert] - public : SC_OUT(Tcontrol_t) ** out_INSERT_STAT_LIST_VAL ;//[nb_inst_insert] - public : SC_IN (Tcontrol_t) ** in_INSERT_STAT_LIST_ACK ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_RENAME_VAL ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_RENAME_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_INSERT_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_INSERT_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_RAT_INSERT_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_RAT_RENAME_ACK ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_RAT_INSERT_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_FREE_LIST_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_STAT_LIST_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t) ** in_INSERT_STAT_LIST_ACK ;//[nb_inst_insert] + + public : SC_IN (Tcontrol_t ) ** in_INSERT_DEPENDENCY_CHECKING_READ_RA ;//[nb_inst_insert] + public : SC_IN (Tgeneral_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_DEPENDENCY_CHECKING_READ_RB ;//[nb_inst_insert] + public : SC_IN (Tgeneral_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_DEPENDENCY_CHECKING_READ_RC ;//[nb_inst_insert] + public : SC_IN (Tspecial_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ;//[nb_inst_insert] + public : SC_IN (Tgeneral_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ;//[nb_inst_insert] + public : SC_IN (Tgeneral_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD;//[nb_inst_insert] + public : SC_IN (Tgeneral_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ;//[nb_inst_insert] + public : SC_IN (Tspecial_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ;//[nb_inst_insert] + public : SC_IN (Tspecial_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD;//[nb_inst_insert] + public : SC_IN (Tspecial_address_t) ** in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW;//[nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_READ_RA ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RA_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_READ_RB ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RB_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_READ_RC ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RC_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_WRITE_RD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_STAT_LIST_WRITE_RE ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RAT_WRITE_RD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_RAT_NUM_REG_RD_LOG ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_RAT_NUM_REG_RD_PHY_NEW ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RAT_WRITE_RE ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_RAT_NUM_REG_RE_LOG ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_RAT_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RA ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RA_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RB ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RB_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RC ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RC_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_WRITE_RD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_LOG ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_PHY_OLD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_PHY_NEW ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_WRITE_RE ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_LOG ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_PHY_OLD ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -124,4 +172,5 @@ public : void transition (void); # endif + public : void genMealy_insert_valack (void); public : void genMealy_insert (void); public : void genMealy_retire (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters.cpp (revision 88) @@ -21,12 +21,24 @@ #define FUNCTION "Register_translation_unit_Glue::Parameters" Parameters::Parameters (uint32_t nb_inst_insert, - uint32_t nb_inst_retire) + uint32_t nb_inst_retire, + uint32_t size_general_register, + uint32_t size_special_register, + bool is_toplevel) { log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); - _nb_inst_insert = nb_inst_insert; - _nb_inst_retire = nb_inst_retire; + _nb_inst_insert = nb_inst_insert; + _nb_inst_retire = nb_inst_retire; test(); + + if (is_toplevel) + { + _size_general_register = size_general_register; + _size_special_register = size_special_register; + + copy (); + } + log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End"); }; @@ -43,5 +55,13 @@ #undef FUNCTION #define FUNCTION "Register_translation_unit_Glue::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); + log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Register_translation_unit_Glue::copy" + void Parameters::copy (void) { log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Parameters_print.cpp (revision 88) @@ -28,6 +28,8 @@ xml.balise_open("register_translation_unit_glue"); - xml.singleton_begin("nb_inst_insert"); xml.attribut("value",toString(_nb_inst_insert)); xml.singleton_end(); - xml.singleton_begin("nb_inst_retire"); xml.attribut("value",toString(_nb_inst_retire)); xml.singleton_end(); + xml.singleton_begin("nb_inst_insert "); xml.attribut("value",toString(_nb_inst_insert )); xml.singleton_end(); + xml.singleton_begin("nb_inst_retire "); xml.attribut("value",toString(_nb_inst_retire )); xml.singleton_end(); + xml.singleton_begin("size_general_register"); xml.attribut("value",toString(_size_general_register)); xml.singleton_end(); + xml.singleton_begin("size_special_register"); xml.attribut("value",toString(_size_special_register)); xml.singleton_end(); xml.balise_close(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue.cpp (revision 88) @@ -39,4 +39,10 @@ log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); +#if DEBUG_Register_translation_unit_Glue == true + log_printf(INFO,Register_translation_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Allocation"); @@ -48,5 +54,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Allocation of statistics"); @@ -57,5 +63,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +73,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Method - transition"); @@ -83,5 +89,5 @@ SC_METHOD (genMealy_retire); dont_initialize (); -// sensitive << (*(in_CLOCK)).neg(); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register for (uint32_t i=0; i<_param->_nb_inst_retire; i++) sensitive << (*(in_RETIRE_VAL [i])) @@ -104,9 +110,9 @@ # endif - log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Method - genMealy_insert"); - - SC_METHOD (genMealy_insert); - dont_initialize (); -// sensitive << (*(in_CLOCK)).neg(); + log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Method - genMealy_insert_valack"); + + SC_METHOD (genMealy_insert_valack); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register for (uint32_t i=0; i<_param->_nb_inst_insert; i++) sensitive << (*(in_INSERT_RENAME_VAL [i])) @@ -152,4 +158,31 @@ } # endif + + log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Method - genMealy_insert"); + + SC_METHOD (genMealy_insert); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + sensitive << (*(in_INSERT_DEPENDENCY_CHECKING_READ_RA [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_READ_RB [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_READ_RC [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD [i])) + << (*(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + #endif @@ -165,5 +198,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_translation_unit_Glue,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 88) @@ -72,4 +72,52 @@ ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1); + + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,"DEPENDENCY_CHECKING_READ_RA" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,"DEPENDENCY_CHECKING_NUM_REG_RA_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RB ,"DEPENDENCY_CHECKING_READ_RB" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,"DEPENDENCY_CHECKING_NUM_REG_RB_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RC ,"DEPENDENCY_CHECKING_READ_RC" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,"DEPENDENCY_CHECKING_NUM_REG_RC_PHY" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,"DEPENDENCY_CHECKING_WRITE_RD" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,"DEPENDENCY_CHECKING_NUM_REG_RD_LOG" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,"DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,"DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,"DEPENDENCY_CHECKING_WRITE_RE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,"DEPENDENCY_CHECKING_NUM_REG_RE_LOG" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,"DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,"DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_READ_RA ,"STAT_LIST_READ_RA" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,"STAT_LIST_NUM_REG_RA_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_READ_RB ,"STAT_LIST_READ_RB" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,"STAT_LIST_NUM_REG_RB_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_READ_RC ,"STAT_LIST_READ_RC" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,"STAT_LIST_NUM_REG_RC_PHY" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_WRITE_RD ,"STAT_LIST_WRITE_RD" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,"STAT_LIST_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_WRITE_RE ,"STAT_LIST_WRITE_RE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,"STAT_LIST_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_WRITE_RD ,"RAT_WRITE_RD" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_NUM_REG_RD_LOG ,"RAT_NUM_REG_RD_LOG" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,"RAT_NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_WRITE_RE ,"RAT_WRITE_RE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_NUM_REG_RE_LOG ,"RAT_NUM_REG_RE_LOG" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,"RAT_NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); + + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RA ,"READ_RA" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_PHY ,"NUM_REG_RA_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RB ,"READ_RB" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_PHY ,"NUM_REG_RB_PHY" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RC ,"READ_RC" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_PHY ,"NUM_REG_RC_PHY" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_LOG ,"NUM_REG_RD_LOG" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_OLD ,"NUM_REG_RD_PHY_OLD" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_NEW ,"NUM_REG_RD_PHY_NEW" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_LOG ,"NUM_REG_RE_LOG" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"NUM_REG_RE_PHY_OLD" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register ); } @@ -89,5 +137,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -24,27 +25,76 @@ log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; delete in_NRESET; - delete [] in_INSERT_RENAME_VAL ; - delete [] out_INSERT_RENAME_ACK ; - delete [] out_INSERT_INSERT_VAL ; - delete [] in_INSERT_INSERT_ACK ; - delete [] out_INSERT_RAT_INSERT_VAL; - delete [] in_INSERT_RAT_RENAME_ACK; - delete [] in_INSERT_RAT_INSERT_ACK; - delete [] out_INSERT_FREE_LIST_VAL ; - delete [] in_INSERT_FREE_LIST_ACK ; - delete [] out_INSERT_STAT_LIST_VAL ; - delete [] in_INSERT_STAT_LIST_ACK ; + DELETE1_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1); + + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RB ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RC ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register ); + + DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); + + DELETE1_SIGNAL(out_INSERT_RAT_WRITE_RD ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RAT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_RAT_WRITE_RE ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RAT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); + + DELETE1_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); + + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_RAT_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_RAT_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_STAT_LIST_VAL,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire,1); - delete [] in_RETIRE_VAL ; - delete [] out_RETIRE_ACK ; - delete [] out_RETIRE_RAT_VAL ; - delete [] in_RETIRE_RAT_ACK ; - delete [] out_RETIRE_STAT_LIST_VAL ; - delete [] in_RETIRE_STAT_LIST_ACK ; } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 88) @@ -23,43 +23,59 @@ void Register_translation_unit_Glue::genMealy_insert (void) { - log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_translation_unit_Glue,FUNCTION); + log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_insert; i++) { - Tcontrol_t rename_val = PORT_READ(in_INSERT_RENAME_VAL [i]); - Tcontrol_t insert_ack = PORT_READ(in_INSERT_INSERT_ACK [i]); - Tcontrol_t rat_rename_ack = PORT_READ(in_INSERT_RAT_RENAME_ACK [i]); - Tcontrol_t rat_insert_ack = PORT_READ(in_INSERT_RAT_INSERT_ACK [i]); - Tcontrol_t free_list_ack = PORT_READ(in_INSERT_FREE_LIST_ACK [i]); - Tcontrol_t stat_list_ack = PORT_READ(in_INSERT_STAT_LIST_ACK [i]); + Tcontrol_t READ_RA = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_READ_RA [i]); + Tgeneral_address_t NUM_REG_RA_PHY = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY [i]); + Tcontrol_t READ_RB = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_READ_RB [i]); + Tgeneral_address_t NUM_REG_RB_PHY = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY [i]); + Tcontrol_t READ_RC = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_READ_RC [i]); + Tspecial_address_t NUM_REG_RC_PHY = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY [i]); + Tcontrol_t WRITE_RD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD [i]); + Tgeneral_address_t NUM_REG_RD_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG [i]); + Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]); + Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]); + Tcontrol_t WRITE_RE = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE [i]); + Tspecial_address_t NUM_REG_RE_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG [i]); + Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD [i]); + Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i]); - PORT_WRITE(out_INSERT_RENAME_ACK [i], (insert_ack and - rat_rename_ack and - rat_insert_ack and - free_list_ack and - stat_list_ack )); - PORT_WRITE(out_INSERT_INSERT_VAL [i], (rename_val and - rat_rename_ack and - rat_insert_ack and - free_list_ack and - stat_list_ack )); - PORT_WRITE(out_INSERT_RAT_INSERT_VAL [i], (rename_val and - insert_ack and - rat_rename_ack and - free_list_ack and - stat_list_ack )); - PORT_WRITE(out_INSERT_FREE_LIST_VAL [i], (rename_val and - insert_ack and - rat_rename_ack and - rat_insert_ack and - stat_list_ack )); - PORT_WRITE(out_INSERT_STAT_LIST_VAL [i], (rename_val and - insert_ack and - rat_rename_ack and - rat_insert_ack and - free_list_ack )); + PORT_WRITE(out_INSERT_STAT_LIST_READ_RA [i], READ_RA ); + PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RA_PHY [i], NUM_REG_RA_PHY ); + PORT_WRITE(out_INSERT_STAT_LIST_READ_RB [i], READ_RB ); + PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RB_PHY [i], NUM_REG_RB_PHY ); + PORT_WRITE(out_INSERT_STAT_LIST_READ_RC [i], READ_RC ); + PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RC_PHY [i], NUM_REG_RC_PHY ); + PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RD [i], WRITE_RD ); + PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW [i], NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_INSERT_STAT_LIST_WRITE_RE [i], WRITE_RE ); + PORT_WRITE(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW [i], NUM_REG_RE_PHY_NEW); + + PORT_WRITE(out_INSERT_RAT_WRITE_RD [i], WRITE_RD ); + PORT_WRITE(out_INSERT_RAT_NUM_REG_RD_LOG [i], NUM_REG_RD_LOG ); + PORT_WRITE(out_INSERT_RAT_NUM_REG_RD_PHY_NEW [i], NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_INSERT_RAT_WRITE_RE [i], WRITE_RE ); + PORT_WRITE(out_INSERT_RAT_NUM_REG_RE_LOG [i], NUM_REG_RE_LOG ); + PORT_WRITE(out_INSERT_RAT_NUM_REG_RE_PHY_NEW [i], NUM_REG_RE_PHY_NEW); + + PORT_WRITE(out_INSERT_READ_RA [i], READ_RA ); + PORT_WRITE(out_INSERT_NUM_REG_RA_PHY [i], NUM_REG_RA_PHY ); + PORT_WRITE(out_INSERT_READ_RB [i], READ_RB ); + PORT_WRITE(out_INSERT_NUM_REG_RB_PHY [i], NUM_REG_RB_PHY ); + PORT_WRITE(out_INSERT_READ_RC [i], READ_RC ); + PORT_WRITE(out_INSERT_NUM_REG_RC_PHY [i], NUM_REG_RC_PHY ); + PORT_WRITE(out_INSERT_WRITE_RD [i], WRITE_RD ); + PORT_WRITE(out_INSERT_NUM_REG_RD_LOG [i], NUM_REG_RD_LOG ); + PORT_WRITE(out_INSERT_NUM_REG_RD_PHY_OLD [i], NUM_REG_RD_PHY_OLD); + PORT_WRITE(out_INSERT_NUM_REG_RD_PHY_NEW [i], NUM_REG_RD_PHY_NEW); + PORT_WRITE(out_INSERT_WRITE_RE [i], WRITE_RE ); + PORT_WRITE(out_INSERT_NUM_REG_RE_LOG [i], NUM_REG_RE_LOG ); + PORT_WRITE(out_INSERT_NUM_REG_RE_PHY_OLD [i], NUM_REG_RE_PHY_OLD); + PORT_WRITE(out_INSERT_NUM_REG_RE_PHY_NEW [i], NUM_REG_RE_PHY_NEW); } - log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End"); + log_end(Register_translation_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert_valack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert_valack.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert_valack.cpp (revision 88) @@ -0,0 +1,98 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace register_translation_unit { +namespace register_translation_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Register_translation_unit_Glue::genMealy_insert_valack" + void Register_translation_unit_Glue::genMealy_insert_valack (void) + { + log_begin(Register_translation_unit_Glue,FUNCTION); + log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str()); + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + Tcontrol_t rename_val = PORT_READ(in_INSERT_RENAME_VAL [i]); + Tcontrol_t insert_ack = PORT_READ(in_INSERT_INSERT_ACK [i]); + Tcontrol_t rat_rename_ack = PORT_READ(in_INSERT_RAT_RENAME_ACK [i]); + Tcontrol_t rat_insert_ack = PORT_READ(in_INSERT_RAT_INSERT_ACK [i]); + Tcontrol_t free_list_ack = PORT_READ(in_INSERT_FREE_LIST_ACK [i]); + Tcontrol_t stat_list_ack = PORT_READ(in_INSERT_STAT_LIST_ACK [i]); + + Tcontrol_t rename_ack = (insert_ack and + rat_rename_ack and + rat_insert_ack and + free_list_ack and + stat_list_ack ); + Tcontrol_t insert_val = (rename_val and + rat_rename_ack and + rat_insert_ack and + free_list_ack and + stat_list_ack ); + Tcontrol_t rat_insert_val = (rename_val and + insert_ack and + rat_rename_ack and + free_list_ack and + stat_list_ack ); + Tcontrol_t free_list_val = (rename_val and + insert_ack and + rat_rename_ack and + rat_insert_ack and + stat_list_ack ); + Tcontrol_t stat_list_val = (rename_val and + insert_ack and + rat_rename_ack and + rat_insert_ack and + free_list_ack ); + + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * inst_insert [%d]",i); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rename_val (r): %d",rename_val ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rename_ack (w): %d",rename_ack ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * insert_val (w): %d",insert_val ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * insert_ack (r): %d",insert_ack ); +// log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_rename_val (w): %d",rat_rename_val); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_rename_val -> rename_val"); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_rename_ack (r): %d",rat_rename_ack); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_insert_val (w): %d",rat_insert_val); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * rat_insert_ack (r): %d",rat_insert_ack); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * free_list_val (w): %d",free_list_val ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * free_list_ack (r): %d",free_list_ack ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * stat_list_val (w): %d",stat_list_val ); + log_printf(TRACE,Register_translation_unit_Glue,FUNCTION," * stat_list_ack (r): %d",stat_list_ack ); + + + PORT_WRITE(out_INSERT_RENAME_ACK [i], rename_ack ); + PORT_WRITE(out_INSERT_INSERT_VAL [i], insert_val ); + PORT_WRITE(out_INSERT_RAT_INSERT_VAL [i], rat_insert_val); + PORT_WRITE(out_INSERT_FREE_LIST_VAL [i], free_list_val ); + PORT_WRITE(out_INSERT_STAT_LIST_VAL [i], stat_list_val ); + + } + + log_end(Register_translation_unit_Glue,FUNCTION); + }; + +}; // end namespace register_translation_unit_glue +}; // end namespace register_translation_unit +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_retire.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_retire.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_retire.cpp (revision 88) @@ -23,5 +23,6 @@ void Register_translation_unit_Glue::genMealy_retire (void) { - log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"Begin"); + log_begin(Register_translation_unit_Glue,FUNCTION); + log_function(Register_translation_unit_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_retire; i++) @@ -36,5 +37,5 @@ } - log_printf(FUNC,Register_translation_unit_Glue,FUNCTION,"End"); + log_end(Register_translation_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Register_translation_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,10 @@ +Register_translation_unit +1 1 *2 #nb_front_end +1 1 *2 #nb_context [nb_front_end] +64 64 *2 #nb_general_register +4 4 *2 #nb_special_register +1 1 *4 #nb_inst_insert +1 1 *4 #nb_inst_retire +1 1 *4 #nb_reg_free +1 1 *2 #nb_bank +1 1 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1.cfg (revision 88) @@ -0,0 +1,10 @@ +Register_translation_unit +1 1 *2 #nb_front_end +1 1 *2 #nb_context [nb_front_end] +64 64 *2 #nb_general_register +16 16 *2 #nb_special_register +1 4 *4 #nb_inst_insert +1 4 *4 #nb_inst_retire +1 4 *4 #nb_reg_free +8 8 *2 #nb_bank +1 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_1a.cfg (revision 88) @@ -0,0 +1,10 @@ +Register_translation_unit +1 1 *2 #nb_front_end +1 1 *2 #nb_context [nb_front_end] +64 64 *2 #nb_general_register +16 16 *2 #nb_special_register +1 4 *4 #nb_inst_insert +1 4 *4 #nb_inst_retire +1 4 *4 #nb_reg_free +8 8 *2 #nb_bank +1 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4a.cfg (revision 88) @@ -0,0 +1,13 @@ +Register_translation_unit +4 4 *2 #nb_front_end +1 1 *2 #nb_context [0] [nb_front_end] +1 1 *2 #nb_context [1] [nb_front_end] +1 1 *2 #nb_context [2] [nb_front_end] +1 1 *2 #nb_context [3] [nb_front_end] +256 256 *2 #nb_general_register +32 32 *2 #nb_special_register +4 4 *4 #nb_inst_insert +4 4 *4 #nb_inst_retire +4 4 *4 #nb_reg_free +8 8 *2 #nb_bank +2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4b.cfg (revision 88) @@ -0,0 +1,10 @@ +Register_translation_unit +1 1 *2 #nb_front_end +4 4 *2 #nb_context [0] [nb_front_end] +256 256 *2 #nb_general_register +32 32 *2 #nb_special_register +4 4 *4 #nb_inst_insert +4 4 *4 #nb_inst_retire +4 4 *4 #nb_reg_free +8 8 *2 #nb_bank +2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4c.cfg (revision 88) @@ -0,0 +1,11 @@ +Register_translation_unit +2 2 *2 #nb_front_end +2 2 *2 #nb_context [0] [nb_front_end] +2 2 *2 #nb_context [1] [nb_front_end] +256 256 *2 #nb_general_register +32 32 *2 #nb_special_register +4 4 *4 #nb_inst_insert +4 4 *4 #nb_inst_retire +4 4 *4 #nb_reg_free +8 8 *2 #nb_bank +2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/config-thread_4d.cfg (revision 88) @@ -0,0 +1,11 @@ +Register_translation_unit +2 2 *2 #nb_front_end +1 1 *2 #nb_context [0] [nb_front_end] +3 3 *2 #nb_context [1] [nb_front_end] +256 256 *2 #nb_general_register +32 32 *2 #nb_special_register +4 4 *4 #nb_inst_insert +4 4 *4 #nb_inst_retire +4 4 *4 #nb_reg_free +8 8 *2 #nb_bank +2 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/configuration.cfg (revision 87) +++ (revision ) @@ -1,10 +1,0 @@ -Register_translation_unit -1 1 *2 #nb_front_end -1 1 *2 #nb_context [nb_front_end] -64 64 *2 #nb_general_register -16 16 *2 #nb_special_register -1 4 *4 #nb_inst_insert -1 4 *4 #nb_inst_retire -1 4 *4 #nb_reg_free -8 8 *2 #nb_bank -1 2 *2 #size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/main.cpp (revision 88) @@ -65,5 +65,7 @@ _nb_reg_free , _nb_bank , - _size_read_counter ); + _size_read_counter , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Register_translation_unit * _Register_translation_unit = new Register_translation_unit (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Stat_List_unit_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/main.cpp (revision 88) @@ -68,5 +68,7 @@ _nb_reg_free , _nb_bank , - _size_counter ); + _size_counter , + true //is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/src/test.cpp (revision 88) @@ -34,4 +34,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Stat_List_unit * _Stat_List_unit = new Stat_List_unit (name.c_str(), @@ -40,5 +50,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -72,7 +82,9 @@ ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ," in_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE_RD_PHY_OLD," in_RETIRE_RESTORE_RD_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW," in_RETIRE_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RE ," in_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_RESTORE_RE_PHY_OLD," in_RETIRE_RESTORE_RE_PHY_OLD",Tcontrol_t ,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire); ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire); @@ -116,7 +128,9 @@ INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE_RD_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_RESTORE_RE_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire); INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire); @@ -347,7 +361,9 @@ in_RETIRE_NUM_REG_RC_PHY [i]->write(rc); in_RETIRE_WRITE_RD [i]->write(write_rd); + in_RETIRE_RESTORE_RD_PHY_OLD [i]->write(0); in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rd_old); in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rd_new); in_RETIRE_WRITE_RE [i]->write(write_re); + in_RETIRE_RESTORE_RE_PHY_OLD [i]->write(0); in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(re_old); in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(re_new); @@ -486,16 +502,18 @@ if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) { - Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); - Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); - Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read(); - Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read(); - Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read(); - Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read(); - Tcontrol_t write_rd = in_RETIRE_WRITE_RD [i]->read(); - Tgeneral_address_t rd_old = in_RETIRE_NUM_REG_RD_PHY_OLD [i]->read(); - Tgeneral_address_t rd_new = in_RETIRE_NUM_REG_RD_PHY_NEW [i]->read(); - Tcontrol_t write_re = in_RETIRE_WRITE_RE [i]->read(); - Tgeneral_address_t re_old = in_RETIRE_NUM_REG_RE_PHY_OLD [i]->read(); - Tgeneral_address_t re_new = in_RETIRE_NUM_REG_RE_PHY_NEW [i]->read(); + Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); + Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); + Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read(); + Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read(); + Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read(); + Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read(); + Tcontrol_t write_rd = in_RETIRE_WRITE_RD [i]->read(); + Tcontrol_t restore_rd_old = in_RETIRE_RESTORE_RD_PHY_OLD [i]->read(); + Tgeneral_address_t rd_old = in_RETIRE_NUM_REG_RD_PHY_OLD [i]->read(); + Tgeneral_address_t rd_new = in_RETIRE_NUM_REG_RD_PHY_NEW [i]->read(); + Tcontrol_t write_re = in_RETIRE_WRITE_RE [i]->read(); + Tcontrol_t restore_re_old = in_RETIRE_RESTORE_RE_PHY_OLD [i]->read(); + Tgeneral_address_t re_old = in_RETIRE_NUM_REG_RE_PHY_OLD [i]->read(); + Tgeneral_address_t re_new = in_RETIRE_NUM_REG_RE_PHY_NEW [i]->read(); LABEL("RETIRE [%d] - Accepted",i); @@ -519,4 +537,5 @@ LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter ); LABEL(" * read_rd : %d",write_rd); + LABEL(" * restore_rd_old : %d",restore_rd_old); LABEL(" * reg_rd_old : %d",rd_old ); LABEL(" * status[%d]._is_free : %d",rd_old,spr_status[rd_old]._is_free ); @@ -530,4 +549,5 @@ LABEL(" * status[%d]._counter : %d",rd_new,spr_status[rd_new]._counter ); LABEL(" * read_re : %d",write_re); + LABEL(" * restore_re_old : %d",restore_re_old); LABEL(" * reg_re_old : %d",re_old ); LABEL(" * status[%d]._is_free : %d",re_old,spr_status[re_old]._is_free ); @@ -555,12 +575,30 @@ if (write_rd) { - gpr_status[rd_old]._is_link = 0; - gpr_status[rd_new]._is_valid = 1; + if (restore_rd_old) + { + gpr_status[rd_old]._is_link = 1; + gpr_status[rd_new]._is_link = 0; + gpr_status[rd_new]._is_valid = 1; + } + else + { + gpr_status[rd_old]._is_link = 0; + gpr_status[rd_new]._is_valid = 1; + } } if (write_re) { - spr_status[re_old]._is_link = 0; - spr_status[re_new]._is_valid = 1; - } + if (restore_re_old) + { + spr_status[re_old]._is_link = 1; + spr_status[re_new]._is_link = 0; + spr_status[re_new]._is_valid = 1; + } + else + { + spr_status[re_old]._is_link = 0; + spr_status[re_new]._is_valid = 1; + } + } } @@ -647,7 +685,9 @@ delete [] in_RETIRE_NUM_REG_RC_PHY ; delete [] in_RETIRE_WRITE_RD ; + delete [] in_RETIRE_RESTORE_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; delete [] in_RETIRE_WRITE_RE ; + delete [] in_RETIRE_RESTORE_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Parameters.h (revision 88) @@ -36,6 +36,6 @@ public : uint32_t _size_counter ; - public : uint32_t _size_general_register ; - public : uint32_t _size_special_register ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; public : uint32_t _max_reader ; @@ -63,8 +63,12 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_counter ); + uint32_t size_counter , + bool is_toplevel=false + ); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h (revision 88) @@ -1,3 +1,3 @@ -#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_register_translation_unit_stat_list_unit_Stat_List_unit_h + #ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_register_translation_unit_stat_list_unit_Stat_List_unit_h #define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_register_translation_unit_stat_list_unit_Stat_List_unit_h @@ -86,7 +86,9 @@ public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RC_PHY ;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RD ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_RESTORE_RD_PHY_OLD;//[nb_inst_retire] public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_PHY_OLD;//[nb_inst_retire] public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_PHY_NEW;//[nb_inst_retire] public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RE ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_RESTORE_RE_PHY_OLD;//[nb_inst_retire] public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_OLD;//[nb_inst_retire] public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_NEW;//[nb_inst_retire] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Types.h (revision 88) @@ -23,8 +23,8 @@ class stat_list_entry_t { - private : bool _is_free ; // set = is present in free list - private : bool _is_link ; // set = is present in rat - private : bool _is_valid; // set = an instruction have write in this register - private : uint32_t _counter ; // number of register that must read this register + public : bool _is_free ; // set = is present in free list + public : bool _is_link ; // set = is present in rat + public : bool _is_valid; // set = an instruction have write in this register + public : uint32_t _counter ; // number of register that must read this register public : stat_list_entry_t (void) {}; @@ -55,11 +55,21 @@ } - public : void retire_write_old (void) + public : void retire_write_old (bool restore_old) { - _is_link = 0; + if (not restore_old) + { + _is_link = 0; + } + // else nothing } - public : void retire_write_new (void) + public : void retire_write_new (bool restore_old) { + if (restore_old) + { + _is_link = 0; + } + + // in all case _is_valid = 1; } @@ -79,17 +89,17 @@ return ((_is_free == 0) and (_is_link == 0) and - (_is_valid == 1) and +// (_is_valid == 1) and // if is_link <- 0, then retire_write_old or reset (_counter == 0)); } - public : friend std::ostream& operator<< (std::ostream& output_stream, + public : friend std::ostream& operator<< (std::ostream& output, stat_list_entry_t & x) { - output_stream << x._is_free << " " - << x._is_link << " " - << x._is_valid << " " - << x._counter; + output << x._is_free << " " + << x._is_link << " " + << x._is_valid << " " + << x._counter; - return output_stream; + return output; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Parameters.cpp (revision 88) @@ -29,5 +29,6 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_counter ) + uint32_t size_counter , + bool is_toplevel) { log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); @@ -43,7 +44,4 @@ _size_counter = size_counter ; - _size_general_register = log2(nb_general_register); - _size_special_register = log2(nb_special_register); - _max_reader = 1< Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Stat_List_unit,FUNCTION,"Allocation"); @@ -48,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Stat_List_unit,FUNCTION,"Allocation of statistics"); @@ -57,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -67,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { // Constant @@ -90,5 +95,5 @@ SC_METHOD (genMoore); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register # ifdef SYSTEMCASS_SPECIFIC @@ -100,5 +105,5 @@ SC_METHOD (genMealy); dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); + sensitive << (*(in_CLOCK)).neg(); // need internal register for (uint32_t i=0; i<_param->_nb_inst_insert; i++) sensitive << (*(in_INSERT_READ_RA [i])) @@ -135,5 +140,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Stat_List_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_allocation.cpp (revision 88) @@ -87,7 +87,9 @@ ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_RESTORE_RD_PHY_OLD,"restore_rd_phy_old",Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_OLD,"num_reg_rd_phy_old",Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_NEW,"num_reg_rd_phy_new",Tgeneral_address_t,_param->_size_general_register); ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_RESTORE_RE_PHY_OLD,"restore_re_phy_old",Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD,"num_reg_re_phy_old",Tspecial_address_t,_param->_size_special_register); ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW,"num_reg_re_phy_new",Tspecial_address_t,_param->_size_special_register); @@ -112,5 +114,7 @@ } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { gpr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; spr_stat_list = new stat_list_entry_t * [_param->_nb_bank]; @@ -128,7 +132,11 @@ internal_PUSH_SPR_VAL = new Tcontrol_t [_param->_nb_reg_free]; internal_PUSH_SPR_NUM_BANK = new uint32_t [_param->_nb_reg_free]; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_deallocation.cpp (revision 88) @@ -24,5 +24,5 @@ log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -51,7 +51,9 @@ delete [] in_RETIRE_NUM_REG_RC_PHY ; delete [] in_RETIRE_WRITE_RD ; + delete [] in_RETIRE_RESTORE_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; delete [] in_RETIRE_WRITE_RE ; + delete [] in_RETIRE_RESTORE_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; @@ -64,15 +66,20 @@ delete [] in_PUSH_SPR_ACK ; delete [] out_PUSH_SPR_NUM_REG ; + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete [] gpr_stat_list; + delete [] spr_stat_list; + + delete [] internal_INSERT_ACK ; + delete [] internal_RETIRE_ACK ; + delete [] internal_PUSH_GPR_VAL ; + delete [] internal_PUSH_GPR_NUM_BANK; + delete [] internal_PUSH_SPR_VAL ; + delete [] internal_PUSH_SPR_NUM_BANK; } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] gpr_stat_list; - delete [] spr_stat_list; - - delete [] internal_INSERT_ACK ; - delete [] internal_RETIRE_ACK ; - delete [] internal_PUSH_GPR_VAL ; - delete [] internal_PUSH_GPR_NUM_BANK; - delete [] internal_PUSH_SPR_VAL ; - delete [] internal_PUSH_SPR_NUM_BANK; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_end_cycle.cpp (revision 88) @@ -26,5 +26,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -32,5 +33,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp (revision 88) @@ -23,5 +23,6 @@ void Stat_List_unit::genMealy (void) { - log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); + log_begin(Stat_List_unit,FUNCTION); + log_function(Stat_List_unit,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_insert; i++) @@ -57,5 +58,5 @@ } - log_printf(FUNC,Stat_List_unit,FUNCTION,"End"); + log_end(Stat_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMoore.cpp (revision 88) @@ -23,5 +23,6 @@ void Stat_List_unit::genMoore (void) { - log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); + log_begin(Stat_List_unit,FUNCTION); + log_function(Stat_List_unit,FUNCTION,_name.c_str()); uint32_t gpr_ptr = internal_GPR_PTR_FREE; @@ -69,5 +70,5 @@ } - log_printf(FUNC,Stat_List_unit,FUNCTION,"End"); + log_end(Stat_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_transition.cpp (revision 88) @@ -23,5 +23,6 @@ void Stat_List_unit::transition (void) { - log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); + log_begin(Stat_List_unit,FUNCTION); + log_function(Stat_List_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -121,9 +122,10 @@ if (PORT_READ(in_RETIRE_WRITE_RD [i])) { + Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RD_PHY_OLD [i]); { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_write_old(); + gpr_stat_list [bank][reg].retire_write_old(restore_old); } { @@ -131,5 +133,5 @@ uint32_t bank = num_reg >> _param->_shift_gpr; uint32_t reg = num_reg & _param->_mask_gpr ; - gpr_stat_list [bank][reg].retire_write_new(); + gpr_stat_list [bank][reg].retire_write_new(restore_old); } } @@ -137,9 +139,10 @@ if (PORT_READ(in_RETIRE_WRITE_RE [i])) { + Tcontrol_t restore_old = PORT_READ(in_RETIRE_RESTORE_RE_PHY_OLD [i]); { Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].retire_write_old(); + spr_stat_list [bank][reg].retire_write_old(restore_old); } { @@ -147,5 +150,5 @@ uint32_t bank = num_reg >> _param->_shift_spr; uint32_t reg = num_reg & _param->_mask_spr ; - spr_stat_list [bank][reg].retire_write_new(); + spr_stat_list [bank][reg].retire_write_new(restore_old); } } @@ -171,28 +174,29 @@ internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1; } - -// log_printf(TRACE,Stat_List_unit,FUNCTION,"Print gpr_stat_list :"); -// for (uint32_t i=0; i<_param->_nb_bank; i++) -// { -// log_printf(TRACE,Stat_List_unit,FUNCTION," * Bank : %d",i); -// for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) -// { -// std::ostringstream str; -// str << gpr_stat_list [i][j]; -// log_printf(TRACE,Stat_List_unit,FUNCTION," [%d] %s",j,str.str().c_str()); - -// } -// } -// log_printf(TRACE,Stat_List_unit,FUNCTION,"Print spr_stat_list :"); -// for (uint32_t i=0; i<_param->_nb_bank; i++) -// { -// log_printf(TRACE,Stat_List_unit,FUNCTION," * Bank : %d",i); -// for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) -// { -// std::ostringstream str; -// str << spr_stat_list [i][j]; -// log_printf(TRACE,Stat_List_unit,FUNCTION," [%d] %s",j,str.str().c_str()); -// } -// } + + +#if (DEBUG >= DEBUG_TRACE) + log_printf(TRACE,Stat_List_unit,FUNCTION," * Dump Stat List"); + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) + log_printf(TRACE,Stat_List_unit,FUNCTION," * GPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", + i, + j, + (i<<_param->_shift_gpr)|j, + gpr_stat_list[i][j]._is_free, + gpr_stat_list[i][j]._is_link, + gpr_stat_list[i][j]._is_valid, + gpr_stat_list[i][j]._counter); + for (uint32_t i=0; i<_param->_nb_bank; i++) + for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) + log_printf(TRACE,Stat_List_unit,FUNCTION," * SPR[%.4d][%.5d] (%.5d) - free %.1d, link %.1d, valid %.1d, counter %.4d", + i, + j, + (i<<_param->_shift_spr)|j, + spr_stat_list[i][j]._is_free, + spr_stat_list[i][j]._is_link, + spr_stat_list[i][j]._is_valid, + spr_stat_list[i][j]._counter); +#endif #if defined(STATISTICS) or defined(VHDL_TESTBENCH) @@ -200,5 +204,5 @@ #endif - log_printf(FUNC,Stat_List_unit,FUNCTION,"End"); + log_end(Stat_List_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h (revision 88) @@ -40,11 +40,11 @@ public : uint32_t _size_read_counter ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_context_id ; - public : uint32_t _size_general_register ; - public : uint32_t _size_special_register ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; - public : uint32_t _have_port_context_id ; - public : uint32_t _have_port_front_end_id; +//public : uint32_t _have_port_context_id ; +//public : uint32_t _have_port_front_end_id; public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::dependency_checking_unit:: Parameters * _param_dependency_checking_unit; @@ -62,7 +62,10 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter ); + uint32_t size_read_counter , + bool is_toplevel=false); // public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Parameters.cpp (revision 88) @@ -28,5 +28,6 @@ uint32_t nb_reg_free , uint32_t nb_bank , - uint32_t size_read_counter ) + uint32_t size_read_counter , + bool is_toplevel) { log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin"); @@ -42,15 +43,8 @@ _size_read_counter = size_read_counter ; - uint32_t max_nb_context = max(nb_context, nb_front_end); + uint32_t size_general_register = log2(nb_general_register); + uint32_t size_special_register = log2(nb_special_register); + uint32_t max_nb_context = max(nb_context, nb_front_end); - _size_front_end_id = log2(nb_front_end ); - _size_context_id = log2(max_nb_context ); - _size_general_register = log2(nb_general_register); - _size_special_register = log2(nb_special_register); - - _have_port_front_end_id = _size_front_end_id>0; - _have_port_context_id = _size_context_id >0; - - uint32_t nb_thread = 0; for (uint32_t i=0; i0; + _have_port_context_id = _size_context_id >0; + + copy(); + } + log_printf(FUNC,Register_translation_unit,FUNCTION,"End"); }; @@ -124,4 +135,19 @@ }; +#undef FUNCTION +#define FUNCTION "Register_translation_unit::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin"); + + COPY(_param_dependency_checking_unit); + COPY(_param_free_list_unit); + COPY(_param_register_address_translation_unit); + COPY(_param_stat_list_unit); + COPY(_param_register_translation_unit_glue); + + log_printf(FUNC,Register_translation_unit,FUNCTION,"End"); + }; + }; // end namespace register_translation_unit }; // end namespace rename_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin"); +#if DEBUG_Register_translation_unit == true + log_printf(INFO,Register_translation_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Register_translation_unit,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_translation_unit,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Register_translation_unit,FUNCTION,"Method - transition"); @@ -90,5 +96,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Register_translation_unit,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 88) @@ -130,6 +130,6 @@ { name = _name+"_dependency_checking_unit"; - std::cout << "Create : " << name << std::endl; - + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + _component_dependency_checking_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::dependency_checking_unit::Dependency_checking_unit (name.c_str() @@ -149,5 +149,5 @@ { name = _name+"_free_list_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_free_list_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::free_list_unit::Free_List_unit @@ -168,5 +168,5 @@ { name = _name+"_register_address_translation_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_register_address_translation_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_address_translation_unit::Register_Address_Translation_unit @@ -187,5 +187,5 @@ { name = _name+"_stat_list_unit"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_stat_list_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::stat_list_unit::Stat_List_unit @@ -206,5 +206,5 @@ { name = _name+"_register_translation_unit_glue"; - std::cout << "Create : " << name << std::endl; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); _component_register_translation_unit_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Register_translation_unit_Glue @@ -225,5 +225,214 @@ // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ std::string src,dest; + + // =================================================================== + // =====[ register_address_translation_unit ]========================= + // =================================================================== + { + src = _name+"_register_address_translation_unit"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(i) + dest,"rename_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_VAL" , + dest, "in_RENAME_"+toString(i)+"_VAL" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_FRONT_END_ID" , + dest, "in_RENAME_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_CONTEXT_ID" , + dest, "in_RENAME_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RA_LOG" , + dest, "in_RENAME_"+toString(i)+"_NUM_REG_RA_LOG" ); + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RB_LOG" , + dest, "in_RENAME_"+toString(i)+"_NUM_REG_RB_LOG" ); + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RC_LOG" , + dest, "in_RENAME_"+toString(i)+"_NUM_REG_RC_LOG" ); + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RD_LOG" , + dest, "in_RENAME_"+toString(i)+"_NUM_REG_RD_LOG" ); + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RE_LOG" , + dest, "in_RENAME_"+toString(i)+"_NUM_REG_RE_LOG" ); + + dest = _name+"_register_translation_unit_glue"; + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_ACK", + dest, "in_INSERT_"+toString(i)+"_RAT_RENAME_ACK"); + + dest = _name+"_dependency_checking_unit"; + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RA_PHY" , + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RB_PHY" , + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RC_PHY" , + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name+"_register_translation_unit_glue"; +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(i) + dest,"rename_in_"+toString(i)); +#endif + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_VAL", + dest,"out_INSERT_"+toString(i)+"_RAT_INSERT_VAL"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_ACK", + dest, "in_INSERT_"+toString(i)+"_RAT_INSERT_ACK"); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RD" , + dest,"out_INSERT_"+toString(i)+"_RAT_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RE" , + dest,"out_INSERT_"+toString(i)+"_RAT_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_LOG", + dest,"out_INSERT_"+toString(i)+"_RAT_NUM_REG_RD_LOG"); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_LOG", + dest,"out_INSERT_"+toString(i)+"_RAT_NUM_REG_RE_LOG"); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY", + dest,"out_INSERT_"+toString(i)+"_RAT_NUM_REG_RD_PHY_NEW"); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY", + dest,"out_INSERT_"+toString(i)+"_RAT_NUM_REG_RE_PHY_NEW"); + } + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i) + dest,"retire_"+toString(i)); +#endif + + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_FRONT_END_ID" , + dest, "in_RETIRE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , + dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_EVENT_STATE" , + dest, "in_RETIRE_"+toString(i)+"_EVENT_STATE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RD" , + dest, "in_RETIRE_"+toString(i)+"_WRITE_RD" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RE" , + dest, "in_RETIRE_"+toString(i)+"_WRITE_RE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + + dest = _name+"_register_translation_unit_glue"; + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL" , + dest,"out_RETIRE_"+toString(i)+"_RAT_VAL" ); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK" , + dest, "in_RETIRE_"+toString(i)+"_RAT_ACK" ); + + dest = _name+"_stat_list_unit"; + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE_RD_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_RESTORE_RD_PHY_OLD"); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_RESTORE_RE_PHY_OLD"); + } + } + // =================================================================== + // =====[ free_list_unit ]============================================ + // =================================================================== + { + src = _name+"_free_list_unit"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ interface : "pop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"pop_"+toString(i) + dest,"rename_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" , + dest,"in_RENAME_"+toString(i)+"_WRITE_RD"); + PORT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" , + dest,"in_RENAME_"+toString(i)+"_WRITE_RE"); + + dest = _name+"_register_translation_unit_glue"; + COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_VAL" , + dest,"out_INSERT_"+toString(i)+"_FREE_LIST_VAL" ); + COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_ACK" , + dest, "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" ); + + dest = _name+"_dependency_checking_unit"; + + COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_GPR_NUM_REG", + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); + COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_SPR_NUM_REG", + dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); + } + + // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_reg_free; i++) + { + dest = _name+"_stat_list_unit"; +#ifdef POSITION + _component->interface_map (src ,"push_gpr_"+toString(i) + dest,"push_gpr_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_PUSH_GPR_"+toString(i)+"_VAL" , + dest,"out_PUSH_GPR_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_PUSH_GPR_"+toString(i)+"_ACK" , + dest, "in_PUSH_GPR_"+toString(i)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_PUSH_GPR_"+toString(i)+"_NUM_REG", + dest,"out_PUSH_GPR_"+toString(i)+"_NUM_REG"); + +#ifdef POSITION + _component->interface_map (src ,"push_spr_"+toString(i) + dest,"push_spr_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_PUSH_SPR_"+toString(i)+"_VAL" , + dest,"out_PUSH_SPR_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_PUSH_SPR_"+toString(i)+"_ACK" , + dest, "in_PUSH_SPR_"+toString(i)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_PUSH_SPR_"+toString(i)+"_NUM_REG", + dest,"out_PUSH_SPR_"+toString(i)+"_NUM_REG"); + } + } + + // =================================================================== // =====[ dependency_checking_unit ]================================== @@ -231,5 +440,5 @@ { src = _name+"_dependency_checking_unit"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -252,6 +461,6 @@ #endif -// PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_VAL" ,dest,); -// PORT_MAP(_component,src ,"out_RENAME_IN_"+toString(i)+"_ACK" ,dest,); +// // PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_VAL" ,dest,); +// // PORT_MAP(_component,src ,"out_RENAME_IN_"+toString(i)+"_ACK" ,dest,); if (_param->_have_port_front_end_id) PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_FRONT_END_ID" , @@ -280,24 +489,13 @@ PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_LOG" , dest, "in_RENAME_"+toString(i)+"_NUM_REG_RE_LOG" ); - - dest = _name+"_register_address_translation_unit"; - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RA_PHY" , - dest,"out_RENAME_"+toString(i)+"_NUM_REG_RA_PHY" ); - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RB_PHY" , - dest,"out_RENAME_"+toString(i)+"_NUM_REG_RB_PHY" ); - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RC_PHY" , - dest,"out_RENAME_"+toString(i)+"_NUM_REG_RC_PHY" ); - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_OLD", - dest,"out_RENAME_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_OLD", - dest,"out_RENAME_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + // in_RENAME_IN_NUM_REG_RA_PHY - register_address_translation_unit + // in_RENAME_IN_NUM_REG_RB_PHY - register_address_translation_unit + // in_RENAME_IN_NUM_REG_RC_PHY - register_address_translation_unit + // in_RENAME_IN_NUM_REG_RD_PHY_OLD - register_address_translation_unit + // in_RENAME_IN_NUM_REG_RE_PHY_OLD - register_address_translation_unit - dest = _name+"_free_list_unit"; - - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_NEW", - dest,"out_POP_"+toString(i)+"_GPR_NUM_REG"); - PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_NEW", - dest,"out_POP_"+toString(i)+"_SPR_NUM_REG"); + // in_RENAME_IN_NUM_REG_RD_PHY_NEW - free_list_unit + // in_RENAME_IN_NUM_REG_RE_PHY_NEW - free_list_unit } @@ -311,8 +509,4 @@ #endif -// PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_VAL" , -// dest,"out_INSERT_"+toString(i)+"_VAL" ); -// PORT_MAP(_component,src , "in_RENAME_OUT_"+toString(i)+"_ACK" , -// dest, "in_INSERT_"+toString(i)+"_ACK" ); if (_param->_have_port_front_end_id) PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_FRONT_END_ID" , @@ -321,47 +515,55 @@ PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_CONTEXT_ID" , dest,"out_INSERT_"+toString(i)+"_CONTEXT_ID" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RA" , - dest,"out_INSERT_"+toString(i)+"_READ_RA" ); PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RA_LOG" , dest,"out_INSERT_"+toString(i)+"_NUM_REG_RA_LOG" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RA_PHY" , - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RB" , - dest,"out_INSERT_"+toString(i)+"_READ_RB" ); PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RB_LOG" , dest,"out_INSERT_"+toString(i)+"_NUM_REG_RB_LOG" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RB_PHY" , - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RC" , - dest,"out_INSERT_"+toString(i)+"_READ_RC" ); PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RC_LOG" , dest,"out_INSERT_"+toString(i)+"_NUM_REG_RC_LOG" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RC_PHY" , - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RD" , - dest,"out_INSERT_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_LOG" , - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_LOG" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_OLD", - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RE" , - dest,"out_INSERT_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_LOG" , - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_LOG" ); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_OLD", - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); - PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", - dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); - } + +// PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_VAL" , +// dest,"out_INSERT_"+toString(i)+"_VAL" ); +// PORT_MAP(_component,src , "in_RENAME_OUT_"+toString(i)+"_ACK" , +// dest, "in_INSERT_"+toString(i)+"_ACK" ); + + dest = _name+"_register_translation_unit_glue"; + + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RA" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_READ_RA" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RA_PHY" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RB" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_READ_RB" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RB_PHY" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RC" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_READ_RC" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RC_PHY" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RD" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_WRITE_RD" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_LOG" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RD_LOG" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RE" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_WRITE_RE" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_LOG" , + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RE_LOG" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", + dest, "in_INSERT_"+toString(i)+"_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW"); + } } // =================================================================== - // =====[ free_list_unit ]============================================ + // =====[ stat_list_unit ]============================================ // =================================================================== { - src = _name+"_free_list_unit"; - std::cout << "Instance : " << src << std::endl; + src = _name+"_stat_list_unit"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -375,243 +577,37 @@ } - // ~~~~~[ interface : "pop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"pop_"+toString(i) - dest,"rename_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" , - dest,"in_RENAME_"+toString(i)+"_WRITE_RD"); - PORT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" , - dest,"in_RENAME_"+toString(i)+"_WRITE_RE"); - - dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src , "in_POP_"+toString(i)+"_VAL" , - dest,"out_INSERT_"+toString(i)+"_FREE_LIST_VAL" ); - PORT_MAP(_component,src ,"out_POP_"+toString(i)+"_ACK" , - dest, "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" ); - - dest = _name+"_dependency_checking_unit"; - - PORT_MAP(_component,src ,"out_POP_"+toString(i)+"_GPR_NUM_REG", - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); - PORT_MAP(_component,src ,"out_POP_"+toString(i)+"_SPR_NUM_REG", - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); - } - // ~~~~~[ interface : "push_gpr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // ~~~~~[ interface : "push_spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_reg_free; i++) - { - dest = _name+"_stat_list_unit"; -#ifdef POSITION - _component->interface_map (src ,"push_gpr_"+toString(i) - dest,"push_gpr_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_PUSH_GPR_"+toString(i)+"_VAL" , - dest,"out_PUSH_GPR_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src ,"out_PUSH_GPR_"+toString(i)+"_ACK" , - dest, "in_PUSH_GPR_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src , "in_PUSH_GPR_"+toString(i)+"_NUM_REG", - dest,"out_PUSH_GPR_"+toString(i)+"_NUM_REG"); - -#ifdef POSITION - _component->interface_map (src ,"push_spr_"+toString(i) - dest,"push_spr_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_PUSH_SPR_"+toString(i)+"_VAL" , - dest,"out_PUSH_SPR_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src ,"out_PUSH_SPR_"+toString(i)+"_ACK" , - dest, "in_PUSH_SPR_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src , "in_PUSH_SPR_"+toString(i)+"_NUM_REG", - dest,"out_PUSH_SPR_"+toString(i)+"_NUM_REG"); - } - } - - // =================================================================== - // =====[ register_address_translation_unit ]========================= - // =================================================================== - { - src = _name+"_register_address_translation_unit"; - std::cout << "Instance : " << src << std::endl; - - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"", - dest,""); -#endif - PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); - PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); - } - - // ~~~~~[ Interface "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"rename_"+toString(i) - dest,"rename_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_VAL" , - dest, "in_RENAME_"+toString(i)+"_VAL" ); - if (_param->_have_port_front_end_id) - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_FRONT_END_ID" , - dest, "in_RENAME_"+toString(i)+"_FRONT_END_ID" ); - if (_param->_have_port_context_id) - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_CONTEXT_ID" , - dest, "in_RENAME_"+toString(i)+"_CONTEXT_ID" ); - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RA_LOG" , - dest, "in_RENAME_"+toString(i)+"_NUM_REG_RA_LOG" ); - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RB_LOG" , - dest, "in_RENAME_"+toString(i)+"_NUM_REG_RB_LOG" ); - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RC_LOG" , - dest, "in_RENAME_"+toString(i)+"_NUM_REG_RC_LOG" ); - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RD_LOG" , - dest, "in_RENAME_"+toString(i)+"_NUM_REG_RD_LOG" ); - PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_NUM_REG_RE_LOG" , - dest, "in_RENAME_"+toString(i)+"_NUM_REG_RE_LOG" ); - - dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_ACK", - dest, "in_INSERT_"+toString(i)+"_RAT_RENAME_ACK"); - - dest = _name+"_dependency_checking_unit"; - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RA_PHY" , - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RA_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RB_PHY" , - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RB_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RC_PHY" , - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RC_PHY" ); - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RD_PHY_OLD", - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); - PORT_MAP(_component,src ,"out_RENAME_"+toString(i)+"_NUM_REG_RE_PHY_OLD", - dest, "in_RENAME_IN_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); - } - // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ for (uint32_t i=0; i<_param->_nb_inst_insert; i++) { - dest = _name+"_dependency_checking_unit"; -#ifdef POSITION - _component->interface_map (src ,"rename_"+toString(i) - dest,"rename_in_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RD" , - dest,"out_RENAME_OUT_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RE" , - dest,"out_RENAME_OUT_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_LOG", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_LOG"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_LOG", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_LOG"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); - dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_VAL", - dest,"out_INSERT_"+toString(i)+"_RAT_INSERT_VAL"); - PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_ACK", - dest, "in_INSERT_"+toString(i)+"_RAT_INSERT_ACK"); - } - - // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_inst_retire; i++) - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"retire_"+toString(i) - dest,"retire_"+toString(i)); -#endif - - if (_param->_have_port_front_end_id) - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_FRONT_END_ID" , - dest, "in_RETIRE_"+toString(i)+"_FRONT_END_ID" ); - if (_param->_have_port_context_id) - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , - dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_EVENT_STATE" , - dest, "in_RETIRE_"+toString(i)+"_EVENT_STATE" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RD" , - dest, "in_RETIRE_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RE" , - dest, "in_RETIRE_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" , - dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" , - dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD", - dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD", - dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); - - dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL" , - dest,"out_RETIRE_"+toString(i)+"_RAT_VAL" ); - PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK" , - dest, "in_RETIRE_"+toString(i)+"_RAT_ACK" ); - } - } - - // =================================================================== - // =====[ stat_list_unit ]============================================ - // =================================================================== - { - src = _name+"_stat_list_unit"; - std::cout << "Instance : " << src << std::endl; - - { - dest = _name; -#ifdef POSITION - _component->interface_map (src ,"", - dest,""); -#endif - PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); - PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); - } - - // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - for (uint32_t i=0; i<_param->_nb_inst_insert; i++) - { - dest = _name+"_dependency_checking_unit"; #ifdef POSITION _component->interface_map (src ,"insert_"+toString(i) - dest,"rename_out_"+toString(i)); -#endif - - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RA" , - dest,"out_RENAME_OUT_"+toString(i)+"_READ_RA" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" , - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RA_PHY" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RB" , - dest,"out_RENAME_OUT_"+toString(i)+"_READ_RB" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" , - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RB_PHY" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RC" , - dest,"out_RENAME_OUT_"+toString(i)+"_READ_RC" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" , - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RC_PHY" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RD" , - dest,"out_RENAME_OUT_"+toString(i)+"_WRITE_RD" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RE" , - dest,"out_RENAME_OUT_"+toString(i)+"_WRITE_RE" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", - dest,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); - - dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_VAL" , - dest,"out_INSERT_"+toString(i)+"_STAT_LIST_VAL"); - PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_ACK" , - dest, "in_INSERT_"+toString(i)+"_STAT_LIST_ACK" ); + dest,"insert_stat_list_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_VAL" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_VAL"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_ACK" , + dest, "in_INSERT_"+toString(i)+"_STAT_LIST_ACK" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RA" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_READ_RA" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RB" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_READ_RB" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_READ_RC" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_READ_RC" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RD" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RD_PHY_NEW"); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_WRITE_RE" , + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_STAT_LIST_NUM_REG_RE_PHY_NEW"); } @@ -650,9 +646,12 @@ dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); + // in_RETIRE_RESTORE_RD_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RD_PHY_OLD + // in_RETIRE_RESTORE_RE_PHY_OLD - register_address_translation_unit.out_RETIRE_RESTORE_RE_PHY_OLD + dest = _name+"_register_translation_unit_glue"; - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL", - dest,"out_RETIRE_"+toString(i)+"_STAT_LIST_VAL"); - PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK", - dest, "in_RETIRE_"+toString(i)+"_STAT_LIST_ACK"); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL", + dest,"out_RETIRE_"+toString(i)+"_STAT_LIST_VAL"); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK", + dest, "in_RETIRE_"+toString(i)+"_STAT_LIST_ACK"); } @@ -667,10 +666,7 @@ #endif - PORT_MAP(_component,src ,"out_PUSH_GPR_"+toString(i)+"_VAL" , - dest, "in_PUSH_GPR_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_PUSH_GPR_"+toString(i)+"_ACK" , - dest,"out_PUSH_GPR_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src ,"out_PUSH_GPR_"+toString(i)+"_NUM_REG", - dest, "in_PUSH_GPR_"+toString(i)+"_NUM_REG"); + //out_PUSH_GPR_VAL - free_list_unit + // in_PUSH_GPR_ACK - free_list_unit + //out_PUSH_GPR_NUM_REG - free_list_unit #ifdef POSITION @@ -679,10 +675,7 @@ #endif - PORT_MAP(_component,src ,"out_PUSH_SPR_"+toString(i)+"_VAL" , - dest, "in_PUSH_SPR_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_PUSH_SPR_"+toString(i)+"_ACK" , - dest,"out_PUSH_SPR_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src ,"out_PUSH_SPR_"+toString(i)+"_NUM_REG", - dest, "in_PUSH_SPR_"+toString(i)+"_NUM_REG"); + //out_PUSH_SPR_VAL - free_list_unit + // in_PUSH_SPR_ACK - free_list_unit + //out_PUSH_SPR_NUM_REG - free_list_unit } } @@ -693,5 +686,5 @@ { src = _name+"_register_translation_unit_glue"; - std::cout << "Instance : " << src << std::endl; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); { @@ -723,23 +716,73 @@ dest, "in_INSERT_"+toString(i)+"_ACK" ); - dest = _name+"_register_address_translation_unit"; - PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_RAT_INSERT_VAL", - dest, "in_INSERT_"+toString(i)+"_VAL"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_RAT_RENAME_ACK", - dest,"out_RENAME_"+toString(i)+"_ACK"); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_RAT_INSERT_ACK", - dest,"out_INSERT_"+toString(i)+"_ACK"); - - dest = _name+"_free_list_unit"; - PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_FREE_LIST_VAL" , - dest, "in_POP_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" , - dest,"out_POP_"+toString(i)+"_ACK" ); - - dest = _name+"_stat_list_unit"; - PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_STAT_LIST_VAL" , - dest, "in_INSERT_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_STAT_LIST_ACK" , - dest,"out_INSERT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RA" , + dest,"out_INSERT_"+toString(i)+"_READ_RA" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RB" , + dest,"out_INSERT_"+toString(i)+"_READ_RB" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RC" , + dest,"out_INSERT_"+toString(i)+"_READ_RC" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_WRITE_RD" , + dest,"out_INSERT_"+toString(i)+"_WRITE_RD" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_WRITE_RE" , + dest,"out_INSERT_"+toString(i)+"_WRITE_RE" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); + + // out_INSERT_RAT_INSERT_VAL - register_address_translation_unit + // in_INSERT_RAT_RENAME_ACK - register_address_translation_unit + // in_INSERT_RAT_INSERT_ACK - register_address_translation_unit + // out_INSERT_FREE_LIST_VAL - free_list_unit + // in_INSERT_FREE_LIST_ACK - free_list_unit + // out_INSERT_STAT_LIST_VAL - stat_list_unit + // in_INSERT_STAT_LIST_ACK - stat_list_unit + + // in_INSERT_DEPENDENCY_CHECKING_READ_RA - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_READ_RB - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_READ_RC - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_WRITE_RD - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_WRITE_RE - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD - dependency_checking_unit + // in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW - dependency_checking_unit + + // out_INSERT_STAT_LIST_READ_RA - stat_list_unit + // out_INSERT_STAT_LIST_NUM_REG_RA_PHY - stat_list_unit + // out_INSERT_STAT_LIST_READ_RB - stat_list_unit + // out_INSERT_STAT_LIST_NUM_REG_RB_PHY - stat_list_unit + // out_INSERT_STAT_LIST_READ_RC - stat_list_unit + // out_INSERT_STAT_LIST_NUM_REG_RC_PHY - stat_list_unit + // out_INSERT_STAT_LIST_WRITE_RD - stat_list_unit + // out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW - stat_list_unit + // out_INSERT_STAT_LIST_WRITE_RE - stat_list_unit + // out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW - stat_list_unit + + // out_INSERT_RAT_WRITE_RD - register_address_translation_unit + // out_INSERT_RAT_NUM_REG_RD_LOG - register_address_translation_unit + // out_INSERT_RAT_NUM_REG_RD_PHY_NEW - register_address_translation_unit + // out_INSERT_RAT_WRITE_RE - register_address_translation_unit + // out_INSERT_RAT_NUM_REG_RE_LOG - register_address_translation_unit + // out_INSERT_RAT_NUM_REG_RE_PHY_NEW - register_address_translation_unit } @@ -758,15 +801,8 @@ dest,"out_RETIRE_"+toString(i)+"_ACK" ); - dest = _name+"_register_address_translation_unit"; - PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RAT_VAL" , - dest, "in_RETIRE_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_RAT_ACK" , - dest,"out_RETIRE_"+toString(i)+"_ACK" ); - - dest = _name+"_stat_list_unit"; - PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_STAT_LIST_VAL", - dest, "in_RETIRE_"+toString(i)+"_VAL"); - PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_STAT_LIST_ACK", - dest,"out_RETIRE_"+toString(i)+"_ACK"); + // out_RETIRE_RAT_VAL - register_address_translation_unit + // in_RETIRE_RAT_ACK - register_address_translation_unit + // out_RETIRE_STAT_LIST_VAL - stat_list_unit + // in_RETIRE_STAT_LIST_ACK - stat_list_unit } } @@ -774,8 +810,11 @@ // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - _component->test_map(); - -#ifdef POSITION - _component->generate_file(); +#if (DEBUG_Register_translation_unit == true) + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Register_translation_unit,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/Makefile.deps (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/Makefile.deps (revision 88) @@ -13,15 +13,20 @@ include $(DIR_MORPHEO)/Behavioural/Makefile.deps endif +ifndef Priority +include $(DIR_MORPHEO)/Behavioural/Generic/Priority/Makefile.deps +endif #-----[ Directory ]---------------------------------------- -Rename_select_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select +Rename_select_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select #-----[ Library ]------------------------------------------ -Rename_select_LIBRARY = -lRename_select \ +Rename_select_LIBRARY = -lRename_select \ + $(Priority_LIBRARY) \ $(Behavioural_LIBRARY) -Rename_select_DIR_LIBRARY = -L$(Rename_select_DIR)/lib \ +Rename_select_DIR_LIBRARY = -L$(Rename_select_DIR)/lib \ + $(Priority_DIR_LIBRARY) \ $(Behavioural_DIR_LIBRARY) @@ -31,4 +36,5 @@ @\ $(MAKE) Behavioural_library; \ + $(MAKE) Priority_library; \ $(MAKE) --directory=$(Rename_select_DIR) --makefile=Makefile; @@ -36,3 +42,4 @@ @\ $(MAKE) Behavioural_library_clean; \ + $(MAKE) Priority_library_clean; \ $(MAKE) --directory=$(Rename_select_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Rename_select_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/main.cpp (revision 88) @@ -16,4 +16,6 @@ err (_(" * nb_front_end (uint32_t )\n")); err (_(" * nb_context [nb_front_end] (uint32_t )\n")); +// err (_(" * size_nb_front_end_id (uint32_t )\n")); +// err (_(" * size_nb_context_id (uint32_t )\n")); err (_(" * max_branch_speculated (uint32_t )\n")); err (_(" * size_general_data (uint32_t )\n")); @@ -49,4 +51,6 @@ _nb_context [i] = atoi(argv[x++]); +// uint32_t _size_front_end_id = atoi(argv[x++]); +// uint32_t _size_context_id = atoi(argv[x++]); uint32_t _max_branch_speculated= atoi(argv[x++]); uint32_t _size_general_data = atoi(argv[x++]); @@ -66,4 +70,6 @@ (_nb_front_end , _nb_context , +// _size_front_end_id , +// _size_context_id , _max_branch_speculated, _size_general_data , @@ -72,5 +78,7 @@ _nb_front_end_select , _priority , - _load_balancing ); + _load_balancing , + true // is_toplevel + ); msg(_("%s"),param->print(1).c_str()); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Rename_select * _Rename_select = new Rename_select (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -40,25 +50,28 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC2_SC_SIGNAL( in_RENAME_IN_VAL ," in_RENAME_IN_VAL ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL(out_RENAME_IN_ACK ,"out_RENAME_IN_ACK ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_FRONT_END_ID ," in_RENAME_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_CONTEXT_ID ," in_RENAME_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_DEPTH ," in_RENAME_IN_DEPTH ",Tdepth_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_TYPE ," in_RENAME_IN_TYPE ",Ttype_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_OPERATION ," in_RENAME_IN_OPERATION ",Toperation_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RA ," in_RENAME_IN_READ_RA ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RA ," in_RENAME_IN_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RB ," in_RENAME_IN_READ_RB ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RB ," in_RENAME_IN_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RC ," in_RENAME_IN_READ_RC ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RC ," in_RENAME_IN_NUM_REG_RC ",Tspecial_address_t,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RD ," in_RENAME_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RD ," in_RENAME_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RE ," in_RENAME_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RE ," in_RENAME_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_EXCEPTION_USE ," in_RENAME_IN_EXCEPTION_USE ",Texception_t ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_VAL ," in_RENAME_IN_VAL ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_RENAME_IN_ACK ,"out_RENAME_IN_ACK ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_FRONT_END_ID ," in_RENAME_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_CONTEXT_ID ," in_RENAME_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_DEPTH ," in_RENAME_IN_DEPTH ",Tdepth_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_TYPE ," in_RENAME_IN_TYPE ",Ttype_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_OPERATION ," in_RENAME_IN_OPERATION ",Toperation_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RA ," in_RENAME_IN_READ_RA ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RA ," in_RENAME_IN_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RB ," in_RENAME_IN_READ_RB ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RB ," in_RENAME_IN_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RC ," in_RENAME_IN_READ_RC ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RC ," in_RENAME_IN_NUM_REG_RC ",Tspecial_address_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RD ," in_RENAME_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RD ," in_RENAME_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RE ," in_RENAME_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RE ," in_RENAME_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_EXCEPTION_USE ," in_RENAME_IN_EXCEPTION_USE ",Texception_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_EXCEPTION ," in_RENAME_IN_EXCEPTION ",Texception_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC1_SC_SIGNAL(out_RENAME_OUT_VAL ,"out_RENAME_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_rename); @@ -69,4 +82,6 @@ ALLOC1_SC_SIGNAL(out_RENAME_OUT_TYPE ,"out_RENAME_OUT_TYPE ",Ttype_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_OPERATION ,"out_RENAME_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_rename); + ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); + ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); @@ -83,4 +98,5 @@ ALLOC1_SC_SIGNAL(out_RENAME_OUT_NUM_REG_RE ,"out_RENAME_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION_USE,"out_RENAME_OUT_EXCEPTION_USE",Texception_t ,_param->_nb_inst_rename); + ALLOC1_SC_SIGNAL(out_RENAME_OUT_EXCEPTION ,"out_RENAME_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_rename); /******************************************************** @@ -93,28 +109,31 @@ (*(_Rename_select->in_NRESET)) (*(in_NRESET)); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select,out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select,out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); if (_param->_have_port_front_end_id) - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); if (_param->_have_port_context_id) - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); if (_param->_have_port_depth) - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_select, in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_VAL ,_param->_nb_inst_rename); @@ -128,4 +147,6 @@ INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_TYPE ,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_OPERATION ,_param->_nb_inst_rename); + INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NO_EXECUTE ,_param->_nb_inst_rename); + INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_IS_DELAY_SLOT,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_ADDRESS ,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_HAS_IMMEDIAT ,_param->_nb_inst_rename); @@ -142,4 +163,5 @@ INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_NUM_REG_RE ,_param->_nb_inst_rename); INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_EXCEPTION_USE,_param->_nb_inst_rename); + INSTANCE1_SC_SIGNAL(_Rename_select,out_RENAME_OUT_EXCEPTION ,_param->_nb_inst_rename); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); @@ -189,4 +211,6 @@ in_RENAME_IN_TYPE [i][j]->write(range(rand(),_param->_size_type )); in_RENAME_IN_OPERATION [i][j]->write(range(rand(),_param->_size_operation )); + in_RENAME_IN_NO_EXECUTE [i][j]->write(rand()%2); + in_RENAME_IN_IS_DELAY_SLOT[i][j]->write(rand()%2); in_RENAME_IN_ADDRESS [i][j]->write(address++ ); in_RENAME_IN_HAS_IMMEDIAT [i][j]->write(range(rand(),1 )); @@ -203,4 +227,5 @@ in_RENAME_IN_NUM_REG_RE [i][j]->write(range(rand(),_param->_size_special_register_logic)); in_RENAME_IN_EXCEPTION_USE[i][j]->write(range(rand(),_param->_size_exception )); + in_RENAME_IN_EXCEPTION [i][j]->write(range(rand(),_param->_size_exception )); } @@ -256,4 +281,6 @@ TEST(Ttype_t ,out_RENAME_OUT_TYPE [i]->read(),in_RENAME_IN_TYPE [x][y]->read()); TEST(Toperation_t ,out_RENAME_OUT_OPERATION [i]->read(),in_RENAME_IN_OPERATION [x][y]->read()); + TEST(Tcontrol_t ,out_RENAME_OUT_NO_EXECUTE [i]->read(),in_RENAME_IN_NO_EXECUTE [x][y]->read()); + TEST(Tcontrol_t ,out_RENAME_OUT_IS_DELAY_SLOT[i]->read(),in_RENAME_IN_IS_DELAY_SLOT[x][y]->read()); TEST(Tcontrol_t ,out_RENAME_OUT_HAS_IMMEDIAT [i]->read(),in_RENAME_IN_HAS_IMMEDIAT [x][y]->read()); TEST(Tgeneral_data_t ,out_RENAME_OUT_IMMEDIAT [i]->read(),in_RENAME_IN_IMMEDIAT [x][y]->read()); @@ -269,5 +296,5 @@ TEST(Tspecial_address_t,out_RENAME_OUT_NUM_REG_RE [i]->read(),in_RENAME_IN_NUM_REG_RE [x][y]->read()); TEST(Texception_t ,out_RENAME_OUT_EXCEPTION_USE[i]->read(),in_RENAME_IN_EXCEPTION_USE[x][y]->read()); - + TEST(Texception_t ,out_RENAME_OUT_EXCEPTION [i]->read(),in_RENAME_IN_EXCEPTION [x][y]->read()); } @@ -300,4 +327,6 @@ delete [] in_RENAME_IN_TYPE ; delete [] in_RENAME_IN_OPERATION ; + delete [] in_RENAME_IN_NO_EXECUTE ; + delete [] in_RENAME_IN_IS_DELAY_SLOT ; delete [] in_RENAME_IN_ADDRESS ; delete [] in_RENAME_IN_HAS_IMMEDIAT ; @@ -314,4 +343,5 @@ delete [] in_RENAME_IN_NUM_REG_RE ; delete [] in_RENAME_IN_EXCEPTION_USE ; + delete [] in_RENAME_IN_EXCEPTION ; delete [] out_RENAME_OUT_VAL ; @@ -322,4 +352,6 @@ delete [] out_RENAME_OUT_TYPE ; delete [] out_RENAME_OUT_OPERATION ; + delete [] out_RENAME_OUT_NO_EXECUTE ; + delete [] out_RENAME_OUT_IS_DELAY_SLOT; delete [] out_RENAME_OUT_ADDRESS ; delete [] out_RENAME_OUT_HAS_IMMEDIAT ; @@ -336,4 +368,5 @@ delete [] out_RENAME_OUT_NUM_REG_RE ; delete [] out_RENAME_OUT_EXCEPTION_USE; + delete [] out_RENAME_OUT_EXCEPTION ; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Parameters.h (revision 88) @@ -28,5 +28,5 @@ public : uint32_t * _nb_context ;//[nb_front_end] public : uint32_t _max_branch_speculated ; - public : uint32_t _size_general_data ; +//public : uint32_t _size_general_data ; public : uint32_t _nb_inst_rename ; public : uint32_t * _nb_inst_decod ;//[nb_front_end] @@ -36,16 +36,17 @@ public : uint32_t _max_nb_inst_decod ; +//public : uint32_t _size_depth ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; - public : uint32_t _size_front_end_id ; - public : uint32_t _size_context_id ; - public : uint32_t _size_depth ; - - public : bool _have_port_front_end_id; - public : bool _have_port_context_id ; - public : bool _have_port_depth ; +//public : bool _have_port_front_end_id; +//public : bool _have_port_context_id ; +//public : bool _have_port_depth ; //-----[ methods ]----------------------------------------------------------- public : Parameters (uint32_t nb_front_end , uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , uint32_t max_branch_speculated, uint32_t size_general_data , @@ -54,7 +55,10 @@ uint32_t nb_front_end_select , Tpriority_t priority , - Tload_balancing_t load_balancing ); -// public : Parameters (Parameters & param) ; + Tload_balancing_t load_balancing , + bool is_toplevel=true); +//public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 88) @@ -13,5 +13,4 @@ #endif -#include #include "Common/include/ToString.h" #include "Common/include/Debug.h" @@ -27,5 +26,9 @@ #endif #include "Behavioural/include/Usage.h" + +#include "Behavioural/Generic/Priority/include/Priority.h" + #include +#include namespace morpheo { @@ -71,4 +74,6 @@ public : SC_IN (Ttype_t ) *** in_RENAME_IN_TYPE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Toperation_t ) *** in_RENAME_IN_OPERATION ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -85,4 +90,5 @@ public : SC_IN (Tspecial_address_t) *** in_RENAME_IN_NUM_REG_RE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Texception_t ) *** in_RENAME_IN_EXCEPTION_USE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Texception_t ) *** in_RENAME_IN_EXCEPTION ;//[nb_front_end][nb_inst_decod] // ~~~~~[ Interface : "rename_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -94,4 +100,6 @@ public : SC_OUT(Ttype_t ) ** out_RENAME_OUT_TYPE ;//[nb_inst_rename] public : SC_OUT(Toperation_t ) ** out_RENAME_OUT_OPERATION ;//[nb_inst_rename] + public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] + public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] @@ -108,12 +116,12 @@ public : SC_OUT(Tspecial_address_t) ** out_RENAME_OUT_NUM_REG_RE ;//[nb_inst_rename] public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION_USE;//[nb_inst_rename] + public : SC_OUT(Texception_t ) ** out_RENAME_OUT_EXCEPTION ;//[nb_inst_rename] // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : generic::priority::Priority * _priority; // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : uint32_t reg_FRONT_END_PRIORITY; // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - private : std::list select; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Types.h (revision 88) @@ -19,17 +19,4 @@ namespace rename_select { - class select_t - { - public : uint32_t _front_end ; - public : uint32_t _inst_decod; - - public : select_t (uint32_t front_end, - uint32_t inst_decod) - { - _front_end = front_end ; - _inst_decod = inst_decod; - } - }; - }; // end namespace rename_select }; // end namespace rename_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp (revision 88) @@ -22,4 +22,6 @@ Parameters::Parameters (uint32_t nb_front_end , uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , uint32_t max_branch_speculated, uint32_t size_general_data , @@ -28,5 +30,6 @@ uint32_t nb_front_end_select , Tpriority_t priority , - Tload_balancing_t load_balancing ) + Tload_balancing_t load_balancing , + bool is_toplevel) { log_printf(FUNC,Rename_select,FUNCTION,"Begin"); @@ -35,5 +38,4 @@ _nb_context = nb_context ; _max_branch_speculated = max_branch_speculated; - _size_general_data = size_general_data ; _nb_inst_rename = nb_inst_rename ; _nb_inst_decod = nb_inst_decod ; @@ -44,13 +46,20 @@ _max_nb_inst_decod = max(nb_inst_decod,nb_front_end); - _size_front_end_id = log2(nb_front_end); - _size_context_id = log2(max(nb_context,nb_front_end)); - _size_depth = log2(max_branch_speculated); + test(); - _have_port_front_end_id= _size_front_end_id > 0; - _have_port_context_id = _size_context_id > 0; - _have_port_depth = _size_depth > 0; + if (is_toplevel) + { + _size_general_data = size_general_data ; + _size_depth = log2(max_branch_speculated); + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(max(_nb_context,_nb_front_end)); - test(); + _have_port_front_end_id= _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; + + copy(); + } + log_printf(FUNC,Rename_select,FUNCTION,"End"); }; @@ -73,4 +82,12 @@ }; +#undef FUNCTION +#define FUNCTION "Rename_select::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Rename_select,FUNCTION,"Begin"); + log_printf(FUNC,Rename_select,FUNCTION,"End"); + }; + }; // end namespace rename_select }; // end namespace rename_unit Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select.cpp (revision 88) @@ -38,4 +38,10 @@ log_printf(FUNC,Rename_select,FUNCTION,"Begin"); +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Rename_select,FUNCTION,"Allocation"); @@ -47,5 +53,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Rename_select,FUNCTION,"Allocation of statistics"); @@ -56,5 +62,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -66,5 +72,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Rename_select,FUNCTION,"Method - transition"); @@ -89,4 +95,6 @@ << (*(in_RENAME_IN_TYPE [i][j])) << (*(in_RENAME_IN_OPERATION [i][j])) + << (*(in_RENAME_IN_NO_EXECUTE [i][j])) + << (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])) << (*(in_RENAME_IN_ADDRESS [i][j])) << (*(in_RENAME_IN_HAS_IMMEDIAT [i][j])) @@ -102,5 +110,6 @@ << (*(in_RENAME_IN_WRITE_RE [i][j])) << (*(in_RENAME_IN_NUM_REG_RE [i][j])) - << (*(in_RENAME_IN_EXCEPTION_USE [i][j])); + << (*(in_RENAME_IN_EXCEPTION_USE [i][j])) + << (*(in_RENAME_IN_EXCEPTION [i][j])); if (_param->_have_port_front_end_id) sensitive << (*(in_RENAME_IN_FRONT_END_ID [i][j])); @@ -150,4 +159,8 @@ (*(out_RENAME_OUT_OPERATION [x])) (*(in_RENAME_IN_VAL [i][j])); (*(out_RENAME_OUT_OPERATION [x])) (*(in_RENAME_IN_OPERATION [i][j])); + (*(out_RENAME_OUT_NO_EXECUTE [x])) (*(in_RENAME_IN_VAL [i][j])); + (*(out_RENAME_OUT_NO_EXECUTE [x])) (*(in_RENAME_IN_NO_EXECUTE [i][j])); + (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_VAL [i][j])); + (*(out_RENAME_OUT_IS_DELAY_SLOT [x])) (*(in_RENAME_IN_IS_DELAY_SLOT [i][j])); (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_VAL [i][j])); (*(out_RENAME_OUT_ADDRESS [x])) (*(in_RENAME_IN_ADDRESS [i][j])); @@ -178,4 +191,6 @@ (*(out_RENAME_OUT_EXCEPTION_USE [x])) (*(in_RENAME_IN_VAL [i][j])); (*(out_RENAME_OUT_EXCEPTION_USE [x])) (*(in_RENAME_IN_EXCEPTION_USE [i][j])); + (*(out_RENAME_OUT_EXCEPTION [x])) (*(in_RENAME_IN_VAL [i][j])); + (*(out_RENAME_OUT_EXCEPTION [x])) (*(in_RENAME_IN_EXCEPTION [i][j])); } } @@ -194,5 +209,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Rename_select,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 88) @@ -58,27 +58,30 @@ // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { - ALLOC2_INTERFACE("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[alloc_interface_it1]); + ALLOC2_INTERFACE("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]); - _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_VALACK_OUT(out_RENAME_IN_ACK ,ACK, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[alloc_signal_it1]); + _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_VALACK_OUT(out_RENAME_IN_ACK ,ACK, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); } @@ -94,4 +97,6 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); @@ -108,11 +113,18 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _priority = new generic::priority::Priority (_name+"_priority" , + _param->_priority , + _param->_load_balancing, + _param->_nb_front_end , + _param->_nb_inst_decod , + _param->_nb_front_end_select); #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_deallocation.cpp (revision 88) @@ -23,5 +23,5 @@ log_printf(FUNC,Rename_select,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -38,4 +38,6 @@ delete [] in_RENAME_IN_TYPE ; delete [] in_RENAME_IN_OPERATION ; + delete [] in_RENAME_IN_NO_EXECUTE ; + delete [] in_RENAME_IN_IS_DELAY_SLOT ; delete [] in_RENAME_IN_ADDRESS ; delete [] in_RENAME_IN_HAS_IMMEDIAT ; @@ -52,4 +54,5 @@ delete [] in_RENAME_IN_NUM_REG_RE ; delete [] in_RENAME_IN_EXCEPTION_USE ; + delete [] in_RENAME_IN_EXCEPTION ; delete [] out_RENAME_OUT_VAL ; @@ -79,5 +82,5 @@ } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - + delete _priority; delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_end_cycle.cpp (revision 88) @@ -25,5 +25,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -31,5 +32,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_genMealy.cpp (revision 88) @@ -22,28 +22,46 @@ void Rename_select::genMealy (void) { - log_printf(FUNC,Rename_select,FUNCTION,"Begin"); + log_begin(Rename_select,FUNCTION); + log_function(Rename_select,FUNCTION,_name.c_str()); - Tcontrol_t ack [_param->_nb_front_end][_param->_max_nb_inst_decod]; + Tcontrol_t val [_param->_nb_inst_rename]; + Tcontrol_t ack [_param->_nb_front_end][_param->_max_nb_inst_decod]; + Tcontrol_t previous_transaction [_param->_nb_front_end]; + + for (uint32_t i=0; i<_param->_nb_inst_rename; ++i) + val [i] = false; for (uint32_t i=0; i<_param->_nb_front_end; i++) - for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) - ack [i][j] = false; - - std::list::iterator it=select.begin(); + { + previous_transaction [i] = true; + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) + ack [i][j] = false; + } + + std::list * select = _priority->select(); + std::list::iterator it=select->begin(); for (uint32_t i=0; i<_param->_nb_inst_rename; i++) { - Tcontrol_t val = false; + log_printf(TRACE,Rename_select,FUNCTION," * inst_rename [%d]",i); - while ((it != select.end()) and (val == false)) + // Scan all instruction until find + while ((it != select->end()) and (val [i] == false)) { - Tcontext_t x = it->_front_end ; - uint32_t y = it->_inst_decod; + Tcontext_t x = it->grp; + uint32_t y = it->elt; - // Test if this instruction is valid - if (PORT_READ(in_RENAME_IN_VAL[x][y]) == 1) + log_printf(TRACE,Rename_select,FUNCTION," * front_end[%d].inst_decod[%d]",x,y); + log_printf(TRACE,Rename_select,FUNCTION," * rename_in_val : %d",PORT_READ(in_RENAME_IN_VAL[x][y])); + log_printf(TRACE,Rename_select,FUNCTION," * previous_transaction : %d",previous_transaction[x]); + + // Test if this instruction is valid and if all previous instruction of this front end is an valid transaction + if (previous_transaction [x] and + PORT_READ(in_RENAME_IN_VAL[x][y])) { // Find !!! - val = true; + val [i] = true; ack [x][y] = PORT_READ(in_RENAME_OUT_ACK [i]); + + log_printf(TRACE,Rename_select,FUNCTION," * rename_out_ack : %d",PORT_READ(in_RENAME_OUT_ACK[i])); if (_param->_have_port_front_end_id) @@ -55,4 +73,6 @@ PORT_WRITE(out_RENAME_OUT_TYPE [i],PORT_READ(in_RENAME_IN_TYPE [x][y])); PORT_WRITE(out_RENAME_OUT_OPERATION [i],PORT_READ(in_RENAME_IN_OPERATION [x][y])); + PORT_WRITE(out_RENAME_OUT_NO_EXECUTE [i],PORT_READ(in_RENAME_IN_NO_EXECUTE [x][y])); + PORT_WRITE(out_RENAME_OUT_IS_DELAY_SLOT[i],PORT_READ(in_RENAME_IN_IS_DELAY_SLOT [x][y])); PORT_WRITE(out_RENAME_OUT_ADDRESS [i],PORT_READ(in_RENAME_IN_ADDRESS [x][y])); PORT_WRITE(out_RENAME_OUT_HAS_IMMEDIAT [i],PORT_READ(in_RENAME_IN_HAS_IMMEDIAT [x][y])); @@ -69,11 +89,17 @@ PORT_WRITE(out_RENAME_OUT_NUM_REG_RE [i],PORT_READ(in_RENAME_IN_NUM_REG_RE [x][y])); PORT_WRITE(out_RENAME_OUT_EXCEPTION_USE[i],PORT_READ(in_RENAME_IN_EXCEPTION_USE [x][y])); + PORT_WRITE(out_RENAME_OUT_EXCEPTION [i],PORT_READ(in_RENAME_IN_EXCEPTION [x][y])); } + + // ack = 1 if previous_transaction == true and rename_in_val == true and rename_out == true + previous_transaction [x] = ack [x][y]; it ++; } - PORT_WRITE(out_RENAME_OUT_VAL [i], val); } + + for (uint32_t i=0; i<_param->_nb_inst_rename; ++i) + PORT_WRITE(out_RENAME_OUT_VAL [i], val [i]); for (uint32_t i=0; i<_param->_nb_front_end; i++) @@ -81,5 +107,5 @@ PORT_WRITE(out_RENAME_IN_ACK [i][j], ack [i][j]); - log_printf(FUNC,Rename_select,FUNCTION,"End"); + log_end(Rename_select,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_transition.cpp (revision 88) @@ -26,65 +26,9 @@ if (PORT_READ(in_NRESET) == 0) { - select.clear(); - reg_FRONT_END_PRIORITY = 0; + _priority->reset(); } else { - switch (_param->_priority) - { - case PRIORITY_STATIC : - { - reg_FRONT_END_PRIORITY = (reg_FRONT_END_PRIORITY+_param->_nb_front_end_select)%_param->_nb_front_end; - break; - } - case PRIORITY_ROUND_ROBIN : - { - reg_FRONT_END_PRIORITY = (reg_FRONT_END_PRIORITY+1)%_param->_nb_front_end; - break; - } - default: - { - break; - } - } - - // flush list - select.clear(); - - // Compute next scan order !!! - switch (_param->_load_balancing) - { - case LOAD_BALANCING_BALANCE : - { - for (uint32_t j=0; j<_param->_max_nb_inst_decod; j++) - for (uint32_t i=0; i<_param->_nb_front_end_select; i++) - { - uint32_t x=(reg_FRONT_END_PRIORITY+i)%_param->_nb_front_end; - - // Test valid inst_decod - if (j < _param->_nb_inst_decod[x]) - select.push_back(select_t(x,j)); - } - - break; - } - case LOAD_BALANCING_MAXIMUM_FOR_PRIORITY : - { - - for (uint32_t i=0; i<_param->_nb_front_end_select; i++) - { - uint32_t x=(reg_FRONT_END_PRIORITY+i)%_param->_nb_front_end; - - for (uint32_t j=0; j<_param->_nb_inst_decod[x]; j++) - select.push_back(select_t(x,j)); - } - - break; - } - default : - { - break; - } - } + _priority->transition(); // #if (DEBUG >= DEBUG_TRACE) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libRename_unit_Glue.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/Makefile.deps (revision 88) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Rename_unit_Glue = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Rename_unit_Glue_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue + +#-----[ Library ]------------------------------------------ + +Rename_unit_Glue_LIBRARY = -lRename_unit_Glue \ + $(Behavioural_LIBRARY) + +Rename_unit_Glue_DIR_LIBRARY = -L$(Rename_unit_Glue_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Rename_unit_Glue_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Rename_unit_Glue_DIR) --makefile=Makefile; + +Rename_unit_Glue_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Rename_unit_Glue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Rename_unit_Glue_LIBRARY) + +DIR_LIBRARY = $(Rename_unit_Glue_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Rename_unit_Glue_library + +library_clean : Rename_unit_Glue_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,7 @@ +Rename_unit_Glue +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_inst_insert +1 1 +1 # nb_inst_retire +32 32 +1 # size_general_data +2 2 +1 # size_special_register Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/include/test.h (revision 88) @@ -0,0 +1,31 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,94 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/include/test.h" + +#define NB_PARAMS 5 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t)\n")); + err (_(" * nb_context [nb_front_end] (uint32_t)\n")); + err (_(" * nb_inst_insert (uint32_t)\n")); + err (_(" * nb_inst_retire (uint32_t)\n")); + err (_(" * size_general_data (uint32_t)\n")); + err (_(" * size_special_register (uint32_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+_nb_front_end)) + usage (argc, argv); + + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + _nb_context [i] = fromString(argv[x++]); + + + uint32_t _nb_inst_insert = fromString(argv[x++]); + uint32_t _nb_inst_retire = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_register = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters + ( + _nb_front_end , + _nb_context , + _nb_inst_insert, + _nb_inst_retire, + _size_general_data, + _size_special_register, + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Rename_unit_Glue : no error"); + else + TEST_KO("Rename_unit_Glue : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + delete [] _nb_context; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,241 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Rename_unit_Glue * _Rename_unit_Glue = new Rename_unit_Glue + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + +//ALLOC1_SC_SIGNAL(out_INSERT_VAL ,"out_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); +//ALLOC1_SC_SIGNAL( in_INSERT_ACK ," in_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_FRONT_END_ID ,"out_INSERT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_CONTEXT_ID ,"out_INSERT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_TYPE ,"out_INSERT_TYPE ",Ttype_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_OPERATION ,"out_INSERT_OPERATION ",Toperation_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT ,"out_INSERT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_insert); +// ALLOC1_SC_SIGNAL(out_INSERT_EXCEPTION_USE ,"out_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_EXCEPTION ,"out_INSERT_EXCEPTION ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,"out_INSERT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_VAL ," in_INSERT_RENAME_SELECT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RENAME_SELECT_ACK ,"out_INSERT_RENAME_SELECT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_FRONT_END_ID ," in_INSERT_RENAME_SELECT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_CONTEXT_ID ," in_INSERT_RENAME_SELECT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_TYPE ," in_INSERT_RENAME_SELECT_TYPE ",Ttype_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_OPERATION ," in_INSERT_RENAME_SELECT_OPERATION ",Toperation_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_IMMEDIAT ," in_INSERT_RENAME_SELECT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_insert); +// ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION_USE ," in_INSERT_RENAME_SELECT_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION ," in_INSERT_RENAME_SELECT_EXCEPTION ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_VAL ,"out_INSERT_REGISTER_TRANSLATION_VAL ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_REGISTER_TRANSLATION_ACK ," in_INSERT_REGISTER_TRANSLATION_ACK ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ,"out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,"out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW ," in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,"out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ," in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ,"out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ,"out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,"out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ",Ttype_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,"out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ",Toperation_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ,"out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ," in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ",Tcontrol_t ,_param->_nb_inst_retire); +//ALLOC1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ,"out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ",Ttype_t ,_param->_nb_inst_retire); +//ALLOC1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ,"out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ",Toperation_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_REGISTER_TRANSLATION_VAL ,"out_RETIRE_REGISTER_TRANSLATION_VAL ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_REGISTER_TRANSLATION_ACK ," in_RETIRE_REGISTER_TRANSLATION_ACK ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC2_SC_SIGNAL( in_SPR_READ_SR ," in_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Rename_unit_Glue.\n"),name.c_str()); + + (*(_Rename_unit_Glue->in_CLOCK)) (*(in_CLOCK)); + (*(_Rename_unit_Glue->in_NRESET)) (*(in_NRESET)); + +//INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_VAL ,_param->_nb_inst_insert); +//INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_ACK ,_param->_nb_inst_insert); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_TYPE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_OPERATION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); +// INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_EXCEPTION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_RENAME_SELECT_ACK ,_param->_nb_inst_insert); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_FRONT_END_ID ,_param->_nb_inst_insert); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_CONTEXT_ID ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_TYPE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_OPERATION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_IMMEDIAT ,_param->_nb_inst_insert); +// INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_EXCEPTION_USE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_RENAME_SELECT_EXCEPTION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_insert); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ,_param->_nb_inst_insert); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_insert); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ,_param->_nb_inst_insert); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_RETIRE_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_RETIRE_ACK ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_retire); +//INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_retire); +//INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue,out_RETIRE_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit_Glue, in_RETIRE_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_retire); + + INSTANCE2_SC_SIGNAL(_Rename_unit_Glue, in_SPR_READ_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + +//DELETE1_SC_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert); +//DELETE1_SC_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_TYPE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_OPERATION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); +// DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RENAME_SELECT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_FRONT_END_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_CONTEXT_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_TYPE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_OPERATION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_IMMEDIAT ,_param->_nb_inst_insert); +// DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_retire); + + DELETE2_SC_SIGNAL( in_SPR_READ_SR ,_param->_nb_front_end,_param->_nb_context[it1]); + } +#endif + + delete _Rename_unit_Glue; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Rename_unit_Glue.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Rename_unit_Glue.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/Rename_unit_Glue.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Rename_unit_Glue} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h (revision 88) @@ -0,0 +1,71 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_inst_insert ; + public : uint32_t _nb_inst_retire ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_register ; + +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; + +//public : bool _have_port_front_end_id; +//public : bool _have_port_context_id ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , + uint32_t nb_inst_insert , + uint32_t nb_inst_retire , + uint32_t size_general_data , + uint32_t size_special_register, + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters & x); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h (revision 88) @@ -0,0 +1,184 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Rename_unit_Glue_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Rename_unit_Glue_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + + class Rename_unit_Glue +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +//public : SC_OUT(Tcontrol_t ) ** out_INSERT_VAL ;//[nb_inst_insert] +//public : SC_IN (Tcontrol_t ) ** in_INSERT_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_FRONT_END_ID ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_CONTEXT_ID ;//[nb_inst_insert] + public : SC_OUT(Ttype_t ) ** out_INSERT_TYPE ;//[nb_inst_insert] + public : SC_OUT(Toperation_t ) ** out_INSERT_OPERATION ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] + public : SC_OUT(Texception_t ) ** out_INSERT_EXCEPTION_USE ;//[nb_inst_insert] + public : SC_OUT(Texception_t ) ** out_INSERT_EXCEPTION ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] + + public : SC_IN (Tcontrol_t ) ** in_INSERT_RENAME_SELECT_VAL ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RENAME_SELECT_ACK ;//[nb_inst_insert] + public : SC_IN (Tcontext_t ) ** in_INSERT_RENAME_SELECT_FRONT_END_ID ;//[nb_inst_insert] + public : SC_IN (Tcontext_t ) ** in_INSERT_RENAME_SELECT_CONTEXT_ID ;//[nb_inst_insert] + public : SC_IN (Ttype_t ) ** in_INSERT_RENAME_SELECT_TYPE ;//[nb_inst_insert] + public : SC_IN (Toperation_t ) ** in_INSERT_RENAME_SELECT_OPERATION ;//[nb_inst_insert] + public : SC_IN (Tgeneral_data_t ) ** in_INSERT_RENAME_SELECT_IMMEDIAT ;//[nb_inst_insert] + public : SC_IN (Texception_t ) ** in_INSERT_RENAME_SELECT_EXCEPTION_USE ;//[nb_inst_insert] + public : SC_IN (Texception_t ) ** in_INSERT_RENAME_SELECT_EXCEPTION ;//[nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) ** out_INSERT_REGISTER_TRANSLATION_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_REGISTER_TRANSLATION_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ;//[nb_inst_insert] + public : SC_IN (Tspecial_address_t) ** in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW;//[nb_inst_insert] + + public : SC_OUT(Tcontrol_t ) ** out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ;//[nb_inst_insert] + public : SC_OUT(Ttype_t ) ** out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ;//[nb_inst_insert] + public : SC_OUT(Toperation_t ) ** out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ;//[nb_inst_insert] + + // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_ACK ;//[nb_inst_retire] + + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ;//[nb_inst_retire] +//public : SC_OUT(Ttype_t ) ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ;//[nb_inst_retire] +//public : SC_OUT(Toperation_t ) ** out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ;//[nb_inst_retire] + + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_REGISTER_TRANSLATION_VAL ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_REGISTER_TRANSLATION_ACK ;//[nb_inst_retire] + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tspr_t ) *** in_SPR_READ_SR ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Rename_unit_Glue); +#endif + public : Rename_unit_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Rename_unit_Glue (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); +//public : void genMoore (void); + public : void genMealy_insert_valack (void); + public : void genMealy_retire_valack (void); + public : void genMealy_insert (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Types.h (revision 88) @@ -0,0 +1,31 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_rename_unit_glue_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters.cpp (revision 88) @@ -0,0 +1,90 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h" +#include "Common/include/Max.h" +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context , +// uint32_t size_front_end_id , +// uint32_t size_context_id , + uint32_t nb_inst_insert , + uint32_t nb_inst_retire , + uint32_t size_general_data , + uint32_t size_special_register , + bool is_toplevel + ) + { + log_begin(Rename_unit_Glue,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_inst_insert = nb_inst_insert; + _nb_inst_retire = nb_inst_retire; + + test(); + + if (is_toplevel) + { + _size_general_data = size_general_data ; + _size_special_register = size_special_register; + + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(max(_nb_context,_nb_front_end)); + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + + copy(); + } + + log_end(Rename_unit_Glue,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Rename_unit_Glue::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Rename_unit_Glue,FUNCTION); +// test(); +// log_end(Rename_unit_Glue,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_end(Rename_unit_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::copy" + void Parameters::copy (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,44 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Rename_unit_Glue,FUNCTION); + + Parameters_test test ("Rename_unit_Glue"); + +// if (_size_special_register < 2) +// test.error(("size_special_register must be >= 2.\n")); + + log_end(Rename_unit_Glue,FUNCTION); + + return test; + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,58 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Rename_unit_Glue,FUNCTION); + + XML xml ("rename_unit_glue"); + + xml.balise_open("rename_unit_glue"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Rename_unit_Glue,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters & x) + { + log_begin(Rename_unit_Glue,FUNCTION); + + output_stream << x.print(0); + + log_end(Rename_unit_Glue,FUNCTION); + + return output_stream; + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue.cpp (revision 88) @@ -0,0 +1,190 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::Rename_unit_Glue" + Rename_unit_Glue::Rename_unit_Glue + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Rename_unit_Glue,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Rename_unit_Glue == true + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +// log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - genMealy_insert_valack"),_name.c_str()); + + SC_METHOD (genMealy_insert_valack); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + sensitive + //<< (*(in_INSERT_ACK [i])) + << (*(in_INSERT_RENAME_SELECT_VAL [i])) + << (*(in_INSERT_REGISTER_TRANSLATION_ACK [i])) + << (*(in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK [i])) + ; + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - genMealy_retire_valack"),_name.c_str()); + + SC_METHOD (genMealy_retire_valack); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + sensitive + << (*(in_RETIRE_VAL [i])) + << (*(in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK [i])) + << (*(in_RETIRE_REGISTER_TRANSLATION_ACK [i])) + ; + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Method - genMealy_insert"),_name.c_str()); + + SC_METHOD (genMealy_insert); + dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // don't need internal register + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + if (_param->_have_port_front_end_id) + sensitive << (*(in_INSERT_RENAME_SELECT_FRONT_END_ID [i])); + if (_param->_have_port_context_id) + sensitive << (*(in_INSERT_RENAME_SELECT_CONTEXT_ID [i])); + sensitive << (*(in_INSERT_RENAME_SELECT_TYPE [i])) + << (*(in_INSERT_RENAME_SELECT_OPERATION [i])) + << (*(in_INSERT_RENAME_SELECT_IMMEDIAT [i])) +// << (*(in_INSERT_RENAME_SELECT_EXCEPTION_USE [i])) + << (*(in_INSERT_RENAME_SELECT_EXCEPTION [i])) + << (*(in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW [i])); + + } + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + sensitive << (*(in_SPR_READ_SR [i][j])); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Rename_unit_Glue,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::~Rename_unit_Glue" + Rename_unit_Glue::~Rename_unit_Glue (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_allocation.cpp (revision 88) @@ -0,0 +1,132 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::allocation" + void Rename_unit_Glue::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Rename_unit_Glue,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Rename_unit_Glue" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("insert",OUT,NORTH,_("Insert interface"),_param->_nb_inst_insert); + +// ALLOC1_SIGNAL_OUT(out_INSERT_VAL ,"VAL" ,Tcontrol_t ,1); +// ALLOC1_SIGNAL_IN ( in_INSERT_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_INSERT_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); +// ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); + ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"NUM_REG_RE_PHY_NEW" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_VAL ,"RENAME_SELECT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_SELECT_ACK ,"RENAME_SELECT_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_FRONT_END_ID ,"RENAME_SELECT_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_CONTEXT_ID ,"RENAME_SELECT_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_TYPE ,"RENAME_SELECT_TYPE" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_OPERATION ,"RENAME_SELECT_OPERATION" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_IMMEDIAT ,"RENAME_SELECT_IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data); +// ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,"RENAME_SELECT_EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_SELECT_EXCEPTION ,"RENAME_SELECT_EXCEPTION" ,Texception_t ,_param->_size_exception); + ALLOC1_SIGNAL_OUT(out_INSERT_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_REGISTER_TRANSLATION_ACK ,"REGISTER_TRANSLATION_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ,"REGISTER_TRANSLATION_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,"REGISTER_TRANSLATION_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_IN ( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,"REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,"LOAD_STORE_QUEUE_POINTER_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ,"LOAD_STORE_QUEUE_POINTER_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ,"LOAD_STORE_QUEUE_POINTER_FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ,"LOAD_STORE_QUEUE_POINTER_CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,"LOAD_STORE_QUEUE_POINTER_TYPE" ,Ttype_t ,_param->_size_type); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,"LOAD_STORE_QUEUE_POINTER_OPERATION" ,Toperation_t ,_param->_size_operation); + } + + // ~~~~~[ Interface : "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("retire",OUT,NORTH,_("Retire interface"),_param->_nb_inst_retire); + + ALLOC1_SIGNAL_IN ( in_RETIRE_VAL ,"VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_ACK ,"ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ,"LOAD_STORE_QUEUE_POINTER_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ,"LOAD_STORE_QUEUE_POINTER_ACK" ,Tcontrol_t ,1); +// ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ,"LOAD_STORE_QUEUE_POINTER_TYPE" ,Ttype_t ,_param->_size_type); +// ALLOC1_SIGNAL_OUT(out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ,"LOAD_STORE_QUEUE_POINTER_OPERATION" ,Toperation_t ,_param->_size_operation); + ALLOC1_SIGNAL_OUT(out_RETIRE_REGISTER_TRANSLATION_VAL ,"REGISTER_TRANSLATION_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_RETIRE_REGISTER_TRANSLATION_ACK ,"REGISTER_TRANSLATION_ACK" ,Tcontrol_t ,1); + } + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_read",IN ,NORTH,_("SPR read"),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN ( in_SPR_READ_SR ,"SR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_deallocation.cpp (revision 88) @@ -0,0 +1,87 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::deallocation" + void Rename_unit_Glue::deallocation (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + +// DELETE1_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert,1); +// DELETE1_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); + DELETE1_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id); + DELETE1_SIGNAL(out_INSERT_TYPE ,_param->_nb_inst_insert,_param->_size_type); + DELETE1_SIGNAL(out_INSERT_OPERATION ,_param->_nb_inst_insert,_param->_size_operation); + DELETE1_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert,_param->_size_general_data); +// DELETE1_SIGNAL(out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert,_param->_size_exception_use); + DELETE1_SIGNAL(out_INSERT_EXCEPTION ,_param->_nb_inst_insert,_param->_size_exception); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RENAME_SELECT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_TYPE ,_param->_nb_inst_insert,_param->_size_type); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_OPERATION ,_param->_nb_inst_insert,_param->_size_operation); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_IMMEDIAT ,_param->_nb_inst_insert,_param->_size_general_data); +// DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION_USE ,_param->_nb_inst_insert,_param->_size_exception_use); + DELETE1_SIGNAL( in_INSERT_RENAME_SELECT_EXCEPTION ,_param->_nb_inst_insert,_param->_size_exception); + DELETE1_SIGNAL(out_INSERT_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); + DELETE1_SIGNAL(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id); + DELETE1_SIGNAL( in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert,_param->_size_special_register); + DELETE1_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id); + DELETE1_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id); + DELETE1_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_insert,_param->_size_type); + DELETE1_SIGNAL(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_insert,_param->_size_operation); + + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK ,_param->_nb_inst_retire,1); +// DELETE1_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE ,_param->_nb_inst_retire,_param->_size_type); +// DELETE1_SIGNAL(out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION ,_param->_nb_inst_retire,_param->_size_operation); + DELETE1_SIGNAL(out_RETIRE_REGISTER_TRANSLATION_VAL ,_param->_nb_inst_retire,1); + DELETE1_SIGNAL( in_RETIRE_REGISTER_TRANSLATION_ACK ,_param->_nb_inst_retire,1); + + DELETE2_SIGNAL( in_SPR_READ_SR ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_end_cycle.cpp (revision 88) @@ -0,0 +1,49 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::end_cycle" +void Rename_unit_Glue::end_cycle () + { + log_begin(Rename_unit_Glue,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert.cpp (revision 88) @@ -0,0 +1,118 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::genMealy_insert" + void Rename_unit_Glue::genMealy_insert (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_function(Rename_unit_Glue,FUNCTION,_name.c_str()); + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + + Tcontext_t FRONT_END_ID = (_param->_have_port_front_end_id)?PORT_READ(in_INSERT_RENAME_SELECT_FRONT_END_ID [i]):0; + Tcontext_t CONTEXT_ID = (_param->_have_port_context_id )?PORT_READ(in_INSERT_RENAME_SELECT_CONTEXT_ID [i]):0; + Ttype_t TYPE = PORT_READ(in_INSERT_RENAME_SELECT_TYPE [i]); + Toperation_t OPERATION = PORT_READ(in_INSERT_RENAME_SELECT_OPERATION [i]); + Tgeneral_data_t IMMEDIAT = PORT_READ(in_INSERT_RENAME_SELECT_IMMEDIAT [i]); +// Texception_t EXCEPTION_USE = PORT_READ(in_INSERT_RENAME_SELECT_EXCEPTION_USE [i]); + Texception_t EXCEPTION = PORT_READ(in_INSERT_RENAME_SELECT_EXCEPTION [i]); + Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW [i]); + Tspr_t SR = PORT_READ(in_SPR_READ_SR[FRONT_END_ID][CONTEXT_ID]); + + switch (TYPE) + { + case TYPE_SPECIAL : + { + switch (OPERATION) + { + case OPERATION_SPECIAL_L_TRAP : + { +#ifdef DEBUG_TEST + if (IMMEDIAT > 32) + throw ERRORMORPHEO(FUNCTION,_("Immediat is too high.\n")); +#endif + + // Test if bit is set + if ((SR>>IMMEDIAT)&1) + EXCEPTION = EXCEPTION_TRAP; + + // Test + break; + } + case OPERATION_SPECIAL_L_MFSPR : + case OPERATION_SPECIAL_L_MTSPR : + { + // HACK : use the field num_reg_re to pass the SM and SUMRA flag. + NUM_REG_RE_PHY_NEW = ( + ((SR >> 16)&1) | // SUMRA + ((SR >> 0)&1) // SM + ); + + break; + } + default : + { + break; + } + } + break; + } + default : + { + break; + } + } + + + if (_param->_have_port_front_end_id) + { + PORT_WRITE(out_INSERT_FRONT_END_ID [i],FRONT_END_ID ); + PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID [i],FRONT_END_ID ); + PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID [i],FRONT_END_ID ); + } + if (_param->_have_port_context_id) + { + PORT_WRITE(out_INSERT_CONTEXT_ID [i],CONTEXT_ID ); + PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID [i],CONTEXT_ID ); + PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID [i],CONTEXT_ID ); + } + PORT_WRITE(out_INSERT_TYPE [i],TYPE ); + PORT_WRITE(out_INSERT_OPERATION [i],OPERATION ); + PORT_WRITE(out_INSERT_IMMEDIAT [i],IMMEDIAT ); +// PORT_WRITE(out_INSERT_EXCEPTION_USE [i],EXCEPTION_USE ); + PORT_WRITE(out_INSERT_EXCEPTION [i],EXCEPTION ); + PORT_WRITE(out_INSERT_NUM_REG_RE_PHY_NEW [i],NUM_REG_RE_PHY_NEW); + PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE [i],TYPE ); + PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION [i],OPERATION ); + } + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert_valack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert_valack.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_insert_valack.cpp (revision 88) @@ -0,0 +1,85 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::genMealy_insert_valack" + void Rename_unit_Glue::genMealy_insert_valack (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_function(Rename_unit_Glue,FUNCTION,_name.c_str()); + +// // Transaction must be in-order +// Tcontrol_t previous_transaction = true; + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + //Tcontrol_t ACK = PORT_READ(in_INSERT_ACK [i]); + Tcontrol_t RENAME_SELECT_VAL = PORT_READ(in_INSERT_RENAME_SELECT_VAL [i]); + Tcontrol_t REGISTER_TRANSLATION_ACK = PORT_READ(in_INSERT_REGISTER_TRANSLATION_ACK [i]); + Tcontrol_t LOAD_STORE_QUEUE_POINTER_ACK = PORT_READ(in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK [i]); + +// Tcontrol_t VAL = ( +// previous_transaction and +// RENAME_SELECT_VAL and +// REGISTER_TRANSLATION_ACK and +// LOAD_STORE_QUEUE_POINTER_ACK ); + Tcontrol_t RENAME_SELECT_ACK = ( +// previous_transaction and +// ACK and + REGISTER_TRANSLATION_ACK and + LOAD_STORE_QUEUE_POINTER_ACK ); + Tcontrol_t REGISTER_TRANSLATION_VAL = ( +// previous_transaction and +// ACK and + RENAME_SELECT_VAL and + LOAD_STORE_QUEUE_POINTER_ACK ); + Tcontrol_t LOAD_STORE_QUEUE_POINTER_VAL = ( +// previous_transaction and +// ACK and + RENAME_SELECT_VAL and + REGISTER_TRANSLATION_ACK ); + + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * insert [%d]",i); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * rename_select_val (r) : %d",RENAME_SELECT_VAL ); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * rename_select_ack (w) : %d",RENAME_SELECT_ACK ); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * register_translation_val (w) : %d",REGISTER_TRANSLATION_VAL ); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * register_translation_ack (r) : %d",REGISTER_TRANSLATION_ACK ); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * load_store_queue_pointer_val (w) : %d",LOAD_STORE_QUEUE_POINTER_VAL); + log_printf(TRACE,Rename_unit_Glue,FUNCTION," * load_store_queue_pointer_ack (r) : %d",LOAD_STORE_QUEUE_POINTER_ACK); + +// PORT_WRITE(out_INSERT_VAL [i], VAL ); + PORT_WRITE(out_INSERT_RENAME_SELECT_ACK [i], RENAME_SELECT_ACK ); + PORT_WRITE(out_INSERT_REGISTER_TRANSLATION_VAL [i], REGISTER_TRANSLATION_VAL ); + PORT_WRITE(out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL [i], LOAD_STORE_QUEUE_POINTER_VAL); + +// previous_transaction = RENAME_SELECT_VAL and RENAME_SELECT_ACK; + } + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_valack.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_valack.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_genMealy_retire_valack.cpp (revision 88) @@ -0,0 +1,64 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::genMealy_retire_valack" + void Rename_unit_Glue::genMealy_retire_valack (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_function(Rename_unit_Glue,FUNCTION,_name.c_str()); + + // Transaction must be in-order + Tcontrol_t previous_transaction = true; + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + Tcontrol_t VAL = PORT_READ(in_RETIRE_VAL [i]); + Tcontrol_t LOAD_STORE_QUEUE_POINTER_ACK = PORT_READ(in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK [i]); + Tcontrol_t REGISTER_TRANSLATION_ACK = PORT_READ(in_RETIRE_REGISTER_TRANSLATION_ACK [i]); + + Tcontrol_t ACK = (previous_transaction and + LOAD_STORE_QUEUE_POINTER_ACK and + REGISTER_TRANSLATION_ACK ); + Tcontrol_t LOAD_STORE_QUEUE_POINTER_VAL = (previous_transaction and + VAL and + REGISTER_TRANSLATION_ACK ); + Tcontrol_t REGISTER_TRANSLATION_VAL = (previous_transaction and + VAL and + LOAD_STORE_QUEUE_POINTER_ACK ); + + PORT_WRITE(out_RETIRE_ACK [i], ACK ); + PORT_WRITE(out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL [i], LOAD_STORE_QUEUE_POINTER_VAL); + PORT_WRITE(out_RETIRE_REGISTER_TRANSLATION_VAL [i], REGISTER_TRANSLATION_VAL ); + + previous_transaction = VAL and ACK; + } + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_allocation.cpp (revision 88) @@ -0,0 +1,41 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::statistics_allocation" + void Rename_unit_Glue::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Rename_unit_Glue,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Rename_unit_Glue", + param_statistics); + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,41 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::statistics_deallocation" + void Rename_unit_Glue::statistics_deallocation (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + + log_printf(INFO,Rename_unit_Glue,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_transition.cpp (revision 88) @@ -0,0 +1,41 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::transition" + void Rename_unit_Glue::transition (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl.cpp (revision 88) @@ -0,0 +1,50 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::vhdl" + void Rename_unit_Glue::vhdl (void) + { + log_begin(Rename_unit_Glue,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_body.cpp (revision 88) @@ -0,0 +1,37 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::vhdl_body" + void Rename_unit_Glue::vhdl_body (Vhdl * & vhdl) + { + log_begin(Rename_unit_Glue,FUNCTION); + vhdl->set_body (""); + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/src/Rename_unit_Glue_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,36 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { +namespace rename_unit_glue { + + +#undef FUNCTION +#define FUNCTION "Rename_unit_Glue::vhdl_declaration" + void Rename_unit_Glue::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Rename_unit_Glue,FUNCTION); + log_end(Rename_unit_Glue,FUNCTION); + }; + +}; // end namespace rename_unit_glue +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Rename_unit_LIBRARY) + +DIR_LIBRARY = $(Rename_unit_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Rename_unit_library + +library_clean : Rename_unit_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,20 @@ +Rename_unit +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_inst_decod [0] [nb_front_end] +1 1 +1 # nb_inst_insert +1 1 +1 # nb_inst_retire +1 1 +1 # nb_load_store_queue +2 2 +1 # size_store_queue [0] [nb_load_store_queue] +1 1 +1 # size_load_queue [0] [nb_load_store_queue] +0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] +1 1 +1 # rename_select_priority +1 1 +1 # rename_select_load_balancing +1 1 +1 # rename_select_nb_front_end_select +1 1 +1 # max_branch_speculated +32 32 +1 # size_general_data +64 64 +1 # nb_general_register +4 4 +1 # nb_special_register +1 1 +1 # nb_reg_free +1 1 +1 # nb_bank +1 1 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_1a.cfg (revision 88) @@ -0,0 +1,20 @@ +Rename_unit +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +4 4 +1 # nb_inst_insert +4 4 +1 # nb_inst_retire +1 1 +1 # nb_load_store_queue +8 8 +1 # size_store_queue [0] [nb_load_store_queue] +8 8 +1 # size_load_queue [0] [nb_load_store_queue] +0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] +1 1 +1 # rename_select_priority +1 1 +1 # rename_select_load_balancing +1 1 +1 # rename_select_nb_front_end_select +4 4 +1 # max_branch_speculated +32 32 +1 # size_general_data +64 64 +1 # nb_general_register +8 8 +1 # nb_special_register +2 2 +1 # nb_reg_free +4 8 *2 # nb_bank +4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4a.cfg (revision 88) @@ -0,0 +1,23 @@ +Rename_unit +1 1 +1 # nb_front_end +4 4 +1 # nb_context [0] [nb_front_end] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +4 4 +1 # nb_inst_insert +4 4 +1 # nb_inst_retire +1 1 +1 # nb_load_store_queue +8 8 +1 # size_store_queue [0] [nb_load_store_queue] +8 8 +1 # size_load_queue [0] [nb_load_store_queue] +0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] +0 0 +1 # link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context] +0 0 +1 # link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context] +0 0 +1 # link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context] +1 1 +1 # rename_select_priority +1 1 +1 # rename_select_load_balancing +1 1 +1 # rename_select_nb_front_end_select +4 4 +1 # max_branch_speculated +32 32 +1 # size_general_data +256 256 +1 # nb_general_register +16 16 +1 # nb_special_register +2 2 +1 # nb_reg_free +8 8 *2 # nb_bank +4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/config-thread_4b.cfg (revision 88) @@ -0,0 +1,25 @@ +Rename_unit +1 1 +1 # nb_front_end +4 4 +1 # nb_context [0] [nb_front_end] +4 4 +1 # nb_inst_decod [0] [nb_front_end] +4 4 +1 # nb_inst_insert +4 4 +1 # nb_inst_retire +2 2 +1 # nb_load_store_queue +8 8 +1 # size_store_queue [0] [nb_load_store_queue] +4 4 +1 # size_store_queue [1] [nb_load_store_queue] +8 8 +1 # size_load_queue [0] [nb_load_store_queue] +4 4 +1 # size_load_queue [1] [nb_load_store_queue] +0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] +1 1 +1 # link_load_store_unit_with_thread [0][1] [nb_front_end][nb_context] +1 1 +1 # link_load_store_unit_with_thread [0][2] [nb_front_end][nb_context] +0 0 +1 # link_load_store_unit_with_thread [0][3] [nb_front_end][nb_context] +1 1 +1 # rename_select_priority +1 1 +1 # rename_select_load_balancing +1 1 +1 # rename_select_nb_front_end_select +4 4 +1 # max_branch_speculated +32 32 +1 # size_general_data +256 256 +1 # nb_general_register +16 16 +1 # nb_special_register +2 2 +1 # nb_reg_free +8 8 *2 # nb_bank +4 4 +1 # size_read_counter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h (revision 88) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,162 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h" + +#define NB_PARAMS 14 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_decod [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_insert (uint32_t )\n")); + err (_(" * nb_inst_retire (uint32_t )\n")); + err (_(" * nb_load_store_queue (uint32_t )\n")); + err (_(" * size_store_queue [nb_load_store_queue] (uint32_t )\n")); + err (_(" * size_load_queue [nb_load_store_queue] (uint32_t )\n")); + err (_(" * link_load_store_unit_with_thread [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * rename_select_priority (Tpriority_t )\n")); + err (_(" * rename_select_load_balancing (Tload_balancing_t)\n")); + err (_(" * rename_select_nb_front_end_select (uint32_t )\n")); + err (_(" * max_branch_speculated (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * nb_general_register (uint32_t )\n")); + err (_(" * nb_special_register (uint32_t )\n")); + err (_(" * nb_reg_free (uint32_t )\n")); + err (_(" * nb_bank (uint32_t )\n")); + err (_(" * size_read_counter (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+2*_nb_front_end)) + usage (argc, argv); + + uint32_t _sum_nb_context = 0; + + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + uint32_t * _nb_inst_decod = new uint32_t [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_context [i] = fromString(argv[x++]); + _sum_nb_context += _nb_context [i]; + } + for (uint32_t i=0; i<_nb_front_end; i++) + _nb_inst_decod [i] = fromString(argv[x++]); + uint32_t _nb_inst_insert = fromString(argv[x++]); + uint32_t _nb_inst_retire = fromString(argv[x++]); + uint32_t _nb_load_store_queue = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+2*_nb_front_end+2*_nb_load_store_queue+_sum_nb_context)) + usage (argc, argv); + + uint32_t * _size_store_queue = new uint32_t [_nb_load_store_queue]; + uint32_t * _size_load_queue = new uint32_t [_nb_load_store_queue]; + + for (uint32_t i=0; i<_nb_load_store_queue; i++) + _size_store_queue [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_load_store_queue; i++) + _size_load_queue [i] = fromString(argv[x++]); + + uint32_t ** _link_load_store_unit_with_thread = new uint32_t * [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _link_load_store_unit_with_thread [i] = new uint32_t [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; j++) + _link_load_store_unit_with_thread [i][j] = fromString(argv[x++]); + } + + Tpriority_t _rename_select_priority = fromString(argv[x++]); + Tload_balancing_t _rename_select_load_balancing = fromString(argv[x++]); + uint32_t _rename_select_nb_front_end_select = fromString(argv[x++]); + uint32_t _max_branch_speculated = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _nb_general_register = fromString(argv[x++]); + uint32_t _nb_special_register = fromString(argv[x++]); + uint32_t _nb_reg_free = fromString(argv[x++]); + uint32_t _nb_bank = fromString(argv[x++]); + uint32_t _size_read_counter = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters * param = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters + (_nb_front_end , + _nb_context , + _nb_inst_decod , + _nb_inst_insert , + _nb_inst_retire , + _nb_load_store_queue , + _size_store_queue , + _size_load_queue , + _link_load_store_unit_with_thread , + _rename_select_priority , + _rename_select_load_balancing , + _rename_select_nb_front_end_select, + _max_branch_speculated , + _size_general_data , + _nb_general_register , + _nb_special_register , + _nb_reg_free , + _nb_bank , + _size_read_counter , + true //is_toplevel + ); + + msg(_("%s"),param->print(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Rename_unit : no error"); + else + TEST_KO("Rename_unit : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + for (uint32_t i=0; i<_nb_front_end; i++) + delete [] _link_load_store_unit_with_thread [i]; + delete [] _link_load_store_unit_with_thread; + + delete [] _nb_inst_decod ; + delete [] _size_store_queue; + delete [] _size_load_queue ; + delete [] _nb_context ; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,378 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Rename_unit * _Rename_unit = new Rename_unit + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_RENAME_IN_VAL ," in_RENAME_IN_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_RENAME_IN_ACK ,"out_RENAME_IN_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_FRONT_END_ID ," in_RENAME_IN_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_CONTEXT_ID ," in_RENAME_IN_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_DEPTH ," in_RENAME_IN_DEPTH ",Tdepth_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_TYPE ," in_RENAME_IN_TYPE ",Ttype_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_OPERATION ," in_RENAME_IN_OPERATION ",Toperation_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RA ," in_RENAME_IN_READ_RA ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RA ," in_RENAME_IN_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RB ," in_RENAME_IN_READ_RB ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RB ," in_RENAME_IN_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_READ_RC ," in_RENAME_IN_READ_RC ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RC ," in_RENAME_IN_NUM_REG_RC ",Tspecial_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RD ," in_RENAME_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RD ," in_RENAME_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_WRITE_RE ," in_RENAME_IN_WRITE_RE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RE ," in_RENAME_IN_NUM_REG_RE ",Tspecial_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_EXCEPTION_USE ," in_RENAME_IN_EXCEPTION_USE ",Texception_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_EXCEPTION ," in_RENAME_IN_EXCEPTION ",Texception_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC1_SC_SIGNAL(out_INSERT_VAL ,"out_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_ACK ," in_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_FRONT_END_ID ,"out_INSERT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_CONTEXT_ID ,"out_INSERT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_DEPTH ,"out_INSERT_DEPTH ",Tdepth_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_TYPE ,"out_INSERT_TYPE ",Ttype_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_OPERATION ,"out_INSERT_OPERATION ",Toperation_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,"out_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,"out_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_ADDRESS ,"out_INSERT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,"out_INSERT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_IMMEDIAT ,"out_INSERT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,"out_INSERT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"out_INSERT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_READ_RA ,"out_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RA_LOG ,"out_INSERT_NUM_REG_RA_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,"out_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_READ_RB ,"out_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RB_LOG ,"out_INSERT_NUM_REG_RB_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,"out_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_READ_RC ,"out_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RC_LOG ,"out_INSERT_NUM_REG_RC_LOG ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,"out_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RD ,"out_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,"out_INSERT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,"out_INSERT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,"out_INSERT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RE ,"out_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,"out_INSERT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,"out_INSERT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,"out_INSERT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_EXCEPTION_USE ,"out_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_EXCEPTION ,"out_INSERT_EXCEPTION ",Texception_t ,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ," in_RETIRE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ," in_RETIRE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); +//ALLOC1_SC_SIGNAL( in_RETIRE_TYPE ," in_RETIRE_TYPE ",Ttype_t ,_param->_nb_inst_retire); +//ALLOC1_SC_SIGNAL( in_RETIRE_OPERATION ," in_RETIRE_OPERATION ",Toperation_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_USE_STORE_QUEUE ," in_RETIRE_USE_STORE_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ," in_RETIRE_USE_LOAD_QUEUE ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE," in_RETIRE_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ," in_RETIRE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_EVENT_STATE ," in_RETIRE_EVENT_STATE ",Tevent_state_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_READ_RB ," in_RETIRE_READ_RB ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ," in_RETIRE_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_READ_RC ," in_RETIRE_READ_RC ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ," in_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ," in_RETIRE_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD ," in_RETIRE_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW ," in_RETIRE_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RE ," in_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ," in_RETIRE_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD ," in_RETIRE_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ," in_RETIRE_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_retire); + ALLOC2_SC_SIGNAL( in_SPR_READ_SR ," in_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Rename_unit.\n"),name.c_str()); + + (*(_Rename_unit->in_CLOCK)) (*(in_CLOCK)); + (*(_Rename_unit->in_NRESET)) (*(in_NRESET)); + + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit,out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_Rename_unit, in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_INSERT_ACK ,_param->_nb_inst_insert); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_DEPTH ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_TYPE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_OPERATION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_ADDRESS ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_EXCEPTION ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_READ_RA ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RA_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_READ_RB ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RB_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_READ_RC ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RC_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_WRITE_RD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_WRITE_RE ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_VAL ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire); +//INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_TYPE ,_param->_nb_inst_retire); +//INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_OPERATION ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_READ_RB ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_READ_RC ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_WRITE_RE ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_retire); + INSTANCE1_SC_SIGNAL(_Rename_unit, in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire); + + INSTANCE2_SC_SIGNAL(_Rename_unit,in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); + + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + + DELETE1_SC_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_DEPTH ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_TYPE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_OPERATION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_EXCEPTION ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RA_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RB_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RC_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert); + + DELETE1_SC_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire); +//DELETE1_SC_SIGNAL( in_RETIRE_TYPE ,_param->_nb_inst_retire); +//DELETE1_SC_SIGNAL( in_RETIRE_OPERATION ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_retire); + DELETE1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire); + + DELETE2_SC_SIGNAL(in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); + } +#endif + + delete _Rename_unit; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Rename_unit.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Rename_unit.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/Rename_unit.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Rename_unit} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h (revision 88) @@ -0,0 +1,110 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Parameters.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t * _nb_inst_decod ;//[nb_front_end] + public : uint32_t _nb_inst_insert ; + public : uint32_t _nb_inst_retire ; + public : uint32_t _nb_load_store_queue ; + public : uint32_t * _size_store_queue ;//[nb_load_store_queue] + public : uint32_t * _size_load_queue ;//[nb_load_store_queue] + public : uint32_t ** _link_load_store_unit_with_thread ;//[nb_front_end][nb_context] + public : Tpriority_t _rename_select_priority ; + public : Tload_balancing_t _rename_select_load_balancing ; + public : uint32_t _rename_select_nb_front_end_select; + public : uint32_t _max_branch_speculated ; +//public : uint32_t _size_general_data ; + public : uint32_t _nb_general_register ; + public : uint32_t _nb_special_register ; + public : uint32_t _nb_reg_free ; + public : uint32_t _nb_bank ; + public : uint32_t _size_read_counter ; + +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_depth ; + +//public : uint32_t _have_port_front_end_id ; +//public : uint32_t _have_port_context_id ; +//public : uint32_t _have_port_load_queue_ptr ; +//public : bool _have_port_depth ; + + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_select ::Parameters * _param_rename_select ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::Parameters * _param_register_translation_unit; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::load_store_pointer_unit ::Parameters * _param_load_store_pointer_unit ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue ::Parameters * _param_glue ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t * nb_inst_decod , + uint32_t nb_inst_insert , + uint32_t nb_inst_retire , + uint32_t nb_load_store_queue , + uint32_t * size_store_queue , + uint32_t * size_load_queue , + uint32_t ** link_load_store_unit_with_thread , + Tpriority_t rename_select_priority , + Tload_balancing_t rename_select_load_balancing , + uint32_t rename_select_nb_front_end_select, + uint32_t max_branch_speculated , + uint32_t size_general_data , + uint32_t nb_general_register , + uint32_t nb_special_register , + uint32_t nb_reg_free , + uint32_t nb_bank , + uint32_t size_read_counter , + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters & x); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 88) @@ -0,0 +1,228 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_Rename_unit_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_rename_unit_Rename_unit_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h" +#include "Behavioural/include/Types.h" + +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/include/Register_translation_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/include/Load_Store_pointer_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue/include/Rename_unit_Glue.h" + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + + class Rename_unit +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_VAL ;//[nb_front_end][nb_inst_decod] + public : SC_OUT(Tcontrol_t ) *** out_RENAME_IN_ACK ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontext_t ) *** in_RENAME_IN_FRONT_END_ID ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontext_t ) *** in_RENAME_IN_CONTEXT_ID ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tdepth_t ) *** in_RENAME_IN_DEPTH ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Ttype_t ) *** in_RENAME_IN_TYPE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Toperation_t ) *** in_RENAME_IN_OPERATION ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_READ_RA ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_IN_NUM_REG_RA ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_READ_RB ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_IN_NUM_REG_RB ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_READ_RC ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tspecial_address_t) *** in_RENAME_IN_NUM_REG_RC ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_WRITE_RD ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_IN_NUM_REG_RD ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_WRITE_RE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tspecial_address_t) *** in_RENAME_IN_NUM_REG_RE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Texception_t ) *** in_RENAME_IN_EXCEPTION_USE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Texception_t ) *** in_RENAME_IN_EXCEPTION ;//[nb_front_end][nb_inst_decod] + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_INSERT_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_FRONT_END_ID ;//[nb_inst_insert] + public : SC_OUT(Tcontext_t ) ** out_INSERT_CONTEXT_ID ;//[nb_inst_insert] + public : SC_OUT(Tdepth_t ) ** out_INSERT_DEPTH ;//[nb_inst_insert] + public : SC_OUT(Ttype_t ) ** out_INSERT_TYPE ;//[nb_inst_insert] + public : SC_OUT(Toperation_t ) ** out_INSERT_OPERATION ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] + public : SC_OUT(Tlsq_ptr_t ) ** out_INSERT_STORE_QUEUE_PTR_WRITE;//[nb_inst_insert] + public : SC_OUT(Tlsq_ptr_t ) ** out_INSERT_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RA ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RA_LOG ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RA_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RB ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RB_LOG ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RB_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_READ_RC ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RC_LOG ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RC_PHY ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_WRITE_RD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_LOG ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_PHY_OLD ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_NUM_REG_RD_PHY_NEW ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_WRITE_RE ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_LOG ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_PHY_OLD ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_NUM_REG_RE_PHY_NEW ;//[nb_inst_insert] + public : SC_OUT(Texception_t ) ** out_INSERT_EXCEPTION_USE ;//[nb_inst_insert] + public : SC_OUT(Texception_t ) ** out_INSERT_EXCEPTION ;//[nb_inst_insert] + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_RETIRE_VAL ;//[nb_inst_retire] + public : SC_OUT(Tcontrol_t ) ** out_RETIRE_ACK ;//[nb_inst_retire] + public : SC_IN (Tcontext_t ) ** in_RETIRE_FRONT_END_ID ;//[nb_inst_retire] + public : SC_IN (Tcontext_t ) ** in_RETIRE_CONTEXT_ID ;//[nb_inst_retire] +//public : SC_IN (Ttype_t ) ** in_RETIRE_TYPE ;//[nb_inst_retire] +//public : SC_IN (Toperation_t ) ** in_RETIRE_OPERATION ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_USE_STORE_QUEUE ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_USE_LOAD_QUEUE ;//[nb_inst_retire] + public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_STORE_QUEUE_PTR_WRITE;//[nb_inst_retire] + public : SC_IN (Tlsq_ptr_t ) ** in_RETIRE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_retire] + public : SC_IN (Tevent_state_t ) ** in_RETIRE_EVENT_STATE ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RA ;//[nb_inst_retire] + public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RA_PHY ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RB ;//[nb_inst_retire] + public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RB_PHY ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_READ_RC ;//[nb_inst_retire] + public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RC_PHY ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RD ;//[nb_inst_retire] + public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_LOG ;//[nb_inst_retire] + public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_PHY_OLD ;//[nb_inst_retire] + public : SC_IN (Tgeneral_address_t) ** in_RETIRE_NUM_REG_RD_PHY_NEW ;//[nb_inst_retire] + public : SC_IN (Tcontrol_t ) ** in_RETIRE_WRITE_RE ;//[nb_inst_retire] + public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_LOG ;//[nb_inst_retire] + public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_OLD ;//[nb_inst_retire] + public : SC_IN (Tspecial_address_t) ** in_RETIRE_NUM_REG_RE_PHY_NEW ;//[nb_inst_retire] + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tspr_t ) *** in_SPR_READ_SR ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_select ::Rename_select * _component_rename_select ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::Register_translation_unit * _component_register_translation_unit; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::load_store_pointer_unit ::Load_Store_pointer_unit * _component_load_store_pointer_unit ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue ::Rename_unit_Glue * _component_glue ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Rename_unit); +#endif + public : Rename_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Rename_unit (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +# endif +#endif + +#if VHDL + public : void vhdl (void); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 88) @@ -0,0 +1,184 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t * nb_inst_decod , + uint32_t nb_inst_insert , + uint32_t nb_inst_retire , + uint32_t nb_load_store_queue , + uint32_t * size_store_queue , + uint32_t * size_load_queue , + uint32_t ** link_load_store_unit_with_thread , + Tpriority_t rename_select_priority , + Tload_balancing_t rename_select_load_balancing , + uint32_t rename_select_nb_front_end_select, + uint32_t max_branch_speculated , + uint32_t size_general_data , + uint32_t nb_general_register , + uint32_t nb_special_register , + uint32_t nb_reg_free , + uint32_t nb_bank , + uint32_t size_read_counter , + bool is_toplevel) + { + log_begin(Rename_unit,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_inst_decod = nb_inst_decod ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_retire = nb_inst_retire ; + _nb_load_store_queue = nb_load_store_queue ; + _size_store_queue = size_store_queue ; + _size_load_queue = size_load_queue ; + _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; + _rename_select_priority = rename_select_priority ; + _rename_select_load_balancing = rename_select_load_balancing ; + _rename_select_nb_front_end_select = rename_select_nb_front_end_select; + _max_branch_speculated = max_branch_speculated ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_reg_free = nb_reg_free ; + _nb_bank = nb_bank ; + _size_read_counter = size_read_counter ; + + uint32_t size_special_register = log2(_nb_special_register); + + test(); + + log_printf(TRACE,Rename_unit,FUNCTION,_("Creation : _param_rename_select.")); + _param_rename_select = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_select::Parameters + ( + _nb_front_end , + _nb_context , + _max_branch_speculated, + _size_general_data , + _nb_inst_insert , + _nb_inst_decod , + _rename_select_nb_front_end_select , + _rename_select_priority , + _rename_select_load_balancing + ); + + log_printf(TRACE,Rename_unit,FUNCTION,_("Creation : _param_register_translation_unit.")); + _param_register_translation_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::Parameters + ( + _nb_front_end , + _nb_context , + _nb_general_register , + _nb_special_register , + _nb_inst_insert , + _nb_inst_retire , + _nb_reg_free , + _nb_bank , + _size_read_counter + ); + + log_printf(TRACE,Rename_unit,FUNCTION,_("Creation : _param_load_store_pointer_unit.")); + _param_load_store_pointer_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::load_store_pointer_unit::Parameters + ( + _nb_front_end , + _nb_context , + _nb_load_store_queue , + _size_store_queue , + _size_load_queue , + _link_load_store_unit_with_thread, + _nb_inst_insert , + _nb_inst_retire + ); + + log_printf(TRACE,Rename_unit,FUNCTION,_("Creation : _param_glue.")); + _param_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Parameters + ( + _nb_front_end , + _nb_context , + _nb_inst_insert , + _nb_inst_retire , + _size_general_data , + _size_special_register + ); + + if (is_toplevel) + { + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(max(_nb_context,_nb_front_end)); + _size_store_queue_ptr = log2(max(_size_store_queue,nb_load_store_queue)); + _size_load_queue_ptr = log2(max(_size_load_queue ,nb_load_store_queue)); + _size_general_register = log2(_nb_general_register); + _size_special_register = size_special_register; + _size_depth = log2(_max_branch_speculated); + _size_general_data = size_general_data ; + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy(); + } + + log_end(Rename_unit,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Rename_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Rename_unit,FUNCTION); +// test(); +// log_end(Rename_unit,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Rename_unit::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Rename_unit,FUNCTION); + + delete _param_rename_select ; + delete _param_register_translation_unit; + delete _param_load_store_pointer_unit ; + delete _param_glue ; + + log_end(Rename_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit::copy" + void Parameters::copy (void) + { + log_begin(Rename_unit,FUNCTION); + + COPY(_param_rename_select ); + COPY(_param_register_translation_unit); + COPY(_param_load_store_pointer_unit ); + COPY(_param_glue ); + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,39 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Rename_unit,FUNCTION); + + Parameters_test test ("Rename_unit"); + + log_end(Rename_unit,FUNCTION); + + return test; + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,107 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Rename_unit,FUNCTION); + + XML xml ("rename_unit"); + + xml.balise_open("rename_unit"); + xml.singleton_begin("nb_front_end "); xml.attribut("value",toString(_nb_front_end )); xml.singleton_end(); + xml.singleton_begin("nb_inst_insert "); xml.attribut("value",toString(_nb_inst_insert )); xml.singleton_end(); + xml.singleton_begin("nb_inst_retire "); xml.attribut("value",toString(_nb_inst_retire )); xml.singleton_end(); + xml.singleton_begin("nb_load_store_queue "); xml.attribut("value",toString(_nb_load_store_queue )); xml.singleton_end(); + xml.singleton_begin("rename_select_priority "); xml.attribut("value",toString(_rename_select_priority )); xml.singleton_end(); + xml.singleton_begin("rename_select_load_balancing "); xml.attribut("value",toString(_rename_select_load_balancing )); xml.singleton_end(); + xml.singleton_begin("rename_select_nb_front_end_select"); xml.attribut("value",toString(_rename_select_nb_front_end_select)); xml.singleton_end(); + xml.singleton_begin("max_branch_speculated "); xml.attribut("value",toString(_max_branch_speculated )); xml.singleton_end(); + xml.singleton_begin("size_general_data "); xml.attribut("value",toString(_size_general_data )); xml.singleton_end(); + xml.singleton_begin("nb_general_register "); xml.attribut("value",toString(_nb_general_register )); xml.singleton_end(); + xml.singleton_begin("nb_special_register "); xml.attribut("value",toString(_nb_special_register )); xml.singleton_end(); + xml.singleton_begin("nb_reg_free "); xml.attribut("value",toString(_nb_reg_free )); xml.singleton_end(); + xml.singleton_begin("nb_bank "); xml.attribut("value",toString(_nb_bank )); xml.singleton_end(); + xml.singleton_begin("size_read_counter "); xml.attribut("value",toString(_size_read_counter )); xml.singleton_end(); + + for (uint32_t i=0;i<_nb_front_end; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","front_end"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + xml.singleton_begin("nb_context "); xml.attribut("value",toString(_nb_context [i])); xml.singleton_end(); + xml.singleton_begin("nb_inst_decod "); xml.attribut("value",toString(_nb_inst_decod [i])); xml.singleton_end(); + + for (uint32_t j=0;j<_nb_context[i]; j++) + { + xml. balise_open_begin("component"); + xml. attribut("type","context"); + xml. attribut("id" ,toString(j)); + xml. balise_open_end(); + + xml.singleton_begin("link_load_store_unit_with_thread "); xml.attribut("value",toString(_link_load_store_unit_with_thread [i][j])); xml.singleton_end(); + + xml. balise_close(); + } + + xml. balise_close(); + } + + for (uint32_t i=0;i<_nb_load_store_queue; i++) + { + xml. balise_open_begin("component"); + xml. attribut("type","load_store_queue"); + xml. attribut("id" ,toString(i)); + xml. balise_open_end(); + + xml.singleton_begin("size_store_queue "); xml.attribut("value",toString(_size_store_queue [i])); xml.singleton_end(); + xml.singleton_begin("size_load_queue "); xml.attribut("value",toString(_size_load_queue [i])); xml.singleton_end(); + + xml. balise_close(); + } + + xml.balise_close(); + + log_end(Rename_unit,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters & x) + { + log_begin(Rename_unit,FUNCTION); + + output_stream << x.print(0); + + log_end(Rename_unit,FUNCTION); + + return output_stream; + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit.cpp (revision 88) @@ -0,0 +1,117 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::Rename_unit" + Rename_unit::Rename_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Rename_unit,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Rename_unit == true + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Rename_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Rename_unit::~Rename_unit" + Rename_unit::~Rename_unit (void) + { + log_begin(Rename_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 88) @@ -0,0 +1,805 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + + +#undef FUNCTION +#define FUNCTION "Rename_unit::allocation" + void Rename_unit::allocation + ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Rename_unit,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Rename_unit" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("rename_in", IN, EAST, "output of decod's stage", _param->_nb_front_end, _param->_nb_inst_decod[it1]); + + _ALLOC2_VALACK_IN ( in_RENAME_IN_VAL ,VAL, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_VALACK_OUT(out_RENAME_IN_ACK ,ACK, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("insert",OUT,WEST , "Instruction with physical register", _param->_nb_inst_insert); + + ALLOC1_VALACK_OUT(out_INSERT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_INSERT_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_INSERT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT(out_INSERT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT(out_INSERT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT(out_INSERT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT(out_INSERT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_INSERT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_INSERT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception_use ); + ALLOC1_SIGNAL_OUT(out_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_LOG ,"num_reg_ra_log" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_LOG ,"num_reg_rb_log" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_LOG ,"num_reg_rc_log" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_INSERT_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); + } + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("retire",IN ,NORTH, "Retire instruction, update renaming structure.", _param->_nb_inst_retire); + + ALLOC1_VALACK_IN ( in_RETIRE_VAL ,VAL); + ALLOC1_VALACK_OUT(out_RETIRE_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_RETIRE_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_IN ( in_RETIRE_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); +// ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); +// ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_IN ( in_RETIRE_EVENT_STATE ,"event_state" ,Tevent_state_t ,_param->_size_event_state ); + ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RA ,"read_ra" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RA_PHY ,"num_reg_ra_phy" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RB ,"read_rb" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RB_PHY ,"num_reg_rb_phy" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_READ_RC ,"read_rc" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RC_PHY ,"num_reg_rc_phy" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_LOG ,"num_reg_rd_log" ,Tgeneral_address_t,_param->_size_general_register_logic); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_OLD ,"num_reg_rd_phy_old" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RD_PHY_NEW ,"num_reg_rd_phy_new" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_LOG ,"num_reg_re_log" ,Tspecial_address_t,_param->_size_special_register_logic); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_OLD ,"num_reg_re_phy_old" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_IN ( in_RETIRE_NUM_REG_RE_PHY_NEW ,"num_reg_re_phy_new" ,Tspecial_address_t,_param->_size_special_register ); + } + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_read", IN,NORTH, _("Special register"), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN (in_SPR_READ_SR ,"sr",Tspr_t ,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + std::string name; + + { + name = _name+"_rename_select"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Create : %s"),name.c_str()); + + _component_rename_select = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_select::Rename_select + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_rename_select + ,_usage); + + _component->set_component (_component_rename_select->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_register_translation_unit"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Create : %s"),name.c_str()); + + _component_register_translation_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::Register_translation_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_register_translation_unit + ,_usage); + + _component->set_component (_component_register_translation_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_load_store_pointer_unit"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Create : %s"),name.c_str()); + + _component_load_store_pointer_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::load_store_pointer_unit::Load_Store_pointer_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_load_store_pointer_unit + ,_usage); + + _component->set_component (_component_load_store_pointer_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_glue"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Create : %s"),name.c_str()); + + _component_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::rename_unit_glue::Rename_unit_Glue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_glue + ,_usage); + + _component->set_component (_component_glue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string src,dest; + + // =================================================================== + // =====[ rename_select ]============================================= + // =================================================================== + { + src = _name+"_rename_select"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_inst_decod[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"rename_in_"+toString(i)+"_"+toString(j), + dest,"rename_in_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_DEPTH" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_DEPTH" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_TYPE" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_TYPE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_OPERATION" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NO_EXECUTE" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NO_EXECUTE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT", + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT"); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IMMEDIAT" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_IMMEDIAT" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RA" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RA" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RB" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RB" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RC" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_READ_RC" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RD" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RE" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_EXCEPTION_USE", + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_EXCEPTION_USE"); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_EXCEPTION" , + dest, "in_RENAME_IN_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); + } + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"rename_out_"+toString(i), + dest,"insert_" +toString(i)); +#endif + + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NO_EXECUTE" , + dest,"out_INSERT_" +toString(i)+"_NO_EXECUTE" ); + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_IS_DELAY_SLOT", + dest,"out_INSERT_" +toString(i)+"_IS_DELAY_SLOT"); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_DEPTH" , + dest,"out_INSERT_" +toString(i)+"_DEPTH" ); + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_ADDRESS" , + dest,"out_INSERT_" +toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_HAS_IMMEDIAT", + dest,"out_INSERT_" +toString(i)+"_HAS_IMMEDIAT"); + PORT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_EXCEPTION_USE", + dest,"out_INSERT_" +toString(i)+"_EXCEPTION_USE"); + + dest = _name+"_register_translation_unit"; + +#ifdef POSITION + _component->interface_map (src ,"rename_out_"+toString(i), + dest,"rename_" +toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RA" , + dest, "in_RENAME_" +toString(i)+"_READ_RA" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RA", + dest, "in_RENAME_" +toString(i)+"_NUM_REG_RA_LOG"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RB" , + dest, "in_RENAME_" +toString(i)+"_READ_RB" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RB", + dest, "in_RENAME_" +toString(i)+"_NUM_REG_RB_LOG"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_READ_RC" , + dest, "in_RENAME_" +toString(i)+"_READ_RC" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RC", + dest, "in_RENAME_" +toString(i)+"_NUM_REG_RC_LOG"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RD" , + dest, "in_RENAME_" +toString(i)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RD", + dest, "in_RENAME_" +toString(i)+"_NUM_REG_RD_LOG"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_WRITE_RE" , + dest, "in_RENAME_" +toString(i)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+"_NUM_REG_RE", + dest, "in_RENAME_" +toString(i)+"_NUM_REG_RE_LOG"); + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"rename_out_"+toString(i), + dest,"insert_" +toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_VAL" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_VAL" ); + COMPONENT_MAP(_component,src , "in_RENAME_OUT_"+toString(i)+ "_ACK" , + dest,"out_INSERT_" +toString(i)+"_RENAME_SELECT_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_FRONT_END_ID" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_CONTEXT_ID" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_CONTEXT_ID" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_TYPE" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_TYPE" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_OPERATION" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_OPERATION" ); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_IMMEDIAT" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_IMMEDIAT" ); +// COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_EXCEPTION_USE", +// dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_EXCEPTION_USE"); + COMPONENT_MAP(_component,src ,"out_RENAME_OUT_"+toString(i)+ "_EXCEPTION" , + dest, "in_INSERT_" +toString(i)+"_RENAME_SELECT_EXCEPTION" ); + } + } + + // =================================================================== + // =====[ register_translation_unit ]================================= + // =================================================================== + { + src = _name+"_register_translation_unit"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name+"_rename_select"; + +#ifdef POSITION + _component->interface_map (src ,"rename_" +toString(i), + dest,"rename_out_"+toString(i)); +#endif + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(i), + dest,"insert_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_VAL" , + dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_VAL" ); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(i)+ "_ACK" , + dest, "in_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_FRONT_END_ID", + dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_FRONT_END_ID"); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(i)+ "_CONTEXT_ID" , + dest,"out_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_CONTEXT_ID" ); + + // in_RENAME_READ_RA - rename_select + // in_RENAME_NUM_REG_RA_LOG - rename_select + // in_RENAME_READ_RB - rename_select + // in_RENAME_NUM_REG_RB_LOG - rename_select + // in_RENAME_READ_RC - rename_select + // in_RENAME_NUM_REG_RC_LOG - rename_select + // in_RENAME_WRITE_RD - rename_select + // in_RENAME_NUM_REG_RD_LOG - rename_select + // in_RENAME_WRITE_RE - rename_select + // in_RENAME_NUM_REG_RE_LOG - rename_select + + } + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i), + dest,"insert_"+toString(i)); +#endif + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_VAL" , + dest,"out_INSERT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_ACK" , + dest, "in_INSERT_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_FRONT_END_ID" , + dest,"out_INSERT_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_CONTEXT_ID" , + dest,"out_INSERT_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RA" , + dest,"out_INSERT_"+toString(i)+"_READ_RA" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RA_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RA_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RA_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RB" , + dest,"out_INSERT_"+toString(i)+"_READ_RB" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RB_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RB_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RB_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_READ_RC" , + dest,"out_INSERT_"+toString(i)+"_READ_RC" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RC_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RC_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RC_PHY" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_WRITE_RD" , + dest,"out_INSERT_"+toString(i)+"_WRITE_RD" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_WRITE_RE" , + dest,"out_INSERT_"+toString(i)+"_WRITE_RE" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_LOG" , + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_LOG" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + + // HACK : use the field num_reg_re to pass the SM and SUMRA flag. + // cf : rename_unit_glue and functionnal_unit/Operation + dest = _name+"_glue"; + + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(i)+ "_NUM_REG_RE_PHY_NEW", + dest, "in_INSERT_"+toString(i)+"_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW"); + } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i), + dest,"retire_"+toString(i)); +#endif + + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_FRONT_END_ID" , + dest, "in_RETIRE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , + dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_EVENT_STATE" , + dest, "in_RETIRE_"+toString(i)+"_EVENT_STATE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_READ_RA" , + dest, "in_RETIRE_"+toString(i)+"_READ_RA" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RA_PHY" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RA_PHY" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_READ_RB" , + dest, "in_RETIRE_"+toString(i)+"_READ_RB" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RB_PHY" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RB_PHY" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_READ_RC" , + dest, "in_RETIRE_"+toString(i)+"_READ_RC" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RC_PHY" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RC_PHY" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RD" , + dest, "in_RETIRE_"+toString(i)+"_WRITE_RD" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_LOG" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_OLD"); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_NEW", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RD_PHY_NEW"); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_WRITE_RE" , + dest, "in_RETIRE_"+toString(i)+"_WRITE_RE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" , + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_LOG" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_OLD"); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_NEW", + dest, "in_RETIRE_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i), + dest,"retire_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL",dest,"out_RETIRE_"+toString(i)+"_REGISTER_TRANSLATION_VAL"); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK",dest, "in_RETIRE_"+toString(i)+"_REGISTER_TRANSLATION_ACK"); + } + } + + // =================================================================== + // =====[ load_store_pointer_unit ]=================================== + // =================================================================== + { + src = _name+"_load_store_pointer_unit"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i), + dest,"insert_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", + dest,"out_INSERT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , + dest,"out_INSERT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i), + dest,"insert_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+ "_VAL" , + dest,"out_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_VAL" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(i)+ "_ACK" , + dest, "in_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+ "_FRONT_END_ID", + dest,"out_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID"); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+ "_CONTEXT_ID" , + dest,"out_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+ "_TYPE" , + dest,"out_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_TYPE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+ "_OPERATION" , + dest,"out_INSERT_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_OPERATION" ); + } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i), + dest,"retire_"+toString(i)); +#endif + + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_FRONT_END_ID" , + dest, "in_RETIRE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_CONTEXT_ID" , + dest, "in_RETIRE_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_USE_STORE_QUEUE" , + dest, "in_RETIRE_"+toString(i)+"_USE_STORE_QUEUE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_USE_LOAD_QUEUE" , + dest, "in_RETIRE_"+toString(i)+"_USE_LOAD_QUEUE" ); + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", + dest, "in_RETIRE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , + dest, "in_RETIRE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i), + dest,"retire_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(i)+ "_VAL" , + dest,"out_RETIRE_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_VAL" ); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+ "_ACK" , + dest, "in_RETIRE_"+toString(i)+"_LOAD_STORE_QUEUE_POINTER_ACK" ); + //// in_RETIRE_TYPE - glue + //// in_RETIRE_OPERATION - glue + } + } + + // =================================================================== + // =====[ glue ]====================================================== + // =================================================================== + { + src = _name+"_glue"; + log_printf(TRACE,Rename_unit,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i), + dest,"insert_"+toString(i)); +#endif + + // //out_INSERT_VAL + // // in_INSERT_ACK + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_FRONT_END_ID" , + dest,"out_INSERT_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_CONTEXT_ID" , + dest,"out_INSERT_"+toString(i)+"_CONTEXT_ID" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_TYPE" , + dest,"out_INSERT_"+toString(i)+"_TYPE" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_OPERATION" , + dest,"out_INSERT_"+toString(i)+"_OPERATION" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_IMMEDIAT" , + dest,"out_INSERT_"+toString(i)+"_IMMEDIAT" ); +// PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_EXCEPTION_USE", +// dest,"out_INSERT_"+toString(i)+"_EXCEPTION_USE"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_EXCEPTION" , + dest,"out_INSERT_"+toString(i)+"_EXCEPTION" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW", + dest,"out_INSERT_"+toString(i)+"_NUM_REG_RE_PHY_NEW"); + + + // in_INSERT_RENAME_SELECT_VAL - rename_select + // out_INSERT_RENAME_SELECT_ACK - rename_select + // in_INSERT_RENAME_SELECT_FRONT_END_ID - rename_select + // in_INSERT_RENAME_SELECT_CONTEXT_ID - rename_select + // in_INSERT_RENAME_SELECT_TYPE - rename_select + // in_INSERT_RENAME_SELECT_OPERATION - rename_select + // in_INSERT_RENAME_SELECT_IMMEDIAT - rename_select +// // in_INSERT_RENAME_SELECT_EXCEPTION_USE - rename_select + // in_INSERT_RENAME_SELECT_EXCEPTION - rename_select + + // out_INSERT_REGISTER_TRANSLATION_VAL - register_translation_unit + // in_INSERT_REGISTER_TRANSLATION_ACK - register_translation_unit + // out_INSERT_REGISTER_TRANSLATION_FRONT_END_ID - register_translation_unit + // out_INSERT_REGISTER_TRANSLATION_CONTEXT_ID - register_translation_unit + // out_INSERT_REGISTER_TRANSLATION_NUM_REG_RE_PHY_NEW - register_translation_unit + + // out_INSERT_LOAD_STORE_QUEUE_POINTER_VAL - load_store_pointer_unit + // in_INSERT_LOAD_STORE_QUEUE_POINTER_ACK - load_store_pointer_unit + // out_INSERT_LOAD_STORE_QUEUE_POINTER_FRONT_END_ID - load_store_pointer_unit + // out_INSERT_LOAD_STORE_QUEUE_POINTER_CONTEXT_ID - load_store_pointer_unit + // out_INSERT_LOAD_STORE_QUEUE_POINTER_TYPE - load_store_pointer_unit + // out_INSERT_LOAD_STORE_QUEUE_POINTER_OPERATION - load_store_pointer_unit + } + + for (uint32_t i=0; i<_param->_nb_inst_retire; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(i), + dest,"retire_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_VAL", + dest, "in_RETIRE_"+toString(i)+"_VAL"); + PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_ACK", + dest,"out_RETIRE_"+toString(i)+"_ACK"); + + // out_RETIRE_LOAD_STORE_QUEUE_POINTER_VAL - load_store_pointer_unit + // in_RETIRE_LOAD_STORE_QUEUE_POINTER_ACK - load_store_pointer_unit + // //out_RETIRE_LOAD_STORE_QUEUE_POINTER_TYPE - load_store_pointer_unit + // //out_RETIRE_LOAD_STORE_QUEUE_POINTER_OPERATION - load_store_pointer_unit + // out_RETIRE_REGISTER_TRANSLATION_VAL - register_translation_unit + // in_RETIRE_REGISTER_TRANSLATION_ACK - register_translation_unit + } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"spr_read_"+toString(i)+"_"+toString(j), + dest,"spr_read_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_SPR_READ_"+toString(i)+"_"+toString(j)+"_SR", + dest, "in_SPR_READ_"+toString(i)+"_"+toString(j)+"_SR"); + } + } + + // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#if DEBUG_Rename_unit == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_deallocation.cpp (revision 88) @@ -0,0 +1,134 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::deallocation" + void Rename_unit::deallocation (void) + { + log_begin(Rename_unit,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_RENAME_IN_VAL ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL(out_RENAME_IN_ACK ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_FRONT_END_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_RENAME_IN_CONTEXT_ID ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_RENAME_IN_DEPTH ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_RENAME_IN_TYPE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_type ); + DELETE2_SIGNAL( in_RENAME_IN_OPERATION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_RENAME_IN_NO_EXECUTE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_ADDRESS ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_IMMEDIAT ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_RENAME_IN_READ_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RA ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_READ_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RB ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_READ_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RC ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_WRITE_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RD ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_general_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_WRITE_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IN_NUM_REG_RE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_special_register_logic); + DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION_USE ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception_use ); + DELETE2_SIGNAL( in_RENAME_IN_EXCEPTION ,_param->_nb_front_end, _param->_nb_inst_decod[it1],_param->_size_exception ); + + DELETE1_SIGNAL(out_INSERT_VAL ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_ACK ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_FRONT_END_ID ,_param->_nb_inst_insert,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_INSERT_CONTEXT_ID ,_param->_nb_inst_insert,_param->_size_context_id ); + DELETE1_SIGNAL(out_INSERT_DEPTH ,_param->_nb_inst_insert,_param->_size_depth ); + DELETE1_SIGNAL(out_INSERT_TYPE ,_param->_nb_inst_insert,_param->_size_type ); + DELETE1_SIGNAL(out_INSERT_OPERATION ,_param->_nb_inst_insert,_param->_size_operation ); + DELETE1_SIGNAL(out_INSERT_NO_EXECUTE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_IS_DELAY_SLOT ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_ADDRESS ,_param->_nb_inst_insert,_param->_size_general_data ); + DELETE1_SIGNAL(out_INSERT_HAS_IMMEDIAT ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_IMMEDIAT ,_param->_nb_inst_insert,_param->_size_general_data ); + DELETE1_SIGNAL(out_INSERT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_insert,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL(out_INSERT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_insert,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL(out_INSERT_EXCEPTION_USE ,_param->_nb_inst_insert,_param->_size_exception_use ); + DELETE1_SIGNAL(out_INSERT_EXCEPTION ,_param->_nb_inst_insert,_param->_size_exception ); + DELETE1_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert,_param->_size_general_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert,_param->_size_special_register_logic); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert,_param->_size_special_register ); + DELETE1_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert,_param->_size_special_register ); + + DELETE1_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_FRONT_END_ID ,_param->_nb_inst_retire,_param->_size_front_end_id ); + DELETE1_SIGNAL( in_RETIRE_CONTEXT_ID ,_param->_nb_inst_retire,_param->_size_context_id ); +// DELETE1_SIGNAL( in_RETIRE_TYPE ,_param->_nb_inst_retire,_param->_size_type ); +// DELETE1_SIGNAL( in_RETIRE_OPERATION ,_param->_nb_inst_retire,_param->_size_operation ); + DELETE1_SIGNAL( in_RETIRE_USE_STORE_QUEUE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_USE_LOAD_QUEUE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL( in_RETIRE_EVENT_STATE ,_param->_nb_inst_retire,_param->_size_event_state ); + DELETE1_SIGNAL( in_RETIRE_READ_RA ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_READ_RB ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_READ_RC ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire,_param->_size_special_register ); + DELETE1_SIGNAL( in_RETIRE_WRITE_RD ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_LOG ,_param->_nb_inst_retire,_param->_size_general_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_retire,_param->_size_general_register ); + DELETE1_SIGNAL( in_RETIRE_WRITE_RE ,_param->_nb_inst_retire,1 ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_LOG ,_param->_nb_inst_retire,_param->_size_special_register_logic); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_retire,_param->_size_special_register ); + DELETE1_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_retire,_param->_size_special_register ); + + DELETE2_SIGNAL(in_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _component_rename_select ; + delete _component_register_translation_unit; + delete _component_load_store_pointer_unit ; + delete _component_glue ; + + delete _component; + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::end_cycle" +void Rename_unit::end_cycle () + { + log_begin(Rename_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_allocation.cpp (revision 88) @@ -0,0 +1,44 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::statistics_allocation" + void Rename_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Rename_unit,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Rename_unit", + param_statistics); + + _stat->add_stat(_component_rename_select ->_stat); + _stat->add_stat(_component_register_translation_unit->_stat); + _stat->add_stat(_component_load_store_pointer_unit ->_stat); + _stat->add_stat(_component_glue ->_stat); + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::statistics_deallocation" + void Rename_unit::statistics_deallocation (void) + { + log_begin(Rename_unit,FUNCTION); + + log_printf(INFO,Rename_unit,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_transition.cpp (revision 88) @@ -0,0 +1,41 @@ +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::transition" + void Rename_unit::transition (void) + { + log_begin(Rename_unit,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +# endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_vhdl.cpp (revision 88) @@ -0,0 +1,45 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace rename_unit { + + +#undef FUNCTION +#define FUNCTION "Rename_unit::vhdl" + void Rename_unit::vhdl (void) + { + log_begin(Rename_unit,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Rename_unit,FUNCTION); + }; + +}; // end namespace rename_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(OOO_Engine_LIBRARY) + +DIR_LIBRARY = $(OOO_Engine_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : OOO_Engine_library + +library_clean : OOO_Engine_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/configuration.cfg (revision 88) @@ -0,0 +1,55 @@ +OOO_Engine +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_rename_unit +1 1 +1 # nb_execute_loop +1 1 +1 # nb_inst_decod [0] [nb_front_end] +1 1 +1 # nb_inst_insert [0] [nb_rename_unit] +1 1 +1 # nb_inst_retire [0] [nb_rename_unit] +1 1 +1 # nb_inst_issue +1 1 +1 # nb_inst_execute [0] [nb_execute_loop] +1 1 +1 # nb_inst_reexecute +1 1 +1 # nb_inst_commit +1 1 +1 # nb_inst_branch_complete +1 1 +1 # nb_branch_speculated [0][0] [nb_front_end][nb_context] +1 1 +1 # nb_rename_unit_select +1 1 +1 # nb_execute_loop_select +32 32 *2 # size_general_data +2 2 *2 # size_special_data +0 0 +1 # link_rename_unit_with_front_end [0] [nb_front_end] +1 1 +1 # size_re_order_buffer +1 1 +1 # nb_re_order_buffer_bank +1 1 +1 # commit_priority +1 1 +1 # commit_load_balancing +1 1 +1 # size_issue_queue +1 1 +1 # nb_issue_queue_bank +1 1 +1 # issue_priority +1 1 +1 # issue_load_balancing +1 1 +1 # table_routing [0][0] [nb_rename_unit][nb_inst_issue] +1 1 +1 # table_issue_type [0][TYPE_ALU ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SHIFT ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MOVE ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_TEST ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MUL ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_DIV ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_EXTEND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_FIND ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_SPECIAL] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_CUSTOM ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_BRANCH ] [nb_inst_issue][nb_type] +1 1 +1 # table_issue_type [0][TYPE_MEMORY ] [nb_inst_issue][nb_type] +1 1 +1 # size_reexecute_queue +1 1 +1 # reexecute_priority +1 1 +1 # reexecute_load_balancing +1 1 +1 # rename_select_priority [0] [nb_rename_unit] +1 1 +1 # rename_select_load_balancing [0] [nb_rename_unit] +1 1 +1 # rename_select_nb_front_end_select [0] [nb_rename_unit] +64 64 +1 # nb_general_register [0] [nb_rename_unit] +4 4 +1 # nb_special_register [0] [nb_rename_unit] +1 1 +1 # nb_reg_free [0] [nb_rename_unit] +1 1 +1 # nb_rename_unit_bank [0] [nb_rename_unit] +1 1 +1 # size_read_counter [0] [nb_rename_unit] +1 1 +1 # nb_load_store_queue [0] [nb_rename_unit] +2 2 +1 # size_store_queue [0][0] [nb_rename_unit][nb_load_store_queue] +1 1 +1 # size_load_queue [0][0] [nb_rename_unit][nb_load_store_queue] +0 0 +1 # link_load_store_unit_with_thread [0][0] [nb_front_end][nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h (revision 88) @@ -0,0 +1,33 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,387 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" + +#define NB_PARAMS 22 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_rename_unit (uint32_t )\n")); + err (_(" * nb_execute_loop (uint32_t )\n")); + err (_(" * nb_inst_decod [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_insert [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_inst_retire [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_inst_issue (uint32_t )\n")); + err (_(" * nb_inst_execute [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_inst_reexecute (uint32_t )\n")); + err (_(" * nb_inst_commit (uint32_t )\n")); + err (_(" * nb_inst_branch_complete (uint32_t )\n")); + err (_(" * nb_branch_speculated [nb_front_end][nb_context] (uint32_t )\n")); + err (_(" * nb_rename_unit_select (uint32_t )\n")); + err (_(" * nb_execute_loop_select (uint32_t )\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); + err (_(" * link_rename_unit_with_front_end [nb_front_end] (uint32_t )\n")); + err (_(" * size_re_order_buffer (uint32_t )\n")); + err (_(" * nb_re_order_buffer_bank (uint32_t )\n")); + err (_(" * commit_priority (Tpriority_t )\n")); + err (_(" * commit_load_balancing (Tload_balancing_t)\n")); + err (_(" * size_issue_queue (uint32_t )\n")); + err (_(" * nb_issue_queue_bank (uint32_t )\n")); + err (_(" * issue_priority (Tpriority_t )\n")); + err (_(" * issue_load_balancing (Tload_balancing_t)\n")); + err (_(" * table_routing [nb_rename_unit][nb_inst_issue] (bool )\n")); + err (_(" * table_issue_type [nb_inst_issue][nb_type] (bool )\n")); + err (_(" * TYPE_ALU \n")); + err (_(" * TYPE_SHIFT \n")); + err (_(" * TYPE_MOVE \n")); + err (_(" * TYPE_TEST \n")); + err (_(" * TYPE_MUL \n")); + err (_(" * TYPE_DIV \n")); + err (_(" * TYPE_EXTEND \n")); + err (_(" * TYPE_FIND \n")); + err (_(" * TYPE_SPECIAL\n")); + err (_(" * TYPE_CUSTOM \n")); + err (_(" * TYPE_BRANCH \n")); + err (_(" * TYPE_MEMORY \n")); + err (_(" * size_reexecute_queue (uint32_t )\n")); + err (_(" * reexecute_priority (Tpriority_t )\n")); + err (_(" * reexecute_load_balancing (Tload_balancing_t)\n")); + err (_(" * rename_select_priority [nb_rename_unit] (Tpriority_t )\n")); + err (_(" * rename_select_load_balancing [nb_rename_unit] (Tload_balancing_t)\n")); + err (_(" * rename_select_nb_front_end_select [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_general_register [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_special_register [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_reg_free [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_rename_unit_bank [nb_rename_unit] (uint32_t )\n")); + err (_(" * size_read_counter [nb_rename_unit] (uint32_t )\n")); + err (_(" * nb_load_store_queue [nb_rename_unit] (uint32_t )\n")); + err (_(" * size_store_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); + err (_(" * size_load_queue [nb_rename_unit][nb_load_store_queue] (uint32_t )\n")); + err (_(" * link_load_store_unit_with_thread [nb_front_end][nb_context] (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t _sum_nb_context = 0; + uint32_t _sum_nb_load_store_queue = 0; + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end)) + usage (argc, argv); + + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_context [i] = fromString(argv[x++]); + _sum_nb_context += _nb_context [i]; + } + uint32_t _nb_rename_unit = fromString(argv[x++]); + uint32_t _nb_execute_loop = fromString(argv[x++]); + uint32_t * _nb_inst_decod = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + _nb_inst_decod [i] = fromString(argv[x++]); + + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+12*_nb_rename_unit+_nb_execute_loop)) + usage (argc, argv); + + uint32_t * _nb_inst_insert = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_inst_retire = new uint32_t [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_inst_insert [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_inst_retire [i] = fromString(argv[x++]); + + uint32_t _nb_inst_issue = fromString(argv[x++]); + uint32_t * _nb_inst_execute = new uint32_t [_nb_execute_loop]; + for (uint32_t i=0; i<_nb_execute_loop; i++) + _nb_inst_execute [i] = fromString(argv[x++]); + uint32_t _nb_inst_reexecute = fromString(argv[x++]); + uint32_t _nb_inst_commit = fromString(argv[x++]); + uint32_t _nb_inst_branch_complete = fromString(argv[x++]); + uint32_t ** _nb_branch_speculated = new uint32_t * [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _nb_branch_speculated [i] = new uint32_t [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; j++) + _nb_branch_speculated [i][j] = fromString(argv[x++]); + } + uint32_t _nb_rename_unit_select = fromString(argv[x++]); + uint32_t _nb_execute_loop_select = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); + uint32_t _size_special_data = fromString(argv[x++]); + uint32_t * _link_rename_unit_with_front_end = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + _link_rename_unit_with_front_end [i] = fromString(argv[x++]); + uint32_t _size_re_order_buffer = fromString(argv[x++]); + uint32_t _nb_re_order_buffer_bank = fromString(argv[x++]); + Tpriority_t _commit_priority = fromString(argv[x++]); + Tload_balancing_t _commit_load_balancing = fromString(argv[x++]); + uint32_t _size_issue_queue = fromString(argv[x++]); + uint32_t _nb_issue_queue_bank = fromString(argv[x++]); + Tpriority_t _issue_priority = fromString(argv[x++]); + Tload_balancing_t _issue_load_balancing = fromString(argv[x++]); + bool ** _table_routing = new bool * [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _table_routing [i] = new bool [_nb_inst_issue]; + for (uint32_t j=0; j<_nb_inst_issue; j++) + _table_routing [i][j] = fromString(argv[x++]); + } + + if (argc <= static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue)) + usage (argc, argv); + + bool ** _table_issue_type = new bool * [_nb_inst_issue]; + for (uint32_t i=0; i<_nb_inst_issue; i++) + { + _table_issue_type [i] = new bool [MAX_TYPE]; + for (uint32_t j=0; j(argv[x++]); + _table_issue_type [i][TYPE_SHIFT ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MOVE ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_TEST ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MUL ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_DIV ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_EXTEND ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_FIND ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_SPECIAL] = fromString(argv[x++]); + _table_issue_type [i][TYPE_CUSTOM ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_BRANCH ] = fromString(argv[x++]); + _table_issue_type [i][TYPE_MEMORY ] = fromString(argv[x++]); + } + + uint32_t _size_reexecute_queue = fromString(argv[x++]); + Tpriority_t _reexecute_priority = fromString(argv[x++]); + Tload_balancing_t _reexecute_load_balancing = fromString(argv[x++]); + + Tpriority_t * _rename_select_priority = new Tpriority_t [_nb_rename_unit]; + Tload_balancing_t * _rename_select_load_balancing = new Tload_balancing_t [_nb_rename_unit]; + uint32_t * _rename_select_nb_front_end_select = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_general_register = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_special_register = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_reg_free = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_rename_unit_bank = new uint32_t [_nb_rename_unit]; + uint32_t * _size_read_counter = new uint32_t [_nb_rename_unit]; + uint32_t * _nb_load_store_queue = new uint32_t [_nb_rename_unit]; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + _rename_select_priority [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _rename_select_load_balancing [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _rename_select_nb_front_end_select [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_general_register [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_special_register [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_reg_free [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _nb_rename_unit_bank [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + _size_read_counter [i] = fromString(argv[x++]); + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _nb_load_store_queue [i] = fromString(argv[x++]); + _sum_nb_load_store_queue += _nb_load_store_queue [i]; + } + + if (argc != static_cast(2+NB_PARAMS+3*_nb_front_end+2*_sum_nb_context+11*_nb_rename_unit+_nb_execute_loop+_nb_rename_unit*_nb_inst_issue+12*_nb_inst_issue+2*_sum_nb_load_store_queue)) + usage (argc, argv); + + + uint32_t ** _size_store_queue = new uint32_t * [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _size_store_queue [i] = new uint32_t [_nb_load_store_queue[i]]; + for (uint32_t j=0; j<_nb_load_store_queue[i]; j++) + _size_store_queue [i][j] = fromString(argv[x++]); + } + + uint32_t ** _size_load_queue = new uint32_t * [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _size_load_queue [i] = new uint32_t [_nb_load_store_queue[i]]; + for (uint32_t j=0; j<_nb_load_store_queue[i]; j++) + _size_load_queue [i][j] = fromString(argv[x++]); + } + + uint32_t ** _link_load_store_unit_with_thread = new uint32_t * [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _link_load_store_unit_with_thread [i] = new uint32_t [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; j++) + _link_load_store_unit_with_thread [i][j] = fromString(argv[x++]); + } + + bool *** _implement_group = new bool ** [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _implement_group [i] = new bool * [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; j++) + { + _implement_group [i][j] = new bool [NB_GROUP]; + + for (uint32_t k=0; kprint(0).c_str()); + + test (name,param); + + delete param; + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("OOO_Engine : no error"); + else + TEST_KO("OOO_Engine : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + for (uint32_t i=0; i<_nb_front_end; i++) + { + for (uint32_t j=0; j<_nb_context[i]; j++) + delete [] _implement_group [i][j]; + delete [] _implement_group [i]; + } + delete [] _implement_group; + + for (uint32_t i=0; i<_nb_front_end; i++) + delete [] _link_load_store_unit_with_thread [i]; + delete [] _link_load_store_unit_with_thread; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + delete [] _size_load_queue [i]; + delete [] _size_load_queue; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + delete []_size_store_queue [i]; + delete []_size_store_queue; + + delete [] _nb_load_store_queue ; + delete [] _size_read_counter ; + delete [] _nb_rename_unit_bank ; + delete [] _nb_reg_free ; + delete [] _nb_special_register ; + delete [] _nb_general_register ; + delete [] _rename_select_nb_front_end_select ; + delete [] _rename_select_load_balancing ; + delete [] _rename_select_priority ; + + for (uint32_t i=0; i<_nb_inst_issue; i++) + delete [] _table_issue_type [i]; + delete [] _table_issue_type; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + delete [] _table_routing [i]; + delete [] _table_routing; + + delete [] _link_rename_unit_with_front_end; + + for (uint32_t i=0; i<_nb_front_end; i++) + delete [] _nb_branch_speculated [i]; + delete [] _nb_branch_speculated; + + delete [] _nb_inst_execute; + delete [] _nb_inst_retire ; + delete [] _nb_inst_insert ; + delete [] _nb_inst_decod ; + delete [] _nb_context ; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,493 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + OOO_Engine * _OOO_Engine = new OOO_Engine + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC2_SC_SIGNAL( in_RENAME_VAL ," in_RENAME_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL(out_RENAME_ACK ,"out_RENAME_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_FRONT_END_ID ," in_RENAME_FRONT_END_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_CONTEXT_ID ," in_RENAME_CONTEXT_ID ",Tcontext_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_DEPTH ," in_RENAME_DEPTH ",Tdepth_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_TYPE ," in_RENAME_TYPE ",Ttype_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_OPERATION ," in_RENAME_OPERATION ",Toperation_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IMMEDIAT ," in_RENAME_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_READ_RA ," in_RENAME_READ_RA ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NUM_REG_RA ," in_RENAME_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_READ_RB ," in_RENAME_READ_RB ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NUM_REG_RB ," in_RENAME_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_READ_RC ," in_RENAME_READ_RC ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NUM_REG_RC ," in_RENAME_NUM_REG_RC ",Tspecial_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_WRITE_RD ," in_RENAME_WRITE_RD ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NUM_REG_RD ," in_RENAME_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_WRITE_RE ," in_RENAME_WRITE_RE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_NUM_REG_RE ," in_RENAME_NUM_REG_RE ",Tspecial_address_t,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_EXCEPTION_USE ," in_RENAME_EXCEPTION_USE ",Texception_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_EXCEPTION ," in_RENAME_EXCEPTION ",Texception_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + ALLOC1_SC_SIGNAL(out_ISSUE_VAL ,"out_ISSUE_VAL ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL( in_ISSUE_ACK ," in_ISSUE_ACK ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_FRONT_END_ID ,"out_ISSUE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_CONTEXT_ID ,"out_ISSUE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_PACKET_ID ,"out_ISSUE_PACKET_ID ",Tpacket_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_TYPE ,"out_ISSUE_TYPE ",Ttype_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_OPERATION ,"out_ISSUE_OPERATION ",Toperation_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_STORE_QUEUE_PTR_WRITE ,"out_ISSUE_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_LOAD_QUEUE_PTR_WRITE ,"out_ISSUE_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_HAS_IMMEDIAT ,"out_ISSUE_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_IMMEDIAT ,"out_ISSUE_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_READ_RA ,"out_ISSUE_READ_RA ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_NUM_REG_RA ,"out_ISSUE_NUM_REG_RA ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_READ_RB ,"out_ISSUE_READ_RB ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_NUM_REG_RB ,"out_ISSUE_NUM_REG_RB ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_READ_RC ,"out_ISSUE_READ_RC ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_NUM_REG_RC ,"out_ISSUE_NUM_REG_RC ",Tspecial_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_WRITE_RD ,"out_ISSUE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_NUM_REG_RD ,"out_ISSUE_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_WRITE_RE ,"out_ISSUE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_issue); + ALLOC1_SC_SIGNAL(out_ISSUE_NUM_REG_RE ,"out_ISSUE_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_issue); + + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_VAL ," in_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL(out_EXECUTE_LOOP_ACK ,"out_EXECUTE_LOOP_ACK ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ," in_EXECUTE_LOOP_FRONT_END_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ," in_EXECUTE_LOOP_CONTEXT_ID ",Tcontext_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ," in_EXECUTE_LOOP_PACKET_ID ",Tpacket_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_TYPE ," in_EXECUTE_LOOP_TYPE ",Ttype_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_OPERATION ," in_EXECUTE_LOOP_OPERATION ",Toperation_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_FLAGS ," in_EXECUTE_LOOP_FLAGS ",Tspecial_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ," in_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + ALLOC1_SC_SIGNAL(out_INSERT_VAL ,"out_INSERT_VAL ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_ACK ," in_INSERT_ACK ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RD_USE ,"out_INSERT_RD_USE ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RD_NUM_REG ,"out_INSERT_RD_NUM_REG ",Tgeneral_address_t,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RE_USE ,"out_INSERT_RE_USE ",Tcontrol_t ,_param->_sum_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,"out_INSERT_RE_NUM_REG ",Tspecial_address_t,_param->_sum_inst_insert); + +// ALLOC1_SC_SIGNAL(out_RETIRE_VAL ,"out_RETIRE_VAL ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL( in_RETIRE_ACK ," in_RETIRE_ACK ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,"out_RETIRE_RD_OLD_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,"out_RETIRE_RD_OLD_NUM_REG ",Tgeneral_address_t,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,"out_RETIRE_RD_NEW_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,"out_RETIRE_RD_NEW_NUM_REG ",Tgeneral_address_t,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,"out_RETIRE_RE_OLD_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,"out_RETIRE_RE_OLD_NUM_REG ",Tspecial_address_t,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,"out_RETIRE_RE_NEW_USE ",Tcontrol_t ,_param->_sum_inst_retire); +// ALLOC1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,"out_RETIRE_RE_NEW_NUM_REG ",Tspecial_address_t,_param->_sum_inst_retire); + + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,"out_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ," in_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,"out_BRANCH_COMPLETE_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,"out_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,"out_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ," in_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); + + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_VAL ,"out_COMMIT_EVENT_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ACK ," in_COMMIT_EVENT_ACK ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ,"out_COMMIT_EVENT_FRONT_END_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ,"out_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_DEPTH ,"out_COMMIT_EVENT_DEPTH ",Tdepth_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_TYPE ,"out_COMMIT_EVENT_TYPE ",Tevent_type_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,"out_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ,"out_COMMIT_EVENT_ADDRESS ",Taddress_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); + + ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL( in_SPR_EVENT_VAL ," in_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_EVENT_ACK ,"out_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EPCR ," in_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ," in_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR ," in_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ," in_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ," in_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,"out_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,"out_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL(out_SPR_SR_IEE ,"out_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_SR_EPH ,"out_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _OOO_Engine.\n"),name.c_str()); + + (*(_OOO_Engine->in_CLOCK)) (*(in_CLOCK)); + (*(_OOO_Engine->in_NRESET)) (*(in_NRESET)); + + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_RENAME_ACK ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_CONTEXT_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + if (_param->_have_port_depth) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_DEPTH ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_TYPE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_OPERATION ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_READ_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NUM_REG_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_READ_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NUM_REG_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_READ_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NUM_REG_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_WRITE_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NUM_REG_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_WRITE_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_NUM_REG_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_EXCEPTION_USE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_RENAME_EXCEPTION ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_VAL ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_ISSUE_ACK ,_param->_nb_inst_issue); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_FRONT_END_ID ,_param->_nb_inst_issue); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_CONTEXT_ID ,_param->_nb_inst_issue); + if (_param->_have_port_rob_ptr) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_PACKET_ID ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_TYPE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_OPERATION ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + if (_param->_have_port_load_queue_ptr) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_HAS_IMMEDIAT ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_IMMEDIAT ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_READ_RA ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_NUM_REG_RA ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_READ_RB ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_NUM_REG_RB ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_READ_RC ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_NUM_REG_RC ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_WRITE_RD ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_NUM_REG_RD ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_WRITE_RE ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_ISSUE_NUM_REG_RE ,_param->_nb_inst_issue); + + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_front_end_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_context_id) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + if (_param->_have_port_rob_ptr) + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_INSERT_VAL ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_INSERT_ACK ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_INSERT_RD_USE ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_INSERT_RE_USE ,_param->_sum_inst_insert); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); + +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_VAL ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine, in_RETIRE_ACK ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); +// INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); + + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue); + + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_VAL ); + INSTANCE_SC_SIGNAL (_OOO_Engine, in_COMMIT_EVENT_ACK ); + if (_param->_have_port_front_end_id) + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_FRONT_END_ID ); + if (_param->_have_port_context_id) + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_CONTEXT_ID ); + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_DEPTH ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_TYPE ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_IS_DELAY_SLOT ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EPCR ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_ADDRESS_EEAR ); + + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_EVENT_IS_DS_TAKE ,_param->_nb_front_end,_param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_SPR_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_EPCR ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_EEAR ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_SR_DSX ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end,_param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + if (_param->_have_port_depth) + INSTANCE_SC_SIGNAL(_OOO_Engine, in_DEPTH_MIN [i][j]); + INSTANCE2_SC_SIGNAL(_OOO_Engine, in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_OOO_Engine,out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE2_SC_SIGNAL( in_RENAME_VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL(out_RENAME_ACK ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_DEPTH ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_TYPE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_OPERATION ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_READ_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NUM_REG_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_READ_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NUM_REG_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_READ_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NUM_REG_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_WRITE_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NUM_REG_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_WRITE_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_NUM_REG_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_EXCEPTION_USE ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + DELETE2_SC_SIGNAL( in_RENAME_EXCEPTION ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + DELETE1_SC_SIGNAL(out_ISSUE_VAL ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL( in_ISSUE_ACK ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_FRONT_END_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_CONTEXT_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_PACKET_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_TYPE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_OPERATION ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_HAS_IMMEDIAT ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_IMMEDIAT ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_READ_RA ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_NUM_REG_RA ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_READ_RB ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_NUM_REG_RB ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_READ_RC ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_NUM_REG_RC ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_WRITE_RD ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_NUM_REG_RD ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_WRITE_RE ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_ISSUE_NUM_REG_RE ,_param->_nb_inst_issue); + + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL(out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + DELETE2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + DELETE1_SC_SIGNAL(out_INSERT_VAL ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_ACK ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RD_USE ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RE_USE ,_param->_sum_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); + +// DELETE1_SC_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); +// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); + + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue); + + DELETE_SC_SIGNAL (out_COMMIT_EVENT_VAL ); + DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ACK ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_DEPTH ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_TYPE ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ); + DELETE_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ); + + DELETE2_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1]); + } +#endif + + delete _OOO_Engine; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libSpecial_Register_unit.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/Makefile.deps (revision 88) @@ -0,0 +1,38 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Special_Register_unit = yes + +ifndef Behavioural +include $(DIR_MORPHEO)/Behavioural/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Special_Register_unit_DIR = $(DIR_MORPHEO)/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit + +#-----[ Library ]------------------------------------------ + +Special_Register_unit_LIBRARY = -lSpecial_Register_unit \ + $(Behavioural_LIBRARY) + +Special_Register_unit_DIR_LIBRARY = -L$(Special_Register_unit_DIR)/lib \ + $(Behavioural_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Special_Register_unit_library : + @\ + $(MAKE) Behavioural_library; \ + $(MAKE) --directory=$(Special_Register_unit_DIR) --makefile=Makefile; + +Special_Register_unit_library_clean : + @\ + $(MAKE) Behavioural_library_clean; \ + $(MAKE) --directory=$(Special_Register_unit_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Special_Register_unit_LIBRARY) + +DIR_LIBRARY = $(Special_Register_unit_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Special_Register_unit_library + +library_clean : Special_Register_unit_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,4 @@ +Special_Register_unit +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_inst_reexecute Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1024 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; +using namespace morpheo::behavioural::core::multi_ooo_engine; +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine; + +using namespace morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit; + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,109 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h" + +#define NB_PARAMS 2 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * nb_front_end (uint32_t)\n")); + err (_(" * nb_context [nb_front_end] (uint32_t)\n")); + err (_(" * nb_inst_reexecute (uint32_t)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + uint32_t _nb_front_end = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+_nb_front_end)) + usage (argc, argv); + + uint32_t * _nb_context = new uint32_t [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + _nb_context [i] = fromString(argv[x++]); + + uint32_t _nb_inst_reexecute = fromString(argv[x++]); + + bool *** _implement_group = new bool ** [_nb_front_end]; + for (uint32_t i=0; i<_nb_front_end; i++) + { + _implement_group [i] = new bool * [_nb_context[i]]; + for (uint32_t j=0; j<_nb_context[i]; j++) + { + _implement_group [i][j] = new bool [NB_GROUP]; + + for (uint32_t k=0; kprint(0).c_str()); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Special_Register_unit : no error"); + else + TEST_KO("Special_Register_unit : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + for (uint32_t i=0; i<_nb_front_end; i++) + { + for (uint32_t j=0; j<_nb_context[i]; j++) + delete [] _implement_group [i][j]; + delete [] _implement_group [i]; + } + delete [] _implement_group; + + delete [] _nb_context; + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,335 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Special_Register_unit * _Special_Register_unit = new Special_Register_unit + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_VAL ," in_SPR_ACCESS_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_ACCESS_ACK ,"out_SPR_ACCESS_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID," in_SPR_ACCESS_FRONT_END_ID",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ," in_SPR_ACCESS_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WEN ," in_SPR_ACCESS_WEN ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ," in_SPR_ACCESS_NUM_GROUP ",Tspr_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ," in_SPR_ACCESS_NUM_REG ",Tspr_address_t,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WDATA ," in_SPR_ACCESS_WDATA ",Tspr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,"out_SPR_ACCESS_RDATA ",Tspr_t ,_param->_nb_inst_reexecute); + ALLOC1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,"out_SPR_ACCESS_INVALID ",Tcontrol_t ,_param->_nb_inst_reexecute); + ALLOC2_SC_SIGNAL(out_SPR_READ_SR ,"out_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_VAL ," in_SPR_COMMIT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_COMMIT_ACK ,"out_SPR_COMMIT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ," in_SPR_COMMIT_SR_F_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F ," in_SPR_COMMIT_SR_F ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ," in_SPR_COMMIT_SR_CY_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ," in_SPR_COMMIT_SR_CY ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ," in_SPR_COMMIT_SR_OV_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ," in_SPR_COMMIT_SR_OV ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + ALLOC2_SC_SIGNAL( in_SPR_EVENT_VAL ," in_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL(out_SPR_EVENT_ACK ,"out_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EPCR ," in_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ," in_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR ," in_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ," in_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ," in_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Special_Register_unit.\n"),name.c_str()); + + (*(_Special_Register_unit->in_CLOCK)) (*(in_CLOCK)); + (*(_Special_Register_unit->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute); + if (_param->_have_port_front_end_id) + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute); + if (_param->_have_port_context_id) + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute); + INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute); + + INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]); + + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]); + INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + const int32_t percent_transaction_spr_access = 75; + const int32_t percent_transaction_spr_commit = 75; + const int32_t percent_transaction_spr_event = 75; + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + Tspr_t sr [_param->_nb_front_end][_param->_max_nb_context]; + Tspr_t dccr [_param->_nb_front_end][_param->_max_nb_context]; + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + sr [i][j] = 0x00008001; + dccr [i][j] = 0x0; + TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]); + } + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration_nb_front_end; + Tcontext_t context = rand()%_param->_nb_context[front_end]; + uint32_t port = rand()%_param->_nb_inst_reexecute; + uint32_t config = rand()%3; + Tcontrol_t wen = rand()%2; + Tspr_t wdata = rand(); + { + in_SPR_ACCESS_VAL [port]->write((rand()%100)write(front_end); + in_SPR_ACCESS_CONTEXT_ID [port]->write(context); + + switch (config) + { + case 0 : + wen = 0; + in_SPR_ACCESS_NUM_GROUP [port]->write(0); + in_SPR_ACCESS_NUM_REG [port]->write(17); + break; + case 1 : + in_SPR_ACCESS_NUM_GROUP [port]->write(3); + in_SPR_ACCESS_NUM_REG [port]->write(0); + break; + case 2 : + in_SPR_ACCESS_NUM_GROUP [port]->write(5); + in_SPR_ACCESS_NUM_REG [port]->write(1); + break; + } + + in_SPR_ACCESS_WEN [port]->write(wen); + in_SPR_ACCESS_WDATA [port]->write(wdata); + } + + { + in_SPR_COMMIT_VAL [front_end][context]->write((rand()%100)write((rand()%100)write((rand()%100)write((rand()%100)write(rand()%2); + in_SPR_COMMIT_SR_CY [front_end][context]->write(rand()%2); + in_SPR_COMMIT_SR_OV [front_end][context]->write(rand()%2); + } + + { + in_SPR_EVENT_VAL [front_end][context]->write((rand()%100)write(rand()); + in_SPR_EVENT_EEAR_WEN [front_end][context]->write(rand()%2); + in_SPR_EVENT_EEAR [front_end][context]->write(rand()); + in_SPR_EVENT_SR_DSX [front_end][context]->write(rand()%2); + in_SPR_EVENT_SR_TO_ESR [front_end][context]->write(rand()%2); + } + + SC_START(0); + + if (in_SPR_ACCESS_VAL [port]->read() and out_SPR_ACCESS_ACK [port]->read()) + { + LABEL("SPR_ACCESS [%d] - Transaction accepted.",port); + LABEL(" * front_end : %d" ,(unsigned int)front_end); + LABEL(" * context : %d" ,(unsigned int)context ); + LABEL(" * config : %d" ,(unsigned int)config ); + LABEL(" * wen : %d" ,(unsigned int)wen ); + LABEL(" * wdata : %d" ,(unsigned int)wdata&0xff ); + + switch (config) + { + case 0 : + TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),sr[front_end][context]); + TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0); + break; + case 1 : + if (sr[front_end][context] & 1) + { + TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),dccr[front_end][context]&0xff); + TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0); + + if (wen) + dccr[front_end][context] = wdata; + } + else + TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1); + break; + case 2 : + TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1); + break; + } + } + + if (in_SPR_COMMIT_VAL [front_end][context]->read() and out_SPR_COMMIT_ACK [front_end][context]->read()) + { + LABEL("SPR_COMMIT [%d][%d] - Transaction accepted.",front_end,context); + LABEL(" * cy_val : %d",in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read()); + LABEL(" * cy : %d",in_SPR_COMMIT_SR_CY [front_end][context]->read()); + LABEL(" * ov_val : %d",in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read()); + LABEL(" * ov : %d",in_SPR_COMMIT_SR_OV [front_end][context]->read()); + LABEL(" * f_val : %d",in_SPR_COMMIT_SR_F_VAL [front_end][context]->read()); + LABEL(" * f : %d",in_SPR_COMMIT_SR_F [front_end][context]->read()); + LABEL(" * sr (old) : 0x%d",sr[front_end][context]); + if (in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read()) + CHANGE_FLAG(sr[front_end][context], 10, in_SPR_COMMIT_SR_CY [front_end][context]->read()); + + if (in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read()) + CHANGE_FLAG(sr[front_end][context], 11, in_SPR_COMMIT_SR_OV [front_end][context]->read()); + + if (in_SPR_COMMIT_SR_F_VAL [front_end][context]->read()) + CHANGE_FLAG(sr[front_end][context], 9, in_SPR_COMMIT_SR_F [front_end][context]->read()); + LABEL(" * sr (new) : 0x%d",sr[front_end][context]); + } + + if (in_SPR_EVENT_VAL [front_end][context]->read() and out_SPR_EVENT_ACK [front_end][context]->read()) + { + LABEL("SPR_EVENT [%d][%d] - Transaction accepted.",front_end,context); + + CHANGE_FLAG(sr[front_end][context], 13, in_SPR_EVENT_SR_DSX [front_end][context]->read()); + } + + SC_START(1); + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]); + + in_SPR_ACCESS_VAL [port]->write(0); + in_SPR_COMMIT_VAL [front_end][context]->write(0); + } + + /******************************************************** + * Simulation - End + ********************************************************/ + + TEST_OK ("End of Simulation"); + delete _time; + + msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL( in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL( in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute); + DELETE1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute); + + DELETE2_SC_SIGNAL(out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]); + + DELETE2_SC_SIGNAL( in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]); + + DELETE2_SC_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]); + DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]); + } +#endif + + delete _Special_Register_unit; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Special_Register_unit.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Special_Register_unit.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/Special_Register_unit.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Special_Register_unit} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h (revision 88) @@ -0,0 +1,65 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_inst_reexecute ; + public : bool *** _implement_group ;//[nb_front_end][nb_context][NB_GROUP] + + public : uint32_t _max_nb_context ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +// +//public : bool _have_port_front_end_id; +//public : bool _have_port_context_id ; + + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_inst_reexecute , + bool *** implement_group , + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters & x); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 88) @@ -0,0 +1,670 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_SPR_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_SPR_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include "Behavioural/include/SPR.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + //---------------------------------------------------------- + // [x][x] GENERIC + //---------------------------------------------------------- + class GENERIC : public morpheo::behavioural::SPR + { + public : Tspr_t x : 32; + + public : GENERIC(uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) {}; + + public : void reset (void ) + { + x = 0; + }; + public : Tspr_t read (void ) + { + return x=0; + }; + public : void write (Tspr_t x) + { + this->x = x; + }; + }; + + //---------------------------------------------------------- + // [0][0] VR + //---------------------------------------------------------- + class VR : public morpheo::behavioural::SPR + { + public : const Tspr_t ver : 8; + public : const Tspr_t _res :10; + public : const Tspr_t cfg : 8; + public : const Tspr_t rev : 8; + + public : VR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + // SPR (), + ver (0), + _res (0), + cfg (0), + rev (0){}; + + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((ver << 24) | + (cfg << 16) | + (rev << 0)); + } + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][1] UPR + //---------------------------------------------------------- + class UPR : public morpheo::behavioural::SPR + { + public : const Tspr_t cup : 8; + public : const Tspr_t _res : 8; + public : const Tspr_t ttp : 1; + public : const Tspr_t pmp : 1; + public : const Tspr_t picp : 1; + public : const Tspr_t pcup : 1; + public : const Tspr_t dup : 1; + public : const Tspr_t mp : 1; + public : const Tspr_t imp : 1; + public : const Tspr_t dmp : 1; + public : const Tspr_t icp : 1; + public : const Tspr_t dcp : 1; + public : const Tspr_t up : 1; + + public : UPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + SPR (), + cup (0), + _res (0), + ttp (0), + pmp (0), + picp (0), + pcup (0), + dup (0), + mp (0), + imp (0), + dmp (0), + icp (0), + dcp (0), + up (0) + {}; + + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((cup << 24) | + (ttp << 10) | + (pmp << 9) | + (picp << 8) | + (pcup << 7) | + (dup << 6) | + (mp << 5) | + (imp << 4) | + (dmp << 3) | + (icp << 2) | + (dcp << 1) | + (up << 0)); + } + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][2] CPUCFGR + //---------------------------------------------------------- + class CPUCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 22; + public : const Tspr_t ov64s : 1; + public : const Tspr_t of64s : 1; + public : const Tspr_t of32s : 1; + public : const Tspr_t ob64s : 1; + public : const Tspr_t ob32s : 1; + public : const Tspr_t cgf : 1; + public : const Tspr_t nsdf : 1; + + public : CPUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + ov64s (0), + of64s (0), + of32s (0), + ob64s (0), + ob32s (0), + cgf (0), + nsdf (0) + {}; + + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((ov64s << 9) | + (of64s << 8) | + (of32s << 7) | + (ob64s << 6) | + (ob32s << 5) | + (cgf << 4) | + (nsdf << 0) ); + } + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][3] DMMUCFGR + //---------------------------------------------------------- + class DMMUCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 20; + public : const Tspr_t htr : 1; + public : const Tspr_t teiri : 1; + public : const Tspr_t pri : 1; + public : const Tspr_t cri : 1; + public : const Tspr_t nae : 3; + public : const Tspr_t nts : 3; + public : const Tspr_t ntw : 2; + + public : DMMUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + htr (0), + teiri (0), + pri (0), + cri (0), + nae (0), + nts (0), + ntw (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((htr << 11) | + (teiri << 10) | + (pri << 9) | + (cri << 8) | + (nae << 5) | + (nts << 2) | + (ntw << 0) ); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][4] IMMUCFGR + //---------------------------------------------------------- + class IMMUCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 20; + public : const Tspr_t htr : 1; + public : const Tspr_t teiri : 1; + public : const Tspr_t pri : 1; + public : const Tspr_t cri : 1; + public : const Tspr_t nae : 3; + public : const Tspr_t nts : 3; + public : const Tspr_t ntw : 2; + + public : IMMUCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + htr (0), + teiri (0), + pri (0), + cri (0), + nae (0), + nts (0), + ntw (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((htr << 11) | + (teiri << 10) | + (pri << 9) | + (cri << 8) | + (nae << 5) | + (nts << 2) | + (ntw << 0) ); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][5] DCCFGR + //---------------------------------------------------------- + class DCCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 17; + public : const Tspr_t cbwbri : 1; + public : const Tspr_t cbfri : 1; + public : const Tspr_t cblri : 1; + public : const Tspr_t cbpri : 1; + public : const Tspr_t cbiri : 1; + public : const Tspr_t ccri : 1; + public : const Tspr_t cws : 1; + public : const Tspr_t cbs : 1; + public : const Tspr_t ncs : 4; + public : const Tspr_t ncw : 3; + + public : DCCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + cbwbri (0), + cbfri (0), + cblri (0), + cbpri (0), + cbiri (0), + ccri (0), + cws (0), + cbs (0), + ncs (0), + ncw (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((cbwbri << 14) | + (cbfri << 13) | + (cblri << 12) | + (cbpri << 11) | + (cbiri << 10) | + (ccri << 9) | + (cws << 8) | + (cbs << 7) | + (ncs << 3) | + (ncw << 0) ); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][6] ICCFGR + //---------------------------------------------------------- + class ICCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res1 : 19; + public : const Tspr_t cblri : 1; + public : const Tspr_t cbpri : 1; + public : const Tspr_t cbiri : 1; + public : const Tspr_t ccri : 1; + public : const Tspr_t _res2 : 1; + public : const Tspr_t cbs : 1; + public : const Tspr_t ncs : 4; + public : const Tspr_t ncw : 3; + + public : ICCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res1 (0), + cblri (0), + cbpri (0), + cbiri (0), + ccri (0), + _res2 (0), + cbs (0), + ncs (0), + ncw (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((cblri << 12) | + (cbpri << 11) | + (cbiri << 10) | + (ccri << 9) | + (cbs << 7) | + (ncs << 3) | + (ncw << 0) ); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][7] DCFGR + //---------------------------------------------------------- + class DCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 28; + public : const Tspr_t wpci : 1; + public : const Tspr_t ndp : 3; + + public : DCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + wpci (0), + ndp (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((wpci << 3) | + (ndp << 0) ); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][8] PCCFGR + //---------------------------------------------------------- + class PCCFGR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 29; + public : const Tspr_t npc : 3; + + public : PCCFGR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + npc (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((npc << 0)); + }; + public : void write (Tspr_t x) {}; // All bit field is Read Only + }; + + //---------------------------------------------------------- + // [0][16] NPC + //---------------------------------------------------------- + class NPC : public GENERIC + { + public : NPC (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][17] SR + //---------------------------------------------------------- + class SR : public morpheo::behavioural::SPR + { + public : Tspr_t cid : 4; + public : const Tspr_t _res : 11; + public : Tspr_t sumra : 1; + public : const Tspr_t fo : 1; + public : Tspr_t eph : 1; + public : Tspr_t dsx : 1; + public : Tspr_t ove : 1; + public : Tspr_t ov : 1; + public : Tspr_t cy : 1; + public : Tspr_t f : 1; + public : Tspr_t ce : 1; + public : Tspr_t lee : 1; + public : Tspr_t ime : 1; + public : Tspr_t dme : 1; + public : Tspr_t ice : 1; + public : Tspr_t dce : 1; + public : Tspr_t iee : 1; + public : Tspr_t tee : 1; + public : Tspr_t sm : 1; + + public : SR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + fo (1) + {}; + public : void reset (void ) + { + cid = 0; + sumra = 0; + eph = 0; + dsx = 0; + ove = 0; + ov = 0; + cy = 0; + f = 0; + ce = 0; + lee = 0; + ime = 0; + dme = 0; + ice = 0; + dce = 0; + iee = 0; + tee = 0; + sm = 1; + }; + public : Tspr_t read (void ) + { + return ((cid << 28) | + (sumra << 16) | + (fo << 15) | + (eph << 14) | + (dsx << 13) | + (ove << 12) | + (ov << 11) | + (cy << 10) | + (f << 9) | + (ce << 8) | + (lee << 7) | + (ime << 6) | + (dme << 5) | + (ice << 4) | + (dce << 3) | + (iee << 2) | + (tee << 1) | + (sm << 0) ); + }; + public : void write (Tspr_t x) + { + cid = x >> 28; + sumra = x >> 16; + eph = x >> 14; + dsx = x >> 13; + ove = x >> 12; + ov = x >> 11; + cy = x >> 10; + f = x >> 9; + ce = x >> 8; + lee = x >> 7; + ime = x >> 6; + dme = x >> 5; + ice = x >> 4; + dce = x >> 3; + iee = x >> 2; + tee = x >> 1; + sm = x >> 0; + }; + }; + + //---------------------------------------------------------- + // [0][18] PPC + //---------------------------------------------------------- + class PPC : public GENERIC + { + public : PPC (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][19] CID + //---------------------------------------------------------- + class CID : public GENERIC + { + public : CID (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][20] FPCSR + //---------------------------------------------------------- + class FPCSR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 20; + public : Tspr_t dzf : 1; + public : Tspr_t inf : 1; + public : Tspr_t ivf : 1; + public : Tspr_t ixf : 1; + public : Tspr_t zf : 1; + public : Tspr_t qnf : 1; + public : Tspr_t snf : 1; + public : Tspr_t unf : 1; + public : Tspr_t ovf : 1; + public : Tspr_t rm : 2; + public : Tspr_t fpee : 1; + + public : FPCSR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0) + {}; + public : void reset (void ) + { + dzf = 0; + inf = 0; + ivf = 0; + ixf = 0; + zf = 0; + qnf = 0; + snf = 0; + unf = 0; + ovf = 0; + rm = 0; + fpee = 0; + }; + public : Tspr_t read (void ) + { + return ((dzf << 11) | + (inf << 10) | + (ivf << 9) | + (ixf << 8) | + (zf << 7) | + (qnf << 6) | + (snf << 5) | + (unf << 4) | + (ovf << 3) | + (rm << 1) | + (fpee << 0) ); + }; + public : void write (Tspr_t x) + { + dzf = x >> 11; + inf = x >> 10; + ivf = x >> 9; + ixf = x >> 8; + zf = x >> 7; + qnf = x >> 6; + snf = x >> 5; + unf = x >> 4; + ovf = x >> 3; + rm = x >> 1; + fpee = x >> 0; + }; + }; + + //---------------------------------------------------------- + // [0][32] EPCR + //---------------------------------------------------------- + class EPCR : public GENERIC + { + public : EPCR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][48] EEAR + //---------------------------------------------------------- + class EEAR : public GENERIC + { + public : EEAR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][64] ESR + //---------------------------------------------------------- + class ESR : public GENERIC + { + public : ESR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [0][1024] GPR + //---------------------------------------------------------- + class GPR : public GENERIC + { + public : GPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [3][0] DCCR + //---------------------------------------------------------- + class DCCR : public morpheo::behavioural::SPR + { + public : const Tspr_t _res : 24; + public : Tspr_t ew : 8; + + public : DCCR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL): + _res (0), + ew (0) + {}; + public : void reset (void ) {}; + public : Tspr_t read (void ) + { + return ((ew << 0)); + }; + public : void write (Tspr_t x) + { + ew = (x >> 0); + }; + }; + + //---------------------------------------------------------- + // [3][1] DCBPR + //---------------------------------------------------------- + class DCBPR : public GENERIC + { + public : DCBPR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [3][2] DCBFR + //---------------------------------------------------------- + class DCBFR : public GENERIC + { + public : DCBFR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [3][3] DCBIR + //---------------------------------------------------------- + class DCBIR : public GENERIC + { + public : DCBIR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [3][4] DCBWR + //---------------------------------------------------------- + class DCBWR : public GENERIC + { + public : DCBWR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + + //---------------------------------------------------------- + // [3][5] DCBLR + //---------------------------------------------------------- + class DCBLR : public GENERIC + { + public : DCBLR (uint32_t num_front_end=0, uint32_t num_context=0,const Parameters * param=NULL) : GENERIC (num_front_end,num_context,param) {}; + }; + +// //---------------------------------------------------------- +// // [0][1] UPR +// //---------------------------------------------------------- +// class UPR : public morpheo::behavioural::SPR +// { +// public : UPR (void): {}; +// public : void reset (void ) {}; +// public : Tspr_t read (void ) +// { +// return (); +// }; +// public : void write (Tspr_t x) {}; +// }; + + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h (revision 88) @@ -0,0 +1,169 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Special_Register_unit_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Special_Register_unit_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Types.h" +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { + +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + + class Special_Register_unit +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_SPR_ACCESS_VAL ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_SPR_ACCESS_ACK ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_SPR_ACCESS_FRONT_END_ID ;//[nb_inst_reexecute] + public : SC_IN (Tcontext_t ) ** in_SPR_ACCESS_CONTEXT_ID ;//[nb_inst_reexecute] + public : SC_IN (Tcontrol_t ) ** in_SPR_ACCESS_WEN ;//[nb_inst_reexecute] + public : SC_IN (Tspr_address_t ) ** in_SPR_ACCESS_NUM_GROUP ;//[nb_inst_reexecute] + public : SC_IN (Tspr_address_t ) ** in_SPR_ACCESS_NUM_REG ;//[nb_inst_reexecute] + public : SC_IN (Tspr_t ) ** in_SPR_ACCESS_WDATA ;//[nb_inst_reexecute] + public : SC_OUT(Tspr_t ) ** out_SPR_ACCESS_RDATA ;//[nb_inst_reexecute] + public : SC_OUT(Tcontrol_t ) ** out_SPR_ACCESS_INVALID ;//[nb_inst_reexecute] + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tspr_t ) *** out_SPR_READ_SR ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_COMMIT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_F_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_F ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_CY_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_CY ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_OV_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_COMMIT_SR_OV ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tspr_t ) *** in_SPR_EVENT_EPCR ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_EEAR_WEN ;//[nb_front_end][nb_context] + public : SC_IN (Tspr_t ) *** in_SPR_EVENT_EEAR ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_SR_DSX ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_SR_TO_ESR ;//[nb_front_end][nb_context] + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : SPR ***** _spr ;//[nb_front_end][nb_context][NB_GROUP][NB_REG_GROUP] + private : SPR_access_mode *** _spr_access_mode ;//[nb_front_end][nb_context] + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : Tcontrol_t * internal_SPR_ACCESS_ACK ;//[nb_inst_reexecute] + private : Tcontrol_t ** internal_SPR_COMMIT_ACK ;//[nb_front_end][nb_context] + private : Tcontrol_t ** internal_SPR_EVENT_ACK ;//[nb_front_end][nb_context] +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Special_Register_unit); +#endif + public : Special_Register_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Special_Register_unit (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC + public : void transition (void); + public : void genMoore (void); + public : void genMealy_spr_access (void); +#endif + +#if VHDL + public : void vhdl (void); + private : void vhdl_declaration (Vhdl * & vhdl); + private : void vhdl_body (Vhdl * & vhdl); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Types.h (revision 88) @@ -0,0 +1,30 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Types_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_special_register_unit_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h" +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters.cpp (revision 88) @@ -0,0 +1,90 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context , + uint32_t nb_inst_reexecute , + bool *** implement_group , + bool is_toplevel + ) + { + log_begin(Special_Register_unit,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_inst_reexecute = nb_inst_reexecute; + _implement_group = implement_group ; + + _max_nb_context = max(_nb_context,_nb_front_end); +// _size_front_end_id = log2(_nb_front_end); +// _size_context_id = log2(_max_nb_context ); +// +// _have_port_front_end_id = _size_front_end_id > 0; +// _have_port_context_id = _size_context_id > 0; + + test(); + + if (is_toplevel) + { + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(_max_nb_context ); + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + + copy(); + } + + + log_end(Special_Register_unit,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Special_Register_unit::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Special_Register_unit,FUNCTION); +// test(); +// log_end(Special_Register_unit,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Special_Register_unit,FUNCTION); + log_end(Special_Register_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::copy" + void Parameters::copy (void) + { + log_begin(Special_Register_unit,FUNCTION); + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,139 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Special_Register_unit,FUNCTION); + + Parameters_test test ("Special_Register_unit"); + + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context[i]; j++) + { + if (_implement_group [i][j][GROUP_SYSTEM_AND_CONTROL ] == false) + test.error(toString(_("Thread [%d][%d] : Group \"SYSTEM_AND_CONTROL\" must be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_DMMU ] == true ) + test.error(toString(_("Thread [%d][%d] : Group \"DMMU\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_IMMU ] == true ) + test.error(toString(_("Thread [%d][%d] : Group \"IMMU\" can't be implemented : not yet supported.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_DCACHE ] == false) +// test.error(toString(_("Thread [%d][%d] : Group \"DCACHE\" must be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_ICACHE ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"ICACHE\" can't be implemented : not yet supported.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_MAC ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"MAC\" can't be implemented here. See functionnal_unit.\n"),i,j)); + + if (_implement_group [i][j][GROUP_DEBUG ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"DEBUG\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_PERFORMANCE_COUNTER] == true) + test.error(toString(_("Thread [%d][%d] : Group \"PERFORMANCE_COUNTER\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_POWER_MANAGEMENT ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"POWER_MANAGEMENT\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_PIC ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"PIC\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_TICK_TIMER ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"TICK_TIMER\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_FLOATING_POINT ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"FLOATIN_POINT\" can't be implemented : not yet supported.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_1 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_1\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_2 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_2\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_3 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_3\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_4 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_4\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_5 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_5\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_6 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_6\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_7 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_7\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_8 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_8\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_9 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_9\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_10 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_10\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_11 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_11\" can't be implemented.\n"),i,j)); + + if (_implement_group [i][j][GROUP_RESERVED_12 ] == true) + test.error(toString(_("Thread [%d][%d] : Group \"RESERVED_12\" can't be implemented.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_1 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_1\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_2 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_2\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_3 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_3\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_4 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_4\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_5 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_5\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_6 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_6\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_7 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_7\" can't be implemented here. See functionnal_unit.\n"),i,j)); + +// if (_implement_group [i][j][GROUP_CUSTOM_8 ] == true) +// test.error(toString(_("Thread [%d][%d] : Group \"CUSTOM_8\" can't be implemented here. See functionnal_unit.\n"),i,j)); + } + + log_end(Special_Register_unit,FUNCTION); + + return test; + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,56 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Special_Register_unit,FUNCTION); + + XML xml ("special_register_unit"); + + xml.balise_open("special_register_unit"); +// xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); + xml.balise_close(); + + log_end(Special_Register_unit,FUNCTION); + + return xml.get_body(depth); + }; + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters & x) + { + log_begin(Special_Register_unit,FUNCTION); + + output_stream << x.print(0); + + log_end(Special_Register_unit,FUNCTION); + + return output_stream; + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit.cpp (revision 88) @@ -0,0 +1,167 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::Special_Register_unit" + Special_Register_unit::Special_Register_unit + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Special_Register_unit,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // Constant + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + internal_SPR_ACCESS_ACK [i] = 1; + PORT_WRITE(out_SPR_ACCESS_ACK [i], internal_SPR_ACCESS_ACK [i]); + } + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + internal_SPR_COMMIT_ACK [i][j] = 1; + internal_SPR_EVENT_ACK [i][j] = 1; + PORT_WRITE(out_SPR_COMMIT_ACK [i][j], internal_SPR_COMMIT_ACK [i][j]); + PORT_WRITE(out_SPR_EVENT_ACK [i][j], internal_SPR_EVENT_ACK [i][j]); + } + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + + SC_METHOD (genMoore); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Method - genMealy_spr_access"),_name.c_str()); + + SC_METHOD (genMealy_spr_access); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); // need internal register + + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + sensitive << (*(in_SPR_ACCESS_NUM_GROUP [i])) + << (*(in_SPR_ACCESS_NUM_REG [i])) +// << (*(in_SPR_ACCESS_VAL [i])) +// << (*(in_SPR_ACCESS_WEN [i])) + ; + if (_param->_have_port_front_end_id) + sensitive << (*(in_SPR_ACCESS_FRONT_END_ID [i])); + if (_param->_have_port_context_id) + sensitive << (*(in_SPR_ACCESS_CONTEXT_ID [i])); + } + + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Special_Register_unit,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::~Special_Register_unit" + Special_Register_unit::~Special_Register_unit (void) + { + log_begin(Special_Register_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 88) @@ -0,0 +1,252 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::allocation" + void Special_Register_unit::allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Special_Register_unit,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Special_Register_unit" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + _("Generalist interface") +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute); + + ALLOC1_VALACK_IN ( in_SPR_ACCESS_VAL ,VAL); + ALLOC1_VALACK_OUT(out_SPR_ACCESS_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_WEN ,"wen" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_NUM_GROUP ,"num_group" ,Tspr_address_t ,_param->_size_special_address_group ); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_NUM_REG ,"num_reg" ,Tspr_address_t ,_param->_size_special_address_register); + ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_WDATA ,"wdata" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_INVALID ,"invalid" ,Tcontrol_t ,1); + } + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_OUT(out_SPR_READ_SR ,"sr",Tspr_t,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_SPR_COMMIT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_SPR_COMMIT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_F_VAL ,"sr_f_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_F ,"sr_f" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_CY_VAL ,"sr_cy_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_CY ,"sr_cy" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV ,"sr_ov" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_SPR_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EPCR ,"EPCR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR_WEN ,"EEAR_WEN" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR ,"EEAR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); + } + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + internal_SPR_ACCESS_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; + internal_SPR_COMMIT_ACK = new Tcontrol_t * [_param->_nb_front_end]; + internal_SPR_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + internal_SPR_COMMIT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; + internal_SPR_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; + } + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _spr_access_mode = new SPR_access_mode ** [_param->_nb_front_end]; + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + _spr_access_mode [i] = new SPR_access_mode * [_param->_nb_context[i]]; + + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + _spr_access_mode [i][j] = new SPR_access_mode; + + for (uint32_t k=0; k_implement_group [i][j][k]) + _spr_access_mode [i][j]->implement_group(k); + } + } + + _spr = new SPR **** [_param->_nb_front_end]; + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + _spr [i] = new SPR *** [_param->_nb_context[i]]; + + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + _spr [i][j] = new SPR ** [NB_GROUP]; + + for (uint32_t k=0; k_implement_group [i][j][k]) + { + _spr [i][j][k] = new SPR * [NB_REG_GROUP[k]]; + + switch (k) + { + case GROUP_SYSTEM_AND_CONTROL : + { + _spr [i][j][k][SPR_VR ] = new VR (i,j,_param); + _spr [i][j][k][SPR_UPR ] = new UPR (i,j,_param); + _spr [i][j][k][SPR_CPUCFGR ] = new CPUCFGR (i,j,_param); + _spr [i][j][k][SPR_DMMUCFGR ] = new DMMUCFGR (i,j,_param); + _spr [i][j][k][SPR_IMMUCFGR ] = new IMMUCFGR (i,j,_param); + _spr [i][j][k][SPR_DCCFGR ] = new DCCFGR (i,j,_param); + _spr [i][j][k][SPR_ICCFGR ] = new ICCFGR (i,j,_param); + _spr [i][j][k][SPR_DCFGR ] = new DCFGR (i,j,_param); + _spr [i][j][k][SPR_PCCFGR ] = new PCCFGR (i,j,_param); + _spr [i][j][k][SPR_NPC ] = new NPC (i,j,_param); + _spr [i][j][k][SPR_SR ] = new SR (i,j,_param); + _spr [i][j][k][SPR_PPC ] = new PPC (i,j,_param); + _spr [i][j][k][SPR_CID ] = new CID (i,j,_param); + _spr [i][j][k][SPR_FPCSR ] = new FPCSR (i,j,_param); + _spr [i][j][k][SPR_EPCR ] = new EPCR (i,j,_param); + _spr [i][j][k][SPR_EEAR ] = new EEAR (i,j,_param); + _spr [i][j][k][SPR_ESR ] = new ESR (i,j,_param); +// _spr [i][j][k][SPR_GPR ] = new GPR (i,j,_param); + + break; + } + case GROUP_DCACHE : + { + _spr [i][j][k][SPR_DCCR ] = new DCCR (i,j,_param); + _spr [i][j][k][SPR_DCBPR ] = new DCBPR (i,j,_param); + _spr [i][j][k][SPR_DCBFR ] = new DCBFR (i,j,_param); + _spr [i][j][k][SPR_DCBIR ] = new DCBIR (i,j,_param); + _spr [i][j][k][SPR_DCBWR ] = new DCBWR (i,j,_param); + _spr [i][j][k][SPR_DCBLR ] = new DCBLR (i,j,_param); + + break; + } + case GROUP_DMMU : + case GROUP_IMMU : + case GROUP_ICACHE : + case GROUP_DEBUG : + case GROUP_PERFORMANCE_COUNTER : + case GROUP_POWER_MANAGEMENT : + case GROUP_PIC : + case GROUP_TICK_TIMER : + case GROUP_FLOATING_POINT : + + case GROUP_MAC : + case GROUP_RESERVED_1 : + case GROUP_RESERVED_2 : + case GROUP_RESERVED_3 : + case GROUP_RESERVED_4 : + case GROUP_RESERVED_5 : + case GROUP_RESERVED_6 : + case GROUP_RESERVED_7 : + case GROUP_RESERVED_8 : + case GROUP_RESERVED_9 : + case GROUP_RESERVED_10 : + case GROUP_RESERVED_11 : + case GROUP_RESERVED_12 : + case GROUP_CUSTOM_1 : + case GROUP_CUSTOM_2 : + case GROUP_CUSTOM_3 : + case GROUP_CUSTOM_4 : + case GROUP_CUSTOM_5 : + case GROUP_CUSTOM_6 : + case GROUP_CUSTOM_7 : + case GROUP_CUSTOM_8 : + default : + { + for (uint32_t l=0; l_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + for (uint32_t k=0; k_implement_group [i][j][k]) + for (uint32_t l=0; linvalid_register (k,l); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 88) @@ -0,0 +1,112 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::deallocation" + void Special_Register_unit::deallocation (void) + { + log_begin(Special_Register_unit,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL( in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute,1); + DELETE1_SIGNAL(out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute,1); + DELETE1_SIGNAL( in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute,1); + DELETE1_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute,_param->_size_context_id ); + DELETE1_SIGNAL( in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute,_param->_size_front_end_id); + DELETE1_SIGNAL( in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute,_param->_size_special_address_group ); + DELETE1_SIGNAL( in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute,_param->_size_special_address_register); + DELETE1_SIGNAL( in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute,_param->_size_spr); + DELETE1_SIGNAL(out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute,_param->_size_spr); + DELETE1_SIGNAL(out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute,1); + + DELETE2_SIGNAL(out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); + + DELETE2_SIGNAL( in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1],1); + + DELETE2_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); + DELETE2_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1],_param->_size_spr); + DELETE2_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1],1); + DELETE2_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1],1); + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] internal_SPR_ACCESS_ACK; + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + delete [] internal_SPR_COMMIT_ACK [i]; + delete [] internal_SPR_EVENT_ACK [i]; + } + delete [] internal_SPR_COMMIT_ACK; + delete [] internal_SPR_EVENT_ACK; + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + for (uint32_t i=0; i<_param->_nb_front_end; i++) + { + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + for (uint32_t k=0; k_implement_group [i][j][k]) + { + for (uint32_t l=0; l_nb_front_end; i++) + { + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + delete _spr_access_mode [i][j]; + delete [] _spr_access_mode [i]; + } + delete [] _spr_access_mode; + + delete _component; + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_end_cycle.cpp (revision 88) @@ -0,0 +1,47 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::end_cycle" +void Special_Register_unit::end_cycle () + { + log_begin(Special_Register_unit,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp (revision 88) @@ -0,0 +1,64 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::genMealy_spr_access" + void Special_Register_unit::genMealy_spr_access (void) + { + log_begin(Special_Register_unit,FUNCTION); + + + // =================================================================== + // =====[ SPR_ACCESS ]================================================ + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) +// if (PORT_READ(in_SPR_ACCESS_VAL [i]) and not PORT_READ(in_SPR_ACCESS_WEN [i])) + { + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; + Tspr_address_t num_group = PORT_READ(in_SPR_ACCESS_NUM_GROUP [i]); + Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); + + SR * sr = static_cast(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); + + Tcontrol_t sm = sr->sm ; + Tcontrol_t sumra = sr->sumra; + + Tcontrol_t valid = _spr_access_mode [front_end_id][context_id]->read(spr_address_t(num_group,num_reg), + sm, + sumra); + + PORT_WRITE(out_SPR_ACCESS_RDATA [i], (valid)?_spr[front_end_id][context_id][num_group][num_reg]->read():0); + PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid); + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp (revision 88) @@ -0,0 +1,46 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::genMoore" + void Special_Register_unit::genMoore (void) + { + log_begin(Special_Register_unit,FUNCTION); + + // =================================================================== + // =====[ SPR_READ ]================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + PORT_WRITE(out_SPR_READ_SR [i][j],_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]->read()); +// { +// SR * sr = static_cast(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); +// PORT_WRITE(out_SPR_READ_SR [i][j],sr->read()); +// } + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_allocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::statistics_allocation" + void Special_Register_unit::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Special_Register_unit,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Special_Register_unit", + param_statistics); + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,39 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::statistics_deallocation" + void Special_Register_unit::statistics_deallocation (void) + { + log_begin(Special_Register_unit,FUNCTION); + + log_printf(INFO,Special_Register_unit,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 88) @@ -0,0 +1,119 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::transition" + void Special_Register_unit::transition (void) + { + log_begin(Special_Register_unit,FUNCTION); + + if (PORT_READ(in_NRESET) == 0) + { + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + for (uint32_t k=0; k_implement_group [i][j][k]) + for (uint32_t l=0; lexist(k,l)) + { +#ifdef DEBUG_TEST + if (_spr [i][j][k] == NULL) + throw ERRORMORPHEO(FUNCTION,toString(_("Group [%d] is not implemented.\n"),k)); + if (_spr [i][j][k][l] == NULL) + throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l)); +#endif +// log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l); + _spr [i][j][k][l]->reset(); + } + + } + else + { + // =================================================================== + // =====[ SPR_ACCESS ]================================================ + // =================================================================== + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + if (PORT_READ(in_SPR_ACCESS_VAL [i]) and internal_SPR_ACCESS_ACK [i]) + if (PORT_READ(in_SPR_ACCESS_WEN [i])) + { + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; + Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; + Tspr_address_t num_group = PORT_READ(in_SPR_ACCESS_NUM_GROUP [i]); + Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); + + SR * sr = static_cast(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); + + Tcontrol_t sm = sr->sm ; + Tcontrol_t sumra = sr->sumra; + + if (_spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg), + sm, + sumra)) + _spr[front_end_id][context_id][num_group][num_reg]->write(PORT_READ(in_SPR_ACCESS_WDATA [i])); + + } + + // =================================================================== + // =====[ SPR_COMMIT ]-=============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + if (PORT_READ(in_SPR_COMMIT_VAL [i][j])) // out_SPR_COMMIT_ACK [i][j] + { + SR * sr = static_cast(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); + + if (PORT_READ(in_SPR_COMMIT_SR_F_VAL [i][j])) + sr->f = PORT_READ(in_SPR_COMMIT_SR_F [i][j]); + + if (PORT_READ(in_SPR_COMMIT_SR_CY_VAL [i][j])) + sr->cy = PORT_READ(in_SPR_COMMIT_SR_CY [i][j]); + + if (PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j])) + sr->ov = PORT_READ(in_SPR_COMMIT_SR_OV [i][j]); + } + + if (PORT_READ(in_SPR_EVENT_VAL [i][j])) // out_SPR_EVENT_ACK [i][j] + { + SR * sr = static_cast(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); + sr->dsx = PORT_READ(in_SPR_EVENT_SR_DSX [i][j]); + + _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_EPCR]->write(PORT_READ(in_SPR_EVENT_EPCR [i][j])); + if (PORT_READ(in_SPR_EVENT_EEAR_WEN [i][j])) + _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_EEAR]->write(PORT_READ(in_SPR_EVENT_EEAR [i][j])); + if (PORT_READ(in_SPR_EVENT_SR_TO_ESR [i][j])) + _spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_ESR ]->write(sr->read()); + } + } + } + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::vhdl" + void Special_Register_unit::vhdl (void) + { + log_begin(Special_Register_unit,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_body.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_body.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::vhdl_body" + void Special_Register_unit::vhdl_body (Vhdl * & vhdl) + { + log_begin(Special_Register_unit,FUNCTION); + vhdl->set_body (""); + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_declaration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_vhdl_declaration.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { +namespace special_register_unit { + + +#undef FUNCTION +#define FUNCTION "Special_Register_unit::vhdl_declaration" + void Special_Register_unit::vhdl_declaration (Vhdl * & vhdl) + { + log_begin(Special_Register_unit,FUNCTION); + log_end(Special_Register_unit,FUNCTION); + }; + +}; // end namespace special_register_unit +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/OOO_Engine.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/OOO_Engine.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/OOO_Engine.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{OOO_Engine} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 88) @@ -0,0 +1,272 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_OOO_Engine_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_OOO_Engine_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h" +#include "Behavioural/include/Types.h" + +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Issue_queue.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/OOO_Engine_Glue.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + class OOO_Engine +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET; + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_RENAME_VAL ;//[nb_front_end][nb_inst_decod] + public : SC_OUT(Tcontrol_t ) *** out_RENAME_ACK ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontext_t ) *** in_RENAME_FRONT_END_ID ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontext_t ) *** in_RENAME_CONTEXT_ID ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tdepth_t ) *** in_RENAME_DEPTH ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Ttype_t ) *** in_RENAME_TYPE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Toperation_t ) *** in_RENAME_OPERATION ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_data_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IMMEDIAT ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_READ_RA ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_NUM_REG_RA ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_READ_RB ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_NUM_REG_RB ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_READ_RC ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tspecial_address_t) *** in_RENAME_NUM_REG_RC ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_WRITE_RD ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tgeneral_address_t) *** in_RENAME_NUM_REG_RD ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tcontrol_t ) *** in_RENAME_WRITE_RE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Tspecial_address_t) *** in_RENAME_NUM_REG_RE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Texception_t ) *** in_RENAME_EXCEPTION_USE ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Texception_t ) *** in_RENAME_EXCEPTION ;//[nb_front_end][nb_inst_decod] + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_VAL ;//[nb_inst_issue] + public : SC_IN (Tcontrol_t ) ** in_ISSUE_ACK ;//[nb_inst_issue] + public : SC_OUT(Tcontext_t ) ** out_ISSUE_FRONT_END_ID ;//[nb_inst_issue] + public : SC_OUT(Tcontext_t ) ** out_ISSUE_CONTEXT_ID ;//[nb_inst_issue] + public : SC_OUT(Tpacket_t ) ** out_ISSUE_PACKET_ID ;//[nb_inst_issue] + public : SC_OUT(Ttype_t ) ** out_ISSUE_TYPE ;//[nb_inst_issue] + public : SC_OUT(Toperation_t ) ** out_ISSUE_OPERATION ;//[nb_inst_issue] + public : SC_OUT(Tlsq_ptr_t ) ** out_ISSUE_STORE_QUEUE_PTR_WRITE ;//[nb_inst_issue] + public : SC_OUT(Tlsq_ptr_t ) ** out_ISSUE_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_HAS_IMMEDIAT ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_data_t ) ** out_ISSUE_IMMEDIAT ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_READ_RA ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_NUM_REG_RA ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_READ_RB ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_NUM_REG_RB ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_READ_RC ;//[nb_inst_issue] + public : SC_OUT(Tspecial_address_t) ** out_ISSUE_NUM_REG_RC ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_WRITE_RD ;//[nb_inst_issue] + public : SC_OUT(Tgeneral_address_t) ** out_ISSUE_NUM_REG_RD ;//[nb_inst_issue] + public : SC_OUT(Tcontrol_t ) ** out_ISSUE_WRITE_RE ;//[nb_inst_issue] + public : SC_OUT(Tspecial_address_t) ** out_ISSUE_NUM_REG_RE ;//[nb_inst_issue] + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_VAL ;//[nb_execute_loop][nb_inst_execute] + public : SC_OUT(Tcontrol_t ) *** out_EXECUTE_LOOP_ACK ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_LOOP_FRONT_END_ID ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontext_t ) *** in_EXECUTE_LOOP_CONTEXT_ID ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tpacket_t ) *** in_EXECUTE_LOOP_PACKET_ID ;//[nb_execute_loop][nb_inst_execute] +//public : SC_IN (Ttype_t ) *** in_EXECUTE_LOOP_TYPE ;//[nb_execute_loop][nb_inst_execute] +//public : SC_IN (Toperation_t ) *** in_EXECUTE_LOOP_OPERATION ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tspecial_data_t ) *** in_EXECUTE_LOOP_FLAGS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_INSERT_VAL ;//[nb_inst_insert] + public : SC_IN (Tcontrol_t ) ** in_INSERT_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RD_USE ;//[nb_inst_insert] + public : SC_OUT(Tgeneral_address_t) ** out_INSERT_RD_NUM_REG ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t ) ** out_INSERT_RE_USE ;//[nb_inst_insert] + public : SC_OUT(Tspecial_address_t) ** out_INSERT_RE_NUM_REG ;//[nb_inst_insert] + +// // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_VAL ;//[nb_inst_retire] +// public : SC_IN (Tcontrol_t ) ** in_RETIRE_ACK ;//[nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RD_OLD_USE ;//[nb_inst_retire] +// public : SC_OUT(Tgeneral_address_t) ** out_RETIRE_RD_OLD_NUM_REG ;//[nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RD_NEW_USE ;//[nb_inst_retire] +// public : SC_OUT(Tgeneral_address_t) ** out_RETIRE_RD_NEW_NUM_REG ;//[nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RE_OLD_USE ;//[nb_inst_retire] +// public : SC_OUT(Tspecial_address_t) ** out_RETIRE_RE_OLD_NUM_REG ;//[nb_inst_retire] +// public : SC_OUT(Tcontrol_t ) ** out_RETIRE_RE_NEW_USE ;//[nb_inst_retire] +// public : SC_OUT(Tspecial_address_t) ** out_RETIRE_RE_NEW_NUM_REG ;//[nb_inst_retire] + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_VAL ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_ACK ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_FRONT_END_ID ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontext_t ) ** out_BRANCH_COMPLETE_CONTEXT_ID ;//[nb_inst_branch_complete] + public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] + public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_VAL ; + public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ACK ; + public : SC_OUT(Tcontext_t ) * out_COMMIT_EVENT_FRONT_END_ID ; + public : SC_OUT(Tcontext_t ) * out_COMMIT_EVENT_CONTEXT_ID ; + public : SC_OUT(Tdepth_t ) * out_COMMIT_EVENT_DEPTH ; + public : SC_OUT(Tevent_type_t ) * out_COMMIT_EVENT_TYPE ; + public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_IS_DELAY_SLOT ; + public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EPCR ; + public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; + public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EEAR ; + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS ;//[nb_front_end][nb_context] + public : SC_IN (Taddress_t ) *** in_EVENT_ADDRESS_NEXT ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_EVENT_ADDRESS_NEXT_VAL ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_EVENT_IS_DS_TAKE ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_VAL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcontrol_t ) *** out_SPR_EVENT_ACK ;//[nb_front_end][nb_context] + public : SC_IN (Tspr_t ) *** in_SPR_EVENT_EPCR ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_EEAR_WEN ;//[nb_front_end][nb_context] + public : SC_IN (Tspr_t ) *** in_SPR_EVENT_EEAR ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_SR_DSX ;//[nb_front_end][nb_context] + public : SC_IN (Tcontrol_t ) *** in_SPR_EVENT_SR_TO_ESR ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_ALL ;//[nb_front_end][nb_context] + public : SC_OUT(Tcounter_t ) *** out_NB_INST_COMMIT_MEM ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tdepth_t ) *** in_DEPTH_MIN ;//[nb_front_end][nb_context] + public : SC_IN (Tdepth_t ) *** in_DEPTH_MAX ;//[nb_front_end][nb_context] + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) *** out_SPR_SR_IEE ;//[nb_front_end][nb_context] - Interrupt Exception Enabled + public : SC_OUT(Tcontrol_t ) *** out_SPR_SR_EPH ;//[nb_front_end][nb_context] - Exception Prefix High + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit ::Rename_unit ** _component_rename_unit ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit ::Commit_unit * _component_commit_unit ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue ::Issue_queue * _component_issue_queue ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit ::Reexecute_unit * _component_reexecute_unit ; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Special_Register_unit * _component_special_register_unit; + private : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue ::OOO_Engine_Glue * _component_glue ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (OOO_Engine); +#endif + public : OOO_Engine + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~OOO_Engine (void); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +# endif +#endif + +#if VHDL + public : void vhdl (void); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h (revision 88) @@ -0,0 +1,195 @@ +#ifndef morpheo_behavioural_core_multi_ooo_engine_ooo_engine_Parameters_h +#define morpheo_behavioural_core_multi_ooo_engine_ooo_engine_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/include/Parameters.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t _nb_rename_unit ; + public : uint32_t _nb_execute_loop ; + public : uint32_t * _nb_inst_decod ;//[nb_front_end] + public : uint32_t * _nb_inst_insert ;//[nb_rename_unit] + public : uint32_t * _nb_inst_retire ;//[nb_rename_unit] + public : uint32_t _nb_inst_issue ; + public : uint32_t * _nb_inst_execute ;//[nb_execute_loop] + public : uint32_t _nb_inst_reexecute ; + public : uint32_t _nb_inst_commit ; + public : uint32_t _nb_inst_branch_complete ; + public : uint32_t ** _nb_branch_speculated ;//[nb_front_end][nb_context] + public : uint32_t _nb_rename_unit_select ; + public : uint32_t _nb_execute_loop_select ; +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : uint32_t * _link_rename_unit_with_front_end ;//[nb_front_end] + // Commit + public : uint32_t _size_re_order_buffer ; + public : uint32_t _nb_re_order_buffer_bank ; + public : Tpriority_t _commit_priority ; + public : Tload_balancing_t _commit_load_balancing ; + // Issue + public : uint32_t _size_issue_queue ; + public : uint32_t _nb_issue_queue_bank ; + public : Tpriority_t _issue_priority ; + public : Tload_balancing_t _issue_load_balancing ; + public : bool ** _table_routing ;//[nb_rename_unit][nb_inst_issue] + public : bool ** _table_issue_type ;//[nb_inst_issue][nb_type] + // Reexecute + public : uint32_t _size_reexecute_queue ; + public : Tpriority_t _reexecute_priority ; + public : Tload_balancing_t _reexecute_load_balancing ; + // Rename_unit + public : Tpriority_t * _rename_select_priority ;//[nb_rename_unit] + public : Tload_balancing_t * _rename_select_load_balancing ;//[nb_rename_unit] + public : uint32_t * _rename_select_nb_front_end_select;//[nb_rename_unit] + public : uint32_t * _nb_general_register ;//[nb_rename_unit] + public : uint32_t * _nb_special_register ;//[nb_rename_unit] + public : uint32_t * _nb_reg_free ;//[nb_rename_unit] + public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_unit] + public : uint32_t * _size_read_counter ;//[nb_rename_unit] + public : uint32_t * _nb_load_store_queue ;//[nb_rename_unit] + public : uint32_t ** _size_store_queue ;//[nb_rename_unit][nb_load_store_queue] + public : uint32_t ** _size_load_queue ;//[nb_rename_unit][nb_load_store_queue] + public : uint32_t ** _link_load_store_unit_with_thread ;//[nb_front_end][nb_context] + // SPR + public : bool *** _implement_group ;//[nb_front_end][nb_context][NB_GROUP] + + + public : std::vector*_link_front_end_with_rename_unit ;//[nb_rename_unit] + public : uint32_t * _rename_unit_nb_front_end ;//[nb_rename_unit] + public : uint32_t ** _rename_unit_nb_context ;//[nb_rename_unit][nb_front_end] + public : uint32_t ** _rename_unit_nb_inst_decod ;//[nb_rename_unit][nb_front_end] + public : uint32_t *** _rename_unit_link_load_store_unit_with_thread ;//[nb_rename_unit][nb_front_end][nb_context] + public : uint32_t * _rename_unit_size_front_end_id ;//[nb_rename_unit] + public : uint32_t * _rename_unit_size_context_id ;//[nb_rename_unit] + public : uint32_t _max_nb_context ; + public : uint32_t _max_branch_speculated ; +//public : uint32_t _size_front_end_id ; +//public : uint32_t _size_context_id ; +//public : uint32_t _size_packet_id ; + public : uint32_t _size_rename_id ; +//public : uint32_t _size_max_depth ; +//public : uint32_t _size_general_register ; +//public : uint32_t _size_special_register ; +//public : uint32_t _size_store_queue_ptr ; +//public : uint32_t _size_load_queue_ptr ; +//public : uint32_t _size_nb_inst ; +//public : uint32_t ** _size_depth ;//[nb_front_end][nb_context] + public : uint32_t _sum_inst_insert ; + public : uint32_t _sum_inst_retire ; + +//public : bool _have_port_front_end_id ; +//public : bool _have_port_context_id ; +//public : bool _have_port_packet_id ; + public : bool _have_port_rename_id ; +//public : bool _have_port_load_queue_ptr ; +//public : bool _have_port_max_depth ; +//public : bool ** _have_port_depth ;//[nb_front_end][nb_context] + + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit ::Parameters ** _param_rename_unit ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit ::Parameters * _param_commit_unit ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue ::Parameters * _param_issue_queue ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit ::Parameters * _param_reexecute_unit ; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * _param_special_register_unit; + public : morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue ::Parameters * _param_glue ; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters (uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t nb_rename_unit , + uint32_t nb_execute_loop , + uint32_t * nb_inst_decod ,//[nb_front_end] + uint32_t * nb_inst_insert ,//[nb_rename_unit] + uint32_t * nb_inst_retire ,//[nb_rename_unit] + uint32_t nb_inst_issue , + uint32_t * nb_inst_execute ,//[nb_execute_loop] + uint32_t nb_inst_reexecute , + uint32_t nb_inst_commit , + uint32_t nb_inst_branch_complete , + uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] + uint32_t nb_rename_unit_select , + uint32_t nb_execute_loop_select , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t * link_rename_unit_with_front_end ,//[nb_front_end] + // Commit + uint32_t size_re_order_buffer , + uint32_t nb_re_order_buffer_bank , + Tpriority_t commit_priority , + Tload_balancing_t commit_load_balancing , + // Issue + uint32_t size_issue_queue , + uint32_t nb_issue_queue_bank , + Tpriority_t issue_priority , + Tload_balancing_t issue_load_balancing , + bool ** table_routing ,//[nb_rename_unit][nb_inst_issue] + bool ** table_issue_type ,//[nb_inst_issue][nb_type] + // Reexecute + uint32_t size_reexecute_queue , + Tpriority_t reexecute_priority , + Tload_balancing_t reexecute_load_balancing , + // Rename_unit + Tpriority_t * rename_select_priority ,//[nb_rename_unit] + Tload_balancing_t * rename_select_load_balancing ,//[nb_rename_unit] + uint32_t * rename_select_nb_front_end_select,//[nb_rename_unit] + uint32_t * nb_general_register ,//[nb_rename_unit] + uint32_t * nb_special_register ,//[nb_rename_unit] + uint32_t * nb_reg_free ,//[nb_rename_unit] + uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] + uint32_t * size_read_counter ,//[nb_rename_unit] + uint32_t * nb_load_store_queue ,//[nb_rename_unit] + uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] + uint32_t ** size_load_queue ,//[nb_rename_unit][nb_load_store_queue] + uint32_t ** link_load_store_unit_with_thread ,//[nb_front_end][nb_context] + // SPR + bool *** implement_group ,//[nb_front_end][nb_context][NB_GROUP] + + bool is_toplevel=false + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : Parameters_test msg_error (void); + + public : void copy (void); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::Parameters & x); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine.cpp (revision 88) @@ -0,0 +1,115 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::OOO_Engine" + OOO_Engine::OOO_Engine + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(OOO_Engine,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_OOO_Engine == true + log_printf(TRACE,OOO_Engine,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(OOO_Engine,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine::~OOO_Engine" + OOO_Engine::~OOO_Engine (void) + { + log_begin(OOO_Engine,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> Deallocation"),_name.c_str()); + deallocation (); + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 88) @@ -0,0 +1,1674 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + +#undef FUNCTION +#define FUNCTION "OOO_Engine::allocation" + void OOO_Engine::allocation + ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(OOO_Engine,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"OOO_Engine" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("rename",IN,WEST,_("Instruction from front_end."),_param->_nb_front_end,_param->_nb_inst_decod[it1]); + + _ALLOC2_VALACK_IN ( in_RENAME_VAL , VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_VALACK_OUT(out_RENAME_ACK , ACK ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register_logic ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register_logic ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register_logic ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register_logic ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register_logic ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION_USE ,"EXCEPTION_USE" ,Texception_t ,_param->_size_exception_use ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + } + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("issue",OUT,EAST,_("Instruction to execute_loop"),_param->_nb_inst_issue); + + ALLOC1_VALACK_OUT (out_ISSUE_VAL , VAL ); + ALLOC1_VALACK_IN ( in_ISSUE_ACK , ACK ); + ALLOC1_SIGNAL_OUT (out_ISSUE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT (out_ISSUE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT (out_ISSUE_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ); + ALLOC1_SIGNAL_OUT (out_ISSUE_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ); + ALLOC1_SIGNAL_OUT (out_ISSUE_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ); + ALLOC1_SIGNAL_OUT (out_ISSUE_STORE_QUEUE_PTR_WRITE ,"STORE_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_store_queue_ptr ); + ALLOC1_SIGNAL_OUT (out_ISSUE_LOAD_QUEUE_PTR_WRITE ,"LOAD_QUEUE_PTR_WRITE" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); + ALLOC1_SIGNAL_OUT (out_ISSUE_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT (out_ISSUE_READ_RA ,"READ_RA" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RA ,"NUM_REG_RA" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT (out_ISSUE_READ_RB ,"READ_RB" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RB ,"NUM_REG_RB" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT (out_ISSUE_READ_RC ,"READ_RC" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RC ,"NUM_REG_RC" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT (out_ISSUE_WRITE_RD ,"WRITE_RD" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RD ,"NUM_REG_RD" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT (out_ISSUE_WRITE_RE ,"WRITE_RE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_ISSUE_NUM_REG_RE ,"NUM_REG_RE" ,Tspecial_address_t,_param->_size_special_register ); + } + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("execute_loop",IN,EAST,_("Instruction executed, from execute_loop."),_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + + _ALLOC2_VALACK_IN ( in_EXECUTE_LOOP_VAL , VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_VALACK_OUT(out_EXECUTE_LOOP_ACK , ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_PACKET_ID ,"PACKET_ID" ,Tpacket_t ,_param->_size_rob_ptr ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_TYPE ,"TYPE" ,Ttype_t ,_param->_size_type ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); +// _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_OPERATION ,"OPERATION" ,Toperation_t ,_param->_size_operation ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_FLAGS ,"FLAGS" ,Tspecial_data_t ,_param->_size_special_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("insert",OUT,EAST,_("Interface with RegisterFile's stat-list (insert Re-Order-Buffer)."),_param->_sum_inst_insert); + + ALLOC1_VALACK_OUT (out_INSERT_VAL , VAL); + ALLOC1_VALACK_IN ( in_INSERT_ACK , ACK); + ALLOC1_SIGNAL_OUT (out_INSERT_RD_USE ,"RD_USE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_INSERT_RD_NUM_REG ,"RD_NUM_REG" ,Tgeneral_address_t,_param->_size_general_register ); + ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); + } + +// // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// { +// ALLOC1_INTERFACE("retire",OUT,EAST,_("Interface with RegisterFile's stat-list (retire Re-Order-Buffer)."),_param->_sum_inst_retire); + +// ALLOC1_VALACK_OUT (out_RETIRE_VAL , VAL); +// ALLOC1_VALACK_IN ( in_RETIRE_ACK , ACK); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_OLD_USE ,"RD_OLD_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_OLD_NUM_REG ,"RD_OLD_NUM_REG" ,Tgeneral_address_t,_param->_size_general_register ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_NEW_USE ,"RD_NEW_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RD_NEW_NUM_REG ,"RD_NEW_NUM_REG" ,Tgeneral_address_t,_param->_size_general_register ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_OLD_USE ,"RE_OLD_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_OLD_NUM_REG ,"RE_OLD_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_USE ,"RE_NEW_USE" ,Tcontrol_t ,1 ); +// ALLOC1_SIGNAL_OUT (out_RETIRE_RE_NEW_NUM_REG ,"RE_NEW_NUM_REG" ,Tspecial_address_t,_param->_size_special_register ); +// } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("branch_complete",OUT,WEST,_("Instruction to execute_loop"),_param->_nb_inst_issue); + + ALLOC1_VALACK_OUT (out_BRANCH_COMPLETE_VAL , VAL); + ALLOC1_VALACK_IN ( in_BRANCH_COMPLETE_ACK , ACK); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_FLAG ,"FLAG" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); + } + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC_INTERFACE("commit_event",OUT,WEST,_("Commit an event (exception).")); + + ALLOC_VALACK_OUT (out_COMMIT_EVENT_VAL , VAL); + ALLOC_VALACK_IN ( in_COMMIT_EVENT_ACK , ACK); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_FRONT_END_ID ,"FRONT_END_ID" ,Tcontext_t ,_param->_size_front_end_id ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_CONTEXT_ID ,"CONTEXT_ID" ,Tcontext_t ,_param->_size_context_id ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_TYPE ,"TYPE" ,Tevent_type_t ,_param->_size_event_type ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_general_data ); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("event",IN,WEST,_("Event from context_state."),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_EVENT_ACK , ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"ADDRESS_NEXT" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"ADDRESS_NEXT_VAL" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"IS_DS_TAKE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr_event",IN,WEST,_("Exception : save spr and set a lot of special register."),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL , VAL ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_VALACK_OUT(out_SPR_EVENT_ACK , ACK ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EPCR ,"EPCR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR_WEN ,"EEAR_WEN" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR ,"EEAR" ,Tspr_t ,_param->_size_spr ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("nb_inst",OUT,WEST,_("Internal number instruction."),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_ALL ,"COMMIT_ALL" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_NB_INST_COMMIT_MEM ,"COMMIT_MEM" ,Tcounter_t ,_param->_size_nb_inst_commit ,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("depth",IN,WEST,_("Interface with Prediction unit."),_param->_nb_front_end, _param->_nb_context[it1]); + + _ALLOC2_SIGNAL_IN ( in_DEPTH_MIN ,"MIN" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end, _param->_nb_context[it1]); + _ALLOC2_SIGNAL_IN ( in_DEPTH_MAX ,"MAX" ,Tdepth_t ,_param->_size_depth+1 ,_param->_nb_front_end, _param->_nb_context[it1]); + } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC2_INTERFACE("spr",OUT,WEST,_("SPR"),_param->_nb_front_end,_param->_nb_context[it1]); + + _ALLOC2_SIGNAL_OUT(out_SPR_SR_IEE ,"SR_IEE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + _ALLOC2_SIGNAL_OUT(out_SPR_SR_EPH ,"SR_EPH" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_context[it1]); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string name; + + _component_rename_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Rename_unit * [_param->_nb_rename_unit]; + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + { + name = _name+"_rename_unit_"+toString(i); + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_rename_unit [i] = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Rename_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_rename_unit [i] + ,_usage); + + _component->set_component (_component_rename_unit [i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_commit_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_commit_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Commit_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_commit_unit + ,_usage); + + _component->set_component (_component_commit_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_issue_queue"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_issue_queue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Issue_queue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_issue_queue + ,_usage); + + _component->set_component (_component_issue_queue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_reexecute_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_reexecute_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Reexecute_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_reexecute_unit + ,_usage); + + _component->set_component (_component_reexecute_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_special_register_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_special_register_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Special_Register_unit + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_special_register_unit + ,_usage); + + _component->set_component (_component_special_register_unit->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_glue"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Create : %s"),name.c_str()); + + _component_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::OOO_Engine_Glue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_glue + ,_usage); + + _component->set_component (_component_glue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string src,dest; + + // =================================================================== + // =====[ rename_unit ]=============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + { + src = _name+"_rename_unit_"+toString(i); + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "rename_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::vector::iterator it = _param->_link_front_end_with_rename_unit[i].begin(); + uint32_t x = 0; + for (uint32_t j=0; j<_param->_nb_front_end; j++) + { + if (i == *it) + { + // this front end is link with this rename_unit + for (uint32_t k=0; k<_param->_nb_inst_decod [j]; k++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"rename_in_"+toString(x)+"_"+toString(k), + dest,"rename_" +toString(j)+"_"+toString(k)); +#endif + + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_VAL" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_VAL" ); + PORT_MAP(_component,src ,"out_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ACK" , + dest,"out_RENAME_" +toString(j)+"_"+toString(k)+"_ACK" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_CONTEXT_ID" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_DEPTH" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_DEPTH" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_TYPE" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_TYPE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_OPERATION" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_OPERATION" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NO_EXECUTE" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NO_EXECUTE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IS_DELAY_SLOT", + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT"); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_ADDRESS" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_HAS_IMMEDIAT" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_HAS_IMMEDIAT" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_IMMEDIAT" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_IMMEDIAT" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_READ_RA" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_READ_RA" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NUM_REG_RA" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NUM_REG_RA" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_READ_RB" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_READ_RB" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NUM_REG_RB" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NUM_REG_RB" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_READ_RC" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_READ_RC" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NUM_REG_RC" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NUM_REG_RC" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_WRITE_RD" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_WRITE_RD" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NUM_REG_RD" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NUM_REG_RD" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_WRITE_RE" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_WRITE_RE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_NUM_REG_RE" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_NUM_REG_RE" ); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_EXCEPTION_USE", + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_EXCEPTION_USE"); + PORT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+"_EXCEPTION" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_EXCEPTION" ); + + // glue + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"rename_in_"+toString(x)+"_"+toString(k), + dest,"rename_" +toString(j)+"_"+toString(k)); +#endif + + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_RENAME_IN_"+toString(x)+"_"+toString(k)+ "_FRONT_END_ID" , + dest, "in_RENAME_" +toString(j)+"_"+toString(k)+"_RENAME_UNIT_FRONT_END_ID" ); + } + + x ++; + it++; + } + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + dest = _name+"_commit_unit"; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(j), + dest,"insert_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_DEPTH" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_DEPTH" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_IS_DELAY_SLOT" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_IS_DELAY_SLOT" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_ADDRESS" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_EXCEPTION_USE" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_EXCEPTION_USE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_EXCEPTION" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_NUM_REG_RA_LOG", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_LOG"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_NUM_REG_RB_LOG", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_LOG"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_NUM_REG_RC_LOG", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_LOG"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_NUM_REG_RD_LOG", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_LOG"); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j) +"_NUM_REG_RE_LOG", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_LOG"); + + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(j), + dest,"insert_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_VAL" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_VAL" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(j)+ "_ACK" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_FRONT_END_ID" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_CONTEXT_ID" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_CONTEXT_ID" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_TYPE" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_TYPE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_OPERATION" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_OPERATION" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NO_EXECUTE" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NO_EXECUTE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_HAS_IMMEDIAT" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_IMMEDIAT" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_IMMEDIAT" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_STORE_QUEUE_PTR_WRITE", + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_LOAD_QUEUE_PTR_WRITE" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_READ_RA" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_READ_RA" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RA_PHY" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_READ_RB" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_READ_RB" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RB_PHY" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_READ_RC" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_READ_RC" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RC_PHY" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_WRITE_RD" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RD" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RD_PHY_OLD" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_OLD" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RD_PHY_NEW" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_NEW" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_WRITE_RE" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RE_PHY_OLD" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_OLD" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(j)+ "_NUM_REG_RE_PHY_NEW" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_NEW" ); + } + + for (uint32_t j=0; j<_param->_nb_inst_retire[i]; j++) + { + dest = _name+"_commit_unit"; + +#ifdef POSITION + _component->interface_map (src ,"retire_"+toString(j), + dest,"retire_"+toString(i)+"_"+toString(j)); +#endif + + + + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_VAL" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(j)+ "_ACK" , + dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_FRONT_END_ID" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RD" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_OLD", + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_PHY_OLD"); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_NEW", + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_PHY_NEW"); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RE" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_OLD", + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_PHY_OLD"); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_NEW", + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_PHY_NEW"); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_EVENT_STATE" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_EVENT_STATE" ); + + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_CONTEXT_ID" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_TYPE" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_TYPE" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_OPERATION" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_USE_STORE_QUEUE" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_USE_STORE_QUEUE" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_USE_LOAD_QUEUE" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_USE_LOAD_QUEUE" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_STORE_QUEUE_PTR_WRITE", + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_LOAD_QUEUE_PTR_WRITE" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RA" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RA" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RA_PHY" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RB" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RB" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RB_PHY" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_READ_RC" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_READ_RC" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RC_PHY" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_LOG" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD_LOG" ); + COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_LOG" , + dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE_LOG" ); + +// dest = _name+"_glue"; + +// #ifdef POSITION +// _component->interface_map (src ,"retire_"+toString(j), +// dest,"retire_"+toString(i)+"_"+toString(j)); +// #endif + +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_VAL" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_VAL" ); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(j)+ "_ACK" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_ACK" ); +// if (_param->_have_port_front_end_id) +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_FRONT_END_ID" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_FRONT_END_ID" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RD" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RD" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_OLD", +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_OLD"); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RD_PHY_NEW", +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RD_PHY_NEW"); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_WRITE_RE" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_WRITE_RE" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_OLD", +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_OLD"); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_NUM_REG_RE_PHY_NEW", +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_NUM_REG_RE_PHY_NEW"); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(j)+ "_EVENT_STATE" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_RENAME_UNIT_EVENT_STATE" ); + } + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"spr_read_"+toString(i)+"_"+toString(j), + dest,"spr_" +toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_SPR_READ_"+toString(i)+"_"+toString(j)+ "_SR", + dest,"out_SPR_" +toString(i)+"_"+toString(j)+"_RENAME_UNIT_SR"); + } + } + + // =================================================================== + // =====[ commit_unit ]=============================================== + // =================================================================== + { + src = _name+"_commit_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i)+"_"+toString(j), + dest,"insert_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_VAL" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_VAL" ); + COMPONENT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_"+toString(j)+ "_ACK" , + dest, "in_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_FRONT_END_ID" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_CONTEXT_ID" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_CONTEXT_ID" ); +// COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_RENAME_UNIT_ID" , +// dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_RENAME_UNIT_ID" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_TYPE" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_TYPE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_OPERATION" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_OPERATION" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NO_EXECUTE" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NO_EXECUTE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_STORE_QUEUE_PTR_WRITE", + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_LOAD_QUEUE_PTR_WRITE" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_READ_RA" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_READ_RA" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RA_PHY" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RA_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_READ_RB" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_READ_RB" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RB_PHY" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RB_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_READ_RC" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_READ_RC" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RC_PHY" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RC_PHY" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_WRITE_RD" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RD_PHY_OLD" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RD_PHY_OLD" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RD_PHY_NEW" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RD_PHY_NEW" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_WRITE_RE" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RE_PHY_OLD" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RE_PHY_OLD" ); + COMPONENT_MAP(_component,src , "in_INSERT_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RE_PHY_NEW" , + dest,"out_INSERT_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RE_PHY_NEW" ); + + dest = _name+"_issue_queue"; +#ifdef POSITION + _component->interface_map (src ,"insert_" +toString(i)+"_"+toString(j), + dest,"issue_in_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(i)+"_"+toString(j)+"_PACKET_ID", + dest, "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+"_PACKET_ID"); + + // in_INSERT_DEPTH - component_rename_unit + // in_INSERT_ADDRESS - component_rename_unit + // in_INSERT_EXCEPTION_USE - component_rename_unit + // in_INSERT_EXCEPTION - component_rename_unit + // in_INSERT_NUM_REG_RA_LOG - component_rename_unit + // in_INSERT_NUM_REG_RB_LOG - component_rename_unit + // in_INSERT_NUM_REG_RC_LOG - component_rename_unit + // in_INSERT_NUM_REG_RD_LOG - component_rename_unit + // in_INSERT_NUM_REG_RE_LOG - component_rename_unit + // in_INSERT_IS_DELAY_SLOT - component_rename_unit + } + + // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_retire [i]; j++) + { +// dest = _name+"_glue"; + +// #ifdef POSITION +// _component->interface_map (src ,"retire_"+toString(i)+"_"+toString(j), +// dest,"retire_"+toString(i)+"_"+toString(j)); +// #endif + +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_VAL" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_VAL" ); +// COMPONENT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_"+toString(j)+ "_ACK" , +// dest,"out_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_ACK" ); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_WRITE_RD" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_WRITE_RD" ); +// if (_param->_have_port_front_end_id) +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_FRONT_END_ID" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_FRONT_END_ID" ); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RD_PHY_OLD", +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RD_PHY_OLD"); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RD_PHY_NEW", +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RD_PHY_NEW"); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_WRITE_RE" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_WRITE_RE" ); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RE_PHY_OLD", +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RE_PHY_OLD"); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RE_PHY_NEW", +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_NUM_REG_RE_PHY_NEW"); +// COMPONENT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_"+toString(j)+ "_EVENT_STATE" , +// dest, "in_RETIRE_"+toString(i)+"_"+toString(j)+"_COMMIT_UNIT_EVENT_STATE" ); + + + // out_RETIRE_VAL - component_rename_unit + // in_RETIRE_ACK - component_rename_unit + // out_RETIRE_WRITE_RD - component_rename_unit + // out_RETIRE_FRONT_END_ID - component_rename_unit + // out_RETIRE_NUM_REG_RD_PHY_OLD - component_rename_unit + // out_RETIRE_NUM_REG_RD_PHY_NEW - component_rename_unit + // out_RETIRE_WRITE_RE - component_rename_unit + // out_RETIRE_NUM_REG_RE_PHY_OLD - component_rename_unit + // out_RETIRE_NUM_REG_RE_PHY_NEW - component_rename_unit + // out_RETIRE_EVENT_STATE - component_rename_unit + + // out_RETIRE_CONTEXT_ID - component_rename_unit + ////out_RETIRE_RENAME_UNIT_ID - component_rename_unit + // out_RETIRE_USE_STORE_QUEUE - component_rename_unit + // out_RETIRE_USE_LOAD_QUEUE - component_rename_unit + // out_RETIRE_STORE_QUEUE_PTR_WRITE - component_rename_unit + // out_RETIRE_LOAD_QUEUE_PTR_WRITE - component_rename_unit + // out_RETIRE_READ_RA - component_rename_unit + // out_RETIRE_NUM_REG_RA_PHY - component_rename_unit + // out_RETIRE_READ_RB - component_rename_unit + // out_RETIRE_NUM_REG_RB_PHY - component_rename_unit + // out_RETIRE_READ_RC - component_rename_unit + // out_RETIRE_NUM_REG_RC_PHY - component_rename_unit + // out_RETIRE_NUM_REG_RD_LOG - component_rename_unit + // out_RETIRE_NUM_REG_RE_LOG - component_rename_unit + } + + // ~~~~~[ Interface : "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_commit; i++) + { + dest = _name+"_reexecute_unit"; +#ifdef POSITION + _component->interface_map (src ,"commit_"+toString(i), + dest,"commit_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_VAL" , + dest,"out_COMMIT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_"+toString(i)+"_ACK" , + dest, "in_COMMIT_"+toString(i)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_WEN" , + dest,"out_COMMIT_"+toString(i)+"_WEN" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_PACKET_ID" , + dest,"out_COMMIT_"+toString(i)+"_PACKET_ID" ); +// COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_OPERATION" , +// dest,"out_COMMIT_"+toString(i)+"_OPERATION" ); +// COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_TYPE" , +// dest,"out_COMMIT_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_FLAGS" , + dest,"out_COMMIT_"+toString(i)+"_FLAGS" ); + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_EXCEPTION" , + dest,"out_COMMIT_"+toString(i)+"_EXCEPTION" ); + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_NO_SEQUENCE", + dest,"out_COMMIT_"+toString(i)+"_NO_SEQUENCE"); + COMPONENT_MAP(_component,src , "in_COMMIT_"+toString(i)+"_ADDRESS" , + dest,"out_COMMIT_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_"+toString(i)+"_NUM_REG_RD" , + dest, "in_COMMIT_"+toString(i)+"_NUM_REG_RD" ); + //@@@@@@@@@@ + } + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + dest = _name+"_reexecute_unit"; +#ifdef POSITION + _component->interface_map (src ,"reexecute_" +toString(i), + dest,"reexecute_rob_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_VAL" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_" +toString(i)+"_ACK" , + dest,"out_REEXECUTE_ROB_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_FRONT_END_ID" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_CONTEXT_ID" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_PACKET_ID" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_PACKET_ID" ); + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_OPERATION" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_OPERATION" ); + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_TYPE" , + dest, "in_REEXECUTE_ROB_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src ,"out_REEXECUTE_" +toString(i)+"_STORE_QUEUE_PTR_WRITE", + dest, "in_REEXECUTE_ROB_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_"+toString(i), + dest,"branch_complete_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_VAL" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ACK" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_FRONT_END_ID" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_DEPTH" ); + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); + } + + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"update", + dest,"commit_event"); +#endif + + PORT_MAP(_component,src ,"out_UPDATE_VAL" ,dest,"out_COMMIT_EVENT_VAL" ); + PORT_MAP(_component,src , "in_UPDATE_ACK" ,dest, "in_COMMIT_EVENT_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src ,"out_UPDATE_FRONT_END_ID" ,dest,"out_COMMIT_EVENT_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_UPDATE_CONTEXT_ID" ,dest,"out_COMMIT_EVENT_CONTEXT_ID" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_UPDATE_DEPTH" ,dest,"out_COMMIT_EVENT_DEPTH" ); + PORT_MAP(_component,src ,"out_UPDATE_TYPE" ,dest,"out_COMMIT_EVENT_TYPE" ); + PORT_MAP(_component,src ,"out_UPDATE_IS_DELAY_SLOT" ,dest,"out_COMMIT_EVENT_IS_DELAY_SLOT" ); + PORT_MAP(_component,src ,"out_UPDATE_ADDRESS" ,dest,"out_COMMIT_EVENT_ADDRESS" ); + PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EPCR" ,dest,"out_COMMIT_EVENT_ADDRESS_EPCR" ); + PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EEAR_VAL",dest,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL"); + PORT_MAP(_component,src ,"out_UPDATE_ADDRESS_EEAR" ,dest,"out_COMMIT_EVENT_ADDRESS_EEAR" ); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(i)+"_"+toString(j), + dest,"event_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" ); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS" , + dest, "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" , + dest, "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT" ); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT_VAL", + dest, "in_EVENT_"+toString(i)+"_"+toString(j)+"_ADDRESS_NEXT_VAL"); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_"+toString(j)+"_IS_DS_TAKE" , + dest, "in_EVENT_"+toString(i)+"_"+toString(j)+"_IS_DS_TAKE" ); + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"nb_inst_"+toString(i)+"_"+toString(j), + dest,"nb_inst_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_ALL", + dest,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_ALL"); + PORT_MAP(_component,src ,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM", + dest,"out_NB_INST_"+toString(i)+"_"+toString(j)+"_COMMIT_MEM"); + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(i)+"_"+toString(j), + dest,"depth_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN", + dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MIN"); + PORT_MAP(_component,src , "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX", + dest, "in_DEPTH_"+toString(i)+"_"+toString(j)+"_MAX"); + } + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"spr_read_"+toString(i)+"_"+toString(j), + dest,"spr_" +toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_SPR_READ_"+toString(i)+"_"+toString(j)+ "_SR_OVE", + dest,"out_SPR_" +toString(i)+"_"+toString(j)+"_COMMIT_UNIT_SR_OVE"); + } + + // ~~~~~[ Interface : "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name+"_special_register_unit"; +#ifdef POSITION + _component->interface_map (src ,"spr_write_" +toString(i)+"_"+toString(j), + dest,"spr_commit_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_ACK" ); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_F_VAL" , + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_F_VAL" ); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_F" , + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_F" ); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_CY_VAL", + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_CY_VAL"); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_CY" , + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_CY" ); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_OV_VAL", + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_OV_VAL"); + COMPONENT_MAP(_component,src ,"out_SPR_WRITE_" +toString(i)+"_"+toString(j)+"_SR_OV" , + dest, "in_SPR_COMMIT_"+toString(i)+"_"+toString(j)+"_SR_OV" ); + } + + } + + // =================================================================== + // =====[ issue_queue ]=============================================== + // =================================================================== + { + src = _name+"_issue_queue"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "issue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_rename_unit; ++i) + for (uint32_t j=0; j<_param->_nb_inst_insert[i]; j++) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"issue_in_"+toString(i)+"_"+toString(j), + dest,"insert_" +toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_VAL" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_VAL" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_ACK" , + dest, "in_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_CONTEXT_ID" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_FRONT_END_ID" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_FRONT_END_ID" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_OPERATION" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_OPERATION" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_TYPE" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_TYPE" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_STORE_QUEUE_PTR_WRITE", + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_LOAD_QUEUE_PTR_WRITE" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_HAS_IMMEDIAT" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_IMMEDIAT" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_READ_RA" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_READ_RA" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RA" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_NUM_REG_RA" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_READ_RB" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_READ_RB" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RB" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_NUM_REG_RB" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_READ_RC" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_READ_RC" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RC" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_NUM_REG_RC" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_WRITE_RD" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RD" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_NUM_REG_RD" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_WRITE_RE" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_ISSUE_IN_"+toString(i)+"_"+toString(j)+ "_NUM_REG_RE" , + dest,"out_INSERT_" +toString(i)+"_"+toString(j)+"_ISSUE_QUEUE_NUM_REG_RE" ); + + + + // in_ISSUE_IN_PACKET_ID - component_commit_unit + } + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + dest = _name+"_reexecute_unit"; +#ifdef POSITION + _component->interface_map (src ,"reexecute_"+toString(i), + dest,"reexecute_"+toString(i)); +#endif + + + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_VAL" , + dest,"out_REEXECUTE_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_REEXECUTE_"+toString(i)+"_ACK" , + dest, "in_REEXECUTE_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_FRONT_END_ID" , + dest,"out_REEXECUTE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_CONTEXT_ID" , + dest,"out_REEXECUTE_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_PACKET_ID" , + dest,"out_REEXECUTE_"+toString(i)+"_PACKET_ID" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_TYPE" , + dest,"out_REEXECUTE_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_OPERATION" , + dest,"out_REEXECUTE_"+toString(i)+"_OPERATION" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", + dest,"out_REEXECUTE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , + dest,"out_REEXECUTE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_HAS_IMMEDIAT" , + dest,"out_REEXECUTE_"+toString(i)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_IMMEDIAT" , + dest,"out_REEXECUTE_"+toString(i)+"_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_READ_RA" , + dest,"out_REEXECUTE_"+toString(i)+"_READ_RA" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_NUM_REG_RA" , + dest,"out_REEXECUTE_"+toString(i)+"_NUM_REG_RA" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_READ_RB" , + dest,"out_REEXECUTE_"+toString(i)+"_READ_RB" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_NUM_REG_RB" , + dest,"out_REEXECUTE_"+toString(i)+"_NUM_REG_RB" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_READ_RC" , + dest,"out_REEXECUTE_"+toString(i)+"_READ_RC" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_NUM_REG_RC" , + dest,"out_REEXECUTE_"+toString(i)+"_NUM_REG_RC" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_WRITE_RD" , + dest,"out_REEXECUTE_"+toString(i)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_NUM_REG_RD" , + dest,"out_REEXECUTE_"+toString(i)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_WRITE_RE" , + dest,"out_REEXECUTE_"+toString(i)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_REEXECUTE_"+toString(i)+"_NUM_REG_RE" , + dest,"out_REEXECUTE_"+toString(i)+"_NUM_REG_RE" ); + } + + // ~~~~~[ Interface : "issue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_issue; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"issue_out_"+toString(i), + dest,"issue_" +toString(i)); +#endif + + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_VAL" , + dest,"out_ISSUE_" +toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_ISSUE_OUT_"+toString(i)+"_ACK" , + dest, "in_ISSUE_" +toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_FRONT_END_ID" , + dest,"out_ISSUE_" +toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_CONTEXT_ID" , + dest,"out_ISSUE_" +toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_PACKET_ID" , + dest,"out_ISSUE_" +toString(i)+"_PACKET_ID" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_TYPE" , + dest,"out_ISSUE_" +toString(i)+"_TYPE" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_OPERATION" , + dest,"out_ISSUE_" +toString(i)+"_OPERATION" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE", + dest,"out_ISSUE_" +toString(i)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" , + dest,"out_ISSUE_" +toString(i)+"_LOAD_QUEUE_PTR_WRITE" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_HAS_IMMEDIAT" , + dest,"out_ISSUE_" +toString(i)+"_HAS_IMMEDIAT" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_IMMEDIAT" , + dest,"out_ISSUE_" +toString(i)+"_IMMEDIAT" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_READ_RA" , + dest,"out_ISSUE_" +toString(i)+"_READ_RA" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_NUM_REG_RA" , + dest,"out_ISSUE_" +toString(i)+"_NUM_REG_RA" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_READ_RB" , + dest,"out_ISSUE_" +toString(i)+"_READ_RB" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_NUM_REG_RB" , + dest,"out_ISSUE_" +toString(i)+"_NUM_REG_RB" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_READ_RC" , + dest,"out_ISSUE_" +toString(i)+"_READ_RC" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_NUM_REG_RC" , + dest,"out_ISSUE_" +toString(i)+"_NUM_REG_RC" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_WRITE_RD" , + dest,"out_ISSUE_" +toString(i)+"_WRITE_RD" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_NUM_REG_RD" , + dest,"out_ISSUE_" +toString(i)+"_NUM_REG_RD" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_WRITE_RE" , + dest,"out_ISSUE_" +toString(i)+"_WRITE_RE" ); + PORT_MAP(_component,src ,"out_ISSUE_OUT_"+toString(i)+"_NUM_REG_RE" , + dest,"out_ISSUE_" +toString(i)+"_NUM_REG_RE" ); + } + } + + // =================================================================== + // =====[ reexecute_unit ]============================================ + // =================================================================== + { + src = _name+"_reexecute_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_execute_loop; i++) + for (uint32_t j=0; j<_param->_nb_inst_execute[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"execute_loop_"+toString(i)+"_"+toString(j), + dest,"execute_loop_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID", + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID"); + if (_param->_have_port_context_id) + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_PACKET_ID" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); +// PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_TYPE" , +// dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_TYPE" ); +// PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OPERATION" , +// dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FLAGS" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FLAGS" ); + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_EXCEPTION" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" ); + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ADDRESS" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + PORT_MAP(_component,src , "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_DATA" , + dest, "in_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_DATA" ); + } + + // ~~~~~[ Interface "commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_COMMIT_VAL - component_commit_unit + // in_COMMIT_ACK - component_commit_unit + // out_COMMIT_WEN - component_commit_unit + // out_COMMIT_FRONT_END_ID - component_commit_unit + // out_COMMIT_CONTEXT_ID - component_commit_unit + // out_COMMIT_PACKET_ID - component_commit_unit + ////out_COMMIT_OPERATION - component_commit_unit + ////out_COMMIT_TYPE - component_commit_unit + // out_COMMIT_FLAGS - component_commit_unit + // out_COMMIT_EXCEPTION - component_commit_unit + // out_COMMIT_NO_SEQUENCE - component_commit_unit + // out_COMMIT_ADDRESS - component_commit_unit + // in_COMMIT_NUM_REG_RD - component_commit_unit + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++) + { + dest = _name+"_special_register_unit"; +#ifdef POSITION + _component->interface_map (src ,"spr_"+toString(i), + dest,"spr_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_VAL" , + dest, "in_SPR_ACCESS_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_SPR_" +toString(i)+"_ACK" , + dest,"out_SPR_ACCESS_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_FRONT_END_ID", + dest, "in_SPR_ACCESS_"+toString(i)+"_FRONT_END_ID"); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_CONTEXT_ID" , + dest, "in_SPR_ACCESS_"+toString(i)+"_CONTEXT_ID" ); + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_WEN" , + dest, "in_SPR_ACCESS_"+toString(i)+"_WEN" ); + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_NUM_GROUP" , + dest, "in_SPR_ACCESS_"+toString(i)+"_NUM_GROUP" ); + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_NUM_REG" , + dest, "in_SPR_ACCESS_"+toString(i)+"_NUM_REG" ); + COMPONENT_MAP(_component,src ,"out_SPR_" +toString(i)+"_WDATA" , + dest, "in_SPR_ACCESS_"+toString(i)+"_WDATA" ); + COMPONENT_MAP(_component,src , "in_SPR_" +toString(i)+"_RDATA" , + dest,"out_SPR_ACCESS_"+toString(i)+"_RDATA" ); + COMPONENT_MAP(_component,src , "in_SPR_" +toString(i)+"_INVALID" , + dest,"out_SPR_ACCESS_"+toString(i)+"_INVALID" ); + } + + // ~~~~~[ Interface : "reexecute_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_REEXECUTE_ROB_VAL - component_commit_unit + // out_REEXECUTE_ROB_ACK - component_commit_unit + // in_REEXECUTE_ROB_FRONT_END_ID - component_commit_unit + // in_REEXECUTE_ROB_CONTEXT_ID - component_commit_unit + // in_REEXECUTE_ROB_PACKET_ID - component_commit_unit + // in_REEXECUTE_ROB_OPERATION - component_commit_unit + // in_REEXECUTE_ROB_TYPE - component_commit_unit + // in_REEXECUTE_ROB_STORE_QUEUE_PTR_WRITE - component_commit_unit + + // ~~~~~[ Interface : "reexecute" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_REEXECUTE_VAL - component_issue_queue + // in_REEXECUTE_ACK - component_issue_queue + // out_REEXECUTE_CONTEXT_ID - component_issue_queue + // out_REEXECUTE_FRONT_END_ID - component_issue_queue + // out_REEXECUTE_PACKET_ID - component_issue_queue + // out_REEXECUTE_OPERATION - component_issue_queue + // out_REEXECUTE_TYPE - component_issue_queue + // out_REEXECUTE_STORE_QUEUE_PTR_WRITE - component_issue_queue + // out_REEXECUTE_LOAD_QUEUE_PTR_WRITE - component_issue_queue + // out_REEXECUTE_HAS_IMMEDIAT - component_issue_queue + // out_REEXECUTE_IMMEDIAT - component_issue_queue + // out_REEXECUTE_READ_RA - component_issue_queue + // out_REEXECUTE_NUM_REG_RA - component_issue_queue + // out_REEXECUTE_READ_RB - component_issue_queue + // out_REEXECUTE_NUM_REG_RB - component_issue_queue + // out_REEXECUTE_READ_RC - component_issue_queue + // out_REEXECUTE_NUM_REG_RC - component_issue_queue + // out_REEXECUTE_WRITE_RD - component_issue_queue + // out_REEXECUTE_NUM_REG_RD - component_issue_queue + // out_REEXECUTE_WRITE_RE - component_issue_queue + // out_REEXECUTE_NUM_REG_RE - component_issue_queue + } + + // =================================================================== + // =====[ special_register_unit ]===================================== + // =================================================================== + { + src = _name+"_special_register_unit"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_SPR_ACCESS_VAL - component_reexecute_unit + // out_SPR_ACCESS_ACK - component_reexecute_unit + // in_SPR_ACCESS_FRONT_END_ID - component_reexecute_unit + // in_SPR_ACCESS_CONTEXT_ID - component_reexecute_unit + // in_SPR_ACCESS_WEN - component_reexecute_unit + // in_SPR_ACCESS_NUM_GROUP - component_reexecute_unit + // in_SPR_ACCESS_NUM_REG - component_reexecute_unit + // in_SPR_ACCESS_WDATA - component_reexecute_unit + // out_SPR_ACCESS_RDATA - component_reexecute_unit + // out_SPR_ACCESS_INVALID - component_reexecute_unit + + // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name+"_glue"; + +#ifdef POSITION + _component->interface_map (src ,"spr_read_"+toString(i)+"_"+toString(j), + dest,"spr_" +toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_SPR_READ_"+toString(i)+"_"+toString(j)+ "_SR", + dest, "in_SPR_" +toString(i)+"_"+toString(j)+"_SPECIAL_REGISTER_UNIT_SR"); + } + + // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_SPR_COMMIT_VAL - component_commit_unit + // out_SPR_COMMIT_ACK - component_commit_unit + // in_SPR_COMMIT_SR_F_VAL - component_commit_unit + // in_SPR_COMMIT_SR_F - component_commit_unit + // in_SPR_COMMIT_SR_CY_VAL - component_commit_unit + // in_SPR_COMMIT_SR_CY - component_commit_unit + // in_SPR_COMMIT_SR_OV_VAL - component_commit_unit + // in_SPR_COMMIT_SR_OV - component_commit_unit + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context[i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"spr_event_"+toString(i)+"_"+toString(j), + dest,"spr_event_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_VAL" ); + PORT_MAP(_component,src ,"out_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_ACK" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EPCR" , + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EPCR" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EEAR_WEN" , + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EEAR_WEN" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EEAR" , + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_EEAR" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_SR_DSX" , + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_SR_DSX" ); + PORT_MAP(_component,src , "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_SR_TO_ESR", + dest, "in_SPR_EVENT_"+toString(i)+"_"+toString(j)+"_SR_TO_ESR"); + } + } + + // =================================================================== + // =====[ glue ]====================================================== + // =================================================================== + { + src = _name+"_glue"; + log_printf(TRACE,OOO_Engine,FUNCTION,_("Instance : %s"),name.c_str()); + + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_inst_decod [i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(i)+"_"+toString(j), + dest,"rename_"+toString(i)+"_"+toString(j)); +#endif + + if (_param->_have_port_front_end_id) + PORT_MAP(_component,src , "in_RENAME_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID", + dest, "in_RENAME_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID"); + + // out_RENAME_RENAME_UNIT_FRONT_END_ID - component_rename_unit + } + + // ~~~~~[ Interface : "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_sum_inst_insert; i++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"insert_"+toString(i), + dest,"insert_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_VAL" , + dest,"out_INSERT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_INSERT_"+toString(i)+"_ACK" , + dest, "in_INSERT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_RD_USE" , + dest,"out_INSERT_"+toString(i)+"_RD_USE" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_RD_NUM_REG", + dest,"out_INSERT_"+toString(i)+"_RD_NUM_REG"); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_RE_USE" , + dest,"out_INSERT_"+toString(i)+"_RE_USE" ); + PORT_MAP(_component,src ,"out_INSERT_"+toString(i)+"_RE_NUM_REG", + dest,"out_INSERT_"+toString(i)+"_RE_NUM_REG"); + } + + // in_INSERT_RENAME_UNIT_VAL - component_rename_unit + // out_INSERT_RENAME_UNIT_ACK - component_rename_unit + // in_INSERT_RENAME_UNIT_FRONT_END_ID - component_rename_unit + // in_INSERT_RENAME_UNIT_CONTEXT_ID - component_rename_unit + // in_INSERT_RENAME_UNIT_TYPE - component_rename_unit + // in_INSERT_RENAME_UNIT_OPERATION - component_rename_unit + // in_INSERT_RENAME_UNIT_NO_EXECUTE - component_rename_unit + // in_INSERT_RENAME_UNIT_HAS_IMMEDIAT - component_rename_unit + // in_INSERT_RENAME_UNIT_IMMEDIAT - component_rename_unit + // in_INSERT_RENAME_UNIT_STORE_QUEUE_PTR_WRITE - component_rename_unit + // in_INSERT_RENAME_UNIT_LOAD_QUEUE_PTR_WRITE - component_rename_unit + // in_INSERT_RENAME_UNIT_READ_RA - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RA_PHY - component_rename_unit + // in_INSERT_RENAME_UNIT_READ_RB - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RB_PHY - component_rename_unit + // in_INSERT_RENAME_UNIT_READ_RC - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RC_PHY - component_rename_unit + // in_INSERT_RENAME_UNIT_WRITE_RD - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_OLD - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RD_PHY_NEW - component_rename_unit + // in_INSERT_RENAME_UNIT_WRITE_RE - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_OLD - component_rename_unit + // in_INSERT_RENAME_UNIT_NUM_REG_RE_PHY_NEW - component_rename_unit + // + // out_INSERT_COMMIT_UNIT_VAL - component_commit_unit + // in_INSERT_COMMIT_UNIT_ACK - component_commit_unit + // out_INSERT_COMMIT_UNIT_FRONT_END_ID - component_commit_unit + // out_INSERT_COMMIT_UNIT_CONTEXT_ID - component_commit_unit + ////out_INSERT_COMMIT_UNIT_RENAME_UNIT_ID - component_commit_unit + // out_INSERT_COMMIT_UNIT_TYPE - component_commit_unit + // out_INSERT_COMMIT_UNIT_OPERATION - component_commit_unit + // out_INSERT_COMMIT_UNIT_NO_EXECUTE - component_commit_unit + // out_INSERT_COMMIT_UNIT_STORE_QUEUE_PTR_WRITE - component_commit_unit + // out_INSERT_COMMIT_UNIT_LOAD_QUEUE_PTR_WRITE - component_commit_unit + // out_INSERT_COMMIT_UNIT_READ_RA - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RA_PHY - component_commit_unit + // out_INSERT_COMMIT_UNIT_READ_RB - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RB_PHY - component_commit_unit + // out_INSERT_COMMIT_UNIT_READ_RC - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RC_PHY - component_commit_unit + // out_INSERT_COMMIT_UNIT_WRITE_RD - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_OLD - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RD_PHY_NEW - component_commit_unit + // out_INSERT_COMMIT_UNIT_WRITE_RE - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_OLD - component_commit_unit + // out_INSERT_COMMIT_UNIT_NUM_REG_RE_PHY_NEW - component_commit_unit + // + // out_INSERT_ISSUE_QUEUE_VAL - component_issue_queue + // in_INSERT_ISSUE_QUEUE_ACK - component_issue_queue + // out_INSERT_ISSUE_QUEUE_CONTEXT_ID - component_issue_queue + // out_INSERT_ISSUE_QUEUE_FRONT_END_ID - component_issue_queue + // out_INSERT_ISSUE_QUEUE_OPERATION - component_issue_queue + // out_INSERT_ISSUE_QUEUE_TYPE - component_issue_queue + // out_INSERT_ISSUE_QUEUE_STORE_QUEUE_PTR_WRITE - component_issue_queue + // out_INSERT_ISSUE_QUEUE_LOAD_QUEUE_PTR_WRITE - component_issue_queue + // out_INSERT_ISSUE_QUEUE_HAS_IMMEDIAT - component_issue_queue + // out_INSERT_ISSUE_QUEUE_IMMEDIAT - component_issue_queue + // out_INSERT_ISSUE_QUEUE_READ_RA - component_issue_queue + // out_INSERT_ISSUE_QUEUE_NUM_REG_RA - component_issue_queue + // out_INSERT_ISSUE_QUEUE_READ_RB - component_issue_queue + // out_INSERT_ISSUE_QUEUE_NUM_REG_RB - component_issue_queue + // out_INSERT_ISSUE_QUEUE_READ_RC - component_issue_queue + // out_INSERT_ISSUE_QUEUE_NUM_REG_RC - component_issue_queue + // out_INSERT_ISSUE_QUEUE_WRITE_RD - component_issue_queue + // out_INSERT_ISSUE_QUEUE_NUM_REG_RD - component_issue_queue + // out_INSERT_ISSUE_QUEUE_WRITE_RE - component_issue_queue + // out_INSERT_ISSUE_QUEUE_NUM_REG_RE - component_issue_queue + +// // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// for (uint32_t i=0; i<_param->_sum_inst_retire; i++) +// { +// dest = _name; +// #ifdef POSITION +// _component->interface_map (src ,"retire_"+toString(i), +// dest,"retire_"+toString(i)); +// #endif + +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_VAL" , +// dest,"out_RETIRE_"+toString(i)+"_VAL" ); +// PORT_MAP(_component,src , "in_RETIRE_"+toString(i)+"_ACK" , +// dest, "in_RETIRE_"+toString(i)+"_ACK" ); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RD_OLD_USE" , +// dest,"out_RETIRE_"+toString(i)+"_RD_OLD_USE" ); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RD_OLD_NUM_REG", +// dest,"out_RETIRE_"+toString(i)+"_RD_OLD_NUM_REG"); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RD_NEW_USE" , +// dest,"out_RETIRE_"+toString(i)+"_RD_NEW_USE" ); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RD_NEW_NUM_REG", +// dest,"out_RETIRE_"+toString(i)+"_RD_NEW_NUM_REG"); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RE_OLD_USE" , +// dest,"out_RETIRE_"+toString(i)+"_RE_OLD_USE" ); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RE_OLD_NUM_REG", +// dest,"out_RETIRE_"+toString(i)+"_RE_OLD_NUM_REG"); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RE_NEW_USE" , +// dest,"out_RETIRE_"+toString(i)+"_RE_NEW_USE" ); +// PORT_MAP(_component,src ,"out_RETIRE_"+toString(i)+"_RE_NEW_NUM_REG", +// dest,"out_RETIRE_"+toString(i)+"_RE_NEW_NUM_REG"); +// } + + // out_RETIRE_RENAME_UNIT_VAL - component_rename_unit + // in_RETIRE_RENAME_UNIT_ACK - component_rename_unit + // out_RETIRE_RENAME_UNIT_FRONT_END_ID - component_rename_unit + // out_RETIRE_RENAME_UNIT_WRITE_RD - component_rename_unit + // out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_OLD - component_rename_unit + // out_RETIRE_RENAME_UNIT_NUM_REG_RD_PHY_NEW - component_rename_unit + // out_RETIRE_RENAME_UNIT_WRITE_RE - component_rename_unit + // out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_OLD - component_rename_unit + // out_RETIRE_RENAME_UNIT_NUM_REG_RE_PHY_NEW - component_rename_unit + // out_RETIRE_RENAME_UNIT_EVENT_STATE - component_rename_unit + + // in_RETIRE_COMMIT_UNIT_VAL - component_commit_unit + // out_RETIRE_COMMIT_UNIT_ACK - component_commit_unit + // in_RETIRE_COMMIT_UNIT_FRONT_END_ID - component_commit_unit + // in_RETIRE_COMMIT_UNIT_WRITE_RD - component_commit_unit + // in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_OLD - component_commit_unit + // in_RETIRE_COMMIT_UNIT_NUM_REG_RD_PHY_NEW - component_commit_unit + // in_RETIRE_COMMIT_UNIT_WRITE_RE - component_commit_unit + // in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_OLD - component_commit_unit + // in_RETIRE_COMMIT_UNIT_NUM_REG_RE_PHY_NEW - component_commit_unit + // in_RETIRE_COMMIT_UNIT_EVENT_STATE - component_commit_unit + + // ~~~~~[ Interface : "spr_sr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; i++) + for (uint32_t j=0; j<_param->_nb_context [i]; j++) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"spr_"+toString(i)+"_"+toString(j), + dest,"spr_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src ,"out_SPR_"+toString(i)+"_"+toString(j)+"_SR_IEE", + dest,"out_SPR_"+toString(i)+"_"+toString(j)+"_SR_IEE"); + PORT_MAP(_component,src ,"out_SPR_"+toString(i)+"_"+toString(j)+"_SR_EPH", + dest,"out_SPR_"+toString(i)+"_"+toString(j)+"_SR_EPH"); + + // out_SPR_RENAME_UNIT_SR - component_rename_unit + // out_SPR_COMMIT_UNIT_SR_OVE - component_commit_unit + // in_SPR_SPECIAL_REGISTER_UNIT_SR - component_special_register_unit + } + + + } + + // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#if DEBUG_OOO_Engine == true + _component->test_map(); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 88) @@ -0,0 +1,167 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::deallocation" + void OOO_Engine::deallocation (void) + { + log_begin(OOO_Engine,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE2_SIGNAL( in_RENAME_VAL ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL(out_RENAME_ACK ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_FRONT_END_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_RENAME_CONTEXT_ID ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_RENAME_DEPTH ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_RENAME_TYPE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_type ); + DELETE2_SIGNAL( in_RENAME_OPERATION ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_RENAME_NO_EXECUTE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IS_DELAY_SLOT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_ADDRESS ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_RENAME_HAS_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_IMMEDIAT ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_RENAME_READ_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_NUM_REG_RA ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_register_logic ); + DELETE2_SIGNAL( in_RENAME_READ_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_NUM_REG_RB ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_register_logic ); + DELETE2_SIGNAL( in_RENAME_READ_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_NUM_REG_RC ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_special_register_logic ); + DELETE2_SIGNAL( in_RENAME_WRITE_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_NUM_REG_RD ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_general_register_logic ); + DELETE2_SIGNAL( in_RENAME_WRITE_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],1 ); + DELETE2_SIGNAL( in_RENAME_NUM_REG_RE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_special_register_logic ); + DELETE2_SIGNAL( in_RENAME_EXCEPTION_USE ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_exception_use ); + DELETE2_SIGNAL( in_RENAME_EXCEPTION ,_param->_nb_front_end,_param->_nb_inst_decod[it1],_param->_size_exception ); + + DELETE1_SIGNAL(out_ISSUE_VAL ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL( in_ISSUE_ACK ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_FRONT_END_ID ,_param->_nb_inst_issue,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_ISSUE_CONTEXT_ID ,_param->_nb_inst_issue,_param->_size_context_id ); + DELETE1_SIGNAL(out_ISSUE_PACKET_ID ,_param->_nb_inst_issue,_param->_size_rob_ptr ); + DELETE1_SIGNAL(out_ISSUE_TYPE ,_param->_nb_inst_issue,_param->_size_type ); + DELETE1_SIGNAL(out_ISSUE_OPERATION ,_param->_nb_inst_issue,_param->_size_operation ); + DELETE1_SIGNAL(out_ISSUE_STORE_QUEUE_PTR_WRITE ,_param->_nb_inst_issue,_param->_size_store_queue_ptr ); + DELETE1_SIGNAL(out_ISSUE_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_issue,_param->_size_load_queue_ptr ); + DELETE1_SIGNAL(out_ISSUE_HAS_IMMEDIAT ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_IMMEDIAT ,_param->_nb_inst_issue,_param->_size_general_data ); + DELETE1_SIGNAL(out_ISSUE_READ_RA ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_NUM_REG_RA ,_param->_nb_inst_issue,_param->_size_general_register ); + DELETE1_SIGNAL(out_ISSUE_READ_RB ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_NUM_REG_RB ,_param->_nb_inst_issue,_param->_size_general_register ); + DELETE1_SIGNAL(out_ISSUE_READ_RC ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_NUM_REG_RC ,_param->_nb_inst_issue,_param->_size_special_register ); + DELETE1_SIGNAL(out_ISSUE_WRITE_RD ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_NUM_REG_RD ,_param->_nb_inst_issue,_param->_size_general_register ); + DELETE1_SIGNAL(out_ISSUE_WRITE_RE ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_ISSUE_NUM_REG_RE ,_param->_nb_inst_issue,_param->_size_special_register ); + + DELETE2_SIGNAL( in_EXECUTE_LOOP_VAL ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); + DELETE2_SIGNAL(out_EXECUTE_LOOP_ACK ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_FRONT_END_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_front_end_id ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_CONTEXT_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_context_id ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_PACKET_ID ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_rob_ptr ); +// DELETE2_SIGNAL( in_EXECUTE_LOOP_TYPE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_type ); +// DELETE2_SIGNAL( in_EXECUTE_LOOP_OPERATION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_operation ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_FLAGS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_special_data ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_exception ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],1 ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_ADDRESS ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_EXECUTE_LOOP_DATA ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1],_param->_size_general_data ); + + DELETE1_SIGNAL(out_INSERT_VAL ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL( in_INSERT_ACK ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RD_USE ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RD_NUM_REG ,_param->_sum_inst_insert,_param->_size_general_register ); + DELETE1_SIGNAL(out_INSERT_RE_USE ,_param->_sum_inst_insert,1 ); + DELETE1_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert,_param->_size_special_register ); + +// DELETE1_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire,_param->_size_general_register ); +// DELETE1_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_general_register ); +// DELETE1_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register ); +// DELETE1_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire,1 ); +// DELETE1_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register ); + + DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue,_param->_size_front_end_id ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue,_param->_size_context_id ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue,_param->_size_depth ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue,_param->_size_general_data ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue,1 ); + + DELETE_SIGNAL (out_COMMIT_EVENT_VAL , 1); + DELETE_SIGNAL ( in_COMMIT_EVENT_ACK , 1); + DELETE_SIGNAL (out_COMMIT_EVENT_FRONT_END_ID ,_param->_size_front_end_id ); + DELETE_SIGNAL (out_COMMIT_EVENT_CONTEXT_ID ,_param->_size_context_id ); + DELETE_SIGNAL (out_COMMIT_EVENT_DEPTH ,_param->_size_depth ); + DELETE_SIGNAL (out_COMMIT_EVENT_TYPE ,_param->_size_event_type ); + DELETE_SIGNAL (out_COMMIT_EVENT_IS_DELAY_SLOT ,1 ); + DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS ,_param->_size_general_data ); + DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,_param->_size_general_data ); + DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,1 ); + DELETE_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,_param->_size_general_data ); + + DELETE2_SIGNAL( in_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_EVENT_ADDRESS ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_general_data ); + DELETE2_SIGNAL( in_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_EVENT_IS_DS_TAKE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr ); + DELETE2_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_spr ); + DELETE2_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_NB_INST_COMMIT_ALL ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); + DELETE2_SIGNAL(out_NB_INST_COMMIT_MEM ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_nb_inst_commit ); + DELETE2_SIGNAL( in_DEPTH_MIN ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth ); + DELETE2_SIGNAL( in_DEPTH_MAX ,_param->_nb_front_end,_param->_nb_context[it1],_param->_size_depth+1 ); + DELETE2_SIGNAL(out_SPR_SR_IEE ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + DELETE2_SIGNAL(out_SPR_SR_EPH ,_param->_nb_front_end,_param->_nb_context[it1],1 ); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete [] _component_rename_unit ; + delete _component_commit_unit ; + delete _component_issue_queue ; + delete _component_reexecute_unit ; + delete _component_special_register_unit ; + delete _component_glue ; + + delete _component; + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_end_cycle.cpp (revision 88) @@ -0,0 +1,45 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::end_cycle" +void OOO_Engine::end_cycle () + { + log_begin(OOO_Engine,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_allocation.cpp (revision 88) @@ -0,0 +1,45 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::statistics_allocation" + void OOO_Engine::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(OOO_Engine,FUNCTION); + + _stat = new Stat (static_cast(_name), + "OOO_Engine", + param_statistics); + + for (uint32_t i=0; i<_param->_nb_rename_unit; i++) + _stat->add_stat(_component_rename_unit [i]->_stat); + _stat->add_stat(_component_commit_unit ->_stat); + _stat->add_stat(_component_issue_queue ->_stat); + _stat->add_stat(_component_reexecute_unit ->_stat); + _stat->add_stat(_component_special_register_unit->_stat); + _stat->add_stat(_component_glue ->_stat); + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,37 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::statistics_deallocation" + void OOO_Engine::statistics_deallocation (void) + { + log_begin(OOO_Engine,FUNCTION); + + log_printf(INFO,OOO_Engine,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_transition.cpp (revision 88) @@ -0,0 +1,39 @@ +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::transition" + void OOO_Engine::transition (void) + { + log_begin(OOO_Engine,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +# endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_vhdl.cpp (revision 88) @@ -0,0 +1,43 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::vhdl" + void OOO_Engine::vhdl (void) + { + log_begin(OOO_Engine,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters.cpp (revision 88) @@ -0,0 +1,417 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::Parameters" + Parameters::Parameters (uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t nb_rename_unit , + uint32_t nb_execute_loop , + uint32_t * nb_inst_decod ,//[nb_front_end] + uint32_t * nb_inst_insert ,//[nb_rename_unit] + uint32_t * nb_inst_retire ,//[nb_rename_unit] + uint32_t nb_inst_issue , + uint32_t * nb_inst_execute ,//[nb_execute_loop] + uint32_t nb_inst_reexecute , + uint32_t nb_inst_commit , + uint32_t nb_inst_branch_complete , + uint32_t ** nb_branch_speculated ,//[nb_front_end][nb_context] + uint32_t nb_rename_unit_select , + uint32_t nb_execute_loop_select , + uint32_t size_general_data , + uint32_t size_special_data , + uint32_t * link_rename_unit_with_front_end ,//[nb_front_end] + // Commit + uint32_t size_re_order_buffer , + uint32_t nb_re_order_buffer_bank , + Tpriority_t commit_priority , + Tload_balancing_t commit_load_balancing , + // Issue + uint32_t size_issue_queue , + uint32_t nb_issue_queue_bank , + Tpriority_t issue_priority , + Tload_balancing_t issue_load_balancing , + bool ** table_routing ,//[nb_rename_unit][nb_inst_issue] + bool ** table_issue_type ,//[nb_inst_issue][nb_type] + // Reexecute + uint32_t size_reexecute_queue , + Tpriority_t reexecute_priority , + Tload_balancing_t reexecute_load_balancing , + // Rename_unit + Tpriority_t * rename_select_priority ,//[nb_rename_unit] + Tload_balancing_t * rename_select_load_balancing ,//[nb_rename_unit] + uint32_t * rename_select_nb_front_end_select,//[nb_rename_unit] + uint32_t * nb_general_register ,//[nb_rename_unit] + uint32_t * nb_special_register ,//[nb_rename_unit] + uint32_t * nb_reg_free ,//[nb_rename_unit] + uint32_t * nb_rename_unit_bank ,//[nb_rename_unit] + uint32_t * size_read_counter ,//[nb_rename_unit] + uint32_t * nb_load_store_queue ,//[nb_rename_unit] + uint32_t ** size_store_queue ,//[nb_rename_unit][nb_load_store_queue] + uint32_t ** size_load_queue ,//[nb_rename_unit][nb_load_store_queue] + uint32_t ** link_load_store_unit_with_thread ,//[nb_front_end][nb_context] + // SPR + bool *** implement_group ,//[nb_front_end][nb_context][NB_GROUP] + + bool is_toplevel + ) + { + log_begin(OOO_Engine,FUNCTION); + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_rename_unit = nb_rename_unit ; + _nb_execute_loop = nb_execute_loop ; + _nb_inst_decod = nb_inst_decod ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_retire = nb_inst_retire ; + _nb_inst_issue = nb_inst_issue ; + _nb_inst_execute = nb_inst_execute ; + _nb_inst_reexecute = nb_inst_reexecute ; + _nb_inst_commit = nb_inst_commit ; + _nb_inst_branch_complete = nb_inst_branch_complete ; + _nb_branch_speculated = nb_branch_speculated ; + _nb_rename_unit_select = nb_rename_unit_select ; + _nb_execute_loop_select = nb_execute_loop_select ; +// _size_general_data = size_general_data ; +// _size_special_data = size_special_data ; + _link_rename_unit_with_front_end = link_rename_unit_with_front_end ; + _size_re_order_buffer = size_re_order_buffer ; + _nb_re_order_buffer_bank = nb_re_order_buffer_bank ; + _commit_priority = commit_priority ; + _commit_load_balancing = commit_load_balancing ; + _size_issue_queue = size_issue_queue ; + _nb_issue_queue_bank = nb_issue_queue_bank ; + _issue_priority = issue_priority ; + _issue_load_balancing = issue_load_balancing ; + _table_routing = table_routing ; + _table_issue_type = table_issue_type ; + _size_reexecute_queue = size_reexecute_queue ; + _reexecute_priority = reexecute_priority ; + _reexecute_load_balancing = reexecute_load_balancing ; + _rename_select_priority = rename_select_priority ; + _rename_select_load_balancing = rename_select_load_balancing ; + _rename_select_nb_front_end_select = rename_select_nb_front_end_select; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_reg_free = nb_reg_free ; + _nb_rename_unit_bank = nb_rename_unit_bank ; + _size_read_counter = size_read_counter ; + _nb_load_store_queue = nb_load_store_queue ; + _size_store_queue = size_store_queue ; + _size_load_queue = size_load_queue ; + _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; + _implement_group = implement_group ; + + test(); + + _link_front_end_with_rename_unit = new std::vector [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_front_end; i++) + _link_front_end_with_rename_unit[_link_rename_unit_with_front_end[i]].push_back(i); + + _rename_unit_size_front_end_id = new uint32_t [_nb_rename_unit]; + _rename_unit_size_context_id = new uint32_t [_nb_rename_unit]; + _rename_unit_nb_front_end = new uint32_t [_nb_rename_unit]; + _rename_unit_nb_context = new uint32_t * [_nb_rename_unit]; + _rename_unit_nb_inst_decod = new uint32_t * [_nb_rename_unit]; + _rename_unit_link_load_store_unit_with_thread = new uint32_t ** [_nb_rename_unit]; + + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + uint32_t x = _link_front_end_with_rename_unit[i].size(); // number of linked front_end + + _rename_unit_nb_front_end [i] = x; + _rename_unit_nb_context [i] = new uint32_t [x]; + _rename_unit_nb_inst_decod [i] = new uint32_t [x]; + _rename_unit_link_load_store_unit_with_thread [i] = new uint32_t * [x]; + + // Scan front_end list + std::vector::iterator it=_link_front_end_with_rename_unit[i].begin(); + for (uint32_t j=0; j(_rename_unit_nb_context [i], _rename_unit_nb_front_end [i])); + } + + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + log_printf(TRACE,OOO_Engine,FUNCTION,"Rename_unit [%d]",i); + log_printf(TRACE,OOO_Engine,FUNCTION," * front_end : %d",_rename_unit_nb_front_end[i]); + + for (uint32_t j=0; j<_rename_unit_nb_front_end[i]; j++) + { + log_printf(TRACE,OOO_Engine,FUNCTION," * [%d] nb_context : %d, nb_inst_decod : %d",j,_rename_unit_nb_context[i][j],_rename_unit_nb_inst_decod[i][j]); + + for (uint32_t k=0; k<_rename_unit_nb_context[i][j]; ++k) + log_printf(TRACE,OOO_Engine,FUNCTION," * [%d][%d] link_lsq : %d",j,k,_rename_unit_link_load_store_unit_with_thread[i][j][k]); + } + } + + _max_nb_context = max(_nb_context,_nb_front_end); + _max_branch_speculated = max(_nb_branch_speculated,_nb_front_end,_nb_context); + _size_rename_id = log2(_nb_rename_unit); +// _size_max_depth = log2(_max_branch_speculated); + uint32_t size_front_end_id = log2(_nb_front_end); + uint32_t size_context_id = log2(_max_nb_context); + uint32_t size_packet_id = log2(nb_re_order_buffer_bank)+log2(size_re_order_buffer/nb_re_order_buffer_bank); + uint32_t size_general_register = log2(max(_nb_general_register,_nb_rename_unit)); + uint32_t size_special_register = log2(max(_nb_special_register,_nb_rename_unit)); + uint32_t size_store_queue_ptr = log2(max(_size_store_queue,_nb_rename_unit,_nb_load_store_queue)); + uint32_t size_load_queue_ptr = log2(max(_size_load_queue ,_nb_rename_unit,_nb_load_store_queue)); + + _sum_inst_insert = 0; + _sum_inst_retire = 0; + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + _sum_inst_insert += _nb_inst_insert [i]; + _sum_inst_retire += _nb_inst_retire [i]; + + log_printf(TRACE,OOO_Engine,FUNCTION,"rename_unit [%d] - nb_inst_insert %d, nb_inst_retire %d", i,_nb_inst_insert [i],_nb_inst_retire [i]); + } + + log_printf(TRACE,OOO_Engine,FUNCTION,"sum_inst_insert %d, sum_inst_retire %d",_sum_inst_insert,_sum_inst_retire); + +// _have_port_front_end_id = _size_front_end_id > 0; +// _have_port_context_id = _size_context_id > 0; +// _have_port_packet_id = _size_packet_id > 0; + _have_port_rename_id = _size_rename_id > 0; +// _have_port_load_queue_ptr = _size_load_queue_ptr > 0; +// _have_port_max_depth = _size_max_depth > 0; +// _have_port_depth = _param_commit_unit->_have_port_depth; + + _param_rename_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters * [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _param_rename_unit [i] = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::Parameters + ( + _rename_unit_nb_front_end [i], + _rename_unit_nb_context [i], + _rename_unit_nb_inst_decod [i], + _nb_inst_insert [i], + _nb_inst_retire [i], + _nb_load_store_queue [i], + _size_store_queue [i], + _size_load_queue [i], + _rename_unit_link_load_store_unit_with_thread [i], + _rename_select_priority [i], + _rename_select_load_balancing [i], + _rename_select_nb_front_end_select [i], + _max_branch_speculated , + size_general_data , + _nb_general_register [i], + _nb_special_register [i], + _nb_reg_free [i], + _nb_rename_unit_bank [i], + _size_read_counter [i] + ); + + _param_commit_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Parameters + ( + _nb_front_end , + _nb_context , + _nb_rename_unit , + _size_re_order_buffer , + _nb_re_order_buffer_bank , + _nb_inst_insert , + _nb_inst_retire , + _nb_inst_commit , + _nb_inst_reexecute , + _nb_inst_branch_complete , + _nb_branch_speculated , + size_general_data , + size_store_queue_ptr , + size_load_queue_ptr , + size_general_register , + size_special_register , + _commit_priority , + _commit_load_balancing , + _nb_rename_unit_select + ); + + + _param_issue_queue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Parameters + (_max_nb_context , + _nb_front_end , + _nb_rename_unit , + _size_issue_queue , + _nb_issue_queue_bank , + size_packet_id , + size_general_data , + size_special_data , + size_general_register ,//+_size_rename_id + size_special_register ,//+_size_rename_id + size_store_queue_ptr , + size_load_queue_ptr , + _nb_inst_issue , + _nb_inst_insert , + _nb_inst_reexecute , + _nb_rename_unit_select , + _issue_priority , + _issue_load_balancing , + _table_routing , + _table_issue_type + ); + + _param_reexecute_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::reexecute_unit::Parameters + ( size_context_id , + size_front_end_id , + size_packet_id , + _size_reexecute_queue , + _nb_execute_loop , + _nb_inst_execute , + _nb_inst_commit , + _nb_inst_reexecute , + _nb_execute_loop_select , + _reexecute_priority , + _reexecute_load_balancing, + size_general_register ,//+_size_rename_id + size_special_register ,//+_size_rename_id + size_general_data , + size_special_data , + size_store_queue_ptr , + size_load_queue_ptr + ); + + _param_special_register_unit = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters + ( + _nb_front_end , + _nb_context , + _nb_inst_reexecute , + _implement_group + ); + + _param_glue = new morpheo::behavioural::core::multi_ooo_engine::ooo_engine::ooo_engine_glue::Parameters + (_nb_front_end , + _nb_context , + _nb_rename_unit , + _nb_inst_decod , + _nb_inst_insert , + _nb_inst_retire , + size_general_data , + size_special_data , + _link_rename_unit_with_front_end , + _link_front_end_with_rename_unit , + size_packet_id , + size_general_register , + size_special_register , + size_store_queue_ptr , + size_load_queue_ptr + ); + + if (is_toplevel) + { + _size_front_end_id = size_front_end_id; + _size_context_id = size_context_id ; + _size_depth = log2(_max_branch_speculated); + _size_instruction_address = size_general_data-2; + _size_general_data = size_general_data; + _size_special_data = size_special_data; + _size_general_register = size_general_register; + _size_special_register = size_special_register; + _size_store_queue_ptr = size_store_queue_ptr ; + _size_load_queue_ptr = size_load_queue_ptr ; + _size_rob_ptr = size_packet_id; + _size_nb_inst_commit = log2(size_re_order_buffer)+1; + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + _have_port_depth = _size_depth > 0; + + copy(); + } + + + log_end(OOO_Engine,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "OOO_Engine::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(OOO_Engine,FUNCTION); +// test(); +// log_end(OOO_Engine,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine::~Parameters" + Parameters::~Parameters (void) + { + log_begin(OOO_Engine,FUNCTION); + + for (uint32_t i=0; i<_nb_rename_unit; i++) + { + for (uint32_t j=0; j<_nb_front_end; j++) + delete [] _rename_unit_link_load_store_unit_with_thread [i][j]; + + delete [] _rename_unit_link_load_store_unit_with_thread [i]; + delete [] _rename_unit_nb_inst_decod [i]; + delete [] _rename_unit_nb_context [i]; + } + + delete [] _rename_unit_link_load_store_unit_with_thread; + delete [] _rename_unit_nb_inst_decod ; + delete [] _rename_unit_nb_context ; + delete [] _rename_unit_nb_front_end ; + delete [] _rename_unit_size_front_end_id ; + delete [] _rename_unit_size_context_id ; + delete [] _link_front_end_with_rename_unit ; + + delete [] _param_rename_unit ; + delete _param_commit_unit ; + delete _param_issue_queue ; + delete _param_reexecute_unit ; + delete _param_special_register_unit; + delete _param_glue ; + + log_end(OOO_Engine,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine::copy" + void Parameters::copy (void) + { + log_begin(OOO_Engine,FUNCTION); + + for (uint32_t i=0; i<_nb_rename_unit; i++) + COPY(_param_rename_unit [i]); + COPY(_param_commit_unit ); + COPY(_param_issue_queue ); + COPY(_param_reexecute_unit ); + COPY(_param_special_register_unit); + COPY(_param_glue ); + + log_end(OOO_Engine,FUNCTION); + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,55 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(OOO_Engine,FUNCTION); + + Parameters_test test ("OOO_Engine"); + + bool _is_link [_nb_rename_unit]; + for (uint32_t i=0; i<_nb_rename_unit; i++) + _is_link[i] = false; + + for (uint32_t i=0; i<_nb_front_end; i++) + { + uint32_t x = _link_rename_unit_with_front_end [i]; + + if (x >= _nb_rename_unit) + test.error(toString(_("Front_end [%d] is linked with invalid rename_unit.\n"),i)); + else + _is_link [x] = true; + } + + for (uint32_t i=0; i<_nb_rename_unit; i++) + if (_is_link[i] == false) + test.error(toString(_("Rename_unit [%d] is not linked with front_end.\n"),i)); + + log_end(OOO_Engine,FUNCTION); + + return test; + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,132 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { +namespace multi_ooo_engine { +namespace ooo_engine { + + +#undef FUNCTION +#define FUNCTION "OOO_Engine::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(OOO_Engine,FUNCTION); + + std::string str = ""; + + str+= toString(MSG_INFORMATION)+" * nb_front_end : "+toString(_nb_front_end )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + str+= toString(MSG_INFORMATION)+" * nb_context ["+toString(i)+"] : "+toString(_nb_context [i] )+"\n";//[nb_front_end] + str+= toString(MSG_INFORMATION)+" * nb_rename_unit : "+toString(_nb_rename_unit )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_execute_loop : "+toString(_nb_execute_loop )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + str+= toString(MSG_INFORMATION)+" * nb_inst_decod ["+toString(i)+"] : "+toString(_nb_inst_decod [i] )+"\n";//[nb_front_end] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_inst_insert ["+toString(i)+"] : "+toString(_nb_inst_insert [i] )+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_inst_retire ["+toString(i)+"] : "+toString(_nb_inst_retire [i] )+"\n";//[nb_rename_unit] + str+= toString(MSG_INFORMATION)+" * nb_inst_issue : "+toString(_nb_inst_issue )+"\n"; + for (uint32_t i=0; i<_nb_execute_loop; ++i) + str+= toString(MSG_INFORMATION)+" * nb_inst_execute ["+toString(i)+"] : "+toString(_nb_inst_execute [i] )+"\n";//[nb_execute_loop] + str+= toString(MSG_INFORMATION)+" * nb_inst_reexecute : "+toString(_nb_inst_reexecute )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_commit : "+toString(_nb_inst_commit )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_branch_complete : "+toString(_nb_inst_branch_complete )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + str+= toString(MSG_INFORMATION)+" * nb_branch_speculated ["+toString(i)+"]["+toString(j)+"] : "+toString(_nb_branch_speculated [i][j] )+"\n";//[nb_front_end][nb_context] + str+= toString(MSG_INFORMATION)+" * nb_rename_unit_select : "+toString(_nb_rename_unit_select )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_execute_loop_select : "+toString(_nb_execute_loop_select )+"\n"; + str+= toString(MSG_INFORMATION)+" * size_general_data : "+toString(_size_general_data )+"\n"; + str+= toString(MSG_INFORMATION)+" * size_special_data : "+toString(_size_special_data )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + str+= toString(MSG_INFORMATION)+" * link_rename_unit_with_front_end ["+toString(i)+"] : "+toString(_link_rename_unit_with_front_end[i])+"\n";//[nb_front_end] + str+= toString(MSG_INFORMATION)+" * size_re_order_buffer : "+toString(_size_re_order_buffer )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_re_order_buffer_bank : "+toString(_nb_re_order_buffer_bank )+"\n"; + str+= toString(MSG_INFORMATION)+" * commit_priority : "+toString(_commit_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * commit_load_balancing : "+toString(_commit_load_balancing )+"\n"; + str+= toString(MSG_INFORMATION)+" * size_issue_queue : "+toString(_size_issue_queue )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_issue_queue_bank : "+toString(_nb_issue_queue_bank )+"\n"; + str+= toString(MSG_INFORMATION)+" * issue_priority : "+toString(_issue_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * issue_load_balancing : "+toString(_issue_load_balancing )+"\n"; + for (uint32_t i=0; i<_nb_rename_unit; ++i) + for (uint32_t j=0; j<_nb_inst_issue ; ++j) + str+= toString(MSG_INFORMATION)+" * table_routing ["+toString(i)+"]["+toString(j)+"] : "+toString(_table_routing [i][j] )+"\n";//[nb_rename_unit][nb_inst_issue] + for (uint32_t i=0; i<_nb_inst_issue ; ++i) + for (uint32_t j=0; j<_nb_type; ++j) + str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString_type(j)+"] : "+toString(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type] + str+= toString(MSG_INFORMATION)+" * size_reexecute_queue : "+toString(_size_reexecute_queue )+"\n"; + str+= toString(MSG_INFORMATION)+" * reexecute_priority : "+toString(_reexecute_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * reexecute_load_balancing : "+toString(_reexecute_load_balancing )+"\n"; + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * rename_select_priority ["+toString(i)+"] : "+toString(_rename_select_priority [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * rename_select_load_balancing ["+toString(i)+"] : "+toString(_rename_select_load_balancing [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * rename_select_nb_front_end_select ["+toString(i)+"] : "+toString(_rename_select_nb_front_end_select[i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_general_register ["+toString(i)+"] : "+toString(_nb_general_register [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_special_register ["+toString(i)+"] : "+toString(_nb_special_register [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_reg_free ["+toString(i)+"] : "+toString(_nb_reg_free [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_rename_unit_bank ["+toString(i)+"] : "+toString(_nb_rename_unit_bank [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * size_read_counter ["+toString(i)+"] : "+toString(_size_read_counter [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + str+= toString(MSG_INFORMATION)+" * nb_load_store_queue ["+toString(i)+"] : "+toString(_nb_load_store_queue [i])+"\n";//[nb_rename_unit] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + for (uint32_t j=0; j<_nb_load_store_queue[i]; ++j) + str+= toString(MSG_INFORMATION)+" * size_store_queue ["+toString(i)+"]["+toString(j)+"] : "+toString(_size_store_queue [i][j])+"\n";//[nb_rename_unit][nb_load_store_queue] + for (uint32_t i=0; i<_nb_rename_unit; ++i) + for (uint32_t j=0; j<_nb_load_store_queue[i]; ++j) + str+= toString(MSG_INFORMATION)+" * size_load_queue ["+toString(i)+"]["+toString(j)+"] : "+toString(_size_load_queue [i][j])+"\n";//[nb_rename_unit][nb_load_store_queue] + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + str+= toString(MSG_INFORMATION)+" * link_load_store_unit_with_thread ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_load_store_unit_with_thread [i][j])+"\n";//[nb_front_end][nb_context] + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + for (uint32_t k=0; k(_implement_group [i][j][k])+"\n";//[nb_front_end][nb_context][NB_GROUP] + +// XML xml ("ooo_engine"); + +// xml.balise_open("ooo_engine"); +// // xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); +// xml.balise_close(); + + log_end(OOO_Engine,FUNCTION); + +// return xml.get_body(depth); + return str; + }; + +#undef FUNCTION +#define FUNCTION "OOO_Engine::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::multi_ooo_engine::ooo_engine::Parameters & x) + { + log_begin(OOO_Engine,FUNCTION); + + output_stream << x.print(0); + + log_end(OOO_Engine,FUNCTION); + + return output_stream; + }; + +}; // end namespace ooo_engine +}; // end namespace multi_ooo_engine +}; // end namespace core + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Core_LIBRARY) + +DIR_LIBRARY = $(Core_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Core_library + +library_clean : Core_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 88) @@ -0,0 +1,133 @@ +Core +32 32 +1 # size_general_data +2 2 +1 # size_special_data +1 1 +1 # nb_thread +1 1 +1 # size_ifetch_queue [0] [nb_thread] +1 1 +1 # nb_inst_fetch [0] [nb_thread] +2 2 +1 # ras_size_queue [0] [nb_thread] +1 1 +1 # upt_size_queue [0] [nb_thread] +1 1 +1 # nb_decod_bloc +1 1 +1 # size_decod_queue [0] [nb_decod_bloc] +1 1 +1 # nb_inst_decod [0] [nb_decod_bloc] +1 1 +1 # nb_context_select [0] [nb_decod_bloc] +1 1 +1 # context_select_priority [0] [nb_decod_bloc] +1 1 +1 # context_select_load_balancing [0] [nb_decod_bloc] +1 1 +1 # nb_rename_bloc +1 1 +1 # nb_inst_insert [0] [nb_rename_bloc] +1 1 +1 # nb_inst_retire [0] [nb_rename_bloc] +1 1 +1 # rename_select_priority [0] [nb_rename_bloc] +1 1 +1 # rename_select_load_balancing [0] [nb_rename_bloc] +1 1 +1 # rename_select_nb_front_end_select [0] [nb_rename_bloc] +64 64 +1 # nb_general_register [0] [nb_rename_bloc] +4 4 +1 # nb_special_register [0] [nb_rename_bloc] +1 1 +1 # nb_reg_free [0] [nb_rename_bloc] +1 1 +1 # nb_rename_unit_bank [0] [nb_rename_bloc] +1 1 +1 # size_read_counter [0] [nb_rename_bloc] +1 1 +1 # nb_read_bloc +1 1 +1 # size_read_queue [0] [nb_read_bloc] +1 1 +1 # size_reservation_station [0] [nb_read_bloc] +1 1 +1 # nb_inst_retire_reservation_station [0] [nb_read_bloc] +1 1 +1 # nb_write_bloc +1 1 +1 # size_write_queue [0] [nb_write_bloc] +1 1 +1 # size_execute_queue [0] [nb_write_bloc] +0 0 +1 # nb_bypass_write [0] [nb_write_bloc] +1 1 +1 # nb_load_store_unit +2 2 +1 # size_store_queue [0] [nb_load_store_unit] +1 1 +1 # size_load_queue [0] [nb_load_store_unit] +1 1 +1 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_inst_functionnal_unit [0] [nb_functionnal_unit] +1 1 +1 # nb_icache_port +1 1 +1 # icache_access_priority +1 1 +1 # icache_access_load_balancing +1 1 +1 # nb_dcache_port +1 1 +1 # dcache_access_priority +1 1 +1 # dcache_access_load_balancing +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_decod_unit [0] [nb_front_end] +1 1 +1 # nb_inst_branch_predict [0] [nb_front_end] +1 1 +1 # nb_inst_branch_decod [0] [nb_front_end] +1 1 +1 # nb_inst_branch_update [0] [nb_front_end] +1 1 +1 # btb_size_queue [0] [nb_front_end] +1 1 +1 # btb_associativity [0] [nb_front_end] +2 2 +1 # btb_size_counter [0] [nb_front_end] +1 1 +1 # btb_victim_scheme [0] [nb_front_end] +1 1 +1 # dir_predictor_scheme [0] [nb_front_end] +1 1 +1 # dir_have_bht [0][0] [nb_front_end][3] +1 1 +1 # dir_have_bht [0][1] [nb_front_end][3] +1 1 +1 # dir_have_bht [0][2] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][0] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][1] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][2] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][0] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][1] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][2] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][0] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][1] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][2] [nb_front_end][3] +1 1 +1 # nb_ooo_engine +1 1 +1 # nb_rename_unit [0] [nb_ooo_engine] +1 1 +1 # nb_inst_issue [0] [nb_ooo_engine] +1 1 +1 # nb_inst_reexecute [0] [nb_ooo_engine] +1 1 +1 # nb_inst_commit [0] [nb_ooo_engine] +1 1 +1 # nb_inst_branch_complete [0] [nb_ooo_engine] +1 1 +1 # nb_rename_unit_select [0] [nb_ooo_engine] +1 1 +1 # nb_execute_loop_select [0] [nb_ooo_engine] +1 1 +1 # size_re_order_buffer [0] [nb_ooo_engine] +1 1 +1 # nb_re_order_buffer_bank [0] [nb_ooo_engine] +1 1 +1 # commit_priority [0] [nb_ooo_engine] +1 1 +1 # commit_load_balancing [0] [nb_ooo_engine] +1 1 +1 # size_issue_queue [0] [nb_ooo_engine] +1 1 +1 # nb_issue_queue_bank [0] [nb_ooo_engine] +1 1 +1 # issue_priority [0] [nb_ooo_engine] +1 1 +1 # issue_load_balancing [0] [nb_ooo_engine] +1 1 +1 # size_reexecute_queue [0] [nb_ooo_engine] +1 1 +1 # reexecute_priority [0] [nb_ooo_engine] +1 1 +1 # reexecute_load_balancing [0] [nb_ooo_engine] +1 1 +1 # nb_execute_loop +1 1 +1 # nb_read_unit [0] [nb_execute_loop] +2 2 +1 # nb_execute_unit [0] [nb_execute_loop] +1 1 +1 # nb_write_unit [0] [nb_execute_loop] +1 1 +1 # nb_gpr_bank [0] [nb_execute_loop] +1 1 +1 # nb_gpr_port_read_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_gpr_port_write_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_port_read_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_port_write_by_bank [0] [nb_execute_loop] +1 1 +1 # execution_unit_to_write_unit_priority [0] [nb_execute_loop] +1 1 +1 # read_unit_to_execution_unit_priority [0] [nb_execute_loop] +0 0 +1 # link_context_with_thread [0] [nb_thread] +0 0 +1 # link_decod_unit_with_decod_bloc [0] [nb_decod_bloc] +0 0 +1 # link_rename_unit_with_rename_bloc [0] [nb_rename_bloc] +0 0 +1 # link_read_unit_with_read_bloc [0] [nb_read_bloc] +0 0 +1 # link_write_unit_with_write_bloc [0] [nb_write_bloc] +0 0 +1 # link_execute_unit_with_functionnal_unit [0] [nb_functionnal_unit] +1 1 +1 # link_execute_unit_with_load_store_unit [0] [nb_load_store_unit] +0 0 +1 # link_decod_bloc_with_thread [0] [nb_thread] +0 0 +1 # link_rename_bloc_with_front_end [0] [nb_front_end] +1 1 +1 # table_dispatch [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] +1 1 +1 # link_read_bloc_and_load_store_unit [0][0] [nb_read_bloc][nb_load_store_unit] +1 1 +1 # link_read_bloc_and_functionnal_unit [0][0] [nb_read_bloc][nb_functionnal_unit] +1 1 +1 # link_write_bloc_and_load_store_unit [0][0] [nb_write_bloc][nb_load_store_unit] +1 1 +1 # link_write_bloc_and_functionnal_unit [0][0] [nb_write_bloc][nb_functionnal_unit] +0 0 +1 # link_load_store_unit_with_thread [0] [nb_thread] +1 1 +1 # link_thread_and_functionnal_unit [0][0] [nb_thread][nb_functionnal_unit] +0 0 +1 # link_icache_port_with_thread [0] [nb_thread] +0 0 +1 # link_dcache_port_with_load_store_unit [0][0] [nb_load_store_unit][nb_cache_port] +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 88) @@ -0,0 +1,133 @@ +Core +32 32 +1 # size_general_data +2 2 +1 # size_special_data +1 1 +1 # nb_thread +4 4 +1 # size_ifetch_queue [0] [nb_thread] +1 1 +1 # nb_inst_fetch [0] [nb_thread] +4 4 +1 # ras_size_queue [0] [nb_thread] +4 4 +1 # upt_size_queue [0] [nb_thread] +1 1 +1 # nb_decod_bloc +4 4 +1 # size_decod_queue [0] [nb_decod_bloc] +1 1 +1 # nb_inst_decod [0] [nb_decod_bloc] +1 1 +1 # nb_context_select [0] [nb_decod_bloc] +1 1 +1 # context_select_priority [0] [nb_decod_bloc] +1 1 +1 # context_select_load_balancing [0] [nb_decod_bloc] +1 1 +1 # nb_rename_bloc +1 1 +1 # nb_inst_insert [0] [nb_rename_bloc] +1 1 +1 # nb_inst_retire [0] [nb_rename_bloc] +1 1 +1 # rename_select_priority [0] [nb_rename_bloc] +1 1 +1 # rename_select_load_balancing [0] [nb_rename_bloc] +1 1 +1 # rename_select_nb_front_end_select [0] [nb_rename_bloc] +64 64 +1 # nb_general_register [0] [nb_rename_bloc] +4 4 +1 # nb_special_register [0] [nb_rename_bloc] +1 1 +1 # nb_reg_free [0] [nb_rename_bloc] +1 1 +1 # nb_rename_unit_bank [0] [nb_rename_bloc] +4 4 +1 # size_read_counter [0] [nb_rename_bloc] +1 1 +1 # nb_read_bloc +4 4 +1 # size_read_queue [0] [nb_read_bloc] +4 4 +1 # size_reservation_station [0] [nb_read_bloc] +1 1 +1 # nb_inst_retire_reservation_station [0] [nb_read_bloc] +1 1 +1 # nb_write_bloc +4 4 +1 # size_write_queue [0] [nb_write_bloc] +4 4 +1 # size_execute_queue [0] [nb_write_bloc] +0 0 +1 # nb_bypass_write [0] [nb_write_bloc] +1 1 +1 # nb_load_store_unit +4 4 +1 # size_store_queue [0] [nb_load_store_unit] +4 4 +1 # size_load_queue [0] [nb_load_store_unit] +4 4 +1 # size_speculative_access_queue [0] [nb_load_store_unit] +1 1 +1 # nb_port_check [0] [nb_load_store_unit] +2 2 +1 # speculative_load [0] [nb_load_store_unit] +0 0 +1 # nb_bypass_memory [0] [nb_load_store_unit] +1 1 +1 # nb_cache_port [0] [nb_load_store_unit] +1 1 +1 # nb_inst_memory [0] [nb_load_store_unit] +1 1 +1 # nb_functionnal_unit +1 1 +1 # nb_inst_functionnal_unit [0] [nb_functionnal_unit] +1 1 +1 # nb_icache_port +1 1 +1 # icache_access_priority +1 1 +1 # icache_access_load_balancing +1 1 +1 # nb_dcache_port +1 1 +1 # dcache_access_priority +1 1 +1 # dcache_access_load_balancing +1 1 +1 # nb_front_end +1 1 +1 # nb_context [0] [nb_front_end] +1 1 +1 # nb_decod_unit [0] [nb_front_end] +1 1 +1 # nb_inst_branch_predict [0] [nb_front_end] +1 1 +1 # nb_inst_branch_decod [0] [nb_front_end] +1 1 +1 # nb_inst_branch_update [0] [nb_front_end] +32 32 +1 # btb_size_queue [0] [nb_front_end] +2 2 +1 # btb_associativity [0] [nb_front_end] +2 2 +1 # btb_size_counter [0] [nb_front_end] +3 3 +1 # btb_victim_scheme [0] [nb_front_end] +1 1 +1 # dir_predictor_scheme [0] [nb_front_end] +1 1 +1 # dir_have_bht [0][0] [nb_front_end][3] +1 1 +1 # dir_have_bht [0][1] [nb_front_end][3] +1 1 +1 # dir_have_bht [0][2] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][0] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][1] [nb_front_end][3] +1 1 +1 # dir_bht_size_shifter [0][2] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][0] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][1] [nb_front_end][3] +1 1 +1 # dir_bht_nb_shifter [0][2] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][0] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][1] [nb_front_end][3] +1 1 +1 # dir_have_pht [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_size_counter [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_nb_counter [0][2] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][0] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][1] [nb_front_end][3] +1 1 +1 # dir_pht_size_address_share [0][2] [nb_front_end][3] +1 1 +1 # nb_ooo_engine +1 1 +1 # nb_rename_unit [0] [nb_ooo_engine] +1 1 +1 # nb_inst_issue [0] [nb_ooo_engine] +1 1 +1 # nb_inst_reexecute [0] [nb_ooo_engine] +1 1 +1 # nb_inst_commit [0] [nb_ooo_engine] +1 1 +1 # nb_inst_branch_complete [0] [nb_ooo_engine] +1 1 +1 # nb_rename_unit_select [0] [nb_ooo_engine] +1 1 +1 # nb_execute_loop_select [0] [nb_ooo_engine] +32 32 +1 # size_re_order_buffer [0] [nb_ooo_engine] +1 1 +1 # nb_re_order_buffer_bank [0] [nb_ooo_engine] +1 1 +1 # commit_priority [0] [nb_ooo_engine] +1 1 +1 # commit_load_balancing [0] [nb_ooo_engine] +4 4 +1 # size_issue_queue [0] [nb_ooo_engine] +1 1 +1 # nb_issue_queue_bank [0] [nb_ooo_engine] +1 1 +1 # issue_priority [0] [nb_ooo_engine] +1 1 +1 # issue_load_balancing [0] [nb_ooo_engine] +4 4 +1 # size_reexecute_queue [0] [nb_ooo_engine] +1 1 +1 # reexecute_priority [0] [nb_ooo_engine] +1 1 +1 # reexecute_load_balancing [0] [nb_ooo_engine] +1 1 +1 # nb_execute_loop +1 1 +1 # nb_read_unit [0] [nb_execute_loop] +2 2 +1 # nb_execute_unit [0] [nb_execute_loop] +1 1 +1 # nb_write_unit [0] [nb_execute_loop] +1 1 +1 # nb_gpr_bank [0] [nb_execute_loop] +1 1 +1 # nb_gpr_port_read_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_gpr_port_write_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_port_read_by_bank [0] [nb_execute_loop] +1 1 +1 # nb_spr_port_write_by_bank [0] [nb_execute_loop] +1 1 +1 # execution_unit_to_write_unit_priority [0] [nb_execute_loop] +1 1 +1 # read_unit_to_execution_unit_priority [0] [nb_execute_loop] +0 0 +1 # link_context_with_thread [0] [nb_thread] +0 0 +1 # link_decod_unit_with_decod_bloc [0] [nb_decod_bloc] +0 0 +1 # link_rename_unit_with_rename_bloc [0] [nb_rename_bloc] +0 0 +1 # link_read_unit_with_read_bloc [0] [nb_read_bloc] +0 0 +1 # link_write_unit_with_write_bloc [0] [nb_write_bloc] +0 0 +1 # link_execute_unit_with_functionnal_unit [0] [nb_functionnal_unit] +1 1 +1 # link_execute_unit_with_load_store_unit [0] [nb_load_store_unit] +0 0 +1 # link_decod_bloc_with_thread [0] [nb_thread] +0 0 +1 # link_rename_bloc_with_front_end [0] [nb_front_end] +1 1 +1 # table_dispatch [0][0][0] [nb_ooo_engine][nb_inst_issue][nb_read_bloc] +1 1 +1 # link_read_bloc_and_load_store_unit [0][0] [nb_read_bloc][nb_load_store_unit] +1 1 +1 # link_read_bloc_and_functionnal_unit [0][0] [nb_read_bloc][nb_functionnal_unit] +1 1 +1 # link_write_bloc_and_load_store_unit [0][0] [nb_write_bloc][nb_load_store_unit] +1 1 +1 # link_write_bloc_and_functionnal_unit [0][0] [nb_write_bloc][nb_functionnal_unit] +0 0 +1 # link_load_store_unit_with_thread [0] [nb_thread] +1 1 +1 # link_thread_and_functionnal_unit [0][0] [nb_thread][nb_functionnal_unit] +0 0 +1 # link_icache_port_with_thread [0] [nb_thread] +0 0 +1 # link_dcache_port_with_load_store_unit [0][0] [nb_load_store_unit][nb_cache_port] +1 1 +1 # dispatch_priority +1 1 +1 # dispatch_load_balancing Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/include/test.h (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Core/include/Core.h" +#include "Behavioural/include/Selftest.h" +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::core; + +void test (string name, + morpheo::behavioural::core::Parameters * param); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,777 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/SelfTest/include/test.h" +#include "Common/include/Max.h" + +#define NB_PARAMS 20 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * size_general_data (uint32_t )\n")); + err (_(" * size_special_data (uint32_t )\n")); +//morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + + err (_(" * nb_thread (uint32_t )\n")); + err (_(" * size_ifetch_queue [nb_thread] (uint32_t )\n")); + err (_(" * nb_inst_fetch [nb_thread] (uint32_t )\n")); +//err (_(" * implement_group [nb_thread][NB_GROUP] (bool )\n")); + err (_(" * ras_size_queue [nb_thread] (uint32_t )\n")); + err (_(" * upt_size_queue [nb_thread] (uint32_t )\n")); + + err (_(" * nb_decod_bloc (uint32_t )\n")); + err (_(" * size_decod_queue [nb_decod_bloc] (uint32_t )\n")); + err (_(" * nb_inst_decod [nb_decod_bloc] (uint32_t )\n")); + err (_(" * nb_context_select [nb_decod_bloc] (uint32_t )\n")); + err (_(" * context_select_priority [nb_decod_bloc] (Tpriority_t )\n")); + err (_(" * context_select_load_balancing [nb_decod_bloc] (Tload_balancing_t)\n")); + + err (_(" * nb_rename_bloc (uint32_t )\n")); + err (_(" * nb_inst_insert [nb_rename_bloc] (uint32_t )\n")); + err (_(" * nb_inst_retire [nb_rename_bloc] (uint32_t )\n")); + err (_(" * rename_select_priority [nb_rename_bloc] (Tpriority_t )\n")); + err (_(" * rename_select_load_balancing [nb_rename_bloc] (Tload_balancing_t)\n")); + err (_(" * rename_select_nb_front_end_select [nb_rename_bloc] (uint32_t )\n")); + err (_(" * nb_general_register [nb_rename_bloc] (uint32_t )\n")); + err (_(" * nb_special_register [nb_rename_bloc] (uint32_t )\n")); + err (_(" * nb_reg_free [nb_rename_bloc] (uint32_t )\n")); + err (_(" * nb_rename_unit_bank [nb_rename_bloc] (uint32_t )\n")); + err (_(" * size_read_counter [nb_rename_bloc] (uint32_t )\n")); + + err (_(" * nb_read_bloc (uint32_t )\n")); + err (_(" * size_read_queue [nb_read_bloc] (uint32_t )\n")); + err (_(" * size_reservation_station [nb_read_bloc] (uint32_t )\n")); + err (_(" * nb_inst_retire_reservation_station [nb_read_bloc] (uint32_t )\n")); + + err (_(" * nb_write_bloc (uint32_t )\n")); + err (_(" * size_write_queue [nb_write_bloc] (uint32_t )\n")); + err (_(" * size_execute_queue [nb_write_bloc] (uint32_t )\n")); + err (_(" * nb_bypass_write [nb_write_bloc] (uint32_t )\n")); + + err (_(" * nb_load_store_unit (uint32_t )\n")); + err (_(" * size_store_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_load_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * size_speculative_access_queue [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_port_check [nb_load_store_unit] (uint32_t )\n")); + err (_(" * speculative_load [nb_load_store_unit] (Tspeculative_load)\n")); + err (_(" * nb_bypass_memory [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_cache_port [nb_load_store_unit] (uint32_t )\n")); + err (_(" * nb_inst_memory [nb_load_store_unit] (uint32_t )\n")); + + err (_(" * nb_functionnal_unit (uint32_t )\n")); + err (_(" * nb_inst_functionnal_unit [nb_functionnal_unit] (uint32_t )\n")); +//err (_(" * timing [nb_functionnal_unit][nb_type][nb_operation] (execute_timing_t )\n")); + + err (_(" * nb_icache_port (uint32_t )\n")); + err (_(" * icache_port_priority (Tpriority_t )\n")); + err (_(" * icache_port_load_balancing (Tload_balancing_t)\n")); + + err (_(" * nb_dcache_port (uint32_t )\n")); + err (_(" * dcache_port_priority (Tpriority_t )\n")); + err (_(" * dcache_port_load_balancing (Tload_balancing_t)\n")); + + err (_(" * nb_front_end (uint32_t )\n")); + err (_(" * nb_context [nb_front_end] (uint32_t )\n")); + err (_(" * nb_decod_unit [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_branch_predict [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_branch_decod [nb_front_end] (uint32_t )\n")); + err (_(" * nb_inst_branch_update [nb_front_end] (uint32_t )\n")); + err (_(" * btb_size_queue [nb_front_end] (uint32_t )\n")); + err (_(" * btb_associativity [nb_front_end] (uint32_t )\n")); + err (_(" * btb_size_counter [nb_front_end] (uint32_t )\n")); + err (_(" * btb_victim_scheme [nb_front_end] (Tvictim_t )\n")); + err (_(" * dir_predictor_scheme [nb_front_end] (Tpredictor_t )\n")); + err (_(" * dir_have_bht [nb_front_end][3] (bool )\n")); + err (_(" * dir_bht_size_shifter [nb_front_end][3] (uint32_t )\n")); + err (_(" * dir_bht_nb_shifter [nb_front_end][3] (uint32_t )\n")); + err (_(" * dir_have_pht [nb_front_end][3] (bool )\n")); + err (_(" * dir_pht_size_counter [nb_front_end][3] (uint32_t )\n")); + err (_(" * dir_pht_nb_counter [nb_front_end][3] (uint32_t )\n")); + err (_(" * dir_pht_size_address_share [nb_front_end][3] (uint32_t )\n")); + + err (_(" * nb_ooo_engine (uint32_t )\n")); + err (_(" * nb_rename_unit [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_issue [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_reexecute [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_commit [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_inst_branch_complete [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_rename_unit_select [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_execute_loop_select [nb_ooo_engine] (uint32_t )\n")); + err (_(" * size_re_order_buffer [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_re_order_buffer_bank [nb_ooo_engine] (uint32_t )\n")); + err (_(" * commit_priority [nb_ooo_engine] (Tpriority_t )\n")); + err (_(" * commit_load_balancing [nb_ooo_engine] (Tload_balancing_t)\n")); + err (_(" * size_issue_queue [nb_ooo_engine] (uint32_t )\n")); + err (_(" * nb_issue_queue_bank [nb_ooo_engine] (uint32_t )\n")); + err (_(" * issue_priority [nb_ooo_engine] (Tpriority_t )\n")); + err (_(" * issue_load_balancing [nb_ooo_engine] (Tload_balancing_t)\n")); + err (_(" * size_reexecute_queue [nb_ooo_engine] (uint32_t )\n")); + err (_(" * reexecute_priority [nb_ooo_engine] (Tpriority_t )\n")); + err (_(" * reexecute_load_balancing [nb_ooo_engine] (Tload_balancing_t)\n")); + + err (_(" * nb_execute_loop (uint32_t )\n")); + err (_(" * nb_read_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_execute_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_write_unit [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_gpr_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_gpr_port_read_by_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_gpr_port_write_by_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_spr_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_spr_port_read_by_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * nb_spr_port_write_by_bank [nb_execute_loop] (uint32_t )\n")); + err (_(" * execution_unit_to_write_unit_priority [nb_execute_loop] (Tpriority_t )\n")); + err (_(" * read_unit_to_execution_unit_priority [nb_execute_loop] (Tpriority_t )\n")); + + err (_(" * link_context_with_thread [nb_thread] (pair_dual )\n")); + err (_(" * link_decod_unit_with_decod_bloc [nb_decod_bloc] (pair_dual )\n")); + err (_(" * link_rename_unit_with_rename_bloc [nb_rename_bloc] (pair_dual )\n")); + err (_(" * link_read_unit_with_read_bloc [nb_read_bloc] (pair_dual )\n")); + err (_(" * link_write_unit_with_write_bloc [nb_write_bloc] (pair_dual )\n")); + err (_(" * link_execute_unit_with_functionnal_unit [nb_functionnal_unit] (pair_dual )\n")); + err (_(" * link_execute_unit_with_load_store_unit [nb_load_store_unit] (pair_dual )\n")); + err (_(" * link_decod_bloc_with_thread [nb_thread] (uint32_t )\n")); + err (_(" * link_rename_bloc_with_front_end [nb_front_end] (uint32_t )\n")); + err (_(" * table_dispatch [nb_ooo_engine][nb_inst_issue][nb_read_bloc] (bool )\n")); + err (_(" * link_read_bloc_and_load_store_unit [nb_read_bloc][nb_load_store_unit] (bool )\n")); + err (_(" * link_read_bloc_and_functionnal_unit [nb_read_bloc][nb_functionnal_unit] (bool )\n")); + err (_(" * link_write_bloc_and_load_store_unit [nb_write_bloc][nb_load_store_unit] (bool )\n")); + err (_(" * link_write_bloc_and_functionnal_unit [nb_write_bloc][nb_functionnal_unit] (bool )\n")); + err (_(" * link_load_store_unit_with_thread [nb_thread] (uint32_t )\n")); + err (_(" * link_thread_and_functionnal_unit [nb_thread][nb_functionnal_unit] (bool )\n")); + err (_(" * link_icache_port_with_thread [nb_thread] (uint32_t )\n")); + err (_(" * link_dcache_port_with_load_store_unit [nb_load_store_unit][nb_cache_port] (uint32_t )\n")); + + err (_(" * dispatch_priority (Tpriority_t )\n")); + err (_(" * dispatch_load_balancing (Tload_balancing_t)\n")); + err (_("\n")); + err (_(" - pair_dual : first = x div 1000, second = x mod 1000\n")); + err (_("\n")); + err (_(" - now they have %d\n"),argc); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc < static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + + // Common + uint32_t _size_general_data ; + uint32_t _size_special_data ; + morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); + + // Thread + uint32_t _nb_thread ; + uint32_t * _size_ifetch_queue ;//[nb_thread] + uint32_t * _nb_inst_fetch ;//[nb_thread] + bool ** _implement_group ;//[nb_thread][NB_GROUP] + uint32_t * _ras_size_queue ;//[nb_thread] + uint32_t * _upt_size_queue ;//[nb_thread] + + // Decod_bloc + uint32_t _nb_decod_bloc ;// + uint32_t * _size_decod_queue ;//[nb_decod_bloc] + uint32_t * _nb_inst_decod ;//[nb_decod_bloc] + uint32_t * _nb_context_select ;//[nb_decod_bloc] + Tpriority_t * _context_select_priority ;//[nb_decod_bloc] + Tload_balancing_t * _context_select_load_balancing ;//[nb_decod_bloc] + + // Rename_bloc + uint32_t _nb_rename_bloc ;// + uint32_t * _nb_inst_insert ;//[nb_rename_bloc] + uint32_t * _nb_inst_retire ;//[nb_rename_bloc] + Tpriority_t * _rename_select_priority ;//[nb_rename_bloc] + Tload_balancing_t * _rename_select_load_balancing ;//[nb_rename_bloc] + uint32_t * _rename_select_nb_front_end_select ;//[nb_rename_bloc] + uint32_t * _nb_general_register ;//[nb_rename_bloc] + uint32_t * _nb_special_register ;//[nb_rename_bloc] + uint32_t * _nb_reg_free ;//[nb_rename_bloc] + uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] + uint32_t * _size_read_counter ;//[nb_rename_bloc] + + // Read bloc + uint32_t _nb_read_bloc ;// + uint32_t * _size_read_queue ;//[nb_read_bloc] + uint32_t * _size_reservation_station ;//[nb_read_bloc] + uint32_t * _nb_inst_retire_reservation_station ;//[nb_read_bloc] + + // Write bloc + uint32_t _nb_write_bloc ;// + uint32_t * _size_write_queue ;//[nb_write_bloc] + uint32_t * _size_execute_queue ;//[nb_write_bloc] + uint32_t * _nb_bypass_write ;//[nb_write_bloc] + + // Load_store_unit + uint32_t _nb_load_store_unit ; + uint32_t * _size_store_queue ;//[nb_load_store_unit] + uint32_t * _size_load_queue ;//[nb_load_store_unit] + uint32_t * _size_speculative_access_queue ;//[nb_load_store_unit] + uint32_t * _nb_port_check ;//[nb_load_store_unit] + multi_execute_loop::execute_loop::Tspeculative_load_t + * _speculative_load ;//[nb_load_store_unit] + uint32_t * _nb_bypass_memory ;//[nb_load_store_unit] + uint32_t * _nb_cache_port ;//[nb_load_store_unit] + uint32_t * _nb_inst_memory ;//[nb_load_store_unit] + + // Functionnal_unit + uint32_t _nb_functionnal_unit ; + uint32_t * _nb_inst_functionnal_unit ;//[nb_functionnal_unit] + multi_execute_loop::execute_loop::execute_timing_t + *** _timing ;//[nb_functionnal_unit][nb_type][nb_operation] + + // Icache_Access + uint32_t _nb_icache_port ; + Tpriority_t _icache_port_priority ; + Tload_balancing_t _icache_port_load_balancing ; + + // Dcache_Access + uint32_t _nb_dcache_port ; + Tpriority_t _dcache_port_priority ; + Tload_balancing_t _dcache_port_load_balancing ; + + // Front_end + uint32_t _nb_front_end ; + uint32_t * _nb_context ;//[nb_front_end] + uint32_t * _nb_decod_unit ;//[nb_front_end] + uint32_t * _nb_inst_branch_predict ;//[nb_front_end] + uint32_t * _nb_inst_branch_decod ;//[nb_front_end] + uint32_t * _nb_inst_branch_update ;//[nb_front_end] + uint32_t * _btb_size_queue ;//[nb_front_end] + uint32_t * _btb_associativity ;//[nb_front_end] + uint32_t * _btb_size_counter ;//[nb_front_end] + Tvictim_t * _btb_victim_scheme ;//[nb_front_end] + Tpredictor_t * _dir_predictor_scheme ;//[nb_front_end] + bool ** _dir_have_bht ;//[nb_front_end][3] + uint32_t ** _dir_bht_size_shifter ;//[nb_front_end][3] + uint32_t ** _dir_bht_nb_shifter ;//[nb_front_end][3] + bool ** _dir_have_pht ;//[nb_front_end][3] + uint32_t ** _dir_pht_size_counter ;//[nb_front_end][3] + uint32_t ** _dir_pht_nb_counter ;//[nb_front_end][3] + uint32_t ** _dir_pht_size_address_share ;//[nb_front_end][3] + + // OOO_Engine + uint32_t _nb_ooo_engine ; + uint32_t * _nb_rename_unit ;//[nb_ooo_engine] + uint32_t * _nb_inst_issue ;//[nb_ooo_engine] + uint32_t * _nb_inst_reexecute ;//[nb_ooo_engine] + uint32_t * _nb_inst_commit ;//[nb_ooo_engine] + uint32_t * _nb_inst_branch_complete ;//[nb_ooo_engine] + uint32_t * _nb_rename_unit_select ;//[nb_ooo_engine] + uint32_t * _nb_execute_loop_select ;//[nb_ooo_engine] + uint32_t * _size_re_order_buffer ;//[nb_ooo_engine] + uint32_t * _nb_re_order_buffer_bank ;//[nb_ooo_engine] + Tpriority_t * _commit_priority ;//[nb_ooo_engine] + Tload_balancing_t * _commit_load_balancing ;//[nb_ooo_engine] + uint32_t * _size_issue_queue ;//[nb_ooo_engine] + uint32_t * _nb_issue_queue_bank ;//[nb_ooo_engine] + Tpriority_t * _issue_priority ;//[nb_ooo_engine] + Tload_balancing_t * _issue_load_balancing ;//[nb_ooo_engine] + uint32_t * _size_reexecute_queue ;//[nb_ooo_engine] + Tpriority_t * _reexecute_priority ;//[nb_ooo_engine] + Tload_balancing_t * _reexecute_load_balancing ;//[nb_ooo_engine] + + // Execute_loop + uint32_t _nb_execute_loop ; + uint32_t * _nb_read_unit ;//[nb_execute_loop] + uint32_t * _nb_execute_unit ;//[nb_execute_loop] + uint32_t * _nb_write_unit ;//[nb_execute_loop] + uint32_t * _nb_gpr_bank ;//[nb_execute_loop] + uint32_t * _nb_gpr_port_read_by_bank ;//[nb_execute_loop] + uint32_t * _nb_gpr_port_write_by_bank ;//[nb_execute_loop] + uint32_t * _nb_spr_bank ;//[nb_execute_loop] + uint32_t * _nb_spr_port_read_by_bank ;//[nb_execute_loop] + uint32_t * _nb_spr_port_write_by_bank ;//[nb_execute_loop] + Tpriority_t * _execution_unit_to_write_unit_priority ;//[nb_execute_loop] + Tpriority_t * _read_unit_to_execution_unit_priority ;//[nb_execute_loop] + + // Link + pair_dual * _link_context_with_thread ;//[nb_thread] + pair_dual * _link_decod_unit_with_decod_bloc ;//[nb_decod_bloc] + pair_dual * _link_rename_unit_with_rename_bloc ;//[nb_rename_bloc] + pair_dual * _link_read_unit_with_read_bloc ;//[nb_read_bloc] + pair_dual * _link_write_unit_with_write_bloc ;//[nb_write_bloc] + pair_dual * _link_execute_unit_with_functionnal_unit ;//[nb_functionnal_unit] + pair_dual * _link_execute_unit_with_load_store_unit ;//[nb_load_store_unit] + uint32_t * _link_decod_bloc_with_thread ;//[nb_thread] + uint32_t * _link_rename_bloc_with_front_end ;//[nb_front_end] + bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + bool ** _link_read_bloc_and_load_store_unit ;//[nb_read_bloc][nb_load_store_unit] + bool ** _link_read_bloc_and_functionnal_unit ;//[nb_read_bloc][nb_functionnal_unit] + bool ** _link_write_bloc_and_load_store_unit ;//[nb_write_bloc][nb_load_store_unit] + bool ** _link_write_bloc_and_functionnal_unit ;//[nb_write_bloc][nb_functionnal_unit] + uint32_t * _link_load_store_unit_with_thread ;//[nb_thread] + bool ** _link_thread_and_functionnal_unit ;//[nb_thread][nb_functionnal_unit] + uint32_t * _link_icache_port_with_thread ;//[nb_thread] + uint32_t ** _link_dcache_port_with_load_store_unit ;//[nb_load_store_unit][nb_cache_port] + + Tpriority_t _dispatch_priority ; + Tload_balancing_t _dispatch_load_balancing ; + + printf("Core parameters :\n"); + + // Common + printf(" * Common\n"); + SELFTEST0(_size_general_data ,uint32_t ,argv,x); + SELFTEST0(_size_special_data ,uint32_t ,argv,x); + _get_custom_information = &(morpheo::behavioural::custom::default_get_custom_information); + + //Thread + printf(" * Thread\n"); + SELFTEST0(_nb_thread ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread)) + usage (argc, argv); + + SELFTEST1(_size_ifetch_queue ,uint32_t ,argv,x,_nb_thread); + SELFTEST1(_nb_inst_fetch ,uint32_t ,argv,x,_nb_thread); + ALLOC2 (_implement_group ,bool ,_nb_thread,NB_GROUP); + for (uint32_t i=0; i<_nb_thread; ++i) + for (uint32_t j=0; j(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc)) + usage (argc, argv); + + SELFTEST1(_size_decod_queue ,uint32_t ,argv,x,_nb_decod_bloc); + SELFTEST1(_nb_inst_decod ,uint32_t ,argv,x,_nb_decod_bloc); + SELFTEST1(_nb_context_select ,uint32_t ,argv,x,_nb_decod_bloc); + SELFTEST1(_context_select_priority ,Tpriority_t ,argv,x,_nb_decod_bloc); + SELFTEST1(_context_select_load_balancing ,Tload_balancing_t ,argv,x,_nb_decod_bloc); + + // Rename bloc + printf(" * Rename bloc\n"); + SELFTEST0(_nb_rename_bloc ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc)) + usage (argc, argv); + + SELFTEST1(_nb_inst_insert ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_nb_inst_retire ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_rename_select_priority ,Tpriority_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_rename_select_load_balancing ,Tload_balancing_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_rename_select_nb_front_end_select ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_nb_general_register ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_nb_special_register ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_nb_reg_free ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_nb_rename_unit_bank ,uint32_t ,argv,x,_nb_rename_bloc); + SELFTEST1(_size_read_counter ,uint32_t ,argv,x,_nb_rename_bloc); + + // Read bloc + printf(" * Read bloc\n"); + SELFTEST0(_nb_read_bloc ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc)) + usage (argc, argv); + + SELFTEST1(_size_read_queue ,uint32_t ,argv,x,_nb_read_bloc); + SELFTEST1(_size_reservation_station ,uint32_t ,argv,x,_nb_read_bloc); + SELFTEST1(_nb_inst_retire_reservation_station ,uint32_t ,argv,x,_nb_read_bloc); + + // Write bloc + printf(" * Write bloc\n"); + SELFTEST0(_nb_write_bloc ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) + usage (argc, argv); + + SELFTEST1(_size_write_queue ,uint32_t ,argv,x,_nb_write_bloc); + SELFTEST1(_size_execute_queue ,uint32_t ,argv,x,_nb_write_bloc); + SELFTEST1(_nb_bypass_write ,uint32_t ,argv,x,_nb_write_bloc); + + // Load store unit + printf(" * Load store unit\n"); + SELFTEST0(_nb_load_store_unit ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) + usage (argc, argv); + + SELFTEST1(_size_store_queue ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_size_load_queue ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_size_speculative_access_queue ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_nb_port_check ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_speculative_load ,multi_execute_loop::execute_loop::Tspeculative_load_t + ,argv,x,_nb_load_store_unit); + SELFTEST1(_nb_bypass_memory ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_nb_cache_port ,uint32_t ,argv,x,_nb_load_store_unit); + SELFTEST1(_nb_inst_memory ,uint32_t ,argv,x,_nb_load_store_unit); + + // Functionnal_unit + printf(" * Functional unit\n"); + SELFTEST0(_nb_functionnal_unit ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) + usage (argc, argv); + + SELFTEST1(_nb_inst_functionnal_unit ,uint32_t ,argv,x,_nb_functionnal_unit); + ALLOC3 (_timing ,multi_execute_loop::execute_loop::execute_timing_t,_nb_functionnal_unit,MAX_TYPE,MAX_OPERATION); + + for (uint32_t i=0; i< _nb_functionnal_unit; i++) + for (uint32_t j=0; j< MAX_TYPE; j++) + if ((j == TYPE_ALU ) | + (j == TYPE_SHIFT ) | + (j == TYPE_MOVE ) | + (j == TYPE_TEST ) | + (j == TYPE_MUL ) | + (j == TYPE_DIV ) | + (j == TYPE_EXTEND ) | + (j == TYPE_FIND ) | + (j == TYPE_SPECIAL) | + (j == TYPE_CUSTOM ) | + (j == TYPE_BRANCH ) // | +// (j == TYPE_MEMORY ) + ) + for (uint32_t k=0; k< MAX_OPERATION; k++) + _timing [i][j][k]._delay = _timing [i][j][k]._latence = 1; + + // Icache_Access + printf(" * Icache access\n"); + + SELFTEST0(_nb_icache_port ,uint32_t ,argv,x); + SELFTEST0(_icache_port_priority ,Tpriority_t ,argv,x); + SELFTEST0(_icache_port_load_balancing ,Tload_balancing_t ,argv,x); + + // Dcache_Access + printf(" * Dcache access\n"); + + SELFTEST0(_nb_dcache_port ,uint32_t ,argv,x); + SELFTEST0(_dcache_port_priority ,Tpriority_t ,argv,x); + SELFTEST0(_dcache_port_load_balancing ,Tload_balancing_t ,argv,x); + + // Front_end + printf(" * Front end\n"); + + SELFTEST0(_nb_front_end ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) + usage (argc, argv); + + SELFTEST1(_nb_context ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_nb_decod_unit ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_nb_inst_branch_predict ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_nb_inst_branch_decod ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_nb_inst_branch_update ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_btb_size_queue ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_btb_associativity ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_btb_size_counter ,uint32_t ,argv,x,_nb_front_end); + SELFTEST1(_btb_victim_scheme ,Tvictim_t ,argv,x,_nb_front_end); + SELFTEST1(_dir_predictor_scheme ,Tpredictor_t ,argv,x,_nb_front_end); + + SELFTEST2(_dir_have_bht ,bool ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_bht_size_shifter ,uint32_t ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_bht_nb_shifter ,uint32_t ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_have_pht ,bool ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_pht_size_counter ,uint32_t ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_pht_nb_counter ,uint32_t ,argv,x,_nb_front_end,3); + SELFTEST2(_dir_pht_size_address_share ,uint32_t ,argv,x,_nb_front_end,3); + + // OOO_Engine + printf(" * OOO Engine\n"); + + SELFTEST0(_nb_ooo_engine ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine)) + usage (argc, argv); + + SELFTEST1(_nb_rename_unit ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_inst_issue ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_inst_reexecute ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_inst_commit ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_inst_branch_complete ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_rename_unit_select ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_execute_loop_select ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_size_re_order_buffer ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_re_order_buffer_bank ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_commit_priority ,Tpriority_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_commit_load_balancing ,Tload_balancing_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_size_issue_queue ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_nb_issue_queue_bank ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_issue_priority ,Tpriority_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_issue_load_balancing ,Tload_balancing_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_size_reexecute_queue ,uint32_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_reexecute_priority ,Tpriority_t ,argv,x,_nb_ooo_engine); + SELFTEST1(_reexecute_load_balancing ,Tload_balancing_t ,argv,x,_nb_ooo_engine); + + //Execute_loop + printf(" * Execute Loop\n"); + + SELFTEST0(_nb_execute_loop ,uint32_t ,argv,x); + + if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) + usage (argc, argv); + + SELFTEST1(_nb_read_unit ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_execute_unit ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_write_unit ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_gpr_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_gpr_port_read_by_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_gpr_port_write_by_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_spr_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_spr_port_read_by_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_nb_spr_port_write_by_bank ,uint32_t ,argv,x,_nb_execute_loop); + SELFTEST1(_execution_unit_to_write_unit_priority ,Tpriority_t ,argv,x,_nb_execute_loop); + SELFTEST1(_read_unit_to_execution_unit_priority ,Tpriority_t ,argv,x,_nb_execute_loop); + + // Link + printf(" * Link\n"); + + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) + usage (argc, argv); + + ALLOC1 (_link_context_with_thread ,pair_dual ,_nb_thread); + ALLOC1 (_link_decod_unit_with_decod_bloc ,pair_dual ,_nb_decod_bloc); + ALLOC1 (_link_rename_unit_with_rename_bloc ,pair_dual ,_nb_rename_bloc); + ALLOC1 (_link_read_unit_with_read_bloc ,pair_dual ,_nb_read_bloc); + ALLOC1 (_link_write_unit_with_write_bloc ,pair_dual ,_nb_write_bloc); + ALLOC1 (_link_execute_unit_with_functionnal_unit ,pair_dual ,_nb_functionnal_unit); + ALLOC1 (_link_execute_unit_with_load_store_unit ,pair_dual ,_nb_load_store_unit); + + for (uint32_t i=0; i<_nb_thread; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_context_with_thread [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_decod_bloc; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_decod_unit_with_decod_bloc [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_rename_bloc; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_rename_unit_with_rename_bloc [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_read_bloc; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_read_unit_with_read_bloc [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_write_bloc; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_write_unit_with_write_bloc [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_execute_unit_with_functionnal_unit [i] = pair_dual(tmp/1000,tmp%1000); + } + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + { + uint32_t tmp=fromString(argv[x++]); + _link_execute_unit_with_load_store_unit [i] = pair_dual(tmp/1000,tmp%1000); + } + + uint32_t _sum_inst_issue = 0; + for (uint32_t i=0; i<_nb_ooo_engine;++i) + _sum_inst_issue += _nb_inst_issue[i]; + uint32_t _sum_cache_port = 0; + for (uint32_t i=0; i<_nb_load_store_unit;++i) + _sum_cache_port += _nb_cache_port[i]; + + if (argc != static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop+ + 3*_nb_thread+_nb_front_end+_sum_inst_issue*_nb_read_bloc+_nb_load_store_unit*(_nb_read_bloc+_nb_write_bloc+_nb_thread)+_nb_functionnal_unit*(_nb_read_bloc+_nb_write_bloc)+_sum_cache_port)) + usage (argc, argv); + + SELFTEST1(_link_decod_bloc_with_thread ,uint32_t ,argv,x,_nb_thread); + SELFTEST1(_link_rename_bloc_with_front_end ,uint32_t ,argv,x,_nb_front_end); + SELFTEST3(_table_dispatch ,bool ,argv,x,_nb_ooo_engine,_nb_inst_issue[it1],_nb_read_bloc); + SELFTEST2(_link_read_bloc_and_load_store_unit ,bool ,argv,x,_nb_read_bloc,_nb_load_store_unit); + SELFTEST2(_link_read_bloc_and_functionnal_unit ,bool ,argv,x,_nb_read_bloc,_nb_functionnal_unit); + SELFTEST2(_link_write_bloc_and_load_store_unit ,bool ,argv,x,_nb_write_bloc,_nb_load_store_unit); + SELFTEST2(_link_write_bloc_and_functionnal_unit ,bool ,argv,x,_nb_write_bloc,_nb_functionnal_unit); + SELFTEST1(_link_load_store_unit_with_thread ,uint32_t ,argv,x,_nb_thread); + SELFTEST2(_link_thread_and_functionnal_unit ,bool ,argv,x,_nb_thread,_nb_functionnal_unit); + SELFTEST1(_link_icache_port_with_thread ,uint32_t ,argv,x,_nb_thread); + SELFTEST2(_link_dcache_port_with_load_store_unit ,uint32_t ,argv,x,_nb_load_store_unit,_nb_cache_port[it1]); + SELFTEST0(_dispatch_priority ,Tpriority_t ,argv,x); + SELFTEST0(_dispatch_load_balancing ,Tload_balancing_t ,argv,x); + + printf(" * End parameters\n"); + printf("--------------------------------\n"); + + int _return = EXIT_SUCCESS; + try + { + morpheo::behavioural::core::Parameters * param = new morpheo::behavioural::core::Parameters + ( + _size_general_data , + _size_special_data , + _get_custom_information , + + _nb_thread , + _size_ifetch_queue , + _nb_inst_fetch , + _implement_group , + _ras_size_queue , + _upt_size_queue , + + _nb_decod_bloc , + _size_decod_queue , + _nb_inst_decod , + _nb_context_select , + _context_select_priority , + _context_select_load_balancing , + + _nb_rename_bloc , + _nb_inst_insert , + _nb_inst_retire , + _rename_select_priority , + _rename_select_load_balancing , + _rename_select_nb_front_end_select , + _nb_general_register , + _nb_special_register , + _nb_reg_free , + _nb_rename_unit_bank , + _size_read_counter , + + _nb_read_bloc , + _size_read_queue , + _size_reservation_station , + _nb_inst_retire_reservation_station , + + _nb_write_bloc , + _size_write_queue , + _size_execute_queue , + _nb_bypass_write , + + _nb_load_store_unit , + _size_store_queue , + _size_load_queue , + _size_speculative_access_queue , + _nb_port_check , + _speculative_load , + _nb_bypass_memory , + _nb_cache_port , + _nb_inst_memory , + + _nb_functionnal_unit , + _nb_inst_functionnal_unit , + _timing , + + _nb_icache_port , + _icache_port_priority , + _icache_port_load_balancing , + + _nb_dcache_port , + _dcache_port_priority , + _dcache_port_load_balancing , + + _nb_front_end , + _nb_context , + _nb_decod_unit , + _nb_inst_branch_predict , + _nb_inst_branch_decod , + _nb_inst_branch_update , + _btb_size_queue , + _btb_associativity , + _btb_size_counter , + _btb_victim_scheme , + _dir_predictor_scheme , + _dir_have_bht , + _dir_bht_size_shifter , + _dir_bht_nb_shifter , + _dir_have_pht , + _dir_pht_size_counter , + _dir_pht_nb_counter , + _dir_pht_size_address_share , + + _nb_ooo_engine , + _nb_rename_unit , + _nb_inst_issue , + _nb_inst_reexecute , + _nb_inst_commit , + _nb_inst_branch_complete , + _nb_rename_unit_select , + _nb_execute_loop_select , + _size_re_order_buffer , + _nb_re_order_buffer_bank , + _commit_priority , + _commit_load_balancing , + _size_issue_queue , + _nb_issue_queue_bank , + _issue_priority , + _issue_load_balancing , + _size_reexecute_queue , + _reexecute_priority , + _reexecute_load_balancing , + + _nb_execute_loop , + _nb_read_unit , + _nb_execute_unit , + _nb_write_unit , + _nb_gpr_bank , + _nb_gpr_port_read_by_bank , + _nb_gpr_port_write_by_bank , + _nb_spr_bank , + _nb_spr_port_read_by_bank , + _nb_spr_port_write_by_bank , + _execution_unit_to_write_unit_priority , + _read_unit_to_execution_unit_priority , + + _link_context_with_thread , + _link_decod_unit_with_decod_bloc , + _link_rename_unit_with_rename_bloc , + _link_read_unit_with_read_bloc , + _link_write_unit_with_write_bloc , + _link_execute_unit_with_functionnal_unit , + _link_execute_unit_with_load_store_unit , + _link_decod_bloc_with_thread , + _link_rename_bloc_with_front_end , + _table_dispatch , + _link_read_bloc_and_load_store_unit , + _link_read_bloc_and_functionnal_unit , + _link_write_bloc_and_load_store_unit , + _link_write_bloc_and_functionnal_unit , + _link_load_store_unit_with_thread , + _link_thread_and_functionnal_unit , + _link_icache_port_with_thread , + _link_dcache_port_with_load_store_unit , + + _dispatch_priority , + _dispatch_load_balancing + ); + + test (name,param); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Core : no error"); + else + TEST_KO("Core : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,210 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "Behavioural/Core/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (string name, + morpheo::behavioural::core::Parameters * _param) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); +#endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Core * _Core = new Core + (name.c_str(), +#ifdef STATISTICS + _parameters_statistics, +#endif + _param, + _usage); + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_address_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_param->_nb_icache_port); + + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_icache_port); + ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_param->_nb_icache_port); + + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,"out_DCACHE_REQ_THREAD_ID ",Tcontext_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tpacket_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_param->_nb_dcache_port); + + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ," in_DCACHE_RSP_THREAD_ID ",Tcontext_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tpacket_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_param->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_param->_nb_dcache_port); + + ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_thread); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Core.\n"),name.c_str()); + + (*(_Core->in_CLOCK)) (*(in_CLOCK)); + (*(_Core->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_REQ_VAL ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Core, in_ICACHE_REQ_ACK ,_param->_nb_icache_port); + if (_param->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port); + if (_param->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_REQ_TYPE ,_param->_nb_icache_port); + + INSTANCE1_SC_SIGNAL(_Core, in_ICACHE_RSP_VAL ,_param->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Core,out_ICACHE_RSP_ACK ,_param->_nb_icache_port); + if (_param->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Core, in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port); + if (_param->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Core, in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port); + INSTANCE2_SC_SIGNAL(_Core, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + INSTANCE1_SC_SIGNAL(_Core, in_ICACHE_RSP_ERROR ,_param->_nb_icache_port); + + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_VAL ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_REQ_ACK ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port); + + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_RSP_VAL ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core,out_DCACHE_RSP_ACK ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port); + if (_param->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Core, in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port); + + INSTANCE1_SC_SIGNAL(_Core, in_INTERRUPT_ENABLE ,_param->_nb_thread); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_icache_port); + + DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_icache_port); + DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + + DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port); + + DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port); + + DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_thread); + } +#endif + + delete _Core; +#ifdef STATISTICS + delete _parameters_statistics; +#endif +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Core.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Core.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Core.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Core} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Core.h (revision 88) @@ -0,0 +1,170 @@ +#ifndef morpheo_behavioural_core_Core_h +#define morpheo_behavioural_core_Core_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h" +#include "Behavioural/Core/Icache_Access/include/Icache_Access.h" +#include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" +#include "Behavioural/Core/Core_Glue/include/Core_Glue.h" + +#include "Behavioural/Core/include/Parameters.h" +#include "Behavioural/include/Types.h" + +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + +#include + +namespace morpheo { +namespace behavioural { +namespace core { + + + class Core +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected : const std::string _name; + protected : const Parameters * _param; + private : const Tusage_t _usage; + +#ifdef STATISTICS + public : Stat * _stat; +#endif + + public : Component * _component; + private : Interfaces * _interfaces; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_REQ_VAL ;//[nb_icache_port] + public : SC_IN (Tcontrol_t ) ** in_ICACHE_REQ_ACK ;//[nb_icache_port] + public : SC_OUT(Tcontext_t ) ** out_ICACHE_REQ_THREAD_ID ;//[nb_icache_port] + public : SC_OUT(Tpacket_t ) ** out_ICACHE_REQ_PACKET_ID ;//[nb_icache_port] + public : SC_OUT(Ticache_address_t ) ** out_ICACHE_REQ_ADDRESS ;//[nb_icache_port] + public : SC_OUT(Ticache_type_t ) ** out_ICACHE_REQ_TYPE ;//[nb_icache_port] + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_ICACHE_RSP_VAL ;//[nb_icache_port] + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_RSP_ACK ;//[nb_icache_port] + public : SC_IN (Tcontext_t ) ** in_ICACHE_RSP_THREAD_ID ;//[nb_icache_port] + public : SC_IN (Tpacket_t ) ** in_ICACHE_RSP_PACKET_ID ;//[nb_icache_port] + public : SC_IN (Ticache_instruction_t) *** in_ICACHE_RSP_INSTRUCTION ;//[nb_icache_port][icache_nb_instruction] + public : SC_IN (Ticache_error_t ) ** in_ICACHE_RSP_ERROR ;//[nb_icache_port] + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_dcache_port] + public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_dcache_port] + public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_THREAD_ID ;//[nb_dcache_port] + public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_dcache_port] + public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_dcache_port] + public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_dcache_port] + public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_dcache_port] + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_dcache_port] + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_dcache_port] + public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_THREAD_ID ;//[nb_dcache_port] + public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_dcache_port] + public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_dcache_port] + public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_dcache_port] + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_INTERRUPT_ENABLE ;//[nb_thread] - Interrupt Exception + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : core::multi_front_end::front_end::Front_end ** _component_front_end; + private : core::multi_ooo_engine::ooo_engine::OOO_Engine ** _component_ooo_engine; + private : core::multi_execute_loop::execute_loop::Execute_loop ** _component_execute_loop; + private : core::icache_access::Icache_Access * _component_icache_access; + private : core::dcache_access::Dcache_Access * _component_dcache_access; + private : core::core_glue::Core_Glue * _component_glue; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Core); +#endif + public : Core + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + Parameters * param, + morpheo::behavioural::Tusage_t usage + ); + public : ~Core (void); + + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + public : void transition (void); +# endif +#endif + +#if VHDL + public : void vhdl (void); +#endif + +#ifdef STATISTICS + public : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + public : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 88) @@ -0,0 +1,507 @@ +#ifndef morpheo_behavioural_core_Parameters_h +#define morpheo_behavioural_core_Parameters_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h" +#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/Parameters.h" +#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Parameters.h" +#include "Behavioural/Core/Icache_Access/include/Parameters.h" +#include "Behavioural/Core/Dcache_Access/include/Parameters.h" +#include "Behavioural/Core/Core_Glue/include/Parameters.h" + +#include "Behavioural/include/Parameters.h" +#include "Common/include/Debug.h" + +#include +#include + +namespace morpheo { +namespace behavioural { + + typedef std::pair pair_dual; + +namespace core { + + + class Parameters : public morpheo::behavioural::Parameters + { + //-----[ fields ]------------------------------------------------------------ + + // Common +//public : uint32_t _size_general_data ; +//public : uint32_t _size_special_data ; + public : morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void); + + // Thread + public : uint32_t _nb_thread ; + public : uint32_t * _size_ifetch_queue ;//[nb_thread] + public : uint32_t * _nb_inst_fetch ;//[nb_thread] + public : bool ** _implement_group ;//[nb_thread][NB_GROUP] + public : uint32_t * _ras_size_queue ;//[nb_thread] + public : uint32_t * _upt_size_queue ;//[nb_thread] + + // Decod bloc + public : uint32_t _nb_decod_bloc ;// + public : uint32_t * _size_decod_queue ;//[nb_decod_bloc] + public : uint32_t * _nb_inst_decod ;//[nb_decod_bloc] + public : uint32_t * _nb_context_select ;//[nb_decod_bloc] + public : Tpriority_t * _context_select_priority ;//[nb_decod_bloc] + public : Tload_balancing_t * _context_select_load_balancing ;//[nb_decod_bloc] + + // Rename bloc + public : uint32_t _nb_rename_bloc ; + public : uint32_t * _nb_inst_insert ;//[nb_rename_bloc] + public : uint32_t * _nb_inst_retire ;//[nb_rename_bloc] + public : Tpriority_t * _rename_select_priority ;//[nb_rename_bloc] + public : Tload_balancing_t * _rename_select_load_balancing ;//[nb_rename_bloc] + public : uint32_t * _rename_select_nb_front_end_select ;//[nb_rename_bloc] + public : uint32_t * _nb_general_register ;//[nb_rename_bloc] + public : uint32_t * _nb_special_register ;//[nb_rename_bloc] + public : uint32_t * _nb_reg_free ;//[nb_rename_bloc] + public : uint32_t * _nb_rename_unit_bank ;//[nb_rename_bloc] + public : uint32_t * _size_read_counter ;//[nb_rename_bloc] + + // Read bloc + public : uint32_t _nb_read_bloc ;// + public : uint32_t * _size_read_queue ;//[nb_read_bloc] + public : uint32_t * _size_reservation_station ;//[nb_read_bloc] + public : uint32_t * _nb_inst_retire_reservation_station ;//[nb_read_bloc] + + // Write bloc + public : uint32_t _nb_write_bloc ;// + public : uint32_t * _size_write_queue ;//[nb_write_bloc] + public : uint32_t * _size_execute_queue ;//[nb_write_bloc] + public : uint32_t * _nb_bypass_write ;//[nb_write_bloc] + + // Load_store_unit + public : uint32_t _nb_load_store_unit ; + public : uint32_t * _size_store_queue ;//[nb_load_store_unit] + public : uint32_t * _size_load_queue ;//[nb_load_store_unit] + public : uint32_t * _size_speculative_access_queue ;//[nb_load_store_unit] + public : uint32_t * _nb_port_check ;//[nb_load_store_unit] + public : multi_execute_loop::execute_loop::Tspeculative_load_t + * _speculative_load ;//[nb_load_store_unit] + public : uint32_t * _nb_bypass_memory ;//[nb_load_store_unit] + public : uint32_t * _nb_cache_port ;//[nb_load_store_unit] + public : uint32_t * _nb_inst_memory ;//[nb_load_store_unit] + + // Functionnal_unit + public : uint32_t _nb_functionnal_unit ; + public : uint32_t * _nb_inst_functionnal_unit ;//[nb_functionnal_unit] + public : multi_execute_loop::execute_loop::execute_timing_t + *** _timing ;//[nb_functionnal_unit][nb_type][nb_operation] + + // Icache_Access + public : uint32_t _nb_icache_port ; + public : Tpriority_t _icache_port_priority ; + public : Tload_balancing_t _icache_port_load_balancing ; + + // Dcache_Access + public : uint32_t _nb_dcache_port ; + public : Tpriority_t _dcache_port_priority ; + public : Tload_balancing_t _dcache_port_load_balancing ; + + // Front_end + public : uint32_t _nb_front_end ; + public : uint32_t * _nb_context ;//[nb_front_end] + public : uint32_t * _nb_decod_unit ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_predict ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_decod ;//[nb_front_end] + public : uint32_t * _nb_inst_branch_update ;//[nb_front_end] + public : uint32_t * _btb_size_queue ;//[nb_front_end] + public : uint32_t * _btb_associativity ;//[nb_front_end] + public : uint32_t * _btb_size_counter ;//[nb_front_end] + public : Tvictim_t * _btb_victim_scheme ;//[nb_front_end] + public : Tpredictor_t * _dir_predictor_scheme ;//[nb_front_end] + public : bool ** _dir_have_bht ;//[nb_front_end][3] + public : uint32_t ** _dir_bht_size_shifter ;//[nb_front_end][3] + public : uint32_t ** _dir_bht_nb_shifter ;//[nb_front_end][3] + public : bool ** _dir_have_pht ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_size_counter ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_nb_counter ;//[nb_front_end][3] + public : uint32_t ** _dir_pht_size_address_share ;//[nb_front_end][3] + + // OOO_Engine + public : uint32_t _nb_ooo_engine ; + public : uint32_t * _nb_rename_unit ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_issue ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_reexecute ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_commit ;//[nb_ooo_engine] + public : uint32_t * _nb_inst_branch_complete ;//[nb_ooo_engine] + public : uint32_t * _nb_rename_unit_select ;//[nb_ooo_engine] + public : uint32_t * _nb_execute_loop_select ;//[nb_ooo_engine] + public : uint32_t * _size_re_order_buffer ;//[nb_ooo_engine] + public : uint32_t * _nb_re_order_buffer_bank ;//[nb_ooo_engine] + public : Tpriority_t * _commit_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _commit_load_balancing ;//[nb_ooo_engine] + public : uint32_t * _size_issue_queue ;//[nb_ooo_engine] + public : uint32_t * _nb_issue_queue_bank ;//[nb_ooo_engine] + public : Tpriority_t * _issue_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _issue_load_balancing ;//[nb_ooo_engine] + public : uint32_t * _size_reexecute_queue ;//[nb_ooo_engine] + public : Tpriority_t * _reexecute_priority ;//[nb_ooo_engine] + public : Tload_balancing_t * _reexecute_load_balancing ;//[nb_ooo_engine] + + //Execute_loop + public : uint32_t _nb_execute_loop ; + public : uint32_t * _nb_read_unit ;//[nb_execute_loop] + public : uint32_t * _nb_execute_unit ;//[nb_execute_loop] + public : uint32_t * _nb_write_unit ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_bank ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_port_read_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_gpr_port_write_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_port_read_by_bank ;//[nb_execute_loop] + public : uint32_t * _nb_spr_port_write_by_bank ;//[nb_execute_loop] + public : Tpriority_t * _execution_unit_to_write_unit_priority ;//[nb_execute_loop] + public : Tpriority_t * _read_unit_to_execution_unit_priority ;//[nb_execute_loop] + + // Link + public : pair_dual * _link_context_with_thread ;//[nb_thread] + public : pair_dual * _link_decod_unit_with_decod_bloc ;//[nb_decod_bloc] + public : pair_dual * _link_rename_unit_with_rename_bloc ;//[nb_rename_bloc] + public : pair_dual * _link_read_unit_with_read_bloc ;//[nb_read_bloc] + public : pair_dual * _link_write_unit_with_write_bloc ;//[nb_write_bloc] + public : pair_dual * _link_execute_unit_with_functionnal_unit ;//[nb_functionnal_unit] + public : pair_dual * _link_execute_unit_with_load_store_unit ;//[nb_load_store_unit] + public : uint32_t * _link_decod_bloc_with_thread ;//[nb_thread] + public : uint32_t * _link_rename_bloc_with_front_end ;//[nb_front_end] + public : bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + public : bool ** _link_read_bloc_and_load_store_unit ;//[nb_read_bloc][nb_load_store_unit] + public : bool ** _link_read_bloc_and_functionnal_unit ;//[nb_read_bloc][nb_functionnal_unit] + public : bool ** _link_write_bloc_and_load_store_unit ;//[nb_write_bloc][nb_load_store_unit] + public : bool ** _link_write_bloc_and_functionnal_unit ;//[nb_write_bloc][nb_functionnal_unit] + public : uint32_t * _link_load_store_unit_with_thread ;//[nb_thread] + public : bool ** _link_thread_and_functionnal_unit ;//[nb_thread][nb_functionnal_unit] + public : uint32_t * _link_icache_port_with_thread ;//[nb_thread] + public : uint32_t ** _link_dcache_port_with_load_store_unit ;//[nb_load_store_unit][nb_cache_port] + + public : Tpriority_t _dispatch_priority ; + public : Tload_balancing_t _dispatch_load_balancing ; + + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + //---------------------------------------------------------------------------- + + // inverse link + public : uint32_t ** _link_thread_with_context ;//[nb_front_end][nb_context] + public : uint32_t ** _link_decod_bloc_with_decod_unit ;//[nb_front_end][nb_decod_unit] + public : uint32_t ** _link_rename_bloc_with_rename_unit ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _link_read_bloc_with_read_unit ;//[nb_execute_loop][nb_read_unit] + public : uint32_t ** _link_write_bloc_with_write_unit ;//[nb_execute_loop][nb_write_unit] + public : uint32_t ** _link_functionnal_unit_with_execute_unit ;//[nb_execute_loop][nb_execute_unit] + public : uint32_t ** _link_load_store_unit_with_execute_unit ;//[nb_execute_loop][nb_execute_unit] +//public : std::vector * _list_thread_with_decod_bloc ;//[nb_decod_bloc] +//public : std::vector * _list_front_end_with_rename_bloc ;//[nb_rename_bloc] + public : std::vector** _list_functionnal_unit_with_rename_unit ;//[nb_ooo_engine][nb_rename_unit]{nb_ooo_engine_nb_functionnal_unit} + public : std::vector** _list_load_store_unit_with_rename_unit ;//[nb_ooo_engine][nb_rename_unit]{nb_ooo_engine_nb_load_store_unit} + public : std::vector * _list_functionnal_unit_with_execute_unit ;//[nb_execute_loop]{execute_loop_nb_functionnal_unit} + public : std::vector * _list_load_store_unit_with_execute_unit ;//[nb_execute_loop]{execute_loop_nb_load_store_unit} + public : std::vector * _list_ooo_engine_with_execute_loop ;//[nb_execute_loop]{execute_loop_nb_ooo_engine} + public : std::vector * _list_front_end_with_execute_loop ;//[nb_execute_loop]{execute_loop_nb_front_end} + + // translate for front_end + public : uint32_t ** _front_end_size_ifetch_queue ;//[nb_front_end][nb_context] + public : uint32_t ** _front_end_nb_inst_fetch ;//[nb_front_end][nb_context] + public : bool *** _front_end_instruction_implemeted ;//[nb_front_end][nb_context][nb_instruction] + public : uint32_t ** _front_end_link_decod_unit_with_context ;//[nb_front_end][nb_context] + public : uint32_t * _front_end_nb_inst_branch_complete ;//[nb_front_end] + public : uint32_t ** _front_end_size_decod_queue ;//[nb_front_end][nb_decod_unit] + public : uint32_t ** _front_end_nb_inst_decod ;//[nb_front_end][nb_decod_unit] + public : uint32_t * _front_end_sum_inst_decod ;//[nb_front_end] + public : uint32_t ** _front_end_nb_context_select ;//[nb_front_end][nb_decod_unit] + public : Tpriority_t ** _front_end_context_select_priority ;//[nb_front_end][nb_decod_unit] + public : Tload_balancing_t ** _front_end_context_select_load_balancing ;//[nb_front_end][nb_decod_unit] + public : uint32_t ** _front_end_ras_size_queue ;//[nb_front_end][nb_context] + public : uint32_t ** _front_end_upt_size_queue ;//[nb_front_end][nb_context] + + // translate for ooo_engine + public : uint32_t * _ooo_engine_nb_front_end ;//[nb_ooo_engine] + public : uint32_t ** _ooo_engine_nb_context ;//[nb_ooo_engine][ooo_engine_nb_front_end] + public : uint32_t * _ooo_engine_nb_execute_loop ;//[nb_ooo_engine] + public : uint32_t ** _ooo_engine_nb_inst_decod ;//[nb_ooo_engine][ooo_engine_nb_front_end] + public : uint32_t ** _ooo_engine_nb_inst_insert ;//[nb_ooo_engine][ooo_engine_nb_rename_unit] + public : uint32_t * _ooo_engine_nb_inst_insert_rob ;//[nb_ooo_engine][ooo_engine_nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_inst_retire ;//[nb_ooo_engine][ooo_engine_nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_inst_execute ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] + public : uint32_t *** _ooo_engine_nb_branch_speculated ;//[nb_ooo_engine][ooo_engine_nb_front_end][ooo_engine_nb_context] + public : uint32_t ** _ooo_engine_link_rename_unit_with_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] + public : Tpriority_t ** _ooo_engine_rename_select_priority ;//[nb_ooo_engine][nb_rename_unit] + public : Tload_balancing_t ** _ooo_engine_rename_select_load_balancing ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_rename_select_nb_front_end_select ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_general_register ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_special_register ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_reg_free ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_nb_rename_unit_bank ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t ** _ooo_engine_size_read_counter ;//[nb_ooo_engine][nb_rename_unit] + public : bool *** _ooo_engine_table_routing ;//[nb_ooo_engine][nb_rename_unit][nb_inst_issue] + public : bool *** _ooo_engine_table_issue_type ;//[nb_ooo_engine][nb_inst_issue][nb_type] + public : uint32_t ** _ooo_engine_nb_load_store_unit ;//[nb_ooo_engine][nb_rename_unit] + public : uint32_t *** _ooo_engine_size_store_queue ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] + public : uint32_t *** _ooo_engine_size_load_queue ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] + public : uint32_t *** _ooo_engine_link_load_store_unit_with_context ;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context] + public : bool **** _ooo_engine_implement_group ;//[nb_ooo_engine][ooo_engine_nb_front_end][nb_context][NB_GROUP] + + // translate for execute_loop + public : uint32_t * _execute_loop_nb_functionnal_unit ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_load_store_unit ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_context ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_front_end ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_ooo_engine ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_thread ;//[nb_execute_loop] + public : uint32_t * _execute_loop_nb_packet ;//[nb_execute_loop] + public : uint32_t ** _execute_loop_size_read_queue ;//[nb_execute_loop][nb_read_unit] + public : uint32_t ** _execute_loop_size_reservation_station ;//[nb_execute_loop][nb_read_unit] + public : uint32_t ** _execute_loop_nb_inst_retire ;//[nb_execute_loop][nb_read_unit] + public : uint32_t ** _execute_loop_nb_inst_functionnal_unit ;//[nb_execute_loop][execute_loop_nb_functionnal_unit] + public : multi_execute_loop::execute_loop::execute_timing_t + **** _execute_loop_timing ;//[nb_execute_loop][nb_execute_unit_nb_functionnal_unit][nb_type][nb_operation] + public : uint32_t ** _execute_loop_size_store_queue ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_size_load_queue ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_size_speculative_access_queue ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_nb_port_check ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : multi_execute_loop::execute_loop::Tspeculative_load_t + ** _execute_loop_speculative_load ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_nb_bypass_memory ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_nb_cache_port ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_nb_inst_memory ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _execute_loop_size_write_queue ;//[nb_execute_loop][nb_write_unit] + public : uint32_t ** _execute_loop_size_execute_queue ;//[nb_execute_loop][nb_write_unit] + public : uint32_t ** _execute_loop_nb_bypass_write ;//[nb_execute_loop][nb_write_unit] + public : uint32_t ** _execute_loop_nb_general_register ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + public : uint32_t ** _execute_loop_nb_special_register ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + public : uint32_t ** _execute_loop_nb_inst_insert_rob ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + public : uint32_t ** _execute_loop_nb_inst_retire_rob ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + public : uint32_t ** _execute_loop_nb_execute_unit_port ;//[nb_execute_loop][nb_execute_unit] + public : bool **** _execute_loop_execution_unit_to_write_unit_table_routing;//[nb_execute_loop][nb_execute_unit][execute_loop_nb_execute_unit_port][nb_write_unit] + public : bool *** _execute_loop_execution_unit_to_write_unit_table_thread ;//[nb_execute_loop][nb_write_unit][execute_loop_nb_thread] + public : bool **** _execute_loop_read_unit_to_execution_unit_table_routing ;//[nb_execute_loop][nb_read_unit][nb_execute_unit][execute_loop_nb_execute_unit_port] + public : bool *** _execute_loop_read_unit_to_execution_unit_table_thread ;//[nb_execute_loop][nb_execute_unit][execute_loop_nb_thread] + public : bool ** _execute_loop_is_load_store_unit ;//[nb_execute_loop][nb_execute_unit] + public : uint32_t ** _execute_loop_translate_num_execute_unit ;//[nb_execute_loop][nb_execute_unit] + + // translate for icache_access + public : uint32_t ** _icache_access_table_routing ;//[nb_front_end][nb_context] + public : uint32_t * _icache_nb_instruction ;//[nb_icache_port] + public : uint32_t ** _icache_access_size_packet_id ;//[nb_front_end][nb_context] + + public : uint32_t _size_icache_thread_id ; + public : uint32_t _size_icache_packet_id ; + public : uint32_t _size_icache_address ; + + public : bool _have_port_icache_thread_id ; + public : bool _have_port_icache_packet_id ; + + // translate for dcache_access + public : uint32_t ** _dcache_access_size_thread_id ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t ** _dcache_access_size_packet_id ;//[nb_execute_loop][execute_loop_nb_load_store_unit] + public : uint32_t *** _dcache_access_table_routing ;//[nb_execute_loop][execute_loop_nb_load_store_unit][execute_loop_nb_cache_port] + public : uint32_t * _dcache_access_nb_context ;//[nb_execute_loop] + public : uint32_t *** _dcache_access_translate_load_store_unit_to_thread;//[nb_execute_loop][execute_loop_nb_load_store_unit][dcache_access_nb_context] + + + public : uint32_t _size_dcache_thread_id ; + public : uint32_t _size_dcache_packet_id ; + public : uint32_t _size_dcache_address ; + public : uint32_t _size_dcache_data ; + + public : bool _have_port_dcache_thread_id ; + public : bool _have_port_dcache_packet_id ; + + + public : bool **** _network_table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit] + + + // Translate + public : uint32_t ** _translate_ooo_engine_num_front_end ;//[nb_ooo_engine][ooo_engine_nb_front_end] + public : uint32_t ** _translate_ooo_engine_num_execute_loop ;//[nb_ooo_engine][ooo_engine_nb_execute_loop] +//public : uint32_t *** _translate_rename_unit_num_load_store_unit ;//[nb_ooo_engine][nb_rename_unit][ooo_engine_nb_load_store_unit] + public : uint32_t ** _translate_execute_loop_num_ooo_engine ;//[nb_execute_loop][execute_loop_nb_ooo_engine] + + public : core::multi_front_end::front_end:: Parameters ** _param_front_end; + public : core::multi_ooo_engine::ooo_engine:: Parameters ** _param_ooo_engine; + public : core::multi_execute_loop::execute_loop::Parameters ** _param_execute_loop; + public : core::icache_access:: Parameters * _param_icache_access; + public : core::dcache_access:: Parameters * _param_dcache_access; + public : core::core_glue:: Parameters * _param_glue; + + //-----[ methods ]----------------------------------------------------------- + public : Parameters ( + // Common + uint32_t size_general_data , + uint32_t size_special_data , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + + // Thread + uint32_t nb_thread , + uint32_t * size_ifetch_queue ,//[nb_thread] + uint32_t * nb_inst_fetch ,//[nb_thread] + bool ** implement_group ,//[nb_thread][NB_GROUP] + uint32_t * ras_size_queue ,//[nb_thread] + uint32_t * upt_size_queue ,//[nb_thread] + + // Decod bloc + uint32_t nb_decod_bloc , + uint32_t * size_decod_queue ,//[nb_decod_bloc] + uint32_t * nb_inst_decod ,//[nb_decod_bloc] + uint32_t * nb_context_select ,//[nb_decod_bloc] + Tpriority_t * context_select_priority ,//[nb_decod_bloc] + Tload_balancing_t * context_select_load_balancing ,//[nb_decod_bloc] + + // Rename bloc + uint32_t nb_rename_bloc , + uint32_t * nb_inst_insert ,//[nb_rename_bloc] + uint32_t * nb_inst_retire ,//[nb_rename_bloc] + Tpriority_t * rename_select_priority ,//[nb_rename_bloc] + Tload_balancing_t * rename_select_load_balancing ,//[nb_rename_bloc] + uint32_t * rename_select_nb_front_end_select ,//[nb_rename_bloc] + uint32_t * nb_general_register ,//[nb_rename_bloc] + uint32_t * nb_special_register ,//[nb_rename_bloc] + uint32_t * nb_reg_free ,//[nb_rename_bloc] + uint32_t * nb_rename_unit_bank ,//[nb_rename_bloc] + uint32_t * size_read_counter ,//[nb_rename_bloc] + + // Read bloc + uint32_t nb_read_bloc ,// + uint32_t * size_read_queue ,//[nb_read_bloc] + uint32_t * size_reservation_station ,//[nb_read_bloc] + uint32_t * nb_inst_retire_reservation_station ,//[nb_read_bloc] + + // Write bloc + uint32_t nb_write_bloc ,// + uint32_t * size_write_queue ,//[nb_write_bloc] + uint32_t * size_execute_queue ,//[nb_write_bloc] + uint32_t * nb_bypass_write ,//[nb_write_bloc] + + // Load_store_unit + uint32_t nb_load_store_unit , + uint32_t * size_store_queue ,//[nb_load_store_unit] + uint32_t * size_load_queue ,//[nb_load_store_unit] + uint32_t * size_speculative_access_queue ,//[nb_load_store_unit] + uint32_t * nb_port_check ,//[nb_load_store_unit] + multi_execute_loop::execute_loop::Tspeculative_load_t + * speculative_load ,//[nb_load_store_unit] + uint32_t * nb_bypass_memory ,//[nb_load_store_unit] + uint32_t * nb_cache_port ,//[nb_load_store_unit] + uint32_t * nb_inst_memory ,//[nb_load_store_unit] + + // Functionnal_unit + uint32_t nb_functionnal_unit , + uint32_t * nb_inst_functionnal_unit ,//[nb_functionnal_unit] + multi_execute_loop::execute_loop::execute_timing_t + *** timing ,//[nb_functionnal_unit][nb_type][nb_operation] + + // Icache_Access + uint32_t nb_icache_port , + Tpriority_t icache_port_priority , + Tload_balancing_t icache_port_load_balancing , + + // Dcache_Access + uint32_t nb_dcache_port , + Tpriority_t dcache_port_priority , + Tload_balancing_t dcache_port_load_balancing , + + // Front_end + uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t * nb_decod_unit ,//[nb_front_end] + uint32_t * nb_inst_branch_predict ,//[nb_front_end] + uint32_t * nb_inst_branch_decod ,//[nb_front_end] + uint32_t * nb_inst_branch_update ,//[nb_front_end] + uint32_t * btb_size_queue ,//[nb_front_end] + uint32_t * btb_associativity ,//[nb_front_end] + uint32_t * btb_size_counter ,//[nb_front_end] + Tvictim_t * btb_victim_scheme ,//[nb_front_end] + Tpredictor_t * dir_predictor_scheme ,//[nb_front_end] + bool ** dir_have_bht ,//[nb_front_end][3] + uint32_t ** dir_bht_size_shifter ,//[nb_front_end][3] + uint32_t ** dir_bht_nb_shifter ,//[nb_front_end][3] + bool ** dir_have_pht ,//[nb_front_end][3] + uint32_t ** dir_pht_size_counter ,//[nb_front_end][3] + uint32_t ** dir_pht_nb_counter ,//[nb_front_end][3] + uint32_t ** dir_pht_size_address_share ,//[nb_front_end][3] + + // OOO_Engine + uint32_t nb_ooo_engine , + uint32_t * nb_rename_unit ,//[nb_ooo_engine] + uint32_t * nb_inst_issue ,//[nb_ooo_engine] + uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] + uint32_t * nb_inst_commit ,//[nb_ooo_engine] + uint32_t * nb_inst_branch_complete ,//[nb_ooo_engine] + uint32_t * nb_rename_unit_select ,//[nb_ooo_engine] + uint32_t * nb_execute_loop_select ,//[nb_ooo_engine] + uint32_t * size_re_order_buffer ,//[nb_ooo_engine] + uint32_t * nb_re_order_buffer_bank ,//[nb_ooo_engine] + Tpriority_t * commit_priority ,//[nb_ooo_engine] + Tload_balancing_t * commit_load_balancing ,//[nb_ooo_engine] + uint32_t * size_issue_queue ,//[nb_ooo_engine] + uint32_t * nb_issue_queue_bank ,//[nb_ooo_engine] + Tpriority_t * issue_priority ,//[nb_ooo_engine] + Tload_balancing_t * issue_load_balancing ,//[nb_ooo_engine] + uint32_t * size_reexecute_queue ,//[nb_ooo_engine] + Tpriority_t * reexecute_priority ,//[nb_ooo_engine] + Tload_balancing_t * reexecute_load_balancing ,//[nb_ooo_engine] + + //Execute_loop + uint32_t nb_execute_loop , + uint32_t * nb_read_unit ,//[nb_execute_loop] + uint32_t * nb_execute_unit ,//[nb_execute_loop] + uint32_t * nb_write_unit ,//[nb_execute_loop] + uint32_t * nb_gpr_bank ,//[nb_execute_loop] + uint32_t * nb_gpr_port_read_by_bank ,//[nb_execute_loop] + uint32_t * nb_gpr_port_write_by_bank ,//[nb_execute_loop] + uint32_t * nb_spr_bank ,//[nb_execute_loop] + uint32_t * nb_spr_port_read_by_bank ,//[nb_execute_loop] + uint32_t * nb_spr_port_write_by_bank ,//[nb_execute_loop] + Tpriority_t * execution_unit_to_write_unit_priority ,//[nb_execute_loop] + Tpriority_t * read_unit_to_execution_unit_priority ,//[nb_execute_loop] + + // Link + pair_dual * link_context_with_thread ,//[nb_thread] + pair_dual * link_decod_unit_with_decod_bloc ,//[nb_decod_bloc] + pair_dual * link_rename_unit_with_rename_bloc ,//[nb_rename_bloc] + pair_dual * link_read_unit_with_read_bloc ,//[nb_read_bloc] + pair_dual * link_write_unit_with_write_bloc ,//[nb_write_bloc] + pair_dual * link_execute_unit_with_functionnal_unit ,//[nb_functionnal_unit] + pair_dual * link_execute_unit_with_load_store_unit ,//[nb_load_store_unit] + uint32_t * link_decod_bloc_with_thread ,//[nb_thread] + uint32_t * link_rename_bloc_with_front_end ,//[nb_front_end] + bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + bool ** link_read_bloc_and_load_store_unit ,//[nb_read_bloc][nb_load_store_unit] + bool ** link_read_bloc_and_functionnal_unit ,//[nb_read_bloc][nb_functionnal_unit] + bool ** link_write_bloc_and_load_store_unit ,//[nb_write_bloc][nb_load_store_unit] + bool ** link_write_bloc_and_functionnal_unit ,//[nb_write_bloc][nb_functionnal_unit] + uint32_t * link_load_store_unit_with_thread ,//[nb_thread] + bool ** link_thread_and_functionnal_unit ,//[nb_thread][nb_functionnal_unit] + uint32_t * link_icache_port_with_thread ,//[nb_thread] + uint32_t ** link_dcache_port_with_load_store_unit ,//[nb_load_store_unit][nb_cache_port] + + Tpriority_t dispatch_priority , + Tload_balancing_t dispatch_load_balancing + ); +// public : Parameters (Parameters & param) ; + public : ~Parameters () ; + + public : void copy (void); + + public : Parameters_test msg_error (void); + + private: Tcontext_t execute_loop_get_num_thread (uint32_t num_execute_loop, + uint32_t num_thread); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::core::Parameters & x); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core.cpp (revision 88) @@ -0,0 +1,109 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::Core" + Core::Core + ( +#ifdef SYSTEMC + sc_module_name name, +#else + string name, +#endif +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics, +#endif + morpheo::behavioural::core::Parameters * param, + morpheo::behavioural::Tusage_t usage + ): + _name (name) + ,_param (param) + ,_usage (usage) + { + log_begin(Core,FUNCTION); + + usage_environment(_usage); + +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + + log_printf(INFO,Core,FUNCTION,_("<%s> Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Core,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str()); + + statistics_allocation(param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Core,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Core,FUNCTION,_("<%s> Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + } +#endif + log_end(Core,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Core::~Core" + Core::~Core (void) + { + log_begin(Core,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Core,FUNCTION,_("<%s> Deallocation"),_name.c_str()); + deallocation (); + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 88) @@ -0,0 +1,1394 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + + +#undef FUNCTION +#define FUNCTION "Core::allocation" + void Core::allocation + ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Core,FUNCTION); + + _component = new Component (_usage); + + Entity * entity = _component->set_entity (_name + ,"Core" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_param->_nb_icache_port); + + ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_icache_thread_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_icache_packet_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_param->_size_icache_address ); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port); + + ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_icache_thread_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_icache_packet_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); + } + { + ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + + _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_param->_size_instruction,_param->_nb_icache_port,_param->_icache_nb_instruction[it1]); + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_param->_nb_dcache_port); + + ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); + ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_dcache_thread_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_dcache_packet_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_param->_size_dcache_address); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_dcache_data); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type); + } + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_param->_nb_dcache_port); + + ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); + ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tcontext_t ,_param->_size_dcache_thread_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tpacket_t ,_param->_size_dcache_packet_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_dcache_data); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_param->_size_dcache_error); + } + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_param->_nb_thread); + + ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + std::string name; + + _component_front_end = new core::multi_front_end::front_end::Front_end * [_param->_nb_front_end]; + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + { + name = _name+"_front_end_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_front_end [i] = new core::multi_front_end::front_end::Front_end + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_front_end [i] + ,_usage); + + _component->set_component (_component_front_end[i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + _component_ooo_engine = new core::multi_ooo_engine::ooo_engine::OOO_Engine * [_param->_nb_ooo_engine]; + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + name = _name+"_ooo_engine_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_ooo_engine [i] = new core::multi_ooo_engine::ooo_engine::OOO_Engine + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_ooo_engine [i] + ,_usage); + + _component->set_component (_component_ooo_engine[i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + _component_execute_loop = new core::multi_execute_loop::execute_loop::Execute_loop * [_param->_nb_execute_loop]; + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + { + name = _name+"_execute_loop_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_execute_loop [i] = new core::multi_execute_loop::execute_loop::Execute_loop + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_execute_loop [i] + ,_usage); + + _component->set_component (_component_execute_loop[i]->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_icache_access"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_icache_access = new morpheo::behavioural::core::icache_access::Icache_Access + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_icache_access + ,_usage); + + _component->set_component (_component_icache_access->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + { + name = _name+"_dcache_access"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_dcache_access = new morpheo::behavioural::core::dcache_access::Dcache_Access + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_dcache_access + ,_usage); + + _component->set_component (_component_dcache_access->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + + { + name = _name+"_glue"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_glue = new morpheo::behavioural::core::core_glue::Core_Glue + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param->_param_glue + ,_usage); + + _component->set_component (_component_glue->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string src,dest; + + + // =================================================================== + // =====[ front_end ]================================================= + // =================================================================== + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + { + src = _name+"_front_end_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_ICACHE_REQ_VAL - icache_access. in_CONTEXT_REQ_VAL + // in_ICACHE_REQ_ACK - icache_access.out_CONTEXT_REQ_ACK +// // out_ICACHE_REQ_THREAD_ID - icache_access. in_CONTEXT_REQ_THREAD_ID + // out_ICACHE_REQ_PACKET_ID - icache_access. in_CONTEXT_REQ_PACKET_ID + // out_ICACHE_REQ_ADDRESS - icache_access. in_CONTEXT_REQ_ADDRESS + // out_ICACHE_REQ_TYPE - icache_access. in_CONTEXT_REQ_TYPE + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_ICACHE_RSP_VAL - icache_access.out_CONTEXT_RSP_VAL + // out_ICACHE_RSP_ACK - icache_access. in_CONTEXT_RSP_ACK +// // in_ICACHE_RSP_THREAD_ID - icache_access.out_CONTEXT_RSP_THREAD_ID + // in_ICACHE_RSP_PACKET_ID - icache_access.out_CONTEXT_RSP_PACKET_ID + // in_ICACHE_RSP_INSTRUCTION - icache_access.out_CONTEXT_RSP_INSTRUCTION + // in_ICACHE_RSP_ERROR - icache_access.out_CONTEXT_RSP_ERROR + + // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_DECOD_VAL - ooo_engine. in_RENAME_VAL + // in_DECOD_ACK - ooo_engine.out_RENAME_ACK + // out_DECOD_CONTEXT_ID - ooo_engine. in_RENAME_CONTEXT_ID + // out_DECOD_DEPTH - ooo_engine. in_RENAME_DEPTH + // out_DECOD_TYPE - ooo_engine. in_RENAME_TYPE + // out_DECOD_OPERATION - ooo_engine. in_RENAME_OPERATION + // out_DECOD_NO_EXECUTE - ooo_engine. in_RENAME_NO_EXECUTE + // out_DECOD_IS_DELAY_SLOT - ooo_engine. in_RENAME_IS_DELAY_SLOT + // out_DECOD_ADDRESS - ooo_engine. in_RENAME_ADDRESS + // out_DECOD_HAS_IMMEDIAT - ooo_engine. in_RENAME_HAS_IMMEDIAT + // out_DECOD_IMMEDIAT - ooo_engine. in_RENAME_IMMEDIAT + // out_DECOD_READ_RA - ooo_engine. in_RENAME_READ_RA + // out_DECOD_NUM_REG_RA - ooo_engine. in_RENAME_NUM_REG_RA + // out_DECOD_READ_RB - ooo_engine. in_RENAME_READ_RB + // out_DECOD_NUM_REG_RB - ooo_engine. in_RENAME_NUM_REG_RB + // out_DECOD_READ_RC - ooo_engine. in_RENAME_READ_RC + // out_DECOD_NUM_REG_RC - ooo_engine. in_RENAME_NUM_REG_RC + // out_DECOD_WRITE_RD - ooo_engine. in_RENAME_WRITE_RD + // out_DECOD_NUM_REG_RD - ooo_engine. in_RENAME_NUM_REG_RD + // out_DECOD_WRITE_RE - ooo_engine. in_RENAME_WRITE_RE + // out_DECOD_NUM_REG_RE - ooo_engine. in_RENAME_NUM_REG_RE + // out_DECOD_EXCEPTION_USE - ooo_engine. in_RENAME_EXCEPTION_USE + // out_DECOD_EXCEPTION - ooo_engine. in_RENAME_EXCEPTION + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_front_end_nb_inst_branch_complete[i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_" +toString(j), + dest,"branch_complete_front_end_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_VAL" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_ACK" , + dest, "in_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_CONTEXT_ID" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_DEPTH" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_DEPTH" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_ADDRESS" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_FLAG" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_FLAG" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_MISS_PREDICTION", + dest, "in_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_MISS_PREDICTION"); + } + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"commit_event" , + dest,"commit_event_front_end_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_VAL" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ACK" , + dest, "in_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_CONTEXT_ID" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_DEPTH" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_DEPTH" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_TYPE" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_IS_DELAY_SLOT" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_IS_DELAY_SLOT" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EPCR" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS_EPCR" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EEAR_VAL", + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS_EEAR_VAL"); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ADDRESS_EEAR" , + dest,"out_COMMIT_EVENT_FRONT_END_"+toString(i)+"_ADDRESS_EEAR" ); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_EVENT_VAL - ooo_engine. in_EVENT_VAL + // in_EVENT_ACK - ooo_engine.out_EVENT_ACK + // out_EVENT_ADDRESS - ooo_engine. in_EVENT_ADDRESS + // out_EVENT_ADDRESS_NEXT - ooo_engine. in_EVENT_ADDRESS_NEXT + // out_EVENT_ADDRESS_NEXT_VAL - ooo_engine. in_EVENT_ADDRESS_NEXT_VAL + // out_EVENT_IS_DS_TAKE - ooo_engine. in_EVENT_IS_DS_TAKE + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //out_SPR_EVENT_VAL - ooo_engine. in_SPR_EVENT_VAL + // in_SPR_EVENT_ACK - ooo_engine.out_SPR_EVENT_ACK + //out_SPR_EVENT_EPCR - ooo_engine. in_SPR_EVENT_EPCR + //out_SPR_EVENT_EEAR_WEN - ooo_engine. in_SPR_EVENT_EEAR_WEN + //out_SPR_EVENT_EEAR - ooo_engine. in_SPR_EVENT_EEAR + //out_SPR_EVENT_SR_DSX - ooo_engine. in_SPR_EVENT_SR_DSX + //out_SPR_EVENT_SR_TO_ESR - ooo_engine. in_SPR_EVENT_SR_TO_ESR + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_NB_INST_COMMIT_ALL - ooo_engine.out_NB_INST_COMMIT_ALL + // in_NB_INST_COMMIT_MEM - ooo_engine.out_NB_INST_COMMIT_MEM + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_DEPTH_MIN - ooo_engine. in_DEPTH_MIN + // out_DEPTH_MAX - ooo_engine. in_DEPTH_MAX + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_SPR_SR_IEE - ooo_engine.out_SPR_SR_IEE + // in_SPR_SR_EPH - ooo_engine.out_SPR_SR_EPH + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_context [i]; ++j) + { + uint32_t x = _param->_link_thread_with_context [i][j]; + + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"interrupt_"+toString(j), + dest,"interrupt_"+toString(x)); +#endif + + PORT_MAP(_component,src , "in_INTERRUPT_"+toString(j)+"_ENABLE", + dest, "in_INTERRUPT_"+toString(x)+"_ENABLE"); + } + } + + // =================================================================== + // =====[ ooo_engine ]================================================ + // =================================================================== + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + { + src = _name+"_ooo_engine_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + for (uint32_t k=0; k<_param->_ooo_engine_nb_inst_decod[i][j]; ++k) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(j)+"_"+toString(k), + dest,"decod_" +toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_DECOD_" +toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_RENAME_"+toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_DECOD_" +toString(k)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_CONTEXT_ID" , + dest,"out_DECOD_" +toString(k)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_DEPTH" , + dest,"out_DECOD_" +toString(k)+"_DEPTH" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_TYPE" , + dest,"out_DECOD_" +toString(k)+"_TYPE" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_OPERATION" , + dest,"out_DECOD_" +toString(k)+"_OPERATION" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NO_EXECUTE" , + dest,"out_DECOD_" +toString(k)+"_NO_EXECUTE" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_IS_DELAY_SLOT", + dest,"out_DECOD_" +toString(k)+"_IS_DELAY_SLOT"); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_ADDRESS" , + dest,"out_DECOD_" +toString(k)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_HAS_IMMEDIAT" , + dest,"out_DECOD_" +toString(k)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_IMMEDIAT" , + dest,"out_DECOD_" +toString(k)+"_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_READ_RA" , + dest,"out_DECOD_" +toString(k)+"_READ_RA" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NUM_REG_RA" , + dest,"out_DECOD_" +toString(k)+"_NUM_REG_RA" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_READ_RB" , + dest,"out_DECOD_" +toString(k)+"_READ_RB" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NUM_REG_RB" , + dest,"out_DECOD_" +toString(k)+"_NUM_REG_RB" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_READ_RC" , + dest,"out_DECOD_" +toString(k)+"_READ_RC" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NUM_REG_RC" , + dest,"out_DECOD_" +toString(k)+"_NUM_REG_RC" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_WRITE_RD" , + dest,"out_DECOD_" +toString(k)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NUM_REG_RD" , + dest,"out_DECOD_" +toString(k)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_WRITE_RE" , + dest,"out_DECOD_" +toString(k)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_NUM_REG_RE" , + dest,"out_DECOD_" +toString(k)+"_NUM_REG_RE" ); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_EXCEPTION_USE", + dest,"out_DECOD_" +toString(k)+"_EXCEPTION_USE"); + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_EXCEPTION" , + dest,"out_DECOD_" +toString(k)+"_EXCEPTION" ); + + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"rename_"+toString(j)+"_"+toString(k), + dest,"rename_"+toString(j)+"_"+toString(k)); +#endif + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_RENAME_"+toString(j)+"_"+toString(k)+"_FRONT_END_ID" , + dest,"out_RENAME_"+toString(j)+"_"+toString(k)+"_FRONT_END_ID" ); + } + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_inst_branch_complete[i];++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"branch_complete_" +toString(j), + dest,"branch_complete_ooo_engine_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_VAL" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_ACK" , + dest,"out_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_FRONT_END_ID" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_CONTEXT_ID" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_DEPTH" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_DEPTH" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_ADDRESS" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_FLAG" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_FLAG" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_MISS_PREDICTION", + dest,"out_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_MISS_PREDICTION"); + } + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"commit_event", + dest,"commit_event_ooo_engine_"+toString(i)); +#endif + + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_VAL" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_COMMIT_EVENT_ACK" , + dest,"out_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_FRONT_END_ID" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_CONTEXT_ID" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_CONTEXT_ID" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_DEPTH" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_DEPTH" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_TYPE" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_TYPE" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_IS_DELAY_SLOT" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_IS_DELAY_SLOT" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS_EPCR" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS_EPCR" ); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL", + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS_EEAR_VAL"); + COMPONENT_MAP(_component,src ,"out_COMMIT_EVENT_ADDRESS_EEAR" , + dest, "in_COMMIT_EVENT_OOO_ENGINE_"+toString(i)+"_ADDRESS_EEAR" ); + } + + // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + for (uint32_t k=0; k<_param->_nb_context[x]; ++k) + { + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(j)+"_"+toString(k), + dest,"event_" +toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_EVENT_" +toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_EVENT_" +toString(k)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(j)+"_"+toString(k)+"_ADDRESS" , + dest,"out_EVENT_" +toString(k)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(j)+"_"+toString(k)+"_ADDRESS_NEXT" , + dest,"out_EVENT_" +toString(k)+"_ADDRESS_NEXT" ); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(j)+"_"+toString(k)+"_ADDRESS_NEXT_VAL", + dest,"out_EVENT_" +toString(k)+"_ADDRESS_NEXT_VAL"); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(j)+"_"+toString(k)+"_IS_DS_TAKE" , + dest,"out_EVENT_" +toString(k)+"_IS_DS_TAKE" ); + } + } + + // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + for (uint32_t k=0; k<_param->_nb_context[x]; ++k) + { + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"spr_event_"+toString(j)+"_"+toString(k), + dest,"spr_event_" +toString(k)); +#endif + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_SPR_EVENT_" +toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_SPR_EVENT_" +toString(k)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_EPCR" , + dest,"out_SPR_EVENT_" +toString(k)+"_EPCR" ); + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_EEAR_WEN" , + dest,"out_SPR_EVENT_" +toString(k)+"_EEAR_WEN" ); + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_EEAR" , + dest,"out_SPR_EVENT_" +toString(k)+"_EEAR" ); + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_SR_DSX" , + dest,"out_SPR_EVENT_" +toString(k)+"_SR_DSX" ); + COMPONENT_MAP(_component,src , "in_SPR_EVENT_"+toString(j)+"_"+toString(k)+"_SR_TO_ESR", + dest,"out_SPR_EVENT_" +toString(k)+"_SR_TO_ESR"); + } + } + + // ~~~~~[ Interface : "nb_inst" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + for (uint32_t k=0; k<_param->_nb_context[x]; ++k) + { + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"nb_inst_"+toString(j)+"_"+toString(k), + dest,"nb_inst_" +toString(k)); +#endif + COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_"+toString(k)+"_COMMIT_ALL", + dest, "in_NB_INST_" +toString(k)+"_COMMIT_ALL"); + COMPONENT_MAP(_component,src ,"out_NB_INST_"+toString(j)+"_"+toString(k)+"_COMMIT_MEM", + dest, "in_NB_INST_" +toString(k)+"_COMMIT_MEM"); + } + } + + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + for (uint32_t k=0; k<_param->_nb_context[x]; ++k) + { + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"depth_"+toString(j)+"_"+toString(k), + dest,"depth_" +toString(k)); +#endif + + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MIN", + dest,"out_DEPTH_" +toString(k)+"_MIN"); + COMPONENT_MAP(_component,src , "in_DEPTH_"+toString(j)+"_"+toString(k)+"_MAX", + dest,"out_DEPTH_" +toString(k)+"_MAX"); + } + } + + // ~~~~~[ Interface : "spr" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_front_end [i]; ++j) + { + uint32_t x = _param->_translate_ooo_engine_num_front_end [i][j]; + for (uint32_t k=0; k<_param->_nb_context[x]; ++k) + { + dest = _name+"_front_end_"+toString(x); +#ifdef POSITION + _component->interface_map (src ,"spr_"+toString(j)+"_"+toString(k), + dest,"spr_" +toString(k)); +#endif + + COMPONENT_MAP(_component,src ,"out_SPR_"+toString(j)+"_"+toString(k)+"_SR_IEE", + dest, "in_SPR_" +toString(k)+"_SR_IEE"); + COMPONENT_MAP(_component,src ,"out_SPR_"+toString(j)+"_"+toString(k)+"_SR_EPH", + dest, "in_SPR_" +toString(k)+"_SR_EPH"); + } + } + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_inst_issue [i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"issue_" +toString(j), + dest,"issue_ooo_engine_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_VAL" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_ISSUE_" +toString(j)+"_ACK" , + dest,"out_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_FRONT_END_ID" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_CONTEXT_ID" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_PACKET_ID" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_TYPE" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_OPERATION" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_STORE_QUEUE_PTR_WRITE", + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_LOAD_QUEUE_PTR_WRITE" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_HAS_IMMEDIAT" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_IMMEDIAT" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_IMMEDIAT" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_READ_RA" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_READ_RA" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_NUM_REG_RA" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_READ_RB" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_READ_RB" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_NUM_REG_RB" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_READ_RC" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_READ_RC" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_NUM_REG_RC" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_WRITE_RD" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_NUM_REG_RD" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_WRITE_RE" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src ,"out_ISSUE_" +toString(j)+"_NUM_REG_RE" , + dest, "in_ISSUE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" ); + } + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_execute_loop [i]; ++j) + { + for (uint32_t k=0; k<_param->_ooo_engine_nb_inst_execute [i][j]; ++k) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"execute_loop_" +toString(j)+"_"+toString(k), + dest,"execute_ooo_engine_"+toString(i)+"_"+toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_FRONT_END_ID", + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_FRONT_END_ID"); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_CONTEXT_ID" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_CONTEXT_ID" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_PACKET_ID" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_PACKET_ID" ); +// COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_TYPE" , +// dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_TYPE" ); +// COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_OPERATION" , +// dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_OPERATION" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_FLAGS" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_FLAGS" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_EXCEPTION" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_EXCEPTION" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_NO_SEQUENCE" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_NO_SEQUENCE" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_ADDRESS" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_" +toString(j)+"_"+toString(k)+"_DATA" , + dest,"out_EXECUTE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_DATA" ); + } + } + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_ooo_engine_nb_inst_insert_rob [i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"insert_" +toString(j), + dest,"insert_ooo_engine_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(j)+"_VAL" , + dest, "in_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_INSERT_" +toString(j)+"_ACK" , + dest,"out_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_ACK" ); + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(j)+"_RD_USE" , + dest, "in_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_RD_USE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(j)+"_RD_NUM_REG", + dest, "in_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_RD_NUM_REG"); + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(j)+"_RE_USE" , + dest, "in_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_RE_USE" ); + COMPONENT_MAP(_component,src ,"out_INSERT_" +toString(j)+"_RE_NUM_REG", + dest, "in_INSERT_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_RE_NUM_REG"); + } + } + + // =================================================================== + // =====[ execute_loop ]============================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + { + src = _name+"_execute_loop_"+toString(i); + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "execute_loop_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_read_unit[i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"execute_loop_in_" +toString(j), + dest,"issue_execute_loop_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_VAL" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_IN_" +toString(j)+"_ACK" , + dest, "in_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_FRONT_END_ID" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_CONTEXT_ID" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_OOO_ENGINE_ID" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OOO_ENGINE_ID" ); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_PACKET_ID" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_OPERATION" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OPERATION" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_TYPE" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_STORE_QUEUE_PTR_WRITE", + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_STORE_QUEUE_PTR_WRITE"); + if (_param->_have_port_load_queue_ptr) + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_LOAD_QUEUE_PTR_WRITE" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_LOAD_QUEUE_PTR_WRITE" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_HAS_IMMEDIAT" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_HAS_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_IMMEDIAT" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_IMMEDIAT" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_READ_RA" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_READ_RA" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_NUM_REG_RA" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NUM_REG_RA" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_READ_RB" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_READ_RB" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_NUM_REG_RB" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NUM_REG_RB" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_READ_RC" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_READ_RC" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_NUM_REG_RC" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NUM_REG_RC" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_WRITE_RD" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_NUM_REG_RD" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NUM_REG_RD" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_WRITE_RE" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_WRITE_RE" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_IN_" +toString(j)+"_NUM_REG_RE" , + dest,"out_ISSUE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NUM_REG_RE" ); + } + + // ~~~~~[ Interface "execute_loop_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_nb_write_unit[i]; ++j) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"execute_loop_out_" +toString(j), + dest,"execute_execute_loop_"+toString(i)+"_"+toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_VAL" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_EXECUTE_LOOP_OUT_" +toString(j)+"_ACK" , + dest,"out_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ACK" ); + if (_param->_have_port_context_id) + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_CONTEXT_ID" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_CONTEXT_ID" ); + if (_param->_have_port_front_end_id) + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_FRONT_END_ID" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FRONT_END_ID" ); + if (_param->_have_port_ooo_engine_id) + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_OOO_ENGINE_ID", + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OOO_ENGINE_ID"); + if (_param->_have_port_rob_ptr) + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_PACKET_ID" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_PACKET_ID" ); +// COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_OPERATION" , +// dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_OPERATION" ); +// COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_TYPE" , +// dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_TYPE" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_FLAGS" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_FLAGS" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_EXCEPTION" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_EXCEPTION" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_NO_SEQUENCE" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_ADDRESS" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); + COMPONENT_MAP(_component,src ,"out_EXECUTE_LOOP_OUT_" +toString(j)+"_DATA" , + dest, "in_EXECUTE_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_DATA" ); + } + + // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t j=0; j<_param->_execute_loop_nb_ooo_engine[i]; ++j) + for (uint32_t k=0; k<_param->_execute_loop_nb_inst_insert_rob[i][j]; ++k) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"insert_rob_" +toString(j)+"_"+toString(k), + dest,"insert_execute_loop_"+toString(i)+"_"+toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_ACK" ); + COMPONENT_MAP(_component,src , "in_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_RD_USE" , + dest,"out_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_RD_USE" ); + COMPONENT_MAP(_component,src , "in_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_RD_NUM_REG", + dest,"out_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_RD_NUM_REG"); + COMPONENT_MAP(_component,src , "in_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_RE_USE" , + dest,"out_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_RE_USE" ); + COMPONENT_MAP(_component,src , "in_INSERT_ROB_" +toString(j)+"_"+toString(k)+"_RE_NUM_REG", + dest,"out_INSERT_EXECUTE_LOOP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_RE_NUM_REG"); + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_DCACHE_REQ_VAL - dcache_access. in_LSQ_REQ_VAL + // in_DCACHE_REQ_ACK - dcache_access.out_LSQ_REQ_ACK + // out_DCACHE_REQ_CONTEXT_ID - dcache_access. in_LSQ_REQ_CONTEXT_ID + // out_DCACHE_REQ_PACKET_ID - dcache_access. in_LSQ_REQ_PACKET_ID + // out_DCACHE_REQ_ADDRESS - dcache_access. in_LSQ_REQ_ADDRESS + // out_DCACHE_REQ_TYPE - dcache_access. in_LSQ_REQ_TYPE + // out_DCACHE_REQ_WDATA - dcache_access. in_LSQ_REQ_WDATA + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_DCACHE_RSP_VAL - dcache_access.out_LSQ_RSP_VAL + // out_DCACHE_RSP_ACK - dcache_access. in_LSQ_RSP_ACK + // in_DCACHE_RSP_CONTEXT_ID - dcache_access.out_LSQ_RSP_CONTEXT_ID + // in_DCACHE_RSP_PACKET_ID - dcache_access.out_LSQ_RSP_PACKET_ID + // in_DCACHE_RSP_RDATA - dcache_access.out_LSQ_RSP_RDATA + // in_DCACHE_RSP_ERROR - dcache_access.out_LSQ_RSP_ERROR + } + + // =================================================================== + // =====[ icache_access ]============================================= + // =================================================================== + { + src = _name+"_icache_access"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_req_"+toString(i), + dest,"icache_req_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" , + dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" , + dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" ); + if (_param->_have_port_icache_thread_id) + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID", + dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID"); + if (_param->_have_port_icache_packet_id) + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID", + dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" , + dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" , + dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_icache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_rsp_"+toString(i), + dest,"icache_rsp_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" , + dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" , + dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" ); + if (_param->_have_port_icache_thread_id) + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID" , + dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID" ); + if (_param->_have_port_icache_packet_id) + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID" , + dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID" ); + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" , + dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" ); + + for (uint32_t j=0; j<_param->_icache_nb_instruction[i];++j) + { +#ifdef POSITION + _component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j), + dest,"icache_rsp_"+toString(i)+"_"+toString(j)); +#endif + + + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION", + dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION"); + } + } + + // ~~~~~[ Interface "context_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + dest = _name+"_front_end_"+toString(i); +#ifdef POSITION + _component->interface_map (src ,"context_req_"+toString(i)+"_"+toString(j), + dest,"icache_req_" +toString(j)); +#endif + + COMPONENT_MAP(_component,src , "in_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_VAL" , + dest,"out_ICACHE_REQ_" +toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_ACK" , + dest, "in_ICACHE_REQ_" +toString(j)+"_ACK" ); +// COMPONENT_MAP(_component,src , "in_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_THREAD_ID", +// dest,"out_ICACHE_REQ_" +toString(j)+"_THREAD_ID"); + if (_param->_have_port_icache_packet_id) + COMPONENT_MAP(_component,src , "in_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_PACKET_ID", + dest,"out_ICACHE_REQ_" +toString(j)+"_PACKET_ID"); + COMPONENT_MAP(_component,src , "in_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_ADDRESS" , + dest,"out_ICACHE_REQ_" +toString(j)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_CONTEXT_REQ_"+toString(i)+"_"+toString(j)+"_TYPE" , + dest,"out_ICACHE_REQ_" +toString(j)+"_TYPE" ); + } + + // ~~~~~[ Interface "context_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + for (uint32_t j=0; j<_param->_nb_context[i]; ++j) + { + dest = _name+"_front_end_"+toString(i); +#ifdef POSITION + _component->interface_map (src ,"context_rsp_"+toString(i)+"_"+toString(j), + dest,"icache_rsp_" +toString(j)); +#endif + + COMPONENT_MAP(_component,src ,"out_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_VAL" , + dest, "in_ICACHE_RSP_" +toString(j)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_ACK" , + dest,"out_ICACHE_RSP_" +toString(j)+"_ACK" ); +// COMPONENT_MAP(_component,src ,"out_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_THREAD_ID" , +// dest, "in_ICACHE_RSP_" +toString(j)+"_THREAD_ID" ); + if (_param->_have_port_icache_packet_id) + COMPONENT_MAP(_component,src ,"out_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_PACKET_ID" , + dest, "in_ICACHE_RSP_" +toString(j)+"_PACKET_ID" ); + COMPONENT_MAP(_component,src ,"out_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_ERROR" , + dest, "in_ICACHE_RSP_" +toString(j)+"_ERROR" ); + + for (uint32_t k=0; k<_param->_front_end_nb_inst_fetch[i][j];++k) + { +#ifdef POSITION + _component->interface_map (src ,"context_rsp_"+toString(i)+"_"+toString(j)+"_"+toString(k), + dest,"icache_rsp_" +toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src ,"out_CONTEXT_RSP_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_INSTRUCTION", + dest, "in_ICACHE_RSP_" +toString(j)+"_"+toString(k)+"_INSTRUCTION"); + } + + } + } + + // =================================================================== + // =====[ dcache_access ]============================================= + // =================================================================== + { + src = _name+"_dcache_access"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"dcache_req_"+toString(i), + dest,"dcache_req_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" , + dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" , + dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" ); + if (_param->_have_port_dcache_thread_id) + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID", + dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID"); + if (_param->_have_port_dcache_packet_id) + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID", + dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" , + dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" , + dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" , + dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ); + } + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"dcache_rsp_"+toString(i), + dest,"dcache_rsp_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" , + dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" , + dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" ); + if (_param->_have_port_dcache_thread_id) + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID" , + dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID" ); + if (_param->_have_port_dcache_packet_id) + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID" , + dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID" ); + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" , + dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" ); + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" , + dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" ); + } + + // ~~~~~[ Interface "lsq_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_execute_loop_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_execute_loop_nb_cache_port [i][j]; ++k) + { + dest = _name+"_execute_loop_"+toString(i); +#ifdef POSITION + _component->interface_map (src ,"lsq_req_" +toString(i)+"_"+toString(j)+"_"+toString(k), + dest,"dcache_req_" +toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" , + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src ,"out_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_ACK" , + dest, "in_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_ACK" ); + if (_param->_have_port_dcache_thread_id) + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_THREAD_ID", + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_THREAD_ID"); + if (_param->_have_port_dcache_packet_id) + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_PACKET_ID", + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_PACKET_ID"); + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_ADDRESS" , + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_ADDRESS" ); + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_WDATA" , + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_WDATA" ); + COMPONENT_MAP(_component,src , "in_LSQ_REQ_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_TYPE" , + dest,"out_DCACHE_REQ_" +toString(j)+"_"+toString(k)+"_TYPE" ); + } + + // ~~~~~[ Interface "lsq_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + for (uint32_t j=0; j<_param->_execute_loop_nb_load_store_unit[i]; ++j) + for (uint32_t k=0; k<_param->_execute_loop_nb_cache_port [i][j]; ++k) + { + dest = _name+"_execute_loop_"+toString(i); +#ifdef POSITION + _component->interface_map (src ,"lsq_rsp_" +toString(i)+"_"+toString(j)+"_"+toString(k), + dest,"dcache_rsp_" +toString(j)+"_"+toString(k)); +#endif + + COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" , + dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_ACK" , + dest,"out_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_ACK" ); + if (_param->_have_port_dcache_thread_id) + COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_THREAD_ID", + dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_THREAD_ID"); + if (_param->_have_port_dcache_packet_id) + COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_PACKET_ID", + dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_PACKET_ID"); + COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_RDATA" , + dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_RDATA" ); + COMPONENT_MAP(_component,src ,"out_LSQ_RSP_" +toString(i)+"_"+toString(j)+"_"+toString(k)+"_ERROR" , + dest, "in_DCACHE_RSP_" +toString(j)+"_"+toString(k)+"_ERROR" ); + } + } + + // =================================================================== + // =====[ glue ]====================================================== + // =================================================================== + { + src = _name+"_glue"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface : "rename" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_RENAME_FRONT_END_ID - ooo_engine. in_RENAME_FRONT_END_ID + + // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_BRANCH_COMPLETE_FRONT_END_VAL - front_end. in_BRANCH_COMPLETE_VAL + // in_BRANCH_COMPLETE_FRONT_END_ACK - front_end.out_BRANCH_COMPLETE_ACK + // out_BRANCH_COMPLETE_FRONT_END_CONTEXT_ID - front_end. in_BRANCH_COMPLETE_CONTEXT_ID + // out_BRANCH_COMPLETE_FRONT_END_DEPTH - front_end. in_BRANCH_COMPLETE_DEPTH + // out_BRANCH_COMPLETE_FRONT_END_ADDRESS - front_end. in_BRANCH_COMPLETE_ADDRESS + // out_BRANCH_COMPLETE_FRONT_END_FLAG - front_end. in_BRANCH_COMPLETE_FLAG + // in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION - front_end.out_BRANCH_COMPLETE_MISS_PREDICTION + + // in_BRANCH_COMPLETE_OOO_ENGINE_VAL - ooo_engine.out_BRANCH_COMPLETE_VAL + // out_BRANCH_COMPLETE_OOO_ENGINE_ACK - ooo_engine. in_BRANCH_COMPLETE_ACK + // in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID - ooo_engine.out_BRANCH_COMPLETE_FRONT_END_ID + // in_BRANCH_COMPLETE_OOO_ENGINE_CONTEXT_ID - ooo_engine.out_BRANCH_COMPLETE_CONTEXT_ID + // in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH - ooo_engine.out_BRANCH_COMPLETE_DEPTH + // in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS - ooo_engine.out_BRANCH_COMPLETE_ADDRESS + // in_BRANCH_COMPLETE_OOO_ENGINE_FLAG - ooo_engine.out_BRANCH_COMPLETE_FLAG + // out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION- ooo_engine. in_BRANCH_COMPLETE_MISS_PREDICTION + + // ~~~~~[ Interface : "commit_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_COMMIT_EVENT_FRONT_END_VAL - front_end. in_COMMIT_EVENT_VAL + // in_COMMIT_EVENT_FRONT_END_ACK - front_end.out_COMMIT_EVENT_ACK + // out_COMMIT_EVENT_FRONT_END_CONTEXT_ID - front_end. in_COMMIT_EVENT_CONTEXT_ID + // out_COMMIT_EVENT_FRONT_END_DEPTH - front_end. in_COMMIT_EVENT_DEPTH + // out_COMMIT_EVENT_FRONT_END_TYPE - front_end. in_COMMIT_EVENT_TYPE + // out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT - front_end. in_COMMIT_EVENT_IS_DELAY_SLOT + // out_COMMIT_EVENT_FRONT_END_ADDRESS - front_end. in_COMMIT_EVENT_ADDRESS + // out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR - front_end. in_COMMIT_EVENT_ADDRESS_EPCR + // out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL - front_end. in_COMMIT_EVENT_ADDRESS_EEAR_VAL + // out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR - front_end. in_COMMIT_EVENT_ADDRESS_EEAR + + // in_COMMIT_EVENT_OOO_ENGINE_VAL - ooo_engine.out_COMMIT_EVENT_VAL + // out_COMMIT_EVENT_OOO_ENGINE_ACK - ooo_engine. in_COMMIT_EVENT_ACK + // in_COMMIT_EVENT_OOO_ENGINE_FRONT_END_ID - ooo_engine.out_COMMIT_EVENT_FRONT_END_ID + // in_COMMIT_EVENT_OOO_ENGINE_CONTEXT_ID - ooo_engine.out_COMMIT_EVENT_CONTEXT_ID + // in_COMMIT_EVENT_OOO_ENGINE_DEPTH - ooo_engine.out_COMMIT_EVENT_DEPTH + // in_COMMIT_EVENT_OOO_ENGINE_TYPE - ooo_engine.out_COMMIT_EVENT_TYPE + // in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT - ooo_engine.out_COMMIT_EVENT_IS_DELAY_SLOT + // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS - ooo_engine.out_COMMIT_EVENT_ADDRESS + // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR - ooo_engine.out_COMMIT_EVENT_ADDRESS_EPCR + // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL- ooo_engine.out_COMMIT_EVENT_ADDRESS_EEAR_VAL + // in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR - ooo_engine.out_COMMIT_EVENT_ADDRESS_EEAR + + // ~~~~~[ Interface : "issue" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_ISSUE_OOO_ENGINE_VAL - ooo_engine.out_ISSUE_VAL + // out_ISSUE_OOO_ENGINE_ACK - ooo_engine. in_ISSUE_ACK + // in_ISSUE_OOO_ENGINE_FRONT_END_ID - ooo_engine.out_ISSUE_FRONT_END_ID + // in_ISSUE_OOO_ENGINE_CONTEXT_ID - ooo_engine.out_ISSUE_CONTEXT_ID + // in_ISSUE_OOO_ENGINE_PACKET_ID - ooo_engine.out_ISSUE_PACKET_ID + // in_ISSUE_OOO_ENGINE_TYPE - ooo_engine.out_ISSUE_TYPE + // in_ISSUE_OOO_ENGINE_OPERATION - ooo_engine.out_ISSUE_OPERATION + // in_ISSUE_OOO_ENGINE_STORE_QUEUE_PTR_WRITE - ooo_engine.out_ISSUE_STORE_QUEUE_PTR_WRITE + // in_ISSUE_OOO_ENGINE_LOAD_QUEUE_PTR_WRITE - ooo_engine.out_ISSUE_LOAD_QUEUE_PTR_WRITE + // in_ISSUE_OOO_ENGINE_HAS_IMMEDIAT - ooo_engine.out_ISSUE_HAS_IMMEDIAT + // in_ISSUE_OOO_ENGINE_IMMEDIAT - ooo_engine.out_ISSUE_IMMEDIAT + // in_ISSUE_OOO_ENGINE_READ_RA - ooo_engine.out_ISSUE_READ_RA + // in_ISSUE_OOO_ENGINE_NUM_REG_RA - ooo_engine.out_ISSUE_NUM_REG_RA + // in_ISSUE_OOO_ENGINE_READ_RB - ooo_engine.out_ISSUE_READ_RB + // in_ISSUE_OOO_ENGINE_NUM_REG_RB - ooo_engine.out_ISSUE_NUM_REG_RB + // in_ISSUE_OOO_ENGINE_READ_RC - ooo_engine.out_ISSUE_READ_RC + // in_ISSUE_OOO_ENGINE_NUM_REG_RC - ooo_engine.out_ISSUE_NUM_REG_RC + // in_ISSUE_OOO_ENGINE_WRITE_RD - ooo_engine.out_ISSUE_WRITE_RD + // in_ISSUE_OOO_ENGINE_NUM_REG_RD - ooo_engine.out_ISSUE_NUM_REG_RD + // in_ISSUE_OOO_ENGINE_WRITE_RE - ooo_engine.out_ISSUE_WRITE_RE + // in_ISSUE_OOO_ENGINE_NUM_REG_RE - ooo_engine.out_ISSUE_NUM_REG_RE + + // out_ISSUE_EXECUTE_LOOP_VAL - execute_loop. in_EXECUTE_LOOP_IN_VAL + // in_ISSUE_EXECUTE_LOOP_ACK - execute_loop. in_EXECUTE_LOOP_IN_ACK + // out_ISSUE_EXECUTE_LOOP_CONTEXT_ID - execute_loop. in_EXECUTE_LOOP_IN_CONTEXT_ID + // out_ISSUE_EXECUTE_LOOP_FRONT_END_ID - execute_loop. in_EXECUTE_LOOP_IN_FRONT_END_ID + // out_ISSUE_EXECUTE_LOOP_OOO_ENGINE_ID - execute_loop. in_EXECUTE_LOOP_IN_OOO_ENGINE_ID + // out_ISSUE_EXECUTE_LOOP_PACKET_ID - execute_loop. in_EXECUTE_LOOP_IN_PACKET_ID + // out_ISSUE_EXECUTE_LOOP_OPERATION - execute_loop. in_EXECUTE_LOOP_IN_OPERATION + // out_ISSUE_EXECUTE_LOOP_TYPE - execute_loop. in_EXECUTE_LOOP_IN_TYPE + // out_ISSUE_EXECUTE_LOOP_STORE_QUEUE_PTR_WRITE - execute_loop. in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE + // out_ISSUE_EXECUTE_LOOP_LOAD_QUEUE_PTR_WRITE - execute_loop. in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE + // out_ISSUE_EXECUTE_LOOP_HAS_IMMEDIAT - execute_loop. in_EXECUTE_LOOP_IN_HAS_IMMEDIAT + // out_ISSUE_EXECUTE_LOOP_IMMEDIAT - execute_loop. in_EXECUTE_LOOP_IN_IMMEDIAT + // out_ISSUE_EXECUTE_LOOP_READ_RA - execute_loop. in_EXECUTE_LOOP_IN_READ_RA + // out_ISSUE_EXECUTE_LOOP_NUM_REG_RA - execute_loop. in_EXECUTE_LOOP_IN_NUM_REG_RA + // out_ISSUE_EXECUTE_LOOP_READ_RB - execute_loop. in_EXECUTE_LOOP_IN_READ_RB + // out_ISSUE_EXECUTE_LOOP_NUM_REG_RB - execute_loop. in_EXECUTE_LOOP_IN_NUM_REG_RB + // out_ISSUE_EXECUTE_LOOP_READ_RC - execute_loop. in_EXECUTE_LOOP_IN_READ_RC + // out_ISSUE_EXECUTE_LOOP_NUM_REG_RC - execute_loop. in_EXECUTE_LOOP_IN_NUM_REG_RC + // out_ISSUE_EXECUTE_LOOP_WRITE_RD - execute_loop. in_EXECUTE_LOOP_IN_WRITE_RD + // out_ISSUE_EXECUTE_LOOP_NUM_REG_RD - execute_loop. in_EXECUTE_LOOP_IN_NUM_REG_RD + // out_ISSUE_EXECUTE_LOOP_WRITE_RE - execute_loop. in_EXECUTE_LOOP_IN_WRITE_RE + // out_ISSUE_EXECUTE_LOOP_NUM_REG_RE - execute_loop. in_EXECUTE_LOOP_IN_NUM_REG_RE + + + // ~~~~~[ Interface "execute_loop" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // out_EXECUTE_OOO_ENGINE_VAL - ooo_engine. in_EXECUTE_LOOP_VAL + // in_EXECUTE_OOO_ENGINE_ACK - ooo_engine.out_EXECUTE_LOOP_ACK + // out_EXECUTE_OOO_ENGINE_FRONT_END_ID - ooo_engine. in_EXECUTE_LOOP_FRONT_END_ID + // out_EXECUTE_OOO_ENGINE_CONTEXT_ID - ooo_engine. in_EXECUTE_LOOP_CONTEXT_ID + // out_EXECUTE_OOO_ENGINE_PACKET_ID - ooo_engine. in_EXECUTE_LOOP_PACKET_ID + //// out_EXECUTE_OOO_ENGINE_TYPE - ooo_engine. in_EXECUTE_LOOP_TYPE + //// out_EXECUTE_OOO_ENGINE_OPERATION - ooo_engine. in_EXECUTE_LOOP_OPERATION + // out_EXECUTE_OOO_ENGINE_FLAGS - ooo_engine. in_EXECUTE_LOOP_FLAGS + // out_EXECUTE_OOO_ENGINE_EXCEPTION - ooo_engine. in_EXECUTE_LOOP_EXCEPTION + // out_EXECUTE_OOO_ENGINE_NO_SEQUENCE - ooo_engine. in_EXECUTE_LOOP_NO_SEQUENCE + // out_EXECUTE_OOO_ENGINE_ADDRESS - ooo_engine. in_EXECUTE_LOOP_ADDRESS + // out_EXECUTE_OOO_ENGINE_DATA - ooo_engine. in_EXECUTE_LOOP_DATA + + // in_EXECUTE_EXECUTE_LOOP_VAL - execute_loop.out_EXECUTE_LOOP_OUT_VAL + // out_EXECUTE_EXECUTE_LOOP_ACK - execute_loop.out_EXECUTE_LOOP_OUT_ACK + // in_EXECUTE_EXECUTE_LOOP_CONTEXT_ID - execute_loop.out_EXECUTE_LOOP_OUT_CONTEXT_ID + // in_EXECUTE_EXECUTE_LOOP_FRONT_END_ID - execute_loop.out_EXECUTE_LOOP_OUT_FRONT_END_ID + // in_EXECUTE_EXECUTE_LOOP_OOO_ENGINE_ID - execute_loop.out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID + // in_EXECUTE_EXECUTE_LOOP_PACKET_ID - execute_loop.out_EXECUTE_LOOP_OUT_PACKET_ID + //// in_EXECUTE_EXECUTE_LOOP_OPERATION - execute_loop.out_EXECUTE_LOOP_OUT_OPERATION + //// in_EXECUTE_EXECUTE_LOOP_TYPE - execute_loop.out_EXECUTE_LOOP_OUT_TYPE + // in_EXECUTE_EXECUTE_LOOP_FLAGS - execute_loop.out_EXECUTE_LOOP_OUT_FLAGS + // in_EXECUTE_EXECUTE_LOOP_EXCEPTION - execute_loop.out_EXECUTE_LOOP_OUT_EXCEPTION + // in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE - execute_loop.out_EXECUTE_LOOP_OUT_NO_SEQUENCE + // in_EXECUTE_EXECUTE_LOOP_ADDRESS - execute_loop.out_EXECUTE_LOOP_OUT_ADDRESS + // in_EXECUTE_EXECUTE_LOOP_DATA - execute_loop.out_EXECUTE_LOOP_OUT_DATA + + // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // in_INSERT_OOO_ENGINE_VAL - ooo_engine.out_INSERT_VAL + // out_INSERT_OOO_ENGINE_ACK - ooo_engine. in_INSERT_ACK + // in_INSERT_OOO_ENGINE_RD_USE - ooo_engine.out_INSERT_RD_USE + // in_INSERT_OOO_ENGINE_RD_NUM_REG - ooo_engine.out_INSERT_RD_NUM_REG + // in_INSERT_OOO_ENGINE_RE_USE - ooo_engine.out_INSERT_RE_USE + // in_INSERT_OOO_ENGINE_RE_NUM_REG - ooo_engine.out_INSERT_RE_NUM_REG + + // out_INSERT_EXECUTE_LOOP_VAL - execute_loop. in_INSERT_ROB_VAL + // in_INSERT_EXECUTE_LOOP_ACK - execute_loop.out_INSERT_ROB_ACK + // out_INSERT_EXECUTE_LOOP_RD_USE - execute_loop. in_INSERT_ROB_RD_USE + // out_INSERT_EXECUTE_LOOP_RD_NUM_REG - execute_loop. in_INSERT_ROB_RD_NUM_REG + // out_INSERT_EXECUTE_LOOP_RE_USE - execute_loop. in_INSERT_ROB_RE_USE + // out_INSERT_EXECUTE_LOOP_RE_NUM_REG - execute_loop. in_INSERT_ROB_RE_NUM_REG + + } + + // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#if DEBUG_Core == true + _component->test_map(false); +#endif + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_deallocation.cpp (revision 88) @@ -0,0 +1,68 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::deallocation" + void Core::deallocation (void) + { + log_begin(Core,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL(out_ICACHE_REQ_VAL ,_param->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_REQ_ACK ,_param->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param->_nb_icache_port,_param->_size_icache_thread_id); + DELETE1_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param->_nb_icache_port,_param->_size_icache_packet_id); + DELETE1_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param->_nb_icache_port,_param->_size_icache_address); + DELETE1_SIGNAL(out_ICACHE_REQ_TYPE ,_param->_nb_icache_port,_param->_size_icache_type); + + DELETE1_SIGNAL( in_ICACHE_RSP_VAL ,_param->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_RSP_ACK ,_param->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param->_nb_icache_port,_param->_size_icache_thread_id); + DELETE1_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param->_nb_icache_port,_param->_size_icache_packet_id); + DELETE1_SIGNAL( in_ICACHE_RSP_ERROR ,_param->_nb_icache_port,_param->_size_icache_error); + DELETE2_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param->_nb_icache_port,_param->_icache_nb_instruction[it1],_param->_size_instruction); + + DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_param->_nb_dcache_port,_param->_size_dcache_thread_id); + DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param->_nb_dcache_port,_param->_size_dcache_packet_id); + DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param->_nb_dcache_port,_param->_size_dcache_address); + DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param->_nb_dcache_port,_param->_size_dcache_data); + DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param->_nb_dcache_port,_param->_size_dcache_type); + + DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_param->_nb_dcache_port,_param->_size_dcache_thread_id); + DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param->_nb_dcache_port,_param->_size_dcache_packet_id); + DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param->_nb_dcache_port,_param->_size_dcache_data); + DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param->_nb_dcache_port,_param->_size_dcache_error); + + DELETE1_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_thread,1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_end_cycle.cpp (revision 88) @@ -0,0 +1,40 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::end_cycle" +void Core::end_cycle () + { + log_begin(Core,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_allocation.cpp (revision 88) @@ -0,0 +1,42 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::statistics_allocation" + void Core::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Core,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Core", + param_statistics); + + for (uint32_t i=0; i<_param->_nb_front_end; ++i) + _stat->add_stat(_component_front_end [i]->_stat); + for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) + _stat->add_stat(_component_ooo_engine [i]->_stat); + for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) + _stat->add_stat(_component_execute_loop [i]->_stat); + _stat->add_stat(_component_icache_access->_stat); + _stat->add_stat(_component_dcache_access->_stat); + _stat->add_stat(_component_glue->_stat); + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,32 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::statistics_deallocation" + void Core::statistics_deallocation (void) + { + log_begin(Core,FUNCTION); + + log_printf(INFO,Core,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_transition.cpp (revision 88) @@ -0,0 +1,34 @@ +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::transition" + void Core::transition (void) + { + log_begin(Core,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +# endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_vhdl.cpp (revision 88) @@ -0,0 +1,38 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Core.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::vhdl" + void Core::vhdl (void) + { + log_begin(Core,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 88) @@ -0,0 +1,2068 @@ +/* + * $id$ + * + * [ description ] + * + */ + +#include "Behavioural/Core/include/Parameters.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Max.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { + +#undef FUNCTION +#define FUNCTION "Core::get_num_thread" + Tcontext_t Parameters::execute_loop_get_num_thread (uint32_t num_execute_loop, + uint32_t num_thread) + { + log_printf(TRACE,Core,FUNCTION,_("execute_loop_get_num_thread")); + log_printf(TRACE,Core,FUNCTION,_(" * Parameters :")); + log_printf(TRACE,Core,FUNCTION,_(" * num_execute_loop : %d"),num_execute_loop); + log_printf(TRACE,Core,FUNCTION,_(" * num_thread : %d"),num_thread); + + // compute all id ! + // * initialisation + uint32_t num_context = _link_context_with_thread [num_thread].second; + uint32_t num_front_end = _link_context_with_thread [num_thread].first; + uint32_t num_ooo_engine = _link_rename_unit_with_rename_bloc[_link_rename_bloc_with_front_end [num_front_end]].first; + + log_printf(TRACE,Core,FUNCTION,_(" * num_context : %d"),num_context ); + log_printf(TRACE,Core,FUNCTION,_(" * num_front_end : %d"),num_front_end ); + log_printf(TRACE,Core,FUNCTION,_(" * num_ooo_engine : %d"),num_ooo_engine); + + uint32_t context_id = num_context; + uint32_t front_end_id ; + uint32_t ooo_engine_id; + + // * compute + for (ooo_engine_id=0; ooo_engine_id<_execute_loop_nb_ooo_engine [num_execute_loop]; ++ooo_engine_id) + if (_list_ooo_engine_with_execute_loop [num_execute_loop][ooo_engine_id] == num_ooo_engine) + break; + +#ifdef DEBUG_TEST + if (ooo_engine_id == _execute_loop_nb_ooo_engine [num_execute_loop]) + throw ERRORMORPHEO(FUNCTION,toString(_("execute_loop [%d] : ooo_engine [%d] is not find."),num_execute_loop,num_ooo_engine)); +#endif + + log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_id : %d"),ooo_engine_id); + + for (front_end_id=0; front_end_id<_ooo_engine_nb_front_end[num_ooo_engine]; ++front_end_id) + if (_translate_ooo_engine_num_front_end [num_ooo_engine][front_end_id] == num_front_end) + break; + +#ifdef DEBUG_TEST + if (front_end_id == _execute_loop_nb_front_end [num_execute_loop]) + throw ERRORMORPHEO(FUNCTION,toString(_("execute_loop [%d] : front_end [%d] is not find."),num_execute_loop,num_front_end)); +#endif + + log_printf(TRACE,Core,FUNCTION,_(" * front_end_id : %d"),front_end_id ); + + // compute the thread number + return get_num_thread(context_id , (1<<_execute_loop_nb_context [num_execute_loop]), + front_end_id , (1<<_execute_loop_nb_front_end [num_execute_loop]), + ooo_engine_id, (1<<_execute_loop_nb_ooo_engine [num_execute_loop])); + } + + +#undef FUNCTION +#define FUNCTION "Core::Parameters" + Parameters::Parameters ( + // Common + uint32_t size_general_data , + uint32_t size_special_data , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void), + + // Thread + uint32_t nb_thread , + uint32_t * size_ifetch_queue ,//[nb_thread] + uint32_t * nb_inst_fetch ,//[nb_thread] + bool ** implement_group ,//[nb_thread][NB_GROUP] + uint32_t * ras_size_queue ,//[nb_thread] + uint32_t * upt_size_queue ,//[nb_thread] + + // Decod bloc + uint32_t nb_decod_bloc , + uint32_t * size_decod_queue ,//[nb_decod_bloc] + uint32_t * nb_inst_decod ,//[nb_decod_bloc] + uint32_t * nb_context_select ,//[nb_decod_bloc] + Tpriority_t * context_select_priority ,//[nb_decod_bloc] + Tload_balancing_t * context_select_load_balancing ,//[nb_decod_bloc] + + // Rename bloc + uint32_t nb_rename_bloc , + uint32_t * nb_inst_insert ,//[nb_rename_bloc] + uint32_t * nb_inst_retire ,//[nb_rename_bloc] + Tpriority_t * rename_select_priority ,//[nb_rename_bloc] + Tload_balancing_t * rename_select_load_balancing ,//[nb_rename_bloc] + uint32_t * rename_select_nb_front_end_select ,//[nb_rename_bloc] + uint32_t * nb_general_register ,//[nb_rename_bloc] + uint32_t * nb_special_register ,//[nb_rename_bloc] + uint32_t * nb_reg_free ,//[nb_rename_bloc] + uint32_t * nb_rename_unit_bank ,//[nb_rename_bloc] + uint32_t * size_read_counter ,//[nb_rename_bloc] + + // Read bloc + uint32_t nb_read_bloc ,// + uint32_t * size_read_queue ,//[nb_read_bloc] + uint32_t * size_reservation_station ,//[nb_read_bloc] + uint32_t * nb_inst_retire_reservation_station ,//[nb_read_bloc] + + // Write bloc + uint32_t nb_write_bloc ,// + uint32_t * size_write_queue ,//[nb_write_bloc] + uint32_t * size_execute_queue ,//[nb_write_bloc] + uint32_t * nb_bypass_write ,//[nb_write_bloc] + + // Load_store_unit + uint32_t nb_load_store_unit , + uint32_t * size_store_queue ,//[nb_load_store_unit] + uint32_t * size_load_queue ,//[nb_load_store_unit] + uint32_t * size_speculative_access_queue ,//[nb_load_store_unit] + uint32_t * nb_port_check ,//[nb_load_store_unit] + multi_execute_loop::execute_loop::Tspeculative_load_t + * speculative_load ,//[nb_load_store_unit] + uint32_t * nb_bypass_memory ,//[nb_load_store_unit] + uint32_t * nb_cache_port ,//[nb_load_store_unit] + uint32_t * nb_inst_memory ,//[nb_load_store_unit] + + // Functionnal_unit + uint32_t nb_functionnal_unit , + uint32_t * nb_inst_functionnal_unit ,//[nb_functionnal_unit] + multi_execute_loop::execute_loop::execute_timing_t + *** timing ,//[nb_functionnal_unit][_nb_type][_nb_operation] + + // Icache_Access + uint32_t nb_icache_port , + Tpriority_t icache_port_priority , + Tload_balancing_t icache_port_load_balancing , + + // Dcache_Access + uint32_t nb_dcache_port , + Tpriority_t dcache_port_priority , + Tload_balancing_t dcache_port_load_balancing , + + // Front_end + uint32_t nb_front_end , + uint32_t * nb_context ,//[nb_front_end] + uint32_t * nb_decod_unit ,//[nb_front_end] + uint32_t * nb_inst_branch_predict ,//[nb_front_end] + uint32_t * nb_inst_branch_decod ,//[nb_front_end] + uint32_t * nb_inst_branch_update ,//[nb_front_end] + uint32_t * btb_size_queue ,//[nb_front_end] + uint32_t * btb_associativity ,//[nb_front_end] + uint32_t * btb_size_counter ,//[nb_front_end] + Tvictim_t * btb_victim_scheme ,//[nb_front_end] + Tpredictor_t * dir_predictor_scheme ,//[nb_front_end] + bool ** dir_have_bht ,//[nb_front_end][3] + uint32_t ** dir_bht_size_shifter ,//[nb_front_end][3] + uint32_t ** dir_bht_nb_shifter ,//[nb_front_end][3] + bool ** dir_have_pht ,//[nb_front_end][3] + uint32_t ** dir_pht_size_counter ,//[nb_front_end][3] + uint32_t ** dir_pht_nb_counter ,//[nb_front_end][3] + uint32_t ** dir_pht_size_address_share ,//[nb_front_end][3] + + // OOO_Engine + uint32_t nb_ooo_engine , + uint32_t * nb_rename_unit ,//[nb_ooo_engine] + uint32_t * nb_inst_issue ,//[nb_ooo_engine] + uint32_t * nb_inst_reexecute ,//[nb_ooo_engine] + uint32_t * nb_inst_commit ,//[nb_ooo_engine] + uint32_t * nb_inst_branch_complete ,//[nb_ooo_engine] + uint32_t * nb_rename_unit_select ,//[nb_ooo_engine] + uint32_t * nb_execute_loop_select ,//[nb_ooo_engine] + uint32_t * size_re_order_buffer ,//[nb_ooo_engine] + uint32_t * nb_re_order_buffer_bank ,//[nb_ooo_engine] + Tpriority_t * commit_priority ,//[nb_ooo_engine] + Tload_balancing_t * commit_load_balancing ,//[nb_ooo_engine] + uint32_t * size_issue_queue ,//[nb_ooo_engine] + uint32_t * nb_issue_queue_bank ,//[nb_ooo_engine] + Tpriority_t * issue_priority ,//[nb_ooo_engine] + Tload_balancing_t * issue_load_balancing ,//[nb_ooo_engine] + uint32_t * size_reexecute_queue ,//[nb_ooo_engine] + Tpriority_t * reexecute_priority ,//[nb_ooo_engine] + Tload_balancing_t * reexecute_load_balancing ,//[nb_ooo_engine] + + //Execute_loop + uint32_t nb_execute_loop , + uint32_t * nb_read_unit ,//[nb_execute_loop] + uint32_t * nb_execute_unit ,//[nb_execute_loop] + uint32_t * nb_write_unit ,//[nb_execute_loop] + uint32_t * nb_gpr_bank ,//[nb_execute_loop] + uint32_t * nb_gpr_port_read_by_bank ,//[nb_execute_loop] + uint32_t * nb_gpr_port_write_by_bank ,//[nb_execute_loop] + uint32_t * nb_spr_bank ,//[nb_execute_loop] + uint32_t * nb_spr_port_read_by_bank ,//[nb_execute_loop] + uint32_t * nb_spr_port_write_by_bank ,//[nb_execute_loop] + Tpriority_t * execution_unit_to_write_unit_priority ,//[nb_execute_loop] + Tpriority_t * read_unit_to_execution_unit_priority ,//[nb_execute_loop] + + // Link + pair_dual * link_context_with_thread ,//[nb_thread] + pair_dual * link_decod_unit_with_decod_bloc ,//[nb_decod_bloc] + pair_dual * link_rename_unit_with_rename_bloc ,//[nb_rename_bloc] + pair_dual * link_read_unit_with_read_bloc ,//[nb_read_bloc] + pair_dual * link_write_unit_with_write_bloc ,//[nb_write_bloc] + pair_dual * link_execute_unit_with_functionnal_unit ,//[nb_functionnal_unit] + pair_dual * link_execute_unit_with_load_store_unit ,//[nb_load_store_unit] + uint32_t * link_decod_bloc_with_thread ,//[nb_thread] + uint32_t * link_rename_bloc_with_front_end ,//[nb_front_end] + bool *** table_dispatch ,//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + bool ** link_read_bloc_and_load_store_unit ,//[nb_read_bloc][nb_load_store_unit] + bool ** link_read_bloc_and_functionnal_unit ,//[nb_read_bloc][nb_functionnal_unit] + bool ** link_write_bloc_and_load_store_unit ,//[nb_write_bloc][nb_load_store_unit] + bool ** link_write_bloc_and_functionnal_unit ,//[nb_write_bloc][nb_functionnal_unit] + uint32_t * link_load_store_unit_with_thread ,//[nb_thread] + bool ** link_thread_and_functionnal_unit ,//[nb_thread][nb_functionnal_unit] + uint32_t * link_icache_port_with_thread ,//[nb_thread] + uint32_t ** link_dcache_port_with_load_store_unit ,//[nb_load_store_unit][nb_cache_port] + + Tpriority_t dispatch_priority , + Tload_balancing_t dispatch_load_balancing + ) + { + log_begin(Core,FUNCTION); + + _size_general_data = size_general_data ; + _size_special_data = size_special_data ; + _get_custom_information = get_custom_information ; + + _nb_thread = nb_thread ; + _size_ifetch_queue = size_ifetch_queue ; + _nb_inst_fetch = nb_inst_fetch ; + _implement_group = implement_group ; + _ras_size_queue = ras_size_queue ; + _upt_size_queue = upt_size_queue ; + + _nb_decod_bloc = nb_decod_bloc ; + _size_decod_queue = size_decod_queue ; + _nb_inst_decod = nb_inst_decod ; + _nb_context_select = nb_context_select ; + _context_select_priority = context_select_priority ; + _context_select_load_balancing = context_select_load_balancing ; + + _nb_rename_bloc = nb_rename_bloc ; + _nb_inst_insert = nb_inst_insert ; + _nb_inst_retire = nb_inst_retire ; + _rename_select_priority = rename_select_priority ; + _rename_select_load_balancing = rename_select_load_balancing ; + _rename_select_nb_front_end_select = rename_select_nb_front_end_select ; + _nb_general_register = nb_general_register ; + _nb_special_register = nb_special_register ; + _nb_reg_free = nb_reg_free ; + _nb_rename_unit_bank = nb_rename_unit_bank ; + _size_read_counter = size_read_counter ; + + _nb_read_bloc = nb_read_bloc ; + _size_read_queue = size_read_queue ; + _size_reservation_station = size_reservation_station ; + _nb_inst_retire_reservation_station = nb_inst_retire_reservation_station ; + + _nb_write_bloc = nb_write_bloc ; + _size_write_queue = size_write_queue ; + _size_execute_queue = size_execute_queue ; + _nb_bypass_write = nb_bypass_write ; + + _nb_load_store_unit = nb_load_store_unit ; + _size_store_queue = size_store_queue ; + _size_load_queue = size_load_queue ; + _size_speculative_access_queue = size_speculative_access_queue ; + _nb_port_check = nb_port_check ; + _speculative_load = speculative_load ; + _nb_bypass_memory = nb_bypass_memory ; + _nb_cache_port = nb_cache_port ; + _nb_inst_memory = nb_inst_memory ; + + _nb_functionnal_unit = nb_functionnal_unit ; + _nb_inst_functionnal_unit = nb_inst_functionnal_unit ; + _timing = timing ; + + _nb_icache_port = nb_icache_port ; + _icache_port_priority = icache_port_priority ; + _icache_port_load_balancing = icache_port_load_balancing ; + + _nb_dcache_port = nb_dcache_port ; + _dcache_port_priority = dcache_port_priority ; + _dcache_port_load_balancing = dcache_port_load_balancing ; + + _nb_front_end = nb_front_end ; + _nb_context = nb_context ; + _nb_decod_unit = nb_decod_unit ; + _nb_inst_branch_predict = nb_inst_branch_predict ; + _nb_inst_branch_decod = nb_inst_branch_decod ; + _nb_inst_branch_update = nb_inst_branch_update ; + _btb_size_queue = btb_size_queue ; + _btb_associativity = btb_associativity ; + _btb_size_counter = btb_size_counter ; + _btb_victim_scheme = btb_victim_scheme ; + _dir_predictor_scheme = dir_predictor_scheme ; + _dir_have_bht = dir_have_bht ; + _dir_bht_size_shifter = dir_bht_size_shifter ; + _dir_bht_nb_shifter = dir_bht_nb_shifter ; + _dir_have_pht = dir_have_pht ; + _dir_pht_size_counter = dir_pht_size_counter ; + _dir_pht_nb_counter = dir_pht_nb_counter ; + _dir_pht_size_address_share = dir_pht_size_address_share ; + + _nb_ooo_engine = nb_ooo_engine ; + _nb_rename_unit = nb_rename_unit ; + _nb_inst_issue = nb_inst_issue ; + _nb_inst_reexecute = nb_inst_reexecute ; + _nb_inst_commit = nb_inst_commit ; + _nb_inst_branch_complete = nb_inst_branch_complete ; + _nb_rename_unit_select = nb_rename_unit_select ; + _nb_execute_loop_select = nb_execute_loop_select ; + _size_re_order_buffer = size_re_order_buffer ; + _nb_re_order_buffer_bank = nb_re_order_buffer_bank ; + _commit_priority = commit_priority ; + _commit_load_balancing = commit_load_balancing ; + _size_issue_queue = size_issue_queue ; + _nb_issue_queue_bank = nb_issue_queue_bank ; + _issue_priority = issue_priority ; + _issue_load_balancing = issue_load_balancing ; + _size_reexecute_queue = size_reexecute_queue ; + _reexecute_priority = reexecute_priority ; + _reexecute_load_balancing = reexecute_load_balancing ; + + _nb_execute_loop = nb_execute_loop ; + _nb_read_unit = nb_read_unit ; + _nb_execute_unit = nb_execute_unit ; + _nb_write_unit = nb_write_unit ; + _nb_gpr_bank = nb_gpr_bank ; + _nb_gpr_port_read_by_bank = nb_gpr_port_read_by_bank ; + _nb_gpr_port_write_by_bank = nb_gpr_port_write_by_bank ; + _nb_spr_bank = nb_spr_bank ; + _nb_spr_port_read_by_bank = nb_spr_port_read_by_bank ; + _nb_spr_port_write_by_bank = nb_spr_port_write_by_bank ; + _execution_unit_to_write_unit_priority = execution_unit_to_write_unit_priority ; + _read_unit_to_execution_unit_priority = read_unit_to_execution_unit_priority ; + + _link_context_with_thread = link_context_with_thread ; + _link_decod_unit_with_decod_bloc = link_decod_unit_with_decod_bloc ; + _link_rename_unit_with_rename_bloc = link_rename_unit_with_rename_bloc ; + _link_read_unit_with_read_bloc = link_read_unit_with_read_bloc ; + _link_write_unit_with_write_bloc = link_write_unit_with_write_bloc ; + _link_execute_unit_with_functionnal_unit = link_execute_unit_with_functionnal_unit ; + _link_execute_unit_with_load_store_unit = link_execute_unit_with_load_store_unit ; + _link_decod_bloc_with_thread = link_decod_bloc_with_thread ; + _link_rename_bloc_with_front_end = link_rename_bloc_with_front_end ; + _table_dispatch = table_dispatch ; + _link_read_bloc_and_load_store_unit = link_read_bloc_and_load_store_unit ; + _link_read_bloc_and_functionnal_unit = link_read_bloc_and_functionnal_unit ; + _link_write_bloc_and_load_store_unit = link_write_bloc_and_load_store_unit ; + _link_write_bloc_and_functionnal_unit = link_write_bloc_and_functionnal_unit ; + _link_load_store_unit_with_thread = link_load_store_unit_with_thread ; + _link_thread_and_functionnal_unit = link_thread_and_functionnal_unit ; + _link_icache_port_with_thread = link_icache_port_with_thread ; + _link_dcache_port_with_load_store_unit = link_dcache_port_with_load_store_unit ; + + _dispatch_priority = dispatch_priority ; + _dispatch_load_balancing = dispatch_load_balancing ; + + test(); + + log_printf(TRACE,Core,FUNCTION,_("Core parameters :")); + + // inverse link + ALLOC2(_link_thread_with_context ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_link_decod_bloc_with_decod_unit ,uint32_t ,_nb_front_end,_nb_decod_unit[it1]); + ALLOC2(_link_rename_bloc_with_rename_unit ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_link_read_bloc_with_read_unit ,uint32_t ,_nb_execute_loop,_nb_read_unit[it1]); + ALLOC2(_link_write_bloc_with_write_unit ,uint32_t ,_nb_execute_loop,_nb_write_unit[it1]); + ALLOC2(_link_functionnal_unit_with_execute_unit ,uint32_t ,_nb_execute_loop,_nb_execute_unit[it1]); + ALLOC2(_link_load_store_unit_with_execute_unit ,uint32_t ,_nb_execute_loop,_nb_execute_unit[it1]); + ALLOC1(_list_functionnal_unit_with_execute_unit ,std::vector,_nb_execute_loop); + ALLOC1(_list_load_store_unit_with_execute_unit ,std::vector,_nb_execute_loop); + + for (uint32_t i=0; i<_nb_thread; ++i) + { + pair_dual x = _link_context_with_thread[i]; + _link_thread_with_context [x.first][x.second] = i; + } + for (uint32_t i=0; i<_nb_decod_bloc; ++i) + { + pair_dual x = _link_decod_unit_with_decod_bloc[i]; + _link_decod_bloc_with_decod_unit [x.first][x.second] = i; + } + for (uint32_t i=0; i<_nb_rename_bloc; ++i) + { + pair_dual x = _link_rename_unit_with_rename_bloc[i]; + _link_rename_bloc_with_rename_unit [x.first][x.second] = i; + } + for (uint32_t i=0; i<_nb_read_bloc; ++i) + { + pair_dual x = _link_read_unit_with_read_bloc[i]; + _link_read_bloc_with_read_unit [x.first][x.second] = i; + } + for (uint32_t i=0; i<_nb_write_bloc; ++i) + { + pair_dual x = _link_write_unit_with_write_bloc[i]; + _link_write_bloc_with_write_unit [x.first][x.second] = i; + } + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + // init with an invalid value + _link_functionnal_unit_with_execute_unit [i][j] = _nb_functionnal_unit; + _link_load_store_unit_with_execute_unit [i][j] = _nb_load_store_unit; + } + + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + { + pair_dual x = _link_execute_unit_with_functionnal_unit[i]; + _link_functionnal_unit_with_execute_unit [x.first][x.second] = i; + } + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + { + pair_dual x = _link_execute_unit_with_load_store_unit[i]; + _link_load_store_unit_with_execute_unit [x.first][x.second] = i; + } + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + log_printf(TRACE,Core,FUNCTION,_(" * execute_unit [%d][%d] : functionnal_unit [%d] - load_store_unit [%d]"),i,j,_link_functionnal_unit_with_execute_unit [i][j],_link_load_store_unit_with_execute_unit [i][j]); + + + if (_link_functionnal_unit_with_execute_unit [i][j] != _nb_functionnal_unit) + _list_functionnal_unit_with_execute_unit [i].push_back(_link_functionnal_unit_with_execute_unit [i][j]); + if (_link_load_store_unit_with_execute_unit [i][j] != _nb_load_store_unit) + _list_load_store_unit_with_execute_unit [i].push_back(_link_load_store_unit_with_execute_unit [i][j]); + } + + // translate for front_end + ALLOC2(_front_end_size_ifetch_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_front_end_nb_inst_fetch ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_front_end_link_decod_unit_with_context ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_front_end_ras_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_front_end_upt_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); + + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + { + uint32_t num_thread = _link_thread_with_context[i][j]; + + _front_end_size_ifetch_queue [i][j] = _size_ifetch_queue [num_thread]; + _front_end_nb_inst_fetch [i][j] = _nb_inst_fetch [num_thread]; + _front_end_ras_size_queue [i][j] = _ras_size_queue [num_thread]; + _front_end_upt_size_queue [i][j] = _upt_size_queue [num_thread]; + + uint32_t num_decod_bloc = _link_decod_bloc_with_thread [num_thread]; + uint32_t num_decod_unit = _link_decod_unit_with_decod_bloc [num_decod_bloc].second; + + _front_end_link_decod_unit_with_context [i][j] = num_decod_unit; + } + + ALLOC3(_front_end_instruction_implemeted ,bool ,_nb_front_end,_nb_context[it1],NB_INSTRUCTION); + + // Reset instruction implemented + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + for (uint32_t k=0; k 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ADDC ] |= (instruction_size_data(INSTRUCTION_L_ADDC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ADDC )._type][instruction_information(INSTRUCTION_L_ADDC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ADDI ] |= (instruction_size_data(INSTRUCTION_L_ADDI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ADDI )._type][instruction_information(INSTRUCTION_L_ADDI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ADDIC ] |= (instruction_size_data(INSTRUCTION_L_ADDIC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ADDIC )._type][instruction_information(INSTRUCTION_L_ADDIC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_AND ] |= (instruction_size_data(INSTRUCTION_L_AND ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_AND )._type][instruction_information(INSTRUCTION_L_AND )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ANDI ] |= (instruction_size_data(INSTRUCTION_L_ANDI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ANDI )._type][instruction_information(INSTRUCTION_L_ANDI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_BF ] |= (instruction_size_data(INSTRUCTION_L_BF ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_BF )._type][instruction_information(INSTRUCTION_L_BF )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_BNF ] |= (instruction_size_data(INSTRUCTION_L_BNF ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_BNF )._type][instruction_information(INSTRUCTION_L_BNF )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CMOV ] |= (instruction_size_data(INSTRUCTION_L_CMOV ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CMOV )._type][instruction_information(INSTRUCTION_L_CMOV )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CSYNC ] |= (instruction_size_data(INSTRUCTION_L_CSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CSYNC )._type][instruction_information(INSTRUCTION_L_CSYNC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST1 ] |= (instruction_size_data(INSTRUCTION_L_CUST1 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST1 )._type][instruction_information(INSTRUCTION_L_CUST1 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST2 ] |= (instruction_size_data(INSTRUCTION_L_CUST2 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST2 )._type][instruction_information(INSTRUCTION_L_CUST2 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST3 ] |= (instruction_size_data(INSTRUCTION_L_CUST3 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST3 )._type][instruction_information(INSTRUCTION_L_CUST3 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST4 ] |= (instruction_size_data(INSTRUCTION_L_CUST4 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST4 )._type][instruction_information(INSTRUCTION_L_CUST4 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST5 ] |= (instruction_size_data(INSTRUCTION_L_CUST5 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST5 )._type][instruction_information(INSTRUCTION_L_CUST5 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST6 ] |= (instruction_size_data(INSTRUCTION_L_CUST6 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST6 )._type][instruction_information(INSTRUCTION_L_CUST6 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST7 ] |= (instruction_size_data(INSTRUCTION_L_CUST7 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST7 )._type][instruction_information(INSTRUCTION_L_CUST7 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST8 ] |= (instruction_size_data(INSTRUCTION_L_CUST8 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_CUST8 )._type][instruction_information(INSTRUCTION_L_CUST8 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_DIV ] |= (instruction_size_data(INSTRUCTION_L_DIV ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_DIV )._type][instruction_information(INSTRUCTION_L_DIV )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_DIVU ] |= (instruction_size_data(INSTRUCTION_L_DIVU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_DIVU )._type][instruction_information(INSTRUCTION_L_DIVU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTBS ] |= (instruction_size_data(INSTRUCTION_L_EXTBS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTBS )._type][instruction_information(INSTRUCTION_L_EXTBS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTBZ ] |= (instruction_size_data(INSTRUCTION_L_EXTBZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTBZ )._type][instruction_information(INSTRUCTION_L_EXTBZ )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTHS ] |= (instruction_size_data(INSTRUCTION_L_EXTHS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTHS )._type][instruction_information(INSTRUCTION_L_EXTHS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTHZ ] |= (instruction_size_data(INSTRUCTION_L_EXTHZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTHZ )._type][instruction_information(INSTRUCTION_L_EXTHZ )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTWS ] |= (instruction_size_data(INSTRUCTION_L_EXTWS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTWS )._type][instruction_information(INSTRUCTION_L_EXTWS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_EXTWZ ] |= (instruction_size_data(INSTRUCTION_L_EXTWZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_EXTWZ )._type][instruction_information(INSTRUCTION_L_EXTWZ )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_FF1 ] |= (instruction_size_data(INSTRUCTION_L_FF1 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_FF1 )._type][instruction_information(INSTRUCTION_L_FF1 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_FL1 ] |= (instruction_size_data(INSTRUCTION_L_FL1 ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_FL1 )._type][instruction_information(INSTRUCTION_L_FL1 )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_J ] |= (instruction_size_data(INSTRUCTION_L_J ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_J )._type][instruction_information(INSTRUCTION_L_J )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_JAL ] |= (instruction_size_data(INSTRUCTION_L_JAL ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_JAL )._type][instruction_information(INSTRUCTION_L_JAL )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_JALR ] |= (instruction_size_data(INSTRUCTION_L_JALR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_JALR )._type][instruction_information(INSTRUCTION_L_JALR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_JR ] |= (instruction_size_data(INSTRUCTION_L_JR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_JR )._type][instruction_information(INSTRUCTION_L_JR )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LBS ] |= (instruction_size_data(INSTRUCTION_L_LBS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LBS )._type][instruction_information(INSTRUCTION_L_LBS )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LBZ ] |= (instruction_size_data(INSTRUCTION_L_LBZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LBZ )._type][instruction_information(INSTRUCTION_L_LBZ )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LD ] |= (instruction_size_data(INSTRUCTION_L_LD ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LHS ] |= (instruction_size_data(INSTRUCTION_L_LHS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LHS )._type][instruction_information(INSTRUCTION_L_LHS )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LHZ ] |= (instruction_size_data(INSTRUCTION_L_LHZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LHZ )._type][instruction_information(INSTRUCTION_L_LHZ )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LWS ] |= (instruction_size_data(INSTRUCTION_L_LWS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LWS )._type][instruction_information(INSTRUCTION_L_LWS )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LWZ ] |= (instruction_size_data(INSTRUCTION_L_LWZ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_LWZ )._type][instruction_information(INSTRUCTION_L_LWZ )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MAC ] |= (instruction_size_data(INSTRUCTION_L_MAC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MAC )._type][instruction_information(INSTRUCTION_L_MAC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MACI ] |= (instruction_size_data(INSTRUCTION_L_MACI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MACI )._type][instruction_information(INSTRUCTION_L_MACI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MACRC ] |= (instruction_size_data(INSTRUCTION_L_MACRC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MACRC )._type][instruction_information(INSTRUCTION_L_MACRC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MFSPR ] |= (instruction_size_data(INSTRUCTION_L_MFSPR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MFSPR )._type][instruction_information(INSTRUCTION_L_MFSPR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MOVHI ] |= (instruction_size_data(INSTRUCTION_L_MOVHI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MOVHI )._type][instruction_information(INSTRUCTION_L_MOVHI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSB ] |= (instruction_size_data(INSTRUCTION_L_MSB ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MSB )._type][instruction_information(INSTRUCTION_L_MSB )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MSYNC ] |= (instruction_size_data(INSTRUCTION_L_MSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MSYNC )._type][instruction_information(INSTRUCTION_L_MSYNC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MTSPR ] |= (instruction_size_data(INSTRUCTION_L_MTSPR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MTSPR )._type][instruction_information(INSTRUCTION_L_MTSPR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MUL ] |= (instruction_size_data(INSTRUCTION_L_MUL ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MUL )._type][instruction_information(INSTRUCTION_L_MUL )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MULI ] |= (instruction_size_data(INSTRUCTION_L_MULI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MULI )._type][instruction_information(INSTRUCTION_L_MULI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_MULU ] |= (instruction_size_data(INSTRUCTION_L_MULU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_MULU )._type][instruction_information(INSTRUCTION_L_MULU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_NOP ] |= (instruction_size_data(INSTRUCTION_L_NOP ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_NOP )._type][instruction_information(INSTRUCTION_L_NOP )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_OR ] |= (instruction_size_data(INSTRUCTION_L_OR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_OR )._type][instruction_information(INSTRUCTION_L_OR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ORI ] |= (instruction_size_data(INSTRUCTION_L_ORI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ORI )._type][instruction_information(INSTRUCTION_L_ORI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_PSYNC ] |= (instruction_size_data(INSTRUCTION_L_PSYNC ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_PSYNC )._type][instruction_information(INSTRUCTION_L_PSYNC )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_RFE ] |= (instruction_size_data(INSTRUCTION_L_RFE ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_RFE )._type][instruction_information(INSTRUCTION_L_RFE )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_ROR ] |= (instruction_size_data(INSTRUCTION_L_ROR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_ROR )._type][instruction_information(INSTRUCTION_L_ROR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_RORI ] |= (instruction_size_data(INSTRUCTION_L_RORI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_RORI )._type][instruction_information(INSTRUCTION_L_RORI )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SB ] |= (instruction_size_data(INSTRUCTION_L_SB ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SD ] |= (instruction_size_data(INSTRUCTION_L_SD ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFEQ ] |= (instruction_size_data(INSTRUCTION_L_SFEQ ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFEQ )._type][instruction_information(INSTRUCTION_L_SFEQ )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFEQI ] |= (instruction_size_data(INSTRUCTION_L_SFEQI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFEQI )._type][instruction_information(INSTRUCTION_L_SFEQI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGES ] |= (instruction_size_data(INSTRUCTION_L_SFGES ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGES )._type][instruction_information(INSTRUCTION_L_SFGES )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGESI ] |= (instruction_size_data(INSTRUCTION_L_SFGESI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGESI )._type][instruction_information(INSTRUCTION_L_SFGESI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGEU ] |= (instruction_size_data(INSTRUCTION_L_SFGEU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGEU )._type][instruction_information(INSTRUCTION_L_SFGEU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGEUI ] |= (instruction_size_data(INSTRUCTION_L_SFGEUI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGEUI )._type][instruction_information(INSTRUCTION_L_SFGEUI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGTS ] |= (instruction_size_data(INSTRUCTION_L_SFGTS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGTS )._type][instruction_information(INSTRUCTION_L_SFGTS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGTSI ] |= (instruction_size_data(INSTRUCTION_L_SFGTSI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGTSI )._type][instruction_information(INSTRUCTION_L_SFGTSI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGTU ] |= (instruction_size_data(INSTRUCTION_L_SFGTU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGTU )._type][instruction_information(INSTRUCTION_L_SFGTU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFGTUI ] |= (instruction_size_data(INSTRUCTION_L_SFGTUI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFGTUI )._type][instruction_information(INSTRUCTION_L_SFGTUI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLES ] |= (instruction_size_data(INSTRUCTION_L_SFLES ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLES )._type][instruction_information(INSTRUCTION_L_SFLES )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLESI ] |= (instruction_size_data(INSTRUCTION_L_SFLESI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLESI )._type][instruction_information(INSTRUCTION_L_SFLESI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLEU ] |= (instruction_size_data(INSTRUCTION_L_SFLEU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLEU )._type][instruction_information(INSTRUCTION_L_SFLEU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLEUI ] |= (instruction_size_data(INSTRUCTION_L_SFLEUI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLEUI )._type][instruction_information(INSTRUCTION_L_SFLEUI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLTS ] |= (instruction_size_data(INSTRUCTION_L_SFLTS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLTS )._type][instruction_information(INSTRUCTION_L_SFLTS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLTSI ] |= (instruction_size_data(INSTRUCTION_L_SFLTSI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLTSI )._type][instruction_information(INSTRUCTION_L_SFLTSI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLTU ] |= (instruction_size_data(INSTRUCTION_L_SFLTU ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLTU )._type][instruction_information(INSTRUCTION_L_SFLTU )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFLTUI ] |= (instruction_size_data(INSTRUCTION_L_SFLTUI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFLTUI )._type][instruction_information(INSTRUCTION_L_SFLTUI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFNE ] |= (instruction_size_data(INSTRUCTION_L_SFNE ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFNE )._type][instruction_information(INSTRUCTION_L_SFNE )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SFNEI ] |= (instruction_size_data(INSTRUCTION_L_SFNEI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SFNEI )._type][instruction_information(INSTRUCTION_L_SFNEI )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SH ] |= (instruction_size_data(INSTRUCTION_L_SH ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SLL ] |= (instruction_size_data(INSTRUCTION_L_SLL ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SLL )._type][instruction_information(INSTRUCTION_L_SLL )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SLLI ] |= (instruction_size_data(INSTRUCTION_L_SLLI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SLLI )._type][instruction_information(INSTRUCTION_L_SLLI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SRA ] |= (instruction_size_data(INSTRUCTION_L_SRA ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SRA )._type][instruction_information(INSTRUCTION_L_SRA )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SRAI ] |= (instruction_size_data(INSTRUCTION_L_SRAI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SRAI )._type][instruction_information(INSTRUCTION_L_SRAI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SRL ] |= (instruction_size_data(INSTRUCTION_L_SRL ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SRL )._type][instruction_information(INSTRUCTION_L_SRL )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SRLI ] |= (instruction_size_data(INSTRUCTION_L_SRLI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SRLI )._type][instruction_information(INSTRUCTION_L_SRLI )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SUB ] |= (instruction_size_data(INSTRUCTION_L_SUB ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SUB )._type][instruction_information(INSTRUCTION_L_SUB )._operation]._latence > 0); +// _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SW ] |= (instruction_size_data(INSTRUCTION_L_SW ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SYS ] |= (instruction_size_data(INSTRUCTION_L_SYS ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_SYS )._type][instruction_information(INSTRUCTION_L_SYS )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_TRAP ] |= (instruction_size_data(INSTRUCTION_L_TRAP ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_TRAP )._type][instruction_information(INSTRUCTION_L_TRAP )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_XOR ] |= (instruction_size_data(INSTRUCTION_L_XOR ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_XOR )._type][instruction_information(INSTRUCTION_L_XOR )._operation]._latence > 0); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_XORI ] |= (instruction_size_data(INSTRUCTION_L_XORI ) <= size_general_data) and (_timing[j][instruction_information(INSTRUCTION_L_XORI )._type][instruction_information(INSTRUCTION_L_XORI )._operation]._latence > 0); + + // ORFPX + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_ADD_D ] |= (instruction_size_data(INSTRUCTION_LF_ADD_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_ADD_S ] |= (instruction_size_data(INSTRUCTION_LF_ADD_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_CUST1_D ] |= (instruction_size_data(INSTRUCTION_LF_CUST1_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_CUST1_S ] |= (instruction_size_data(INSTRUCTION_LF_CUST1_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_DIV_D ] |= (instruction_size_data(INSTRUCTION_LF_DIV_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_DIV_S ] |= (instruction_size_data(INSTRUCTION_LF_DIV_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_FTOI_D ] |= (instruction_size_data(INSTRUCTION_LF_FTOI_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_FTOI_S ] |= (instruction_size_data(INSTRUCTION_LF_FTOI_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_ITOF_D ] |= (instruction_size_data(INSTRUCTION_LF_ITOF_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_ITOF_S ] |= (instruction_size_data(INSTRUCTION_LF_ITOF_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_MADD_D ] |= (instruction_size_data(INSTRUCTION_LF_MADD_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_MADD_S ] |= (instruction_size_data(INSTRUCTION_LF_MADD_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_MUL_D ] |= (instruction_size_data(INSTRUCTION_LF_MUL_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_MUL_S ] |= (instruction_size_data(INSTRUCTION_LF_MUL_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_REM_D ] |= (instruction_size_data(INSTRUCTION_LF_REM_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_REM_S ] |= (instruction_size_data(INSTRUCTION_LF_REM_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFEQ_D ] |= (instruction_size_data(INSTRUCTION_LF_SFEQ_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFEQ_S ] |= (instruction_size_data(INSTRUCTION_LF_SFEQ_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFGE_D ] |= (instruction_size_data(INSTRUCTION_LF_SFGE_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFGE_S ] |= (instruction_size_data(INSTRUCTION_LF_SFGE_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFGT_D ] |= (instruction_size_data(INSTRUCTION_LF_SFGT_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFGT_S ] |= (instruction_size_data(INSTRUCTION_LF_SFGT_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFLE_D ] |= (instruction_size_data(INSTRUCTION_LF_SFLE_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFLE_S ] |= (instruction_size_data(INSTRUCTION_LF_SFLE_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFLT_D ] |= (instruction_size_data(INSTRUCTION_LF_SFLT_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFLT_S ] |= (instruction_size_data(INSTRUCTION_LF_SFLT_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFNE_D ] |= (instruction_size_data(INSTRUCTION_LF_SFNE_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SFNE_S ] |= (instruction_size_data(INSTRUCTION_LF_SFNE_S ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SUB_D ] |= (instruction_size_data(INSTRUCTION_LF_SUB_D ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LF_SUB_S ] |= (instruction_size_data(INSTRUCTION_LF_SUB_S ) <= size_general_data) and false; + + // ORVDX + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADD_B ] |= (instruction_size_data(INSTRUCTION_LV_ADD_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADD_H ] |= (instruction_size_data(INSTRUCTION_LV_ADD_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDS_B ] |= (instruction_size_data(INSTRUCTION_LV_ADDS_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDS_H ] |= (instruction_size_data(INSTRUCTION_LV_ADDS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDU_B ] |= (instruction_size_data(INSTRUCTION_LV_ADDU_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDU_H ] |= (instruction_size_data(INSTRUCTION_LV_ADDU_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDUS_B ] |= (instruction_size_data(INSTRUCTION_LV_ADDUS_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ADDUS_H ] |= (instruction_size_data(INSTRUCTION_LV_ADDUS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_EQ_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_EQ_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_EQ_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_EQ_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_GE_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_GE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_GE_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_GE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_GT_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_GT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_GT_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_GT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_LE_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_LE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_LE_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_LE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_LT_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_LT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_LT_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_LT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_NE_B] |= (instruction_size_data(INSTRUCTION_LV_ALL_NE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ALL_NE_H] |= (instruction_size_data(INSTRUCTION_LV_ALL_NE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_AND ] |= (instruction_size_data(INSTRUCTION_LV_AND ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_EQ_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_EQ_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_EQ_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_EQ_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_GE_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_GE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_GE_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_GE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_GT_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_GT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_GT_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_GT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_LE_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_LE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_LE_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_LE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_LT_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_LT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_LT_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_LT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_NE_B] |= (instruction_size_data(INSTRUCTION_LV_ANY_NE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_ANY_NE_H] |= (instruction_size_data(INSTRUCTION_LV_ANY_NE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_AVG_B ] |= (instruction_size_data(INSTRUCTION_LV_AVG_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_AVG_H ] |= (instruction_size_data(INSTRUCTION_LV_AVG_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_EQ_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_EQ_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_EQ_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_EQ_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_GE_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_GE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_GE_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_GE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_GT_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_GT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_GT_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_GT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_LE_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_LE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_LE_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_LE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_LT_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_LT_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_LT_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_LT_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_NE_B] |= (instruction_size_data(INSTRUCTION_LV_CMP_NE_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CMP_NE_H] |= (instruction_size_data(INSTRUCTION_LV_CMP_NE_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CUST1 ] |= (instruction_size_data(INSTRUCTION_LV_CUST1 ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CUST2 ] |= (instruction_size_data(INSTRUCTION_LV_CUST2 ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CUST3 ] |= (instruction_size_data(INSTRUCTION_LV_CUST3 ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_CUST4 ] |= (instruction_size_data(INSTRUCTION_LV_CUST4 ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MADDS_H ] |= (instruction_size_data(INSTRUCTION_LV_MADDS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MAX_B ] |= (instruction_size_data(INSTRUCTION_LV_MAX_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MAX_H ] |= (instruction_size_data(INSTRUCTION_LV_MAX_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MERGE_B ] |= (instruction_size_data(INSTRUCTION_LV_MERGE_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MERGE_H ] |= (instruction_size_data(INSTRUCTION_LV_MERGE_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MIN_B ] |= (instruction_size_data(INSTRUCTION_LV_MIN_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MIN_H ] |= (instruction_size_data(INSTRUCTION_LV_MIN_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MSUBS_H ] |= (instruction_size_data(INSTRUCTION_LV_MSUBS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_MULS_H ] |= (instruction_size_data(INSTRUCTION_LV_MULS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_NAND ] |= (instruction_size_data(INSTRUCTION_LV_NAND ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_NOR ] |= (instruction_size_data(INSTRUCTION_LV_NOR ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_OR ] |= (instruction_size_data(INSTRUCTION_LV_OR ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACK_B ] |= (instruction_size_data(INSTRUCTION_LV_PACK_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACK_H ] |= (instruction_size_data(INSTRUCTION_LV_PACK_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACKS_B ] |= (instruction_size_data(INSTRUCTION_LV_PACKS_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACKS_H ] |= (instruction_size_data(INSTRUCTION_LV_PACKS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACKUS_B] |= (instruction_size_data(INSTRUCTION_LV_PACKUS_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PACKUS_H] |= (instruction_size_data(INSTRUCTION_LV_PACKUS_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_PERM_N ] |= (instruction_size_data(INSTRUCTION_LV_PERM_N ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_RL_B ] |= (instruction_size_data(INSTRUCTION_LV_RL_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_RL_H ] |= (instruction_size_data(INSTRUCTION_LV_RL_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SLL ] |= (instruction_size_data(INSTRUCTION_LV_SLL ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SLL_B ] |= (instruction_size_data(INSTRUCTION_LV_SLL_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SLL_H ] |= (instruction_size_data(INSTRUCTION_LV_SLL_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SRA_B ] |= (instruction_size_data(INSTRUCTION_LV_SRA_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SRA_H ] |= (instruction_size_data(INSTRUCTION_LV_SRA_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SRL ] |= (instruction_size_data(INSTRUCTION_LV_SRL ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SRL_B ] |= (instruction_size_data(INSTRUCTION_LV_SRL_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SRL_H ] |= (instruction_size_data(INSTRUCTION_LV_SRL_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUB_B ] |= (instruction_size_data(INSTRUCTION_LV_SUB_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUB_H ] |= (instruction_size_data(INSTRUCTION_LV_SUB_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBS_B ] |= (instruction_size_data(INSTRUCTION_LV_SUBS_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBS_H ] |= (instruction_size_data(INSTRUCTION_LV_SUBS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBU_B ] |= (instruction_size_data(INSTRUCTION_LV_SUBU_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBU_H ] |= (instruction_size_data(INSTRUCTION_LV_SUBU_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBUS_B ] |= (instruction_size_data(INSTRUCTION_LV_SUBUS_B ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_SUBUS_H ] |= (instruction_size_data(INSTRUCTION_LV_SUBUS_H ) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_UNPACK_B] |= (instruction_size_data(INSTRUCTION_LV_UNPACK_B) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_UNPACK_H] |= (instruction_size_data(INSTRUCTION_LV_UNPACK_H) <= size_general_data) and false; + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_LV_XOR ] |= (instruction_size_data(INSTRUCTION_LV_XOR ) <= size_general_data) and false; + } + + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST1 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST2 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST3 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST4 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST5 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST6 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST7 ] |= ; + //_front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_CUST8 ] |= ; + + // Test if a lsu is connected with this thread + + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LBS ] |= (instruction_size_data(INSTRUCTION_L_LBS ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LBZ ] |= (instruction_size_data(INSTRUCTION_L_LBZ ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LD ] |= (instruction_size_data(INSTRUCTION_L_LD ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LHS ] |= (instruction_size_data(INSTRUCTION_L_LHS ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LHZ ] |= (instruction_size_data(INSTRUCTION_L_LHZ ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LWS ] |= (instruction_size_data(INSTRUCTION_L_LWS ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_LWZ ] |= (instruction_size_data(INSTRUCTION_L_LWZ ) <= size_general_data); + + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SB ] |= (instruction_size_data(INSTRUCTION_L_SB ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SD ] |= (instruction_size_data(INSTRUCTION_L_SD ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SH ] |= (instruction_size_data(INSTRUCTION_L_SH ) <= size_general_data); + _front_end_instruction_implemeted [num_front_end][num_context][INSTRUCTION_L_SW ] |= (instruction_size_data(INSTRUCTION_L_SW ) <= size_general_data); + } + + ALLOC1(_front_end_nb_inst_branch_complete ,uint32_t ,_nb_front_end); + ALLOC2(_front_end_size_decod_queue ,uint32_t ,_nb_front_end,_nb_decod_unit[it1]); + ALLOC2(_front_end_nb_inst_decod ,uint32_t ,_nb_front_end,_nb_decod_unit[it1]); + ALLOC1(_front_end_sum_inst_decod ,uint32_t ,_nb_front_end); + ALLOC2(_front_end_nb_context_select ,uint32_t ,_nb_front_end,_nb_decod_unit[it1]); + ALLOC2(_front_end_context_select_priority ,Tpriority_t ,_nb_front_end,_nb_decod_unit[it1]); + ALLOC2(_front_end_context_select_load_balancing ,Tload_balancing_t,_nb_front_end,_nb_decod_unit[it1]); + + for (uint32_t i=0; i<_nb_front_end; ++i) + { + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end [i]; + uint32_t num_ooo_engine = _link_rename_unit_with_rename_bloc [num_rename_bloc].first; + + _front_end_nb_inst_branch_complete [i] = _nb_inst_branch_complete [num_ooo_engine]; + _front_end_sum_inst_decod [i] = 0; + for (uint32_t j=0; j<_nb_decod_unit[i]; ++j) + { + uint32_t num_decod_bloc=_link_decod_bloc_with_decod_unit[i][j]; + + _front_end_size_decod_queue [i][j] = _size_decod_queue [num_decod_bloc]; + _front_end_nb_inst_decod [i][j] = _nb_inst_decod [num_decod_bloc]; + _front_end_sum_inst_decod [i] += _nb_inst_decod [num_decod_bloc]; + _front_end_nb_context_select [i][j] = _nb_context_select [num_decod_bloc]; + _front_end_context_select_priority [i][j] = _context_select_priority [num_decod_bloc]; + _front_end_context_select_load_balancing [i][j] = _context_select_load_balancing [num_decod_bloc]; + } + } + + ALLOC1(_ooo_engine_nb_front_end ,uint32_t ,_nb_ooo_engine); + + { + std::vector list_front_end [_nb_ooo_engine]; + + // initialization counter + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + _ooo_engine_nb_front_end [i] = 0; + + // scan all front_end + for (uint32_t i=0; i<_nb_front_end; ++i) + { + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end [i]; + uint32_t num_ooo_engine = _link_rename_unit_with_rename_bloc [num_rename_bloc].first; + + // insert a new front_end + _ooo_engine_nb_front_end [num_ooo_engine] ++; // === list_front_end.size() + list_front_end [num_ooo_engine].push_back(i); // No double + } + + log_printf(TRACE,Core,FUNCTION,_(" * translate_ooo_engine_num_front_end")); + + ALLOC2(_translate_ooo_engine_num_front_end ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i];++j) + { + uint32_t num_front_end = list_front_end[i][j]; + + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> %d"),i,j,num_front_end); + _translate_ooo_engine_num_front_end [i][j++] = num_front_end; + } + } + + ALLOC1(_ooo_engine_nb_execute_loop ,uint32_t ,_nb_ooo_engine); + + { + std::vector list_execute_loop [_nb_ooo_engine]; + + // initialization counter + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + _ooo_engine_nb_execute_loop [i] = 0; + + // scan the dispatch table + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + for (uint32_t k=0; k<_nb_read_bloc; ++k) + // have route between this slot's ooo_engine and an read_bloc + if (_table_dispatch [i][j][k]) + { + uint32_t num_execute_loop = _link_read_unit_with_read_bloc [k].first; + + list_execute_loop[i].push_back(num_execute_loop); + } + + sort (list_execute_loop[i].begin(), + list_execute_loop[i].end()); + unique(list_execute_loop[i].begin(), + list_execute_loop[i].end()); + + _ooo_engine_nb_execute_loop [i] = list_execute_loop[i].size(); + } + + log_printf(TRACE,Core,FUNCTION,_(" * translate_ooo_engine_num_execute_loop")); + + ALLOC2(_translate_ooo_engine_num_execute_loop ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j %d"),i,j,num_execute_loop); + _translate_ooo_engine_num_execute_loop [i][j++] = num_execute_loop; + } + } + + ALLOC2(_ooo_engine_nb_context ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + ALLOC2(_ooo_engine_nb_inst_decod ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; + + _ooo_engine_nb_context [i][j] = _nb_context [num_front_end]; + _ooo_engine_nb_inst_decod [i][j] = 0; + + // All context is route to the same rename_unit + for (uint32_t k=0; k<_nb_decod_unit[num_front_end]; ++k) + _ooo_engine_nb_inst_decod [i][j] += _front_end_nb_inst_decod [num_front_end][k]; + } + + ALLOC2(_ooo_engine_nb_inst_execute ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_execute_loop[i]; ++j) + { + uint32_t num_execute_loop = _translate_ooo_engine_num_execute_loop [i][j]; + + // each write_unit manage one instruction per cycle. + _ooo_engine_nb_inst_execute [i][j] = _nb_write_unit [num_execute_loop]; + } + + ALLOC3(_ooo_engine_nb_branch_speculated ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); + ALLOC2(_ooo_engine_link_rename_unit_with_front_end ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; + + for (uint32_t k=0; k<_nb_context[num_front_end];++k) + { + uint32_t num_thread = _link_thread_with_context[num_front_end][k]; + + _ooo_engine_nb_branch_speculated [i][j][k] = _upt_size_queue [num_thread]; + } + + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end [num_front_end]; + uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc[num_rename_bloc].second; + + _ooo_engine_link_rename_unit_with_front_end [i][j] = num_rename_unit; + } + + ALLOC2(_ooo_engine_nb_inst_insert ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC1(_ooo_engine_nb_inst_insert_rob ,uint32_t ,_nb_ooo_engine); + ALLOC2(_ooo_engine_nb_inst_retire ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_rename_select_priority ,Tpriority_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_rename_select_load_balancing ,Tload_balancing_t,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_rename_select_nb_front_end_select ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_nb_general_register ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_nb_special_register ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_nb_reg_free ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_nb_rename_unit_bank ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_ooo_engine_size_read_counter ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + log_printf(TRACE,Core,FUNCTION,_("OOO_Engine [%d] - nb_rename_unit %d"),i,_nb_rename_unit[i]); + _ooo_engine_nb_inst_insert_rob [i] = 0; + + for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) + { + uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit [i][j]; + + log_printf(TRACE,Core,FUNCTION,_(" * [%d] - num_rename_bloc %d, nb_inst_insert %d"),j,num_rename_bloc,_nb_inst_insert[num_rename_bloc]); + + _ooo_engine_nb_inst_insert [i][j] = _nb_inst_insert [num_rename_bloc]; + _ooo_engine_nb_inst_insert_rob [i] += _nb_inst_insert [num_rename_bloc]; + _ooo_engine_nb_inst_retire [i][j] = _nb_inst_retire [num_rename_bloc]; + _ooo_engine_rename_select_priority [i][j] = _rename_select_priority [num_rename_bloc]; + _ooo_engine_rename_select_load_balancing [i][j] = _rename_select_load_balancing [num_rename_bloc]; + _ooo_engine_rename_select_nb_front_end_select [i][j] = _rename_select_nb_front_end_select [num_rename_bloc]; + _ooo_engine_nb_general_register [i][j] = _nb_general_register [num_rename_bloc]; + _ooo_engine_nb_special_register [i][j] = _nb_special_register [num_rename_bloc]; + _ooo_engine_nb_reg_free [i][j] = _nb_reg_free [num_rename_bloc]; + _ooo_engine_nb_rename_unit_bank [i][j] = _nb_rename_unit_bank [num_rename_bloc]; + _ooo_engine_size_read_counter [i][j] = _size_read_counter [num_rename_bloc]; + } + } + + ALLOC4(_network_table_dispatch ,bool ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_execute_loop,_nb_read_unit[it3]); + ALLOC3(_ooo_engine_table_routing ,bool ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]); + ALLOC3(_ooo_engine_table_issue_type ,bool ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_type); + ALLOC2(_list_functionnal_unit_with_rename_unit ,std::vector,_nb_ooo_engine,_nb_rename_unit[it1]); + ALLOC2(_list_load_store_unit_with_rename_unit ,std::vector,_nb_ooo_engine,_nb_rename_unit[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + // Init + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + { + for (uint32_t k=0; k<_nb_execute_loop; ++k) + for (uint32_t l=0; l<_nb_read_unit[k]; ++l) + _network_table_dispatch [i][j][k][l] = false; + for (uint32_t k=0; k<_nb_rename_unit[i]; ++k) + _ooo_engine_table_routing [i][k][j] = false; + for (uint32_t k=0; k<_nb_type; ++k) + _ooo_engine_table_issue_type [i][j][k] = false; + } + + std::vector list_thread_with_inst_issue [_nb_inst_issue[i]]; + + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + { + for (uint32_t k=0; k<_nb_read_bloc; ++k) + // Test if the issue slot is linked with the read_bloc + if (_table_dispatch[i][j][k]) + { + pair_dual x = _link_read_unit_with_read_bloc[i]; + _network_table_dispatch [i][j][x.first][x.second] = true; + + // Test functional unit connected with this read bloc + for (uint32_t l=0; l<_nb_functionnal_unit; ++l) + // the issue slot [j] is connected with the read bloc [k] and it's connected with the functionnal_unit [l] + if (_link_read_bloc_and_functionnal_unit [k][l]) + { + // Scan timing table, test if have an instruction + for (uint32_t m=0; m<_nb_type; ++m) + for (uint32_t n=0; n<_nb_operation; ++n) + if (_timing[l][m][n]._latence > 0) + { + _ooo_engine_table_issue_type [i][j][m] = true; + break; + } + + for (uint32_t m=0; m<_nb_thread; ++m) + { + list_thread_with_inst_issue [j].push_back(m); + + uint32_t num_front_end = _link_context_with_thread [m].first; + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; + uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; + + _list_functionnal_unit_with_rename_unit [i][num_rename_unit].push_back(l); + } + } + + // Test load store unit connected with this read bloc + for (uint32_t l=0; l<_nb_load_store_unit; ++l) + { + _ooo_engine_table_issue_type [i][j][TYPE_MEMORY] = true; +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBS)._type][instruction_information(INSTRUCTION_L_LBS)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LBZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LBZ)._type][instruction_information(INSTRUCTION_L_LBZ)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LD )._type][instruction_information(INSTRUCTION_L_LD )._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHS)._type][instruction_information(INSTRUCTION_L_LHS)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LHZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LHZ)._type][instruction_information(INSTRUCTION_L_LHZ)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWS)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWS)._type][instruction_information(INSTRUCTION_L_LWS)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_LWZ)._type] |= (_timing[l][instruction_information(INSTRUCTION_L_LWZ)._type][instruction_information(INSTRUCTION_L_LWZ)._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SB )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SB )._type][instruction_information(INSTRUCTION_L_SB )._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SD )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SD )._type][instruction_information(INSTRUCTION_L_SD )._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SH )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SH )._type][instruction_information(INSTRUCTION_L_SH )._operation]._latence > 0); +// _ooo_engine_table_issue_type [i][j][instruction_information(INSTRUCTION_L_SW )._type] |= (_timing[l][instruction_information(INSTRUCTION_L_SW )._type][instruction_information(INSTRUCTION_L_SW )._operation]._latence > 0); + + if (_link_read_bloc_and_load_store_unit [k][l]) + // the issue slot [j] is connected with the read bloc [k] and it's connected with the load_store_unit [l] + for (uint32_t m=0; m<_nb_thread; ++m) + { + list_thread_with_inst_issue [j].push_back(m); + + + uint32_t num_front_end = _link_context_with_thread [m].first; + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end[num_front_end]; + uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; + + _list_load_store_unit_with_rename_unit [i][num_rename_unit].push_back(l); + } + } + } + // sort and erase duplicate value + + sort (list_thread_with_inst_issue [j].begin(), + list_thread_with_inst_issue [j].end()); + unique(list_thread_with_inst_issue [j].begin(), + list_thread_with_inst_issue [j].end()); + } + + log_printf(TRACE,Core,FUNCTION,_(" * ooo_engine_table_routing [%d]"),i); + for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) + { + // sort and erase duplicate value + sort (_list_load_store_unit_with_rename_unit [i][j].begin(), + _list_load_store_unit_with_rename_unit [i][j].end()); + unique(_list_load_store_unit_with_rename_unit [i][j].begin(), + _list_load_store_unit_with_rename_unit [i][j].end()); + sort (_list_functionnal_unit_with_rename_unit [i][j].begin(), + _list_functionnal_unit_with_rename_unit [i][j].end()); + unique(_list_functionnal_unit_with_rename_unit [i][j].begin(), + _list_functionnal_unit_with_rename_unit [i][j].end()); + + uint32_t num_rename_bloc = _link_rename_bloc_with_rename_unit[i][j]; + + for (uint32_t k=0; k<_nb_front_end; ++k) + // test if this front_end is connected with this rename_bloc + if (_link_rename_bloc_with_front_end[k] == num_rename_bloc) + // the front end is connected with rename_bloc. Now test all slot issue that it can accepted this front_end + for (uint32_t l=0; l<_nb_inst_issue[i]; ++l) + for (std::vector::iterator it = list_thread_with_inst_issue [l].begin(); + it != list_thread_with_inst_issue [l].end(); + ++it) + // Test if the this is in front_end [k] + if (_link_context_with_thread[*it].first == k) + { + _ooo_engine_table_routing [i][j][l] |= true; + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> true"),j,l); + } + } + } + + ALLOC2(_ooo_engine_nb_load_store_unit ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) + _ooo_engine_nb_load_store_unit [i][j] = _list_load_store_unit_with_rename_unit [i][j].size(); + + ALLOC3(_ooo_engine_size_store_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); + ALLOC3(_ooo_engine_size_load_queue ,uint32_t ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); + ALLOC3(_ooo_engine_link_load_store_unit_with_context ,uint32_t ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + for (uint32_t j=0; j<_nb_rename_unit[i]; ++j) + for (uint32_t k=0; k<_list_load_store_unit_with_rename_unit [i][j].size(); ++k) + { + uint32_t num_load_store_unit = _list_load_store_unit_with_rename_unit[i][j][k]; + + _ooo_engine_size_store_queue [i][j][k] = _size_store_queue[num_load_store_unit]; + _ooo_engine_size_load_queue [i][j][k] = _size_load_queue [num_load_store_unit]; + } + + for (uint32_t j=0; j<_ooo_engine_nb_front_end[i]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][j]; + uint32_t num_rename_bloc = _link_rename_bloc_with_front_end [num_front_end]; + uint32_t num_rename_unit = _link_rename_unit_with_rename_bloc [num_rename_bloc].second; + + std::vector list_lsq = _list_load_store_unit_with_rename_unit[i][num_rename_unit]; + + for (uint32_t k=0; k<_ooo_engine_nb_context[i][j]; ++k) + { + uint32_t num_thread = _link_thread_with_context [num_front_end][k]; + uint32_t num_load_store_unit = _link_load_store_unit_with_thread [num_thread]; + uint32_t num_lsq; + + // Find correspondence between load_store_unit and num_load_store_unit in rename_unit + for (num_lsq=0; num_lsq,_nb_execute_loop); + ALLOC1(_list_front_end_with_execute_loop ,std::vector,_nb_execute_loop); + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + for (uint32_t j=0; j<_ooo_engine_nb_execute_loop[i]; ++j) + { + uint32_t num_execute_loop = _translate_ooo_engine_num_execute_loop [i][j]; + + _list_ooo_engine_with_execute_loop [num_execute_loop].push_back(i); + + for (uint32_t k=0; k<_ooo_engine_nb_front_end[i]; ++k) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [i][k]; + + _list_front_end_with_execute_loop [num_execute_loop].push_back(num_front_end); + } + } + } + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + sort (_list_ooo_engine_with_execute_loop[i].begin(), + _list_ooo_engine_with_execute_loop[i].end()); + unique(_list_ooo_engine_with_execute_loop[i].begin(), + _list_ooo_engine_with_execute_loop[i].end()); + + sort (_list_front_end_with_execute_loop [i].begin(), + _list_front_end_with_execute_loop [i].end()); + unique(_list_front_end_with_execute_loop [i].begin(), + _list_front_end_with_execute_loop [i].end()); + } + + +#if (DEBUG >= DEBUG_TRACE) + + log_printf(TRACE,Core,FUNCTION,_("list_ooo_engine_with_execute_loop")); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_list_ooo_engine_with_execute_loop[i].size(); ++j) + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> %d"),i,j,_list_ooo_engine_with_execute_loop[i][j]); + + log_printf(TRACE,Core,FUNCTION,_("list_front_end_with_execute_loop")); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_list_front_end_with_execute_loop[i].size(); ++j) + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d] -> %d"),i,j,_list_front_end_with_execute_loop[i][j]); + +#endif + + ALLOC1(_execute_loop_nb_front_end ,uint32_t,_nb_execute_loop); + ALLOC1(_execute_loop_nb_context ,uint32_t,_nb_execute_loop); + ALLOC1(_execute_loop_nb_ooo_engine ,uint32_t,_nb_execute_loop); + ALLOC1(_execute_loop_nb_packet ,uint32_t,_nb_execute_loop); + ALLOC1(_execute_loop_nb_thread ,uint32_t,_nb_execute_loop); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + log_printf(TRACE,Core,FUNCTION,_("execute_loop [%d] information :"),i); + + _execute_loop_nb_ooo_engine [i] = _list_ooo_engine_with_execute_loop[i].size(); + + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_ooo_engine : %d"),_execute_loop_nb_ooo_engine [i]); + + uint32_t max_nb_front_end = 0; + uint32_t max_nb_context = 0; + uint32_t max_size_rob = 0; + + for (std::vector::iterator it=_list_ooo_engine_with_execute_loop[i].begin(); + it!=_list_ooo_engine_with_execute_loop[i].end(); + ++it) + { + uint32_t num_ooo_engine = *it; + + max_size_rob = std::max(max_size_rob,_size_re_order_buffer[num_ooo_engine]); + max_nb_front_end = std::max(max_nb_front_end,_ooo_engine_nb_front_end[num_ooo_engine]); + + for (uint32_t j=0; j<_ooo_engine_nb_front_end[num_ooo_engine]; ++j) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [num_ooo_engine][j]; + + max_nb_context = std::max(max_nb_context,_nb_context[num_front_end]); + } + } + _execute_loop_nb_front_end [i] = max_nb_front_end; + _execute_loop_nb_context [i] = max_nb_context ; + _execute_loop_nb_packet [i] = max_size_rob ; + + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_front_end : %d"),_execute_loop_nb_front_end [i]); + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_context : %d"),_execute_loop_nb_context [i]); + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_packet : %d"),_execute_loop_nb_packet [i]); + + _execute_loop_nb_thread [i] = get_nb_thread(_execute_loop_nb_context [i], + _execute_loop_nb_front_end [i], + _execute_loop_nb_ooo_engine [i]); + + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_thread : %d"),_execute_loop_nb_thread [i]); + } + + ALLOC2(_translate_execute_loop_num_ooo_engine ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + { + _translate_execute_loop_num_ooo_engine [i][j] = _list_ooo_engine_with_execute_loop[i][j]; + } + + ALLOC2(_execute_loop_size_read_queue ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]); + ALLOC2(_execute_loop_size_reservation_station ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]); + ALLOC2(_execute_loop_nb_inst_retire ,uint32_t,_nb_execute_loop,_nb_read_unit[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_read_unit[i]; ++j) + { + uint32_t num_read_bloc = _link_read_bloc_with_read_unit [i][j]; + + _execute_loop_size_read_queue [i][j] = _size_read_queue [num_read_bloc]; + _execute_loop_size_reservation_station [i][j] = _size_reservation_station [num_read_bloc]; + _execute_loop_nb_inst_retire [i][j] = _nb_inst_retire [num_read_bloc]; + } + + ALLOC2(_execute_loop_nb_inst_functionnal_unit ,uint32_t,_nb_execute_loop,_execute_loop_nb_functionnal_unit[it1]); + ALLOC4(_execute_loop_timing ,multi_execute_loop::execute_loop::execute_timing_t + ,_nb_execute_loop,_execute_loop_nb_functionnal_unit[it1],_nb_type,_nb_operation); + ALLOC2(_execute_loop_is_load_store_unit ,bool ,_nb_execute_loop,_nb_execute_unit[it1]); + ALLOC2(_execute_loop_translate_num_execute_unit ,uint32_t,_nb_execute_loop,_nb_execute_unit[it1]); + +// for (uint32_t i=0; i<_nb_execute_loop; ++i) +// { +// for (uint32_t j=0; j<_nb_execute_unit [i]; ++j) +// { +// _execute_loop_is_load_store_unit [i][j] = false; +// _execute_loop_translate_num_execute_unit [i][j] = 0; +// } +// for (uint32_t j=0; j<_execute_loop_nb_functionnal_unit[i]; ++j) +// for (uint32_t k=0; k<_nb_type; ++k) +// for (uint32_t l=0; l<_nb_operation; ++l) +// _execute_loop_timing [i][j][k][l]._delay = _execute_loop_timing [i][j][k][l]._latence = 0; +// } + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + uint32_t num_lsu = 0; + uint32_t num_fu = 0; + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + uint32_t num_functionnal_unit = _link_functionnal_unit_with_execute_unit [i][j]; + uint32_t num_load_store_unit = _link_load_store_unit_with_execute_unit [i][j]; + + bool is_lsu = (num_load_store_unit != _nb_load_store_unit); + + _execute_loop_is_load_store_unit [i][j] = is_lsu; + + if (is_lsu) + { + // update translation + _execute_loop_translate_num_execute_unit [i][j] = num_lsu; + num_lsu ++; + } + else + { + // update translation + _execute_loop_translate_num_execute_unit [i][j] = num_fu; + num_fu ++; + + // timing information + _execute_loop_nb_inst_functionnal_unit [i][j] = _nb_inst_functionnal_unit [num_functionnal_unit]; + + for (uint32_t k=0; k<_nb_type; ++k) + for (uint32_t l=0; l<_nb_operation; ++l) + { + //log_printf(TRACE,Core,FUNCTION,_("execute_loop_timing [%d][%d][%d][%d] = timing [%d][%d][%d]"),i,j,k,l,num_functionnal_unit,k,l); + _execute_loop_timing [i][j][k][l] = _timing [num_functionnal_unit][k][l]; + } + +// // is not a load store unit +// for (uint32_t k=0; k<_nb_operation; ++k) +// _execute_loop_timing [i][j][TYPE_MEMORY][k]._delay = _execute_loop_timing [i][j][TYPE_MEMORY][k]._latence = 0; + } + } + } + + ALLOC2(_execute_loop_size_store_queue ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_size_load_queue ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_size_speculative_access_queue ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_nb_port_check ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_speculative_load ,multi_execute_loop::execute_loop::Tspeculative_load_t + ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_nb_bypass_memory ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_nb_cache_port ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_execute_loop_nb_inst_memory ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_load_store_unit[i]; ++j) + { + uint32_t num_load_store_unit = _list_load_store_unit_with_execute_unit [i][j]; + + log_printf(TRACE,Core,FUNCTION,_(" * execute_loop_nb_load_store_unit [%d][%d] : %d"),i,j,num_load_store_unit); + log_printf(TRACE,Core,FUNCTION,_(" * nb_bypass_memory : %d"),_nb_bypass_memory[num_load_store_unit]); + + _execute_loop_size_store_queue [i][j] = _size_store_queue [num_load_store_unit]; + _execute_loop_size_load_queue [i][j] = _size_load_queue [num_load_store_unit]; + _execute_loop_size_speculative_access_queue [i][j] = _size_speculative_access_queue [num_load_store_unit]; + _execute_loop_nb_port_check [i][j] = _nb_port_check [num_load_store_unit]; + _execute_loop_speculative_load [i][j] = _speculative_load [num_load_store_unit]; + _execute_loop_nb_bypass_memory [i][j] = _nb_bypass_memory [num_load_store_unit]; + _execute_loop_nb_cache_port [i][j] = _nb_cache_port [num_load_store_unit]; + _execute_loop_nb_inst_memory [i][j] = _nb_inst_memory [num_load_store_unit]; + } + + ALLOC2(_execute_loop_size_write_queue ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]); + ALLOC2(_execute_loop_size_execute_queue ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]); + ALLOC2(_execute_loop_nb_bypass_write ,uint32_t,_nb_execute_loop,_nb_write_unit[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_write_unit[i]; ++j) + { + uint32_t num_write_bloc = _link_write_bloc_with_write_unit [i][j]; + + _execute_loop_size_write_queue [i][j] = _size_write_queue [num_write_bloc]; + _execute_loop_size_execute_queue [i][j] = _size_execute_queue [num_write_bloc]; + _execute_loop_nb_bypass_write [i][j] = _nb_bypass_write [num_write_bloc]; + } + + ALLOC2(_execute_loop_nb_general_register ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + ALLOC2(_execute_loop_nb_special_register ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + ALLOC2(_execute_loop_nb_inst_insert_rob ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + ALLOC2(_execute_loop_nb_inst_retire_rob ,uint32_t,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_ooo_engine[i]; ++j) + { + uint32_t num_ooo_engine = _list_ooo_engine_with_execute_loop[i][j]; + + // sum number of general register + uint32_t gpr_reg = *std::max_element(_ooo_engine_nb_general_register[num_ooo_engine], + _ooo_engine_nb_general_register[num_ooo_engine]+_nb_rename_unit[num_ooo_engine]); + + gpr_reg *= _nb_rename_unit[num_ooo_engine]; + + _execute_loop_nb_general_register [i][j] = gpr_reg; + + // sum number of special register + uint32_t spr_reg = *std::max_element(_ooo_engine_nb_special_register[num_ooo_engine], + _ooo_engine_nb_special_register[num_ooo_engine]+_nb_rename_unit[num_ooo_engine]); + + spr_reg *= _nb_rename_unit[num_ooo_engine]; + + _execute_loop_nb_special_register [i][j] = spr_reg; + + + uint32_t insert = 0; + uint32_t retire = 0; + + for (uint32_t k=0; k<_nb_rename_unit[num_ooo_engine]; ++k) + { + insert = _ooo_engine_nb_inst_insert [num_ooo_engine][k]; + retire = _ooo_engine_nb_inst_retire [num_ooo_engine][k]; + } + + _execute_loop_nb_inst_insert_rob [i][j] = insert; + _execute_loop_nb_inst_retire_rob [i][j] = retire; + } + + ALLOC2(_execute_loop_nb_execute_unit_port ,uint32_t,_nb_execute_loop,_nb_execute_unit[it1]); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + uint32_t num_functionnal_unit = _link_functionnal_unit_with_execute_unit [i][j]; + uint32_t num_load_store_unit = _link_load_store_unit_with_execute_unit [i][j]; + + if (num_functionnal_unit != _nb_functionnal_unit) + _execute_loop_nb_execute_unit_port [i][j] = _nb_inst_functionnal_unit [num_functionnal_unit]; + else + { + _execute_loop_nb_execute_unit_port [i][j] = _nb_inst_memory [num_load_store_unit]; + +#ifdef DEBUG_TEST + if (num_load_store_unit == _nb_load_store_unit) + throw ERRORMORPHEO(FUNCTION,_("execute_unit is not a functional unit and load store unit.")); +#endif + } + } + + ALLOC4(_execute_loop_read_unit_to_execution_unit_table_routing ,bool ,_nb_execute_loop,_nb_read_unit[it1],_nb_execute_unit[it1],_execute_loop_nb_execute_unit_port[it1][it2]); + + log_printf(TRACE,Core,FUNCTION,_("execute_loop_read_unit_to_execution_unit_table_routing [execute_loop][read_unit][execute_unit][execute_unit_port]")); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + uint32_t num_functionnal_unit = _link_functionnal_unit_with_execute_unit [i][j]; + uint32_t num_load_store_unit = _link_load_store_unit_with_execute_unit [i][j]; + + bool is_lsu = (num_load_store_unit != _nb_load_store_unit); + + for (uint32_t l=0; l<_nb_read_unit[i];++l) + { + uint32_t num_read_bloc = _link_read_bloc_with_read_unit [i][l]; + bool link = false; + + if (is_lsu) + link = _link_read_bloc_and_load_store_unit [num_read_bloc][num_load_store_unit]; + else + link = _link_read_bloc_and_functionnal_unit [num_read_bloc][num_functionnal_unit]; + + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d][all] -> %d"),i,l,j,link); + + for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) + _execute_loop_read_unit_to_execution_unit_table_routing [i][l][j][k] = link; + } + } + + ALLOC4(_execute_loop_execution_unit_to_write_unit_table_routing,bool ,_nb_execute_loop,_nb_execute_unit[it1],_execute_loop_nb_execute_unit_port[it1][it2],_nb_write_unit[it1]); + + log_printf(TRACE,Core,FUNCTION,_("execute_loop_execution_unit_to_write_unit_table_routing [execute_loop][execute_unit][execute_unit_port][write_unit]")); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + uint32_t num_functionnal_unit = _link_functionnal_unit_with_execute_unit [i][j]; + uint32_t num_load_store_unit = _link_load_store_unit_with_execute_unit [i][j]; + + bool is_lsu = (num_load_store_unit != _nb_load_store_unit); + + for (uint32_t l=0; l<_nb_write_unit[i];++l) + { + uint32_t num_write_bloc = _link_write_bloc_with_write_unit [i][l]; + bool link = false; + + if (is_lsu) + link = _link_write_bloc_and_load_store_unit [num_write_bloc][num_load_store_unit]; + else + link = _link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]; + + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][all][%d] -> %d"),i,j,l,link); + + for (uint32_t k=0; k<_execute_loop_nb_execute_unit_port [i][j]; ++k) + _execute_loop_execution_unit_to_write_unit_table_routing [i][j][k][l] = link; + } + } + + ALLOC3(_execute_loop_read_unit_to_execution_unit_table_thread ,bool ,_nb_execute_loop,_nb_execute_unit[it1],_execute_loop_nb_thread[it1]); + ALLOC3(_execute_loop_execution_unit_to_write_unit_table_thread ,bool ,_nb_execute_loop,_nb_write_unit[it1],_execute_loop_nb_thread [it1]); + + log_printf(TRACE,Core,FUNCTION,_("execute_loop_read_unit_to_execution_unit_table_thread")); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + for (uint32_t k=0; k<_execute_loop_nb_thread[i]; ++k) + { + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + _execute_loop_read_unit_to_execution_unit_table_thread [i][j][k] = false; + for (uint32_t j=0; j<_nb_write_unit[i]; ++j) + _execute_loop_execution_unit_to_write_unit_table_thread [i][j][k] = false; + } + + for (uint32_t j=0; j<_nb_execute_unit[i]; ++j) + { + uint32_t num_functionnal_unit = _link_functionnal_unit_with_execute_unit [i][j]; + uint32_t num_load_store_unit = _link_load_store_unit_with_execute_unit [i][j]; + + bool is_lsu = (num_load_store_unit != _nb_load_store_unit); + + // Test this execute_unit + for (uint32_t k=0; k<_nb_thread; ++k) + { + // Have a link ? + bool have_link = (is_lsu)?(_link_load_store_unit_with_thread [k] == num_load_store_unit):(_link_thread_and_functionnal_unit [k][num_functionnal_unit]); + + if (have_link) + { + uint32_t num_thread = execute_loop_get_num_thread (i,k); + _execute_loop_read_unit_to_execution_unit_table_thread [i][j][num_thread] = true; + log_printf(TRACE,Core,FUNCTION,_(" [%d][%d][%d] -> Ok"),i,j,num_thread); + + } + } + + for (uint32_t k=0; k<_nb_write_unit[i]; ++k) + { + uint32_t num_write_bloc = _link_write_bloc_with_write_unit[i][k]; + bool have_link = (is_lsu)?(_link_write_bloc_and_load_store_unit [num_write_bloc][num_load_store_unit]):(_link_write_bloc_and_functionnal_unit [num_write_bloc][num_functionnal_unit]); + + if (have_link) + for (uint32_t l=0; l<_execute_loop_nb_thread [i]; ++l) + _execute_loop_execution_unit_to_write_unit_table_thread [i][k][l] |= _execute_loop_read_unit_to_execution_unit_table_thread [i][j][l]; + } + } + } + + ALLOC2(_icache_access_size_packet_id,uint32_t,_nb_front_end,_nb_context[it1]); + ALLOC2(_icache_access_table_routing ,uint32_t,_nb_front_end,_nb_context[it1]); + + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i]; ++j) + { + uint32_t num_thread = _link_thread_with_context [i][j]; + + _icache_access_size_packet_id [i][j] = log2(_front_end_size_ifetch_queue[i][j]); + _icache_access_table_routing [i][j] = _link_icache_port_with_thread [num_thread]; + } + + ALLOC1(_icache_nb_instruction ,uint32_t,_nb_icache_port); + + for (uint32_t i=0; i<_nb_icache_port; ++i) + _icache_nb_instruction [i] = 0; + for (uint32_t i=0; i<_nb_front_end; i++) + for (uint32_t j=0; j<_nb_context[i]; j++) + { + uint32_t port = _icache_access_table_routing [i][j]; + + // Take the greater + if (_icache_nb_instruction[port] < _front_end_nb_inst_fetch [i][j]) + _icache_nb_instruction[port] = _front_end_nb_inst_fetch [i][j]; + } + + ALLOC2(_dcache_access_size_thread_id,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC2(_dcache_access_size_packet_id,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + ALLOC3(_dcache_access_table_routing ,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_execute_loop_nb_cache_port[it1][it2]); + + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_load_store_unit[i]; ++j) + { + uint32_t num_load_store_unit = _list_load_store_unit_with_execute_unit [i][j]; + + for (uint32_t k=0; k<_execute_loop_nb_cache_port [i][j]; ++k) + _dcache_access_table_routing [i][j][k] = _link_dcache_port_with_load_store_unit [num_load_store_unit][k]; + + _dcache_access_size_thread_id [i][j] = (log2(_execute_loop_nb_context [i]) + + log2(_execute_loop_nb_front_end [i]) + + log2(_execute_loop_nb_ooo_engine [i])); + + // max size +1 (+1 to add a bit to select the queue) + _dcache_access_size_packet_id [i][j] = log2(std::max(_size_store_queue[num_load_store_unit], + _size_load_queue [num_load_store_unit]))+1; + } + + ALLOC1(_dcache_access_nb_context ,uint32_t,_nb_execute_loop); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + _dcache_access_nb_context [i] = 1<(_dcache_access_size_thread_id [i],_execute_loop_nb_load_store_unit[i]); + + ALLOC3(_dcache_access_translate_load_store_unit_to_thread,uint32_t,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_dcache_access_nb_context[it1]); + + // parameters depends + _size_context_id = log2(max(_nb_context,_nb_front_end)); + _size_front_end_id = log2(_nb_front_end); + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_execute_loop_nb_load_store_unit[i]; ++j) + { + uint32_t num_load_store_unit = _list_load_store_unit_with_execute_unit [i][j]; + + uint32_t num_thread; + for (num_thread = 0; num_thread<_nb_thread; ++num_thread) + if (_link_load_store_unit_with_thread [num_thread] == num_load_store_unit) + break; + +#ifdef DEBUG_TEST + if (num_thread == _nb_thread) + throw ERRORMORPHEO(FUNCTION,toString(_("Load_store_unit [%d] is not link with a thread.\n"),num_load_store_unit)); +#endif + // init with an invalid thread_id + for (uint32_t k=0; k<_dcache_access_nb_context [i]; ++k) + _dcache_access_translate_load_store_unit_to_thread [i][j][k] = _nb_thread; + + // cf Load_store_unit : create thread_id + // dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) | + // (front_end_id <<(_param->_size_context_id)) | + // (context_id)); + + for (std::vector::iterator it=_list_ooo_engine_with_execute_loop[i].begin(); + it!=_list_ooo_engine_with_execute_loop[i].end(); + ++it) + { + uint32_t num_ooo_engine = *it; + for (uint32_t x=0; x<_ooo_engine_nb_front_end[num_ooo_engine]; ++x) + { + uint32_t num_front_end = _translate_ooo_engine_num_front_end [num_ooo_engine][x]; + + for (uint32_t num_context = 0; num_context < _nb_context[num_front_end]; ++num_context) + { + uint32_t num_thread = _link_thread_with_context [num_front_end][num_context]; + + uint32_t index = ((num_ooo_engine<<(_size_context_id + _size_front_end_id )) | + (num_front_end <<(_size_context_id)) | + (num_context)); + + _dcache_access_translate_load_store_unit_to_thread [i][j][index] = num_thread; + } + } + } + } + + // parameters depends + _size_ooo_engine_id = log2(_nb_ooo_engine); + _size_instruction_address = size_general_data-2; + _size_data_address = size_general_data; + _size_nb_inst_decod = log2(max(_size_decod_queue,_nb_decod_bloc ))+1; + _size_nb_inst_commit = log2(max(_size_re_order_buffer,_nb_ooo_engine))+1; + _size_depth = log2(max(_upt_size_queue,_nb_thread)); + _size_ifetch_queue_ptr = log2(max(_size_ifetch_queue,_nb_thread)); + _size_inst_ifetch_ptr = log2(max(_nb_inst_fetch,_nb_thread)); + _size_rob_ptr = _size_nb_inst_commit; // nb_rob_bank must be a multiple of size_rob + _size_load_queue_ptr = log2(max(_size_load_queue ,_nb_load_store_unit)); + _size_store_queue_ptr = log2(max(_size_store_queue,_nb_load_store_unit)); + _size_general_data = size_general_data; + _size_special_data = size_special_data; + _size_general_register = log2(max(_nb_general_register,_nb_rename_bloc)); + _size_special_register = log2(max(_nb_special_register,_nb_rename_bloc)); + + _have_port_context_id = _size_context_id > 0; + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_ooo_engine_id = _size_ooo_engine_id > 0; + _have_port_depth = _size_depth > 0; + _have_port_ifetch_queue_ptr = _size_ifetch_queue_ptr > 0; + _have_port_inst_ifetch_ptr = _size_inst_ifetch_ptr > 0; + _have_port_rob_ptr = _size_rob_ptr > 0; + _have_port_load_queue_ptr = _size_load_queue_ptr > 0; + + // interface parameters + _size_icache_thread_id = log2(_nb_thread); +// _size_icache_thread_id = log2(_nb_front_end) + log2(max(_nb_context,_nb_front_end)); + _size_icache_packet_id = _size_ifetch_queue_ptr; +// _size_icache_packet_id = max(_icache_access_size_packet_id,_nb_front_end, _nb_context); + _size_icache_address = _size_instruction_address; + _have_port_icache_thread_id = _size_icache_thread_id > 0; + _have_port_icache_packet_id = _size_icache_packet_id > 0; + _size_dcache_thread_id = _size_icache_thread_id; +// _size_dcache_thread_id = (log2(_nb_execute_loop) + +// log2(max(_execute_loop_nb_load_store_unit, _nb_execute_loop)) + +// log2(max(_execute_loop_nb_cache_port, _nb_execute_loop, _execute_loop_nb_load_store_unit)) + +// max(_dcache_access_size_packet_id , _nb_execute_loop, _execute_loop_nb_load_store_unit)); + _size_dcache_packet_id = max(_dcache_access_size_packet_id, _nb_execute_loop, _execute_loop_nb_load_store_unit); + _size_dcache_address = _size_data_address; + _size_dcache_data = _size_general_data; + + _have_port_dcache_thread_id = _size_dcache_thread_id > 0; + _have_port_dcache_packet_id = _size_dcache_packet_id > 0; // always 1 + + + _param_front_end = new core::multi_front_end::front_end::Parameters * [_nb_front_end]; + + for (uint32_t i=0; i<_nb_front_end; ++i) + _param_front_end [i]= new core::multi_front_end::front_end::Parameters + ( + _nb_context [i], + _nb_decod_unit [i], + _size_general_data , + _get_custom_information , + _front_end_size_ifetch_queue [i], + _front_end_nb_inst_fetch [i], + _front_end_instruction_implemeted [i], + _front_end_link_decod_unit_with_context [i], + _front_end_size_decod_queue [i], + _front_end_nb_inst_decod [i], + _front_end_nb_context_select [i], + _front_end_context_select_priority [i], + _front_end_context_select_load_balancing[i], + _nb_inst_branch_predict [i], + _nb_inst_branch_decod [i], + _nb_inst_branch_update [i], + _front_end_nb_inst_branch_complete [i], + _btb_size_queue [i], + _btb_associativity [i], + _btb_size_counter [i], + _btb_victim_scheme [i], + _dir_predictor_scheme [i], + _dir_have_bht [i], + _dir_bht_size_shifter [i], + _dir_bht_nb_shifter [i], + _dir_have_pht [i], + _dir_pht_size_counter [i], + _dir_pht_nb_counter [i], + _dir_pht_size_address_share [i], + _front_end_ras_size_queue [i], + _front_end_upt_size_queue [i], + _size_nb_inst_commit + ); + + _param_ooo_engine = new core::multi_ooo_engine::ooo_engine::Parameters * [_nb_ooo_engine]; + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + _param_ooo_engine [i] = new core::multi_ooo_engine::ooo_engine::Parameters + ( + _ooo_engine_nb_front_end [i], + _ooo_engine_nb_context [i], + _nb_rename_unit [i], + _ooo_engine_nb_execute_loop [i], + _ooo_engine_nb_inst_decod [i], + _ooo_engine_nb_inst_insert [i], + _ooo_engine_nb_inst_retire [i], + _nb_inst_issue [i], + _ooo_engine_nb_inst_execute [i], + _nb_inst_reexecute [i], + _nb_inst_commit [i], + _nb_inst_branch_complete [i], + _ooo_engine_nb_branch_speculated [i], + _nb_rename_unit_select [i], + _nb_execute_loop_select [i], + _size_general_data , + _size_special_data , + _ooo_engine_link_rename_unit_with_front_end [i], + _size_re_order_buffer [i], + _nb_re_order_buffer_bank [i], + _commit_priority [i], + _commit_load_balancing [i], + _size_issue_queue [i], + _nb_issue_queue_bank [i], + _issue_priority [i], + _issue_load_balancing [i], + _ooo_engine_table_routing [i], + _ooo_engine_table_issue_type [i], + _size_reexecute_queue [i], + _reexecute_priority [i], + _reexecute_load_balancing [i], + _ooo_engine_rename_select_priority [i], + _ooo_engine_rename_select_load_balancing [i], + _ooo_engine_rename_select_nb_front_end_select [i], + _ooo_engine_nb_general_register [i], + _ooo_engine_nb_special_register [i], + _ooo_engine_nb_reg_free [i], + _ooo_engine_nb_rename_unit_bank [i], + _ooo_engine_size_read_counter [i], + _ooo_engine_nb_load_store_unit [i], + _ooo_engine_size_store_queue [i], + _ooo_engine_size_load_queue [i], + _ooo_engine_link_load_store_unit_with_context [i], + _ooo_engine_implement_group [i] + ); + + _param_execute_loop = new core::multi_execute_loop::execute_loop::Parameters * [_nb_execute_loop]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + _param_execute_loop [i] = new core::multi_execute_loop::execute_loop::Parameters + ( + _nb_read_unit [i], + _execute_loop_nb_functionnal_unit [i], + _execute_loop_nb_load_store_unit [i], + _nb_write_unit [i], + + _execute_loop_nb_context [i], + _execute_loop_nb_front_end [i], + _execute_loop_nb_ooo_engine [i], + _execute_loop_nb_packet [i], + _size_general_data , + _size_special_data , + + _execute_loop_size_read_queue [i], + _execute_loop_size_reservation_station [i], + _execute_loop_nb_inst_retire [i], + + _execute_loop_nb_inst_functionnal_unit [i], + _execute_loop_timing [i], + _get_custom_information , + + _execute_loop_size_store_queue [i], + _execute_loop_size_load_queue [i], + _execute_loop_size_speculative_access_queue [i], + _execute_loop_nb_port_check [i], + _execute_loop_speculative_load [i], + _execute_loop_nb_bypass_memory [i], + _execute_loop_nb_cache_port [i], + _execute_loop_nb_inst_memory [i], + + _execute_loop_size_write_queue [i], + _execute_loop_size_execute_queue [i], + _execute_loop_nb_bypass_write [i], + + _nb_gpr_bank [i], + _nb_gpr_port_read_by_bank [i], + _nb_gpr_port_write_by_bank [i], + _nb_spr_bank [i], + _nb_spr_port_read_by_bank [i], + _nb_spr_port_write_by_bank [i], + _execute_loop_nb_general_register [i], + _execute_loop_nb_special_register [i], + _execute_loop_nb_inst_insert_rob [i], + _execute_loop_nb_inst_retire_rob [i], + + _execution_unit_to_write_unit_priority [i], + _execute_loop_execution_unit_to_write_unit_table_routing [i], + _execute_loop_execution_unit_to_write_unit_table_thread [i], + + _read_unit_to_execution_unit_priority [i], + _execute_loop_read_unit_to_execution_unit_table_routing [i], + _execute_loop_read_unit_to_execution_unit_table_thread [i], + + _execute_loop_is_load_store_unit [i], + _execute_loop_translate_num_execute_unit [i] + ); + + _param_icache_access = new core::icache_access::Parameters + ( + _nb_thread , + _nb_front_end , + _nb_context , + _nb_icache_port , + _size_icache_address , + _size_icache_thread_id , + _size_icache_packet_id , + _front_end_nb_inst_fetch , + _icache_access_size_packet_id, + _icache_access_table_routing , + _icache_port_priority , + _icache_port_load_balancing , + _link_thread_with_context + ); + + _param_dcache_access = new core::dcache_access::Parameters + ( + _nb_thread , + _nb_execute_loop , + _execute_loop_nb_load_store_unit , + _dcache_access_nb_context , + _execute_loop_nb_cache_port , + _nb_dcache_port , + _size_dcache_address , + _size_dcache_data , + _size_dcache_thread_id , + _size_dcache_packet_id , + _dcache_access_size_thread_id , + _dcache_access_size_packet_id , + _dcache_access_table_routing , + _dcache_port_priority , + _dcache_port_load_balancing , + _dcache_access_translate_load_store_unit_to_thread + ); + + _param_glue = new core::core_glue::Parameters + ( + _nb_front_end , + _nb_context ,//[nb_front_end] + _nb_ooo_engine , + _nb_execute_loop , + _ooo_engine_nb_front_end ,//[nb_ooo_engine] + _ooo_engine_nb_execute_loop ,//[nb_ooo_engine] + _execute_loop_nb_ooo_engine ,//[nb_execute_loop] + _front_end_sum_inst_decod ,//[nb_front_end] -> [sum_inst_decod] + _front_end_nb_inst_branch_complete ,//[nb_front_end] + _nb_inst_branch_complete ,//[nb_ooo_engine] + _ooo_engine_nb_inst_insert_rob ,//[nb_ooo_engine] + _nb_inst_issue ,//[nb_ooo_engine] + _ooo_engine_nb_inst_execute ,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + _nb_read_unit ,//[nb_execute_loop] + _nb_write_unit ,//[nb_execute_loop] + _size_depth , + _size_rob_ptr , + _size_load_queue_ptr , + _size_store_queue_ptr , + _size_general_data , + _size_special_data , + _size_general_register , + _size_special_register , + _dispatch_priority , + _dispatch_load_balancing , + _network_table_dispatch ,//[nb_ooo_engine][nb_inst_issue][nb_execute_loop][nb_read_unit] + _translate_ooo_engine_num_front_end ,//[nb_ooo_engine][ooo_engine_nb_front_end] + _translate_ooo_engine_num_execute_loop,//[nb_ooo_engine][ooo_engine_nb_execute_loop] + _translate_execute_loop_num_ooo_engine //*[nb_execute_loop][execute_loop_nb_ooo_engine] + ); + + copy(); + + log_end(Core,FUNCTION); + }; + +// #undef FUNCTION +// #define FUNCTION "Core::Parameters (copy)" +// Parameters::Parameters (Parameters & param) +// { +// log_begin(Core,FUNCTION); +// test(); +// log_end(Core,FUNCTION); +// }; + +#undef FUNCTION +#define FUNCTION "Core::~Parameters" + Parameters::~Parameters (void) + { + log_begin(Core,FUNCTION); + + delete [] _param_front_end; + delete [] _param_ooo_engine; + delete [] _param_execute_loop; + delete _param_icache_access; + delete _param_dcache_access; + delete _param_glue; + + DELETE3(_dcache_access_translate_load_store_unit_to_thread ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_dcache_access_nb_context[it1]); + DELETE1(_dcache_access_nb_context ,_nb_execute_loop); + DELETE3(_dcache_access_table_routing ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1],_execute_loop_nb_cache_port[it1][it2]); + DELETE2(_dcache_access_size_packet_id ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_dcache_access_size_thread_id ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE1(_icache_nb_instruction ,_nb_icache_port); + DELETE2(_icache_access_table_routing ,_nb_front_end,_nb_context[it1]); + DELETE2(_icache_access_size_packet_id ,_nb_front_end,_nb_context[it1]); + DELETE3(_execute_loop_execution_unit_to_write_unit_table_thread ,_nb_execute_loop,_nb_write_unit[it1],_execute_loop_nb_thread [it1]); + DELETE3(_execute_loop_read_unit_to_execution_unit_table_thread ,_nb_execute_loop,_nb_execute_unit[it1],_execute_loop_nb_thread[it1]); + DELETE4(_execute_loop_execution_unit_to_write_unit_table_routing,_nb_execute_loop,_nb_execute_unit[it1],_execute_loop_nb_execute_unit_port[it1][it2],_nb_write_unit[it1]); + DELETE4(_execute_loop_read_unit_to_execution_unit_table_routing ,_nb_execute_loop,_nb_read_unit[it1],_nb_execute_unit[it1],_execute_loop_nb_execute_unit_port[it1][it2]); + DELETE2(_execute_loop_nb_execute_unit_port ,_nb_execute_loop,_nb_execute_unit[it1]); + DELETE2(_execute_loop_nb_inst_retire_rob ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_execute_loop_nb_inst_insert_rob ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_execute_loop_nb_special_register ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_execute_loop_nb_general_register ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE2(_execute_loop_nb_bypass_write ,_nb_execute_loop,_nb_write_unit[it1]); + DELETE2(_execute_loop_size_execute_queue ,_nb_execute_loop,_nb_write_unit[it1]); + DELETE2(_execute_loop_size_write_queue ,_nb_execute_loop,_nb_write_unit[it1]); + DELETE2(_execute_loop_nb_inst_memory ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_nb_cache_port ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_nb_bypass_memory ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_speculative_load ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_nb_port_check ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_size_speculative_access_queue ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_size_load_queue ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_size_store_queue ,_nb_execute_loop,_execute_loop_nb_load_store_unit[it1]); + DELETE2(_execute_loop_translate_num_execute_unit ,_nb_execute_loop,_nb_execute_unit[it1]); + DELETE2(_execute_loop_is_load_store_unit ,_nb_execute_loop,_nb_execute_unit[it1]); + DELETE4(_execute_loop_timing ,_nb_execute_loop,_execute_loop_nb_functionnal_unit[it1],_nb_type,_nb_operation); + DELETE2(_execute_loop_nb_inst_functionnal_unit ,_nb_execute_loop,_execute_loop_nb_functionnal_unit[it1]); + DELETE2(_execute_loop_nb_inst_retire ,_nb_execute_loop,_nb_read_unit[it1]); + DELETE2(_execute_loop_size_reservation_station ,_nb_execute_loop,_nb_read_unit[it1]); + DELETE2(_execute_loop_size_read_queue ,_nb_execute_loop,_nb_read_unit[it1]); + DELETE2(_translate_execute_loop_num_ooo_engine ,_nb_execute_loop,_execute_loop_nb_ooo_engine[it1]); + DELETE1(_execute_loop_nb_thread ,_nb_execute_loop); + DELETE1(_execute_loop_nb_packet ,_nb_execute_loop); + DELETE1(_execute_loop_nb_ooo_engine ,_nb_execute_loop); + DELETE1(_execute_loop_nb_context ,_nb_execute_loop); + DELETE1(_execute_loop_nb_front_end ,_nb_execute_loop); + DELETE1(_list_front_end_with_execute_loop ,_nb_execute_loop); + DELETE1(_list_ooo_engine_with_execute_loop ,_nb_execute_loop); + DELETE1(_execute_loop_nb_load_store_unit ,_nb_execute_loop); + DELETE1(_execute_loop_nb_functionnal_unit ,_nb_execute_loop); + DELETE4(_ooo_engine_implement_group ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2],NB_GROUP); + DELETE3(_ooo_engine_link_load_store_unit_with_context ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); + DELETE3(_ooo_engine_size_load_queue ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); + DELETE3(_ooo_engine_size_store_queue ,_nb_ooo_engine,_nb_rename_unit[it1],_ooo_engine_nb_load_store_unit[it1][it2]); + DELETE2(_ooo_engine_nb_load_store_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_list_load_store_unit_with_rename_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_list_functionnal_unit_with_rename_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE3(_ooo_engine_table_issue_type ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_type); + DELETE3(_ooo_engine_table_routing ,_nb_ooo_engine,_nb_rename_unit[it1],_nb_inst_issue[it1]); + DELETE4(_network_table_dispatch ,_nb_ooo_engine,_nb_inst_issue[it1],_nb_execute_loop,_nb_read_unit[it3]); + DELETE2(_ooo_engine_size_read_counter ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_rename_unit_bank ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_reg_free ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_special_register ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_general_register ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_rename_select_nb_front_end_select ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_rename_select_load_balancing ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_rename_select_priority ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_inst_retire ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_nb_inst_insert ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_ooo_engine_link_rename_unit_with_front_end ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + DELETE3(_ooo_engine_nb_branch_speculated ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1],_ooo_engine_nb_context[it1][it2]); + DELETE2(_ooo_engine_nb_inst_execute ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); + DELETE2(_ooo_engine_nb_inst_decod ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + DELETE2(_ooo_engine_nb_context ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + DELETE2(_translate_ooo_engine_num_execute_loop ,_nb_ooo_engine,_ooo_engine_nb_execute_loop[it1]); + DELETE1(_ooo_engine_nb_execute_loop ,_nb_ooo_engine); + DELETE2(_translate_ooo_engine_num_front_end ,_nb_ooo_engine,_ooo_engine_nb_front_end[it1]); + DELETE1(_ooo_engine_nb_front_end ,_nb_ooo_engine); + DELETE2(_front_end_context_select_load_balancing ,_nb_front_end,_nb_decod_unit[it1]); + DELETE2(_front_end_context_select_priority ,_nb_front_end,_nb_decod_unit[it1]); + DELETE2(_front_end_nb_context_select ,_nb_front_end,_nb_decod_unit[it1]); + DELETE1(_front_end_sum_inst_decod ,_nb_front_end); + DELETE2(_front_end_nb_inst_decod ,_nb_front_end,_nb_decod_unit[it1]); + DELETE2(_front_end_size_decod_queue ,_nb_front_end,_nb_decod_unit[it1]); + DELETE1(_front_end_nb_inst_branch_complete ,_nb_front_end); + DELETE3(_front_end_instruction_implemeted ,_nb_front_end,_nb_context[it1],NB_INSTRUCTION); + DELETE2(_front_end_upt_size_queue ,_nb_front_end,_nb_context[it1]); + DELETE2(_front_end_ras_size_queue ,_nb_front_end,_nb_context[it1]); + DELETE2(_front_end_link_decod_unit_with_context ,_nb_front_end,_nb_context[it1]); + DELETE2(_front_end_nb_inst_fetch ,_nb_front_end,_nb_context[it1]); + DELETE2(_front_end_size_ifetch_queue ,_nb_front_end,_nb_context[it1]); + DELETE1(_list_load_store_unit_with_execute_unit ,_nb_execute_loop); + DELETE1(_list_functionnal_unit_with_execute_unit ,_nb_execute_loop); + DELETE2(_link_load_store_unit_with_execute_unit ,_nb_execute_loop,_nb_execute_unit[it1]); + DELETE2(_link_functionnal_unit_with_execute_unit ,_nb_execute_loop,_nb_execute_unit[it1]); + DELETE2(_link_write_bloc_with_write_unit ,_nb_execute_loop,_nb_write_unit[it1]); + DELETE2(_link_read_bloc_with_read_unit ,_nb_execute_loop,_nb_read_unit[it1]); + DELETE2(_link_rename_bloc_with_rename_unit ,_nb_ooo_engine,_nb_rename_unit[it1]); + DELETE2(_link_decod_bloc_with_decod_unit ,_nb_front_end,_nb_decod_unit[it1]); + DELETE2(_link_thread_with_context ,_nb_front_end,_nb_context[it1]); + + log_end(Core,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Core::copy" + void Parameters::copy (void) + { + log_begin(Core,FUNCTION); + + for (uint32_t i=0; i<_nb_front_end; ++i) + COPY(_param_front_end [i]); + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + COPY(_param_ooo_engine [i]); + for (uint32_t i=0; i<_nb_execute_loop; ++i) + COPY(_param_execute_loop [i]); + COPY(_param_icache_access); + COPY(_param_dcache_access); + COPY(_param_glue); + + log_end(Core,FUNCTION); + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_msg_error.cpp (revision 88) @@ -0,0 +1,409 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Behavioural/Core/include/Parameters.h" +#include "Common/include/Max.h" +#include + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::msg_error" + Parameters_test Parameters::msg_error(void) + { + log_begin(Core,FUNCTION); + + Parameters_test test ("Core"); + + // TESTER SI LES VALEURS NE DEPASSE PAS DE L'INTERVALLE AUTORISE + + { + // initialisation + uint32_t nb_link_context [_nb_front_end][max(_nb_context,_nb_front_end)]; + + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i];++j) + nb_link_context [i][j] = 0; + + // set link + for (uint32_t i=0; i<_nb_thread; ++i) + nb_link_context[_link_context_with_thread[i].first][_link_context_with_thread[i].second] ++; + + // test + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_context[i];++j) + { + if (nb_link_context[i][j] == 0) + test.error(toString(_("Context [%d][%d] is not link with a thread.\n"),i,j)); + if (nb_link_context[i][j] > 1) + test.error(toString(_("Context [%d][%d] is linked with 2 or more threads.\n"),i,j)); + } + } + + { + // initialisation + uint32_t nb_link_decod_unit [_nb_front_end][max(_nb_decod_unit,_nb_front_end)]; + + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_decod_unit[i];++j) + nb_link_decod_unit [i][j] = 0; + + // set link + for (uint32_t i=0; i<_nb_decod_bloc; ++i) + nb_link_decod_unit[_link_decod_unit_with_decod_bloc[i].first][_link_decod_unit_with_decod_bloc[i].second] ++; + + // test + for (uint32_t i=0; i<_nb_front_end; ++i) + for (uint32_t j=0; j<_nb_decod_unit[i];++j) + { + if (nb_link_decod_unit[i][j] == 0) + test.error(toString(_("Decod_Unit [%d][%d] is not link with a decod_bloc.\n"),i,j)); + if (nb_link_decod_unit[i][j] > 1) + test.error(toString(_("Decod_Unit [%d][%d] is linked with 2 or more decod_bloc.\n"),i,j)); + } + } + + { + // initialisation + uint32_t nb_link_rename_unit [_nb_ooo_engine][max(_nb_rename_unit,_nb_ooo_engine)]; + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_rename_unit[i];++j) + nb_link_rename_unit [i][j] = 0; + + // set link + for (uint32_t i=0; i<_nb_rename_bloc; ++i) + nb_link_rename_unit[_link_rename_unit_with_rename_bloc[i].first][_link_rename_unit_with_rename_bloc[i].second] ++; + + // test + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_rename_unit[i];++j) + { + if (nb_link_rename_unit[i][j] == 0) + test.error(toString(_("Rename_Unit [%d][%d] is not link with a rename_bloc.\n"),i,j)); + if (nb_link_rename_unit[i][j] > 1) + test.error(toString(_("Rename_Unit [%d][%d] is linked with 2 or more rename_bloc.\n"),i,j)); + } + } + + { + // initialisation + uint32_t nb_link_read_unit [_nb_execute_loop][max(_nb_read_unit,_nb_execute_loop)]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_read_unit[i];++j) + nb_link_read_unit [i][j] = 0; + + // set link + for (uint32_t i=0; i<_nb_read_bloc; ++i) + nb_link_read_unit[_link_read_unit_with_read_bloc[i].first][_link_read_unit_with_read_bloc[i].second] ++; + + // test + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_read_unit[i];++j) + { + if (nb_link_read_unit[i][j] == 0) + test.error(toString(_("Read_Unit [%d][%d] is not link with a read_bloc.\n"),i,j)); + if (nb_link_read_unit[i][j] > 1) + test.error(toString(_("Read_Unit [%d][%d] is linked with 2 or more read_bloc.\n"),i,j)); + } + } + + { + // initialisation + uint32_t nb_link_write_unit [_nb_execute_loop][max(_nb_write_unit,_nb_execute_loop)]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_write_unit[i];++j) + nb_link_write_unit [i][j] = 0; + + // set link + for (uint32_t i=0; i<_nb_write_bloc; ++i) + nb_link_write_unit[_link_write_unit_with_write_bloc[i].first][_link_write_unit_with_write_bloc[i].second] ++; + + // test + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_write_unit[i];++j) + { + if (nb_link_write_unit[i][j] == 0) + test.error(toString(_("Write_Unit [%d][%d] is not link with a write_bloc.\n"),i,j)); + if (nb_link_write_unit[i][j] > 1) + test.error(toString(_("Write_Unit [%d][%d] is linked with 2 or more write_bloc.\n"),i,j)); + } + } + + { + // initialisation + uint32_t nb_link_execute_unit [_nb_execute_loop][max(_nb_execute_unit,_nb_execute_loop)]; + uint32_t nb_functionnal_unit [_nb_execute_loop]; + uint32_t nb_load_store_unit [_nb_execute_loop]; + + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + nb_functionnal_unit [i] = 0; + nb_load_store_unit [i] = 0; + + for (uint32_t j=0; j<_nb_execute_unit[i];++j) + nb_link_execute_unit [i][j] = 0; + } + + // set link + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + { + uint32_t num_execute_loop = _link_execute_unit_with_functionnal_unit [i].first; + uint32_t num_execute_unit = _link_execute_unit_with_functionnal_unit [i].second; + + nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; + nb_functionnal_unit [i] ++; + } + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + { + uint32_t num_execute_loop = _link_execute_unit_with_load_store_unit [i].first; + uint32_t num_execute_unit = _link_execute_unit_with_load_store_unit [i].second; + + nb_link_execute_unit [num_execute_loop][num_execute_unit] ++; + nb_load_store_unit [i] ++; + } + + // test + for (uint32_t i=0; i<_nb_execute_loop; ++i) + for (uint32_t j=0; j<_nb_execute_unit[i];++j) + { + if (nb_link_execute_unit[i][j] == 0) + test.error(toString(_("Execute_Unit [%d][%d] is not link with a load_store_unit or functionnal_unit.\n"),i,j)); + if (nb_link_execute_unit[i][j] > 1) + test.error(toString(_("Execute_Unit [%d][%d] is linked with 2 or more time.\n"),i,j)); + } + + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + { + if (nb_functionnal_unit[i] == 0) + test.error(toString(_("Functionnal_Unit [%d] is not instanced.\n"),i)); + if (nb_functionnal_unit[i] > 1) + test.error(toString(_("Functionnal_Unit [%d] is linked with 2 or more time.\n"),i)); + } + + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + { + if (nb_load_store_unit[i] == 0) + test.error(toString(_("Load_Store_Unit [%d] is not instanced.\n"),i)); + if (nb_load_store_unit[i] > 1) + test.error(toString(_("Load_Store_Unit [%d] is linked with 2 or more time.\n"),i)); + } + } + + { + // initialisation + uint32_t nb_link_slot [_nb_ooo_engine][max(_nb_inst_issue,_nb_ooo_engine)]; + uint32_t nb_link_read_bloc [_nb_read_bloc]; + + // initialisation + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + nb_link_slot [i][j] = 0; + for (uint32_t i=0; i<_nb_read_bloc; ++i) + nb_link_read_bloc [i] = 0; + + // set link + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + for (uint32_t k=0; k<_nb_read_bloc; ++k) + if (_table_dispatch [i][j][k]) + { + nb_link_slot [i][j] ++; + nb_link_read_bloc [k] ++; + } + + // test + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + if (nb_link_slot [i][j] == 0) + test.error(toString(_("In Out Of Order Engine [%d], the slot issue [%d] is not link with a read_bloc.\n"),i,j)); + for (uint32_t i=0; i<_nb_read_bloc; ++i) + if (nb_link_read_bloc [i] == 0) + test.error(toString(_("Read_bloc [%d] is not link with a issue's slot.\n"),i)); + } + + { + uint32_t nb_link_read_bloc [_nb_read_bloc]; + uint32_t nb_link_load_store_unit [_nb_load_store_unit]; + uint32_t nb_link_functionnal_unit [_nb_functionnal_unit]; + + for (uint32_t i=0; i<_nb_read_bloc; ++i) + nb_link_read_bloc [i] = 0; + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + nb_link_load_store_unit [i] = 0; + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + nb_link_functionnal_unit [i] = 0; + + for (uint32_t i=0; i<_nb_read_bloc; ++i) + { + for (uint32_t j=0; j<_nb_load_store_unit; ++j) + if (_link_read_bloc_and_load_store_unit [i][j]) + { + nb_link_read_bloc [i] ++; + nb_link_load_store_unit [j] ++; + } + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + if (_link_read_bloc_and_functionnal_unit [i][j]) + { + nb_link_read_bloc [i] ++; + nb_link_functionnal_unit [j] ++; + } + } + + for (uint32_t i=0; i<_nb_read_bloc; ++i) + if (nb_link_read_bloc [i] == 0) + test.error(toString(_("Read_bloc [%d] is not link with an execute_unit.\n"),i)); + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + if (nb_link_load_store_unit [i] == 0) + test.error(toString(_("load_store_unit [%d] is not link with a read_bloc.\n"),i)); + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + if (nb_link_functionnal_unit [i] == 0) + test.error(toString(_("functionnal_unit [%d] is not link with a read_bloc.\n"),i)); + } + + { + uint32_t nb_link_write_bloc [_nb_write_bloc]; + uint32_t nb_link_load_store_unit [_nb_load_store_unit]; + uint32_t nb_link_functionnal_unit [_nb_functionnal_unit]; + + for (uint32_t i=0; i<_nb_write_bloc; ++i) + nb_link_write_bloc [i] = 0; + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + nb_link_load_store_unit [i] = 0; + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + nb_link_functionnal_unit [i] = 0; + + for (uint32_t i=0; i<_nb_write_bloc; ++i) + { + for (uint32_t j=0; j<_nb_load_store_unit; ++j) + if (_link_write_bloc_and_load_store_unit [i][j]) + { + nb_link_write_bloc [i] ++; + nb_link_load_store_unit [j] ++; + } + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + if (_link_write_bloc_and_functionnal_unit [i][j]) + { + nb_link_write_bloc [i] ++; + nb_link_functionnal_unit [j] ++; + } + } + + for (uint32_t i=0; i<_nb_write_bloc; ++i) + if (nb_link_write_bloc [i] == 0) + test.error(toString(_("Write_bloc [%d] is not link with an execute_unit.\n"),i)); + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + if (nb_link_load_store_unit [i] == 0) + test.error(toString(_("load_store_unit [%d] is not link with a write_bloc.\n"),i)); + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + if (nb_link_functionnal_unit [i] == 0) + test.error(toString(_("functionnal_unit [%d] is not link with a write_bloc.\n"),i)); + } + + { + uint32_t nb_link_thread [_nb_thread]; + uint32_t nb_link_load_store_unit [_nb_load_store_unit]; + uint32_t nb_link_functionnal_unit [_nb_functionnal_unit]; + + for (uint32_t i=0; i<_nb_thread; ++i) + nb_link_thread [i] = 0; + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + nb_link_load_store_unit [i] = 0; + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + nb_link_functionnal_unit [i] = 0; + + for (uint32_t i=0; i<_nb_thread; ++i) + { + { + uint32_t num_load_store_unit = _link_load_store_unit_with_thread [i]; + + nb_link_thread [i] ++; + nb_link_load_store_unit [num_load_store_unit] ++; + } + + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + if (_link_thread_and_functionnal_unit [i][j]) + { + nb_link_thread [i] ++; + nb_link_functionnal_unit [j] ++; + } + } + + for (uint32_t i=0; i<_nb_thread; ++i) + if (nb_link_thread [i] < 2) + test.error(toString(_("Thread [%d] is not link with a load_store_unit and a functionnal_unit.\n"),i)); + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + if (nb_link_load_store_unit [i] == 0) + test.error(toString(_("Load_store_unit [%d] is not link with a thread.\n"),i)); + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + if (nb_link_functionnal_unit [i] == 0) + test.error(toString(_("Functionnal_unit [%d] is not link with a thread.\n"),i)); + } + + { + uint32_t nb_link_icache_port [_nb_icache_port]; + + for (uint32_t i=0; i<_nb_icache_port; ++i) + nb_link_icache_port [i] = 0; + + for (uint32_t i=0; i<_nb_thread; ++i) + nb_link_icache_port [_link_icache_port_with_thread [i]] ++; + + for (uint32_t i=0; i<_nb_icache_port; ++i) + if (nb_link_icache_port [i] == 0) + test.error(toString(_("Icache port [%d] is not link with a thread.\n"),i)); + } + + { + uint32_t nb_link_dcache_port [_nb_dcache_port]; + + for (uint32_t i=0; i<_nb_dcache_port; ++i) + nb_link_dcache_port [i] = 0; + + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + for (uint32_t j=0; j<_nb_cache_port[i]; ++j) + nb_link_dcache_port [_link_dcache_port_with_load_store_unit[i][j]] ++; + + for (uint32_t i=0; i<_nb_dcache_port; ++i) + if (nb_link_dcache_port [i] == 0) + test.error(toString(_("Dcache port [%d] is not link with a port of load store unit.\n"),i)); + } + + +// public : pair_dual * _link_context_with_thread ;//[nb_thread] +// public : pair_dual * _link_decod_unit_with_decod_bloc ;//[nb_decod_bloc] +// public : pair_dual * _link_rename_unit_with_rename_bloc ;//[nb_rename_bloc] +// public : pair_dual * _link_read_unit_with_read_bloc ;//[nb_read_bloc] +// public : pair_dual * _link_write_unit_with_write_bloc ;//[nb_write_bloc] +// public : pair_dual * _link_execute_unit_with_functionnal_unit ;//[nb_functionnal_unit] +// public : pair_dual * _link_execute_unit_with_load_store_unit ;//[nb_load_store_unit] +// public : uint32_t * _link_decod_bloc_with_thread ;//[nb_thread] +// public : uint32_t * _link_rename_bloc_with_front_end ;//[nb_front_end] +// public : bool *** _table_dispatch ;//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] +// public : bool ** _link_read_bloc_and_load_store_unit ;//[nb_read_bloc][nb_load_store_unit] +// public : bool ** _link_read_bloc_and_functionnal_unit ;//[nb_read_bloc][nb_functionnal_unit] +// public : bool ** _link_write_bloc_and_load_store_unit ;//[nb_write_bloc][nb_load_store_unit] +// public : bool ** _link_write_bloc_and_functionnal_unit ;//[nb_write_bloc][nb_functionnal_unit] +// public : uint32_t * _link_load_store_unit_with_thread ;//[nb_thread] +// public : bool ** _link_thread_and_functionnal_unit ;//[nb_thread][nb_functionnal_unit] +// public : uint32_t * _link_icache_port_with_thread ;//[nb_thread] +// public : uint32_t ** _link_dcache_port_with_load_store_unit ;//[nb_load_store_unit][nb_cache_port] + + log_end(Core,FUNCTION); + + return test; + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 88) @@ -0,0 +1,286 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Core/include/Parameters.h" +#include "Behavioural/include/XML.h" + +namespace morpheo { +namespace behavioural { +namespace core { + + +#undef FUNCTION +#define FUNCTION "Core::print" + std::string Parameters::print (uint32_t depth) + { + log_begin(Core,FUNCTION); + +// XML xml ("core"); + +// xml.balise_open("core"); +// // xml.singleton_begin(""); xml.attribut("value",toString(_)); xml.singleton_end(); +// xml.balise_close(); + +// return xml.get_body(depth); + + std::string str = ""; + + str+= toString(MSG_INFORMATION)+" -----[ Common ]-----------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * size_general_data : "+toString(_size_general_data)+"\n"; + str+= toString(MSG_INFORMATION)+" * size_special_data : "+toString(_size_special_data)+"\n"; + + str+= toString(MSG_INFORMATION)+" -----[ Thread ]-----------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_thread : "+toString(_nb_thread)+"\n"; + for (uint32_t i=0; i<_nb_thread; ++i) + { + str+= toString(MSG_INFORMATION)+" * THREAD ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * size_ifetch_queue : "+toString(_size_ifetch_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_fetch : "+toString(_nb_inst_fetch [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * ras_size_queue : "+toString(_ras_size_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * upt_size_queue : "+toString(_upt_size_queue [i])+"\n"; + + for (uint32_t j=0; j(_implement_group [i][j])+"\n"; + } + } + + str+= toString(MSG_INFORMATION)+" -----[ Decod bloc ]-------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_decod_bloc : "+toString(_nb_decod_bloc)+"\n"; + for (uint32_t i=0; i<_nb_decod_bloc; ++i) + { + str+= toString(MSG_INFORMATION)+" * DECOD_BLOC ["+toString(i)+"]\n"; + + str+= toString(MSG_INFORMATION)+" * size_decod_queue : "+toString(_size_decod_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_decod : "+toString(_nb_inst_decod [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_context_select : "+toString(_nb_context_select [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * context_select_priority : "+toString(_context_select_priority [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * context_select_load_balancing : "+toString(_context_select_load_balancing[i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Rename bloc ]------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_rename_bloc : "+toString(_nb_rename_bloc)+"\n"; + for (uint32_t i=0; i<_nb_rename_bloc; ++i) + { + str+= toString(MSG_INFORMATION)+" * RENAME_BLOC ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_insert : "+toString(_nb_inst_insert [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_retire : "+toString(_nb_inst_retire [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * rename_select_priority : "+toString(_rename_select_priority [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * rename_select_load_balancing : "+toString(_rename_select_load_balancing [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * rename_select_nb_front_end_select : "+toString(_rename_select_nb_front_end_select[i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_general_register : "+toString(_nb_general_register [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_special_register : "+toString(_nb_special_register [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_reg_free : "+toString(_nb_reg_free [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_rename_unit_bank : "+toString(_nb_rename_unit_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_read_counter : "+toString(_size_read_counter [i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Read bloc ]--------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_read_bloc : "+toString(_nb_read_bloc )+"\n"; + for (uint32_t i=0; i<_nb_read_bloc; ++i) + { + str+= toString(MSG_INFORMATION)+" * READ_BLOC ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * size_read_queue : "+toString(_size_read_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_reservation_station : "+toString(_size_reservation_station [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_retire_reservation_station : "+toString(_nb_inst_retire_reservation_station[i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Write bloc ]-------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_write_bloc : "+toString(_nb_write_bloc )+"\n"; + for (uint32_t i=0; i<_nb_write_bloc; ++i) + { + str+= toString(MSG_INFORMATION)+" * WRITE_BLOC ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * size_write_queue : "+toString(_size_write_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_execute_queue : "+toString(_size_execute_queue[i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_bypass_write : "+toString(_nb_bypass_write [i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Load_store_unit ]--------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_load_store_unit : "+toString(_nb_load_store_unit )+"\n"; + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + { + str+= toString(MSG_INFORMATION)+" * LOAD_STORE_UNIT ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * size_store_queue : "+toString(_size_store_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_load_queue : "+toString(_size_load_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_speculative_access_queue : "+toString(_size_speculative_access_queue[i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_port_check : "+toString(_nb_port_check [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * speculative_load : "+toString(_speculative_load [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_bypass_memory : "+toString(_nb_bypass_memory [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_cache_port : "+toString(_nb_cache_port [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_memory : "+toString(_nb_inst_memory [i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Functionnal_unit ]-------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_functionnal_unit : "+toString(_nb_functionnal_unit )+"\n"; + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + { + str+= toString(MSG_INFORMATION)+" * FUNCTIONNAL_UNIT ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_functionnal_unit : "+toString(_nb_inst_functionnal_unit [i])+"\n"; + } + +//multi_execute_loop::execute_loop::execute_timing_t *** timing; //[nb_functionnal_unit][nb_type][nb_operation] + + str+= toString(MSG_INFORMATION)+" -----[ Icache_Access ]----------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_icache_port : "+toString(_nb_icache_port )+"\n"; + str+= toString(MSG_INFORMATION)+" * icache_port_priority : "+toString(_icache_port_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * icache_port_load_balancing : "+toString(_icache_port_load_balancing)+"\n"; + + str+= toString(MSG_INFORMATION)+" -----[ Dcache_Access ]----------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_dcache_port : "+toString(_nb_dcache_port )+"\n"; + str+= toString(MSG_INFORMATION)+" * dcache_port_priority : "+toString(_dcache_port_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * dcache_port_load_balancing : "+toString(_dcache_port_load_balancing)+"\n"; + + str+= toString(MSG_INFORMATION)+" -----[ Front_end ]--------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_front_end : "+toString(_nb_front_end )+"\n"; + for (uint32_t i=0; i<_nb_front_end; ++i) + { + str+= toString(MSG_INFORMATION)+" * FRONT_END ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * nb_context : "+toString(_nb_context [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_decod_unit : "+toString(_nb_decod_unit [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_branch_predict : "+toString(_nb_inst_branch_predict [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_branch_decod : "+toString(_nb_inst_branch_decod [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_branch_update : "+toString(_nb_inst_branch_update [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * btb_size_queue : "+toString(_btb_size_queue [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * btb_associativity : "+toString(_btb_associativity [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * btb_size_counter : "+toString(_btb_size_counter [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * btb_victim_scheme : "+toString(_btb_victim_scheme [i] )+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_predictor_scheme : "+toString(_dir_predictor_scheme [i] )+"\n"; + for (uint32_t j=0; j<3; ++j) + { + str+= toString(MSG_INFORMATION)+" * PREDICTOR ["+toString(i)+"]["+toString(j)+"]\n"; + str+= toString(MSG_INFORMATION)+" * dir_have_bht : "+toString(_dir_have_bht [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_bht_size_shifter : "+toString(_dir_bht_size_shifter [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_bht_nb_shifter : "+toString(_dir_bht_nb_shifter [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_have_pht : "+toString(_dir_have_pht [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_pht_size_counter : "+toString(_dir_pht_size_counter [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_pht_nb_counter : "+toString(_dir_pht_nb_counter [i][j])+"\n"; + str+= toString(MSG_INFORMATION)+" * dir_pht_size_address_share : "+toString(_dir_pht_size_address_share[i][j])+"\n"; + } + } + + str+= toString(MSG_INFORMATION)+" -----[ OOO_Engine ]-------------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_ooo_engine : "+toString(_nb_ooo_engine )+"\n"; + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + { + str+= toString(MSG_INFORMATION)+" * OOO_ENGINE ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * nb_rename_unit : "+toString(_nb_rename_unit [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_issue : "+toString(_nb_inst_issue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_reexecute : "+toString(_nb_inst_reexecute [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_commit : "+toString(_nb_inst_commit [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_inst_branch_complete : "+toString(_nb_inst_branch_complete [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_rename_unit_select : "+toString(_nb_rename_unit_select [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_execute_loop_select : "+toString(_nb_execute_loop_select [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_re_order_buffer : "+toString(_size_re_order_buffer [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_re_order_buffer_bank : "+toString(_nb_re_order_buffer_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * commit_priority : "+toString(_commit_priority [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * commit_load_balancing : "+toString(_commit_load_balancing [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_issue_queue : "+toString(_size_issue_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_issue_queue_bank : "+toString(_nb_issue_queue_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * issue_priority : "+toString(_issue_priority [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * issue_load_balancing : "+toString(_issue_load_balancing [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * size_reexecute_queue : "+toString(_size_reexecute_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * reexecute_priority : "+toString(_reexecute_priority [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * reexecute_load_balancing : "+toString(_reexecute_load_balancing[i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Execute_loop ]-----------------------------\n"; + str+= toString(MSG_INFORMATION)+" * nb_execute_loop : "+toString(_nb_execute_loop )+"\n"; + for (uint32_t i=0; i<_nb_execute_loop; ++i) + { + str+= toString(MSG_INFORMATION)+" * EXECUTE_LOOP ["+toString(i)+"]\n"; + str+= toString(MSG_INFORMATION)+" * nb_read_unit : "+toString(_nb_read_unit [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_execute_unit : "+toString(_nb_execute_unit [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_write_unit : "+toString(_nb_write_unit [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_gpr_bank : "+toString(_nb_gpr_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_gpr_port_read_by_bank : "+toString(_nb_gpr_port_read_by_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_gpr_port_write_by_bank : "+toString(_nb_gpr_port_write_by_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_spr_bank : "+toString(_nb_spr_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_spr_port_read_by_bank : "+toString(_nb_spr_port_read_by_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * nb_spr_port_write_by_bank : "+toString(_nb_spr_port_write_by_bank [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * execution_unit_to_write_unit_priority : "+toString(_execution_unit_to_write_unit_priority[i])+"\n"; + str+= toString(MSG_INFORMATION)+" * read_unit_to_execution_unit_priority : "+toString(_read_unit_to_execution_unit_priority [i])+"\n"; + } + + str+= toString(MSG_INFORMATION)+" -----[ Link ]-------------------------------------\n"; + + for (uint32_t i=0; i<_nb_thread; ++i) + str+= toString(MSG_INFORMATION)+" * link_context_with_thread ["+toString(i)+"] -> ["+toString(_link_context_with_thread [i].first)+"]["+toString(_link_context_with_thread [i].second)+"]\n";//[nb_thread] + for (uint32_t i=0; i<_nb_decod_bloc; ++i) + str+= toString(MSG_INFORMATION)+" * link_decod_unit_with_decod_bloc ["+toString(i)+"] -> ["+toString(_link_decod_unit_with_decod_bloc [i].first)+"]["+toString(_link_decod_unit_with_decod_bloc [i].second)+"]\n";//[nb_decod_bloc] + for (uint32_t i=0; i<_nb_rename_bloc; ++i) + str+= toString(MSG_INFORMATION)+" * link_rename_unit_with_rename_bloc ["+toString(i)+"] -> ["+toString(_link_rename_unit_with_rename_bloc [i].first)+"]["+toString(_link_rename_unit_with_rename_bloc [i].second)+"]\n";//[nb_rename_bloc] + for (uint32_t i=0; i<_nb_read_bloc; ++i) + str+= toString(MSG_INFORMATION)+" * link_read_unit_with_read_bloc ["+toString(i)+"] -> ["+toString(_link_read_unit_with_read_bloc [i].first)+"]["+toString(_link_read_unit_with_read_bloc [i].second)+"]\n";//[nb_read_bloc] + for (uint32_t i=0; i<_nb_write_bloc; ++i) + str+= toString(MSG_INFORMATION)+" * link_write_unit_with_write_bloc ["+toString(i)+"] -> ["+toString(_link_write_unit_with_write_bloc [i].first)+"]["+toString(_link_write_unit_with_write_bloc [i].second)+"]\n";//[nb_write_bloc] + for (uint32_t i=0; i<_nb_functionnal_unit; ++i) + str+= toString(MSG_INFORMATION)+" * link_execute_unit_with_functionnal_unit ["+toString(i)+"] -> ["+toString(_link_execute_unit_with_functionnal_unit[i].first)+"]["+toString(_link_execute_unit_with_functionnal_unit[i].second)+"]\n";//[nb_functionnal_unit] + for (uint32_t i=0; i<_nb_load_store_unit;++i) + str+= toString(MSG_INFORMATION)+" * link_execute_unit_with_load_store_unit ["+toString(i)+"] -> ["+toString(_link_execute_unit_with_load_store_unit [i].first)+"]["+toString(_link_execute_unit_with_load_store_unit [i].second)+"]\n";//[nb_load_store_unit] + + for (uint32_t i=0; i<_nb_thread; ++i) + str+= toString(MSG_INFORMATION)+" * link_decod_bloc_with_thread ["+toString(i)+"] -> ["+toString(_link_decod_bloc_with_thread [i])+"]\n";//[nb_thread] + for (uint32_t i=0; i<_nb_front_end; ++i) + str+= toString(MSG_INFORMATION)+" * link_rename_bloc_with_front_end ["+toString(i)+"] -> ["+toString(_link_rename_bloc_with_front_end [i])+"]\n";//[nb_front_end] + for (uint32_t i=0; i<_nb_thread; ++i) + str+= toString(MSG_INFORMATION)+" * link_load_store_unit_with_thread ["+toString(i)+"] -> ["+toString(_link_load_store_unit_with_thread [i])+"]\n";//[nb_thread] + for (uint32_t i=0; i<_nb_thread; ++i) + str+= toString(MSG_INFORMATION)+" * link_icache_port_with_thread ["+toString(i)+"] -> ["+toString(_link_icache_port_with_thread [i])+"]\n";//[nb_thread] + for (uint32_t i=0; i<_nb_load_store_unit; ++i) + for (uint32_t j=0; j<_nb_cache_port[i]; ++j) + str+= toString(MSG_INFORMATION)+" * link_dcache_port_with_load_store_unit ["+toString(i)+"]["+toString(j)+"] -> ["+toString(_link_dcache_port_with_load_store_unit [i][j])+"]\n";//[nb_load_store_unit][nb_cache_port] + + + for (uint32_t i=0; i<_nb_read_bloc; ++i) + for (uint32_t j=0; j<_nb_load_store_unit; ++j) + str+= toString(MSG_INFORMATION)+" * link_read_bloc_and_load_store_unit ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_read_bloc_and_load_store_unit [i][j])+"\n";//[nb_read_bloc][nb_load_store_unit] + for (uint32_t i=0; i<_nb_read_bloc; ++i) + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + str+= toString(MSG_INFORMATION)+" * link_read_bloc_and_functionnal_unit ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_read_bloc_and_functionnal_unit [i][j])+"\n";//[nb_read_bloc][nb_functionnal_unit] + for (uint32_t i=0; i<_nb_write_bloc; ++i) + for (uint32_t j=0; j<_nb_load_store_unit; ++j) + str+= toString(MSG_INFORMATION)+" * link_write_bloc_and_load_store_unit ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_write_bloc_and_load_store_unit [i][j])+"\n";//[nb_write_bloc][nb_load_store_unit] + for (uint32_t i=0; i<_nb_write_bloc; ++i) + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + str+= toString(MSG_INFORMATION)+" * link_write_bloc_and_functionnal_unit ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_write_bloc_and_functionnal_unit[i][j])+"\n";//[nb_write_bloc][nb_functionnal_unit] + for (uint32_t i=0; i<_nb_thread; ++i) + for (uint32_t j=0; j<_nb_functionnal_unit; ++j) + str+= toString(MSG_INFORMATION)+" * link_thread_and_functionnal_unit ["+toString(i)+"]["+toString(j)+"] : "+toString(_link_thread_and_functionnal_unit [i][j])+"\n";//[nb_thread][nb_functionnal_unit] + + str+= toString(MSG_INFORMATION)+" -----[ Dispatch ]---------------------------------\n"; + + for (uint32_t i=0; i<_nb_ooo_engine; ++i) + for (uint32_t j=0; j<_nb_inst_issue[i]; ++j) + for (uint32_t k=0; k<_nb_read_bloc; ++k) + str+= toString(MSG_INFORMATION)+" * table_dispatch ["+toString(i)+"]["+toString(j)+"]["+toString(k)+"] : "+toString(_table_dispatch [i][j][k])+"\n";//[nb_ooo_engine][nb_inst_issue][nb_read_bloc] + + str+= toString(MSG_INFORMATION)+" * dispatch_priority : "+toString(_dispatch_priority )+"\n"; + str+= toString(MSG_INFORMATION)+" * dispatch_load_balancing : "+toString(_dispatch_load_balancing); + + log_end(Core,FUNCTION); + + return str; + }; + +#undef FUNCTION +#define FUNCTION "Core::operator<<" + std::ostream& operator<< (std::ostream& output_stream , + morpheo::behavioural::core::Parameters & x) + { + log_begin(Core,FUNCTION); + + output_stream << x.print(0); + + log_end(Core,FUNCTION); + + return output_stream; + }; + +}; // end namespace core +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_default.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_default.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_default.h (revision 88) @@ -26,5 +26,6 @@ custom_vhdl_t * default_get_vhdl_execute (void); - custom_information_t default_get_custom_information (uint32_t context); +//custom_information_t default_get_custom_information (uint32_t context); + custom_information_t default_get_custom_information (void); }; // end namespace custom Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_example.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_example.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/include/Custom_example.h (revision 88) @@ -26,5 +26,6 @@ custom_vhdl_t * example_get_vhdl_execute (void); - custom_information_t example_get_custom_information (uint32_t context); +//custom_information_t example_get_custom_information (uint32_t context); + custom_information_t example_get_custom_information (void); }; // end namespace custom Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_default.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_default.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_default.cpp (revision 88) @@ -223,5 +223,6 @@ #undef FUNCTION #define FUNCTION "custom::default_get_custom_information" - custom_information_t default_get_custom_information (uint32_t context) +//custom_information_t default_get_custom_information (uint32_t context) + custom_information_t default_get_custom_information (void) { custom_information_t info; @@ -236,4 +237,5 @@ info._get_vhdl_decod = &morpheo::behavioural::custom::default_get_vhdl_decod ; info._get_vhdl_execute = &morpheo::behavioural::custom::default_get_vhdl_execute ; + return info; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_example.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_example.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Custom/src/Custom_example.cpp (revision 88) @@ -265,8 +265,7 @@ #undef FUNCTION #define FUNCTION "custom::example_get_custom_information" - custom_information_t example_get_custom_information (uint32_t context) - { - // for all context - +//custom_information_t example_get_custom_information (uint32_t context) + custom_information_t example_get_custom_information (void) + { custom_information_t info; @@ -280,4 +279,5 @@ info._get_vhdl_decod = &morpheo::behavioural::custom::example_get_vhdl_decod ; info._get_vhdl_execute = &morpheo::behavioural::custom::example_get_vhdl_execute ; + return info; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Counter_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/SelfTest/src/test.cpp (revision 88) @@ -37,4 +37,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Counter * _Counter = new Counter (name.c_str(), #ifdef STATISTICS @@ -42,5 +52,5 @@ #endif param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Counter.h (revision 88) @@ -85,8 +85,8 @@ public : ~Counter (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC #if defined(STATISTICS) or defined(VHDL_TESTBENCH) public : void transition (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/include/Parameters.h (revision 88) @@ -29,6 +29,8 @@ public : Parameters (uint32_t size_data, uint32_t nb_port ); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter.cpp (revision 88) @@ -32,40 +32,61 @@ log_printf(FUNC,Counter,"Counter","Begin"); -#ifdef SYSTEMC +#if DEBUG_Counter == true + log_printf(INFO,Counter,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << param << std::endl; +#endif + + log_printf(INFO,Core,FUNCTION,_("<%s> Allocation"),_name.c_str()); allocation (); -#endif #ifdef STATISTICS - // Allocation of statistics - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Core,FUNCTION,_("<%s> Allocation of statistics"),_name.c_str()); + + // Allocation of statistics + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Core,FUNCTION,_("<%s> Generate the vhdl"),_name.c_str()); + + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { #if defined(STATISTICS) or defined(VHDL_TESTBENCH) - SC_METHOD (transition); - dont_initialize (); - sensitive << (*(in_CLOCK)).pos(); + log_printf(INFO,Core,FUNCTION,_("<%s> Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); #endif - SC_METHOD (genMealy); - dont_initialize (); - for (uint32_t i=0; i<_param._nb_port; i++) - sensitive << *(in_COUNTER_DATA [i]) - << *(in_COUNTER_ADDSUB [i]); - + log_printf(INFO,Core,FUNCTION,_("<%s> Method - genMealy"),_name.c_str()); + SC_METHOD (genMealy); + dont_initialize (); + for (uint32_t i=0; i<_param._nb_port; i++) + sensitive << *(in_COUNTER_DATA [i]) + << *(in_COUNTER_ADDSUB [i]); + #ifdef SYSTEMCASS_SPECIFIC - // List dependency information - for (uint32_t i=0; i<_param._nb_port; i++) - { - (*(out_COUNTER_DATA [i])) (*(in_COUNTER_DATA [i])); - (*(out_COUNTER_DATA [i])) (*(in_COUNTER_ADDSUB [i])); + // List dependency information + for (uint32_t i=0; i<_param._nb_port; i++) + { + (*(out_COUNTER_DATA [i])) (*(in_COUNTER_DATA [i])); + (*(out_COUNTER_DATA [i])) (*(in_COUNTER_ADDSUB [i])); + } +#endif } -#endif #endif @@ -76,11 +97,15 @@ { log_printf(FUNC,Counter,"~Counter","Begin"); -#ifdef SYSTEMC - deallocation (); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + delete _stat; + } #endif -#ifdef STATISTICS - delete _stat; -#endif + log_printf(INFO,Core,FUNCTION,_("<%s> Deallocation"),_name.c_str()); + deallocation (); + log_printf(FUNC,Counter,"~Counter","End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_allocation.cpp (revision 88) @@ -1,7 +1,6 @@ -#ifdef SYSTEMC /* * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -29,5 +28,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { Interface * interface = _interfaces->set_interface("" @@ -43,5 +42,5 @@ } - // ~~~~~[ Interface : "counter" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "counter" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ { in_COUNTER_DATA = new SC_IN (Tdata_t) * [_param._nb_port]; @@ -64,9 +63,11 @@ } } + #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ log_printf(FUNC,Counter,"allocation","End"); }; @@ -77,3 +78,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_deallocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -19,11 +18,14 @@ log_printf(FUNC,Counter,"deallocation","Begin"); - delete in_CLOCK; - delete in_NRESET; - - delete [] in_COUNTER_DATA ; - delete [] in_COUNTER_ADDSUB; - delete [] out_COUNTER_DATA ; - + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK; + delete in_NRESET; + + delete [] in_COUNTER_DATA ; + delete [] in_COUNTER_ADDSUB; + delete [] out_COUNTER_DATA ; + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -38,3 +40,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Counter_end_cycle.cpp (revision 88) @@ -20,5 +20,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -26,5 +27,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Counter/src/Parameters.cpp (revision 88) @@ -25,13 +25,13 @@ }; - Parameters::Parameters (Parameters & param): - _size_data(param._size_data), - _nb_port (param._nb_port ), - _data_max (param._data_max ) - { - log_printf(FUNC,Counter,"Parameters","Begin"); - test(); - log_printf(FUNC,Counter,"Parameters","End"); - }; +// Parameters::Parameters (Parameters & param): +// _size_data(param._size_data), +// _nb_port (param._nb_port ), +// _data_max (param._data_max ) +// { +// log_printf(FUNC,Counter,"Parameters","Begin"); +// test(); +// log_printf(FUNC,Counter,"Parameters","End"); +// }; Parameters::~Parameters () @@ -41,7 +41,12 @@ }; + void Parameters::copy (void) + { + log_printf(FUNC,Counter,"copy","Begin"); + log_printf(FUNC,Counter,"copy","End"); + }; + }; // end namespace counter }; // end namespace generic - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libPriority.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = ../../.. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/Makefile.deps (revision 88) @@ -0,0 +1,37 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Priority = yes +ifndef Common +include $(DIR_MORPHEO)/Common/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Priority_DIR = $(DIR_MORPHEO)/Behavioural/Generic/Priority + +#-----[ Library ]------------------------------------------ + +Priority_LIBRARY = -lPriority\ + $(Common_LIBRARY) + +Priority_DIR_LIBRARY = -L$(Priority_DIR)/lib\ + $(Common_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Priority_library : + @\ + $(MAKE) --directory=$(Priority_DIR) --makefile=Makefile;\ + $(MAKE) Common_library; + +Priority_library_clean : + @\ + $(MAKE) --directory=$(Priority_DIR) --makefile=Makefile clean;\ + $(MAKE) Common_library_clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/Makefile (revision 88) @@ -0,0 +1,32 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Priority_LIBRARY) + +DIR_LIBRARY = $(Priority_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Priority_library + +library_clean : Priority_library_clean + +local_clean : + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_mono_gpr.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_mono_gpr.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_mono_gpr.cfg (revision 88) @@ -0,0 +1,6 @@ +Priority +0 1 +1 # priority +0 1 +1 # load_balancing +1 1 +1 # nb_grp +1 16 *4 # nb_elt [0] [nb_grp] +1 1 +1 # nb_grp_select Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_multi_gpr.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_multi_gpr.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/config_multi_gpr.cfg (revision 88) @@ -0,0 +1,9 @@ +Priority +0 1 +1 # priority +0 1 +1 # load_balancing +4 4 +1 # nb_grp +4 4 *4 # nb_elt [0] [nb_grp] +1 1 *4 # nb_elt [1] [nb_grp] +16 16 *4 # nb_elt [2] [nb_grp] +2 2 *4 # nb_elt [3] [nb_grp] +1 4 +1 # nb_grp_select Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/include/test.h (revision 88) @@ -0,0 +1,24 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 1 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "Behavioural/Generic/Priority/include/Priority.h" + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural; +using namespace morpheo::behavioural::generic; +using namespace morpheo::behavioural::generic::priority; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,102 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/SelfTest/include/test.h" + +#define NB_PARAMS 4 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * priority (Tpriority_t )\n")); + err (_(" * load_balancing (Tload_balancing_t)\n")); + err (_(" * nb_grp (uint32_t )\n")); + err (_(" * nb_elt [nb_grp] (uint32_t )\n")); + err (_(" * nb_grp_select (uint32_t )\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + if (argc <= static_cast(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + Tpriority_t _priority = fromString(argv[x++]); + Tload_balancing_t _load_balancing = fromString(argv[x++]); + + uint32_t _nb_grp = fromString(argv[x++]); + + if (argc != static_cast(2+NB_PARAMS+_nb_grp)) + usage (argc, argv); + + uint32_t * _nb_elt = new uint32_t [_nb_grp]; + for (uint32_t i=0; i<_nb_grp; i++) + _nb_elt [i] = fromString(argv[x++]); + + uint32_t _nb_grp_select = fromString(argv[x++]); + + int _return = EXIT_SUCCESS; + try + { + Priority * _Priority = new Priority + (name.c_str(), + _priority, + _load_balancing, + _nb_grp , + _nb_elt , + _nb_grp_select); + + _Priority->reset(); + + + std::list * select; + + for (uint32_t i=0; i<32; i++) + { + msg("Iteration [%d]\n",i); + _Priority->transition(); + select = _Priority->select(); + for (std::list::iterator it = select->begin(); + it != select->end(); + it ++) + { + msg(" - [%d] %d\n",(*it).grp, (*it).elt); + } + } + + delete _Priority; + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Priority : no error"); + else + TEST_KO("Priority : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Priority.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Priority.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/Priority.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Priority} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Priority.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Priority.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Priority.h (revision 88) @@ -0,0 +1,98 @@ +#ifndef morpheo_behavioural_generic_priority_Priority_h +#define morpheo_behavioural_generic_priority_Priority_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Types.h" +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" +#include +#include + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + + + class Priority + { + // -----[ fields ]---------------------------------------------------- + // Parameters + protected: const std::string _name ; + private : Tpriority_t _priority ; + private : Tload_balancing_t _load_balancing; + private : uint32_t _nb_grp ; + private : uint32_t * _nb_elt ;//[nb_grp] + private : uint32_t _nb_grp_select ; + private : uint32_t _max_nb_elt ; + + private : void (morpheo::behavioural::generic::priority::Priority::*reset_priority ) (void); + private : void (morpheo::behavioural::generic::priority::Priority::*reset_load_balancing ) (void); + + private : void (morpheo::behavioural::generic::priority::Priority::*transition_priority ) (void); + private : void (morpheo::behavioural::generic::priority::Priority::*transition_load_balancing) (void); + + private : uint32_t reg_GRP_PRIORITY; + private : std::list _select; + + // -----[ method ]---------------------------------------------------- + public : Priority (std::string name, + Tpriority_t priority , + Tload_balancing_t load_balancing, + uint32_t nb_grp , + uint32_t * nb_elt ,//[nb_grp] + uint32_t nb_grp_select + ); + public : Priority (std::string name, + Tpriority_t priority , + uint32_t nb_grp , + uint32_t nb_grp_select + ); + + public : Priority (std::string name, + Tpriority_t priority , + uint32_t nb_grp + ); + + public : ~Priority (void); + + public : void allocation (void); + public : void deallocation (void); + + public : void reset (void); + public : void transition (void); + + public : void reset_priority_none (void); + public : void reset_priority_static (void); + public : void reset_priority_round_robin (void); + + public : void reset_load_balancing_none (void); + public : void reset_load_balancing_priority_only (void); + public : void reset_load_balancing_balance (void); + public : void reset_load_balancing_maximum_for_priority (void); + + public : void transition_priority_none (void); + public : void transition_priority_static (void); + public : void transition_priority_round_robin (void); + + public : void transition_load_balancing_none (void); + public : void transition_load_balancing_priority_only (void); + public : void transition_load_balancing_balance (void); + public : void transition_load_balancing_maximum_for_priority (void); + + public : std::list * select (void); + }; + +}; // end namespace priority +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/include/Types.h (revision 88) @@ -0,0 +1,36 @@ +#ifndef morpheo_behavioural_generic_priority_Types_h +#define morpheo_behavioural_generic_priority_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + + class select_t + { + public : uint32_t grp ; + public : uint32_t elt; + + public : select_t (uint32_t grp, + uint32_t elt) + { + this->grp = grp; + this->elt = elt; + } + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority.cpp (revision 88) @@ -0,0 +1,101 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" +#include "Common/include/Max.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::Priority" + Priority::Priority (std::string name, + Tpriority_t priority , + Tload_balancing_t load_balancing, + uint32_t nb_grp , + uint32_t * nb_elt ,//[nb_grp] + uint32_t nb_grp_select + ): + _name (name) + { + log_begin(Priority,FUNCTION); + + _priority = priority ; + _load_balancing = load_balancing; + _nb_grp = nb_grp ; + _nb_elt = nb_elt ; + _nb_grp_select = nb_grp_select ; + _max_nb_elt = max(_nb_elt,_nb_grp); + + allocation(); + + log_end(Priority,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Priority::Priority" + Priority::Priority (std::string name, + Tpriority_t priority , + uint32_t nb_grp , + uint32_t nb_grp_select + ): + _name (name) + { + log_begin(Priority,FUNCTION); + + _priority = priority ; + _load_balancing = LOAD_BALANCING_MAXIMUM_FOR_PRIORITY; + _nb_grp = nb_grp ; +// _nb_elt = nb_elt ; + _nb_grp_select = nb_grp_select ; + _max_nb_elt = 1; + + allocation(); + + log_end(Priority,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Priority::Priority" + Priority::Priority (std::string name, + Tpriority_t priority , + uint32_t nb_grp + ): + _name (name) + { + log_begin(Priority,FUNCTION); + + _priority = priority ; + _load_balancing = LOAD_BALANCING_MAXIMUM_FOR_PRIORITY; + _nb_grp = nb_grp ; +// _nb_elt = nb_elt ; + _nb_grp_select = nb_grp ; + _max_nb_elt = 1; + + allocation(); + + log_end(Priority,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Priority::~Priority" + Priority::~Priority (void) + { + log_begin(Priority,FUNCTION); + + deallocation (); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_allocation.cpp (revision 88) @@ -0,0 +1,70 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::allocation" + void Priority::allocation (void) + { + log_begin(Priority,FUNCTION); + + if (_nb_grp == 1) + { + reset_priority = &morpheo::behavioural::generic::priority::Priority::reset_priority_none ; + transition_priority = &morpheo::behavioural::generic::priority::Priority::transition_priority_none; + } + else + switch (_priority) + { + case PRIORITY_STATIC : {reset_priority = &morpheo::behavioural::generic::priority::Priority::reset_priority_static ; + transition_priority = &morpheo::behavioural::generic::priority::Priority::transition_priority_static ; + break;} + case PRIORITY_ROUND_ROBIN : {reset_priority = &morpheo::behavioural::generic::priority::Priority::reset_priority_round_robin ; + transition_priority = &morpheo::behavioural::generic::priority::Priority::transition_priority_round_robin; + break;} + default: {throw ERRORMORPHEO(FUNCTION,_("Unknow Priority scheme.\n"));} + } + + if ((_max_nb_elt == 1) and (_nb_grp_select == 1)) + { + reset_load_balancing = &morpheo::behavioural::generic::priority::Priority::reset_load_balancing_none; + transition_load_balancing = &morpheo::behavioural::generic::priority::Priority::transition_load_balancing_none; + } + else + { + if (_max_nb_elt == 1) + { + reset_load_balancing = &morpheo::behavioural::generic::priority::Priority::reset_load_balancing_priority_only; + transition_load_balancing = &morpheo::behavioural::generic::priority::Priority::transition_load_balancing_priority_only; + } + else + switch (_load_balancing) + { + case LOAD_BALANCING_BALANCE : {reset_load_balancing = &morpheo::behavioural::generic::priority::Priority::reset_load_balancing_balance ; + transition_load_balancing = &morpheo::behavioural::generic::priority::Priority::transition_load_balancing_balance ; + break;} + case LOAD_BALANCING_MAXIMUM_FOR_PRIORITY : {reset_load_balancing = &morpheo::behavioural::generic::priority::Priority::reset_load_balancing_maximum_for_priority ; + transition_load_balancing = &morpheo::behavioural::generic::priority::Priority::transition_load_balancing_maximum_for_priority; + break;} + default: {throw ERRORMORPHEO(FUNCTION,_("Unknow Load Balancing scheme.\n"));} + } + } + + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_deallocation.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::deallocation" + void Priority::deallocation (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset.cpp (revision 88) @@ -0,0 +1,30 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset" + void Priority::reset (void) + { + log_begin(Priority,FUNCTION); + + (this->*reset_priority ) (); + (this->*reset_load_balancing) (); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_balance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_balance.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_balance.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_load_balancing_balance" + void Priority::reset_load_balancing_balance (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_maximum_for_priority.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_maximum_for_priority.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_maximum_for_priority.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_load_balancing_maximum_for_priority" + void Priority::reset_load_balancing_maximum_for_priority (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_none.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_none.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_none.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_load_balancing_none" + void Priority::reset_load_balancing_none (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_priority_only.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_priority_only.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_load_balancing_priority_only.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_load_balancing_priority_only" + void Priority::reset_load_balancing_priority_only (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_none.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_none.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_none.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_priority_none" + void Priority::reset_priority_none (void) + { + log_begin(Priority,FUNCTION); + + reg_GRP_PRIORITY = 0; + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_round_robin.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_round_robin.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_round_robin.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_priority_round_robin" + void Priority::reset_priority_round_robin (void) + { + log_begin(Priority,FUNCTION); + + reg_GRP_PRIORITY = 0; + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_static.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_static.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_reset_priority_static.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::reset_priority_static" + void Priority::reset_priority_static (void) + { + log_begin(Priority,FUNCTION); + + reg_GRP_PRIORITY = 0; + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_select.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_select.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_select.cpp (revision 88) @@ -0,0 +1,31 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::select" + std::list * Priority::select (void) + { + log_begin(Priority,FUNCTION); + + std::list * _return = &_select; + + log_end(Priority,FUNCTION); + + return _return; + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition.cpp (revision 88) @@ -0,0 +1,31 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition" + void Priority::transition (void) + { + log_begin(Priority,FUNCTION); + + (this->*transition_priority ) (); + _select.clear(); // flush list + (this->*transition_load_balancing) (); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_balance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_balance.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_balance.cpp (revision 88) @@ -0,0 +1,37 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_load_balancing_balance" + void Priority::transition_load_balancing_balance (void) + { + log_begin(Priority,FUNCTION); + + for (uint32_t j=0; j<_max_nb_elt; j++) + for (uint32_t i=0; i<_nb_grp_select; i++) + { + uint32_t x=(reg_GRP_PRIORITY+i)%_nb_grp; + + // Test valid elt + if (j < _nb_elt[x]) + _select.push_back(select_t(x,j)); + } + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_maximum_for_priority.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_maximum_for_priority.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_maximum_for_priority.cpp (revision 88) @@ -0,0 +1,35 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_load_balancing_maximum_for_priority" + void Priority::transition_load_balancing_maximum_for_priority (void) + { + log_begin(Priority,FUNCTION); + + for (uint32_t i=0; i<_nb_grp_select; i++) + { + uint32_t x=(reg_GRP_PRIORITY+i)%_nb_grp; + + for (uint32_t j=0; j<_nb_elt[x]; j++) + _select.push_back(select_t(x,j)); + } + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_none.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_none.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_none.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_load_balancing_none" + void Priority::transition_load_balancing_none (void) + { + log_begin(Priority,FUNCTION); + + _select.push_back(select_t(reg_GRP_PRIORITY,0)); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_priority_only.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_priority_only.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_load_balancing_priority_only.cpp (revision 88) @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_load_balancing_priority_only" + void Priority::transition_load_balancing_priority_only (void) + { + log_begin(Priority,FUNCTION); + + for (uint32_t i=0; i<_nb_grp_select; i++) + { + uint32_t x=(reg_GRP_PRIORITY+i)%_nb_grp; + + _select.push_back(select_t(x,0)); + } + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_none.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_none.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_none.cpp (revision 88) @@ -0,0 +1,27 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_priority_none" + void Priority::transition_priority_none (void) + { + log_begin(Priority,FUNCTION); + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_round_robin.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_round_robin.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_round_robin.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_priority_round_robin" + void Priority::transition_priority_round_robin (void) + { + log_begin(Priority,FUNCTION); + + reg_GRP_PRIORITY = (reg_GRP_PRIORITY+1)%_nb_grp; + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_static.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_static.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Priority/src/Priority_transition_priority_static.cpp (revision 88) @@ -0,0 +1,29 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Priority/include/Priority.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace priority { + +#undef FUNCTION +#define FUNCTION "Priority::transition_priority_static" + void Priority::transition_priority_static (void) + { + log_begin(Priority,FUNCTION); + + reg_GRP_PRIORITY = (reg_GRP_PRIORITY+_nb_grp_select)%_nb_grp; + + log_end(Priority,FUNCTION); + }; + +}; // end namespace priority +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Queue_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/SelfTest/src/test.cpp (revision 88) @@ -22,4 +22,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Queue * _Queue = new Queue (name.c_str(), @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/include/Parameters.h (revision 88) @@ -29,6 +29,8 @@ public : Parameters (uint32_t size_queue, uint32_t size_data ); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + + public : void copy (void); public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Parameters.cpp (revision 88) @@ -26,18 +26,26 @@ }; +// #undef FUNCTION +// #define FUNCTION "Queue::Parameters (copy)" +// Parameters::Parameters (Parameters & param): +// _size_queue (param._size_queue), +// _size_data (param._size_data ) +// { +// log_printf(FUNC,Queue,FUNCTION,"Begin"); +// test(); +// log_printf(FUNC,Queue,FUNCTION,"End"); +// }; + #undef FUNCTION -#define FUNCTION "Queue::Parameters (copy)" - Parameters::Parameters (Parameters & param): - _size_queue (param._size_queue), - _size_data (param._size_data ) +#define FUNCTION "Queue::~Parameters" + Parameters::~Parameters () { log_printf(FUNC,Queue,FUNCTION,"Begin"); - test(); log_printf(FUNC,Queue,FUNCTION,"End"); }; #undef FUNCTION -#define FUNCTION "Queue::~Parameters" - Parameters::~Parameters () +#define FUNCTION "Queue::copy" + void Parameters::copy (void) { log_printf(FUNC,Queue,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue.cpp (revision 88) @@ -35,9 +35,15 @@ log_printf(FUNC,Queue,FUNCTION,"Begin"); +#if DEBUG_Core == true + log_printf(INFO,Core,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Queue,FUNCTION,"Allocation"); allocation (); #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Queue,FUNCTION,"Allocation of statistics"); @@ -48,5 +54,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -58,5 +64,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Queue,FUNCTION,"Method - transition"); @@ -92,5 +98,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Queue,FUNCTION,"Generate Statistics file"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_allocation.cpp (revision 88) @@ -75,12 +75,16 @@ } + if (usage_is_set(_usage,USE_SYSTEMC)) + { // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ _queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control::Queue_Control(_param->_size_queue); _queue_data = new Tdata_t [_param->_size_queue]; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_deallocation.cpp (revision 88) @@ -20,5 +20,5 @@ log_printf(FUNC,Queue,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; @@ -33,8 +33,9 @@ delete out_RETIRE_DATA; + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + delete _queue_control; + delete _queue_data; } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete _queue_control; - delete _queue_data; + delete _component; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Queue/src/Queue_end_cycle.cpp (revision 88) @@ -21,5 +21,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -27,5 +28,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/Makefile (revision 88) @@ -23,4 +23,6 @@ library_clean : RegisterFile_Monolithic_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/debug.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/debug.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/debug.cfg (revision 88) @@ -0,0 +1,6 @@ +RegisterFile_Monolithic +1 1 *2 # nb_port_read +1 1 *2 # nb_port_write +0 0 *2 # nb_port_read_write +128 128 *2 # nb_word +32 32 *2 # size_word Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp (revision 88) @@ -32,4 +32,14 @@ exit (EXIT_FAILURE); } + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); #ifdef STATISTICS @@ -42,5 +52,5 @@ #endif ,_param - ,USE_ALL); + ,_usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/Parameters.h (revision 88) @@ -34,8 +34,11 @@ uint32_t nb_word , uint32_t size_word ); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/Parameters.cpp (revision 88) @@ -32,18 +32,23 @@ }; - Parameters::Parameters (Parameters & param) : - _nb_port_read (param._nb_port_read ), - _nb_port_write (param._nb_port_write), - _nb_port_read_write(param._nb_port_read_write), - _nb_word (param._nb_word ), - _size_word (param._size_word ), - _size_address (param._size_address ), - _have_port_address (param._have_port_address) +// Parameters::Parameters (Parameters & param) : +// _nb_port_read (param._nb_port_read ), +// _nb_port_write (param._nb_port_write), +// _nb_port_read_write(param._nb_port_read_write), +// _nb_word (param._nb_word ), +// _size_word (param._size_word ), +// _size_address (param._size_address ), +// _have_port_address (param._have_port_address) +// { +// test(); +// }; + + Parameters::~Parameters () { - test(); }; - Parameters::~Parameters () - { }; + void Parameters::copy (void) + { + }; }; // end namespace registerfile_monolithic Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 88) @@ -33,9 +33,15 @@ log_printf(FUNC,RegisterFile_Monolithic,"RegisterFile_Monolithic","Begin"); +#if DEBUG_RegisterFile_Monolithic == true + log_printf(INFO,RegisterFile_Monolithic,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,RegisterFile_Monolithic,"RegisterFile_Monolithic","Allocation"); allocation (); #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) statistics_declaration(param_statistics); #endif @@ -47,5 +53,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { SC_METHOD (transition); @@ -102,5 +108,5 @@ { #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) delete _stat; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp (revision 88) @@ -120,8 +120,10 @@ // ----- Register - reg_DATA = new Tdata_t [_param->_nb_word]; + if (usage_is_set(_usage,USE_SYSTEMC)) + reg_DATA = new Tdata_t [_param->_nb_word]; #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_deallocation.cpp (revision 88) @@ -18,5 +18,5 @@ delete _component; - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_end_cycle.cpp (revision 88) @@ -20,5 +20,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -27,5 +28,6 @@ // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp (revision 88) @@ -24,5 +24,6 @@ { #ifdef STATISTICS - (*_stat_nb_write) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_write) ++; #endif @@ -49,5 +50,6 @@ { #ifdef STATISTICS - (*_stat_nb_write) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_write) ++; #endif @@ -67,5 +69,6 @@ else { - (*_stat_nb_read) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_read) ++; } #endif @@ -74,7 +77,8 @@ #ifdef STATISTICS - for (uint32_t i=0; i<_param->_nb_port_read; i++) - if ( PORT_READ(in_READ_VAL [i]) == 1) - (*_stat_nb_read) ++; + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_port_read; i++) + if ( PORT_READ(in_READ_VAL [i]) == 1) + (*_stat_nb_read) ++; #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : RegisterFile_Multi_Banked_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + RegisterFile_Multi_Banked * _RegisterFile_Multi_Banked = new RegisterFile_Multi_Banked (name.c_str(), @@ -29,5 +39,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/Parameters.h (revision 88) @@ -61,11 +61,14 @@ uint32_t nb_port_write_by_bank, Tcrossbar_t crossbar ); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); - public : std::string print (uint32_t depth); - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters & x); + + public : std::string print (uint32_t depth); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h (revision 88) @@ -106,8 +106,8 @@ public : ~RegisterFile_Multi_Banked (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC private : Taddress_t address_bank (Taddress_t address); private : Taddress_t address_num_reg (Taddress_t address); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/Parameters.cpp (revision 88) @@ -87,49 +87,49 @@ }; - Parameters::Parameters (Parameters & param): - _nb_port_read (param._nb_port_read ), - _nb_port_write (param._nb_port_write ), - _nb_word (param._nb_word ), - _size_word (param._size_word ), - _nb_bank (param._nb_bank ), - _nb_port_read_by_bank (param._nb_port_read_by_bank ), - _nb_port_write_by_bank (param._nb_port_write_by_bank), - _crossbar (param._crossbar ), - _size_address (param._size_address ), - _size_address_by_bank (param._size_address_by_bank ), - _bank_shift (param._bank_shift ), - _bank_mask (param._bank_mask ), - _num_reg_shift (param._num_reg_shift ), - _num_reg_mask (param._num_reg_mask ), - _nb_word_by_bank (param._nb_word_by_bank ), - _have_port_address (param._have_port_address ), - _have_bank_port_address(param._have_bank_port_address) - { - log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","Begin"); +// Parameters::Parameters (Parameters & param): +// _nb_port_read (param._nb_port_read ), +// _nb_port_write (param._nb_port_write ), +// _nb_word (param._nb_word ), +// _size_word (param._size_word ), +// _nb_bank (param._nb_bank ), +// _nb_port_read_by_bank (param._nb_port_read_by_bank ), +// _nb_port_write_by_bank (param._nb_port_write_by_bank), +// _crossbar (param._crossbar ), +// _size_address (param._size_address ), +// _size_address_by_bank (param._size_address_by_bank ), +// _bank_shift (param._bank_shift ), +// _bank_mask (param._bank_mask ), +// _num_reg_shift (param._num_reg_shift ), +// _num_reg_mask (param._num_reg_mask ), +// _nb_word_by_bank (param._nb_word_by_bank ), +// _have_port_address (param._have_port_address ), +// _have_bank_port_address(param._have_bank_port_address) +// { +// log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","Begin"); - if (_crossbar == PARTIAL_CROSSBAR) - { - // All port_src is connected with one port_dest on each bank +// if (_crossbar == PARTIAL_CROSSBAR) +// { +// // All port_src is connected with one port_dest on each bank - _link_port_read_to_bank_read = new uint32_t [_nb_port_read ]; -// _link_port_read_to_num_bank = new uint32_t [_nb_port_read ]; - _link_port_write_to_bank_write = new uint32_t [_nb_port_write]; -// _link_port_write_to_num_bank = new uint32_t [_nb_port_write]; +// _link_port_read_to_bank_read = new uint32_t [_nb_port_read ]; +// // _link_port_read_to_num_bank = new uint32_t [_nb_port_read ]; +// _link_port_write_to_bank_write = new uint32_t [_nb_port_write]; +// // _link_port_write_to_num_bank = new uint32_t [_nb_port_write]; - for (uint32_t i=0; i<_nb_port_read ;i++) - { - _link_port_read_to_bank_read [i] = param._link_port_read_to_bank_read [i]; -// _link_port_read_to_num_bank [i] = param._link_port_read_to_num_bank [i]; - } - for (uint32_t i=0; i<_nb_port_write ;i++) - { - _link_port_write_to_bank_write [i] = param._link_port_write_to_bank_write [i]; -// _link_port_write_to_num_bank [i] = param._link_port_write_to_num_bank [i]; - } - } +// for (uint32_t i=0; i<_nb_port_read ;i++) +// { +// _link_port_read_to_bank_read [i] = param._link_port_read_to_bank_read [i]; +// // _link_port_read_to_num_bank [i] = param._link_port_read_to_num_bank [i]; +// } +// for (uint32_t i=0; i<_nb_port_write ;i++) +// { +// _link_port_write_to_bank_write [i] = param._link_port_write_to_bank_write [i]; +// // _link_port_write_to_num_bank [i] = param._link_port_write_to_num_bank [i]; +// } +// } - test(); - log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","End"); - }; +// test(); +// log_printf(FUNC,RegisterFile_Multi_Banked,"Parameters (copy)","End"); +// }; Parameters::~Parameters () @@ -147,4 +147,10 @@ }; + void Parameters::copy (void) + { + log_printf(FUNC,RegisterFile_Multi_Banked,"copy","Begin"); + log_printf(FUNC,RegisterFile_Multi_Banked,"copy","End"); + }; + }; // end namespace registerfile_multi_banked }; // end namespace registerfile Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp (revision 88) @@ -14,4 +14,6 @@ namespace registerfile_multi_banked { +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::RegisterFile_Multi_Banked" RegisterFile_Multi_Banked::RegisterFile_Multi_Banked ( @@ -30,27 +32,39 @@ ,_usage (usage) { - log_printf(FUNC,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Begin"); + log_printf(FUNC,RegisterFile_Multi_Banked,FUNCTION,"Begin"); -#ifdef SYSTEMC - log_printf(INFO,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Allocation"); +#if DEBUG_RegisterFile_Multi_Banked == true + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,_("<%s> Parameters"),_name.c_str()); + std::cout << *param << std::endl; +#endif + + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Allocation"); + allocation (); -#endif #ifdef STATISTICS - log_printf(INFO,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Allocation of statistics"); - - // Allocation of statistics - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Allocation of statistics"); + + // Allocation of statistics + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(INFO,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Generate the vhdl"); - - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Generate the vhdl"); + + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { // Function pointer if (_param->_crossbar == FULL_CROSSBAR) @@ -67,5 +81,5 @@ } - log_printf(INFO,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Method - transition"); + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Method - transition"); SC_METHOD (transition); @@ -77,5 +91,5 @@ #endif - log_printf(INFO,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","Method - genMealy_write"); + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Method - genMealy_write"); SC_METHOD (genMealy_read); @@ -129,26 +143,27 @@ } #endif - + } #endif - log_printf(FUNC,RegisterFile_Multi_Banked,"RegisterFile_Multi_Banked","End"); + log_printf(FUNC,RegisterFile_Multi_Banked,FUNCTION,"End"); }; +#undef FUNCTION +#define FUNCTION "RegisterFile_Multi_Banked::~RegisterFile_Multi_Banked" RegisterFile_Multi_Banked::~RegisterFile_Multi_Banked (void) { - log_printf(FUNC,RegisterFile_Multi_Banked,"~RegisterFile_Multi_Banked","Begin"); + log_printf(FUNC,RegisterFile_Multi_Banked,FUNCTION,"Begin"); #ifdef STATISTICS - log_printf(INFO,RegisterFile_Multi_Banked,"~RegisterFile_Multi_Banked","Generate Statistics file"); - - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Generate Statistics file"); + delete _stat; + } #endif -#ifdef SYSTEMC - log_printf(INFO,RegisterFile_Multi_Banked,"~RegisterFile_Multi_Banked","Deallocation"); + log_printf(INFO,RegisterFile_Multi_Banked,FUNCTION,"Deallocation"); + deallocation (); - deallocation (); -#endif - - log_printf(FUNC,RegisterFile_Multi_Banked,"~RegisterFile_Multi_Banked","End"); + log_printf(FUNC,RegisterFile_Multi_Banked,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_allocation.cpp (revision 88) @@ -1,7 +1,6 @@ -#ifdef SYSTEMC /* * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -31,5 +30,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Interface * interface = _interfaces->set_interface("" @@ -44,5 +43,5 @@ in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); - // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; @@ -69,5 +68,5 @@ } - // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; @@ -94,5 +93,7 @@ } - // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (usage_is_set(_usage,USE_SYSTEMC)) + { + // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ reg_DATA = new Tdata_t * [_param->_nb_bank]; @@ -103,13 +104,15 @@ } - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ internal_WRITE_VAL = new bool [_param->_nb_port_write]; internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; + } - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif @@ -123,3 +126,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_deallocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -20,28 +19,31 @@ log_printf(FUNC,RegisterFile_Multi_Banked,"deallocation","Begin"); - delete in_CLOCK; - delete in_NRESET; - - // ----- Interface Read - delete [] in_READ_VAL ; - delete [] out_READ_ACK ; - if (_param->_have_port_address == true) - delete [] in_READ_ADDRESS; - delete [] out_READ_DATA ; - - // ----- Interface Write - delete [] in_WRITE_VAL ; - delete [] out_WRITE_ACK ; - if (_param->_have_port_address == true) - delete [] in_WRITE_ADDRESS; - delete [] in_WRITE_DATA ; - - // ----- Register - delete [] reg_DATA; - - // ----- Internal - delete [] internal_WRITE_VAL; - delete [] internal_WRITE_BANK; - delete [] internal_WRITE_NUM_REG; + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK; + delete in_NRESET; + + // ----- Interface Read + delete [] in_READ_VAL ; + delete [] out_READ_ACK ; + if (_param->_have_port_address == true) + delete [] in_READ_ADDRESS; + delete [] out_READ_DATA ; + + // ----- Interface Write + delete [] in_WRITE_VAL ; + delete [] out_WRITE_ACK ; + if (_param->_have_port_address == true) + delete [] in_WRITE_ADDRESS; + delete [] in_WRITE_DATA ; + + // ----- Register + delete [] reg_DATA; + + // ----- Internal + delete [] internal_WRITE_VAL; + delete [] internal_WRITE_BANK; + delete [] internal_WRITE_NUM_REG; + } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -58,3 +60,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_end_cycle.cpp (revision 88) @@ -23,5 +23,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -29,5 +30,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : RegisterFile_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/main.cpp (revision 88) @@ -58,9 +58,11 @@ if (instance == instance_RegisterFile_Monolithic) { - morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters * param1 = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters (nb_port_read , - nb_port_write , - 0 , - nb_word , - size_word ); + morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters * param1 = new morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters + (nb_port_read , + nb_port_write , + 0 , + nb_word , + size_word + ); param = new morpheo::behavioural::generic::registerfile::Parameters(param1); @@ -68,12 +70,14 @@ else { - morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param2 = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters (nb_port_read , - nb_port_write , - nb_word , - size_word , - nb_bank , - nb_port_read_by_bank , - nb_port_write_by_bank, - crossbar ); + morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param2 = new morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters + (nb_port_read , + nb_port_write , + nb_word , + size_word , + nb_bank , + nb_port_read_by_bank , + nb_port_write_by_bank, + crossbar + ); param = new morpheo::behavioural::generic::registerfile::Parameters(param2); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/SelfTest/src/test.cpp (revision 88) @@ -22,4 +22,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + RegisterFile * _RegisterFile = new RegisterFile (name.c_str(), #ifdef STATISTICS @@ -27,5 +37,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/include/Parameters.h (revision 88) @@ -40,8 +40,11 @@ public : Parameters (morpheo::behavioural::generic::registerfile::registerfile_monolithic ::Parameters * param); public : Parameters (morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/src/Parameters.cpp (revision 88) @@ -26,5 +26,6 @@ _param_registerfile_monolithic = param; - + _param_registerfile_multi_banked = NULL; + test(); @@ -43,4 +44,5 @@ log_printf(FUNC,RegisterFile,"Parameters","Begin"); + _param_registerfile_monolithic = NULL; _param_registerfile_multi_banked = param; @@ -50,20 +52,20 @@ }; - Parameters::Parameters (Parameters & param): - _instance (param._instance ), - _nb_port_read (param._nb_port_read ), - _nb_port_write (param._nb_port_write), - _nb_word (param._nb_word ), - _size_word (param._size_word ), - _size_address (param._size_address ), - _have_port_address (param._have_port_address) - { - log_printf(FUNC,RegisterFile,"Parameters (copy)","Begin"); +// Parameters::Parameters (Parameters & param): +// _instance (param._instance ), +// _nb_port_read (param._nb_port_read ), +// _nb_port_write (param._nb_port_write), +// _nb_word (param._nb_word ), +// _size_word (param._size_word ), +// _size_address (param._size_address ), +// _have_port_address (param._have_port_address) +// { +// log_printf(FUNC,RegisterFile,"Parameters (copy)","Begin"); - _param_registerfile_multi_banked = param._param_registerfile_multi_banked; - _param_registerfile_monolithic = param._param_registerfile_monolithic; - test(); - log_printf(FUNC,RegisterFile,"Parameters (copy)","End"); - }; +// _param_registerfile_multi_banked = param._param_registerfile_multi_banked; +// _param_registerfile_monolithic = param._param_registerfile_monolithic; +// test(); +// log_printf(FUNC,RegisterFile,"Parameters (copy)","End"); +// }; Parameters::~Parameters () @@ -73,4 +75,18 @@ }; + void Parameters::copy (void) + { + log_printf(FUNC,RegisterFile,"copy","Begin"); + + throw ERRORMORPHEO("RegisterFile::copy",_("Invalid copy")); + +// if (_instance == instance_RegisterFile_Monolithic) +// COPY(_param_registerfile_monolithic); +// if (_instance == instance_RegisterFile_Multi_Banked) +// COPY(_param_registerfile_multi_banked); + + log_printf(FUNC,RegisterFile,"copy","End"); + }; + }; // end namespace registerfile }; // end namespace generic Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/Makefile (revision 88) @@ -23,4 +23,6 @@ library_clean : Select_Priority_Fixed_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 88) @@ -18,8 +18,18 @@ cout << "<" << name << "> : Simulation SystemC" << endl; - #ifdef STATISTICS morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,50); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Select_Priority_Fixed * _Select_Priority_Fixed = new Select_Priority_Fixed (name.c_str(), @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Parameters.h (revision 88) @@ -31,8 +31,11 @@ bool encoding_one_hot, bool encoding_compact); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h (revision 88) @@ -95,8 +95,8 @@ public : ~Select_Priority_Fixed (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC # if defined(STATISTICS) or defined(VHDL_TESTBENCH) public : void transition (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Parameters.cpp (revision 88) @@ -28,14 +28,14 @@ }; - Parameters::Parameters (Parameters & param): - _nb_entity (param._nb_entity ), - _encoding_one_hot (param._encoding_one_hot), - _encoding_compact (param._encoding_compact), - _size_entity (param._size_entity ) - { - log_printf(FUNC,Select_Priority_Fixed,"Parameters","Begin"); - test(); - log_printf(FUNC,Select_Priority_Fixed,"Parameters","End"); - }; +// Parameters::Parameters (Parameters & param): +// _nb_entity (param._nb_entity ), +// _encoding_one_hot (param._encoding_one_hot), +// _encoding_compact (param._encoding_compact), +// _size_entity (param._size_entity ) +// { +// log_printf(FUNC,Select_Priority_Fixed,"Parameters","Begin"); +// test(); +// log_printf(FUNC,Select_Priority_Fixed,"Parameters","End"); +// }; Parameters::~Parameters () @@ -43,4 +43,10 @@ log_printf(FUNC,Select_Priority_Fixed,"~Parameters","Begin"); log_printf(FUNC,Select_Priority_Fixed,"~Parameters","End"); + }; + + void Parameters::copy (void) + { + log_printf(FUNC,Select_Priority_Fixed,"copy","Begin"); + log_printf(FUNC,Select_Priority_Fixed,"copy","End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 88) @@ -2,5 +2,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -33,9 +33,15 @@ log_printf(FUNC,Select_Priority_Fixed,"Select_Priority_Fixed","Begin"); +#if DEBUG_Select_Priority_Fixed == true + log_printf(INFO,Select_Priority_Fixed,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Allocation"); allocation (); #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Allocation of statistics"); @@ -46,13 +52,16 @@ #ifdef VHDL - // generate the vhdl - log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Generate the vhdl"); - - vhdl(); + if (usage_is_set(_usage,USE_VHDL) + { + // generate the vhdl + log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Generate the vhdl"); + + vhdl(); + } #endif #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) - { + if (usage_is_set(_usage,USE_SYSTEMC)) + { # if defined(STATISTICS) or defined(VHDL_TESTBENCH) log_printf(INFO,Select_Priority_Fixed,"Select_Priority_Fixed","Method - transition"); @@ -96,5 +105,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Select_Priority_Fixed,"~Select_Priority_Fixed","Generate Statistics file"); @@ -104,9 +113,6 @@ #endif -#ifdef SYSTEMC log_printf(INFO,Select_Priority_Fixed,"~Select_Priority_Fixed","Deallocation"); - deallocation (); -#endif log_printf(FUNC,Select_Priority_Fixed,"~Select_Priority_Fixed","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_allocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -30,5 +29,5 @@ _interfaces = entity->set_interfaces(); - // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Interface_fifo * interface = _interfaces->set_interface("" @@ -63,5 +62,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif @@ -74,3 +74,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_deallocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -20,5 +19,5 @@ log_printf(FUNC,Select_Priority_Fixed,"deallocation","Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK; @@ -48,3 +47,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed_end_cycle.cpp (revision 88) @@ -22,5 +22,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -28,5 +29,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/Makefile (revision 88) @@ -23,4 +23,6 @@ library_clean : Shifter_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/SelfTest/src/test.cpp (revision 88) @@ -38,4 +38,15 @@ morpheo::behavioural::Parameters_Statistics * param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); #endif + + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); + _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Shifter * _Shifter = new Shifter (name.c_str(), #ifdef STATISTICS @@ -43,5 +54,5 @@ #endif ¶m, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Parameters.h (revision 88) @@ -56,8 +56,11 @@ carry_t carry , bool type_completion_bool = false); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/include/Shifter.h (revision 88) @@ -5,5 +5,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -38,5 +38,5 @@ #endif { - // -----[ fields ]---------------------------------------------------- + // -----[ fields ]---------------------------------------------------- // Parameters protected : const std::string _name; @@ -52,5 +52,5 @@ #ifdef SYSTEMC - // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ public : SC_CLOCK * in_CLOCK ; public : SC_IN (Tcontrol_t) * in_NRESET ; @@ -66,10 +66,10 @@ public : SC_OUT(Tdata_t) ** out_SHIFTER_DATA ; - // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ #endif - // -----[ methods ]--------------------------------------------------- + // -----[ methods ]--------------------------------------------------- #ifdef SYSTEMC @@ -93,8 +93,8 @@ public : ~Shifter (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) public : void transition (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Parameters.cpp (revision 88) @@ -80,38 +80,43 @@ }; - Parameters::Parameters (Parameters & param): - _size_data (param._size_data ), - _nb_port (param._nb_port ), - _shift_value (param._shift_value ), - _rotate (param._rotate ), - _direction (param._direction ), - _carry (param._carry ), - _size_data_completion (param._size_data_completion ), - _type_completion_bool (param._type_completion_bool ), +// Parameters::Parameters (Parameters & param): +// _size_data (param._size_data ), +// _nb_port (param._nb_port ), +// _shift_value (param._shift_value ), +// _rotate (param._rotate ), +// _direction (param._direction ), +// _carry (param._carry ), +// _size_data_completion (param._size_data_completion ), +// _type_completion_bool (param._type_completion_bool ), - _internal_direction (param._internal_direction ), - _internal_type (param._internal_type ), - _internal_carry (param._internal_carry ), +// _internal_direction (param._internal_direction ), +// _internal_type (param._internal_type ), +// _internal_carry (param._internal_carry ), - _have_shift_logic_left (param._have_shift_logic_left ), - _have_shift_logic_right (param._have_shift_logic_right ), - _have_shift_logic (param._have_shift_logic ), - _have_shift_arithmetic_left (param._have_shift_arithmetic_left ), - _have_shift_arithmetic_right (param._have_shift_arithmetic_right ), - _have_shift_arithmetic (param._have_shift_arithmetic ), - _have_shift (param._have_shift ), - _have_rotate_left (param._have_rotate_left ), - _have_rotate_right (param._have_rotate_right ), - _have_rotate (param._have_rotate ), +// _have_shift_logic_left (param._have_shift_logic_left ), +// _have_shift_logic_right (param._have_shift_logic_right ), +// _have_shift_logic (param._have_shift_logic ), +// _have_shift_arithmetic_left (param._have_shift_arithmetic_left ), +// _have_shift_arithmetic_right (param._have_shift_arithmetic_right ), +// _have_shift_arithmetic (param._have_shift_arithmetic ), +// _have_shift (param._have_shift ), +// _have_rotate_left (param._have_rotate_left ), +// _have_rotate_right (param._have_rotate_right ), +// _have_rotate (param._have_rotate ), - _have_direction_left (param._have_direction_left ), - _have_direction_right (param._have_direction_right ) +// _have_direction_left (param._have_direction_left ), +// _have_direction_right (param._have_direction_right ) +// { +// test(); +// }; + + Parameters::~Parameters () { - test(); }; - Parameters::~Parameters () - { }; + void Parameters::copy (void) + { + }; }; // end namespace shifter Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter.cpp (revision 88) @@ -14,4 +14,6 @@ +#undef FUNCTION +#define FUNCTION "Shifter::Shifter" Shifter::Shifter ( #ifdef SYSTEMC @@ -29,19 +31,32 @@ ,_usage (usage) { -#ifdef SYSTEMC + +#if DEBUG_Shifter == true + log_printf(INFO,Shifter,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + allocation (); -#endif #ifdef STATISTICS - // Allocation of statistics - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + // Allocation of statistics + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + vhdl(); + } #endif #ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) SC_METHOD (transition); @@ -91,17 +106,18 @@ } #endif - + } #endif }; +#undef FUNCTION +#define FUNCTION "Shifter::~Shifter" Shifter::~Shifter (void) { -#ifdef SYSTEMC - deallocation (); +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + delete _stat; #endif -#ifdef STATISTICS - delete _stat; -#endif + deallocation (); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_allocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -86,9 +85,10 @@ in_SHIFTER_COMPLETION [i] = interface->set_signal_in ("completion",_param->_size_data_completion); out_SHIFTER_DATA [i] = interface->set_signal_out ("data" ,_param->_size_data); - } + } } #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif @@ -99,3 +99,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_deallocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -17,4 +16,6 @@ void Shifter::deallocation (void) { + if (usage_is_set(_usage,USE_SYSTEMC)) + { #if (defined(STATISTICS) || defined (VHDL_TESTBENCH)) delete in_CLOCK; @@ -36,4 +37,5 @@ delete [] in_SHIFTER_COMPLETION; delete [] out_SHIFTER_DATA ; + } delete _component; @@ -46,3 +48,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Shifter/src/Shifter_end_cycle.cpp (revision 88) @@ -21,5 +21,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -27,5 +28,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Sort_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/SelfTest/src/test.cpp (revision 88) @@ -31,4 +31,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Sort * _Sort = new Sort (name.c_str(), #ifdef STATISTICS @@ -36,5 +46,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC @@ -154,5 +164,5 @@ tab [ptr]._val = false; - LABEL("OUTPUT [%d] %d - %d",i, out_OUTPUT_VAL [i]->read(), out_OUTPUT_DATA [i]->read(), out_OUTPUT_INDEX [i]->read()); + LABEL("OUTPUT [%d] %d %d - %d",i, out_OUTPUT_VAL [i]->read(), out_OUTPUT_DATA [i]->read(), out_OUTPUT_INDEX [i]->read()); TEST(Tcontrol_t,out_OUTPUT_VAL [i]->read(),find); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/include/Parameters.h (revision 88) @@ -42,4 +42,6 @@ public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Parameters.cpp (revision 88) @@ -55,4 +55,12 @@ }; +#undef FUNCTION +#define FUNCTION "Sort::copy" + void Parameters::copy (void) + { + log_printf(FUNC,Sort,FUNCTION,"Begin"); + log_printf(FUNC,Sort,FUNCTION,"End"); + }; + }; // end namespace sort }; // end namespace generic Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort.cpp (revision 88) @@ -35,4 +35,10 @@ log_printf(FUNC,Sort,FUNCTION,"Begin"); +#if DEBUG_Sort == true + log_printf(INFO,Sort,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(INFO,Sort,FUNCTION,"Allocation"); @@ -44,5 +50,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { log_printf(INFO,Sort,FUNCTION,"Allocation of statistics"); @@ -53,5 +59,5 @@ #ifdef VHDL - if (_usage & USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl @@ -63,5 +69,5 @@ #ifdef SYSTEMC - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { log_printf(INFO,Sort,FUNCTION,"Method - transition"); @@ -117,5 +123,5 @@ #ifdef STATISTICS - if (_usage & USE_STATISTICS) + if (usage_is_set(_usage,USE_STATISTICS)) { statistics_deallocation(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_allocation.cpp (revision 88) @@ -13,6 +13,4 @@ namespace generic { namespace sort { - - #undef FUNCTION @@ -75,5 +73,6 @@ #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSTION)) + _component->generate_file(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_deallocation.cpp (revision 88) @@ -20,5 +20,5 @@ log_printf(FUNC,Sort,FUNCTION,"Begin"); - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_end_cycle.cpp (revision 88) @@ -22,5 +22,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -28,5 +29,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : Victim_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/SelfTest/src/test.cpp (revision 88) @@ -23,4 +23,14 @@ #endif + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + Victim * _Victim = new Victim (name.c_str(), #ifdef STATISTICS @@ -28,5 +38,5 @@ #endif _param, - USE_ALL); + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/Makefile (revision 88) @@ -23,4 +23,6 @@ library_clean : Victim_Pseudo_LRU_library_clean +local_clean : + include ../Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp (revision 88) @@ -38,10 +38,21 @@ #endif - Victim_Pseudo_LRU * _Victim_Pseudo_LRU = new Victim_Pseudo_LRU (name.c_str(), + Tusage_t _usage = USE_ALL; + +// _usage = usage_unset(_usage,USE_SYSTEMC ); +// _usage = usage_unset(_usage,USE_VHDL ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); +// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); +// _usage = usage_unset(_usage,USE_POSITION ); +// _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_INFORMATION ); + + Victim_Pseudo_LRU * _Victim_Pseudo_LRU = new Victim_Pseudo_LRU + (name.c_str(), #ifdef STATISTICS - param_stat, -#endif - ¶m, - USE_ALL); + param_stat, +#endif + ¶m, + _usage); #ifdef SYSTEMC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Parameters.h (revision 88) @@ -35,8 +35,11 @@ uint32_t size_table, bool table_global); - public : Parameters (Parameters & param) ; +// public : Parameters (Parameters & param) ; public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); + public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h (revision 88) @@ -112,10 +112,10 @@ public : ~Victim_Pseudo_LRU (void); -#ifdef SYSTEMC private : void allocation (void); private : void deallocation (void); +#ifdef SYSTEMC public : void transition (void); - public : void genMoore (void); + public : void genMealy (void); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Parameters.cpp (revision 88) @@ -30,17 +30,22 @@ }; - Parameters::Parameters (Parameters & param): - _nb_entity (param._nb_entity ), - _nb_access (param._nb_access ), -// _nb_update (param._nb_update ), - _size_table (param._size_table), - _table_global(param._table_global), - _size_address(param._size_address) - { - test(); +// Parameters::Parameters (Parameters & param): +// _nb_entity (param._nb_entity ), +// _nb_access (param._nb_access ), +// // _nb_update (param._nb_update ), +// _size_table (param._size_table), +// _table_global(param._table_global), +// _size_address(param._size_address) +// { +// test(); +// }; + + Parameters::~Parameters () + { }; - Parameters::~Parameters () - { }; + void Parameters::copy (void) + { + }; }; // end namespace victim_pseudo_lru Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU.cpp (revision 88) @@ -32,35 +32,35 @@ log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Begin"); -#ifdef SYSTEMC +#if DEBUG_Victim_Pseudo_LRU == true + log_printf(INFO,Victim_Pseudo_LRU,FUNCTION,_("<%s> Parameters"),_name.c_str()); + + std::cout << *param << std::endl; +#endif + log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation"); allocation (); -#endif #ifdef STATISTICS - log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation of statistics"); - - // Allocation of statistics - statistics_declaration(param_statistics); + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Allocation of statistics"); + + // Allocation of statistics + statistics_declaration(param_statistics); + } #endif #ifdef VHDL - // generate the vhdl - log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Generation of VHDL"); - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Generation of VHDL"); + vhdl(); + } #endif #ifdef SYSTEMC - log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); - SC_METHOD (transition); - dont_initialize (); - sensitive << (*(in_CLOCK)).pos(); - - SC_METHOD (genMoore); - dont_initialize (); - sensitive << (*(in_CLOCK)).neg(); - -#ifdef SYSTEMCASS_SPECIFIC -#endif - + if (usage_is_set(_usage,USE_SYSTEMC)) + { // Constant - ack is always at one for (uint32_t i=0; i<_param->_nb_access; i++) @@ -70,4 +70,22 @@ } + log_printf(TRACE,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","Definition of sc_method"); + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + + SC_METHOD (genMealy); + dont_initialize (); + sensitive << (*(in_CLOCK)).neg(); + for (uint32_t i=0; i<_param->_nb_access; i++) + if (_param->_size_table>1) + sensitive << (*(in_ACCESS_ADDRESS[i])); + +#ifdef SYSTEMCASS_SPECIFIC + if (_param->_size_table>1) + for (uint32_t i=0; i<_param->_nb_access; i++) + (*(out_ACCESS_VICTIM[i])) (*(in_ACCESS_ADDRESS[i])); +#endif + } #endif log_printf(FUNC,Victim_Pseudo_LRU,"Victim_Pseudo_LRU","End"); @@ -77,10 +95,11 @@ { log_printf(FUNC,Victim_Pseudo_LRU,"~Victim_Pseudo_LRU","Begin"); -#ifdef SYSTEMC + deallocation (); -#endif + #ifdef STATISTICS - delete _stat; + if (usage_is_set(_usage,USE_STATISTICS)) + delete _stat; #endif log_printf(FUNC,Victim_Pseudo_LRU,"~Victim_Pseudo_LRU","End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -53,4 +52,6 @@ } + if (usage_is_set(_usage,USE_SYSTEMC)) + { // -----[ Register ]--------------------------------------------------- reg_TABLE = new entry_t * [_param->_size_table]; @@ -62,7 +63,9 @@ internal_ACCESS_ACK = new Tcontrol_t [_param->_nb_access]; internal_ACCESS_VICTIM = new Tentity_t [_param->_nb_access]; + } #ifdef POSITION - _component->generate_file(); + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); #endif }; @@ -74,3 +77,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_deallocation.cpp (revision 88) @@ -1,3 +1,2 @@ -#ifdef SYSTEMC /* * $Id$ @@ -17,4 +16,6 @@ void Victim_Pseudo_LRU::deallocation (void) { + if (usage_is_set(_usage,USE_SYSTEMC)) + { delete in_CLOCK; delete in_NRESET; @@ -34,4 +35,5 @@ delete [] internal_ACCESS_ACK ; delete [] internal_ACCESS_VICTIM; + } delete _component; @@ -43,3 +45,2 @@ }; // end namespace behavioural }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_end_cycle.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_end_cycle.cpp (revision 88) @@ -22,5 +22,6 @@ #ifdef STATISTICS - _stat->end_cycle(); + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); #endif @@ -28,5 +29,6 @@ // Evaluation before read the ouput signal // sc_start(0); - _interfaces->testbench(); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMealy.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMealy.cpp (revision 88) @@ -0,0 +1,34 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h" + +namespace morpheo { +namespace behavioural { +namespace generic { +namespace victim { +namespace victim_pseudo_lru { + + void Victim_Pseudo_LRU::genMealy (void) + { + for (uint32_t i=0; i<_param->_nb_access; i++) + { + Taddress_t address = (_param->_size_table>1)?PORT_READ(in_ACCESS_ADDRESS[i]):0; + + internal_ACCESS_VICTIM[i] = reg_TABLE[address]->access(); + + PORT_WRITE(out_ACCESS_VICTIM[i], internal_ACCESS_VICTIM[i]); + }//end for i + }; + +}; // end namespace victim_pseudo_lru +}; // end namespace victim +}; // end namespace generic +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_genMoore.cpp (revision 87) +++ (revision ) @@ -1,34 +1,0 @@ -#ifdef SYSTEMC -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h" - -namespace morpheo { -namespace behavioural { -namespace generic { -namespace victim { -namespace victim_pseudo_lru { - - void Victim_Pseudo_LRU::genMoore (void) - { - for (uint32_t i=0; i<_param->_nb_access; i++) - { - Taddress_t address = (_param->_size_table>1)?PORT_READ(in_ACCESS_ADDRESS[i]):0; - - internal_ACCESS_VICTIM[i] = reg_TABLE[address]->access(); - - PORT_WRITE(out_ACCESS_VICTIM[i], internal_ACCESS_VICTIM[i]); - }//end for i - }; - -}; // end namespace victim_pseudo_lru -}; // end namespace victim -}; // end namespace generic -}; // end namespace behavioural -}; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/include/Parameters.h (revision 88) @@ -24,5 +24,4 @@ namespace generic { namespace victim { - class Parameters : public morpheo::behavioural::Parameters @@ -57,4 +56,6 @@ public : ~Parameters () ; + public : void copy (void); + public : Parameters_test msg_error (void); @@ -66,5 +67,4 @@ }; // end namespace victim }; // end namespace generic - }; // end namespace behavioural }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters.cpp (revision 88) @@ -69,10 +69,30 @@ switch (_victim_scheme) { -// case VICTIM_RANDOM : delete _param_victim_random ; -// case VICTIM_ROUND_ROBIN : delete _param_victim_round_robin; -// case VICTIM_NLU : delete _param_victim_nlu ; - case VICTIM_PSEUDO_LRU : delete _param_victim_pseudo_lru ; -// case VICTIM_LRU : delete _param_victim_lru ; -// case VICTIM_FIFO : delete _param_victim_fifo ; +// case VICTIM_RANDOM : delete _param_victim_random ; break; +// case VICTIM_ROUND_ROBIN : delete _param_victim_round_robin; break; +// case VICTIM_NLU : delete _param_victim_nlu ; break; + case VICTIM_PSEUDO_LRU : delete _param_victim_pseudo_lru ; break; +// case VICTIM_LRU : delete _param_victim_lru ; break; +// case VICTIM_FIFO : delete _param_victim_fifo ; break; + default : break; + } + + log_printf(FUNC,Victim,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Victim::copy" + void morpheo::behavioural::generic::victim::Parameters::copy (void) + { + log_printf(FUNC,Victim,FUNCTION,"Begin"); + + switch (_victim_scheme) + { +// case VICTIM_RANDOM : COPY(_param_victim_random ); break; +// case VICTIM_ROUND_ROBIN : COPY(_param_victim_round_robin); break; +// case VICTIM_NLU : COPY(_param_victim_nlu ); break; + case VICTIM_PSEUDO_LRU : COPY(_param_victim_pseudo_lru ); break; +// case VICTIM_LRU : COPY(_param_victim_lru ); break; +// case VICTIM_FIFO : COPY(_param_victim_fifo ); break; default : break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters_msg_error.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Parameters_msg_error.cpp (revision 88) @@ -26,10 +26,10 @@ switch (_victim_scheme) { - case VICTIM_RANDOM : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; - case VICTIM_ROUND_ROBIN : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; - case VICTIM_NLU : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; -// case VICTIM_PSEUDO_LRU : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; - case VICTIM_LRU : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; - case VICTIM_FIFO : test.error("Victim scheme '"+toString(_victim_scheme)+"' is not supported. (Coming Soon)"); break; + case VICTIM_RANDOM : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; + case VICTIM_ROUND_ROBIN : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; + case VICTIM_NLU : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; +// case VICTIM_PSEUDO_LRU : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; + case VICTIM_LRU : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; + case VICTIM_FIFO : test.error(toString(_("Victim scheme \"%s\" is not supported. (Coming Soon)\n"),toString(_victim_scheme).c_str())); break; default : break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim.cpp (revision 88) @@ -39,21 +39,18 @@ allocation ( #ifdef STATISTICS - param_statistics + param_statistics #endif - ); + ); #ifdef STATISTICS - if (_usage & USE_STATISTICS) - { - switch (_param->_victim_scheme) - { -// case VICTIM_RANDOM : _stat = _component_victim_random ->_stat; break; -// case VICTIM_ROUND_ROBIN : _stat = _component_victim_round_robin ->_stat; break; -// case VICTIM_NLU : _stat = _component_victim_nlu ->_stat; break; - case VICTIM_PSEUDO_LRU : _stat = _component_victim_pseudo_lru ->_stat; break; -// case VICTIM_LRU : _stat = _component_victim_lru ->_stat; break; -// case VICTIM_FIFO : _stat = _component_victim_fifo ->_stat; break; - default : break; - } + switch (_param->_victim_scheme) + { +// case VICTIM_RANDOM : _stat = _component_victim_random ->_stat; break; +// case VICTIM_ROUND_ROBIN : _stat = _component_victim_round_robin ->_stat; break; +// case VICTIM_NLU : _stat = _component_victim_nlu ->_stat; break; + case VICTIM_PSEUDO_LRU : _stat = _component_victim_pseudo_lru ->_stat; break; +// case VICTIM_LRU : _stat = _component_victim_lru ->_stat; break; +// case VICTIM_FIFO : _stat = _component_victim_fifo ->_stat; break; + default : break; } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/src/Victim_deallocation.cpp (revision 88) @@ -32,5 +32,5 @@ } - if (_usage & USE_SYSTEMC) + if (usage_is_set(_usage,USE_SYSTEMC)) { delete in_CLOCK ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common (revision 88) @@ -7,10 +7,25 @@ # -include $(MORPHEO_TOPLEVEL)/Makefile.tools +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif +ifeq ($(origin MORPHEO_TMP), undefined) + $(error "variable MORPHEO_TMP is undefined"); +endif +ifeq ($(origin MORPHEO_SCRIPT), undefined) + $(error "variable MORPHEO_SCRIPT is undefined"); +endif +ifeq ($(origin DIR_MORPHEO), undefined) + $(error "variable DIR_MORPHEO is undefined"); +endif #-----[ Directory ]---------------------------------------- +DIR_TMP = $(MORPHEO_TMP) DIR_INC = include DIR_SRC = src DIR_OBJ = obj +#DIR_LIB = $(DIR_TMP)/lib DIR_SCRIPT = $(MORPHEO_SCRIPT) @@ -35,6 +50,5 @@ #-----[ Variable ]----------------------------------------- - -ENTITY = `$(BASENAME) $$PWD` +ENTITY = $$($(BASENAME) $$PWD) OBJECTS_COMMON = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) @@ -46,13 +60,4 @@ test_env : -ifeq ($(origin MORPHEO_TOPLEVEL), undefined) - $(error "variable MORPHEO_TOPLEVEL is undefined"); -endif -ifeq ($(origin MORPHEO_SCRIPT), undefined) - $(error "variable MORPHEO_SCRIPT is undefined"); -endif -ifeq ($(origin DIR_MORPHEO), undefined) - $(error "variable DIR_MORPHEO is undefined"); -endif @$(ECHO) "-------------------| $(ENTITY)" @@ -77,4 +82,6 @@ $(DIR_INC)/*~; +common_clean_all : common_clean + common_help : @\ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Component (revision 88) @@ -1,6 +1,6 @@ #-----[ Directory ]---------------------------------------- DIR_DOC = doc -DIR_LIB = lib DIR_TEST = SelfTest +DIR_LIB = lib #-----[ Variable ]----------------------------------------- @@ -30,4 +30,10 @@ component_clean : @$(RM) $(DIR_LIB) + +# if $(TEST) -d $(DIR_DOC); then $(MAKE) --directory=$(DIR_DOC) --makefile=Makefile clean; fi; + +component_clean_all : component_clean + +# if $(TEST) -d $(DIR_DOC); then $(MAKE) --directory=$(DIR_DOC) --makefile=Makefile clean_all; fi; component_help : @@ -50,4 +56,8 @@ @\ $(MAKE) common_clean ;\ - $(MAKE) component_clean;\ - if $(TEST) -d $(DIR_DOC); then $(MAKE) --directory=$(DIR_DOC) --makefile=Makefile clean; fi; + $(MAKE) component_clean; + +clean_all : + @\ + $(MAKE) common_clean_all ;\ + $(MAKE) component_clean_all; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Documentation =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Documentation (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Documentation (revision 88) @@ -1,10 +1,11 @@ -#-----[ Directory ]---------------------------------------- +#-----[ Directory ]---------------------------------------- -DIR_DOCUMENTATION = . -DIR_TEX = $(DIR_DOCUMENTATION) -DIR_SCHEMA = $(DIR_DOCUMENTATION)/fig -DIR_SCHEMA_EPS = $(DIR_DOCUMENTATION)/eps +DIR_DOC = . +DIR_TEX = $(DIR_DOC) +DIR_FIG = $(DIR_DOC)/fig +DIR_EPS = $(DIR_DOC)/eps +DIR_STY = $(DIR_DOC)/sty -#-----[ Files ]-------------------------------------------- +#-----[ Files ]-------------------------------------------- TEX_FILES = $(wildcard $(DIR_TEX)/*.tex) @@ -12,16 +13,17 @@ PS_FILES = $(patsubst $(DIR_TEX)/%.tex,%.ps ,$(TEX_FILES)) PDF_FILES = $(patsubst $(DIR_TEX)/%.tex,%.pdf,$(TEX_FILES)) -EPS_FILES = $(patsubst $(DIR_SCHEMA)/%.fig,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.fig)) \ - $(patsubst $(DIR_SCHEMA)/%.eps,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.eps)) +EPS_FILES = $(patsubst $(DIR_FIG)/%.fig,$(DIR_EPS)/%.eps,$(wildcard $(DIR_FIG)/*.fig)) \ + $(patsubst $(DIR_FIG)/%.dot,$(DIR_EPS)/%.eps,$(wildcard $(DIR_FIG)/*.dot)) \ + $(patsubst $(DIR_FIG)/%.eps,$(DIR_EPS)/%.eps,$(wildcard $(DIR_FIG)/*.eps)) -#-----[ Rules ]-------------------------------------------- +#-----[ Rules ]-------------------------------------------- #-------------------------------------------------------------------------------- # The reset of this file shall not be editted #-------------------------------------------------------------------------------- -.PHONY : all clean help -.SECONDARY : $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_SCHEMA_EPS) +.PHONY : all clean clean_all help +.SECONDARY : $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_EPS) -all_documentation : $(EPS_FILES) +all_documentation : $(EPS_FILES) $(MAKE) $(PDF_FILES) @@ -30,24 +32,24 @@ # regular flow tex -> dvi -> ps -> pdf. #-------------------------------------------------------------------------------- -%.pdf : %.ps +%.pdf : %.ps @\ - $(ECHO) "Génération du fichier $*.pdf"; \ + $(ECHO) "Génération du fichier $*.pdf"; \ $(PS2PDF) $< $@; -%.ps : %.dvi +%.ps : %.dvi @\ - $(ECHO) "Génération du fichier $*.ps"; \ + $(ECHO) "Génération du fichier $*.ps"; \ $(DVIPS) -o $@ $<; -%.dvi : $(DIR_TEX)/%.tex +%.dvi : $(DIR_TEX)/%.tex @\ - $(ECHO) "Génération du fichier $*.dvi"; \ - $(LATEX) $<; \ - $(LATEX) $< > /dev/null; \ - citation=`$(GREP) "citation" $*.aux`; \ - if $(TEST) -n "$$citation" ; then \ - $(BIBTEX) $* ; \ - fi; \ - $(LATEX) $< > /dev/null; \ + $(ECHO) "Génération du fichier $*.dvi"; \ + $(LATEX) $<; \ + $(LATEX) $< > /dev/null; \ + citation=`$(GREP) "citation" $*.aux`; \ + if $(TEST) -n "$$citation" ; then \ + $(BIBTEX) $* ; \ + fi; \ + $(LATEX) $< > /dev/null; \ $(LATEX) $< > /dev/null; @@ -55,18 +57,25 @@ # The figures directory #-------------------------------------------------------------------------------- -$(DIR_SCHEMA_EPS) : +$(DIR_EPS) : @\ - $(ECHO) "Make directory : $@"; \ + $(ECHO) "Make directory : $@"; \ $(MKDIR) $@; -$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.eps $(DIR_SCHEMA_EPS) +$(DIR_EPS)/%.eps : $(DIR_FIG)/%.eps $(DIR_EPS) @\ - $(ECHO) "Generate files : $*.eps"; \ - $(CP) $(DIR_SCHEMA)/$*.eps $(DIR_SCHEMA_EPS); + $(ECHO) "Generate files : $*.eps"; \ + $(CP) $(DIR_FIG)/$*.eps $(DIR_EPS); -$(DIR_SCHEMA_EPS)/%.eps : $(DIR_SCHEMA)/%.fig $(DIR_SCHEMA_EPS) +$(DIR_EPS)/%.eps : $(DIR_FIG)/%.fig $(DIR_EPS) @\ - $(ECHO) "Generate files : $*.eps"; \ + $(ECHO) "Generate files : $*.eps"; \ $(FIG2EPS) $< $@; + +$(DIR_EPS)/%.eps : $(DIR_FIG)/%.dot $(DIR_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(DOT) -Tfig -o $(DIR_EPS)/${*}.fig $<; \ + $(FIG2EPS) $(DIR_EPS)/${*}.fig $@; \ + $(RM) $(DIR_EPS)/${*}.fig; #-------------------------------------------------------------------------------- @@ -74,37 +83,33 @@ #-------------------------------------------------------------------------------- -clean : +clean : @\ $(ECHO) "Delete temporary files "$(PWD); \ - $(RM) $(DIR_SCHEMA_EPS); \ - $(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES); \ - $(MAKE) clean_rec DIR_CLEAN=.; + $(RM) $(DIR_EPS) \ + $(DVI_FILES) \ + $(PS_FILES) \ + $(DIR_DOC)/*~ \ + $(DIR_STY)/*~ \ + $(DIR_TEX)/*~ \ + $(DIR_FIG)/*~ \ + $(DIR_DOC)/*.bak \ + $(DIR_DOC)/*.aux \ + $(DIR_DOC)/*.bbl \ + $(DIR_DOC)/*.blg \ + $(DIR_DOC)/*.bmt \ + $(DIR_DOC)/*.log \ + $(DIR_DOC)/*.mtc* \ + $(DIR_DOC)/*.toc \ + $(DIR_DOC)/*.idx \ + $(DIR_DOC)/*.maf \ + $(DIR_DOC)/*.ilg \ + $(DIR_DOC)/*.ind \ + $(DIR_DOC)/*.out \ + $(DIR_DOC)/*.nav \ + $(DIR_DOC)/*.snm \ + $(DIR_DOC)/missfont.log; \ -#Clean recursive -clean_rec : - @\ - $(ECHO) "Delete temporary files in directory $(DIR_CLEAN)"; \ - $(RM) $(DIR_CLEAN)/*~ \ - $(DIR_CLEAN)/*.bak \ - $(DIR_CLEAN)/*.aux \ - $(DIR_CLEAN)/*.bbl \ - $(DIR_CLEAN)/*.blg \ - $(DIR_CLEAN)/*.bmt \ - $(DIR_CLEAN)/*.log \ - $(DIR_CLEAN)/*.mtc* \ - $(DIR_CLEAN)/*.toc \ - $(DIR_CLEAN)/*.idx \ - $(DIR_CLEAN)/*.ilg \ - $(DIR_CLEAN)/*.ind \ - $(DIR_CLEAN)/*.out \ - $(DIR_CLEAN)/*.nav \ - $(DIR_CLEAN)/*.snm \ - $(DIR_CLEAN)/missfont.log; \ - for files in `$(LS) $(DIR_CLEAN)`; do \ - if $(TEST) -d $(DIR_CLEAN)/$$files; \ - then \ - $(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files; \ - fi; \ - done; +clean_all : clean + @$(RM) $(PDF_FILES); #-------------------------------------------------------------------------------- @@ -112,10 +117,11 @@ #-------------------------------------------------------------------------------- -help : +help : @\ - $(ECHO) " -----[ Documentation ]------------------------------";\ - $(ECHO) ""; \ - $(ECHO) " * all_documentation : Generate all documents"; \ - $(ECHO) " * clean : Erase all generate files"; \ - $(ECHO) " * help : Print this message"; \ + $(ECHO) " -----[ Documentation ]------------------------------";\ + $(ECHO) ""; \ + $(ECHO) " * all_documentation : Generate all documents"; \ + $(ECHO) " * clean : Erase all temporary files"; \ + $(ECHO) " * clean_all : Erase all generate files"; \ + $(ECHO) " * help : Print this message"; \ $(ECHO) ""; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Selftest (revision 88) @@ -8,7 +8,7 @@ #-----[ Directory ]---------------------------------------- -DIR_BIN = bin -DIR_LIB = ../lib -DIR_CFG_GEN = configuration_generated +DIR_BIN = $(DIR_TMP)/bin +DIR_LIB = ../lib +DIR_CFG_GEN = $(DIR_TMP)/configuration_generated DIR_CFG_USER = configuration DIR_LOG = log @@ -34,7 +34,7 @@ @\ $(MAKE) library;\ - $(MAKE) $(DIR_BIN)/$(EXEC).x; - -execute : all_selftest + $(MAKE) $(DIR_BIN)/$(EXEC).x; + +execute_only : @\ $(MAKE) $(EXEC_LOG); \ @@ -45,5 +45,7 @@ $(GREP) -q "Test KO" $$i; \ declare -i test_ko=$$?; \ - if $(TEST) $$test_ko -eq 0 -o $$test_ok -ne 0; \ + $(GREP) -q "ERROR" $$i; \ + declare -i test_error=$$?; \ + if $(TEST) $$test_ko -eq 0 -o $$test_error -eq 0 -o $$test_ok -ne 0; \ then all_ok=0; \ fi; \ @@ -54,4 +56,8 @@ fi; +execute : all_selftest + @\ + $(MAKE) execute_only; + reconfig : @\ @@ -74,15 +80,44 @@ fi; \ \ - for file in $$files; do \ - \ + declare -i NB_CONFIG=0; \ + declare -i NB_DIGIT=0; \ + \ + for file in $${files}; do \ + declare -ai PERIOD=(); \ + declare -i IT=0; \ + \ + PERIOD[0]=1; \ + \ + while read line; do \ + declare -a LINE=($${line}); \ + \ + if $(TEST) $${IT} -ne 0; then \ + declare -a RANGE_LOCAL=($$($(DIR_SCRIPT)/range.sh $${LINE[0]} $${LINE[1]} $${LINE[2]})); \ + declare -i SIZE=$${#RANGE_LOCAL[*]}; \ + PERIOD[$${IT}]=$$(($${PERIOD[$$(($${IT}-1))]}*$${SIZE})); \ + fi; \ + \ + IT=$$(($${IT}+1)); \ + done < $${file}; \ + \ + NB_CONFIG=$$(($${NB_CONFIG} + $${PERIOD[$$(($${IT}-1))]})); \ + done; \ + \ + $(ECHO) " * They are $${NB_CONFIG} configurations"; \ + \ + declare -i x=$${NB_CONFIG}; \ + \ + while test $${x} -ne 0; do \ + NB_DIGIT=$$(($${NB_DIGIT} + 1)); \ + x=$$(($${x} / 10)); \ + done; \ + \ + for file in $${files}; do \ declare NAME; \ - declare -ai MIN ; \ - declare -ai MAX ; \ - declare -a STEP; \ - declare -a LINE; \ - declare -ai PERIOD; \ - declare -a RANGE; \ - declare -a RANGE_LOCAL; \ - declare -a SIZE; \ + declare -ai MIN=(); \ + declare -ai PERIOD=(); \ + declare -a RANGE_LOCAL=(); \ + declare -a RANGE=(); \ + declare -a SIZE=(); \ declare -i IT=0; \ \ @@ -90,40 +125,39 @@ \ while read line; do \ - LINE=($$line); \ - \ - if $(TEST) $$IT -eq 0; then \ + declare -a LINE=($${line}); \ + \ + if $(TEST) $${IT} -eq 0; then \ NAME=$${LINE[0]}; \ else \ - MIN[$$IT]=$${LINE[0]}; \ - MAX[$$IT]=$${LINE[1]}; \ - STEP[$$IT]=$${LINE[2]}; \ - RANGE[$$IT]=$$($(DIR_SCRIPT)/range.sh $${LINE[0]} $${LINE[1]} $${LINE[2]}); \ - RANGE_LOCAL=($${RANGE[$$IT]}); \ - SIZE[$$IT]=$${#RANGE_LOCAL[*]}; \ - PERIOD[$$IT]=$$(($${PERIOD[$$(($$IT-1))]}*$${SIZE[$$IT]})); \ + MIN[$${IT}]=$${LINE[0]}; \ + RANGE[$${IT}]=$$($(DIR_SCRIPT)/range.sh $${LINE[0]} $${LINE[1]} $${LINE[2]}); \ + RANGE_LOCAL=($${RANGE[$${IT}]}); \ + SIZE[$${IT}]=$${#RANGE_LOCAL[*]}; \ + PERIOD[$${IT}]=$$(($${PERIOD[$$(($${IT}-1))]}*$${SIZE[$${IT}]})); \ fi; \ \ - IT=$$(($$IT+1)); \ - done < $$file; \ - \ - declare -i x; \ - declare -a DATA; \ - declare -ai ENUM_CONFIG=($$($(DIR_SCRIPT)/range.sh 0 $$(($${PERIOD[$$(($$IT-1))]}-1)))); \ + IT=$$(($${IT}+1)); \ + done < $${file}; \ + \ + declare -a DATA=(); \ + declare -ai ENUM_CONFIG=($$($(DIR_SCRIPT)/range.sh 0 $$(($${PERIOD[$$(($${IT}-1))]}-1)))); \ declare -ai ENUM_PARAM=($$($(DIR_SCRIPT)/range.sh 1 $${#MIN[*]})); \ + declare -i NB_PARAM=$${#MIN[*]}; \ \ $(ECHO) " * File : $$file"; \ - $(ECHO) " * They are $${#MIN[*]} parameters"; \ - $(ECHO) " * Generate $${PERIOD[$$(($$IT-1))]} configurations"; \ + $(ECHO) " * They are $${NB_PARAM} parameters"; \ + $(ECHO) " * Generate $${PERIOD[$$(($${IT}-1))]} configurations"; \ \ for i in $${ENUM_CONFIG[*]}; do \ x=$$i; \ for j in $${ENUM_PARAM[*]}; do \ - RANGE_LOCAL=($${RANGE[$$j]}); \ + declare -a RANGE_LOCAL=($${RANGE[$$j]}); \ DATA[$$j]="$${RANGE_LOCAL[$$((($$x % $${SIZE[$$j]})))]} "; \ x=$$(($$x/$${SIZE[$$j]})); \ done; \ - $(ECHO) $${DATA[*]} > "$(DIR_CFG_GEN)/$${NAME}_$$CPT.cfg"; \ - $(ECHO) " - {$$CPT} $${DATA[*]}"; \ - CPT=$$(($$CPT+1)); \ + declare NUM=$$($(PRINTF) %.$${NB_DIGIT}d $${CPT}); \ + $(ECHO) $${DATA[*]} > "$(DIR_CFG_GEN)/$${NAME}_$${NUM}.cfg"; \ + $(ECHO) " - {$${NUM}} $${DATA[*]}"; \ + CPT=$$(($${CPT}+1)); \ done; \ done; @@ -132,5 +166,5 @@ @\ $(ECHO) "Execute : $*";\ - export SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(EXEC_PREFIX) ./$(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \ + export SYSTEMC=$(SYSTEMC_$(SIMULATOR)); $(EXEC_PREFIX) $(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \ declare timing=`$(GREP) -h "Timing" $@`; \ $(GREP) -q "Test OK" $@; \ @@ -138,5 +172,7 @@ $(GREP) -q "Test KO" $@; \ declare -i test_ko=$$?; \ - if $(TEST) $$test_ko -ne 0 -a $$test_ok -eq 0; \ + $(GREP) -q "ERROR" $@; \ + declare -i test_error=$$?; \ + if $(TEST) $$test_ko -ne 0 -a $$test_error -ne 0 -a $$test_ok -eq 0; \ then echo -e " $* ... OK\t$$timing";\ else echo " $* ... KO"; \ @@ -146,5 +182,5 @@ @\ $(ECHO) "Execute : $*";\ - export SYSTEMC=$(SYSTEMC_$(SIMULATOR)) ; $(EXEC_PREFIX) ./$(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \ + export SYSTEMC=$(SYSTEMC_$(SIMULATOR)); $(EXEC_PREFIX) $(DIR_BIN)/$(EXEC).x $(EXEC_PARAMS) $* `$(CAT) $<` &> $@; \ declare timing=`$(GREP) -h "Timing" $@`; \ $(GREP) -q "Test OK" $@; \ @@ -152,7 +188,9 @@ $(GREP) -q "Test KO" $@; \ declare -i test_ko=$$?; \ - if $(TEST) $$test_ko -ne 0 -a $$test_ok -eq 0; \ - then echo -e " $* ... OK\t$$timing";\ - else echo " $* ... KO"; \ + $(GREP) -q "ERROR" $@; \ + declare -i test_error=$$?; \ + if $(TEST) $$test_ko -ne 0 -a $$test_error -ne 0 -a $$test_ok -eq 0; \ + then $(ECHO) -e " $* ... OK\t$$timing";\ + else $(ECHO) " $* ... KO"; \ fi; @@ -162,4 +200,9 @@ $(CXX) $(LFLAGS) -o $@ $(OBJECTS) $(LIBS); +$(DIR_LIB) : + @\ + $(ECHO) "Create directory : $@";\ + $(MKDIR) $@; + $(DIR_BIN) : @\ @@ -177,7 +220,5 @@ $(MKDIR) $@; -selftest_clean_all : library_clean - -selftest_clean : config_clean +selftest_clean : local_clean config_clean @$(RM) $(DIR_LOG) \ $(DIR_CFG_USER)/*~ \ @@ -185,8 +226,13 @@ *.pos \ *.stat \ + *.log \ *.dot \ *.txt \ generated_by_systemcass \ + semantic.cache \ core*; + +selftest_clean_all : library_clean + selftest_help : @@ -196,4 +242,5 @@ $(ECHO) " * all_selftest : compile all c++ file and execute";\ $(ECHO) " * execute : execute all instance";\ + $(ECHO) " * execute_only : execute all instance without rebuild all libraries";\ $(ECHO) " * config : generate configuration with configuration's file" ;\ $(ECHO) " * reconfig : regenerate configuration with configuration's file" ;\ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (revision 88) @@ -87,4 +87,6 @@ $(RM) $(DIR_WORK) transcript Makefile.mkf $(FPGA_CFG_FILE_LOCAL) *.wlf; +synthesis_clean_all : synthesis_clean + synthesis_help : @\ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.flags (revision 88) @@ -5,38 +5,7 @@ # -#-----[ Simulator ]---------------------------------------- -SIMULATOR = systemcass -#SIMULATOR = systemc - -# 3 simulators : -# systemc - SystemC -# systemcass - SystemCASS -# systemcass_deps - Systemcass, and use port dependency information instead of sensitivity list - -#-----[ Flags ]-------------------------------------------- -MORPHEO_FLAGS = -DSYSTEMC \ - -DSTATISTICS \ - -DDEBUG=DEBUG_TRACE - -# -DVHDL \ -# -DVHDL_TESTBENCH \ -# -DVHDL_TESTBENCH_ASSERT \ -# -DPOSITION \ -# -DNO_TRANSLATION \ - -# Flags : -# DEBUG={level} - Print Debug Message -# SYSTEMC - To generate a systemc's model -# VHDL - To generate a vhdl's models -# VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model -# VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in testbench's file an serie of assert -# POSITION - To generate a position's files (it's input of viewer) -# STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file -# INFORMATION (need STATISTICS) - Instance Information : -# * Static : at the instance creation -# * register number -# * worst way -# * Dynamique : at the runtime -# * consomation -# NO_TRANSLATION - No translate message -# NO_INIT - No init a lot of register +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.flags +endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : @COMPONENT_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/main.cpp (revision 88) @@ -37,7 +37,8 @@ morpheo::behavioural::@NAMESPACE_USE::Parameters * param = new morpheo::behavioural::@NAMESPACE_USE::Parameters ( + true //is_toplevel ); - msg(_("%s"),param->print(1).c_str()); + msg(_("%s"),param->print(0).c_str()); test (name,param); @@ -58,5 +59,5 @@ catch (morpheo::ErrorMorpheo & error) { - msg (_("<%s> :\n%s"),name.c_str(), error.what ()); +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); _return = EXIT_FAILURE; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/SelfTest/src/test.cpp (revision 88) @@ -14,4 +14,7 @@ { msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); #ifdef STATISTICS Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/include/Parameters.h (revision 88) @@ -21,7 +21,9 @@ //-----[ methods ]----------------------------------------------------------- - public : Parameters (); -// public : Parameters (Parameters & param) ; - public : ~Parameters () ; + public : Parameters (bool is_toplevel=false); +//public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); public : Parameters_test msg_error (void); @@ -29,5 +31,5 @@ public : std::string print (uint32_t depth); public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::@NAMESPACE_USE::Parameters & x); + morpheo::behavioural::@NAMESPACE_USE::Parameters & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component.cpp (revision 88) @@ -35,5 +35,5 @@ usage_environment(_usage); - log_printf(INFO,@COMPONENT,FUNCTION,_("Allocation")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Allocation"),_name.c_str()); allocation ( @@ -46,5 +46,5 @@ if (usage_is_set(_usage,USE_STATISTICS)) { - log_printf(INFO,@COMPONENT,FUNCTION,_("Allocation of statistics")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); statistics_allocation(param_statistics); @@ -56,5 +56,5 @@ { // generate the vhdl - log_printf(INFO,@COMPONENT,FUNCTION,_("Generate the vhdl")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); vhdl(); @@ -65,5 +65,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - log_printf(INFO,@COMPONENT,FUNCTION,_("Method - transition")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); SC_METHOD (transition); @@ -74,4 +74,14 @@ // List dependency information # endif + +// log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Method - genMoore"),_name.c_str()); + +// SC_METHOD (genMoore); +// dont_initialize (); +// sensitive << (*(in_CLOCK)).neg(); // need internal register + +// # ifdef SYSTEMCASS_SPECIFIC +// // List dependency information +// # endif #endif @@ -93,5 +103,5 @@ #endif - log_printf(INFO,@COMPONENT,FUNCTION,_("Deallocation")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); deallocation (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component_statistics_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/New_Component_statistics_deallocation.cpp (revision 88) @@ -19,5 +19,5 @@ log_begin(@COMPONENT,FUNCTION); - log_printf(INFO,@COMPONENT,FUNCTION,_("Generate Statistics file")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); delete _stat; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vbe/src/Parameters.cpp (revision 88) @@ -14,8 +14,15 @@ #undef FUNCTION #define FUNCTION "@COMPONENT::Parameters" - Parameters::Parameters () + Parameters::Parameters (bool is_toplevel) { log_begin(@COMPONENT,FUNCTION); + test(); + + if (is_toplevel) + { + copy(); + } + log_end(@COMPONENT,FUNCTION); }; @@ -32,5 +39,13 @@ #undef FUNCTION #define FUNCTION "@COMPONENT::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_begin(@COMPONENT,FUNCTION); + log_end(@COMPONENT,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "@COMPONENT::copy" + void Parameters::copy (void) { log_begin(@COMPONENT,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/Makefile (revision 88) @@ -24,4 +24,6 @@ library_clean : @COMPONENT_library_clean +local_clean : + include $(DIR_COMPONENT)/Makefile.deps include $(DIR_MORPHEO)/Behavioural/Makefile.flags Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/main.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/main.cpp (revision 88) @@ -37,7 +37,8 @@ morpheo::behavioural::@NAMESPACE_USE::Parameters * param = new morpheo::behavioural::@NAMESPACE_USE::Parameters ( + true // is_toplevel ); - msg(_("%s"),param->print(1).c_str()); + msg(_("%s"),param->print(0).c_str()); test (name,param); @@ -58,5 +59,5 @@ catch (morpheo::ErrorMorpheo & error) { - msg (_("<%s> :\n%s"),name.c_str(), error.what ()); +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); _return = EXIT_FAILURE; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/SelfTest/src/test.cpp (revision 88) @@ -14,4 +14,7 @@ { msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); #ifdef STATISTICS Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/include/Parameters.h (revision 88) @@ -21,13 +21,15 @@ //-----[ methods ]----------------------------------------------------------- - public : Parameters (); -// public : Parameters (Parameters & param) ; - public : ~Parameters () ; + public : Parameters (bool is_toplevel=false); +//public : Parameters (Parameters & param) ; + public : ~Parameters (void); + + public : void copy (void); public : Parameters_test msg_error (void); public : std::string print (uint32_t depth); - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::@NAMESPACE_USE::Parameters & x); + public : friend std::ostream& operator<< (std::ostream& output, + morpheo::behavioural::@NAMESPACE_USE::Parameters & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component.cpp (revision 88) @@ -35,5 +35,5 @@ usage_environment(_usage); - log_printf(INFO,@COMPONENT,FUNCTION,_("Allocation")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Allocation"),_name.c_str()); allocation ( @@ -46,5 +46,5 @@ if (usage_is_set(_usage,USE_STATISTICS)) { - log_printf(INFO,@COMPONENT,FUNCTION,_("Allocation of statistics")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); statistics_allocation(param_statistics); @@ -56,5 +56,5 @@ { // generate the vhdl - log_printf(INFO,@COMPONENT,FUNCTION,_("Generate the vhdl")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); vhdl(); @@ -65,5 +65,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - log_printf(INFO,@COMPONENT,FUNCTION,_("Method - transition")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); SC_METHOD (transition); @@ -93,5 +93,5 @@ #endif - log_printf(INFO,@COMPONENT,FUNCTION,_("Deallocation")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); deallocation (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component_statistics_deallocation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/New_Component_statistics_deallocation.cpp (revision 88) @@ -19,5 +19,5 @@ log_begin(@COMPONENT,FUNCTION); - log_printf(INFO,@COMPONENT,FUNCTION,_("Generate Statistics file")); + log_printf(INFO,@COMPONENT,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); delete _stat; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/Parameters.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/New_Component_vst/src/Parameters.cpp (revision 88) @@ -14,8 +14,15 @@ #undef FUNCTION #define FUNCTION "@COMPONENT::Parameters" - Parameters::Parameters () + Parameters::Parameters (bool is_toplevel) { log_begin(@COMPONENT,FUNCTION); + test(); + + if (is_toplevel) + { + copy(); + } + log_end(@COMPONENT,FUNCTION); }; @@ -32,5 +39,13 @@ #undef FUNCTION #define FUNCTION "@COMPONENT::~Parameters" - Parameters::~Parameters () + Parameters::~Parameters (void) + { + log_begin(@COMPONENT,FUNCTION); + log_end(@COMPONENT,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "@COMPONENT::copy" + void Parameters::copy (void) { log_begin(@COMPONENT,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/AbstractXMLLight.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/AbstractXMLLight.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/AbstractXMLLight.h (revision 88) @@ -0,0 +1,242 @@ +#ifndef _ABSTRACT_XMLLIGHT_H +#define _ABSTRACT_XMLLIGHT_H + +// WORK IN PROGRESS THERE MUST BE SYNTAX ERROR AND OTHER BOGUS THING + +#include "Behavioural/include/IXMLLight.h" +#include "Behavioural/include/XMLLightVector.h" +#include "Behavioural/include/XMLLightFunctors.h" +#include +#include +#include +#include + +using std::basic_stringstream ; +using std::basic_string; +using std::basic_ostream; +using std::basic_istream; + +namespace morpheo { + namespace XMLUtils { + + + //******************************************Class Declaration***************************************// + + template< typename char_type, typename ReferenceCounter = ClassicReferenceCounter > + class AbstractXMLLight : public IXMLLight { + protected : + basic_string m_internalString; + public : + inline basic_string getInternalString(void) const; + protected : + inline explicit AbstractXMLLight ( const basic_string & str); + inline explicit AbstractXMLLight( const basic_istream & s ,IXMLLight *parent = NULL); + inline ~AbstractXMLLight(void); + + XMLLightVector > getNodes ( const basic_string & pattern ); + + //vector getNodes ( const string & pattern ); + //XMLLight & getFirstNode ( const string & pattern = ""); + + + //IXMLLightImpl & getRoot ( void ); + basic_string getName ( void ) ; + //string & getValue ( void ) ; + //string & getValue ( const string & firstNodeName ) ; + bool containsAttribute ( const basic_string & attributeName ); + map , basic_string > getAttributes ( void ); + basic_string getAttributeValue ( const basic_string & attributeName ); + + friend basic_ostream & operator<< + ( basic_ostream & os, const AbstractXMLLight * xl) { + return os << endl << "\t\t" << xl->m_internalString << endl; + } + + private: + inline basic_string extractEndRootTag(void); + inline void trim(void) ; + + }; + + //******************************************Inline implementation***********************************// + + // implementation of constructors and destructors + template < typename char_type, typename ReferenceCounter> + AbstractXMLLight::AbstractXMLLight ( const basic_string & str) + : m_internalString(str) { + trim(); + } + // CHANGE HERE + + template< typename char_type, typename ReferenceCounter> + AbstractXMLLight::AbstractXMLLight + ( const basic_istream & str, IXMLLight * parent) { + basic_stringstream st ; + st << str.rdbuf() ; + m_internalString = st.str(); + trim(); + if ( parent == NULL ) { + typename basic_string::iterator iterator = m_internalString.begin(); + while ( *(++iterator) != BEGIN_TAG ); + m_internalString = basic_string(iterator, m_internalString.end() ); + } + } + + template< typename char_type, typename ReferenceCounter> + AbstractXMLLight::~AbstractXMLLight( void ) {} + // + // implementation of getter. + template< typename char_type, typename ReferenceCounter> + basic_string AbstractXMLLight::getInternalString(void) const { + return m_internalString; + } + + // implementation of helper method. + template < typename char_type, typename ReferenceCounter> + void AbstractXMLLight::trim(void) { + + int index = m_internalString.find_first_of(BEGIN_TAG); + int lastIndex = m_internalString.find_last_of(END_TAG); + basic_string reducedString = m_internalString.substr(index,lastIndex - index + 1 ); + m_internalString = reducedString; + } + + template < typename char_type, typename ReferenceCounter> + basic_string AbstractXMLLight::extractEndRootTag(void) { + basic_string internal = m_internalString.substr(0,m_internalString.find_last_of(BEGIN_TAG)); + return internal.substr(0, m_internalString.find_last_of(END_TAG) + 1 ); + } + + template < typename char_type, typename ReferenceCounter> + XMLLightVector > AbstractXMLLight::getNodes ( const basic_string & pattern ) + { + XMLLightVector > returnedNodesVector; + basic_string reduceString = extractEndRootTag(); + if ( reduceString.empty() ) + { + return returnedNodesVector; + } + typename basic_string::iterator iterator = reduceString.begin(); + typename basic_string::iterator endStringIterator = reduceString.end(); + typename basic_string::iterator tempIterator = iterator; + bool first = true; + + while ( iterator != endStringIterator ) + { + if ( first ) + { + while ( *(++iterator) != END_TAG ) ; + if ( ++iterator == endStringIterator ) + { + return returnedNodesVector; + } + first = false; + } + tempIterator = iterator; + iterator = adjacent_find(iterator, endStringIterator, XMLLightComparator()); + if ( iterator != endStringIterator ) + { + iterator+=2; + } + + basic_string s ( tempIterator, iterator ); + if ( s.empty() || s.find_first_of(BEGIN_TAG) == basic_string::npos ) + { + return returnedNodesVector; + } + AbstractXMLLight * abstractXMLLight = new AbstractXMLLight(s); + if ( pattern.empty() || abstractXMLLight->getName() == pattern ) + { + returnedNodesVector.push_back(abstractXMLLight); + } + else + { + delete abstractXMLLight; + } + if ( iterator != endStringIterator ) + { + iterator++; + } + } + return returnedNodesVector; + } + + + template < typename char_type, typename ReferenceCounter> + basic_string AbstractXMLLight::getName( void ) + { + if ( m_internalString.empty() ) { + std::cout << " oups chaine non copie " << std::endl ; + } + typename basic_string::iterator iterator = m_internalString.begin(); + basic_string resultString ; + while ( *( ++ iterator ) != END_TAG && *iterator != ' ' && *iterator != '\n' && *iterator != '\t' && *iterator != SECOND_TAG ) + + { + resultString.append(1,*( iterator) ); + } + return resultString; + } + + + template < typename char_type, typename ReferenceCounter> + map< basic_string, basic_string > AbstractXMLLight::getAttributes(void) + { + char equalSeparator = '='; + basic_string separator(" \a\b\n\t\f\r\v"); + basic_string key; + basic_string value; + + map, basic_string > returnedMap; + size_t last_position = 0; + size_t previous_position = 0; + size_t begin_position = 0; + size_t end_position = m_internalString.find_first_of(END_TAG); + basic_string nodeString = m_internalString.substr(0,end_position); + + while ( last_position = nodeString.find_first_of(equalSeparator,last_position) , last_position != basic_string::npos ) + { + begin_position = last_position; + last_position = nodeString.find_last_not_of(separator,begin_position-1); + previous_position = nodeString.find_last_of(separator,last_position); + key = nodeString.substr(previous_position+1, last_position-previous_position ); + last_position = nodeString.find_first_not_of(separator, begin_position +1) ; + previous_position = last_position; + last_position = nodeString.find_first_of(nodeString[previous_position] , previous_position +1 ); + value = nodeString.substr(previous_position +1 ,last_position - previous_position - 1); + returnedMap.insert(make_pair(key,value)); + // test d'erreur pour l'insertion a ajouter + + } + + return returnedMap; + } + + + template < typename char_type, typename ReferenceCounter> + bool AbstractXMLLight::containsAttribute ( const basic_string & attributeName ) + { + map,basic_string > attributeMap = getAttributes(); + if ( ! attributeMap.empty() && attributeMap.count(attributeName) == 1 ) + { + return true; + } + + return false; + } + + template < typename char_type, typename ReferenceCounter> + basic_string AbstractXMLLight::getAttributeValue ( const basic_string & attributeName ) + { + map, basic_string > attributeMap = getAttributes() ; + typename map,basic_string >::iterator it = attributeMap.find(attributeName); + if ( it == attributeMap.end() ) + { + return basic_string(""); + } + return (*it).second; + } + } + } + #endif + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Allocation.h (revision 88) @@ -11,6 +11,89 @@ #include "Common/include/Debug.h" +// ====================================================================== +// =====[ ALLOCATION / DELETE of ARRAY ]================================= +// ====================================================================== + +#define ALLOC1(var,type,s1) \ + var = new type [s1] + +#define ALLOC2(var,type,s1,s2) \ + var = new type * [s1]; \ + for (uint32_t it1=0; it1 : Interface's creation : %s (%s, %d)",_name.c_str(),name,__FILE__,__LINE__); +#define PRINT_SIGNAL_ADDRESS(name,address) log_printf(TRACE,Allocation,FUNCTION,"Signal : %s 0x%.8x(%s, %d)",name,(uint32_t)((uint64_t)(address)),__FILE__,__LINE__); +#define PRINT_SIZE_NUL(component,interface,signal) log_printf(TRACE,Allocation,FUNCTION,_("<%s> %s.%s.%s : size is nul."),_name.c_str(),component->get_name().c_str(),interface->get_name().c_str(),signal); +#define TEST_SIGNAL(name,address) PRINT_SIGNAL_ADDRESS(name,address); TEST_PTR(address) // ---------------------------------------------------------------------- @@ -18,75 +101,101 @@ // ---------------------------------------------------------------------- -#define __ALLOC_SIGNAL(sig, name, type) \ - { \ - sig = new type (name); \ +#define __ALLOC_SIGNAL(sig, name, type) \ + { \ + sig = new type (name); \ } #ifdef POSITION -#define ALLOC_INTERFACE( name, direction, localisation, str) \ - INTERFACE_PRINT(name); \ - Interface_fifo * interface = _interfaces->set_interface( name, direction, localisation, str); +#define ALLOC_INTERFACE( name, direction, localisation, str) \ + INTERFACE_PRINT(name); \ + morpheo::behavioural::Interface_fifo * interface = _interfaces->set_interface( name, direction, localisation, str); #else -#define ALLOC_INTERFACE( name, direction, localisation, str) \ - INTERFACE_PRINT(name); \ - Interface_fifo * interface = _interfaces->set_interface( name); +#define ALLOC_INTERFACE( name, direction, localisation, str) \ + INTERFACE_PRINT(name); \ + morpheo::behavioural::Interface_fifo * interface = _interfaces->set_interface( name); #endif -#define ALLOC_VAL_ACK_IN( sig, name, type) \ - { \ - sig = interface->set_signal_valack_in (name, type); \ - } -#define ALLOC_VAL_ACK_OUT( sig, name, type) \ - { \ - sig = interface->set_signal_valack_out(name, type); \ - } -#define ALLOC_VALACK_IN( sig, type) \ - { \ - sig = interface->set_signal_valack_in (type); \ - } -#define ALLOC_VALACK_OUT( sig, type) \ - { \ - sig = interface->set_signal_valack_out(type); \ - } -#define ALLOC_SIGNAL_IN( sig, name, type, size) \ - if (size > 0) \ - { \ - sig = interface->set_signal_in (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface->get_name().c_str(),name); \ +#define ALLOC_VAL_ACK_IN( sig, name, type) \ + { \ + sig = interface->set_signal_valack_in (name, type); \ + } +#define ALLOC_VAL_ACK_OUT( sig, name, type) \ + { \ + sig = interface->set_signal_valack_out(name, type); \ + } +#define ALLOC_VALACK_IN( sig, type) \ + { \ + sig = interface->set_signal_valack_in (type); \ + } +#define ALLOC_VALACK_OUT( sig, type) \ + { \ + sig = interface->set_signal_valack_out(type); \ + } +#define ALLOC_SIGNAL_IN( sig, name, type, size) \ + if (size > 0) \ + { \ + sig = interface->set_signal_in (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface,name); \ } -#define ALLOC_SIGNAL_OUT( sig, name, type, size) \ - if (size > 0) \ - { \ - sig = interface->set_signal_out (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface->get_name().c_str(),name); \ +#define ALLOC_SIGNAL_OUT( sig, name, type, size) \ + if (size > 0) \ + { \ + sig = interface->set_signal_out (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface,name); \ } -#define DELETE_SIGNAL( sig, size) \ - if (size > 0) \ - { \ - delete sig; \ +#define DELETE_SIGNAL( sig, size) \ + if (size > 0) \ + { \ + delete sig; \ } -#define ALLOC_SC_SIGNAL( sig, name, type) \ - sc_signal * sig = new sc_signal (name); - -#define INSTANCE_SC_SIGNAL(component, sig) \ - { \ - TEST_PTR(component->sig); \ - TEST_PTR(sig); \ - (*(component->sig)) (*(sig)); \ - } - -#define DELETE_SC_SIGNAL( sig) \ - { \ - delete sig; \ - } +#define ALLOC_SC_SIGNAL( sig, name, type) \ + sc_signal * sig = new sc_signal (name); \ + PRINT_SIGNAL_ADDRESS(name,sig); + +#define INSTANCE_SC_SIGNAL(component, sig) \ + { \ + TEST_SIGNAL(component->sig->name(),component->sig); \ + TEST_SIGNAL(sig ->name(),sig); \ + (*(component->sig)) (*(sig)); \ + } + +#define _INSTANCE_SC_SIGNAL(component, sig1,sig2) \ + { \ + TEST_SIGNAL(component->sig1->name(),component->sig1); \ + TEST_SIGNAL(sig2 ->name(),sig2); \ + (*(component->sig1)) (*(sig2)); \ + } + +#define DELETE_SC_SIGNAL( sig) \ + { \ + delete sig; \ + } + + +#define __ALLOC0_SIGNAL(sig, name, type) __ALLOC_SIGNAL(sig, name, type) + +#define ALLOC0_INTERFACE( name, direction, localisation, str) ALLOC_INTERFACE( name, direction, localisation, str) + +#define ALLOC0_VAL_ACK_IN( sig, name, type) ALLOC_VAL_ACK_IN( sig, name, type) +#define ALLOC0_VAL_ACK_OUT( sig, name, type) ALLOC_VAL_ACK_OUT( sig, name, type) +#define ALLOC0_VALACK_IN( sig, type) ALLOC_VALACK_IN( sig, type) +#define ALLOC0_VALACK_OUT( sig, type) ALLOC_VALACK_OUT( sig, type) +#define ALLOC0_SIGNAL_IN( sig, name, type, size) ALLOC_SIGNAL_IN( sig, name, type, size) +#define ALLOC0_SIGNAL_OUT( sig, name, type, size) ALLOC_SIGNAL_OUT( sig, name, type, size) +#define DELETE0_SIGNAL( sig, size) DELETE_SIGNAL( sig, size) + +#define ALLOC0_SC_SIGNAL( sig, name, type) ALLOC_SC_SIGNAL( sig, name, type) +#define INSTANCE0_SC_SIGNAL(component, sig) INSTANCE_SC_SIGNAL(component, sig) +#define _INSTANCE0_SC_SIGNAL(component, sig) _INSTANCE_SC_SIGNAL(component, sig) +#define DELETE0_SC_SIGNAL( sig) DELETE_SC_SIGNAL( sig) // ---------------------------------------------------------------------- @@ -94,160 +203,169 @@ // ---------------------------------------------------------------------- -#define __ALLOC1_INTERFACE(name, it1) \ - INTERFACE_PRINT(name); \ - const std::string interface_name = name; \ - const uint32_t iterator_1 = it1; - -#define __ALLOC1_SIGNAL_IN( sig, name, type) \ - { \ - sig = new SC_IN(type) * [iterator_1]; \ - std::string separator="_"; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_interface( name+separator+toString(alloc_interface_it1), direction, localisation, str); \ - } \ +#define ALLOC1_INTERFACE( name, direction, localisation, str, x1) \ + INTERFACE_PRINT(name); \ + const uint32_t iterator_1 = x1; \ + morpheo::behavioural::Interface_fifo * interface [iterator_1]; \ + { \ + std::string separator="_"; \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1), direction, localisation, str); \ + } \ } #else -#define ALLOC1_INTERFACE( name, direction, localisation, str, it1) \ - INTERFACE_PRINT(name); \ - const uint32_t iterator_1 = it1; \ - Interface_fifo * interface [iterator_1]; \ - { \ - std::string separator="_"; \ - for (uint32_t alloc_interface_it1=0; alloc_interface_it1set_interface( name+separator+toString(alloc_interface_it1)); \ - } \ +#define ALLOC1_INTERFACE( name, direction, localisation, str, x1) \ + INTERFACE_PRINT(name); \ + const uint32_t iterator_1 = x1; \ + morpheo::behavioural::Interface_fifo * interface [iterator_1]; \ + { \ + std::string separator="_"; \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1)); \ + } \ } #endif -#define ALLOC1_VAL_ACK_IN( sig, name, type) \ - { \ - sig = new SC_IN (Tcontrol_t) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_in (name, type); \ - } \ - } -#define ALLOC1_VAL_ACK_OUT(sig, name, type) \ - { \ - sig = new SC_OUT(Tcontrol_t) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_out(name, type); \ - } \ - } -#define ALLOC1_VALACK_IN( sig, type) \ - { \ - sig = new SC_IN (Tcontrol_t) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_in (type); \ - } \ - } -#define ALLOC1_VALACK_OUT( sig, type) \ - { \ - sig = new SC_OUT(Tcontrol_t) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_out(type); \ - } \ - } -#define ALLOC1_SIGNAL_IN( sig, name, type, size) \ - { \ - sig = new SC_IN (type) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - sig [alloc_signal_it1] = interface[alloc_signal_it1]->set_signal_in (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface[alloc_signal_it1]->get_name().c_str(),name); \ - } \ - } \ - } - -#define ALLOC1_SIGNAL_OUT(sig, name, type, size) \ - { \ - sig = new SC_OUT(type) * [iterator_1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - sig [alloc_signal_it1] = interface[alloc_signal_it1]->set_signal_out (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface[alloc_signal_it1]->get_name().c_str(),name); \ - } \ - } \ - } - -#define DELETE1_SIGNAL(sig, it1, size) \ - { \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - delete sig[alloc_signal_it1]; \ - } \ - } \ - delete [] sig; \ - } - -#define ALLOC1_SC_SIGNAL( sig, name, type, it1) \ - sc_signal ** sig = new sc_signal * [it1]; \ - { \ - std::string separator="_"; \ - std::string str; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 (str.c_str()); \ - } \ - } - -#define INSTANCE1_SC_SIGNAL(component, sig, it1) \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1sig [alloc_signal_it1]); \ - TEST_PTR(sig [alloc_signal_it1]); \ - (*(component->sig[alloc_signal_it1])) (*(sig[alloc_signal_it1])); \ +#define ALLOC1_VAL_ACK_IN( sig, name, type) \ + { \ + sig = new SC_IN (Tcontrol_t) * [iterator_1]; \ + for (uint32_t it1=0; it1set_signal_valack_in (name, type); \ + } \ + } +#define ALLOC1_VAL_ACK_OUT(sig, name, type) \ + { \ + sig = new SC_OUT(Tcontrol_t) * [iterator_1]; \ + for (uint32_t it1=0; it1set_signal_valack_out(name, type); \ + } \ + } +#define ALLOC1_VALACK_IN( sig, type) \ + { \ + sig = new SC_IN (Tcontrol_t) * [iterator_1]; \ + for (uint32_t it1=0; it1set_signal_valack_in (type); \ + } \ + } +#define ALLOC1_VALACK_OUT( sig, type) \ + { \ + sig = new SC_OUT(Tcontrol_t) * [iterator_1]; \ + for (uint32_t it1=0; it1set_signal_valack_out(type); \ + } \ + } +#define ALLOC1_SIGNAL_IN( sig, name, type, size) \ + { \ + sig = new SC_IN (type) * [iterator_1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1] = interface[it1]->set_signal_in (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1],name); \ + } \ + } \ + } + +#define ALLOC1_SIGNAL_OUT(sig, name, type, size) \ + { \ + sig = new SC_OUT(type) * [iterator_1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1] = interface[it1]->set_signal_out (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1],name); \ + } \ + } \ + } + +#define DELETE1_SIGNAL(sig, x1, size) \ + { \ + for (uint32_t it1=0; it1 0) \ + { \ + delete sig[it1]; \ + } \ + } \ + delete [] sig; \ + } + +#define ALLOC1_SC_SIGNAL( sig, name, type, x1) \ + sc_signal ** sig = new sc_signal * [x1]; \ + { \ + std::string separator="_"; \ + std::string str; \ + for (uint32_t it1=0; it1 (str.c_str()); \ + PRINT_SIGNAL_ADDRESS(str.c_str(),sig[it1]); \ + } \ + } + +#define INSTANCE1_SC_SIGNAL(component, sig, x1) \ + for (uint32_t it1=0; it1sig [it1]->name(),component->sig [it1]); \ + TEST_SIGNAL(sig [it1]->name(),sig [it1]); \ + (*(component->sig[it1])) (*(sig[it1])); \ } -#define DELETE1_SC_SIGNAL(sig, it1) \ - { \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1sig1 [it1]->name(),component->sig1 [it1]); \ + TEST_SIGNAL(sig2 [it1]->name(),sig2 [it1]); \ + (*(component->sig1[it1])) (*(sig2[it1])); \ + } + +#define DELETE1_SC_SIGNAL(sig, x1) \ + { \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(alloc_interface_it1)+separator+toString(alloc_interface_it2), direction, localisation, str); \ - } \ - } \ +#define ALLOC2_INTERFACE( name, direction, localisation, str, x1, x2) \ + INTERFACE_PRINT(name); \ + uint32_t iterator_1 = 0; \ + uint32_t iterator_2 = 0; \ + morpheo::behavioural::Interface_fifo *** interface; \ + { \ + std::string separator="_"; \ + iterator_1 = x1; \ + interface = new morpheo::behavioural::Interface_fifo ** [iterator_1]; \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1)+separator+toString(it2), direction, localisation, str); \ + } \ + } \ } #else -#define ALLOC2_INTERFACE( name, direction, localisation, str, it1, it2) \ - INTERFACE_PRINT(name); \ - uint32_t iterator_1 = 0; \ - uint32_t iterator_2 = 0; \ - Interface_fifo *** interface; \ - { \ - std::string separator="_"; \ - iterator_1 = it1; \ - interface = new Interface_fifo ** [iterator_1]; \ - for (uint32_t alloc_interface_it1=0; alloc_interface_it1set_interface( name+separator+toString(alloc_interface_it1)+separator+toString(alloc_interface_it2)); \ - } \ - } \ +#define ALLOC2_INTERFACE( name, direction, localisation, str, x1, x2) \ + INTERFACE_PRINT(name); \ + uint32_t iterator_1 = 0; \ + uint32_t iterator_2 = 0; \ + morpheo::behavioural::Interface_fifo *** interface; \ + { \ + std::string separator="_"; \ + iterator_1 = x1; \ + interface = new morpheo::behavioural::Interface_fifo ** [iterator_1]; \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1)+separator+toString(it2)); \ + } \ + } \ } #endif -#define _ALLOC2_VAL_ACK_IN( sig, name, type, it1, it2) \ - { \ - sig = new SC_IN (Tcontrol_t) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_in (name, type); \ - } \ - } \ - } - -#define _ALLOC2_VAL_ACK_OUT( sig, name, type, it1, it2) \ - { \ - sig = new SC_OUT (Tcontrol_t) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_out (name, type); \ - } \ - } \ - } - -#define _ALLOC2_VALACK_IN( sig,type, it1, it2) \ - { \ - sig = new SC_IN (Tcontrol_t) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_in (type); \ - } \ - } \ - } - -#define _ALLOC2_VALACK_OUT( sig,type, it1, it2) \ - { \ - sig = new SC_OUT (Tcontrol_t) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1set_signal_valack_out (type); \ - } \ - } \ - } - -#define _ALLOC2_SIGNAL_IN( sig, name, type, size, it1, it2) \ - { \ - sig = new SC_IN (type) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - sig [alloc_signal_it1][alloc_signal_it2] = interface[alloc_signal_it1][alloc_signal_it2]->set_signal_in (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface[alloc_signal_it1][alloc_signal_it2]->get_name().c_str(),name); \ - } \ - } \ - } \ - } - -#define _ALLOC2_SIGNAL_OUT( sig, name, type, size, it1, it2) \ - { \ - sig = new SC_OUT (type) ** [it1]; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - sig [alloc_signal_it1][alloc_signal_it2] = interface[alloc_signal_it1][alloc_signal_it2]->set_signal_out (name, size); \ - } \ - else \ - { \ - log_printf(INFO,true,FUNCTION,_("%s %s.%s.%s : size is nul."),MSG_INFORMATION,_component->get_name().c_str(),interface[alloc_signal_it1][alloc_signal_it2]->get_name().c_str(),name); \ - } \ - } \ - } \ +#define _ALLOC2_VAL_ACK_IN( sig, name, type, x1, x2) \ + { \ + sig = new SC_IN (Tcontrol_t) ** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_in (name, type); \ + } \ + } \ + } + +#define _ALLOC2_VAL_ACK_OUT( sig, name, type, x1, x2) \ + { \ + sig = new SC_OUT (Tcontrol_t) ** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_out (name, type); \ + } \ + } \ + } + +#define _ALLOC2_VALACK_IN( sig,type, x1, x2) \ + { \ + sig = new SC_IN (Tcontrol_t) ** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_in (type); \ + } \ + } \ + } + +#define _ALLOC2_VALACK_OUT( sig,type, x1, x2) \ + { \ + sig = new SC_OUT (Tcontrol_t) ** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_out (type); \ + } \ + } \ + } + +#define _ALLOC2_SIGNAL_IN( sig, name, type, size, x1, x2) \ + { \ + sig = new SC_IN (type) ** [x1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1][it2] = interface[it1][it2]->set_signal_in (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1][it2],name); \ + } \ + } \ + } \ + } + +#define _ALLOC2_SIGNAL_OUT( sig, name, type, size, x1, x2) \ + { \ + sig = new SC_OUT (type) ** [x1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1][it2] = interface[it1][it2]->set_signal_out (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1][it2],name); \ + } \ + } \ + } \ } @@ -397,57 +515,296 @@ #define ALLOC2_SIGNAL_OUT( sig, name, type, size) _ALLOC2_SIGNAL_OUT( sig, name, type, size, iterator_1, iterator_2) -#define DELETE2_SIGNAL(sig, it1,it2, size) \ - { \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 0) \ - { \ - delete sig[alloc_signal_it1][alloc_signal_it2]; \ - } \ - } \ - delete [] sig[alloc_signal_it1]; \ - } \ - delete [] sig; \ - } - -#define ALLOC2_SC_SIGNAL( sig, name, type, it1, it2) \ - sc_signal *** sig = new sc_signal ** [it1]; \ - { \ - std::string separator="_"; \ - std::string str; \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1 * [it2]; \ - for (uint32_t alloc_signal_it2=0; alloc_signal_it2 (str.c_str()); \ - } \ - } \ - } - -#define INSTANCE2_SC_SIGNAL(component, sig, it1, it2) \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1sig [alloc_signal_it1][alloc_signal_it2]); \ - TEST_PTR(sig [alloc_signal_it1][alloc_signal_it2]); \ - (*(component->sig[alloc_signal_it1][alloc_signal_it2])) (*(sig[alloc_signal_it1][alloc_signal_it2])); \ +#define DELETE2_SIGNAL(sig, x1,x2, size) \ + { \ + for (uint32_t it1=0; it1 0) \ + { \ + delete sig[it1][it2]; \ + } \ + } \ + delete [] sig[it1]; \ + } \ + delete [] sig; \ + } + +#define ALLOC2_SC_SIGNAL( sig, name, type, x1, x2) \ + sc_signal *** sig = new sc_signal ** [x1]; \ + { \ + std::string separator="_"; \ + std::string str; \ + for (uint32_t it1=0; it1 * [x2]; \ + for (uint32_t it2=0; it2 (str.c_str()); \ + PRINT_SIGNAL_ADDRESS(str.c_str(),sig[it1][it2]); \ + } \ + } \ + } + +#define INSTANCE2_SC_SIGNAL(component, sig, x1, x2) \ + for (uint32_t it1=0; it1sig [it1][it2]->name(),component->sig [it1][it2]); \ + TEST_SIGNAL(sig [it1][it2]->name(),sig [it1][it2]); \ + (*(component->sig[it1][it2])) (*(sig[it1][it2])); \ } -#define DELETE2_SC_SIGNAL(sig,it1,it2) \ - { \ - for (uint32_t alloc_signal_it1=0; alloc_signal_it1sig1 [it1][it2]->name(),component->sig1 [it1][it2]); \ + TEST_SIGNAL(sig2 [it1][it2]->name(),sig2 [it1][it2]); \ + (*(component->sig1[it1][it2])) (*(sig2[it1][it2])); \ + } + +#define DELETE2_SC_SIGNAL(sig,x1,x2) \ + { \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1)+separator+toString(it2)+separator+toString(it3), direction, localisation, str); \ + } \ + } \ + } \ + } +#else +#define ALLOC3_INTERFACE( name, direction, localisation, str, x1, x2, x3) \ + INTERFACE_PRINT(name); \ + uint32_t iterator_1 = 0; \ + uint32_t iterator_2 = 0; \ + uint32_t iterator_3 = 0; \ + morpheo::behavioural::Interface_fifo **** interface; \ + { \ + std::string separator="_"; \ + iterator_1 = x1; \ + interface = new morpheo::behavioural::Interface_fifo *** [iterator_1]; \ + for (uint32_t it1=0; it1set_interface( name+separator+toString(it1)+separator+toString(it2)+separator+toString(it3)); \ + } \ + } \ + } \ + } #endif + +// #define _ALLOC3_VAL_ACK_IN( sig, name, type, x1, x2, x3) +// #define _ALLOC3_VAL_ACK_OUT( sig, name, type, x1, x2, x3) + +#define _ALLOC3_VALACK_IN( sig,type, x1, x2, x3) \ + { \ + sig = new SC_IN (Tcontrol_t) *** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_in (type); \ + } \ + } \ + } \ + } + +#define _ALLOC3_VALACK_OUT( sig,type, x1, x2, x3) \ + { \ + sig = new SC_OUT (Tcontrol_t) *** [x1]; \ + for (uint32_t it1=0; it1set_signal_valack_out (type); \ + } \ + } \ + } \ + } + + +#define _ALLOC3_SIGNAL_IN( sig, name, type, size, x1, x2,x3) \ + { \ + sig = new SC_IN (type) *** [x1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1][it2][it3] = interface[it1][it2][it3]->set_signal_in (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1][it2][it3],name); \ + } \ + } \ + } \ + } \ + } + +#define _ALLOC3_SIGNAL_OUT( sig, name, type, size, x1, x2,x3) \ + { \ + sig = new SC_OUT (type) *** [x1]; \ + for (uint32_t it1=0; it1 0) \ + { \ + sig [it1][it2][it3] = interface[it1][it2][it3]->set_signal_out (name, size); \ + } \ + else \ + { \ + PRINT_SIZE_NUL(_component,interface[it1][it2][it3],name); \ + } \ + } \ + } \ + } \ + } + +// #define ALLOC3_VAL_ACK_IN( sig, name, type ) _ALLOC3_VAL_ACK_IN( sig, name, type , iterator_1, iterator_2, iterator_3) +// #define ALLOC3_VAL_ACK_OUT(sig, name, type ) _ALLOC3_VAL_ACK_OUT(sig, name, type , iterator_1, iterator_2, iterator_3) +#define ALLOC3_VALACK_IN( sig, type ) _ALLOC3_VALACK_IN( sig, type , iterator_1, iterator_2, iterator_3) +#define ALLOC3_VALACK_OUT( sig, type ) _ALLOC3_VALACK_OUT( sig, type , iterator_1, iterator_2, iterator_3) +#define ALLOC3_SIGNAL_IN( sig, name, type, size) _ALLOC3_SIGNAL_IN( sig, name, type, size, iterator_1, iterator_2, iterator_3) +#define ALLOC3_SIGNAL_OUT( sig, name, type, size) _ALLOC3_SIGNAL_OUT( sig, name, type, size, iterator_1, iterator_2, iterator_3) + +#define DELETE3_SIGNAL(sig, x1, x2, x3, size) \ + { \ + for (uint32_t it1=0; it1 0) \ + { \ + delete sig[it1][it2][it3]; \ + } \ + } \ + delete [] sig[it1][it2]; \ + } \ + delete [] sig[it1]; \ + } \ + delete [] sig; \ + } + +#define ALLOC3_SC_SIGNAL( sig, name, type, x1, x2, x3) \ + sc_signal **** sig = new sc_signal *** [x1]; \ + { \ + std::string separator="_"; \ + std::string str; \ + for (uint32_t it1=0; it1 ** [x2]; \ + for (uint32_t it2=0; it2 * [x3]; \ + for (uint32_t it3=0; it3 (str.c_str()); \ + PRINT_SIGNAL_ADDRESS(str.c_str(),sig[it1][it2][it3]); \ + } \ + } \ + } \ + } + +#define INSTANCE3_SC_SIGNAL(component, sig, x1, x2, x3) \ + for (uint32_t it1=0; it1sig [it1][it2][it3]->name(),component->sig [it1][it2][it3]); \ + TEST_SIGNAL(sig [it1][it2][it3]->name(),sig [it1][it2][it3]); \ + (*(component->sig[it1][it2][it3])) (*(sig[it1][it2][it3])); \ + } + +#define _INSTANCE3_SC_SIGNAL(component, sig1, sig2, x1, x2, x3) \ + for (uint32_t it1=0; it1sig1 [it1][it2][it3]->name(),component->sig1 [it1][it2][it3]); \ + TEST_SIGNAL(sig2 [it1][it2][it3]->name(),sig2 [it1][it2][it3]); \ + (*(component->sig1[it1][it2][it3])) (*(sig2[it1][it2][it3])); \ + } + +#define DELETE3_SC_SIGNAL(sig,x1,x2,x3) \ + { \ + for (uint32_t it1=0; it1 + +namespace morpheo { + namespace ReferenceCountersUtils { + + //*****************************************Class declaration*****************************************// + + class ClassicReferenceCounter : virtual public IReferenceCounter { + private: + unsigned long m_ulReferenceCounter; + protected: + inline explicit ClassicReferenceCounter(void); + inline ~ClassicReferenceCounter(void); + public: + inline unsigned long getReferenceCount(void) const; + + inline unsigned long attach(void); + + inline unsigned long detach(void); + }; + + //**********************************Inline definition************************************************// + + ClassicReferenceCounter::ClassicReferenceCounter(void) : m_ulReferenceCounter(1) {} + + ClassicReferenceCounter::~ClassicReferenceCounter(void) { + assert( m_ulReferenceCounter == 0 || m_ulReferenceCounter == 1 ); + } + + unsigned long ClassicReferenceCounter::attach(void) { + return ++m_ulReferenceCounter; + } + + unsigned long ClassicReferenceCounter::detach(void) { + return --m_ulReferenceCounter ? m_ulReferenceCounter : (delete this , 0 ) ; + } + + + unsigned long ClassicReferenceCounter::getReferenceCount(void) const { + return m_ulReferenceCounter; + } + + } //end of namespace ReferenceCountersUtils. +}// end of namespace morpheo. + +#endif // _CLASSIC_REF_COUNTER_ + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Configuration_Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Configuration_Parameters.h (revision 87) +++ (revision ) @@ -1,56 +1,0 @@ -#ifndef morpheo_behavioural_Configuration_Parameters_h -#define morpheo_behavioural_Configuration_Parameters_h -#ifdef CONFIGURATION - -/* - * $Id$ - * - * [ Description ] - * - */ - -#include -#include -#include "Behavioural/include/XML.h" -#include "Behavioural/include/Environment.h" -#include "Common/include/ErrorMorpheo.h" -#include "Common/include/ToString.h" - -namespace morpheo { -namespace behavioural { - - class Configuration_Parameters - { - // -----[ fields ]---------------------------------------------------- - // Constant - public : const std::string _name ; - public : const uint32_t _value ; - public : const uint32_t _min ; - public : const uint32_t _max ; - public : const std::string _step ; - public : const uint32_t _default; - public : const uint32_t _level ; - public : const std::string _comment; - - // -----[ methods ]--------------------------------------------------- - public : Configuration_Parameters (std::string name , - uint32_t value , - uint32_t min , - uint32_t max , - std::string step , - uint32_t value_default, - uint32_t level , - std::string comment); - public : ~Configuration_Parameters (); - - // methods to print and test parameters_configuration - public : std::string print (uint32_t depth); - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::Configuration_Parameters & x); - }; - -}; // end namespace behavioural -}; // end namespace morpheo - -#endif -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 88) @@ -2,6 +2,33 @@ #define morpheo_behavioural_Constants_h +/* + WARNING : + + I Use reserved exception : + + 0x10 - EXCEPTION_MEMORY_MISS_SPECULATION - Load miss speculation + 0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE - The load is speculative : write in register file, but don't commit + 0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID - SPR present in ALU but not compatible privilege + 0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ - SPR not present in ALU + 0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU + + I Use reserved SPR : + [0][19] - SPR_CID +*/ + namespace morpheo { namespace behavioural { + +# define SET_FLAG( x,pos) {(x) |= (1<<(pos));} while (0) +# define UNSET_FLAG( x,pos) {(x) &= ~(1<<(pos));} while (0) +# define IS_SET_FLAG( x,pos) (((x) & (1<<(pos))) != 0) +# define IS_UNSET_FLAG(x,pos) (((x) & (1<<(pos))) == 0) +# define CHANGE_FLAG( x,pos,f) \ + { \ + if (f) \ + {SET_FLAG(x,pos);} \ + else \ + {UNSET_FLAG(x,pos);} \ + } while (0) //=========================================================[ Type ]===== @@ -10,14 +37,30 @@ # define TYPE_MOVE 0x2 // 00000 - unit multiple # define TYPE_TEST 0x3 // 00000 - unit multiple -# define TYPE_MUL_DIV 0x4 // 00000 - unit multiple -# define TYPE_EXTEND 0x5 // 00000 - unit multiple, type optionnal -# define TYPE_FIND 0x6 // 00000 - unit multiple, type optionnal -# define TYPE_SPECIAL 0x7 // 00000 - unit uniq -# define TYPE_CUSTOM 0x8 // 00000 - unit uniq , type optionnal -# define TYPE_BRANCH 0x9 // 00000 - unit multiple -# define TYPE_MEMORY 0xa // 00000 - unit uniq - +# define TYPE_MUL 0x4 // 00000 - unit multiple +# define TYPE_DIV 0x5 // 00000 - unit multiple, type optionnal +# define TYPE_EXTEND 0x6 // 00000 - unit multiple, type optionnal +# define TYPE_FIND 0x7 // 00000 - unit multiple, type optionnal +# define TYPE_SPECIAL 0x8 // 00000 - unit uniq +# define TYPE_CUSTOM 0x9 // 00000 - unit uniq , type optionnal +# define TYPE_BRANCH 0xa // 00000 - unit multiple +# define TYPE_MEMORY 0xb // 00000 - unit uniq + +//#define NB_TYPE 11 # define SIZE_TYPE 5 # define MAX_TYPE (1< incondionnal -#define BRANCH_STATE_SPEC_NTAKE 2 // 1 0 -#define BRANCH_STATE_SPEC_TAKE 3 // 1 1 - -//---------------------------------------------------- -// Name to particular register -//---------------------------------------------------- - -//~~~~~~~~~~~~~~~~~~~~~~~~~~ -// GENERAL PURPOSE REGISTER -//~~~~~~~~~~~~~~~~~~~~~~~~~~ -#define M_CPU_LOG2_NB_GPR_LOG 5 -#define M_CPU_NB_GPR_LOG (1< + +using std::basic_ifstream; + +namespace morpheo { + namespace XMLUtils { + //**************************************Class Declaration*******************************************// + + template + class FileXMLLight : public AbstractXMLLight { + public: + inline explicit FileXMLLight(const basic_ifstream & inputFileStream, + IXMLLight * parent = NULL ); + }; + + //*****************************************Inline Implementation*************************************// + template < typename char_type, typename ref_counter_type> + FileXMLLight::FileXMLLight + (const basic_ifstream & inputFileStream, IXMLLight * parent) + : AbstractXMLLight(inputFileStream, parent) {} + + } +} +#endif //_FILE_XMLLIGHT_H Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IReferenceCounters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IReferenceCounters.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IReferenceCounters.h (revision 88) @@ -0,0 +1,25 @@ +#ifndef _REFERENCE_COUNTER_ +#define _REFERENCE_COUNTER_ + +namespace morpheo { + namespace ReferenceCountersUtils { + + //**********************************Class Declaration********************************************// + + template< typename reference_counter_type> class IReferenceCounter { + public: + virtual inline ~IReferenceCounter(void) = 0; + + virtual reference_counter_type attach(void) = 0; + virtual reference_counter_type detach(void) = 0; + }; + + //**********************************Inline implementation*****************************************// + + template < typename reference_counter_type> + IReferenceCounter::~IReferenceCounter(void) {} + + } // end of ReferenceCountersUtils namespace. +} // end of morpheo namespace. + +#endif // end of _REFERENCE_COUNTER_ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IXMLLight.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IXMLLight.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/IXMLLight.h (revision 88) @@ -0,0 +1,79 @@ +#ifndef _XMLLIGHT_H +#define _XMLLIGHT_H + +#include +#include +#include "Behavioural/include/ClassicReferenceCounter.h" +#include "Behavioural/include/XMLLightVector.h" + +using std::map; +using std::basic_string; +using morpheo::ReferenceCountersUtils::ClassicReferenceCounter; + +namespace morpheo { + namespace XMLUtils { + + //*******************************Class Declaration***************************************************// + + enum ETEXT_ENCODING { + ASCII, + UTF8, + UTF16, + // UTF16_LE, + // UTF16_BE, + UTF32 + }; + + + // the main interface for XML parsing used a reference counter class to implement ref counting + + template< typename char_type, typename ReferenceCounter = ClassicReferenceCounter> class IXMLLight + : virtual public ReferenceCounter { + protected : + typedef IXMLLight XMLLight; + typedef basic_string string; + public : + // used to fetch XML Nodes contains inside a XMLLight object with the pattern name + virtual XMLLightVector getNodes( const string & pattern = "") = 0; + //virtual XMLLight & getFirstNode ( const string & pattern ) = 0 ; + //virtual XMLLight & getRoot ( void ) = 0 ; + + // fetch the name of tne node selected + virtual basic_string getName ( void ) = 0 ; + // fetch the encoding used inside the XML document. + //virtual ETEXT_ENCODING getEncodingForm ( void ) = 0; + + /* + virtual string & getValue ( void ) = 0 ; + virtual string & getValue ( const string & firstNodeName ) = 0 ; + */ + virtual bool containsAttribute ( const basic_string & attributeName ) = 0 ; + + virtual map, basic_string > getAttributes ( void ) = 0 ; + + virtual basic_string getAttributeValue ( const basic_string & attributeName ) = 0; + virtual basic_string getInternalString(void) const = 0 ; + // only instanciated to bring a virtual destructor. + virtual inline ~IXMLLight( void ) = 0 ; + + }; + + //*************************************Inline implementation*****************************************// + + // implementation of XMLLight virtual destructor. + template IXMLLight::~IXMLLight(void) {} + + //******************************** Typedef of multiple XMLLight Interface**********************// + + // valid with 32 bits computer only . don't forget use of widen to widening string + + typedef IXMLLight IXMLLightASCII; + typedef IXMLLight IXMLLightUTF8; + typedef IXMLLight IXMLLightUTF16; + typedef IXMLLight IXMLLightUTF32; + + + } // end of XMLUtils namespace. +} // end of morpheo namespace. + +#endif // _XMLLIGHT_H Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface.h (revision 88) @@ -34,5 +34,5 @@ { // -----[ fields ]---------------------------------------------------- - protected : const std::string _name ; + protected : const std::string _name ; #ifdef POSITION protected : const direction_t _direction ; @@ -42,8 +42,8 @@ #ifdef POSITION - protected : std::string _comment ; -#endif - - protected : std::list * _list_signal ; + protected : std::string _comment ; +#endif + + protected : std::list * _list_signal ; #ifdef POSITION @@ -69,13 +69,13 @@ public : ~Interface (); - public : std::string get_name (); + public : std::string get_name (); #ifdef POSITION public : void set_comment (std::string comment); - protected : std::string get_comment (void ); -#endif - - protected : std::string signal_name (std::string name_interface, - std::string name_signal , + protected : std::string get_comment (void); +#endif + + protected : std::string signal_name (std::string name_interface, + std::string name_signal , direction_t direction ); @@ -83,13 +83,13 @@ public : bool find_signal (Signal * signal); - protected : std::string get_signal (void); - public : Signal * set_signal (std::string name , + protected : std::string get_signal (void); + public : Signal * set_signal (std::string name , direction_t direction, uint32_t size , presence_port_t presence_port = PORT_VHDL_YES_TESTBENCH_YES); - public : std::list * get_signal_list (void); + public : std::list * get_signal_list (void); #ifdef SYSTEMC - public : sc_in_clk * set_signal_clk (std::string name , + public : sc_in_clk * set_signal_clk (std::string name , uint32_t size , presence_port_t presence_port=CLOCK_VHDL_YES) @@ -120,5 +120,5 @@ public : template - sc_in * set_signal_in (std::string name , + sc_in * set_signal_in (std::string name , uint32_t size , presence_port_t presence_port=PORT_VHDL_YES_TESTBENCH_YES) @@ -149,5 +149,5 @@ public : template - sc_out * set_signal_out (std::string name , + sc_out * set_signal_out (std::string name , uint32_t size , presence_port_t presence_port=PORT_VHDL_YES_TESTBENCH_YES) @@ -218,17 +218,17 @@ public : void testbench_cycle (void); public : void testbench_body (Vhdl * & vhdl , - std::string counter_name , - std::string reset_name ); + std::string counter_name , + std::string reset_name ); public : std::string testbench_test (Vhdl * & vhdl , - std::string counter_name, - std::string reset_name); - public : std::string testbench_test_ok (Vhdl * & vhdl ); - protected : std::string testbench_test_name (Vhdl * & vhdl); - protected : std::string testbench_test_ok_name(Vhdl * & vhdl); - protected : std::string testbench_test_transaction_name(Vhdl * & vhdl); + std::string counter_name, + std::string reset_name); + public : std::string testbench_test_ok (Vhdl * & vhdl); + protected : std::string testbench_test_name (Vhdl * & vhdl); + protected : std::string testbench_test_ok_name (Vhdl * & vhdl); + protected : std::string testbench_test_transaction_name (Vhdl * & vhdl); #endif public : bool test_map (uint32_t depth, bool top_level, bool is_behavioural); -// public : bool test_equi (uint32_t depth); +//public : bool test_equi (uint32_t depth); #ifdef POSITION @@ -238,6 +238,6 @@ public : XML toXML_mapping (void); #endif - public : friend std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::Interface & x); + public : friend std::ostream& operator<< (std::ostream& output_stream, + morpheo::behavioural::Interface & x); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interface_fifo.h (revision 88) @@ -5,5 +5,5 @@ * $Id$ * - * [ Description ] + * [ Description ] * */ @@ -35,9 +35,9 @@ #ifdef VHDL_TESTBENCH - private : bool _test_exhaustive; + private : bool _test_exhaustive; private : std::list * _list_cycle ; #endif - // -----[ methods ]--------------------------------------------------- + // -----[ methods ]--------------------------------------------------- public : Interface_fifo (std::string name #ifdef POSITION @@ -107,7 +107,11 @@ public : bool testbench_transaction(void); public : void testbench_cycle (void); - public : std::string testbench_test (Vhdl * & vhdl , - std::string counter_name, - std::string reset_name ); + public : std::string testbench_test (Vhdl * & vhdl , + std::string counter_name, + std::string reset_name ); +#ifdef VHDL_TESTBENCH_ASSERT + public : void testbench_assert (Vhdl * & vhdl , + std::string counter_name); +#endif public : std::string testbench_test_transaction (Vhdl * & vhdl); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Interfaces.h (revision 88) @@ -27,7 +27,7 @@ { // -----[ fields ]---------------------------------------------------- - private : const std::string _name; - private : const Tusage_t _usage; - private : std::list * _list_interface; + private : const std::string _name; + private : const Tusage_t _usage; + private : std::list * _list_interface; // -----[ methods ]--------------------------------------------------- Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Operation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Operation.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Operation.h (revision 88) @@ -0,0 +1,26 @@ +#ifndef Morpheo_Behavioural_Operation_h +#define Morpheo_Behavioural_Operation_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +namespace morpheo { +namespace behavioural { + +#define neg(size,data) (~(data)+1) +#define sign(size,data) ((data)>>(size-1)) +#define unsigned(size,data) (data) +#define signed(size,data) ((sign(size,data)==0)?(data):neg(size,data)) +#define ovf(size,op1, op2, res) ((sign(size,op1) == sign(size,op2))?(sign(size,op1) xor sign(size,res)):0) +#define carry(size,op1, op2, res) (((res)<(op1)) or ((res)<(op2))) +#define set_flag(data,flag,is_set) (((is_set)==1)?((data)|(flag)):((data)&~(flag))) +#define get_flag(data,flag) (((data)&(flag))!=0) +#define concatenation_bool(a,b) (((a)<<1) | (b)) + +}; // end namespace behavioural +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters.h (revision 88) @@ -9,8 +9,6 @@ */ -#include -#include -#include -#include "Behavioural/include/Environment.h" +#include "Common/include/Environment.h" +#include "Behavioural/include/Parameters_test.h" #include "Behavioural/include/Constants.h" #include "Behavioural/include/Test.h" @@ -19,34 +17,16 @@ #include "Common/include/Log2.h" #include "Common/include/Debug.h" +#include +#include +#include namespace morpheo { namespace behavioural { + +#ifdef COPY +#error "Need COPY macro" +#endif - template bool test (uint32_t size) - { - return (size <= (8*sizeof(T))); - }; - - class Parameters_test - { - private : std::string _component; - protected : std::string _error; - protected : std::string _warning; - protected : std::string _information; - - public : Parameters_test (std::string component) - { - _component = component; - _error = ""; - _warning = ""; - }; - public : ~Parameters_test (void) {}; - - public : bool have_error (void) { return (_error.length() != 0);}; - public : void error (std::string str) { _error += MSG_ERROR ; _error += " <" + _component + "> " + str + "\n";} - public : void warning (std::string str) { _warning += MSG_WARNING ; _warning += " <" + _component + "> " + str + "\n";} - public : void information (std::string str) { _information += MSG_INFORMATION; _information += " <" + _component + "> " + str + "\n";} - public : std::string print (void) { return _error + _warning + _information;}; - }; +#define COPY(param) do {duplicate(param); param->copy();} while (0) // Virtual Class - Interface of each component @@ -54,28 +34,94 @@ { // -----[ fields ]---------------------------------------------------- - public : static const uint32_t _size_instruction = 32; - public : static const uint32_t _nb_operation = MAX_OPERATION; - public : static const uint32_t _nb_type = MAX_TYPE; - public : static const uint32_t _size_operation = SIZE_OPERATION; - public : static const uint32_t _size_type = SIZE_TYPE; - public : static const uint32_t _size_exception = SIZE_EXCEPTION; - public : static const uint32_t _size_exception_use = SIZE_EXCEPTION_USE; - public : static const uint32_t _size_exception_memory = SIZE_EXCEPTION_MEMORY; - public : static const uint32_t _size_exception_custom = SIZE_EXCEPTION_CUSTOM; - public : static const uint32_t _size_exception_alu = SIZE_EXCEPTION_ALU ; - public : static const uint32_t _size_exception_decod = SIZE_EXCEPTION_DECOD ; - public : static const uint32_t _size_exception_ifetch = SIZE_EXCEPTION_IFETCH; - public : static const uint32_t _size_icache_type = SIZE_ICACHE_TYPE; - public : static const uint32_t _size_icache_error = SIZE_ICACHE_ERROR; - public : static const uint32_t _size_dcache_type = SIZE_DCACHE_TYPE; - public : static const uint32_t _size_dcache_error = SIZE_DCACHE_ERROR; - public : static const uint32_t _nb_general_register_logic = 32; - public : static const uint32_t _nb_special_register_logic = NB_SPR_LOGIC; - public : static const uint32_t _size_general_register_logic = 5; - public : static const uint32_t _size_special_register_logic = LOG2_NB_SPR_LOGIC; - public : static const uint32_t _size_event_state = SIZE_EVENT_STATE; - public : static const uint32_t _size_event_type = SIZE_EVENT_TYPE; - public : static const uint32_t _size_branch_state = SIZE_BRANCH_STATE; - public : static const uint32_t _size_branch_condition = SIZE_BRANCH_CONDITION; + public : static const uint32_t _size_instruction = 32; + public : static const uint32_t _size_spr = 32; + public : static const uint32_t _nb_operation = MAX_OPERATION; + public : static const uint32_t _nb_type = MAX_TYPE; + public : static const uint32_t _size_operation = SIZE_OPERATION; + public : static const uint32_t _size_type = SIZE_TYPE; + public : static const uint32_t _size_exception = SIZE_EXCEPTION; + public : static const uint32_t _size_exception_use = SIZE_EXCEPTION_USE; + public : static const uint32_t _size_exception_memory = SIZE_EXCEPTION_MEMORY; + public : static const uint32_t _size_exception_custom = SIZE_EXCEPTION_CUSTOM; + public : static const uint32_t _size_exception_alu = SIZE_EXCEPTION_ALU ; + public : static const uint32_t _size_exception_decod = SIZE_EXCEPTION_DECOD ; + public : static const uint32_t _size_exception_ifetch = SIZE_EXCEPTION_IFETCH; + public : static const uint32_t _size_icache_type = SIZE_ICACHE_TYPE; + public : static const uint32_t _size_icache_error = SIZE_ICACHE_ERROR; + public : static const uint32_t _size_dcache_type = SIZE_DCACHE_TYPE; + public : static const uint32_t _size_dcache_error = SIZE_DCACHE_ERROR; + public : static const uint32_t _nb_general_register_logic = 32; + public : static const uint32_t _nb_special_register_logic = NB_SPR_LOGIC; + public : static const uint32_t _size_general_register_logic = 5; + public : static const uint32_t _size_special_register_logic = LOG2_NB_SPR_LOGIC; + public : static const uint32_t _size_special_address_group = 5; + public : static const uint32_t _size_special_address_register = 11; + public : static const uint32_t _size_event_state = SIZE_EVENT_STATE; + public : static const uint32_t _size_event_type = SIZE_EVENT_TYPE; + public : static const uint32_t _size_branch_state = SIZE_BRANCH_STATE; + public : static const uint32_t _size_branch_condition = SIZE_BRANCH_CONDITION; + + public : static const uint32_t _shift_spr_num_group = _size_special_address_register; + public : static const uint32_t _mask_spr_num_group = 0x1f ; // 1_1111 + public : static const uint32_t _mask_spr_num_reg = 0x7ff; // 111_1111_1111 + + // simulation + public : uint64_t _simulation_nb_cyle ; + public : uint64_t _simulation_nb_instruction ; + + // parameters depends + public : uint32_t _size_context_id ; + public : bool _have_port_context_id ; + + public : uint32_t _size_front_end_id ; + public : bool _have_port_front_end_id ; + + public : uint32_t _size_ooo_engine_id ; + public : bool _have_port_ooo_engine_id ; + + public : uint32_t _size_instruction_address ; +//public : bool _have_port_instruction_address ; // always true + + public : uint32_t _size_data_address ; +//public : bool _have_port_data_address ; // always true + + public : uint32_t _size_nb_inst_decod ; +//public : bool _have_port_nb_inst_decod ; // always true + + public : uint32_t _size_nb_inst_commit ; +//public : bool _have_port_nb_inst_commit ; // always true + + public : uint32_t _size_depth ; + public : bool _have_port_depth ; + + public : uint32_t _size_ifetch_queue_ptr ; + public : bool _have_port_ifetch_queue_ptr ; + + public : uint32_t _size_inst_ifetch_ptr ; // nb_inst_fetch + public : bool _have_port_inst_ifetch_ptr ; + +//public : uint32_t _size_branch_update_prediction_id ; // = size_depth +//public : bool _have_port_branch_update_prediction_id ; // = size_depth + + public : uint32_t _size_rob_ptr ; + public : bool _have_port_rob_ptr ; + + public : uint32_t _size_load_queue_ptr ; + public : bool _have_port_load_queue_ptr ; + + public : uint32_t _size_store_queue_ptr ; +//public : bool _have_port_store_queue_ptr ; // always true (min = 1) + + public : uint32_t _size_general_data ; +//public : bool _have_port_general_data ; // always true + + public : uint32_t _size_special_data ; +//public : bool _have_port_special_data ; // always true + + public : uint32_t _size_general_register ; +//public : bool _have_port_general_register ; // always true + + public : uint32_t _size_special_register ; +//public : bool _have_port_special_register ; // always true // -----[ methods ]--------------------------------------------------- @@ -87,6 +133,10 @@ public : virtual Parameters_test msg_error (void) = 0; - // methods to generate configuration file - + // methods to copy depends parameters + // (these parameters can't be static : because can have multi instance of toplevel) + public : virtual void copy (void) = 0; +//public : void copy (Parameters * param); + public : void duplicate (Parameters * param); + // methods to test public : void test (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Parameters_test.h (revision 88) @@ -0,0 +1,46 @@ +#ifndef morpheo_behavioural_Parameters_test_h +#define morpheo_behavioural_Parameters_test_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" + +namespace morpheo { +namespace behavioural { + + template bool test (uint32_t size) + { + return (size <= (8*sizeof(T))); + }; + + class Parameters_test + { + private : std::string _component; + protected : std::string _error; + protected : std::string _warning; + protected : std::string _information; + + public : Parameters_test (std::string component) + { + _component = component; + _error = ""; + _warning = ""; + }; + public : ~Parameters_test (void) {}; + + public : bool have_error (void) { return (_error.length() != 0);}; + public : void error (std::string str) { _error += MSG_ERROR ; _error += " <" + _component + "> " + str;} + public : void warning (std::string str) { _warning += MSG_WARNING ; _warning += " <" + _component + "> " + str;} + public : void information (std::string str) { _information += MSG_INFORMATION; _information += " <" + _component + "> " + str;} + public : std::string print (void) { return _error + _warning + _information;}; + }; + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR.h (revision 88) @@ -0,0 +1,19 @@ +#ifndef morpheo_behavioural_SPR_h +#define morpheo_behavioural_SPR_h + +#include "Behavioural/include/SPR_access_mode.h" + +namespace morpheo { +namespace behavioural { + + class SPR + { + public : virtual ~SPR (void ) {}; + public : virtual void reset (void ) = 0; + public : virtual Tspr_t read (void ) = 0; + public : virtual void write (Tspr_t) = 0; + }; + +} // end namespace behavioural +} // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/SPR_access_mode.h (revision 88) @@ -10,15 +10,22 @@ namespace behavioural { - typedef struct + class spr_address_t { - Tgeneral_data_t _group; - Tgeneral_data_t _register; - } spr_address_t; + public : Tgeneral_data_t _group; + public : Tgeneral_data_t _register; + public : spr_address_t (void) {}; + public : spr_address_t (Tgeneral_data_t grp, + Tgeneral_data_t reg) + { + _group = grp; + _register = reg; + }; + }; class SPR_access_mode { - private : spr_access_mode_t ** _spr_generic; - private : uint32_t * _max_register_by_group; + private : spr_access_mode_t ** _spr_generic ; //[NB_GROUP][NB_REG_GROUP] + private : uint32_t * _max_register_by_group; //[NB_GROUP] public : SPR_access_mode(); @@ -29,4 +36,6 @@ public : bool valid (uint32_t num_group, uint32_t num_reg); public : bool valid (spr_address_t address); + public : bool exist (uint32_t num_group, uint32_t num_reg); + public : bool exist (spr_address_t address); public : bool read (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); public : bool write (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA); @@ -35,4 +44,6 @@ public : uint32_t implement_group (uint32_t num_group); public : void change_mode (uint32_t num_group, uint32_t num_reg, spr_access_mode_t new_mode); + public : void invalid_register(uint32_t num_group, uint32_t num_reg); + }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Selftest.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Selftest.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Selftest.h (revision 88) @@ -0,0 +1,72 @@ +#ifndef morpheo_behavioural_Selftest_h +#define morpheo_behavioural_Selftest_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Allocation.h" +#include "Common/include/FromString.h" +#include "Common/include/Debug.h" + +// ====================================================================== +// =====[ ALLOCATION / DELETE of ARRAY ]================================= +// ====================================================================== + +#define AFFECT0(var,type,argv,x) \ + var = morpheo::fromString(argv[x++]); + +#define AFFECT1(var,type,argv,x,s1) \ + for (uint32_t it1=0; it1(argv[x++]); \ + } + +#define AFFECT2(var,type,argv,x,s1,s2) \ + for (uint32_t it1=0; it1(argv[x++]); \ + } + +#define AFFECT3(var,type,argv,x,s1,s2,s3) \ + for (uint32_t it1=0; it1(argv[x++]); \ + } + +#define AFFECT4(var,type,argv,x,s1,s2,s3,s4) \ + for (uint32_t it1=0; it1(argv[x++]); \ + } + + +#define SELFTEST0(var,type,argv,x) \ + AFFECT0(var,type,argv,x); \ + +#define SELFTEST1(var,type,argv,x,s1) \ + ALLOC1(var,type,s1); \ + AFFECT1(var,type,argv,x,s1); + +#define SELFTEST2(var,type,argv,x,s1,s2) \ + ALLOC2(var,type,s1,s2); \ + AFFECT2(var,type,argv,x,s1,s2); + +#define SELFTEST3(var,type,argv,x,s1,s2,s3) \ + ALLOC3(var,type,s1,s2,s3); \ + AFFECT3(var,type,argv,x,s1,s2,s3); + +#define SELFTEST4(var,type,argv,x,s1,s2,s3,s4) \ + ALLOC4(var,type,s1,s2,s3,s4); \ + AFFECT4(var,type,argv,x,s1,s2,s3,s4); + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Signal.h (revision 88) @@ -38,5 +38,6 @@ UINT64_T } type_info_t; - typedef enum {PORT_VHDL_YES_TESTBENCH_YES, + typedef enum {PORT_SYSTEMC_NO , // also, vhdl_no and testbench_no + PORT_VHDL_YES_TESTBENCH_YES, PORT_VHDL_YES_TESTBENCH_NO , PORT_VHDL_NO_TESTBENCH_YES , @@ -72,10 +73,10 @@ // -----[ methods ]--------------------------------------------------- - public : Signal (std::string name , - direction_t direction , - uint32_t size , - presence_port_t presence_port = PORT_VHDL_YES_TESTBENCH_YES); - public : Signal (const Signal &); - public : ~Signal (); + public : Signal (std::string name , + direction_t direction , + uint32_t size , + presence_port_t presence_port = PORT_VHDL_YES_TESTBENCH_YES); + public : Signal (const Signal &); + public : ~Signal (); public : std::string get_name (void); @@ -93,5 +94,5 @@ public : bool test_map (uint32_t depth, bool top_level, bool is_behavioural); -// public : bool test_equi (uint32_t depth); +//public : bool test_equi (uint32_t depth); public : void link (Signal * signal_dest, @@ -108,5 +109,5 @@ case IN : {return read_in ();} case OUT : {return read_out ();} - default : throw (ErrorMorpheo ("Signal \""+_name+"\" : direction unknow.")); + default : throw (ErrorMorpheo ("Signal \""+_name+"\" : direction unknow.\n")); } } @@ -122,5 +123,5 @@ case UINT32_T : return (static_cast *>(_sc_signal_map)->read()); case UINT64_T : return (static_cast *>(_sc_signal_map)->read()); - default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); + default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.\n")); } } @@ -136,5 +137,5 @@ case UINT32_T : return (static_cast *>(_sc_signal_map)->read()); case UINT64_T : return (static_cast *>(_sc_signal_map)->read()); - default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.")); + default : throw (ErrorMorpheo ("Signal \""+_name+"\" : type unknow.\n")); } } @@ -148,8 +149,8 @@ if (_type_info != UNKNOW) - throw (ErrorMorpheo ("Signal \""+_name+"\" : already allocate.")); + throw (ErrorMorpheo (toString(_("Signal \"%s\" : already allocate.\n"),_name.c_str()))); if (test(_size) == false) - throw (ErrorMorpheo ("Signal \""+_name+"\" : size is too small to the associate type.")); + throw (ErrorMorpheo (toString(_("Signal \"%s\" : size is too small (%d bits) to the associate type (%d bits).\n"),_name.c_str(),_size,8*sizeof(T)))); _is_allocate = true; @@ -157,6 +158,4 @@ _sc_signal_map = sc_signal; - log_printf(TRACE,Behavioural,FUNCTION, "Allocation of %s - %.8x", _name.c_str(), (uint32_t)(_sc_signal_map)); - if (typeid(T) == typeid(bool )) _type_info = BOOL; @@ -175,4 +174,6 @@ else _type_info = UNKNOW; + + log_printf(TRACE,Behavioural,FUNCTION, "Allocation of %s (%s, 0x%.8x)", _name.c_str(),toString(_type_info).c_str(), static_cast(reinterpret_cast(_sc_signal_map))); log_printf(FUNC,Behavioural,FUNCTION,"End"); @@ -204,4 +205,7 @@ }; }; // end namespace behavioural + + + template<> inline std::string toString(const morpheo::behavioural::presence_port_t& x) @@ -221,4 +225,25 @@ } + typedef enum {UNKNOW , + BOOL , + UINT8_T , + UINT16_T , + UINT32_T , + UINT64_T } type_info_t; + + template<> inline std::string toString(const morpheo::behavioural::type_info_t& x) + { + switch (x) + { + case morpheo::behavioural::BOOL : return "bool" ; break; + case morpheo::behavioural::UINT8_T : return "uint8_t" ; break; + case morpheo::behavioural::UINT16_T : return "uint16_t"; break; + case morpheo::behavioural::UINT32_T : return "uint32_t"; break; + case morpheo::behavioural::UINT64_T : return "uint64_t"; break; + case morpheo::behavioural::UNKNOW : + default : return "unknow" ; break; + } + } + }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Simulation.h (revision 88) @@ -0,0 +1,44 @@ +#ifdef SYSTEMC +#ifndef morpheo_behavioural_Simulation_h +#define morpheo_behavioural_Simulation_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" + +#include +#include +#include + +namespace morpheo { +namespace behavioural { + +extern double _simulation_nb_cycle; +// extern double _simulation_nb_instruction; +// extern std::vector * _simulation_nb_instruction_commited; + + // Warning, now no mutek to protect this variable + +// class Simulation +// { +// private : const uint32_t _num_context; + +// public : Simulation (void); +// public : ~Simulation (void); +// public : void end_cycle (double nb_instruction_commited); +// }; + + bool simulation_test_end (void); + void simulation_init (double nb_cycle, + double nb_instruction); + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat.h (revision 88) @@ -44,19 +44,19 @@ class Stat { - const std::string _name_instance; - const std::string _name_component; - const cycle_t _nb_cycle_before_begin; - const cycle_t _period; - const bool _save_periodic; + private: const std::string _name_instance; + private: const std::string _name_component; + private: const cycle_t _nb_cycle_before_begin; + private: const cycle_t _period; + private: const bool _save_periodic; // Tableau des variables - std::map * _list_operand; + private: std::map * _list_operand; // Liste chaîné des expressions - std::list * _list_expr; + private: std::list * _list_expr; - counter_t * _cycle; + private: counter_t * _cycle; - std::list * _list_stat; + private: std::list * _list_stat; - bool _generate_file; + private: bool _generate_file; public : Stat (std::string name_instance, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_binary_tree.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_binary_tree.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Stat_binary_tree.h (revision 88) @@ -14,5 +14,5 @@ namespace behavioural { - typedef enum {VARIABLE, CONSTANT, OPERATOR_UNARY, OPERATOR_BINARY} data_type_t; + typedef enum {NONE, VARIABLE, CONSTANT, OPERATOR_UNARY, OPERATOR_BINARY} data_type_t; typedef union @@ -26,32 +26,44 @@ { // arbre binaire - private : Stat_binary_tree * _root; - private : Stat_binary_tree * _left; - private : Stat_binary_tree * _right; - private : data_type_t _data_type; - private : data_t _data; + private : Stat_binary_tree * _root; + private : Stat_binary_tree * _left; + private : Stat_binary_tree * _right; + private : data_type_t _data_type; + private : data_t _data; /* private : Stat_binary_tree (data_type_t data_type, data_t data); */ - public : Stat_binary_tree (counter_t cst); - public : Stat_binary_tree (counter_t * var); - public : Stat_binary_tree (operator_t op ); - - public : ~Stat_binary_tree (void); + public : Stat_binary_tree (std::string expr, + std::map * operand); + public : Stat_binary_tree (counter_t cst); + public : Stat_binary_tree (counter_t * var); + public : Stat_binary_tree (operator_t op ); - private : void insert_tree (Stat_binary_tree * tree); - public : Stat_binary_tree * insert_tree (counter_t cst); - public : Stat_binary_tree * insert_tree (counter_t * var); - public : Stat_binary_tree * insert_tree (operator_t op ); + public : ~Stat_binary_tree (void); + + private : void insert_tree (Stat_binary_tree * tree); + public : Stat_binary_tree * insert_tree (counter_t cst); + public : Stat_binary_tree * insert_tree (counter_t * var); + public : Stat_binary_tree * insert_tree (operator_t op ); - public : Stat_binary_tree * goto_top_level (void); - public : Stat_binary_tree * goto_next_root (void); + private : void change_type (counter_t cst); + private : void change_type (counter_t * var); + private : void change_type (operator_t op ); + + public : Stat_binary_tree * goto_top_level (void); + public : Stat_binary_tree * goto_next_root (void); - public : bool valid (void); + public : bool valid (void); - public : counter_t eval (void); + public : counter_t eval (void); - private : counter_t val_tree (void); - private : counter_t val_leaf (void); - private : bool is_leaf (void); + private : counter_t val_tree (void); + private : counter_t val_leaf (void); + private : bool is_leaf (void); + + public : void import (std::string expr, + std::map * operand); + + + public : void print (uint32_t depth=0); // public : friend std::ostream& operator<< (std::ostream&, const morpheo::Stat_binary_tree &); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 88) @@ -25,5 +25,7 @@ typedef uint8_t Tcounter_t; // universal counter typedef uint8_t Tptr_t; // universal pointer - + typedef uint32_t Tspr_t; + typedef uint16_t Tspr_address_t; + //typedef uint32_t Tdestination1_t; //typedef uint32_t Tdestination2_t; @@ -69,4 +71,13 @@ typedef enum { + ORBIS32, + ORBIS64, + ORFPX32, + ORFPX64, + ORVDX64 + } ISA; + + typedef enum + { PRIORITY_STATIC, PRIORITY_ROUND_ROBIN @@ -93,5 +104,5 @@ PREDICTOR_NEVER_TAKE , // Branch is never Take PREDICTOR_ALWAYS_TAKE , // Branch is always Take - PREDICTOR_STATIC , // If the adress of destination is previous, then the branch is take + PREDICTOR_STATIC , // If the address of destination is previous, then the branch is take PREDICTOR_LAST_TAKE , // The direction is as the last time (if is the first time : static) PREDICTOR_COUNTER , // Counter table @@ -99,6 +110,30 @@ PREDICTOR_GLOBAL , // Counter bank indexed with history table PREDICTOR_META , // A meta_predictor choose between 2 predictor : the local or the global - PREDICTOR_CUSTOM // Note predefined scheme + PREDICTOR_CUSTOM // Not predefined scheme } Tpredictor_t; + + //--------------------------------------------------[ instruction ]----- + class instruction_t + { + public : + Ttype_t _type ; + Toperation_t _operation ; + ISA _isa_subset; + uint8_t _isa_class ; + + instruction_t (Ttype_t type , + Toperation_t operation , + ISA isa_subset, + uint8_t isa_class ) + { + _type = type ; + _operation = operation ; + _isa_subset = isa_subset; + _isa_class = isa_class ; + } + }; + + instruction_t instruction_information (uint32_t instruction); + uint32_t instruction_size_data (uint32_t instruction); //----------------------------------------------[ spr_mode_access ]----- @@ -122,16 +157,17 @@ switch (x) { - case TYPE_ALU : return "ALU" ; break; - case TYPE_SHIFT : return "SHIFT" ; break; - case TYPE_MOVE : return "MOVE" ; break; - case TYPE_TEST : return "TEST" ; break; - case TYPE_MUL_DIV : return "MUL_DIV"; break; - case TYPE_EXTEND : return "EXTEND" ; break; - case TYPE_FIND : return "FIND" ; break; - case TYPE_SPECIAL : return "SPECIAL"; break; - case TYPE_CUSTOM : return "CUSTOM" ; break; - case TYPE_BRANCH : return "BRANCH" ; break; - case TYPE_MEMORY : return "MEMORY" ; break; - default : return "" ; break; + case TYPE_ALU : return "ALU" ; break; + case TYPE_SHIFT : return "SHIFT" ; break; + case TYPE_MOVE : return "MOVE" ; break; + case TYPE_TEST : return "TEST" ; break; + case TYPE_MUL : return "MUL" ; break; + case TYPE_DIV : return "DIV" ; break; + case TYPE_EXTEND : return "EXTEND" ; break; + case TYPE_FIND : return "FIND" ; break; + case TYPE_SPECIAL : return "SPECIAL" ; break; + case TYPE_CUSTOM : return "CUSTOM" ; break; + case TYPE_BRANCH : return "BRANCH" ; break; + case TYPE_MEMORY : return "MEMORY" ; break; + default : return "Unknow type"; break; } }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Usage.h (revision 88) @@ -16,4 +16,5 @@ # define USE_STATISTICS 0x20 # define USE_INFORMATION 0x40 +# define USE_HEADER 0x80 //#define USE_ 0x80 Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 88) @@ -10,10 +10,16 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION 87 +#define MORPHEO_REVISION @REVISION +#define MORPHEO_CODENAME "Castor" + +#define MORPHEO_DATE_DAY @DATE_DAY +#define MORPHEO_DATE_MONTH @DATE_MONTH +#define MORPHEO_DATE_YEAR @DATE_YEAR #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION) +#define MORPHEO_HEADER morpheo::toString(MORPHEO_VERSION)+" - "+morpheo::toString(MORPHEO_CODENAME) +#define MORPHEO_DATE morpheo::toString(MORPHEO_DATE_YEAR)+"/"+morpheo::toString(MORPHEO_DATE_MONTH)+"/"+morpheo::toString(MORPHEO_DATE_DAY) /* - [ Change Log ] | @@ -22,5 +28,5 @@ | SystemC Only | - +-[ Minor Version 1 ] + +-[ Minor Version 1 ] - Castor | | | | Second Architecture, change the load_store_unit and implement exception Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed (revision 88) @@ -11,9 +11,15 @@ #define MORPHEO_MINOR_VERSION 2 #define MORPHEO_REVISION @REVISION +#define MORPHEO_CODENAME "Castor" + +#define MORPHEO_DATE_DAY @DATE_DAY +#define MORPHEO_DATE_MONTH @DATE_MONTH +#define MORPHEO_DATE_YEAR @DATE_YEAR #define MORPHEO_VERSION morpheo::toString(MORPHEO_MAJOR_VERSION)+"."+morpheo::toString(MORPHEO_MINOR_VERSION)+"."+morpheo::toString(MORPHEO_REVISION) +#define MORPHEO_HEADER morpheo::toString(MORPHEO_VERSION)+" - "+morpheo::toString(MORPHEO_CODENAME) +#define MORPHEO_DATE morpheo::toString(MORPHEO_DATE_YEAR)+"/"+morpheo::toString(MORPHEO_DATE_MONTH)+"/"+morpheo::toString(MORPHEO_DATE_DAY) /* - [ Change Log ] | @@ -22,5 +28,5 @@ | SystemC Only | - +-[ Minor Version 1 ] + +-[ Minor Version 1 ] - Castor | | | | Second Architecture, change the load_store_unit and implement exception Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 88) @@ -14,5 +14,5 @@ #include #include -#include "Behavioural/include/Environment.h" +#include "Common/include/Environment.h" #include "Behavioural/include/Direction.h" #include "Common/include/ToString.h" @@ -53,91 +53,93 @@ private : void generate_file_package (void); private : void generate_file_model (void); - - private : std::string get_package (uint32_t depth , - std::string filename , - std::string package_name , - std::string entity_name ); - private : std::string get_model (uint32_t depth , - std::string filename , - std::string entity_name , - std::string architecture_name ); - private : std::string get_header (uint32_t depth , - std::string filename ); - private : std::string get_entity (uint32_t depth , - std::string name ); - private : std::string get_architecture (uint32_t depth , - std::string name , - std::string entity_name ); - private : std::string get_component (uint32_t depth , - std::string name ); - - private : std::string get_port (uint32_t depth ); - public : void set_port (std::string name , + + private : std::string get_package (uint32_t depth , + std::string filename , + std::string package_name , + std::string entity_name ); + private : std::string get_model (uint32_t depth , + std::string filename , + std::string entity_name , + std::string architecture_name ); + private : std::string get_header (uint32_t depth , + std::string filename ); + private : std::string get_entity (uint32_t depth , + std::string name ); + private : std::string get_architecture (uint32_t depth , + std::string name , + std::string entity_name ); + private : std::string get_component (uint32_t depth , + std::string name ); + + private : std::string get_port (uint32_t depth ); + public : void set_port (std::string name , direction_t direction , - std::string type ); - public : void set_port (std::string name , + std::string type ); + public : void set_port (std::string name , direction_t direction , uint32_t size ); - private : std::string get_signal (uint32_t depth ); - public : void set_signal (std::string name , - std::string type ); - public : void set_signal (std::string name , + private : std::string get_signal (uint32_t depth ); + public : void set_signal (std::string name , + std::string type ); + public : void set_signal (std::string name , uint32_t signal ); - public : void set_signal (std::string name , - std::string type , - std::string init ); - public : void set_signal (std::string name , + public : void set_signal (std::string name , + std::string type , + std::string init ); + public : void set_signal (std::string name , uint32_t size , - std::string init ); - public : void set_signal (std::string name , + std::string init ); + public : void set_signal (std::string name , uint32_t size , uint32_t init ); - public : void set_constant (std::string name , - std::string type , - std::string init ); - public : void set_constant (std::string name , + public : void set_constant (std::string name , + std::string type , + std::string init ); + public : void set_constant (std::string name , uint32_t size , - std::string init ); - public : void set_constant (std::string name , + std::string init ); + public : void set_constant (std::string name , uint32_t size , uint32_t init ); - private : std::string get_type (uint32_t depth ); - public : void set_type (std::string name , - std::string type ); - private : std::string get_alias (uint32_t depth ); - public : void set_alias (std::string name1 , - std::string type1 , - std::string name2 , - std::string range2 ); - public : void set_alias (std::string name1 , + private : std::string get_type (uint32_t depth ); + public : void set_type (std::string name , + std::string type ); + private : std::string get_alias (uint32_t depth ); + public : void set_alias (std::string name1 , + std::string type1 , + std::string name2 , + std::string range2 ); + public : void set_alias (std::string name1 , uint32_t size1 , - std::string name2 , - std::string range2 ); + std::string name2 , + std::string range2 ); + + public : std::string get_list (std::list liste , + uint32_t depth , + std::string separator , + bool last_separator ); + public : void set_list (std::list & liste , + std::string text ); - public : std::string get_list (std::list liste , - uint32_t depth , - std::string separator , - bool last_separator ); - public : void set_list (std::list & liste , - std::string text ); + private : std::string get_body (uint32_t depth ); + public : void set_body (std::string text ); + + public : void set_body (Vhdl * vhdl ); + + public : void set_body_component (std::string name_instance , + std::string name_component , + std::list list_port_map); + public : void set_body_component_port_map (std::list & list_port_map, + std::string name_port , + uint32_t size_port , + std::string name_signal , + uint32_t size_signal ); - private : std::string get_body (uint32_t depth ); - public : void set_body (std::string text ); + private : std::string get_library_ieee (uint32_t depth ); + private : std::string get_library_work (uint32_t depth ); + public : void set_library_work (std::string package_name ); - public : void set_body_component (std::string name_instance , - std::string name_component , - std::list list_port_map ); - public : void set_body_component_port_map (std::list & list_port_map , - std::string name_port , - uint32_t size_port , - std::string name_signal , - uint32_t size_signal ); - - private : std::string get_library_ieee (uint32_t depth ); - private : std::string get_library_work (uint32_t depth ); - public : void set_library_work (std::string package_name ); - - private : std::string direction_toString (direction_t direction); + private : std::string direction_toString (direction_t direction ); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XML.h (revision 88) @@ -40,17 +40,17 @@ public : bool singleton_end (void); public : bool attribut (std::string name, std::string value); - public : bool insert_XML (XML xml ); + public : bool insert_XML (XML xml, uint32_t offset_depth=0); public : void filename_extension (std::string extension); - public : void generate_file (void); - public : void generate_file (std::string encoding); - public : std::string get_body (void); - public : std::string get_body (uint32_t depth); + public : void generate_file (std::string dirname, std::string encoding); + public : void generate_file (std::string dirname="."); + public : std::string get_body (void); + public : std::string get_body (uint32_t depth); public : bool comment (std::string text); public : bool text (std::string text); - private : std::string indent (uint32_t depth ); - private : std::string indent (void); + private : std::string indent (uint32_t depth ); + private : std::string indent (void); private : uint32_t depth (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightFunctors.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightFunctors.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightFunctors.h (revision 88) @@ -0,0 +1,46 @@ +#ifndef _XMLLIGHT_FUNCTORS +#define _XMLLIGHT_FUNCTORS + +#include "Behavioural/include/IXMLLight.h" + +namespace morpheo { + namespace XMLUtils { + + //******************************************CLASS DECLARATION**************************************// + + // enum to enumerate some XML tags playing a part within parsing process. + enum EXML_DELIMITOR { + BEGIN_TAG = '<', + SECOND_TAG = '/', + END_TAG = '>' + }; + + // functor class used inside XML parsing algorithm + class XMLLightComparator { + public: + bool operator () ( char firstChar, char secondChar ) ; + + }; + + // Deleter is a functor to handle deletion algorithm of XMLLightVector + + template class XMLLightDeleter { + public: + inline T * operator() ( T *); + }; + + //*********************************** INLINE DEFINITION*********************************************// + + //definition of Deleter functor + template T* XMLLightDeleter::operator() ( T * xmlLightPointer ) + { + xmlLightPointer -> detach(); + //delete xmlLightPointer ; + return NULL; + } + + } // end of namespace XMLUtils. +} // end of morpheo's namespace. + +#endif // _XMLLIGHT_FUNCTORS + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightVector.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightVector.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/XMLLightVector.h (revision 88) @@ -0,0 +1,95 @@ +#ifndef _XMLLIGHT_VECTOR_ +#define _XMLLIGHT_VECTOR_ + +#include "Behavioural/include/XMLLightFunctors.h" +#include +#include +#include + +using std::basic_ostream; +using std::basic_ios; +using std::endl; + +namespace morpheo { + namespace XMLUtils { + + //********************************************Class Declaration***************************************// + + // an helper class to handle XMLLight * vector + template < typename XMLLightImpl> + class XMLLightVector : public std::vector { + public : + inline explicit XMLLightVector(void); + inline ~XMLLightVector(void); + + XMLLightVector(const XMLLightVector & xmlLightVectorCopied); + XMLLightVector & operator= ( const XMLLightVector & copy ); + + // must be defined inside template class declaration + template < typename charT, typename traits> friend + basic_ostream & operator<< + ( basic_ostream & os , const XMLLightVector & vect) { + if ( vect.size() == 0 ) { + os << "There's no Child Nodes " << endl ; + } else { + for ( unsigned int i = 0 ; i < vect.size() ; ++i ) { + os <<"Nodes "<< i << ": \n\t" << vect[i] ->getInternalString() << endl; + } + } + return os; + } + + }; + + //******************************************Inline implementation************************************// + + template< typename T > class XMLLightDeleter; + + template < typename XMLLightImpl > + XMLLightVector::XMLLightVector() { + } + + template < typename XMLLightImpl > + XMLLightVector< XMLLightImpl>::~XMLLightVector(void) { + transform ( this -> begin(), this -> end(), this -> begin(), XMLLightDeleter() ); + } + + //**************************************** template implementation*******************************// + + template < typename XMLLightImpl > + XMLLightVector::XMLLightVector(const XMLLightVector & copy ) { + for ( unsigned int i = 0 ; i < copy.size() ; ++i ) { + this -> push_back(copy[i]); + copy[i] -> attach(); + } + } + + template < typename XMLLightImpl > + XMLLightVector & XMLLightVector::operator= ( const XMLLightVector & vector ) { + if ( &vector != this ) { + unsigned int this_size = this -> size(); + unsigned int copy_max_size = vector.size(); + unsigned int max_size = copy_max_size < this_size ? this_size : copy_max_size; + for ( unsigned int i = 0 ; i < max_size ; ++i ) { + if ( this_size ) { + (*this)[i] -> detach(); + } + if ( i < copy_max_size ) { + if ( this_size == 0 ) { + this -> push_back(vector[i]); + } else { + (*this)[i] = vector[i]; + } + (*this)[i] -> attach(); + } else { + (*this)[i] = NULL; + } + } + } + return *this; + } + + }// end of XMLUtils namespace +} // end of morpheo namespace + +#endif // _XMLLIGHT_VECTOR_ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_generate_file.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_generate_file.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_generate_file.cpp (revision 88) @@ -8,8 +8,11 @@ #include "Behavioural/include/Component.h" +#include "Common/include/Environment.h" namespace morpheo { namespace behavioural { +#undef FUNCTION +#define FUNCTION "Component::generate_file" void Component::generate_file (void) { @@ -18,14 +21,16 @@ try { + directory(); + XML xml = toXML(); - xml.filename_extension ("pos"); + xml.filename_extension (".pos"); - xml.generate_file("ISO-8859-1"); + xml.generate_file(MORPHEO_POSITION,"ISO-8859-1"); } catch (ErrorMorpheo e) { - throw (ErrorMorpheo ("Component \""+_entity->get_name()+"\" have a bad mapping : "+e.what())); + throw ERRORMORPHEO(FUNCTION,toString(_("Component \"%s\" have a bad mapping : %s\n")),_entity->get_name().c_str(),e.what().c_str()); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_port_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_port_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_port_map.cpp (revision 88) @@ -20,5 +20,5 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); -// log_printf(NONE,Behavioural,FUNCTION,"Map %s.%s with %s.%s", +// log_printf(INFO,Behavioural,FUNCTION,"Map %s.%s with %s.%s", // component_src.c_str(), // port_src.c_str(), Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp (revision 88) @@ -15,5 +15,5 @@ bool Component::test_map (bool recursive) { - log_printf(NONE,Behavioural,FUNCTION, "Test port map and interface."); + log_printf(INFO,Behavioural,FUNCTION, "Test port map and interface."); return test_map (0, recursive); } @@ -23,5 +23,5 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string tab = std::string(depth,'\t'); + std::string tab = std::string(depth,' '); std::string name = _entity->get_name(); bool test_ok = true; @@ -30,17 +30,17 @@ if (is_behavioural) { - log_printf(NONE,Behavioural,FUNCTION, "%s* Component \"%s\" is a behavioural description",tab.c_str(),name.c_str()); + log_printf(INFO,Interface,FUNCTION, "%s* Component \"%s\" is a behavioural description",tab.c_str(),name.c_str()); } else { - log_printf(NONE,Behavioural,FUNCTION, "%s* Component \"%s\" is a structural description",tab.c_str(),name.c_str()); + log_printf(INFO,Interface,FUNCTION, "%s* Component \"%s\" is a structural description",tab.c_str(),name.c_str()); } - // log_printf(NONE,Behavioural,FUNCTION, "%s* Test port I/O",tab.c_str()); + // log_printf(INFO,Behavioural,FUNCTION, "%s* Test port I/O",tab.c_str()); test_ok &= _entity->test_map(depth+1,true,is_behavioural); - // log_printf(NONE,Behavioural,FUNCTION, "%s* Test all internal component",tab.c_str()); + // log_printf(INFO,Behavioural,FUNCTION, "%s* Test all internal component",tab.c_str()); for (std::list::iterator i= _list_component->begin(); @@ -72,5 +72,5 @@ // bool Component::test_equi (bool recursive) // { -// log_printf(NONE,Behavioural,FUNCTION, "Test port equi and interface."); +// log_printf(INFO,Behavioural,FUNCTION, "Test port equi and interface."); // return test_equi (0, recursive); // } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters.cpp (revision 87) +++ (revision ) @@ -1,50 +1,0 @@ -#ifdef CONFIGURATION -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Behavioural/include/Configuration_Parameters.h" - -namespace morpheo { -namespace behavioural { - -#undef FUNCTION -#define FUNCTION "Configuration_Parameters::Configuration_Parameters" - Configuration_Parameters::Configuration_Parameters (std::string name , - uint32_t value , - uint32_t min , - uint32_t max , - std::string step , - uint32_t value_default, - uint32_t level , - std::string comment): - _name (name ), - _value (value ), - _min (min ), - _max (max ), - _step (step ), - _default (value_default), - _level (level ), - _comment (comment ) - { - log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - if ((valuemax)) - throw (ErrorMorpheo ("Parameters \""+name+"\" is out of bound : "+toString(value)+" not include in ["+toString(min)+":"+toString(max)+"]")); - log_printf(FUNC,Behavioural,FUNCTION,"End"); - }; - - -#undef FUNCTION -#define FUNCTION "Configuration_Parameters::~Configuration_Parameters" - Configuration_Parameters::~Configuration_Parameters () - { - log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - log_printf(FUNC,Behavioural,FUNCTION,"End"); - }; - -}; // end namespace behavioural -}; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Configuration_Parameters_print.cpp (revision 87) +++ (revision ) @@ -1,51 +1,0 @@ -#ifdef CONFIGURATION -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "Behavioural/include/Configuration_Parameters.h" - - -namespace morpheo { -namespace behavioural { - -#undef FUNCTION -#define FUNCTION "Configuration_Parameters::print" - std::string Configuration_Parameters::print (uint32_t depth) - { - log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - XML * xml = new XML (_name); - - xml->balise_open_begin("generic"); - xml-> attribut("name" , _name ); - xml-> attribut("value" ,toString(_value)); - xml-> attribut("min" ,toString(_min )); - xml-> attribut("max" ,toString(_max )); - xml-> attribut("step" , _step ); - xml-> attribut("default",toString(_value)); - xml-> attribut("level" ,toString(_level)); - xml->balise_open_end (); - xml-> text (_comment); - xml->balise_close(); - - log_printf(FUNC,Behavioural,FUNCTION,"End"); - return xml->get_body(depth); - }; - -#undef FUNCTION -#define FUNCTION "Configuration_Parameters::operator<<" - std::ostream& operator<< (std::ostream& output_stream, - morpheo::behavioural::Configuration_Parameters & x) - { - log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - output_stream << x.print(0); - log_printf(FUNC,Behavioural,FUNCTION,"End"); - return output_stream; - }; - -}; // end namespace behavioural -}; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_test_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Entity_test_map.cpp (revision 88) @@ -18,6 +18,6 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string tab = std::string(depth,'\t'); - log_printf(NONE,Behavioural,FUNCTION, "%s* Entity \"%s\"",tab.c_str(),_name.c_str()); + std::string tab = std::string(depth,' '); + log_printf(INFO,Interface,FUNCTION,"%s* Entity \"%s\"",tab.c_str(),_name.c_str()); bool _return = _interfaces->test_map(depth+1,top_level, is_behavioural); @@ -42,5 +42,5 @@ // std::string tab = std::string(depth,'\t'); -// log_printf(NONE,Behavioural,FUNCTION, "%s* Entity \"%s\"",tab.c_str(),_name.c_str()); +// log_printf(INFO,Behavioural,FUNCTION, "%s* Entity \"%s\"",tab.c_str(),_name.c_str()); // bool _return = _interfaces->test_equi(depth+1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_assert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_assert.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_assert.cpp (revision 88) @@ -0,0 +1,51 @@ +#ifdef VHDL_TESTBENCH +#ifdef VHDL_TESTBENCH_ASSERT +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Interface_fifo.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Interface_fifo::testbench_assert" + void Interface_fifo::testbench_assert (Vhdl * & vhdl, + std::string counter_name) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + + if (not _test_exhaustive) + if (_list_cycle->empty()== false) + { + std::string test_name = Interface::testbench_test_name(vhdl); + + vhdl->set_body(""); + vhdl->set_body("-- Interface \""+_name+"\""); + vhdl->set_body(""); + + uint32_t j = 0; + std::list::iterator i = _list_cycle->begin(); + + while (i != _list_cycle->end()) + { + vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '1')) report \"***** <"+_name+"> Test number "+toString(j)+" is OK *****\" severity NOTE;"); + vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '0')) report \"@@@@@ <"+_name+"> Test number "+toString(j)+" is KO !!! @@@@@\" severity NOTE;"); + j++; + ++i; + } + + vhdl->set_body(""); + } + + log_printf(FUNC,Behavioural,FUNCTION,"End"); + }; + +}; // end namespace behavioural +}; // end namespace morpheo +#endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_fifo_testbench_test.cpp (revision 88) @@ -13,6 +13,6 @@ std::string Interface_fifo::testbench_test (Vhdl * & vhdl, - std::string counter_name, - std::string reset_name ) + std::string counter_name, + std::string reset_name ) { log_printf(FUNC,Behavioural,"testbench_test","Begin"); @@ -27,5 +27,5 @@ vhdl->set_body(""); - test_name = testbench_test_name (vhdl); + test_name = testbench_test_name (vhdl); std::string test_name_tmp = test_name+"_tmp"; std::string test_name_ok = testbench_test_ok (vhdl); @@ -54,25 +54,25 @@ vhdl->set_body(test_name + " <= '1' when ("+reset_name+" = '0') else "+test_name_tmp+";"); -#ifdef VHDL_TESTBENCH_ASSERT - if (_list_cycle->empty()== false) - { - vhdl->set_body(""); - vhdl->set_body("-- Assert ..."); - vhdl->set_body(""); +// #ifdef VHDL_TESTBENCH_ASSERT +// if (_list_cycle->empty()== false) +// { +// vhdl->set_body(""); +// vhdl->set_body("-- Assert ..."); +// vhdl->set_body(""); - uint32_t j = 0; - std::list::iterator i = _list_cycle->begin(); +// uint32_t j = 0; +// std::list::iterator i = _list_cycle->begin(); - while (i != _list_cycle->end()) - { - vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '1')) report \"***** <"+_name+"> Test number "+toString(j)+" is OK *****\" severity NOTE;"); - vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '0')) report \"@@@@@ <"+_name+"> Test number "+toString(j)+" is KO !!! @@@@@\" severity NOTE;"); - j++; - ++i; - } +// while (i != _list_cycle->end()) +// { +// vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '1')) report \"***** <"+_name+"> Test number "+toString(j)+" is OK *****\" severity NOTE;"); +// vhdl->set_body("assert not (("+counter_name+" = "+toString(*i)+" and "+test_name+" = '0')) report \"@@@@@ <"+_name+"> Test number "+toString(j)+" is KO !!! @@@@@\" severity NOTE;"); +// j++; +// ++i; +// } - vhdl->set_body(""); - } -#endif +// vhdl->set_body(""); +// } +// #endif } @@ -80,5 +80,4 @@ return test_name; - }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_set_signal.cpp (revision 88) @@ -11,5 +11,5 @@ namespace behavioural { - Signal * Interface::set_signal (std::string name , + Signal * Interface::set_signal (std::string name , direction_t direction, uint32_t size , @@ -19,5 +19,5 @@ std::string signame = signal_name(_name, name, direction); - + Signal * sig = new Signal (signame, direction, size, presence_port); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_test_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_test_map.cpp (revision 88) @@ -18,8 +18,8 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string tab = std::string(depth,'\t'); + std::string tab = std::string(depth,' '); bool _return = true; - log_printf(NONE,Behavioural,FUNCTION, "%s* Interface \"%s\"",tab.c_str(),_name.c_str()); + log_printf(INFO,Interface,FUNCTION, "%s* Interface \"%s\"",tab.c_str(),_name.c_str()); for (std::list::iterator i = _list_signal->begin(); @@ -42,5 +42,5 @@ // bool _return = true; -// log_printf(NONE,Behavioural,FUNCTION, "%s* Interface \"%s\"",tab.c_str(),_name.c_str()); +// log_printf(INFO,Behavioural,FUNCTION, "%s* Interface \"%s\"",tab.c_str(),_name.c_str()); // for (std::list::iterator i = _list_signal->begin(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_test_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_test_map.cpp (revision 88) @@ -18,9 +18,9 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string tab = std::string(depth,'\t'); + std::string tab = std::string(depth,' '); bool _return = true; - log_printf(NONE,Behavioural,FUNCTION, "%s* Interfaces \"%s\"",tab.c_str(),_name.c_str()); + log_printf(INFO,Interface,FUNCTION, "%s* Interfaces \"%s\"",tab.c_str(),_name.c_str()); for (std::list::iterator i = _list_interface->begin(); @@ -44,5 +44,5 @@ // bool _return = true; -// log_printf(NONE,Behavioural,FUNCTION, "%s* Interfaces \"%s\"",tab.c_str(),_name.c_str()); +// log_printf(INFO,Behavioural,FUNCTION, "%s* Interfaces \"%s\"",tab.c_str(),_name.c_str()); // for (std::list::iterator i = _list_interface->begin(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp (revision 88) @@ -17,11 +17,11 @@ log_printf(FUNC,Behavioural,"generate_file","Begin"); - Vhdl * vhdl = new Vhdl(_name+"_Testbench"); - std::string counter = "counter"; - Signal * clock = this->get_clock(); - Signal * reset = this->get_reset(); - std::string clock_name = clock->get_name(); - std::string reset_name = reset->get_name(); - uint32_t cycle = this->get_cycle(); + Vhdl * vhdl = new Vhdl(_name+"_Testbench"); + std::string counter = "counter"; + Signal * clock = this->get_clock(); + Signal * reset = this->get_reset(); + std::string clock_name = clock->get_name(); + std::string reset_name = reset->get_name(); + uint32_t cycle = this->get_cycle(); vhdl->set_signal (clock_name, 1, 0); @@ -87,14 +87,25 @@ vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;"); vhdl->set_body(""); - vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); - vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;"); - #ifdef VHDL_TESTBENCH_ASSERT - vhdl->set_body("\t\t\t-- Assert ..."); for (uint32_t cpt=0; cpt<=cycle; cpt++) vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;"); + + for (std::list::iterator it=_list_interface->begin(); + it!=_list_interface->end(); + ++it) + { + Vhdl * vhdl_assert = new Vhdl(""); + + (*it)->testbench_assert (vhdl_assert,counter); + + vhdl->set_body(vhdl_assert); + + delete vhdl_assert; + } #endif vhdl->set_body(""); + vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;"); + vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;"); vhdl->set_body("\t\tend if;"); vhdl->set_body("\tend if;"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_copy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_copy.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_copy.cpp (revision 88) @@ -0,0 +1,76 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Parameters.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "Parameters::duplicate" + void Parameters::duplicate (Parameters * param) + { + param->_simulation_nb_cyle = _simulation_nb_cyle ; + param->_simulation_nb_instruction = _simulation_nb_instruction ; + + param->_size_context_id = _size_context_id ; + param->_have_port_context_id = _have_port_context_id ; + + param->_size_front_end_id = _size_front_end_id ; + param->_have_port_front_end_id = _have_port_front_end_id ; + + param->_size_ooo_engine_id = _size_ooo_engine_id ; + param->_have_port_ooo_engine_id = _have_port_ooo_engine_id ; + + param->_size_instruction_address = _size_instruction_address ; +// param->_have_port_instruction_address = _have_port_instruction_address ; // always true + + param->_size_data_address = _size_data_address ; +// param->_have_port_data_address = _have_port_data_address ; // always true + + param->_size_nb_inst_decod = _size_nb_inst_decod ; +// param->_have_port_nb_inst_decod = _have_port_nb_inst_decod ; // always true + + param->_size_nb_inst_commit = _size_nb_inst_commit ; +// param->_have_port_nb_inst_commit = _have_port_nb_inst_commit ; // always true + + param->_size_depth = _size_depth ; + param->_have_port_depth = _have_port_depth ; + + param->_size_ifetch_queue_ptr = _size_ifetch_queue_ptr ; + param->_have_port_ifetch_queue_ptr = _have_port_ifetch_queue_ptr ; + + param->_size_inst_ifetch_ptr = _size_inst_ifetch_ptr ; // nb_inst_fetch + param->_have_port_inst_ifetch_ptr = _have_port_inst_ifetch_ptr ; + +// param->_size_branch_update_prediction_id = _size_branch_update_prediction_id ; // = size_depth +// param->_have_port_branch_update_prediction_id = _have_port_branch_update_prediction_id ; // = size_depth + + param->_size_rob_ptr = _size_rob_ptr ; + param->_have_port_rob_ptr = _have_port_rob_ptr ; + + param->_size_load_queue_ptr = _size_load_queue_ptr ; + param->_have_port_load_queue_ptr = _have_port_load_queue_ptr ; + + param->_size_store_queue_ptr = _size_store_queue_ptr ; +// param->_have_port_store_queue_ptr = _have_port_store_queue_ptr ; // always true (min = 1) + + param->_size_general_data = _size_general_data ; +// param->_have_port_general_data = _have_port_general_data ; // always true + + param->_size_special_data = _size_special_data ; +// param->_have_port_special_data = _have_port_special_data ; // always true + + param->_size_general_register = _size_general_register ; +// param->_have_port_general_register = _have_port_general_register ; // always true + + param->_size_special_register = _size_special_register ; +// param->_have_port_special_register = _have_port_special_register ; // always true + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Parameters_test.cpp (revision 88) @@ -23,5 +23,5 @@ if (x.have_error()) - throw (ErrorMorpheo ("Error(s) in parameters")); + throw ERRORMORPHEO (FUNCTION,_("Error(s) in parameters\n")); log_printf(FUNC,Behavioural,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp (revision 88) @@ -0,0 +1,24 @@ +#include "Behavioural/include/SPR_access_mode.h" + +namespace morpheo { +namespace behavioural { + + bool SPR_access_mode::exist (spr_address_t address) + { + return exist(address._group, address._register); + } + + bool SPR_access_mode::exist (uint32_t num_group, uint32_t num_reg) + { + if (not valid(num_group, num_reg)) + return false; + + spr_access_mode_t mode = _spr_generic [num_group][num_reg]; + + return ((mode._supervisor_access_mode != SPR_ACCESS_MODE_NONE) or + (mode._user_access_mode != SPR_ACCESS_MODE_NONE)); + } + +}; // end namespace behavioural +}; // end namespace morpheo + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp (revision 88) @@ -28,4 +28,6 @@ for (uint32_t i=16; i<=18; i++) _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; + _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY; + _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 19]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._user_access_mode = SPR_ACCESS_MODE_READ_ONLY_COND; _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; @@ -77,5 +79,5 @@ _spr_generic [GROUP_DCACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - for (uint32_t i=0; i<=5; i++) + for (uint32_t i=1; i<=5; i++) { _spr_generic [GROUP_DCACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; @@ -91,5 +93,5 @@ _spr_generic [GROUP_ICACHE ][ 0]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - for (uint32_t i=0; i<=3; i++) + for (uint32_t i=1; i<=3; i++) { _spr_generic [GROUP_ICACHE ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_WRITE_ONLY; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_invalid_register.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_invalid_register.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_invalid_register.cpp (revision 88) @@ -0,0 +1,14 @@ +#include "Behavioural/include/SPR_access_mode.h" + +namespace morpheo { +namespace behavioural { + + void SPR_access_mode::invalid_register (uint32_t num_group, uint32_t num_reg) + { + if (valid(num_group, num_reg)) + change_mode (num_group, num_reg, spr_access_mode_t(SPR_ACCESS_MODE_NONE,SPR_ACCESS_MODE_NONE)); + } + +}; // end namespace behavioural +}; // end namespace morpheo + Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_read_write.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_read_write.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_read_write.cpp (revision 88) @@ -1,3 +1,5 @@ #include "Behavioural/include/SPR_access_mode.h" + +#include "Common/include/Debug.h" namespace morpheo { @@ -14,8 +16,15 @@ bool SPR_access_mode::read (spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA) { - if (not valid(address)) +// log_printf(TRACE,true,"SPR_access_mode::read","address [%d][%d]",address._group,address._register); +// log_printf(TRACE,true,"SPR_access_mode::read","sm : %d",SM ); +// log_printf(TRACE,true,"SPR_access_mode::read","sumra : %d",SUMRA); + + if (not exist(address)) return false; spr_access_mode_t mode = _spr_generic [address._group][address._register]; + +// log_printf(TRACE,true,"SPR_access_mode::read","kernel : %d",(int)mode._supervisor_access_mode); +// log_printf(TRACE,true,"SPR_access_mode::read","user : %d",(int)mode._supervisor_access_mode); return (((SM == 1) and ( (mode._supervisor_access_mode == SPR_ACCESS_MODE_READ_ONLY ) or @@ -28,5 +37,5 @@ bool SPR_access_mode::write(spr_address_t address, Tcontrol_t SM, Tcontrol_t SUMRA) { - if (not valid(address)) + if (not exist(address)) return false; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_link.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_link.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_link.cpp (revision 88) @@ -51,5 +51,5 @@ // if (destination_have_multi_producer) // // throw (ERRORMORPHEO (FUNCTION,"Signal \""+_name+"\" can't been linked with signal \""+signal_dest->get_name()+"\" : destination have multi producer.")); -// log_printf(NONE,Behavioural,FUNCTION,"Signal \"%s\" can't been linked with signal \"%s\" : destination have multi producer.",_name.c_str(),signal_dest->get_name().c_str()); +// log_printf(INFO,Behavioural,FUNCTION,"Signal \"%s\" can't been linked with signal \"%s\" : destination have multi producer.",_name.c_str(),signal_dest->get_name().c_str()); // update info source Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_test_map.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_test_map.cpp (revision 88) @@ -19,13 +19,13 @@ std::string str = ""; - std::string tab = std::string(depth,'\t'); + std::string tab = std::string(depth,' '); bool _return = true; -// log_printf(NONE,Behavioural,FUNCTION, "%s* Signal \"%s\"",tab.c_str(),_name.c_str()); -// log_printf(NONE,Behavioural,FUNCTION, "%s%d - %d - %d",tab.c_str(), +// log_printf(INFO,Behavioural,FUNCTION, "%s* Signal \"%s\"",tab.c_str(),_name.c_str()); +// log_printf(INFO,Behavioural,FUNCTION, "%s%d - %d - %d",tab.c_str(), // _is_map_as_toplevel_dest, // _is_map_as_component_src, // _is_map_as_component_dest); -// log_printf(NONE,Behavioural,FUNCTION, "%stop_level %d, is_behavioural %d",tab.c_str(), +// log_printf(INFO,Behavioural,FUNCTION, "%stop_level %d, is_behavioural %d",tab.c_str(), // top_level, // is_behavioural); @@ -143,13 +143,13 @@ if (_return == false) { - log_printf(NONE,Behavioural,FUNCTION, "%s* %s",tab.c_str(),str.c_str()); - #ifndef DEBUG std::cerr << str << std::endl; +#else + log_printf(INFO,Interface,FUNCTION, "%s* %s",tab.c_str(),str.c_str()); #endif } else { -// log_printf(NONE,Behavioural,FUNCTION, "%s* Signal \"%s\" is OK.",tab.c_str(),_name.c_str()); +// log_printf(INFO,Interface,FUNCTION, "%s* Signal \"%s\" is OK.",tab.c_str(),_name.c_str()); } @@ -173,5 +173,5 @@ // if (_return == false) // { -// log_printf(NONE,Behavioural,FUNCTION, "%s* %s",tab.c_str(),str.c_str()); +// log_printf(INFO,Behavioural,FUNCTION, "%s* %s",tab.c_str(),str.c_str()); // #ifndef DEBUG @@ -181,5 +181,5 @@ // else // { -// // log_printf(NONE,Behavioural,FUNCTION, "%s* Signal \"%s\" is OK.",tab.c_str(),_name.c_str()); +// // log_printf(INFO,Behavioural,FUNCTION, "%s* Signal \"%s\" is OK.",tab.c_str(),_name.c_str()); // } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation.cpp (revision 88) @@ -0,0 +1,69 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Simulation.h" +#include "Common/include/ErrorMorpheo.h" + +namespace morpheo { +namespace behavioural { + + static bool simulation_initialized; +// static uint32_t _simulation_num_context_next; + double _simulation_nb_cycle; +// double _simulation_nb_instruction; +// std::vector * _simulation_nb_instruction_commited; + +// Simulation::Simulation (void): +// _num_context (_simulation_num_context_next) +// { +// // Test if is first context create +// if (_simulation_num_context_next == 0) +// _simulation_nb_instruction_commited = new std::vector; + +// _simulation_num_context_next ++; +// } + +// Simulation::~Simulation (void) +// { +// _simulation_num_context_next --; + +// // Test if is last context destroy +// if (_simulation_num_context_next == 0) +// delete _simulation_nb_instruction_commited; +// } + + void simulation_init (double nb_cycle, + double nb_instruction) + { + if (not simulation_initialized) + { +// _simulation_num_context_next = 0; + _simulation_nb_cycle = nb_cycle ; +// _simulation_nb_instruction = nb_instruction; + + if (nb_instruction != 0) + throw ERRORMORPHEO("simulation_init",_("Stop Condition on number instruction is not yet implemented")); + + simulation_initialized = true; + } + else + { + msg_printf(WARNING,_("Multi instance of Morpheo : stop condition, take the highest.")); + + if (_simulation_nb_cycle < nb_cycle) + _simulation_nb_cycle = nb_cycle; + +// if (_simulation_nb_instruction < nb_instruction) +// _simulation_nb_instruction = nb_instruction; + } + } + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_end_cycle.cpp (revision 88) @@ -0,0 +1,23 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Simulation.h" + +namespace morpheo { +namespace behavioural { + +// void Simulation::end_cycle (double nb_instruction_commited) +// { +// // must test if _simulation_nb_instruction_commited is allocate +// (*_simulation_nb_instruction_commited) [_num_context] += nb_instruction_commited; +// } + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Simulation_test_end.cpp (revision 88) @@ -0,0 +1,49 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Simulation.h" + +namespace morpheo { +namespace behavioural { + + bool simulation_test_end (void) + { + msg("##########[ cycle %d ]\n",static_cast(sc_simulation_time())); + + // Test if a stop condition is activate + if ((_simulation_nb_cycle == 0)// and +// (_simulation_nb_instruction == 0) + ) + return false; + + bool end_cycle = true; +// bool end_inst = true; + + if (_simulation_nb_cycle != 0) + end_cycle = (_simulation_nb_cycle <= sc_simulation_time()); + +// if (_simulation_nb_instruction != 0) +// { +// std::vector::iterator it=_simulation_nb_instruction_commited->begin(); + +// // Scan all context and test if all can finish +// while (end_inst and it!=_simulation_nb_instruction_commited->end()) +// { +// end_inst &= (*it <= _simulation_nb_instruction); +// it ++; +// } +// } + + return end_cycle // and end_inst + ; + } + +}; // end namespace behavioural +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree.cpp (revision 88) @@ -21,41 +21,41 @@ Stat_binary_tree:: Stat_binary_tree (counter_t cst) { - _root = NULL; - _left = NULL; - _right = NULL; + _root = NULL; + _left = NULL; + _right = NULL; + _data_type = NONE; - data_t data; - data.cst = cst; - _data_type = CONSTANT; - _data = data; - -// Stat_binary_tree(CONSTANT, data); + change_type (cst); } Stat_binary_tree:: Stat_binary_tree (counter_t * var) { - _root = NULL; - _left = NULL; - _right = NULL; + _root = NULL; + _left = NULL; + _right = NULL; + _data_type = NONE; - data_t data; - data.var = var; - _data_type = VARIABLE; - _data = data; - -// Stat_binary_tree(VARIABLE, data); + change_type (var); } Stat_binary_tree:: Stat_binary_tree (operator_t op) { - _root = NULL; - _left = NULL; - _right = NULL; + _root = NULL; + _left = NULL; + _right = NULL; + _data_type = NONE; - data_t data; - data.op = op; - _data_type = ((op == inc) or (op == dec))?OPERATOR_UNARY:OPERATOR_BINARY; - _data = data; + change_type (op); + } + Stat_binary_tree:: Stat_binary_tree (std::string expr, + std::map * operand) + { + _root = NULL; + _left = NULL; + _right = NULL; + _data_type = NONE; + + import (expr, operand); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_change_type.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_change_type.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_change_type.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef STATISTICS +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { + + void Stat_binary_tree::change_type (counter_t cst) + { + if (_data_type != NONE) + throw (ERRORMORPHEO("Stat_binary_tree::change_type",_("To change type, data_type must be \'NONE\'.\n"))); + + _data_type = CONSTANT; + _data.cst = cst; + } + + void Stat_binary_tree::change_type (counter_t * var) + { + if (_data_type != NONE) + throw (ERRORMORPHEO("Stat_binary_tree::change_type",_("To change type, data_type must be \'NONE\'.\n"))); + + _data_type = VARIABLE; + _data.var = var; + } + + void Stat_binary_tree::change_type (operator_t op ) + { + if (_data_type != NONE) + throw (ERRORMORPHEO("Stat_binary_tree::change_type",_("To change type, data_type must be \'NONE\'.\n"))); + + _data_type = ((op == inc) or (op == dec))?OPERATOR_UNARY:OPERATOR_BINARY; + _data.op = op; + } +}; +}; +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_import.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_import.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_import.cpp (revision 88) @@ -0,0 +1,139 @@ +#ifdef STATISTICS +#include "Behavioural/include/Stat_binary_tree.h" + +namespace morpheo { +namespace behavioural { + +#define string2operator(x) (x=="+")?add:((x=="-")?sub:((x=="*")?mul:((x=="/" )?div:((x=="++")?inc:dec)))) + + void Stat_binary_tree::import (std::string expr, + std::map * operand) + { + const std::string delims (" "); // délimiteur : " " + const std::string numbers ("0123456789"); // délimiteur : " " + std::string::size_type index_begin, index_end; + + Stat_binary_tree * tree = this; + + index_begin = expr.find_first_not_of(delims); + + while (index_begin != std::string::npos) + { + index_end = expr.find_first_of(delims, index_begin); + + if (index_end == std::string::npos) + { + index_end = expr.length(); + } + + std::string str = expr.substr(index_begin, index_end-index_begin); + + // 3 possibilités : + // * operator + // * constante + // * variable + { + // Test constantes + std::string::size_type index = str.find_first_not_of(numbers); + if (index == std::string::npos) + { +// std::cout << " * c'est une constante." << std::endl; + counter_t cst = atoi(str.c_str()); + + if (tree->_data_type == NONE) + change_type(cst); + else + if (tree==NULL) + tree = new Stat_binary_tree (cst); + else + tree = tree->insert_tree (cst); + } + else + { + // Test variables + std::map::iterator it = operand->find(str); + if (it != operand->end()) + { +// std::cout << " * c'est une variable." << std::endl; + counter_t * var = it->second; + + if (tree->_data_type == NONE) + change_type(var); + else + if (tree==NULL) + tree = new Stat_binary_tree (var); + else + tree = tree->insert_tree (var); + } + else + { + if ((str == "+") or + (str == "-") or + (str == "*") or + (str == "/")) + { +// std::cout << " * c'est un operator à 2 opérandes." << std::endl; + + operator_t op = string2operator(str); + + if (tree->_data_type == NONE) + change_type(op); + else + if (tree==NULL) + tree = new Stat_binary_tree (op); + else + tree = tree->insert_tree (op); + } + else + { + if ((str == "++") or + (str == "--")) + { +// std::cout << " * c'est un operator à 1 opérande." << std::endl; + + operator_t op = string2operator(str); + + if (tree->_data_type == NONE) + change_type(op); + else + if (tree==NULL) + tree = new Stat_binary_tree (op); + else + tree = tree->insert_tree (op); + } + else + { +// std::cout << " * c'est autre chose." << std::endl; + throw(ERRORMORPHEO("Stat_binary_tree::string2tree",toString(_("expression '%s' doesn't a constant, a declarated variable or an operator.\n"),str.c_str()))); + } + } + } + } + } + + index_begin = expr.find_first_not_of(delims, index_end); + + if (index_begin != std::string::npos) + tree = tree->goto_next_root(); + } + + if (tree == NULL) + throw (ERRORMORPHEO("Stat_binary_tree::string2tree",_("The tree generated is empty.\n"))); + +// std::cout << " goto_top_level" << std::endl; + + tree = tree->goto_top_level(); + +// std::cout << " valid" << std::endl; + +// print(); + + if ((not tree->valid()) or (not valid())) + throw (ERRORMORPHEO("Stat_binary_tree::string2tree",_("the tree generated is invalid.\n"))); + +// std::cout << " End" << std::endl; + } + +}; +}; +#endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_valid.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_valid.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_binary_tree_valid.cpp (revision 88) @@ -4,24 +4,90 @@ namespace morpheo { namespace behavioural { + bool Stat_binary_tree::valid (void) { + if (_data_type == NONE) + return false; + if ((_data_type == VARIABLE) or (_data_type == CONSTANT)) return ((_left == NULL) and - (_right == NULL) ); - + (_right == NULL) ); + if (_data_type == OPERATOR_UNARY) return ((_right == NULL) and - (_left != NULL) and - (_left->valid())); + (_left != NULL) and + (_left->valid())); if (_data_type == OPERATOR_BINARY) return ((_left != NULL ) and - (_left ->valid()) and - (_right != NULL ) and - (_right->valid())); + (_left ->valid()) and + (_right != NULL ) and + (_right->valid())); return false; } + + void Stat_binary_tree::print (uint32_t depth) + { + std::string tab = std::string(depth,'\t'); + std::string sep = " "; + if (_data_type == NONE) + { + std::cout << tab << " NONE (error)" << std::endl; + + if (_left != NULL) + _left ->print(depth+1); + if (_right != NULL) + _right->print(depth+1); + } + + if ((_data_type == VARIABLE) or + (_data_type == CONSTANT)) + { + std::cout << tab << "" + << " " + << ((_left == NULL)?"left == NULL ":"left != NULL (error)") + << " " + << ((_right == NULL)?"right == NULL ":"right != NULL (error)") + << std::endl; + + if (_left != NULL) + _left ->print(depth+1); + if (_right != NULL) + _right->print(depth+1); + } + + if (_data_type == OPERATOR_UNARY) + { + std::cout << tab << "" + << " " + << ((_left == NULL)?"left == NULL (error)":"left != NULL ") + << " " + << ((_right == NULL)?"right == NULL ":"right != NULL (error)") + << std::endl; + + if (_left != NULL) + _left ->print(depth+1); + if (_right != NULL) + _right->print(depth+1); + } + + if (_data_type == OPERATOR_BINARY) + { + std::cout << tab << "" + << " " + << ((_left == NULL)?"left == NULL (error)":"left != NULL ") + << " " + << ((_right == NULL)?"right == NULL (error)":"right != NULL ") + << std::endl; + + if (_left != NULL) + _left ->print(depth+1); + if (_right != NULL) + _right->print(depth+1); + } + } + }; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_generate_file.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_generate_file.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_generate_file.cpp (revision 88) @@ -2,4 +2,5 @@ #include "Behavioural/include/Stat.h" #include "Behavioural/include/Version.h" +#include "Common/include/Environment.h" namespace morpheo { @@ -8,4 +9,6 @@ void Stat::generate_file (void) { + directory(); + std::string body = print(1); @@ -26,6 +29,6 @@ xml->balise_close(); - xml->filename_extension ("stat"); - xml->generate_file(); + xml->filename_extension (".stat"); + xml->generate_file(MORPHEO_STATISTICS); delete xml; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_have_counter.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_have_counter.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_have_counter.cpp (revision 88) @@ -10,7 +10,8 @@ i!= _list_operand->end(); ++i) - if (i->second.type == TYPE_COUNTER) - return true; - + { + if (i->second.type == TYPE_COUNTER) + return true; + } return false; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_print.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_print.cpp (revision 88) @@ -7,4 +7,7 @@ std::string Stat::print (uint32_t depth) { +// log_printf(TRACE,Behavioural,"Stat::print","Component name : %s",_name_component.c_str()); +// log_printf(TRACE,Behavioural,"Stat::print","Instance name : %s",_name_instance .c_str()); + end_simulation(); @@ -21,6 +24,7 @@ stat != _list_stat->end(); stat ++) - xml.text((*stat)->print(1)); - + { + xml.text((*stat)->print(1)); + } // Test special case @@ -63,5 +67,5 @@ ++operand) { - if (operand->second.type == TYPE_COUNTER) + if (operand->second.type == TYPE_COUNTER) { xml.singleton_begin(operand->second.name); @@ -80,6 +84,7 @@ } } + xml.balise_close(); - + return xml.get_body(depth); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_string2tree.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_string2tree.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Stat_string2tree.cpp (revision 88) @@ -5,125 +5,18 @@ namespace behavioural { -#define string2operator(x) (x=="+")?add:((x=="-")?sub:((x=="*")?mul:((x=="/" )?div:((x=="++")?inc:dec)))) - Stat_binary_tree * Stat::string2tree (std::string expr) { - const std::string delims (" "); // délimiteur : " " - const std::string numbers ("0123456789"); // délimiteur : " " - std::string::size_type index_begin, index_end; + std::map * operand = new std::map; - Stat_binary_tree * tree = NULL; + for (std::map::iterator it = _list_operand->begin(); + it != _list_operand->end(); + ++ it) + (*operand) [it->first] = it->second.counter; - index_begin = expr.find_first_not_of(delims); + Stat_binary_tree * tree = new Stat_binary_tree(expr,operand); - while (index_begin != std::string::npos) - { - index_end = expr.find_first_of(delims, index_begin); - - if (index_end == std::string::npos) - { - index_end = expr.length(); - } - - std::string str = expr.substr(index_begin, index_end-index_begin); - - // 3 possibilités : - // * operator - // * constante - // * variable - { - // Test constantes - std::string::size_type index = str.find_first_not_of(numbers); - if (index == std::string::npos) - { -// std::cout << " * c'est une constante." << std::endl; - - if (tree==NULL) - tree = new Stat_binary_tree (atoi(str.c_str())); - else - tree = tree->insert_tree (atoi(str.c_str())); - } - else - { - // Test variables - std::map::iterator it = _list_operand->find(str); - if (it != _list_operand->end()) - { -// std::cout << " * c'est une variable." << std::endl; - - if (tree==NULL) - tree = new Stat_binary_tree (it->second.counter); - else - tree = tree->insert_tree (it->second.counter); - } - else - { - if ((str == "+") or - (str == "-") or - (str == "*") or - (str == "/")) - { -// std::cout << " * c'est un operator à 2 opérandes." << std::endl; - -// if (tree==NULL) -// tree = new Stat_binary_tree (morpheo::string2operator[str].second); -// else -// tree->insert_tree (morpheo::string2operator[str].second); - if (tree==NULL) - tree = new Stat_binary_tree (string2operator(str)); - else - tree = tree->insert_tree (string2operator(str)); - } - else - { - if ((str == "++") or - (str == "--")) - { -// std::cout << " * c'est un operator à 1 opérande." << std::endl; - -// if (tree==NULL) -// tree = new Stat_binary_tree (string2operator[str.c_str()]); -// else -// tree->insert_tree (string2operator[str.c_str()]); - - if (tree==NULL) - tree = new Stat_binary_tree (string2operator(str)); - else - tree = tree->insert_tree (string2operator(str)); - - } - else - { -// std::cout << " * c'est autre chose." << std::endl; - str = "expression '"+str+"' doesn't a constant, a declarated variable or an operator."; - throw(ERRORMORPHEO("Stat::string2tree",_(str.c_str()))); - } - } - } - } - } - - index_begin = expr.find_first_not_of(delims, index_end); - - if (index_begin != std::string::npos) - tree = tree->goto_next_root(); - } - - if (tree == NULL) - throw (ERRORMORPHEO("Stat::string2tree",_("the tree generated is empty."))); - -// std::cout << " goto_top_level" << std::endl; - - tree = tree->goto_top_level(); - -// std::cout << " valid" << std::endl; - - if (not tree->valid()) - throw (ERRORMORPHEO("Stat::string2tree",_("the tree generated is invalid."))); - -// std::cout << " End" << std::endl; + delete operand; return tree; - } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Types.cpp (revision 88) @@ -0,0 +1,258 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" +#include "Common/include/Translation.h" + +namespace morpheo { +namespace behavioural { + +#undef FUNCTION +#define FUNCTION "instruction_information" + instruction_t instruction_information (uint32_t instruction) + { + switch (instruction) + { + case INSTRUCTION_L_ADD : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_ADDC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_ADDI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_ADDIC : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_ADD ,ORBIS32,1); + case INSTRUCTION_L_AND : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_AND ,ORBIS32,1); + case INSTRUCTION_L_ANDI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_AND ,ORBIS32,1); + case INSTRUCTION_L_BF : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_TEST_F ,ORBIS32,1); + case INSTRUCTION_L_BNF : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_TEST_NF ,ORBIS32,1); + case INSTRUCTION_L_CMOV : return instruction_t (TYPE_MOVE ,OPERATION_MOVE_L_CMOV ,ORBIS32,2); + case INSTRUCTION_L_CSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_CSYNC ,ORBIS32,2); + case INSTRUCTION_L_CUST1 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_1 ,ORBIS32,2); + case INSTRUCTION_L_CUST2 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_2 ,ORBIS32,2); + case INSTRUCTION_L_CUST3 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_3 ,ORBIS32,2); + case INSTRUCTION_L_CUST4 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_4 ,ORBIS32,2); + case INSTRUCTION_L_CUST5 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_5 ,ORBIS32,2); + case INSTRUCTION_L_CUST6 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_6 ,ORBIS32,2); + case INSTRUCTION_L_CUST7 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_7 ,ORBIS32,2); + case INSTRUCTION_L_CUST8 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_L_8 ,ORBIS32,2); + case INSTRUCTION_L_DIV : return instruction_t (TYPE_DIV ,OPERATION_DIV_L_DIV ,ORBIS32,2); + case INSTRUCTION_L_DIVU : return instruction_t (TYPE_DIV ,OPERATION_DIV_L_DIVU ,ORBIS32,2); + case INSTRUCTION_L_EXTBS : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_S ,ORBIS32,2); + case INSTRUCTION_L_EXTBZ : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_Z ,ORBIS32,2); + case INSTRUCTION_L_EXTHS : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_S ,ORBIS32,2); + case INSTRUCTION_L_EXTHZ : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_Z ,ORBIS32,2); + case INSTRUCTION_L_EXTWS : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_S ,ORBIS64,2); + case INSTRUCTION_L_EXTWZ : return instruction_t (TYPE_EXTEND ,OPERATION_EXTEND_L_EXTEND_Z ,ORBIS64,2); + case INSTRUCTION_L_FF1 : return instruction_t (TYPE_FIND ,OPERATION_FIND_L_FF1 ,ORBIS32,2); + case INSTRUCTION_L_FL1 : return instruction_t (TYPE_FIND ,OPERATION_FIND_L_FL1 ,ORBIS32,2); + case INSTRUCTION_L_J : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_NONE ,ORBIS32,1); + case INSTRUCTION_L_JAL : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_JALR ,ORBIS32,1); + case INSTRUCTION_L_JALR : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_JALR ,ORBIS32,1); + case INSTRUCTION_L_JR : return instruction_t (TYPE_BRANCH ,OPERATION_BRANCH_L_JALR ,ORBIS32,1); + case INSTRUCTION_L_LBS : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_8_S ,ORBIS32,1); + case INSTRUCTION_L_LBZ : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_8_Z ,ORBIS32,1); + case INSTRUCTION_L_LD : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_64_S ,ORBIS64,1); + case INSTRUCTION_L_LHS : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_16_S ,ORBIS32,1); + case INSTRUCTION_L_LHZ : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_16_Z ,ORBIS32,1); + case INSTRUCTION_L_LWS : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_32_S ,ORBIS32,1); + case INSTRUCTION_L_LWZ : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_LOAD_32_Z ,ORBIS32,1); + case INSTRUCTION_L_MAC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MAC ,ORBIS32,2); + case INSTRUCTION_L_MACI : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MAC ,ORBIS32,2); + case INSTRUCTION_L_MACRC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MACRC ,ORBIS32,2); + case INSTRUCTION_L_MFSPR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MFSPR ,ORBIS32,1); + case INSTRUCTION_L_MOVHI : return instruction_t (TYPE_MOVE ,OPERATION_MOVE_L_MOVHI ,ORBIS32,1); + case INSTRUCTION_L_MSB : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MSB ,ORBIS32,2); + case INSTRUCTION_L_MSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MSYNC ,ORBIS32,2); + case INSTRUCTION_L_MTSPR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_MTSPR ,ORBIS32,1); + case INSTRUCTION_L_MUL : return instruction_t (TYPE_MUL ,OPERATION_MUL_L_MUL ,ORBIS32,1); + case INSTRUCTION_L_MULI : return instruction_t (TYPE_MUL ,OPERATION_MUL_L_MUL ,ORBIS32,1); + case INSTRUCTION_L_MULU : return instruction_t (TYPE_MUL ,OPERATION_MUL_L_MULU ,ORBIS32,1); + case INSTRUCTION_L_NOP : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORBIS32,1); + case INSTRUCTION_L_OR : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_OR ,ORBIS32,1); + case INSTRUCTION_L_ORI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_OR ,ORBIS32,1); + case INSTRUCTION_L_PSYNC : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_PSYNC ,ORBIS32,2); + case INSTRUCTION_L_RFE : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_RFE ,ORBIS32,1); + case INSTRUCTION_L_ROR : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_ROR ,ORBIS32,2); + case INSTRUCTION_L_RORI : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_ROR ,ORBIS32,2); + case INSTRUCTION_L_SB : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_STORE_8 ,ORBIS32,1); + case INSTRUCTION_L_SD : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_STORE_64 ,ORBIS64,1); + case INSTRUCTION_L_SFEQ : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFEQ ,ORBIS32,1); + case INSTRUCTION_L_SFEQI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFEQ ,ORBIS32,1); + case INSTRUCTION_L_SFGES : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGES ,ORBIS32,1); + case INSTRUCTION_L_SFGESI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGES ,ORBIS32,2); + case INSTRUCTION_L_SFGEU : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGEU ,ORBIS32,1); + case INSTRUCTION_L_SFGEUI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGEU ,ORBIS32,2); + case INSTRUCTION_L_SFGTS : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGTS ,ORBIS32,1); + case INSTRUCTION_L_SFGTSI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGTS ,ORBIS32,2); + case INSTRUCTION_L_SFGTU : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGTU ,ORBIS32,1); + case INSTRUCTION_L_SFGTUI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFGTU ,ORBIS32,2); + case INSTRUCTION_L_SFLES : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLES ,ORBIS32,1); + case INSTRUCTION_L_SFLESI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLES ,ORBIS32,2); + case INSTRUCTION_L_SFLEU : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLEU ,ORBIS32,1); + case INSTRUCTION_L_SFLEUI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLEU ,ORBIS32,2); + case INSTRUCTION_L_SFLTS : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLTS ,ORBIS32,1); + case INSTRUCTION_L_SFLTSI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLTS ,ORBIS32,2); + case INSTRUCTION_L_SFLTU : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLTU ,ORBIS32,1); + case INSTRUCTION_L_SFLTUI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFLTU ,ORBIS32,2); + case INSTRUCTION_L_SFNE : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFNE ,ORBIS32,1); + case INSTRUCTION_L_SFNEI : return instruction_t (TYPE_TEST ,OPERATION_TEST_L_SFNE ,ORBIS32,2); + case INSTRUCTION_L_SH : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_STORE_16 ,ORBIS32,1); + case INSTRUCTION_L_SLL : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SLL ,ORBIS32,1); + case INSTRUCTION_L_SLLI : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SLL ,ORBIS32,1); + case INSTRUCTION_L_SRA : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SRA ,ORBIS32,1); + case INSTRUCTION_L_SRAI : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SRA ,ORBIS32,1); + case INSTRUCTION_L_SRL : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SRL ,ORBIS32,1); + case INSTRUCTION_L_SRLI : return instruction_t (TYPE_SHIFT ,OPERATION_SHIFT_L_SRL ,ORBIS32,1); + case INSTRUCTION_L_SUB : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_SUB ,ORBIS32,1); + case INSTRUCTION_L_SW : return instruction_t (TYPE_MEMORY ,OPERATION_MEMORY_STORE_32 ,ORBIS32,1); + case INSTRUCTION_L_SYS : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_SYS ,ORBIS32,1); + case INSTRUCTION_L_TRAP : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_TRAP ,ORBIS32,2); + case INSTRUCTION_L_XOR : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_XOR ,ORBIS32,1); + case INSTRUCTION_L_XORI : return instruction_t (TYPE_ALU ,OPERATION_ALU_L_XOR ,ORBIS32,1); + + case INSTRUCTION_LF_ADD_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_ADD_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_CUST1_D : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LF_1_D ,ORFPX64,2); + case INSTRUCTION_LF_CUST1_S : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LF_1_S ,ORFPX32,2); + case INSTRUCTION_LF_DIV_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,2); + case INSTRUCTION_LF_DIV_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,2); + case INSTRUCTION_LF_FTOI_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_FTOI_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_ITOF_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_ITOF_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_MADD_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,2); + case INSTRUCTION_LF_MADD_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,2); + case INSTRUCTION_LF_MUL_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_MUL_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_REM_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,2); + case INSTRUCTION_LF_REM_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,2); + case INSTRUCTION_LF_SFEQ_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFEQ_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SFGE_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFGE_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SFGT_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFGT_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SFLE_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFLE_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SFLT_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFLT_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SFNE_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SFNE_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + case INSTRUCTION_LF_SUB_D : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX64,1); + case INSTRUCTION_LF_SUB_S : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORFPX32,1); + + case INSTRUCTION_LV_ADD_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADD_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDU_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDU_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDUS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ADDUS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_EQ_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_EQ_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_GE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_GE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_GT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_GT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_LE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_LE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_LT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_LT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_NE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ALL_NE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_AND : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_EQ_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_EQ_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_GE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_GE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_GT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_GT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_LE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_LE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_LT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_LT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_NE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_ANY_NE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_AVG_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_AVG_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_EQ_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_EQ_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_GE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_GE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_GT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_GT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_LE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_LE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_LT_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_LT_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_NE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CMP_NE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_CUST1 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LV_1 ,ORVDX64,2); + case INSTRUCTION_LV_CUST2 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LV_2 ,ORVDX64,2); + case INSTRUCTION_LV_CUST3 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LV_3 ,ORVDX64,2); + case INSTRUCTION_LV_CUST4 : return instruction_t (TYPE_CUSTOM ,OPERATION_CUSTOM_LV_4 ,ORVDX64,2); + case INSTRUCTION_LV_MADDS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MAX_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MAX_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MERGE_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MERGE_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MIN_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MIN_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MSUBS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_MULS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,2); + case INSTRUCTION_LV_NAND : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_NOR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_OR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACK_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACK_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACKS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACKS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACKUS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PACKUS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_PERM_N : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_RL_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_RL_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SLL : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SLL_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SLL_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SRA_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SRA_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SRL : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SRL_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SRL_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUB_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUB_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBU_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBU_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBUS_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_SUBUS_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_UNPACK_B : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_UNPACK_H : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + case INSTRUCTION_LV_XOR : return instruction_t (TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP ,ORVDX64,1); + + default : throw (ERRORMORPHEO (FUNCTION,_("Unknow instruction"))); + } + }; + +#undef FUNCTION +#define FUNCTION "instruction_size_data" + uint32_t instruction_size_data (uint32_t instruction) + { + ISA subset = instruction_information(instruction)._isa_subset; + + switch(subset) + { + case ORBIS32 : + case ORFPX32 : return 32; + case ORBIS64 : + case ORFPX64 : + case ORVDX64 : return 64; + default : throw (ERRORMORPHEO (FUNCTION,_("Unknow subset"))); + } + } + +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Usage.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Usage.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Usage.cpp (revision 88) @@ -20,34 +20,35 @@ return ((usage & flag) != 0); } - +#undef FUNCTION +#define FUNCTION "usage_environment" void usage_environment (Tusage_t usage) { #ifndef SYSTEMC if (usage_is_set(usage,USE_SYSTEMC)) - throw ErrorMorpheo(_("Component use the flag \"USE_SYSTEMC\", but the macro's compiler \"SYSTEMC\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_SYSTEMC\", but the macro's compiler \"SYSTEMC\" is unset.\n")); #endif #ifndef VHDL if (usage_is_set(usage,USE_VHDL)) - throw ErrorMorpheo(_("Component use the flag \"USE_VHDL\", but the macro's compiler \"VHDL\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_VHDL\", but the macro's compiler \"VHDL\" is unset.\n")); #endif #ifndef VHDL_TESTBENCH if (usage_is_set(usage,USE_VHDL_TESTBENCH)) - throw ErrorMorpheo(_("Component use the flag \"USE_VHDL_TESTBENCH\", but the macro's compiler \"VHDL_TESTBENCH\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_VHDL_TESTBENCH\", but the macro's compiler \"VHDL_TESTBENCH\" is unset.\n")); #endif #ifndef VHDL_TESTBENCH_ASSERT if (usage_is_set(usage,USE_VHDL_TESTBENCH_ASSERT)) - throw ErrorMorpheo(_("Component use the flag \"USE_VHDL_TESTBENCH_ASSERT\", but the macro's compiler \"VHDL_TESTBENCH_ASSERT\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_VHDL_TESTBENCH_ASSERT\", but the macro's compiler \"VHDL_TESTBENCH_ASSERT\" is unset.\n")); #endif #ifndef POSITION if (usage_is_set(usage,USE_POSITION)) - throw ErrorMorpheo(_("Component use the flag \"USE_POSITION\", but the macro's compiler \"POSITION\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_POSITION\", but the macro's compiler \"POSITION\" is unset.\n")); #endif #ifndef STATISTICS if (usage_is_set(usage,USE_STATISTICS)) - throw ErrorMorpheo(_("Component use the flag \"USE_STATISTICS\", but the macro's compiler \"STATISTICS\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_STATISTICS\", but the macro's compiler \"STATISTICS\" is unset.\n")); #endif #ifndef INFORMATION if (usage_is_set(usage,USE_INFORMATION)) - throw ErrorMorpheo(_("Component use the flag \"USE_INFORMATION\", but the macro's compiler \"INFORMATION\" is unset.")); + throw ERRORMORPHEO(FUNCTION,_("Component use the flag \"USE_INFORMATION\", but the macro's compiler \"INFORMATION\" is unset.\n")); #endif @@ -56,17 +57,17 @@ if (usage_is_set(usage,USE_STATISTICS) and not usage_is_set(usage,USE_SYSTEMC)) - throw ErrorMorpheo(_("Usage flags conflit : to use the statistics, you must set flag USE_SYSTEMC")); + throw ERRORMORPHEO(FUNCTION,_("Usage flags conflit : to use the statistics, you must set flag USE_SYSTEMC\n")); if (usage_is_set(usage,USE_INFORMATION) and not usage_is_set(usage,USE_STATISTICS)) - throw ErrorMorpheo(_("Usage flags conflit : to use the information, you must set flag USE_STATISTICS")); + throw ERRORMORPHEO(FUNCTION,_("Usage flags conflit : to use the information, you must set flag USE_STATISTICS\n")); if (usage_is_set(usage,USE_VHDL_TESTBENCH) and not usage_is_set(usage,USE_SYSTEMC)) - throw ErrorMorpheo(_("Usage flags conflit : to use the vhdl's test bench, you must set flag USE_SYSTEMC")); + throw ERRORMORPHEO(FUNCTION,_("Usage flags conflit : to use the vhdl's test bench, you must set flag USE_SYSTEMC\n")); if (usage_is_set(usage,USE_VHDL_TESTBENCH) and not usage_is_set(usage,USE_VHDL)) - throw ErrorMorpheo(_("Usage flags conflit : to use the vhdl's test bench, you must set flag USE_VHDL")); + throw ERRORMORPHEO(FUNCTION,_("Usage flags conflit : to use the vhdl's test bench, you must set flag USE_VHDL\n")); if (usage_is_set(usage,USE_VHDL_TESTBENCH_ASSERT) and not usage_is_set(usage,USE_VHDL_TESTBENCH)) - throw ErrorMorpheo(_("Usage flags conflit : to use an assert in vhdl's test bench, you must set flag USE_VHDL_TESTBENCH")); + throw ERRORMORPHEO(FUNCTION,_("Usage flags conflit : to use an assert in vhdl's test bench, you must set flag USE_VHDL_TESTBENCH\n")); } @@ -96,5 +97,5 @@ usage = usage_set(usage,USE_INFORMATION); #endif - + usage = usage_set(usage,USE_HEADER); #ifdef DEBUG #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_model.cpp (revision 88) @@ -9,4 +9,5 @@ #include "Behavioural/include/Vhdl.h" +#include "Common/include/Environment.h" #include #include @@ -19,8 +20,9 @@ log_printf(FUNC,Behavioural,"generate_file_model","Begin"); - std::string filename = _name + ".vhdl"; + directory(); + + std::string filename = MORPHEO_VHDL + "/" + _name + ".vhdl"; - log_printf(TRACE,Behavioural,"generate_file_model","print %s",filename.c_str()); - std::cout << "Generate file \""<< filename << "\"" << std::endl; + msg_printf(INFORMATION,_("Generate file \"%s\"."),filename.c_str()); log_printf(TRACE,Behavioural,"generate_file_model","declaration"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_generate_file_package.cpp (revision 88) @@ -9,4 +9,5 @@ #include "Behavioural/include/Vhdl.h" +#include "Common/include/Environment.h" #include #include @@ -19,8 +20,10 @@ log_printf(FUNC,Behavioural,"generate_file_package","Begin"); + directory(); + std::string name = _name + "_Pack"; - std::string filename = name + ".vhdl"; + std::string filename = MORPHEO_VHDL + "/" + name + ".vhdl"; - std::cout << "Generate file \""<< filename << "\"" << std::endl; + msg_printf(INFORMATION,_("Generate file \"%s\"."),filename.c_str()); std::ofstream file; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_get_header.cpp (revision 88) @@ -32,5 +32,5 @@ text += "-- "+toString(_("File : ")) + filename +"\n"; text += "-- "+toString(_("Date : ")) + ctime (¤t_time ); - text += "-- "+toString(_("Morpheo version : ")) + MORPHEO_VERSION +"\n"; + text += "-- "+toString(_("Morpheo version : ")) + MORPHEO_HEADER +"\n"; text += "-- "+toString(_("Comment : ")) + _("it's a autogenerated file, don't modify") +"\n"; text += "-------------------------------------------------------------------------------\n"; @@ -38,5 +38,5 @@ log_printf(FUNC,Behavioural,FUNCTION,"End"); - return text.str(); + return text; }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body.cpp (revision 88) @@ -17,8 +17,22 @@ #undef FUNCTION #define FUNCTION "Vhdl::set_body" - void Vhdl::set_body (std::string text ) + void Vhdl::set_body (std::string text) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); set_list(_list_body, text); + log_printf(FUNC,Behavioural,FUNCTION,"End"); + }; + +#undef FUNCTION +#define FUNCTION "Vhdl::set_body" + void Vhdl::set_body (Vhdl * vhdl) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + + for (std::list::iterator it=vhdl->_list_body.begin(); + it!=vhdl->_list_body.end(); + ++it) + set_list(_list_body, *it); + log_printf(FUNC,Behavioural,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML.cpp (revision 88) @@ -17,5 +17,5 @@ { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - _filename_extension="xml"; + _filename_extension=".xml"; log_printf(FUNC,Behavioural,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XMLLightFunctors.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XMLLightFunctors.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XMLLightFunctors.cpp (revision 88) @@ -0,0 +1,42 @@ +#include "Behavioural/include/XMLLightFunctors.h" + +using namespace morpheo::XMLUtils; +using namespace std; + + //****************************XMLLightComparator method implementation*****************************// + + // the comparator functor used within parsing algorithm. + + bool XMLLightComparator::operator() ( char firstChar, char secondChar ) { + static unsigned int counter = 0; + static bool searchForEndTag = false; + + if ( searchForEndTag ) { + if ( secondChar == END_TAG ) { + searchForEndTag = false; + return true; + } + return false; + } + + if + ( ( firstChar == BEGIN_TAG && secondChar == SECOND_TAG ) || + ( firstChar == SECOND_TAG && secondChar == END_TAG ) ) { + --counter; + if ( ! counter ) { + if( firstChar == SECOND_TAG ) { + return true; + } + searchForEndTag = true; + return false; + } + return false; + } + else if ( firstChar == BEGIN_TAG ) { + counter++; + return false; + } + else { + return false; + } + } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_generate_file.cpp (revision 88) @@ -7,4 +7,5 @@ #include "Behavioural/include/XML.h" +#include "Common/include/ErrorMorpheo.h" #include @@ -14,5 +15,5 @@ #undef FUNCTION #define FUNCTION "XML::generate_file" - void XML::generate_file (std::string encoding) + void XML::generate_file (std::string dirname, std::string encoding) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); @@ -20,10 +21,13 @@ header (encoding); - std::string filename = _name + "." + _filename_extension; + std::string filename = dirname + "/" + _name + _filename_extension; - std::cout << "Generate file \""<< filename << "\"" << std::endl; + msg_printf(INFORMATION,_("Generate file \"%s\"."),filename.c_str()); std::ofstream file; - file.open(filename.c_str(),std::ios::out | std::ios::trunc); + file.open(filename.c_str() ,std::ios::out | std::ios::trunc); + + if (!file) + throw ERRORMORPHEO(FUNCTION,toString(_("Error opening \"%s\" file.\n"),filename.c_str())); file << get_body(); @@ -34,8 +38,8 @@ }; - void XML::generate_file (void) + void XML::generate_file (std::string dirname) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - generate_file("UTF-8"); + generate_file(dirname,"UTF-8"); log_printf(FUNC,Behavioural,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/XML_get_body.cpp (revision 88) @@ -24,10 +24,10 @@ log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string body = _body; - std::string tabulation = indent(depth); + std::string body = _body; + std::string tab = indent(depth); -// body.insert(0,tabulation); + body.insert(0,tab); for (size_t pos=body.find('\n',0); (pos #include #include @@ -31,4 +33,6 @@ #include #include + +namespace morpheo { enum _debug_verbosity @@ -54,7 +58,16 @@ ( DEBUG_ ## component == true )) ) \ { \ + if (DEBUG_ ## level <= DEBUG_INFO) \ + { \ + msg("%s ",MSG_INFORMATION); \ + } \ + else \ + { \ + msg("%s ",MSG_DEBUG); \ + } \ + \ if (DEBUG >= DEBUG_FUNC) \ { \ - msg(_("%s"),debug_tab().c_str()); \ + msg("%s",debug_tab().c_str()); \ } \ if (DEBUG >= DEBUG_ALL ) \ @@ -72,12 +85,11 @@ if (DEBUG >= DEBUG_FUNC) \ { \ - msg(_("<%s> "),func); \ - msg(_("In file %s, "),__FILE__); \ - msg(_("at line %d " ),__LINE__); \ - msg(_(": ")); \ - } \ - msg(str); \ - msg(_("\n")); \ - fflush (stdout); \ + msg( "<%s> " ,func); \ + msg(_("In file %s, "),__FILE__); \ + msg(_("at line %d " ),__LINE__); \ + msg( ": " ); \ + } \ + msg(str); \ + msg("\n"); \ } \ } while(0) @@ -87,5 +99,5 @@ { \ debug_tab_inc (); \ - log_printf(FUNC,component,func,"Begin"); \ + log_printf(FUNC,component,func,_("Begin")); \ } while(0) @@ -93,5 +105,5 @@ do \ { \ - log_printf(FUNC,component,func,"End"); \ + log_printf(FUNC,component,func,_("End")); \ debug_tab_dec (); \ } while(0) @@ -115,9 +127,30 @@ #endif // DEBUG +# define log_function(component,func,name) \ + do \ + { \ + log_printf(TRACE,component,func,_("[%d] %s.%s"),static_cast(sc_simulation_time()),name,func); \ + } while(0) + + +#define msg_printf(type,str...) \ + do \ + { \ + msg("%s ",MSG_ ## type); \ + msg(str); \ + msg("\n"); \ + } while(0) + + #define breakpoint(str...) \ do \ { \ - msg(_("Breakpoint : file %s, line %d. Enter Any key to continue\n"),__FILE__,__LINE__); \ - msg(str); \ + fprintf(stdout,_("%s "),MSG_BREAKPOINT); \ + fprintf(stdout,_("Breakpoint in file %s, line %d.\n"),__FILE__,__LINE__); \ + fprintf(stdout,_("%s "),MSG_NONE); \ + fprintf(stdout,str); \ + fprintf(stdout,_("\n")); \ + fprintf(stdout,_("%s "),MSG_NONE); \ + fprintf(stdout,_("Enter any key to continue\n")); \ getchar(); \ } while(0) @@ -128,5 +161,5 @@ { \ if (x == NULL) \ - err(_("%s File %s, Line %d, this pointeur is null\n"),MSG_ERROR,__FILE__,__LINE__); \ + err(_("File %s, Line %d, this pointeur is null\n"),__FILE__,__LINE__); \ } \ while (0) @@ -139,4 +172,4 @@ #endif - +}; // end namespace morpheo #endif // !DEBUG_H Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Environment.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Environment.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Environment.h (revision 88) @@ -0,0 +1,62 @@ +#ifndef Morpheo_Environment_h +#define Morpheo_Environment_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include + +namespace morpheo { + +#if (defined(STATISTICS) and not defined(SYSTEMC)) +# error "To have the statistics, you must set flags SYSTEMC" +#endif + +#if (defined(INFORMATION) and not defined(STATISTICS)) +# error "To have the information, you must set flags STATISTICS" +#endif + +#if (defined(VHDL_TESTBENCH) and not defined(SYSTEMC)) +# error "To have the vhdl's test bench, you must set flags SYSTEMC" +#endif + +#if (defined(VHDL_TESTBENCH) and not defined(VHDL)) +# error "To have the vhdl's test bench, you must set flags VHDL" +#endif + +#if (defined(VHDL_TESTBENCH_ASSERT) and not defined(VHDL_TESTBENCH)) +# error "To have an assert in vhdl's test bench, you must set flags VHDL_TESTBENCH" +#endif + +#if (defined(VHDL_TESTBENCH) and defined(SYSTEMC)) +# define SYSTEMC_VHDL_COMPATIBILITY +#endif + +#if (defined(DEBUG)) +# define DEBUG_TEST +#endif + + // Environment variable + extern std::string MORPHEO_HOME; + extern std::string MORPHEO_TOPLEVEL; + + void environment (void); + + extern std::string MORPHEO_STATISTICS; + extern std::string MORPHEO_VHDL; + extern std::string MORPHEO_POSITION; + extern std::string MORPHEO_LOG; + + void directory (void); + void directory_init (std::string MORPHEO_STATISTICS =".", + std::string MORPHEO_VHDL =".", + std::string MORPHEO_POSITION =".", + std::string MORPHEO_LOG ="."); + +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/Common/include/ErrorMorpheo.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/ErrorMorpheo.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/ErrorMorpheo.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_ErrorMorpheo -#define morpheo_ErrorMorpheo +#ifndef Morpheo_ErrorMorpheo_h +#define Morpheo_ErrorMorpheo_h /* @@ -9,5 +9,8 @@ */ -#include "ToString.h" +#include "Common/include/ToString.h" +#include "Common/include/Translation.h" +#include "Common/include/Message.h" + #include #include @@ -23,6 +26,6 @@ // -----[ methods ]--------------------------------------------------- - public : ErrorMorpheo () throw() {_msg="Exception detected ...";} - public : ErrorMorpheo (std::string msg) throw() {_msg=msg;} + public : ErrorMorpheo () throw() {_msg = toString("%s ",MSG_ERROR); _msg+="Exception detected ...";} + public : ErrorMorpheo (std::string msg) throw() {_msg = toString("%s ",MSG_ERROR); _msg+=msg;} public : ErrorMorpheo (std::string funcname, std::string msg , @@ -30,5 +33,9 @@ std::string file ) throw() { - _msg = toString("<%s> at line %d, in file %s : %s",funcname.c_str(),line,file.c_str(),msg.c_str()); +#ifdef DEBUG + _msg = toString(_("%s <%s> at line %d, in file %s : %s"),MSG_ERROR,funcname.c_str(),line,file.c_str(),msg.c_str()); +#else + _msg = toString(_("%s %s"),MSG_ERROR,msg.c_str()); +#endif } public : ~ErrorMorpheo (void) throw() {} @@ -43,5 +50,5 @@ // -----[ methods ]--------------------------------------------------- - public : TestMorpheo () throw() {_msg="Test error ...";} + public : TestMorpheo () throw() {_msg=_("Test error ...");} public : TestMorpheo (std::string msg) throw() {_msg=msg;} public : ~TestMorpheo (void) throw() {} Index: trunk/IPs/systemC/processor/Morpheo/Common/include/FromString.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/FromString.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/FromString.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_fromstring -#define morpheo_fromstring +#ifndef Morpheo_FromString_h +#define Morpheo_FromString_h /* @@ -27,4 +27,14 @@ } + template<> inline uint64_t fromString (const std::string& x) + { + return static_cast(atoll(x.c_str())); + } + + template<> inline double fromString (const std::string& x) + { + return static_cast(atof(x.c_str())); + } + template<> inline bool fromString (const std::string& x) { Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Log2.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Log2.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Log2.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_Log2 -#define morpheo_Log2 +#ifndef Morpheo_Log2_h +#define Morpheo_Log2_h /* Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Max.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Max.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Max.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_max -#define morpheo_max +#ifndef Morpheo_Max_h +#define Morpheo_Max_h /* @@ -13,16 +13,48 @@ namespace morpheo { - template inline T max (const T * x, uint32_t size) + template inline T max (T * x, uint32_t size) { T res = x[0]; for (uint32_t i=1; i inline T max (const T * x, uint32_t size, uint32_t n) + template inline T max (T ** x, uint32_t size1, uint32_t size2) + { + T res = max(x[0],size2); + + for (uint32_t i=1; i inline T max (T ** x, uint32_t size1, uint32_t * size2) + { + T res = max(x[0],size2[0]); + + for (uint32_t i=1; i inline T max (T * x, uint32_t size, uint32_t n) { if ((n==0) or (n>size)) Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef MESSAGE_H -#define MESSAGE_H +#ifndef Morpheo_Message_h +#define Morpheo_Message_h /* * $Id$ @@ -15,20 +15,87 @@ namespace morpheo { -#define MSG_ERROR _("[ ERROR ]") -#define MSG_WARNING _("[ WARNING ]") -#define MSG_INFORMATION _("[INFORMATION]") + // Color + // 31 : rouge + // 32 : vert + // 33 : jaune + // 34 : bleu + // 35 : rose + // 36 : cyan + // 37 : blanc + // 38 : noir souligne + // 39 : noir -#define msg(arg...) \ +# define MSG_NONE _(" ") +#ifdef PRINT_COLOR +# define MSG_DEBUG _("[ DEBUG ]") +# define MSG_ERROR _("[ ERROR ]") +# define MSG_WARNING _("[ WARNING ]") +# define MSG_INFORMATION _("[INFORMATION]") +# define MSG_BREAKPOINT _("[ BREAK ]") +#else +# define MSG_DEBUG _("[ DEBUG ]") +# define MSG_ERROR _("[ ERROR ]") +# define MSG_WARNING _("[ WARNING ]") +# define MSG_INFORMATION _("[INFORMATION]") +# define MSG_BREAKPOINT _("[ BREAK ]") +#endif + +#ifdef LOG_FILE +extern FILE * log_stream; +void log_init (void); + +#define fmsg(stream,arg...) \ do \ { \ - fprintf(stdout,arg); \ + log_init(); \ + fprintf(log_stream,arg); \ + fflush(log_stream); \ + } while (0) + +#else + +#define fmsg(stream,arg...) \ + do \ + { \ + fprintf(stream,arg); \ + fflush(stream); \ } while (0) -#define err(arg...) \ +#endif + +#define fmsgDebug(stream,arg...) \ do \ { \ - fprintf(stderr,arg); \ + fmsg(stream,"%s ",MSG_DEBUG); \ + fmsg(stream,arg); \ } while (0) +#define fmsgError(stream,arg...) \ + do \ + { \ + fmsg(stream,"%s ",MSG_ERROR); \ + fmsg(stream,arg); \ + } while (0) + +#define fmsgWarning(stream,arg...) \ + do \ + { \ + fmsg(stream,"%s ",MSG_WARNING); \ + fmsg(stream,arg); \ + } while (0) + +#define fmsgInformation(stream,arg...) \ + do \ + { \ + fmsg(stream,"%s ",MSG_INFORMATION); \ + fmsg(stream,arg); \ + } while (0) + +#define msg(arg...) fmsg(stdout,arg) +#define msgDebug(arg...) fmsgDebug(stdout,arg) +#define msgError(arg...) fmsgError(stdout,arg) +#define msgWarning(arg...) fmsgWarning(stdout,arg) +#define msgInformation(arg...) fmsgInformation(stdout,arg) +#define err(arg...) fmsgError(stderr,arg) }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Percent.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Percent.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Percent.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_Percent -#define morpheo_Percent +#ifndef Morpheo_Percent_h +#define Morpheo_Percent_h /* Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Test.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Test.h (revision 88) @@ -1,4 +1,12 @@ -#ifndef TEST_H -#define TEST_H +#ifndef Morpheo_Test_h +#define Morpheo_Test_h + +/* + * $Id$ + * + * [ Description ] + * + * Macro / function to test + */ #include @@ -11,5 +19,6 @@ namespace morpheo { -//-----[ Routine de test ]--------------------------------------- +#define STR_OK "Test OK" +#define STR_KO "Test KO" static uint32_t num_test; @@ -24,5 +33,8 @@ inline void test_ko (char * file, uint32_t line, T exp1, T exp2) { - std::cerr << "[" << num_test << "] : Test KO" + fflush (stdout); + fflush (stderr); + + std::cerr << "[" << num_test << "] : " << STR_KO << "\tline " << line << std::endl << " * Localisation" << std::endl @@ -38,5 +50,8 @@ inline void test_ko (char * file, uint32_t line) { - std::cerr << "[" << num_test << "] : Test KO" + fflush (stdout); + fflush (stderr); + + std::cerr << "[" << num_test << "] : " << STR_KO << "\tline " << line << std::endl << " * Localisation" << std::endl @@ -49,5 +64,8 @@ inline void test_ok () { - msg (_("[%d] : Test OK\n"), num_test); + fflush (stdout); + fflush (stderr); + + msg (_("[%d] : %s\n"), num_test,STR_OK); num_test ++; @@ -56,5 +74,8 @@ inline void test_ok (char * file, uint32_t line) { - msg (_("[%d] : Test OK\n"), num_test); + fflush (stdout); + fflush (stderr); + + msg (_("[%d] : %s\n"), num_test,STR_OK); msg (_("\tline %d\n"), line); @@ -65,5 +86,8 @@ inline void test_ok (char * file, uint32_t line, T exp) { - msg (_("[%d] : Test OK\n"), num_test); + fflush (stdout); + fflush (stderr); + + msg (_("[%d] : %s\n"), num_test, STR_OK); msg (_("\tline %d\n"), line); msg (_("\tvalue %s\n"), (morpheo::toString(exp)).c_str()); @@ -91,6 +115,6 @@ msg (str); \ msg (_("\n")); \ + fflush (stdout); \ } while(0) - #ifndef CYCLE_MAX @@ -109,5 +133,5 @@ } \ \ - if (cycle_current > CYCLE_MAX) \ + if ((CYCLE_MAX != 0) and (cycle_current > CYCLE_MAX)) \ { \ TEST_KO("Maximal cycles Reached"); \ Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef TIME_H -#define TIME_H +#ifndef Morpheo_Time_h +#define Morpheo_Time_h #ifdef SYSTEMC @@ -10,14 +10,22 @@ #include +namespace morpheo { + class Time { -private : timeval time_begin; +#ifdef SYSTEMC +private : double nb_cycles_begin; +#endif +private : timeval time_begin; // private : timeval time_end; public : Time () - { - gettimeofday(&time_begin ,NULL); + { +#ifdef SYSTEMC + nb_cycles_begin = sc_simulation_time(); +#endif + gettimeofday(&time_begin,NULL); }; - + public : ~Time () { @@ -25,20 +33,27 @@ }; -public : friend std::ostream& operator<< (std::ostream& output_stream, +public : friend std::ostream& operator<< (std::ostream& output, const Time & x) { timeval time_end; - gettimeofday(&time_end ,NULL); + gettimeofday(&time_end,NULL); - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); +#ifdef SYSTEMC + double nb_cycles_end = sc_simulation_time(); + double average = static_cast(nb_cycles_end-x.nb_cycles_begin+1) / static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); - output_stream << "Timing : " << nb_cycles << " cycles \t(" << average << " cycles/s)" << std::endl; - - return output_stream; + output << "Timing : " << nb_cycles_end << " cycles \t(" << average << " cycles/s)" << std::endl; +#else + double average = static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); + + output << "Timing : " average << " s" << std::endl; +#endif + + return output; } }; +}; // end namespace morpheo + #endif Index: trunk/IPs/systemC/processor/Morpheo/Common/include/ToBase2.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/ToBase2.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/ToBase2.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_ToBase2 -#define morpheo_ToBase2 +#ifndef Morpheo_ToBase2_h +#define Morpheo_ToBase2_h /* Index: trunk/IPs/systemC/processor/Morpheo/Common/include/ToString.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/ToString.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/ToString.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_tostring -#define morpheo_tostring +#ifndef Morpheo_ToString_h +#define Morpheo_ToString_h /* Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Translation.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Translation.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Translation.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_Translation_H -#define morpheo_Translation_H +#ifndef Morpheo_Translation_h +#define Morpheo_Translation_h /* * $Id$ @@ -16,18 +16,13 @@ #define MORPHEO_PACKAGE "morpheo" -#ifdef NO_TRANSLATION +#ifdef TRANSLATION +# define _(str) dgettext (MORPHEO_PACKAGE,str) +#else # define _(str) (str) -#else -# define _(str) dgettext (MORPHEO_PACKAGE,str) #endif namespace morpheo { - class Translation - { - public : Translation (void); - public : ~Translation (void); - }; - + void translation (void); }; // end namespace morpheo #endif Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Types.h (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Types.h (revision 88) @@ -1,4 +1,4 @@ -#ifndef morpheo_Type -#define morpheo_Type +#ifndef Morpheo_Type_h +#define Morpheo_Type_h /* @@ -34,19 +34,19 @@ // #endif -#define SC_CLOCK sc_in_clk -// #define SC_INTERNAL(type) type -// #define SC_REGISTER(type) sc_signal -// #define SC_SIGNAL(type) sc_signal -#define SC_IN(type) sc_in -#define SC_OUT(type) sc_out +# define SC_CLOCK sc_in_clk +//#define SC_INTERNAL(type) type +//#define SC_REGISTER(type) sc_signal +//#define SC_SIGNAL(type) sc_signal +# define SC_IN(type) sc_in +# define SC_OUT(type) sc_out -#define PORT_READ(sig) sig->read() -#define PORT_WRITE(sig,val) sig->write(val) -// #define INTERNAL_READ(sig) (*sig) -// #define INTERNAL_WRITE(sig,val) (*sig) = val -// #define SIGNAL_READ(sig) sig->read() -// #define SIGNAL_WRITE(sig,val) sig->write(val) -// #define REGISTER_READ(sig) sig->read() -// #define REGISTER_WRITE(sig,val) sig->write(val) +# define PORT_READ(sig) sig->read() +# define PORT_WRITE(sig,val) sig->write(val) +//#define INTERNAL_READ(sig) (*sig) +//#define INTERNAL_WRITE(sig,val) (*sig) = val +//#define SIGNAL_READ(sig) sig->read() +//#define SIGNAL_WRITE(sig,val) sig->write(val) +//#define REGISTER_READ(sig) sig->read() +//#define REGISTER_WRITE(sig,val) sig->write(val) #endif Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 88) @@ -7,7 +7,12 @@ #include "Common/include/Debug.h" +#include "Common/include/Environment.h" + +namespace morpheo { static uint32_t _debug_depth = 0; +#undef FUNCTION +#define FUNCTION "debug_tab" std::string debug_tab (void) { @@ -15,4 +20,6 @@ } +#undef FUNCTION +#define FUNCTION "debug_tab_inc" void debug_tab_inc (void) { @@ -20,6 +27,10 @@ } +#undef FUNCTION +#define FUNCTION "debug_tab_dec" void debug_tab_dec (void) { // _debug_depth --; } + +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp (revision 88) @@ -0,0 +1,104 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Environment.h" +#include "Common/include/ErrorMorpheo.h" +#include "Common/include/Debug.h" +#include + +namespace morpheo { + +static bool environment_initialized; +std::string MORPHEO_HOME; +std::string MORPHEO_TOPLEVEL; + +#undef FUNCTION +#define FUNCTION "environment" +void environment (void) +{ + if (not environment_initialized) + { + { + char * toplevel = getenv("MORPHEO_TOPLEVEL"); + + if (toplevel == NULL) + throw ERRORMORPHEO(FUNCTION,_("Error morpheo environment is not positioned.\n")); + + MORPHEO_TOPLEVEL = toplevel; + } + + { + char * home = getenv("MORPHEO_HOME"); + + if (home == NULL) + throw ERRORMORPHEO(FUNCTION,_("Error morpheo environment is not positioned.\n")); + + MORPHEO_HOME = home; + } + + environment_initialized = true; + } +} + +static bool directory_initialized; +std::string MORPHEO_STATISTICS; +std::string MORPHEO_VHDL; +std::string MORPHEO_POSITION; +std::string MORPHEO_LOG; + +#undef FUNCTION +#define FUNCTION "exist_directory" +void exist_directory (std::string dir) +{ +// struct stat *buf; +// int res = stat(dir.c_str(), buf); +// if ((res != 0) or not S_ISDIR(buf->st_mode)) +// throw ERRORMORPHEO(FUNCTION,toString(_("Error in opening directory \"%s\".\n"),dir.c_str())); + + + char * pwd = getenv("PWD"); + if (chdir(dir.c_str())!=0) + throw ERRORMORPHEO(FUNCTION,toString(_("Error in opening directory \"%s\".\n"),dir.c_str())); + chdir(pwd); +} + +#undef FUNCTION +#define FUNCTION "directory_init" +void directory_init (std::string morpheo_statistics, + std::string morpheo_vhdl , + std::string morpheo_position , + std::string morpheo_log ) +{ + if (not directory_initialized) + { + exist_directory(morpheo_statistics); + exist_directory(morpheo_vhdl ); + exist_directory(morpheo_position ); + exist_directory(morpheo_log ); + + MORPHEO_STATISTICS = morpheo_statistics; + MORPHEO_VHDL = morpheo_vhdl ; + MORPHEO_POSITION = morpheo_position ; + MORPHEO_LOG = morpheo_log ; + + directory_initialized = true; + } +// else +// { +// msg_printf(WARNING,_("Multi instance of Morpheo : directory, keep actual directory.")); +// } +} + +#undef FUNCTION +#define FUNCTION "directory" +void directory (void) +{ + // with default value + directory_init(); +}; + +}; //end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 88) @@ -0,0 +1,48 @@ +#ifdef LOG_FILE +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Common/include/Debug.h" +#include "Common/include/Environment.h" +#include "Common/include/ToString.h" +#include "Common/include/ErrorMorpheo.h" +#include +#include + +namespace morpheo { + +static bool log_initialized; +FILE * log_stream; + +#undef FUNCTION +#define FUNCTION "log_init" +void log_init (void) +{ + if (not log_initialized) + { + log_initialized = true; + + directory(); + + std::string filename = MORPHEO_LOG+"/Morpheo_"+toString(getpid())+".log"; + + log_stream = fopen (filename.c_str(), "w"); + + if (log_stream==NULL) + { + fprintf(stderr,_("%s Error create log file \"%s\", take the standard output.\n"),MSG_ERROR,filename.c_str()); + log_stream = stdout; + } + else + { + fprintf(stdout,_("%s Create log file \"%s\".\n"),MSG_INFORMATION,filename.c_str()); + } + } +} + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Translation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Translation.cpp (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Translation.cpp (revision 88) @@ -6,28 +6,29 @@ */ -#include "../include/Translation.h" -#include "../include/ErrorMorpheo.h" +#include "Common/include/Environment.h" +#include "Common/include/Translation.h" +#include "Common/include/ErrorMorpheo.h" namespace morpheo { - Translation:: Translation (void) + static bool translation_initialized; + + void translation (void) { -#ifndef NO_TRANSLATION - char * top_level = getenv("MORPHEO_TOPLEVEL"); - - if (top_level == NULL) - throw ERRORMORPHEO("Translation","Error morpheo environment is not positioned\n"); - - std::string dirname = top_level; - dirname += "IPs/systemC/processor/Morpheo/locale"; +#ifdef TRANSLATION + if (not translation_initialized) + { + environment(); + + std::string dirname = MORPHEO_TOPLEVEL; + dirname += "/IPs/systemC/processor/Morpheo/locale"; - bindtextdomain(MORPHEO_PACKAGE,dirname.c_str()); + if (bindtextdomain(MORPHEO_PACKAGE,dirname.c_str()) == NULL) + throw ERRORMORPHEO("Translation","Error in set directory containing message catalogs.\n"); + + translation_initialized = true; + } #endif } - Translation::~Translation (void) - { - - } - }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-morpheo-microarchitecture/en/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-morpheo-microarchitecture/en/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation-morpheo-microarchitecture/en/root.tex (revision 88) @@ -0,0 +1,7 @@ +\ContentsCurrent + +\slidetitle{Context} + { + } + { + } Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation_bull/fr/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation_bull/fr/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Documents/presentation_bull/fr/root.tex (revision 88) @@ -0,0 +1,753 @@ +\section{Motivations} +\ContentsCurrent + +\slidetitle{Cadre de la thèse} + { + \begin{itemize} + \item {\it Cadre :}\newline + Collaboration avec Bull sur le projet PFC\newline + (Plate-forme de confiance totale) + \item {\it Notre contribution :}\newline + Réalisation d'un générateur de processeur ouvert. + \end{itemize} + } + { + Expliquer PFC + } + +\slidetitle{Approche actuelle fondée sur le secret} + { + \begin{itemize} + \item Composants fermés. + \item Consortium de certification + \begin{itemize} + \item Trusted Computing Platform Alliance +% \begin{itemize} +% \item Next-Generation Secure Computing Base +% \item Intel Trusted Execution Technology +% \end{itemize} + \end{itemize} + \end{itemize} + + \printgraph{Logo-trusted_computing_group}{0.8} + + Limite de l'approche : + + \begin{itemize} + \item Pas de confiance : + \begin{itemize} + \item Chevaux de troie + \end{itemize} + \item Pas de pérennité : + \begin{itemize} + \item Arrêt de production + \item Changement de protocole + \end{itemize} + \end{itemize} + } + { + Consortium : intel, amd, ibm, microsoft ... + + Le principe du TCG : + + \begin{itemize} + \item Assigner une signature à chaque objet informatique (logiciel, par extension matériel). + \item Déléguer à un {\it tiers de confiance} la tâche de vérifier si l'objet manipulé est autorisé à être utilisé sur le système local. + \end{itemize} + + Enjeux commerciaux != Ouvert et Pérennité. + } + +\slidetitle{Nouvelle approche} + { + \begin{itemize} + \item Composants ouverts + \begin{itemize} + \item Pas de fonctionnalités cachées. + \item Pas de secret à conserver. + \end{itemize} + \item Intégration : + \begin{itemize} + \item Field-Programmable Gate Array (FPGA). + \item System On Chip (SOC). + \end{itemize} + \end{itemize} + + \begin{center} + \begin{minipage}{.4\textwidth} + \printgraph{Logo-opencores}{0.8} + \end{minipage} + \begin{minipage}{.4\textwidth} + \printgraph{Logo-soclib}{0.8} + \end{minipage} + \end{center} + } + { + Composant matériel ouvert = code source disponible = FPGA = prototypage = SOC. + } + +\section{Cahier des charges} +\ContentsCurrent + +\slidetitle{Besoins : Cahier des charges} + { + Il faut une architecture : + \begin{description} + \item [Ouverte :] Évite les fonctionnalités cachées. + \item [Pérenne :] Évite les problèmes d'approvisionnements. + \item [Paramétrable :] S'adapte aux critères de l'application. + \item [Performante :] Applications nécessitant de la puissance de calculs. + \end{description} + } + { + Concevoir un cpu pour PFC : + + ouverte, pérenne, paramétrable, performante. + + Applications cibles : cryptographique. + } + +\subsection{Architecture Ouverte} +\slidetitle{Architecture Ouverte} + { + \begin{itemize} + \item Instruction Set Architecture gratuite. + %\item Présence d'une communauté autour de l'architecture logicielle. + \item Chaîne de compilation disponible et ouverte. + \item Modèle disponible : + \begin{itemize} + \item Modèle systemC-CABA + \item Modèle VHDL-RTL + \end{itemize} + \end{itemize} + } + { + Chaîne de compilation $\Rightarrow$ présence d'une communauté, espère une pérennité des logicielles. + + VHDL = FPGA + + SystemC = dévellopement + } + +\subsection{Architecture Pérenne} +\slidetitle{Architecture Pérenne} + { + \begin{itemize} + \item Instruction Set Architecture gratuite. + %\item Présence d'une communauté autour de l'architecture logicielle. + \item Chaîne de compilation disponible et ouverte. + \item Technologie cible flexible : FPGA. + \end{itemize} + } + { + ISA et Modèle disponible = implémentation possible. + } + +\subsection{Architecture Paramétrable} +\slidetitle{Architecture Paramétrable} + { + S'adapter aux critères de l'application : + \begin{itemize} + \item Performance + \item Surface + \item Consommation + \item Temps réel + \item \dots + \end{itemize} + + Pas un processeur mais plusieurs processeurs.\\ + \begin{itemize} + \item[$\Rightarrow$] Générateur d'architecture. + \item[$\Rightarrow$] Technologie cible : FPGA. + \end{itemize} + } + { + Aucune connaissance à priori des besoins des applications. Peuvent avoir des critères variés ... + + Pas 1CPU mais plusieurs CPU = ASIC trop onéreux + } + +\subsection{Architecture Performante} +\slidetitle{Architecture Performante} + { + \begin{center} + {\it Exécution de plusieurs instructions simultanément} + \end{center} + + Exploitation de toutes les formes de parallélisme. + + \begin{description} + \item[ILP :] Instruction Level Parallelism + \item[TLP :] Thread Level Parallelism + \item[DLP :] Data Level Parallelism + \end{description} + } + { + } + +%\subsubsection{ILP} +\slidetitle{Instruction Level Paralelism} + { + \begin{center} + {\it Exécution simultanée de plusieurs instructions provenant d'un même flux.} + \end{center} + \printgraph{GENERAL_ILP}{1 } + } + { + } +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Exploitation implicite du point de vue logicielle. +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Coût quadratique du contrôle. +% \end{itemize} +% \end{description} +% } +% { +% } + + +%\subsubsection{TLP} +\slidetitle{Thread Level Paralelism} + { + \begin{center} + {\it Exécution simultanée de plusieurs instructions provenant de différents flux.} + \end{center} + + \printgraph{GENERAL_TLP}{1 } + } + { + } + +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Implantation très simple : duplication des coeurs +% \item Ressources dédiés aux threads exécutés sur le coeur +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Il doit avoir plus de thread que de coeurs afin d'éviter l'oisiveté des coeurs +% \end{itemize} +% \end{description} +% } +% { +% } +% +%\slidetitle{TLP - Simulatenous Multi Threading (SMT)} +% { +% \printgraph{GENERAL_TLP-SMT}{1 } +% } +% { +% } +% +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Implantation très simple et peu coûteuse en surface. +% \item Meilleur exploitation des ressources +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Dimensionner le nombre de threads proportionnellement à l'ILP exploitable. +% \end{itemize} +% \end{description} +% } +% { +% } + +%\subsubsection{DLP} +\slidetitle{Data Level Paralelism} + { + \begin{center} + {\it Exécution d'instructions avec plusieurs données. (SIMD)} + \end{center} + + \printgraph{GENERAL_DLP}{1 } + } + { + Matrice 3x3 + 10 + } +%\slide +% { +% \begin{description} +% \item[Avantages :]~ +% \begin{itemize} +% \item Une instruction SIMD est équivalente à beaucoup d'instructions SISD. +% \end{itemize} +% \item[Inconvénients :]~ +% \begin{itemize} +% \item Pas adapter pour les applications qui n'exploite pas le DLP. +% \item Exploitation explicite par le programmeur. +% \end{itemize} +% \end{description} +% } +% { +% } +% + +\slidetitle{Implémentation matérielle} + { + \printgraph{GENERAL_hardware}{.98} + } + { + Streaming SIMD Extensions, généralement abrégé SSE, est un jeu de 70 instructions supplémentaires pour microprocesseurs x86, apparu sur le Pentium III. Le fonctionnement est de type SIMD. + + + AltiVec est un ensemble d'instructions SIMD d'opérations en virgule flottante conçu par, et propriété de, Apple, IBM et Motorola (l'AIM alliance), et mis en application sur des versions du PowerPC telle le G4 de Motorola et le G5 d'IBM. + } + +\slide + { + \begin{description} + \item[ILP] + \begin{itemize} + \item Super Scalaire\\ + \item \sout{VLIW} + \begin{itemize} + \item[$\Rightarrow$] Compilateur spécialisé. + \item[$\Rightarrow$] Pas scalable + \end{itemize} + \end{itemize} + \item[TLP] + \begin{itemize} + \item CMP + \begin{itemize} + \item[$\Rightarrow$] Scalable mais sous utilisation des ressources. + \end{itemize} + \item SMT + \begin{itemize} + \item[$\Rightarrow$] Utilisation optimale des ressources mais peu scalable. + \end{itemize} + \item Mixte + \end{itemize} + \item[DLP] + \begin{itemize} + \item Extension SIMD\\ + \end{itemize} + \end{description} + } + { + Mixte : tirer partie du CMP et SMT + } + +\section{État actuel} +\ContentsCurrent + +\slidetitle{Processeurs libres existants} + { + \begin{tabular}{l|ccccc} + + {\it Processeur} & {\it Date} & {\it ISA} & \multicolumn{2}{c}{{\it Support}} \\ + & & & {\it ASIC} & {\it FPGA} \\ + + \hline + OpenRISC 1200 & 2001 & or1000-ORBIS32 & X & X\\ %&Mono-core, Scalaire 5 étages, 32 bits\\ + LEON2 & 2003 & SPARC-V8 & X & X\\ %&Mono-core, Scalaire 5 étages, 32 bits\\ + LEON3 & 2005 & SPARC-V8e & X & X\\ %&Mono-core, Scalaire 7 étages, 32 bits\\ + OpenSparcT1 & 2005 & UltraSPARC-V9 & X & X\\ + MANIK & 2006 & MANIK & & X\\ + aeMB & 2007 & Xilinx EDK 3.2 & & X\\ %&Mono-core, Scalaire 3 étages, 32 bits\\ + OpenFIRE & 2007 & Xilinx EDK 6.3 & & X\\ %&Mono-core, Scalaire 3 étages, 32 bits\\ + OpenSparcS1 & 2007 & UltraSPARC-V9 & X & X\\ + OpenSparcT2 & 2007 & UltraSPARC-V9 & X & X\\ + \end{tabular} + } + { + Xilinx EDK 3.2 : 2003 + + Xilinx EDK 6.3 : 2004 + + \begin{tabular}{l|cccc} + + {\it Processeur} & FPGA & taille & freq (Mhz) & remarque\\ + + \hline + OpenRISC 1200 & statix 2 & 3000 & 33 & sans cache\\ + LEON2 & virtex 2 & 5000 + RAM & 80 & \\ + LEON3 & ? & 3500 & 125 & \\ + MANIK & & & & \\ + aeMB & & & & \\ + OpenFIRE & virtex 2 & 641 & 100\\ + \end{tabular} + + + Xilinx XC4VLX200 SPARC FPU CCX + LUTs 134,973 13,863 25,090 + + + With FPGA\_SYN, FPGA\_SYN\_1THREAD, and FPGA\_SYN\_NO\_SPU options: + Xilinx XC4VFX100 SPARC FPU CCX + LUTs 40,613 9,398 26,051 + + + + With FPGA\_SYN and FPGA\_SYN\_NO\_SPU options (4 threaded core): + Xilinx XC4VFX100 SPARC FPU CCX + LUTs 68,476 9,398 26,051 + } + +\slidetitle{État actuel} + { + Il existe plusieurs processeurs libres, mais : + + \begin{itemize} + \item Aucun processeur n'exploite l'ILP. + \item Les paramètres concernent principalement le cache. + \item Seuls les modèles de l'OpenSPARC exploitent le TLP. + \end{itemize} + } + { + } + +%\slidetitle{Fonction de coûts} +% { +% Comparaison de deux instances du générateur : +% +% \begin{itemize} +% \item Soit : obtenir le meilleur compromis Performance / Complexité. +% \begin{itemize} +% \item Performance : nombre de cycles nécessaire pour exécuter les Benchmarks. +% \item Complexité : surface occupée du FPGA. +% \end{itemize} +% \item Soit : obtenir le meilleur partage des ressources entre les contextes matériels. (Gain Performance / Coût surface). +% \begin{itemize} +% \item Gain en performance : rapport entre la performance MT sur la performance ST. +% \item Coût en surface : rapport entre la surface MT sur la surface ST. +% \end{itemize} +% \end{itemize} +% } +% { +% benchmark : SPECINT2k, Dhrystone +% +% +% } + +\section{Morpheo} +\ContentsCurrent + +\subsection{Paramètres} +\slidetitle{Paramètres} + { + 3 types : + \begin{description} + \item [Global] + \begin{itemize} + \item Occurrence de chaque entité %[1:8] + \item Nombre d'instructions pour chaque entité %[1:8] + \end{itemize} + \item [Local] + \begin{itemize} + \item Présence/Absence du réseau de bypass + \item Nombre de registres physiques %[32:512] + \item Nombre de ports du banc de registres %[2:16] + \item Taille des files d'attente (fetch\_queue, \dots) %[2:8] + \item Taille des structures internes (BTB, RAS, \dots) + \item Type et taille du prédicteur de branchement + \item Type des unités d'exécution + \end{itemize} + \item [Routage] + \begin{itemize} + \item Entre les différentes entités + \end{itemize} + \end{description} + } + { + } + +\subsection{Architecture interne} +\slidetitle{Architecture interne} + { + \printgraph{MORPHEO_micro_architecture-overview}{0.48} + } + { + 3 grandes parties : + \begin{description} + \item[Front end :] Amène des paquets d'instructions en séquence, et les décodes. Calcules les adresses suivantes (spéculation) et maintiens l'état des threads (idle, wait, run ...) + \item[Out Of Order Engine :] Renomme les registres (annulations des dépendances RAW, WAW et WAR). Re Order Buffer : mettre à jour l'état du contexte dans l'ordre d'arriver des threads. + \item[Execution Loop :] Boucle ``Read, execute, Write''. Ainsi que les bypass. Instructions peuvent ce lancer dans le désordres. + \end{description} + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex01}{0.48} + } + { + Hypothèse de départ + + SMT 2 + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex02}{0.48} + } + { + contexte x4 prédicteur dédié + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex03}{0.48} + } + { + Select ... + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex04}{0.48} + } + { + possibilité de CMP + } + + +%\slidetitle{Micro Architecture : Front end} +% { +% \printgraph{MORPHEO_micro_architecture-front_end}{0.7} +% } +% { +% } +% +%\slidetitle{Micro Architecture : Out Of Order Engine} +% { +% \printgraph{MORPHEO_micro_architecture-out_of_order_engine}{0.7} +% } +% { +% } +% +%\slidetitle{Micro Architecture : Execution Loop} +% { +% \printgraph{MORPHEO_micro_architecture-execute_loop}{0.7} +% } +% { +% } +% +\section{Méthodologie} +\ContentsCurrent + +\subsection{Service offert} +\slidetitle{Service offert} + { + \printgraph{MORPHEO_service}{0.75} + } + { + } + +\subsection{Méthodologie pour le modèle systemC/CABA} +\slidetitle{Structure du modèle systemC/CABA} + { + Deux types de composants : + \begin{description} + \item[Comportementale : ]~\\ + \begin{itemize} + \item 0-1 Fonction de Transition + \item 0-1 Fonction de Moore + \item 0-N Fonction de Mealy + \end{itemize} + \item[Structurelle : ] Contient des instances de composants comportementale et/ou structuelle. + \end{description} + + Encapsulation des interfaces de chaque composant ainsi que les instanciations. + } + { + } + + +\slide + { + Pour chaque composant du modèle + \begin{itemize} + \item<1->{\bf Construction :}~\\ + \begin{itemize} + \item Vérification des paramètres + \item Génération du modèle VHDL + \item Création des compteurs d'activités + \end{itemize} + \item<2-> {\bf Run-time :} A chaque cycle~\\ + \begin{itemize} + \item Evaluation des compteurs d'activités + \item Enregistrement de l'état des interfaces + \end{itemize} + \item<3-> {\bf Destruction :}~\\ + \begin{itemize} + \item Sauvegardes des compteurs d'activités dans un fichier au format XML + \item Mise en forme des activités sur les interfaces afin de générer un test bench pour le modèle VHDL + \end{itemize} + \end{itemize} + + } + { + + } + +%\subsection{Validation du modèle systemC/CABA} +% +%\slidetitle{Environnement de simulation} +% { +% \begin{itemize} +% \item Benchmark SPECINT2k. +% \begin{tabular}{ll} +% 164.gzip & Compression. \\ +% 175.vpr & Placement et routage de circuit FPGA. \\ +% 181.mcf & Optimisation combinatoire. \\ +% 255.vortex & Object-oriented Database. \\ +% 256.bzip2 & Compression. \\ +% 300.twolf & Simulateur de placement et de routage.\\ +% \end{tabular} +% \item Appel système : librairie {\it newlib}. +% \item Plate-forme matérielle ``custom'' +% \begin{itemize} +% \item Gestion de l'endienness. +% \item Pont entre la simulation et le système hôte. +% \end{itemize} +% \end{itemize} +% } +% { +% sim2os : +% \begin{itemize} +% \item SERVICE\_OPEN +% \item SERVICE\_CLOSE +% \item SERVICE\_READ +% \item SERVICE\_WRITE +% \item SERVICE\_TIME +% \item SERVICE\_CLOCK +% \item SERVICE\_LSEEK +% \end{itemize} +% } + +%\slidetitle{Hypothèse de travail} +% { +% Architecture de références +% \begin{itemize} +% \item 4 Threads +% \item 8 Unités d'exécutions +% \item 8 Instructions lancées par cycle +% \end{itemize} +% +% Variation de l'architecture +% \begin{itemize} +% \item Nombre de cache de premier niveau +% \item Nombre d'unité de lancement (Front\_End et OoO\_Engine) +% \item Nombre de contexte matériel +% \item Partage des unités fonctionnelles +% \end{itemize} +% } +% { +% } +% +%\slidetitle{Résultats} +% { +% \begin{center} +% Variation du partage des ressources entre les contextes matérielles. +% \end{center} +% %Rapport entre la performance MT sur la performance ST. +% +% \printgraph{simulation_performance}{0.7} +% } +% { +% DIRE : ST / MT. +% +% MT = exécution parallèle des benchmarks +% +% ST = exécution séquentielle des benchmarks +% +% +% ordonnée : IPC +% +% abscisse : degré de partage +% } +% +%\slide +% { +% %Rapport entre la performance MT sur la performance ST. +% +% \printgraph{simulation_surface}{0.7} +% } +% { +% } + +\subsection{Méthodologie pour le modèle VHDL/RTL} + +\slidetitle{Passage du modèle systemC au modèle VHDL} + { + \begin{description} + \item [Composants structurelles :]~\\ + \begin{itemize} + \item Générés automatiquement. + \end{itemize} + \item [Composants comportementales : ]~\\ + \begin{itemize} + \item En tête et interfaces sont générés automatiquement. + \item Reste le corps du composant à écrire. + \end{itemize} + \item [Tests :]~\\ + \begin{itemize} + \item Générés lors de la simulation systemC. + \end{itemize} + \end{description} + } + { + } + +\slide%title{Méthodologie pour l'écriture du générateur VHDL} + { + \begin{minipage}{0.54\textwidth} + \printgraph{VHDL_methodologie}{0.65} + \end{minipage} + \begin{minipage}{0.44\textwidth} + \begin{itemize} + \item Simulation systemC :\\{\it SystemCass } + \item Simulation VHDL :\\{\it Modelsim } + \item Synthèse FPGA :\\{\it Xilinx ISE } + \item FPGA cible :\\{\it Virtex5LX 330} + \end{itemize} + \end{minipage} + } + { + FPGA : virtex5LX 330 + } + +%\slidetitle{Exemple : Banc de registres 512x32 bits} +% { +% \printgraph{synthese_FPGA-registerfile}{0.7} +% } +% { +% } +% +%\slidetitle{Planning} +% { +% \begin{itemize} +% \item Optimisation du modèle SytemC/CABA +% \item Écriture du générateur de VHDL/RTL +% \item Réalisation d'un démonstrateur : +% \begin{itemize} +% \item synthèse sur un FPGA d'une instance du générateur. +% \item exécution d'une application de test +% \end{itemize} +% \end{itemize} +% } +% { +% } + + +\slidetitle{Conclusion} + { + \begin{itemize} + \item Définition d'un processeur ouvert, haute performance, paramétrable et pérenne. + \item Disposer d'un outil d'aide à l'exploration architecturale + \end{itemize} + } + { + } Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Include/doc-style.sty (revision 88) @@ -14,5 +14,5 @@ \usepackage[latin1]{inputenc} % Pour utiliser les caractères accentués dans votre texte \usepackage{openbib} -\usepackage[draft]{fixme} +%\usepackage[draft]{fixme} \bibliographystyle{plain} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.lang =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.lang (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.lang (revision 88) @@ -0,0 +1,1 @@ +en Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.sty (revision 88) @@ -0,0 +1,14 @@ +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{MORPHEO\newline Microarchitecture Specification} + +\institute{Equipe ALSOC - Département SOC - Laboratoire d'informatique de Paris VI - France} + +\author{Mathieu Rosière\newline + encadrement :\newline + Nathalie Drach-Temam\newline + Jean-Lou Desbarbieux\newline + Franck Wajsbürt} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.tex (revision 88) @@ -0,0 +1,6 @@ +%\documentclass{article} +\documentclass{beamer} + +\usepackage{beamerthemetree} + +%\setbeameroption{show notes on second screen} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.type =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.type (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation-morpheo-microarchitecture.type (revision 88) @@ -0,0 +1,1 @@ +ppt Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.lang =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.lang (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.lang (revision 88) @@ -0,0 +1,1 @@ +fr Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.sty (revision 88) @@ -0,0 +1,14 @@ +\def\review{2007/09/28} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{MORPHEO :\newline Processeur ouvert, haute performance, paramétrable et pérenne pour plate-forme de confiance.} + +\institute{Département SOC - Laboratoire d'informatique de Paris VI - France} + +\author{Mathieu Rosière\newline + encadrement :\newline + Nathalie Drach-Temam\newline + Jean-Lou Desbarbieux\newline + Franck Wajsbürt} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.tex (revision 88) @@ -0,0 +1,3 @@ +%\documentclass[10pt,a4paper,onecolumn]{article} +\documentclass{beamer} +\usepackage{beamerthemetree} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.type =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.type (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Info/presentation_bull.type (revision 88) @@ -0,0 +1,1 @@ +ppt Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Makefile (revision 88) @@ -32,5 +32,4 @@ DIR_SCHEMA_PNG = Schema_png DIR_TEX = Source -DIR_LINK = Link #-------------------------------------------------------------------------------- @@ -103,5 +102,4 @@ $(DVIPS) -o $@ $<; -#$(DIR_LINK)/%/* %.dvi : $(DIR_TEX)/%.tex @\ @@ -170,7 +168,4 @@ $(MKDIR) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG); \ \ - $(ECHO) "Create link : $(DIR_LINK)/$$FILENAME-$(DEFAULT_LANG)"; \ - $(LINK_SYMBOLIC) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG) $(DIR_LINK)/$$FILENAME-$(DEFAULT_LANG); \ - \ $(ECHO) "Create file : $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex"; \ $(TOUCH) $(DIR_DOCUMENTS)/$$FILENAME/$(DEFAULT_LANG)/root.tex @@ -224,7 +219,5 @@ \ $(ECHO) "Delete directory : $(DIR_DOCUMENTS)/$$FILENAME"; \ - $(RM) $(DIR_DOCUMENTS)/$$FILENAME; \ - $(ECHO) "Delete link : $(DIR_DOCUMENTS)/$$FILENAME"; \ - $(RM) $(DIR_LINK)/$$FILENAME-*; + $(RM) $(DIR_DOCUMENTS)/$$FILENAME; rename : @@ -282,6 +275,5 @@ \ $(ECHO) "Rename directory : $(DIR_DOCUMENTS)/$$FILENAME_SRC"; \ - $(MV) $(DIR_DOCUMENTS)/$$FILENAME_SRC $(DIR_DOCUMENTS)/$$FILENAME_DEST; \ - $(ECHO) "Rename link : manually please"; + $(MV) $(DIR_DOCUMENTS)/$$FILENAME_SRC $(DIR_DOCUMENTS)/$$FILENAME_DEST; Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex01.fig (revision 88) @@ -12,10 +12,4 @@ 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 --6 -6 4770 3240 5490 3690 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 -4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 -4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 -6 6 5850 3690 6570 4140 @@ -40,9 +34,4 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 -6 -6 6570 3015 7290 3465 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 -4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 --6 6 3825 3060 4635 3510 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 @@ -60,4 +49,10 @@ 4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 -6 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 @@ -168,4 +163,6 @@ 3 0 1.00 60.00 120.00 3690 4050 4770 4050 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 @@ -178,2 +175,3 @@ 4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex02.fig (revision 88) @@ -29,9 +29,4 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 -6 -6 6570 3015 7290 3465 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 -4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 --6 6 4770 3285 5490 3735 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 @@ -39,25 +34,25 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3555 decod\001 -6 +6 3825 2655 4635 3105 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3105 3870 3105 3870 2655 4590 2655 4590 3105 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\001 +-6 +6 2970 3285 3690 3735 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 3735 2970 3735 2970 3285 3690 3285 3690 3735 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 6 4770 2835 5490 3285 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5490 3285 4770 3285 4770 2835 5490 2835 5490 3285 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3015 context\001 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3195 state\001 --6 -6 3825 2655 4635 3105 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 4590 3105 3870 3105 3870 2655 4590 2655 4590 3105 -4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\001 --6 -6 2970 3285 3690 3735 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 3690 3735 2970 3735 2970 3285 3690 3285 3690 3735 -4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\001 --6 -6 1890 3690 2610 4140 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 -4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 -4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 -6 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 @@ -204,11 +199,13 @@ 1710 5535 12510 5535 12510 2295 1710 2295 1710 5535 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5490 4545 4770 4545 4770 4995 5490 4995 5490 4545 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095 4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 @@ -226,2 +223,3 @@ 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4860 context\001 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4995 predictor\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex03.fig (revision 88) @@ -128,5 +128,4 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 7695 dcache\001 -6 -6 1890 3600 7650 6660 6 5850 4995 6570 5445 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 @@ -134,9 +133,4 @@ 4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 5265 rename\001 -6 -6 6570 4320 7290 4770 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 7290 4770 6570 4770 6570 4320 7290 4320 7290 4770 -4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 4590 commit\001 --6 6 4770 4590 5490 5040 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 @@ -144,26 +138,50 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 4860 decod\001 -6 +6 3825 3960 4635 4410 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 4410 3870 4410 3870 3960 4590 3960 4590 4410 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4230 predictor\001 +-6 +6 2970 4590 3690 5040 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 5040 2970 5040 2970 4590 3690 4590 3690 5040 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4860 fetch\001 +-6 +6 1890 4995 2610 5445 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 5445 1890 5445 1890 4995 2610 4995 2610 5445 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 5355 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 5175 icache\001 +-6 6 4770 4140 5490 4590 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5490 4590 4770 4590 4770 4140 5490 4140 5490 4590 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4320 context\001 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 4500 state\001 -6 -6 3825 3960 4635 4410 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 4590 4410 3870 4410 3870 3960 4590 3960 4590 4410 -4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4230 predictor\001 --6 -6 2970 4590 3690 5040 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 3690 5040 2970 5040 2970 4590 3690 4590 3690 5040 -4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4860 fetch\001 --6 -6 1890 4995 2610 5445 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 2610 5445 1890 5445 1890 4995 2610 4995 2610 5445 -4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 5355 port\001 -4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 5175 icache\001 --6 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 7020 10170 7515 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6525 8370 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 6525 12150 6525 12150 7200 8010 7200 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 @@ -256,11 +274,16 @@ 6930 4320 6930 4095 6030 4095 5130 3645 5130 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 5400 4770 5400 4770 5850 5490 5850 5490 5400 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6030 3870 6030 3870 6480 4590 6480 4590 6030 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 5400 2970 5400 2970 5850 3690 5850 3690 5400 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 4770 6570 4770 6570 4320 7290 4320 7290 4770 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5490 5850 4770 5850 4770 6300 5490 6300 5490 5850 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 5490 5400 4770 5400 4770 5850 5490 5850 5490 5400 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 4590 6030 3870 6030 3870 6480 4590 6480 4590 6030 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 3690 5400 2970 5400 2970 5850 3690 5850 3690 5400 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 3825 Out Of Order Engine\001 4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 3735 Front End\001 @@ -270,30 +293,3 @@ 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 6165 context\001 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 6300 predictor\001 --6 -2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 8010 3915 8370 3915 -2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 - 3 0 1.00 60.00 120.00 - 11970 3915 12150 3915 12150 3240 8010 3240 -2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 - 3 0 1.00 60.00 120.00 - 3 0 1.00 60.00 120.00 - 10170 2925 10170 3420 -2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 - 3 0 1.00 60.00 120.00 - 3 0 1.00 60.00 120.00 - 10170 7020 10170 7515 -2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 - 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 -2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 - 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 -2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 8010 6525 8370 6525 -2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 - 3 0 1.00 60.00 120.00 - 11970 6525 12150 6525 12150 7200 8010 7200 -4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 -4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 -4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 4590 commit\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-ex04.fig (revision 88) @@ -157,5 +157,10 @@ 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 -6 -6 2790 2880 5580 4320 +6 1890 6300 2610 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001 +-6 6 4770 3690 5490 4140 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 @@ -163,48 +168,19 @@ 4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 -6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +-6 6 4770 3240 5490 3690 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 --6 -6 3825 3060 4635 3510 -2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 - 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 -4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 --6 -6 2970 3690 3690 4140 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 -4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 --6 -2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 - 3 0 1.00 60.00 120.00 - 3 0 1.00 60.00 120.00 - 4410 3510 4410 3870 4770 3870 -2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 - 3 0 1.00 60.00 120.00 - 3 0 1.00 60.00 120.00 - 4050 3510 4050 3870 3690 3870 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 3780 3960 4770 3960 -2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 - 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 -2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 - 3 0 1.00 60.00 120.00 - 3 0 1.00 60.00 120.00 - 3960 3510 3960 3780 3780 3780 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 3690 4050 4770 4050 -2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 - 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 --6 -6 1890 6300 2610 6750 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 -4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001 -4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001 -6 2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 @@ -292,6 +268,4 @@ 3690 6390 4770 6390 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 5490 6300 4770 6300 4770 6750 5490 6750 5490 6300 2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 @@ -314,4 +288,28 @@ 2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 6570 6300 5850 6300 5850 6750 6570 6750 6570 6300 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 @@ -324,4 +322,4 @@ 4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 7065 context\001 4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 7200 predictor\001 -4 1 0 50 -1 -1 12 6.2832 4 135 555 6930 7245 commit\001 -4 1 0 50 -1 -1 12 6.2832 4 90 555 6210 6525 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 7245 commit\001 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 6525 rename\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/MORPHEO_micro_architecture-overview.fig (revision 88) @@ -1,3 +1,3 @@ -#FIG 3.2 Produced by xfig version 3.2.5 +#FIG 3.2 Landscape Center @@ -8,41 +8,30 @@ -2 1200 2 -6 4770 3240 5490 3690 -2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 - 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 -4 1 0 50 -1 -1 12 0.0000 4 120 645 5130 3420 context\001 -4 1 0 50 -1 -1 12 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Core\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +4 1 0 50 -1 0 12 0.0000 4 90 555 6210 3960 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +4 1 0 50 -1 0 12 0.0000 4 135 450 5130 3960 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Source/Schema/VHDL_methodologie.fig (revision 88) @@ -8,14 +8,21 @@ -2 1200 2 -6 -1425 -600 2850 4050 +6 900 -1500 2100 -750 +6 900 -1500 2100 -1200 +2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 + 2100 -1200 900 -1200 900 -1500 2100 -1500 2100 -1200 +4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -1350 D\351but\001 +-6 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -1200 1500 -750 +-6 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 -750 750 600 225 -750 750 -150 525 +1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850 +1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 375 600 225 1500 375 2100 150 1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950 -1 1 0 1 0 6 51 -1 20 0.000 1 0.0000 1500 3075 600 225 1500 3075 2100 2850 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 - 1650 600 2250 1050 -2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 1350 600 1050 1050 + 1500 825 2250 1050 2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 3 0 1.00 60.00 120.00 @@ -38,35 +45,45 @@ 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 4 3 0 1.00 60.00 120.00 - -750 525 -750 -75 1200 -75 1200 150 + -750 525 -750 -975 1200 -975 1200 -750 2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 3 0 1.00 60.00 120.00 900 3075 -750 3075 -750 975 -2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 - 3 0 1.00 60.00 120.00 - 1500 -300 1500 150 -2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 - 2100 -300 900 -300 900 -600 2100 -600 2100 -300 2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 2100 4050 900 4050 900 3750 2100 3750 2100 4050 -2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 - 2100 600 900 600 900 150 2100 150 2100 600 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 1350 1500 150 1500 150 1050 1350 1050 1350 1500 2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 2850 1500 1650 1500 1650 1050 2850 1050 2850 1500 -4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 -4 1 0 50 -1 2 8 0.0000 0 90 990 2250 1275 TestBench VHDL\001 -4 1 0 50 -1 2 8 0.0000 0 105 1005 750 1275 G\351n\351rateur VHDL\001 -4 1 0 50 -1 2 8 0.0000 0 105 465 1500 375 SystemC\001 -4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 -4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 -4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -450 D\351but\001 -4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 -4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 --6 +2 1 0 1 0 7 50 -1 20 0.000 0 0 7 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 825 1050 1050 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 0 0 2 + 1500 600 1500 825 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 2100 375 2250 375 2250 -900 1800 -900 1800 -750 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -300 1500 150 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 2100 -300 900 -300 900 -750 2100 -750 2100 -300 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 3450 ok\001 4 0 0 51 -1 0 8 0.0000 0 75 315 -75 675 locale\001 4 0 0 51 -1 0 8 0.0000 0 90 375 -675 450 globale\001 4 2 0 51 -1 0 8 0.0000 0 75 120 900 3000 ko\001 -4 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001 +4 1 0 50 -1 2 8 0.0000 0 90 1050 -750 675 Modification locale\001 +4 1 0 50 -1 2 8 0.0000 0 105 1035 -750 825 (micro architecture)\001 +4 1 0 50 -1 2 8 0.0000 0 135 810 1500 3075 Synth\350tisable ?\001 +4 1 0 50 -1 2 8 0.0000 0 90 195 1500 3900 Fin\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 750 ok\001 +4 1 0 50 -1 2 8 0.0000 0 75 240 1500 375 Test\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 2025 225 ko\001 4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001 +4 1 0 50 -1 2 8 0.0000 0 75 240 1500 2175 Test\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 825 2025 ko\001 +4 1 0 50 -1 2 8 0.0000 0 75 375 750 1425 VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 75 375 2250 1425 VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 90 615 2250 1200 TestBench \001 +4 1 0 50 -1 2 8 0.0000 0 105 465 1500 -375 SystemC\001 +4 1 0 50 -1 2 8 0.0000 0 105 450 750 1200 Mod\350le \001 +4 1 0 50 -1 2 8 0.0000 0 105 450 1500 -600 Mod\350le \001 Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 88) @@ -0,0 +1,181 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 88) @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 88) @@ -0,0 +1,151 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 88) @@ -0,0 +1,140 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 88) @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Makefile (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Makefile (revision 88) @@ -1,98 +1,58 @@ -include $(MORPHEO_TOPLEVEL)/Makefile.tools +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +#-----[ Variables ]---------------------------------------------------- +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- #-----[ Directory ]---------------------------------------------------- -DIR_LIB = Library -DIR_DOC = Documentation/Source +DIR_DOC = ./Documentation/Source +DIR_LOCALE = ./locale -#-----[ Options ]------------------------------------------------------ +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +#-----[ Rules ]-------------------------------------------------------- +#---------------------------------------------------------------------- +#---------------------------------------------------------------------- +.PHONY : all help lib translate clean clean_all -PREFIXE_PATH = "." -SUFFIXE_PATH = ".txt" +all : doc translate lib -#-----[ Rules ]-------------------------------------------------------- -.PHONY : all help - -all : help - -#~~~~~[ doc ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ doc : @\ - $(ECHO) "";\ - $(ECHO) "=====[ doc ]=====================================";\ - $(ECHO) "";\ - $(MAKE) -C $(DIR_DOC) view; + $(MAKE) -C $(DIR_DOC) doc; -#~~~~~[ path ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -path : +lib : Morpheo_library + +translate : @\ - $(ECHO) "";\ - $(ECHO) "=====[ path ]====================================";\ - $(ECHO) "";\ - $(ECHO) -n "+ ";\ - $(BASENAME) $(PWD);\ - $(ECHO) "| ";\ - $(ECHO) "|";\ - $(MAKE) path_rec TAB="| " DIR_PATH=.; + for i in $(DIR_LOCALE)/*/*/*.po; do \ + dir=$$($(DIRNAME) $$i); \ + file=$$($(BASENAME) $$i .po); \ + $(ECHO) "Translate : $$i"; \ + $(MSGFMT) $$i -o $$dir/$$file.mo; \ + done -path_rec : - @\ - for files in `$(LS) $(DIR_PATH)`; do \ - if $(TEST) -d $(DIR_PATH)/$$files; \ - then \ - $(ECHO) "$(TAB)+ $$files"; \ - \ - if test -f $(DIR_PATH)/$(PREFIXE_PATH)`$(BASENAME) $$files`$(SUFFIXE_PATH); \ - then \ - $(ECHO) "$(TAB)| <\c"; \ - $(CAT) $(DIR_PATH)/$(PREFIXE_PATH)`$(BASENAME) $$files`$(SUFFIXE_PATH); \ - $(ECHO) ">"; \ - else \ - $(ECHO) "$(TAB)| "; \ - fi; \ - $(ECHO) "$(TAB)|"; \ - \ - $(MAKE) path_rec TAB="$(TAB)| " DIR_PATH=$(DIR_PATH)/$$files; \ - fi; \ - done; - -#~~~~~[ Lib ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -lib : - @\ - $(ECHO) "";\ - $(ECHO) "=====[ lib ]=====================================";\ - $(ECHO) "";\ - $(ECHO) " Function unimplemented";\ - $(ECHO) ""; - -# @$(ECHO) " The library is generate into the directory : $(PWD)/$(DIR_LIB)" - -#~~~~~[ Maintenance ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#~~~~~[ Clean ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ clean : @\ - $(ECHO) "";\ - $(ECHO) "=====[ clean ]===================================";\ - $(ECHO) "";\ - $(ECHO) "Delete temporary files "$(PWD);\ - $(RM) *~; -# @$(MAKE) clean_rec DIR_CLEAN=. + $(RM) *~;\ + $(MAKE) -C $(DIR_DOC) clean; -#Clean recursive -#clean_rec : -# @$(ECHO) "Delete temporary files in directory $(DIR_CLEAN)" -# @$(RM) -f $(DIR_CLEAN)/*~ -# @ \ -# if $(TEST) -f $(DIR_CLEAN)/Makefile -a "$(DIR_CLEAN)" != "."; \ -# then \ -# ($(CD) $(DIR_CLEAN); $(MAKE) clean;) \ -# else \ -# for files in `$(LS) $(DIR_CLEAN)`; do \ -# if $(TEST) -d $(DIR_CLEAN)/$$files; \ -# then \ -# $(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files; \ -# fi; \ -# done; \ -# fi; + +clean_all : + @\ + $(RM) *~ $(DIR_LOCALE)/*/*/*.mo;\ + $(MAKE) -C $(DIR_DOC) clean_all;\ + $(MAKE) Morpheo_library_clean + #~~~~~[ Help ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -107,8 +67,10 @@ $(ECHO) " * all cf rule \"help\"";\ $(ECHO) " * clean Delete temporary files";\ + $(ECHO) " * clean_all Delete all generated files";\ $(ECHO) " * doc View documentation files";\ + $(ECHO) " * help Print this message";\ $(ECHO) " * lib Generate the library to include";\ - $(ECHO) " * help Print this message";\ - $(ECHO) " * path Print a little description of each directory";\ + $(ECHO) " * translate Generate the traduction";\ $(ECHO) ""; +include Makefile.deps Index: trunk/IPs/systemC/processor/Morpheo/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/Makefile.deps (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# + +#-----[ Test ]--------------------------------------------- + +# Test Environment variables +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif + +#-----[ Dependency ]--------------------------------------- + +DIR_MORPHEO = $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/ +include $(DIR_MORPHEO)/TopLevel/Makefile.deps + +#-----[ Variables ]---------------------------------------- + +MORPHEO_DIR = $(DIR_MORPHEO) +MORPHEO_INCDIR = -I$(MORPHEO_DIR) -I$(MORPHEO_DIR)/TopLevel/include +MORPHEO_LIBDIR = $(Morpheo_DIR_LIBRARY) +MORPHEO_LIBNAME = $(Morpheo_LIBRARY) -lm Index: trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Script/SelfTest.sh (revision 88) @@ -10,84 +10,102 @@ declare test_ok="Test OK"; declare tmp="${MORPHEO_HOME}/tmp/SelfTest"; -declare path="${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/Behavioural"; +declare path="${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/"; declare -a directory=( - "" - "Custom" - - "Generic/Counter" - "Generic/Queue_Control" - "Generic/Queue" - "Generic/RegisterFile/RegisterFile_Monolithic" - "Generic/RegisterFile/RegisterFile_Multi_Banked" - "Generic/RegisterFile" - "Generic/Select/Select_Priority_Fixed" - "Generic/Select" - "Generic/Shifter" - "Generic/Sort" - "Generic/Victim/Victim_Pseudo_LRU" - "Generic/Victim" - - "Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation" - "Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue" - "Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station" - "Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue" - "Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue" - "Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit" - "Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit" - "Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit" - "Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit" - "Core/Multi_Execute_loop/Execute_loop/Network" - "Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue" - "Core/Multi_Execute_loop/Execute_loop/Register_unit" -# "Core/Multi_Execute_loop/Execute_loop" -# "Core/Multi_Execute_loop" - - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_queue" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select" - "Core/Multi_OOO_Engine/OOO_Engine/Rename_unit" - "Core/Multi_OOO_Engine/OOO_Engine" - "Core/Multi_OOO_Engine" + "Common" + + "Behavioural" + "Behavioural/Configuration" + "Behavioural/Custom" + + "Behavioural/Generic/Counter" + "Behavioural/Generic/Priority" + "Behavioural/Generic/Queue_Control" + "Behavioural/Generic/Queue" + "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic" + "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked" + "Behavioural/Generic/RegisterFile" + "Behavioural/Generic/Select/Select_Priority_Fixed" + "Behavioural/Generic/Select" + "Behavioural/Generic/Shifter" + "Behavioural/Generic/Sort" + "Behavioural/Generic/Victim/Victim_Pseudo_LRU" + "Behavioural/Generic/Victim" + + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Execute_loop_Glue" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Network" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/Register_unit_Glue" + "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit" + "Behavioural/Core/Multi_Execute_loop/Execute_loop" + "Behavioural/Core/Multi_Execute_loop" + + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Dependency_checking_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Free_List_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_unit_Glue" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit" + "Behavioural/Core/Multi_OOO_Engine/OOO_Engine" + "Behavioural/Core/Multi_OOO_Engine" - "Core/Multi_Front_end/Front_end/Context_State" - "Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction" - "Core/Multi_Front_end/Front_end/Decod_unit/Decod" - "Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue" - "Core/Multi_Front_end/Front_end/Decod_unit" - "Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management" - "Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue" - "Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue" - "Core/Multi_Front_end/Front_end/Ifetch_unit" - "Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue" - "Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register" - "Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer" - "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue" - "Core/Multi_Front_end/Front_end/Prediction_unit/Direction" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor" -# "Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor" - "Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue" - "Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack" - "Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table" - "Core/Multi_Front_end/Front_end/Prediction_unit" - "Core/Multi_Front_end/Front_end" - "Core/Multi_Front_end" - + "Behavioural/Core/Multi_Front_end/Front_end/Context_State" + "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction" + "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod" + "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue" + "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit" + "Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue" + "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management" + "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue" + "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_unit_Glue" + "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Direction_Glue" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Meta_Predictor_Glue" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Two_Level_Branch_Predictor_Glue" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor/Two_Level_Branch_Predictor" +# "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Direction/Meta_Predictor" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table" + "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit" + "Behavioural/Core/Multi_Front_end/Front_end" + "Behavioural/Core/Multi_Front_end" + + "Behavioural/Core/Icache_Access" + "Behavioural/Core/Dcache_Access" + + "Behavioural/Core/Core_Glue" + "Behavioural/Core" + + "TopLevel" ); @@ -126,5 +144,5 @@ if test ! -d ${tmp}; then - mkdir ${tmp}; + mkdir -p ${tmp}; fi; @@ -212,15 +230,17 @@ cd ${path}/${i}; - make clean; - dir="SelfTest"; - - if test -d ${dir}; then - cd ${dir}; + + if test -f "Makefile"; then make clean; - else - echo "${component} have not SelfTest directory."; - fi; - cd ${pwd}; - + dir="SelfTest"; + + if test -d ${dir}; then + cd ${dir}; + make clean; + else + echo "${component} have not SelfTest directory."; + fi; + cd ${pwd}; + fi; done; ;; Index: trunk/IPs/systemC/processor/Morpheo/Script/first_run.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/first_run.sh (revision 87) +++ (revision ) @@ -1,30 +1,0 @@ -#!/bin/bash - -#----------------------------------------------------------- -# $Id$ -#----------------------------------------------------------- - -#-----[ usage ]--------------------------------------------- -function usage () -{ - echo "Usage : ${0}"; - echo "Note :"; - echo " * Morpheo's environnement must be positionned."; - exit; -} - -#-----[ main ]---------------------------------------------- -function main () -{ - if test ${#} -ne 0 -o -z ${MORPHEO_HOME}; then - usage ${*}; - fi; - - # create directories - mkdir ${MORPHEO_HOME}; - mkdir ${MORPHEO_HOME}/lock; # lock directory - mkdir ${MORPHEO_HOME}/tmp; # temporary directory -} - -#-----[ Body ]---------------------------------------------- -main ${*} Index: trunk/IPs/systemC/processor/Morpheo/Script/version.sh =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Script/version.sh (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/Script/version.sh (revision 88) @@ -7,4 +7,5 @@ file_sed_src="${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h.sed"; file_sed_dest="${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h"; +file_sed_script="/tmp/file_sed_script"; #-----[ usage ]--------------------------------------------- @@ -47,7 +48,17 @@ # +1 because is the next revision revision=$(($(export LC_ALL=C; svnversion | tr -d [:alpha:] | cut -d : -f 2) + 1)); - - cat ${file_sed_src} |sed s/"@REVISION"/"${revision}"/ &> ${file_sed_dest}; - + date_day=$(date +%d); + date_month=$(date +%m); + date_year=$(date +%Y); + + echo "s/\"@REVISION\"/\"${revision}\"/" > ${file_sed_script}; + echo "s/\"@DATE_DAY\"/\"${date_day}\"/" >> ${file_sed_script}; + echo "s/\"@DATE_MONTH\"/\"${date_month}\"/" >> ${file_sed_script}; + echo "s/\"@DATE_YEAR\"/\"${date_year}\"/" >> ${file_sed_script}; + + cat ${file_sed_src} |sed -f ${file_sed_script} &> ${file_sed_dest}; + + rm ${file_sed_script}; + svn commit; Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile (revision 88) @@ -0,0 +1,24 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ./ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ Library ]------------------------------------------ +LIBRARY = $(DIR_LIB)/libMorpheo.a + + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_component + +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Component Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.defs =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.defs (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.defs (revision 88) @@ -0,0 +1,11 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT_MORPHEO = .. +DIR_MORPHEO = $(DIR_COMPONENT)/$(DIR_COMPONENT_MORPHEO) Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.deps (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/Makefile.deps (revision 88) @@ -0,0 +1,47 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# +# DIR_MORPHEO must be defined + +Morpheo = yes + +ifndef Configuration +include $(DIR_MORPHEO)/Behavioural/Configuration/Makefile.deps +endif +ifndef Core +include $(DIR_MORPHEO)/Behavioural/Core/Makefile.deps +endif + +#-----[ Directory ]---------------------------------------- + +Morpheo_DIR = $(DIR_MORPHEO)/TopLevel + +#-----[ Library ]------------------------------------------ + +Morpheo_LIBRARY = -lMorpheo \ + $(Configuration_LIBRARY) \ + $(Core_LIBRARY) + +Morpheo_DIR_LIBRARY = -L$(Morpheo_DIR)/lib \ + $(Configuration_DIR_LIBRARY) \ + $(Core_DIR_LIBRARY) + +#-----[ Rules ]-------------------------------------------- + +Morpheo_library : + @\ + $(MAKE) Configuration_library; \ + $(MAKE) Core_library; \ + $(MAKE) --directory=$(Morpheo_DIR) --makefile=Makefile; + +Morpheo_library_clean : + @\ + $(MAKE) Configuration_library_clean; \ + $(MAKE) Core_library_clean; \ + $(MAKE) --directory=$(Morpheo_DIR) --makefile=Makefile clean; + + Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/Makefile (revision 88) @@ -0,0 +1,34 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +LIBRARY = $(Morpheo_LIBRARY) + +DIR_LIBRARY = $(Morpheo_DIR_LIBRARY) + +#-----[ include ]------------------------------------------ + +all : + @$(MAKE) all_selftest + +library : Morpheo_library + +library_clean : Morpheo_library_clean + +local_clean : + @$(RM) data_in/*~ \ + data_out/* + +include $(DIR_COMPONENT)/Makefile.deps +include $(DIR_MORPHEO)/Behavioural/Makefile.flags +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Selftest +include $(DIR_MORPHEO)/Behavioural/Makefile.Synthesis Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/configuration/Morpheo-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/configuration/Morpheo-min.cfg (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/configuration/Morpheo-min.cfg (revision 88) @@ -0,0 +1,1 @@ +../../Files/Morpheo.sim ../../Files/Morpheo.gen ../../Files/Instance_min.cfg Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/include/test.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/include/test.h (revision 88) @@ -0,0 +1,33 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test "RegisterFile" + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#define NB_ITERATION 16 +#define CYCLE_MAX (1024*NB_ITERATION) + +#include "Common/include/Test.h" +#include "Common/include/Time.h" +#include "TopLevel/include/Morpheo.h" + +#include +#include +#include + +using namespace std; +using namespace morpheo; +using namespace morpheo::behavioural::custom; + +void test (string name, + std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + custom_information_t (*get_custom_information) (void) + ); Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/main.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/main.cpp (revision 88) @@ -0,0 +1,74 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/SelfTest/include/test.h" + +#define NB_PARAMS 3 + +void usage (int argc, char * argv[]) +{ + err (_(" %s name_instance list_params.\n"),argv[0]); + err (_("list_params is :\n")); + err (_(" * filename_simulator (string)\n")); + err (_(" * filename_generator (string)\n")); + err (_(" * filename_instance (string)\n")); + + exit (1); +} + +#ifndef SYSTEMC +int main (int argc, char * argv[]) +#else +int sc_main (int argc, char * argv[]) +#endif +{ + for (int32_t i=0; i(2+NB_PARAMS)) + usage (argc, argv); + + uint32_t x = 1; + + string name = argv[x++]; + string filename_simulator = argv[x++]; + string filename_generator = argv[x++]; + string filename_instance = argv[x++]; + + int _return = EXIT_SUCCESS; + try + { + test (name, + filename_simulator, + filename_generator, + filename_instance, + NULL +// &(morpheo::behavioural::custom::example_get_custom_information) + ); + } + catch (morpheo::ErrorMorpheo & error) + { + msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + try + { + if (_return == EXIT_SUCCESS) + TEST_OK("Morpheo : no error"); + else + TEST_KO("Morpheo : a lot of error"); + } + catch (morpheo::ErrorMorpheo & error) + { +// msg (_("<%s> :\n%s"),name.c_str(), error.what ()); + _return = EXIT_FAILURE; + } + + return (_return); +} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/test.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/src/test.cpp (revision 88) @@ -0,0 +1,215 @@ +/* + * $Id$ + * + * [ Description ] + * + * Test + */ + +#include "TopLevel/SelfTest/include/test.h" +#include "Behavioural/include/Allocation.h" + +void test (std::string name, + std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + custom_information_t (*get_custom_information) (void) + ) +{ + msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); + + if (setlocale (LC_ALL, "") == NULL) + msg(_("setlocale ko.\n")); + else + msg(_("setlocale ok : %s.\n"),setlocale (LC_ALL, "")); + + Morpheo * _Morpheo = new Morpheo + (name.c_str(), + filename_simulator, + filename_generator, + filename_instance , + get_custom_information + ); + +#ifdef SYSTEMC + if (1) + { + /********************************************************************* + * Déclarations des signaux + *********************************************************************/ + string rename; + + sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * in_NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_VAL ,"out_ICACHE_REQ_VAL ",Tcontrol_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_REQ_ACK ," in_ICACHE_REQ_ACK ",Tcontrol_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,"out_ICACHE_REQ_THREAD_ID ",Ticache_context_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,"out_ICACHE_REQ_PACKET_ID ",Ticache_packet_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,"out_ICACHE_REQ_ADDRESS ",Ticache_address_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,"out_ICACHE_REQ_TYPE ",Ticache_type_t ,_Morpheo->_nb_icache_port); + + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ," in_ICACHE_RSP_THREAD_ID ",Ticache_context_t ,_Morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Ticache_packet_t ,_Morpheo->_nb_icache_port); + ALLOC2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,_Morpheo->_nb_icache_port,_Morpheo->_icache_nb_instruction[it1]); + ALLOC1_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ,_Morpheo->_nb_icache_port); + + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,"out_DCACHE_REQ_THREAD_ID ",Tdcache_context_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,"out_DCACHE_REQ_PACKET_ID ",Tdcache_packet_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,"out_DCACHE_REQ_ADDRESS ",Tdcache_address_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,"out_DCACHE_REQ_WDATA ",Tdcache_data_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,"out_DCACHE_REQ_TYPE ",Tdcache_type_t ,_Morpheo->_nb_dcache_port); + + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_VAL ," in_DCACHE_RSP_VAL ",Tcontrol_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(out_DCACHE_RSP_ACK ,"out_DCACHE_RSP_ACK ",Tcontrol_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ," in_DCACHE_RSP_THREAD_ID ",Tdcache_context_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ," in_DCACHE_RSP_PACKET_ID ",Tdcache_packet_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_RDATA ," in_DCACHE_RSP_RDATA ",Tdcache_data_t ,_Morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL( in_DCACHE_RSP_ERROR ," in_DCACHE_RSP_ERROR ",Tdcache_error_t ,_Morpheo->_nb_dcache_port); + + ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_Morpheo->_nb_thread); + + /******************************************************** + * Instanciation + ********************************************************/ + + msg(_("<%s> : Instanciation of _Morpheo.\n"),name.c_str()); + + (*(_Morpheo->in_CLOCK)) (*(in_CLOCK)); + (*(_Morpheo->in_NRESET)) (*(in_NRESET)); + + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_REQ_VAL ,_Morpheo->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Morpheo, in_ICACHE_REQ_ACK ,_Morpheo->_nb_icache_port); + if (_Morpheo->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_REQ_THREAD_ID ,_Morpheo->_nb_icache_port); + if (_Morpheo->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_REQ_PACKET_ID ,_Morpheo->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_REQ_ADDRESS ,_Morpheo->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_REQ_TYPE ,_Morpheo->_nb_icache_port); + + INSTANCE1_SC_SIGNAL(_Morpheo, in_ICACHE_RSP_VAL ,_Morpheo->_nb_icache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_ICACHE_RSP_ACK ,_Morpheo->_nb_icache_port); + if (_Morpheo->_have_port_icache_thread_id) + INSTANCE1_SC_SIGNAL(_Morpheo, in_ICACHE_RSP_THREAD_ID ,_Morpheo->_nb_icache_port); + if (_Morpheo->_have_port_icache_packet_id) + INSTANCE1_SC_SIGNAL(_Morpheo, in_ICACHE_RSP_PACKET_ID ,_Morpheo->_nb_icache_port); + INSTANCE2_SC_SIGNAL(_Morpheo, in_ICACHE_RSP_INSTRUCTION ,_Morpheo->_nb_icache_port,_Morpheo->_icache_nb_instruction[it1]); + INSTANCE1_SC_SIGNAL(_Morpheo, in_ICACHE_RSP_ERROR ,_Morpheo->_nb_icache_port); + + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_VAL ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_REQ_ACK ,_Morpheo->_nb_dcache_port); + if (_Morpheo->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_THREAD_ID ,_Morpheo->_nb_dcache_port); + if (_Morpheo->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_PACKET_ID ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_ADDRESS ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_WDATA ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_REQ_TYPE ,_Morpheo->_nb_dcache_port); + + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_RSP_VAL ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo,out_DCACHE_RSP_ACK ,_Morpheo->_nb_dcache_port); + if (_Morpheo->_have_port_dcache_thread_id) + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_RSP_THREAD_ID ,_Morpheo->_nb_dcache_port); + if (_Morpheo->_have_port_dcache_packet_id) + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_RSP_PACKET_ID ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_RSP_RDATA ,_Morpheo->_nb_dcache_port); + INSTANCE1_SC_SIGNAL(_Morpheo, in_DCACHE_RSP_ERROR ,_Morpheo->_nb_dcache_port); + + INSTANCE1_SC_SIGNAL(_Morpheo, in_INTERRUPT_ENABLE ,_Morpheo->_nb_thread); + + msg(_("<%s> : Start Simulation ............\n"),name.c_str()); + + Time * _time = new Time(); + + /******************************************************** + * Simulation - Begin + ********************************************************/ + + // Initialisation + + const uint32_t seed = 0; +//const uint32_t seed = static_cast(time(NULL)); + + srand(seed); + + SC_START(0); + LABEL("Initialisation"); + + LABEL("Reset"); + in_NRESET->write(0); + SC_START(5); + in_NRESET->write(1); + + for (uint32_t i=0; i<_Morpheo->_nb_icache_port; ++i) + { + in_ICACHE_REQ_ACK [i]->write(0); + in_ICACHE_RSP_VAL [i]->write(0); + } + for (uint32_t i=0; i<_Morpheo->_nb_dcache_port; ++i) + { + in_DCACHE_REQ_ACK [i]->write(0); + in_DCACHE_RSP_VAL [i]->write(0); + } + for (uint32_t i=0; i<_Morpheo->_nb_thread; ++i) + in_INTERRUPT_ENABLE [i]->write(0); + + LABEL("Loop of Test"); + + for (uint32_t iteration=0; iteration : ............ Stop Simulation\n"),name.c_str()); + + delete in_CLOCK; + delete in_NRESET; + + DELETE1_SC_SIGNAL(out_ICACHE_REQ_VAL ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_REQ_ACK ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_ADDRESS ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_REQ_TYPE ,_Morpheo->_nb_icache_port); + + DELETE1_SC_SIGNAL( in_ICACHE_RSP_VAL ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(out_ICACHE_RSP_ACK ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_Morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL( in_ICACHE_RSP_ERROR ,_Morpheo->_nb_icache_port); + DELETE2_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_Morpheo->_nb_icache_port,_Morpheo->_icache_nb_instruction[it1]); + + DELETE1_SC_SIGNAL(out_DCACHE_REQ_VAL ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_REQ_ACK ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_ADDRESS ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_WDATA ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_REQ_TYPE ,_Morpheo->_nb_dcache_port); + + DELETE1_SC_SIGNAL( in_DCACHE_RSP_VAL ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(out_DCACHE_RSP_ACK ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_RDATA ,_Morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL( in_DCACHE_RSP_ERROR ,_Morpheo->_nb_dcache_port); + + DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_Morpheo->_nb_thread); + } +#endif + + delete _Morpheo; +} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/toto =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/toto (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/toto (revision 88) @@ -0,0 +1,1754 @@ +-------------------| SelfTest +Create directory : obj +Create directory : /tmp/Morpheo/bin +Create directory : log +Create directory : obj +Compilation : Translation +Compilation : Environm-------------------| Common +Archive : libCommon +ar: creating lib/libCommon.a +a - obj/Debug.o +a - obj/Environment.o +a - obj/Message.o +a - obj/ToString.o +a - obj/Translation.o +Create directory : obj +Create directory : lib +Compilation : Vhdl_get_architecture +testbencComCompCompilation : Stat_create_counter +Archive : libBehavioural +ar: creating lib/libBehavioural.a +a - obj/Component.o +a - obj/Component_find_entity.o +a - obj/Component_generate_file.o +a - obj/Component_get_component.o +a - obj/Component_get_entity.o +a - obj/Component_get_name.o +a - obj/Component_interface_map.o +a - obj/Component_port_map.o +a - obj/Component_print.o +a - obj/Component_set_component.o +a - obj/Component_set_entity.o +a - obj/Component_signal_internal.o +a - obj/Component_test_map.o +a - obj/Component_toXML.o +a - obj/Component_vhdl_instance.o +a - obj/Entity.o +a - obj/Entity_find_interface.o +a - obj/Entity_find_signal.o +a - obj/Entity_get_comment.o +a - obj/Entity_get_interfaces.o +a - obj/Entity_get_name.o +a - obj/Entity_get_type.o +a - obj/Entity_mapping.o +a - obj/Entity_print.o +a - obj/Entity_set_comment.o +a - obj/Entity_set_interfaces.o +a - obj/Entity_test_map.o +a - obj/Entity_toXML.o +a - obj/Identification.o +a - obj/Interface.o +a - obj/Interface_fifo.o +a - obj/Interface_fifo_get_cycle.o +a - obj/Interface_fifo_save_ptr.o +a - obj/Interface_fifo_set_signal.o +a - obj/Interface_fifo_testbench.o +a - obj/Interface_fifo_testbench_cycle.o +a - obj/Interface_fifo_testbench_test.o +a - obj/Interface_fifo_testbench_test_transaction.o +a - obj/Interface_fifo_testbench_transaction.o +a - obj/Interface_find_signal.o +a - obj/Interface_get_clock.o +a - obj/Interface_get_comment.o +a - obj/Interface_get_cycle.o +a - obj/Interface_get_name.o +a - obj/Interface_get_reset.o +a - obj/Interface_get_signal.o +a - obj/Interface_interface_map.o +a - obj/Interface_print.o +a - obj/Interfaces.o +a - obj/Interface_set_comment.o +a - obj/Interface_set_port.o +a - obj/Interface_set_signal.o +a - obj/Interfaces_find_interface.o +a - obj/Interfaces_find_signal.o +a - obj/Interfaces_get_clock.o +a - obj/Interfaces_get_cycle.o +a - obj/Interfaces_get_interface.o +a - obj/Interfaces_get_reset.o +a - obj/Interfaces_get_signal.o +a - obj/Interface_signal_name.o +a - obj/Interfaces_print.o +a - obj/Interfaces_set_interface.o +a - obj/Interfaces_set_port.o +a - obj/Interfaces_set_signal.o +a - obj/Interfaces_testbench_body.o +a - obj/Interfaces_testbench.o +a - obj/Interfaces_testbench_generate_file.o +a - obj/Interfaces_test_map.o +a - obj/Interfaces_toXML.o +a - obj/Interface_testbench_body.o +a - obj/Interface_testbench.o +a - obj/Interface_testbench_cycle.o +a - obj/Interface_testbench_test.o +a - obj/Interface_testbench_test_name.o +a - obj/Interface_testbench_test_ok.o +a - obj/Interface_test_map.o +a - obj/Interface_toXML.o +a - obj/Parameters_copy.o +a - obj/Parameters.o +a - obj/Parameters_Statistics.o +a - obj/Parameters_test.o +a - obj/Signal_connect.o +a - obj/Signal.o +a - obj/Signal_get_clock.o +a - obj/Signal_get_connect_from_signal.o +a - obj/Signal_get_connect_to_signal.o +a - obj/Signal_get_direction.o +a - obj/Signal_get_name.o +a - obj/Signal_get_name_vhdl.o +a - obj/Signal_get_reset.o +a - obj/Signal_get_reset_cycle.o +a - obj/Signal_get_size.o +a - obj/Signal_get_type_info.o +a - obj/Signal_link.o +a - obj/Signal_presence_testbench.o +a - obj/Signal_presence_vhdl.o +a - obj/Signal_print.o +a - obj/Signal_set_port.o +a - obj/Signal_set_size.o +a - obj/Signal_testbench_body.o +a - obj/Signal_testbench.o +a - obj/Signal_testbench_test_ok.o +a - obj/Signal_test_map.o +a - obj/Signal_toXML.o +a - obj/Simulation.o +a - obj/Simulation_end_cycle.o +a - obj/Simulation_test_end.o +a - obj/SPR_access_mode_change_mode.o +a - obj/SPR_access_mode.o +a - obj/SPR_access_mode_exist.o +a - obj/SPR_access_mode_implement_group.o +a - obj/SPR_access_mode_invalid_register.o +a - obj/SPR_access_mode_read_write.o +a - obj/SPR_access_mode_translate_address.o +a - obj/SPR_access_mode_valid.o +a - obj/Stat_add_stat.o +a - obj/Stat_alloc_operand.o +a - obj/Stat_binary_tree_change_type.o +a - obj/Stat_binary_tree.o +a - obj/Stat_binary_tree_eval.o +a - obj/Stat_binary_tree_goto_next_root.o +a - obj/Stat_binary_tree_goto_top_level.o +a - obj/Stat_binary_tree_import.o +a - obj/Stat_binary_tree_insert_tree.o +a - obj/Stat_binary_tree_is_leaf.o +a - obj/Stat_binary_tree_valid.o +a - obj/Stat_binary_tree_val_leaf.o +a - obj/Stat_binary_tree_val_tree.o +a - obj/Stat.o +a - obj/Stat_create_counter.o +a - obj/Stat_create_expr.o +a - obj/Stat_create_variable.o +a - obj/Stat_end_cycle.o +a - obj/Stat_end_simulation.o +a - obj/Stat_eval_expr.o +a - obj/Stat_eval_exprs.o +a - obj/Stat_generate_file.o +a - obj/Stat_have_counter.o +a - obj/Stat_is_valid_var.o +a - obj/Stat_print.o +a - obj/Stat_string2tree.o +a - obj/Stat_test_and_save.o +a - obj/Test.o +a - obj/Types.o +a - obj/Usage.o +a - obj/Vhdl.o +a - obj/Vhdl_direction_toString.o +a - obj/Vhdl_generate_file.o +a - obj/Vhdl_generate_file_model.o +a - obj/Vhdl_generate_file_package.o +a - obj/Vhdl_get_alias.o +a - obj/Vhdl_get_architecture.o +a - obj/Vhdl_get_body.o +a - obj/Vhdl_get_component.o +a - obj/Vhdl_get_entity.o +a - obj/Vhdl_get_header.o +a - obj/Vhdl_get_library_ieee.o +a - obj/Vhdl_get_library_work.o +a - obj/Vhdl_get_list.o +a - obj/Vhdl_get_model.o +a - obj/Vhdl_get_package.o +a - obj/Vhdl_get_port.o +a - obj/Vhdl_get_signal.o +a - obj/Vhdl_get_type.o +a - obj/Vhdl_set_alias.o +a - obj/Vhdl_set_body_component.o +a - obj/Vhdl_set_body_component_port_map.o +a - obj/Vhdl_set_body.o +a - obj/Vhdl_set_constant.o +a - obj/Vhdl_set_library_work.o +a - obj/Vhdl_set_list.o +a - obj/Vhdl_set_port.o +a - obj/Vhdl_set_signal.o +a - obj/Vhdl_set_type.o +a - obj/Vhdl_std_logic.o +a - obj/XML_attribut.o +a - obj/XML_balise_close.o +a - obj/XML_balise_open_begin.o +a - obj/XML_balise_open.o +a - obj/XML_balise_open_end.o +a - obj/XML_comment.o +a - obj/XML.o +a - obj/XML_depth.o +a - obj/XML_filename_extension.o +a - obj/XML_generate_file.o +a - obj/XML_get_body.o +a - obj/XML_header.o +a - obj/XML_indent.o +a - obj/XML_insert_XML.o +a - obj/XMLLightFunctors.o +a - obj/XML_singleton_begin.o +a - obj/XML_singleton.o +a - obj/XML_singleton_end.o +a - obj/XML_text.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Instruction +-------------------| Instruction +Archive : libInstruction +ar: creating lib/libInstruction.a +a - obj/Instruction.o +Create directory : obj +Compilation : Operation +-------------------| Operation +Archive : libOperation +ar: creating lib/libOperation.a +a - obj/Operation.o +Create directory : obj +Compilation : Custom_default +-------------------| Custom +Archive : libCustom +ar: creating lib/libCustom.a +a - obj/Custom_default.o +a - obj/Custom_example.o +a - obj/Encryption.o +a - obj/Random.o +Create directory : obj +Compilation : Generator_getLinkCompilation : Instance_gCompilation : Link_affectation_print +-------------------| Configuration +File +Compilation : Parameter_affectation_toXML +src/Instance_link2array.cpp: In member function 'std::vector, std::allocator >, std::allocator, std::allocator > > > morpheo::behavioural::configuration::Instance::link2array(std::string)': +src/Instance_link2array.cpp:33: attention : comparaison est toujours vraie en raison d'une gamme limitée de type de données +Archive : libConfiguration +ar: creating lib/libConfiguration.a +a - obj/Configuration.o +a - obj/Configuration_getName.o +a - obj/Configuration_getParam.o +a - obj/Configuration_getParamStatistics.o +a - obj/Configuration_getUsage.o +a - obj/Configuration_print.o +a - obj/Configuration_toFile.o +a - obj/Generator.o +a - obj/Generator_fromFile.o +a - obj/Generator_getLink.o +a - obj/Generator_getParam.o +a - obj/Generator_insert.o +a - obj/Generator_print.o +a - obj/Generator_test.o +a - obj/Generator_toFile.o +a - obj/Generator_toXML.o +a - obj/Instance.o +a - obj/Instance_fromFile.o +a - obj/Instance_fromInternalStructure.o +a - obj/Instance_fromXMLLight.o +a - obj/Instance_getLink.o +a - obj/Instance_getName.o +a - obj/Instance_getParam.o +a - obj/Instance_link2array.o +a - obj/Instance_print.o +a - obj/Instance_test.o +a - obj/Instance_test_use.o +a - obj/Instance_toFile.o +a - obj/Instance_toXML.o +a - obj/Link_affectation.o +a - obj/Link_affectation_print.o +a - obj/Link_affectation_toXML.o +a - obj/Link_definition.o +a - obj/Link_definition_print.o +a - obj/Link_definition_toXML.o +a - obj/Parameter_affectation.o +a - obj/Parameter_affectation_print.o +a - obj/Parameter_affectation_toXML.o +a - obj/Parameter_definition.o +a - obj/Parameter_definition_print.o +a - obj/Parameter_definition_test.o +a - obj/Parameter_definition_toXML.o +a - obj/Simulator.o +a - obj/Simulator_fromFile.o +a - obj/Simulator_getParam.o +a - obj/Simulator_insert.o +a - obj/Simulator_print.o +a - obj/Simulator_toFile.o +a - obj/Simulator_toXML.o +a - obj/XMLUtils_getAttribute.o +a - obj/XMLUtils_testAttributesEmpty.o +a - obj/XMLUtils_testNoAttribute.o +a - obj/XMLUtils_testNodeName.o +a - obj/XMLUtils_testSingleton.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Priority_reset_load_balancing_noneCompilation : Priority_allocation +Archive : libPriority +ar: creating lib/libPriority.a +a - obj/Priority_allocation.o +a - obj/Priority.o +a - obj/Priority_deallocation.o +a - obj/Priority_reset.o +a - obj/Priority_reset_load_balancing_balance.o +a - obj/Priority_reset_load_balancing_maximum_for_priority.o +a - obj/Priority_reset_load_balancing_none.o +a - obj/Priority_reset_load_balancing_priority_only.o +a - obj/Priority_reset_priority_none.o +a - obj/Priority_reset_priority_round_robin.o +a - obj/Priority_reset_priority_static.o +a - obj/Priority_select.o +a - obj/Priority_transition.o +a - obj/Priority_transition_load_balancing_balance.o +a - obj/Priority_transition_load_balancing_maximum_for_priority.o +a - obj/Priority_transition_load_balancing_none.o +a - obj/Priority_transition_load_balancing_priority_only.o +a - obj/Priority_transition_priority_none.o +a - obj/Priority_transition_priority_round_robin.o +a - obj/Priority_transition_priority_static.o +-------------------| Common +Create directory : obj +Compilation : Icache_Access_deallocCompCompilCompilation Compilation : Icache_Access_end_cycle +Archive : libIcache_Access +ar: creating lib/libIcache_Access.a +a - obj/Icache_Access_allocation.o +a - obj/Icache_Access.o +a - obj/Icache_Access_deallocation.o +a - obj/Icache_Access_end_cycle.o +a - obj/Icache_Access_genMealy_req.o +a - obj/Icache_Access_genMealy_rsp.o +a - obj/Icache_Access_statistics_allocation.o +a - obj/Icache_Access_statistics_deallocation.o +a - obj/Icache_Access_transition.o +a - obj/Icache_Access_vhdl_body.o +a - obj/Icache_Access_vhdl.o +a - obj/Icache_Access_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Compilation : Dcache_AcceCompilation : Dcache_Access_genMealy_rCompilation : Dcache_Access_deallocation +Archive : libDcache_Access +ar: creating lib/libDcache_Access.a +a - obj/Dcache_Access_allocation.o +a - obj/Dcache_Access.o +a - obj/Dcache_Access_deallocation.o +a - obj/Dcache_Access_end_cycle.o +a - obj/Dcache_Access_genMealy_req.o +a - obj/Dcache_Access_genMealy_rsp.o +a - obj/Dcache_Access_statistics_allocation.o +a - obj/Dcache_Access_statistics_deallocation.o +a - obj/Dcache_Access_transition.o +a - obj/Dcache_Access_vhdl_body.o +a - obj/Dcache_Access_vhdl.o +a - obj/Dcache_Access_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Address_management +Compilation : Parameters +agement_statistics_deallocatioCompilation : Address_management_vhdl +-------------------| Address_management +Compilation : Address_management_allocation +Compilation : Address_management_end_cycle +Compilation : Address_management_transition +Archive : libAddress_management +ar: creating lib/libAddress_management.a +a - obj/Address_management_allocation.o +a - obj/Address_management.o +a - obj/Address_management_deallocation.o +a - obj/Address_management_end_cycle.o +a - obj/Address_management_genMoore.o +a - obj/Address_management_statistics_allocation.o +a - obj/Address_management_statistics_deallocation.o +a - obj/Address_management_transition.o +a - obj/Address_management_vhdl_body.o +a - obj/Address_management_vhdl.o +a - obj/Address_management_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Ifetch_queue_statCompilation : Ifetch_queue_allocation +e +-------------------| Ifetch_queue +Archive : libIfetch_queue +ar: creating lib/libIfetch_queue.a +a - obj/Ifetch_queue_allocation.o +a - obj/Ifetch_queue.o +a - obj/Ifetch_queue_deallocation.o +a - obj/Ifetch_queue_end_cycle.o +a - obj/Ifetch_queue_genMoore.o +a - obj/Ifetch_queue_statistics_allocation.o +a - obj/Ifetch_queue_statistics_deallocation.o +a - obj/Ifetch_queue_transition.o +a - obj/Ifetch_queue_vhdl_body.o +a - obj/Ifetch_queue_vhdl.o +a - obj/Ifetch_queue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Ifetch_unit_Glue_vhdlCompilation : Ifetch_unitCompilation : Ifetch_unit_Glue_allocation +Compilation : Ifetch_unit_Glue_statistics_deallocation +-------------------| Ifetch_unit_Glue +Archive : libIfetch_unit_Glue +ar: creating lib/libIfetch_unit_Glue.a +a - obj/Ifetch_unit_Glue_allocation.o +a - obj/Ifetch_unit_Glue.o +a - obj/Ifetch_unit_Glue_deallocation.o +a - obj/Ifetch_unit_Glue_end_cycle.o +a - obj/Ifetch_unit_Glue_genMealy_event.o +a - obj/Ifetch_unit_Glue_genMealy_icache_req.o +a - obj/Ifetch_unit_Glue_statistics_allocation.o +a - obj/Ifetch_unit_Glue_statistics_deallocation.o +a - obj/Ifetch_unit_Glue_transition.o +a - obj/Ifetch_unit_Glue_vhdl_body.o +a - obj/Ifetch_unit_Glue_vhdl.o +a - obj/Ifetch_unit_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Ifetch_unit_transCompi-------------------| Ifetch_unit +Archive : libIfetch_unit +ar: creating lib/libIfetch_unit.a +a - obj/Ifetch_unit_allocation.o +a - obj/Ifetch_unit.o +a - obj/Ifetch_unit_deallocation.o +a - obj/Ifetch_unit_end_cycle.o +a - obj/Ifetch_unit_statistics_allocation.o +a - obj/Ifetch_unit_statistics_deallocation.o +a - obj/Ifetch_unit_transition.o +a - obj/Ifetch_unit_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Branch_Targ-------------------| Branch_TargCompilation : Branch_Target_Buffer_Glue_statistics_deallocation +_Buffer_Glue_vhdl_declaration +Compilation : Branch_Target_Buffer_Glue_end_cycle +Archive : libBranch_Target_Buffer_Glue +ar: creating lib/libBranch_Target_Buffer_Glue.a +a - obj/Branch_Target_Buffer_Glue_allocation.o +a - obj/Branch_Target_Buffer_Glue.o +a - obj/Branch_Target_Buffer_Glue_deallocation.o +a - obj/Branch_Target_Buffer_Glue_end_cycle.o +a - obj/Branch_Target_Buffer_Glue_genMealy_decod.o +a - obj/Branch_Target_Buffer_Glue_genMealy_predict.o +a - obj/Branch_Target_Buffer_Glue_genMealy_update.o +a - obj/Branch_Target_Buffer_Glue_statistics_allocation.o +a - obj/Branch_Target_Buffer_Glue_statistics_deallocation.o +a - obj/Branch_Target_Buffer_Glue_transition.o +a - obj/Branch_Target_Buffer_Glue_vhdl_body.o +a - obj/Branch_Target_Buffer_Glue_vhdl.o +a - obj/Branch_Target_Buffer_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Branch_Target_Buffer_Register_genMeCompilation Compilation : Branch-------------------| Branch_Target_Buffer_Register +Archive : libBranch_Target_Buffer_Register +ar: creating lib/libBranch_Target_Buffer_Register.a +a - obj/Branch_Target_Buffer_Register_allocation.o +a - obj/Branch_Target_Buffer_Register.o +a - obj/Branch_Target_Buffer_Register_deallocation.o +a - obj/Branch_Target_Buffer_Register_end_cycle.o +a - obj/Branch_Target_Buffer_Register_genMealy_decod.o +a - obj/Branch_Target_Buffer_Register_genMealy_predict.o +a - obj/Branch_Target_Buffer_Register_genMealy_update.o +a - obj/Branch_Target_Buffer_Register_statistics_allocation.o +a - obj/Branch_Target_Buffer_Register_statistics_deallocation.o +a - obj/Branch_Target_Buffer_Register_transition.o +a - obj/Branch_Target_Buffer_Register_vhdl_body.o +a - obj/Branch_Target_Buffer_Register_vhdl.o +a - obj/Branch_Target_Buffer_Register_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : ParamCompilatio-------------------| Sort +on +arameters_printCompilation : Parameters +Compilation : Sort_allocation +Archive : libSort +ar: creating lib/libSort.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Sort_allocation.o +a - obj/Sort.o +a - obj/Sort_deallocation.o +a - obj/Sort_end_cycle.o +a - obj/Sort_genMealy.o +a - obj/Sort_statistics_allocation.o +a - obj/Sort_statistics_deallocation.o +a - obj/Sort_transition.o +a - obj/Sort_vhdl_body.o +a - obj/Sort_vhdl.o +a - obj/Sort_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Victim_Pseudo_LRU_vhdCompilation : Parameters + : Victim_Pseudo_LRCompilation : Victim_Pseudo_LRU_deallocation +Archive : libVictim_Pseudo_LRU +ar: creating lib/libVictim_Pseudo_LRU.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Victim_Pseudo_LRU_allocation.o +a - obj/Victim_Pseudo_LRU.o +a - obj/Victim_Pseudo_LRU_deallocation.o +a - obj/Victim_Pseudo_LRU_end_cycle.o +a - obj/Victim_Pseudo_LRU_genMealy.o +a - obj/Victim_Pseudo_LRU_statistics_declaration.o +a - obj/Victim_Pseudo_LRU_transition.o +a - obj/Victim_Pseudo_LRU_vhdl_body.o +a - obj/Victim_Pseudo_LRU_vhdl.o +a - obj/Victim_Pseudo_LRU_vhdl_declaration.o +Create directory : obj +Compilation : Victim_deallocatio-------------------| Victim +Compilation : Parameters_print +Archive : libVictim +ar: creating lib/libVictim.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Victim_allocation.o +a - obj/Victim.o +a - obj/Victim_deallocation.o +Create directory : obj +Compilation : Branch_TargCompilation -------------------| Branch_Target_Buffer +Archive : libBranch_Target_Buffer +ar: creating lib/libBranch_Target_Buffer.a +a - obj/Branch_Target_Buffer_allocation.o +a - obj/Branch_Target_Buffer.o +a - obj/Branch_Target_Buffer_deallocation.o +a - obj/Branch_Target_Buffer_end_cycle.o +a - obj/Branch_Target_Buffer_statistics_allocation.o +a - obj/Branch_Target_Buffer_statistics_deallocation.o +a - obj/Branch_Target_Buffer_transition.o +a - obj/Branch_Target_Buffer_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Direction_Glue_vhdl +yCompilationCompiCompilation : Direction_Glue_genMealy_update +Archive : libDirection_Glue +ar: creating lib/libDirection_Glue.a +a - obj/Direction_Glue_allocation.o +a - obj/Direction_Glue.o +a - obj/Direction_Glue_deallocation.o +a - obj/Direction_Glue_end_cycle.o +a - obj/Direction_Glue_genMealy_predict.o +a - obj/Direction_Glue_genMealy_update.o +a - obj/Direction_Glue_statistics_allocation.o +a - obj/Direction_Glue_statistics_deallocation.o +a - obj/Direction_Glue_transition.o +a - obj/Direction_Glue_vhdl_body.o +a - obj/Direction_Glue_vhdl.o +a - obj/Direction_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Direction_statistics_CoCompilation : Parameters_print +Archive : libDirection +ar: creating lib/libDirection.a +a - obj/Direction_allocation.o +a - obj/Direction.o +a - obj/Direction_deallocation.o +a - obj/Direction_end_cycle.o +a - obj/Direction_statistics_allocation.o +a - obj/Direction_statistics_deallocation.o +a - obj/Direction_transition.o +a - obj/Direction_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Return_Address_Stack_statistics_dealloCompilation : Parameters +-------------------| Return_Address_Stack +Archive : libReturn_Address_Stack +ar: creating lib/libReturn_Address_Stack.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Return_Address_Stack_allocation.o +a - obj/Return_Address_Stack.o +a - obj/Return_Address_Stack_deallocation.o +a - obj/Return_Address_Stack_end_cycle.o +a - obj/Return_Address_Stack_genMealy_decod.o +a - obj/Return_Address_Stack_genMealy_predict.o +a - obj/Return_Address_Stack_statistics_allocation.o +a - obj/Return_Address_Stack_statistics_deallocation.o +a - obj/Return_Address_Stack_transition.o +a - obj/Return_Address_Stack_vhdl_body.o +a - obj/Return_Address_Stack_vhdl.o +a - obj/Return_Address_Stack_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Update_Prediction_Table_end_cCompilation : Update_Prediction_Table_genMealy_predict +Archive : libUpdate_Prediction_Table +ar: creating lib/libUpdate_Prediction_Table.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Update_Prediction_Table_allocation.o +a - obj/Update_Prediction_Table.o +a - obj/Update_Prediction_Table_deallocation.o +a - obj/Update_Prediction_Table_end_cycle.o +a - obj/Update_Prediction_Table_genMealy_branch_complete.o +a - obj/Update_Prediction_Table_genMealy_decod.o +a - obj/Update_Prediction_Table_genMealy_predict.o +a - obj/Update_Prediction_Table_genMoore.o +a - obj/Update_Prediction_Table_statistics_allocation.o +a - obj/Update_Prediction_Table_statistics_deallocation.o +a - obj/Update_Prediction_Table_transition.o +a - obj/Update_Prediction_Table_vhdl_body.o +a - obj/Update_Prediction_Table_vhdl.o +a - obj/Update_Prediction_Table_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Prediction_unit_Glue_statisticsCompilation : Prediction_unit_Glue_genMealy_decod +t +_deCompilation : Parameters_msg_error + +-------------------| Prediction_unit_Glue +Archive : libPrediction_unit_Glue +ar: creating lib/libPrediction_unit_Glue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Prediction_unit_Glue_allocation.o +a - obj/Prediction_unit_Glue.o +a - obj/Prediction_unit_Glue_deallocation.o +a - obj/Prediction_unit_Glue_end_cycle.o +a - obj/Prediction_unit_Glue_genMealy_decod.o +a - obj/Prediction_unit_Glue_genMealy_predict.o +a - obj/Prediction_unit_Glue_genMealy_update.o +a - obj/Prediction_unit_Glue_statistics_allocation.o +a - obj/Prediction_unit_Glue_statistics_deallocation.o +a - obj/Prediction_unit_Glue_transition.o +a - obj/Prediction_unit_Glue_vhdl_body.o +a - obj/Prediction_unit_Glue_vhdl.o +a - obj/Prediction_unit_Glue_vhdl_declaration.o +Create directory : obj +Compilation : Prediction_unit_-------------------| Prediction_unit +Archive : libPrediction_unit +ar: creating lib/libPrediction_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Prediction_unit_allocation.o +a - obj/Prediction_unit.o +a - obj/Prediction_unit_deallocation.o +a - obj/Prediction_unit_end_cycle.o +a - obj/Prediction_unit_statistics_allocation.o +a - obj/Prediction_unit_statistics_deallocation.o +a - obj/Prediction_unit_transition.o +a - obj/Prediction_unit_vhdl.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +-------------------| Common +-------------------| Behavioural +-------------------| Instruction +-------------------| Operation +-------------------| Custom +Create directory : obj +Compilation : Decod_transition-------------------| Decod +Archive : libDecod +ar: creating lib/libDecod.a +a - obj/Decod_allocation.o +a - obj/Decod.o +a - obj/Decod_deallocation.o +a - obj/Decod_end_cycle.o +a - obj/Decod_genMealy.o +a - obj/Decod_statistics_allocation.o +a - obj/Decod_statistics_deallocation.o +a - obj/Decod_transition.o +a - obj/Decod_vhdl_body.o +a - obj/Decod_vhdl.o +a - obj/Decod_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Decod_queueCompilation : Decod_queu-------------------| Decod_queue +Archive : libDecod_queue +ar: creating lib/libDecod_queue.a +a - obj/Decod_queue_allocation.o +a - obj/Decod_queue.o +a - obj/Decod_queue_deallocation.o +a - obj/Decod_queue_end_cycle.o +a - obj/Decod_queue_genMealy_decod_out.o +a - obj/Decod_queue_genMoore.o +a - obj/Decod_queue_statistics_allocation.o +a - obj/Decod_queue_statistics_deallocation.o +a - obj/Decod_queue_transition.o +a - obj/Decod_queue_vhdl_body.o +a - obj/Decod_queue_vhdl.o +a - obj/Decod_queue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Decod_unit_statiCompilation : Decod_unit_end_cycle +n +n +-------------------| Decod_unit +Compilation : Decod_unit_statistics_allocation +Archive : libDecod_unit +ar: creating lib/libDecod_unit.a +a - obj/Decod_unit_allocation.o +a - obj/Decod_unit.o +a - obj/Decod_unit_deallocation.o +a - obj/Decod_unit_end_cycle.o +a - obj/Decod_unit_statistics_allocation.o +a - obj/Decod_unit_statistics_deallocation.o +a - obj/Decod_unit_transition.o +a - obj/Decod_unit_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Context_State_endCoCompilation : Context_State +vhdl_declaratio-------------------| Context_State +Archive : libContext_State +ar: creating lib/libContext_State.a +a - obj/Context_State_allocation.o +a - obj/Context_State.o +a - obj/Context_State_deallocation.o +a - obj/Context_State_end_cycle.o +a - obj/Context_State_genMoore.o +a - obj/Context_State_statistics_allocation.o +a - obj/Context_State_statistics_deallocation.o +a - obj/Context_State_transition.o +a - obj/Context_State_vhdl_body.o +a - obj/Context_State_vhdl.o +a - obj/Context_State_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Parameters_Compilation : Parameters_prin-------------------| Front_end_Glue +Archive : libFront_end_Glue +ar: creating lib/libFront_end_Glue.a +a - obj/Front_end_Glue_allocation.o +a - obj/Front_end_Glue.o +a - obj/Front_end_Glue_deallocation.o +a - obj/Front_end_Glue_end_cycle.o +a - obj/Front_end_Glue_genMealy_branch_complete.o +a - obj/Front_end_Glue_genMealy_decod.o +a - obj/Front_end_Glue_genMealy_depth.o +a - obj/Front_end_Glue_genMealy_event.o +a - obj/Front_end_Glue_statistics_allocation.o +a - obj/Front_end_Glue_statistics_deallocation.o +a - obj/Front_end_Glue_transition.o +a - obj/Front_end_Glue_vhdl_body.o +a - obj/Front_end_Glue_vhdl.o +a - obj/Front_end_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Front_end_statistCompilation : Front_end_end_cycle + +CoCreate directory : lib +Archive : libFront_end +ar: creating lib/libFront_end.a +a - obj/Front_end_allocation.o +a - obj/Front_end.o +a - obj/Front_end_deallocation.o +a - obj/Front_end_end_cycle.o +a - obj/Front_end_statistics_allocation.o +a - obj/Front_end_statistics_deallocation.o +a - obj/Front_end_transition.o +a - obj/Front_end_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Create directory : lib +-------------------| Commit_unit +src/Commit_unit_transition.cpp: In member function 'void morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Commit_unit::transition()': +src/Commit_unit_transition.cpp:460: attention : format '%d' expects type 'int', but argument 4 has type 'size_t' +Archive : libCommit_unit +ar: creating lib/libCommit_unit.a +a - obj/Commit_unit_allocation.o +a - obj/Commit_unit.o +a - obj/Commit_unit_deallocation.o +a - obj/Commit_unit_end_cycle.o +a - obj/Commit_unit_genMealy_commit.o +a - obj/Commit_unit_genMealy_insert.o +a - obj/Commit_unit_genMealy_retire.o +a - obj/Commit_unit_genMoore.o +a - obj/Commit_unit_statistics_allocation.o +a - obj/Commit_unit_statistics_deallocation.o +a - obj/Commit_unit_transition.o +a - obj/Commit_unit_vhdl_body.o +a - obj/Commit_unit_vhdl.o +a - obj/Commit_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Compilation : Issue_queueCCompilation : Issue_queue_statistics_allocation +src/Issue_queue_transition.cpp: In member function 'void morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Issue_queue::transition()': +src/Issue_queue_transition.cpp:157: attention : format '%d' expects type 'int', but argument 4 has type 'size_t' +Archive : libIssue_queue +ar: creating lib/libIssue_queue.a +a - obj/Issue_queue_allocation.o +a - obj/Issue_queue.o +a - obj/Issue_queue_deallocation.o +a - obj/Issue_queue_end_cycle.o +a - obj/Issue_queue_genMealy.o +a - obj/Issue_queue_genMoore.o +a - obj/Issue_queue_statistics_allocation.o +a - obj/Issue_queue_statistics_deallocation.o +a - obj/Issue_queue_transition.o +a - obj/Issue_queue_vhdl_body.o +a - obj/Issue_queue_vhdl.o +a - obj/Issue_queue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Compilation : Reexecute_unit_vhdl_body + +allocaCreate -------------------| Reexecute_unit +Archive : libReexecute_unit +ar: creating lib/libReexecute_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Reexecute_unit_allocation.o +a - obj/Reexecute_unit.o +a - obj/Reexecute_unit_deallocation.o +a - obj/Reexecute_unit_end_cycle.o +a - obj/Reexecute_unit_genMealy_commit.o +a - obj/Reexecute_unit_genMealy_reexecute.o +a - obj/Reexecute_unit_genMoore.o +a - obj/Reexecute_unit_must_reexecute.o +a - obj/Reexecute_unit_statistics_allocation.o +a - obj/Reexecute_unit_statistics_deallocation.o +a - obj/Reexecute_unit_transition.o +a - obj/Reexecute_unit_vhdl_body.o +a - obj/Reexecute_unit_vhdl.o +a - obj/Reexecute_unit_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Load_Store_pointeCompilation : Load_Store_pointer_unit_genMealy_retire +Compilation : Load_Store_pointer_unit_statistics_declaration +Compilation : LoadCompilation : Load_Store_pointer_unit_vhdl_body +Compilation : Load_Store_pointer_unit_genMealy_insert +-------------------| Load_Store_pointer_unit +Archive : libLoad_Store_pointer_unit +ar: creating lib/libLoad_Store_pointer_unit.a +a - obj/Load_Store_pointer_unit_allocation.o +a - obj/Load_Store_pointer_unit.o +a - obj/Load_Store_pointer_unit_deallocation.o +a - obj/Load_Store_pointer_unit_end_cycle.o +a - obj/Load_Store_pointer_unit_genMealy_insert.o +a - obj/Load_Store_pointer_unit_genMealy_retire.o +a - obj/Load_Store_pointer_unit_statistics_declaration.o +a - obj/Load_Store_pointer_unit_transition.o +a - obj/Load_Store_pointer_unit_vhdl_body.o +a - obj/Load_Store_pointer_unit_vhdl.o +a - obj/Load_Store_pointer_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Register_Address_Translation_unit_-------------------| Register_Address_Translation_unit +Archive : libRegister_Address_Translation_unit +ar: creating lib/libRegister_Address_Translation_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Register_Address_Translation_unit_allocation.o +a - obj/Register_Address_Translation_unit.o +a - obj/Register_Address_Translation_unit_deallocation.o +a - obj/Register_Address_Translation_unit_end_cycle.o +a - obj/Register_Address_Translation_unit_genMealy_rename.o +a - obj/Register_Address_Translation_unit_genMealy_retire.o +a - obj/Register_Address_Translation_unit_statistics_declaration.o +a - obj/Register_Address_Translation_unit_transition.o +a - obj/Register_Address_Translation_unit_vhdl_body.o +a - obj/Register_Address_Translation_unit_vhdl.o +a - obj/Register_Address_Translation_unit_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Free_List_uCompilation -------------------| Free_List_unit +Archive : libFree_List_unit +ar: creating lib/libFree_List_unit.a +a - obj/Free_List_unit_allocation.o +a - obj/Free_List_unit.o +a - obj/Free_List_unit_deallocation.o +a - obj/Free_List_unit_end_cycle.o +a - obj/Free_List_unit_genMealy_pop.o +a - obj/Free_List_unit_genMealy_push_gpr.o +a - obj/Free_List_unit_genMealy_push_spr.o +a - obj/Free_List_unit_statistics_declaration.o +a - obj/Free_List_unit_transition.o +a - obj/Free_List_unit_vhdl_body.o +a - obj/Free_List_unit_vhdl.o +a - obj/Free_List_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Para-----------------Compilation : Stat_List_unit +Archive : libStat_List_unit +ar: creating lib/libStat_List_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Stat_List_unit_allocation.o +a - obj/Stat_List_unit.o +a - obj/Stat_List_unit_deallocation.o +a - obj/Stat_List_unit_end_cycle.o +a - obj/Stat_List_unit_genMealy.o +a - obj/Stat_List_unit_genMoore.o +a - obj/Stat_List_unit_statistics_declaration.o +a - obj/Stat_List_unit_transition.o +a - obj/Stat_List_unit_vhdl_body.o +a - obj/Stat_List_unit_vhdl.o +a - obj/Stat_List_unit_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Create directory : lib +ndency_checking_unit_allocation +Compilation : Dependency_checking_unit_deallocation +Archive : libDependency_checking_unit +ar: creating lib/libDependency_checking_unit.a +a - obj/Dependency_checking_unit_allocation.o +a - obj/Dependency_checking_unit.o +a - obj/Dependency_checking_unit_deallocation.o +a - obj/Dependency_checking_unit_end_cycle.o +a - obj/Dependency_checking_unit_genMealy.o +a - obj/Dependency_checking_unit_statistics_declaration.o +a - obj/Dependency_checking_unit_transition.o +a - obj/Dependency_checking_unit_vhdl_body.o +a - obj/Dependency_checking_unit_vhdl.o +a - obj/Dependency_checking_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Register_translation_unit_Glue_vhdl_CompiCompilation : Parameters +rror +unit_Glue +deallocatiCre-------------------| Register_translation_unit_Glue +Archive : libRegister_translation_unit_Glue +ar: creating lib/libRegister_translation_unit_Glue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Register_translation_unit_Glue_allocation.o +a - obj/Register_translation_unit_Glue.o +a - obj/Register_translation_unit_Glue_deallocation.o +a - obj/Register_translation_unit_Glue_end_cycle.o +a - obj/Register_translation_unit_Glue_genMealy_insert.o +a - obj/Register_translation_unit_Glue_genMealy_insert_valack.o +a - obj/Register_translation_unit_Glue_genMealy_retire.o +a - obj/Register_translation_unit_Glue_statistics_declaration.o +a - obj/Register_translation_unit_Glue_transition.o +a - obj/Register_translation_unit_Glue_vhdl_body.o +a - obj/Register_translation_unit_Glue_vhdl.o +a - obj/Register_translation_unit_Glue_vhdl_declaration.o +Create directory : obj +Compilation : Register_translation_unit_deallocatiCompilation : Parameters +print +ion_-------------------| Register_translation_unit +Archive : libRegister_translation_unit +ar: creating lib/libRegister_translation_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Register_translation_unit_allocation.o +a - obj/Register_translation_unit.o +a - obj/Register_translation_unit_deallocation.o +a - obj/Register_translation_unit_end_cycle.o +a - obj/Register_translation_unit_statistics_declaration.o +a - obj/Register_translation_unit_transition.o +a - obj/Register_translation_unit_vhdl.o +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Compilation : Rename_select_deallCompilation : Rename_select_genMealy +-------------------| Rename_select +Archive : libRename_select +ar: creating lib/libRename_select.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Rename_select_allocation.o +a - obj/Rename_select.o +a - obj/Rename_select_deallocation.o +a - obj/Rename_select_end_cycle.o +a - obj/Rename_select_genMealy.o +a - obj/Rename_select_statistics_declaration.o +a - obj/Rename_select_transition.o +a - obj/Rename_select_vhdl_body.o +a - obj/Rename_select_vhdl.o +a - obj/Rename_select_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Rename_unit_Glue_statisticsCompilation : Rename_unit_Glue_allocation +Archive : libRename_unit_Glue +ar: creating lib/libRename_unit_Glue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Rename_unit_Glue_allocation.o +a - obj/Rename_unit_Glue.o +a - obj/Rename_unit_Glue_deallocation.o +a - obj/Rename_unit_Glue_end_cycle.o +a - obj/Rename_unit_Glue_genMealy_insert.o +a - obj/Rename_unit_Glue_genMealy_insert_valack.o +a - obj/Rename_unit_Glue_genMealy_retire_valack.o +a - obj/Rename_unit_Glue_statistics_allocation.o +a - obj/Rename_unit_Glue_statistics_deallocation.o +a - obj/Rename_unit_Glue_transition.o +a - obj/Rename_unit_Glue_vhdl_body.o +a - obj/Rename_unit_Glue_vhdl.o +a - obj/Rename_unit_Glue_vhdl_declaration.o +Create directory : obj +Compilation : Parameters_msg_erCreat-------------------| Rename_unit +Archive : libRename_unit +ar: creating lib/libRename_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Rename_unit_allocation.o +a - obj/Rename_unit.o +a - obj/Rename_unit_deallocation.o +a - obj/Rename_unit_end_cycle.o +a - obj/Rename_unit_statistics_allocation.o +a - obj/Rename_unit_statistics_deallocation.o +a - obj/Rename_unit_transition.o +a - obj/Rename_unit_vhdl.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Special_Register_unit_Compilation -------------------| Special_Register_unit +Archive : libSpecial_Register_unit +ar: creating lib/libSpecial_Register_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Special_Register_unit_allocation.o +a - obj/Special_Register_unit.o +a - obj/Special_Register_unit_deallocation.o +a - obj/Special_Register_unit_end_cycle.o +a - obj/Special_Register_unit_genMealy_spr_access.o +a - obj/Special_Register_unit_genMoore.o +a - obj/Special_Register_unit_statistics_allocation.o +a - obj/Special_Register_unit_statistics_deallocation.o +a - obj/Special_Register_unit_transition.o +a - obj/Special_Register_unit_vhdl_body.o +a - obj/Special_Register_unit_vhdl.o +a - obj/Special_Register_unit_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : OOO_Engine_Glue_gCompilati-------------------| OOO_Engine_Glue +Archive : libOOO_Engine_Glue +ar: creating lib/libOOO_Engine_Glue.a +a - obj/OOO_Engine_Glue_allocation.o +a - obj/OOO_Engine_Glue.o +a - obj/OOO_Engine_Glue_deallocation.o +a - obj/OOO_Engine_Glue_end_cycle.o +a - obj/OOO_Engine_Glue_genMealy_insert.o +a - obj/OOO_Engine_Glue_genMealy_insert_valack.o +a - obj/OOO_Engine_Glue_genMealy_rename.o +a - obj/OOO_Engine_Glue_genMealy_retire.o +a - obj/OOO_Engine_Glue_genMealy_retire_valack.o +a - obj/OOO_Engine_Glue_genMealy_spr.o +a - obj/OOO_Engine_Glue_statistics_allocation.o +a - obj/OOO_Engine_Glue_statistics_deallocation.o +a - obj/OOO_Engine_Glue_transition.o +a - obj/OOO_Engine_Glue_vhdl_body.o +a - obj/OOO_Engine_Glue_vhdl.o +a - obj/OOO_Engine_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : OOO_Engine +Compilation : OOO_Engine_allocation +Archive : libOOO_Engine +ar: creating lib/libOOO_Engine.a +a - obj/OOO_Engine_allocation.o +a - obj/OOO_Engine.o +a - obj/OOO_Engine_deallocation.o +a - obj/OOO_Engine_end_cycle.o +a - obj/OOO_Engine_statistics_allocation.o +a - obj/OOO_Engine_statistics_deallocation.o +a - obj/OOO_Engine_transition.o +a - obj/OOO_Engine_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Parameters_msg_erCreate directory : lib +ute_loop_Glue_vhdl_body +-------------------| Execute_loop_Glue +oop_Glue_genMealy_spr_Compilation : Execute_loop_Glue_statistics_allocation +Archive : libExecute_loop_Glue +ar: creating lib/libExecute_loop_Glue.a +a - obj/Execute_loop_Glue_allocation.o +a - obj/Execute_loop_Glue.o +a - obj/Execute_loop_Glue_deallocation.o +a - obj/Execute_loop_Glue_end_cycle.o +a - obj/Execute_loop_Glue_genMealy_gpr_write.o +a - obj/Execute_loop_Glue_genMealy_spr_write.o +a - obj/Execute_loop_Glue_statistics_allocation.o +a - obj/Execute_loop_Glue_statistics_deallocation.o +a - obj/Execute_loop_Glue_transition.o +a - obj/Execute_loop_Glue_vhdl_body.o +a - obj/Execute_loop_Glue_vhdl.o +a - obj/Execute_loop_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Queue_Control +nb_eCreate directory : lib +-------------------| Queue_Control +Archive : libQueue_Control +ar: creating lib/libQueue_Control.a +a - obj/Queue_Control_clear.o +a - obj/Queue_Control.o +a - obj/Queue_Control_flags.o +a - obj/Queue_Control_nb_elt.o +a - obj/Queue_Control_operator.o +a - obj/Queue_Control_pop.o +a - obj/Queue_Control_push.o +Create directory : obj +Compilation : Queue_genMoore + + +declarCompilation : Queu-------------------| Queue +Archive : libQueue +ar: creating lib/libQueue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Queue_allocation.o +a - obj/Queue.o +a - obj/Queue_deallocation.o +a - obj/Queue_end_cycle.o +a - obj/Queue_genMoore.o +a - obj/Queue_statistics_declaration.o +a - obj/Queue_transition.o +a - obj/Queue_vhdl_body.o +a - obj/Queue_vhdl.o +a - obj/Queue_vhdl_declaration.o +Create directory : obj +Compilation : Read_queue_transCompiC-------------------| Read_queue +src/Read_queue_transition.cpp: In member function 'void morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Read_queue::transition()': +src/Read_queue_transition.cpp:49: attention : format '%d' expects type 'int', but argument 3 has type 'size_t' +src/Read_queue_transition.cpp:144: attention : format '%d' expects type 'int', but argument 3 has type 'size_t' +Archive : libRead_queue +ar: creating lib/libRead_queue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Read_queue_allocation.o +a - obj/Read_queue.o +a - obj/Read_queue_deallocation.o +a - obj/Read_queue_end_cycle.o +a - obj/Read_queue_genMealy_read_queue_out_gpr.o +a - obj/Read_queue_genMealy_read_queue_out_spr.o +a - obj/Read_queue_genMealy_read_queue_out_val.o +a - obj/Read_queue_genMoore.o +a - obj/Read_queue_statistics_declaration.o +a - obj/Read_queue_transition.o +a - obj/Read_queue_vhdl_body.o +a - obj/Read_queue_vhdl.o +a - obj/Read_queue_vhdl_declaration.o +-------------------| Queue_Control +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Parameters_msg_error +nd_cCompiCompilation : Parameters_print +Archive : libReservation_station +ar: creating lib/libReservation_station.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Reservation_station_allocation.o +a - obj/Reservation_station.o +a - obj/Reservation_station_deallocation.o +a - obj/Reservation_station_end_cycle.o +a - obj/Reservation_station_genMoore.o +a - obj/Reservation_station_statistics_declaration.o +a - obj/Reservation_station_transition.o +a - obj/Reservation_station_vhdl_body.o +a - obj/Reservation_station_vhdl.o +a - obj/Reservation_station_vhdl_declaration.o +Create directory : obj +Compilation : Read_unit_deallCompiCompilation : Read_unit_allocation +Archive : libRead_unit +ar: creating lib/libRead_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Read_unit_allocation.o +a - obj/Read_unit.o +a - obj/Read_unit_deallocation.o +a - obj/Read_unit_end_cycle.o +a - obj/Read_unit_statistics_declaration.o +a - obj/Read_unit_transition.o +a - obj/Read_unit_vhdl.o +-------------------| Common +-------------------| Behavioural +-------------------| Instruction +-------------------| Operation +-------------------| Custom +-------------------| Common +-------------------| Behavioural +Create directory : obj +Create directory : lib +Compilation : Functionnal_unit_Compi-------------------| Functionnal_unit +Archive : libFunctionnal_unit +ar: creating lib/libFunctionnal_unit.a +a - obj/Functionnal_unit_allocation.o +a - obj/Functionnal_unit.o +a - obj/Functionnal_unit_deallocation.o +a - obj/Functionnal_unit_end_cycle.o +a - obj/Functionnal_unit_genMoore.o +a - obj/Functionnal_unit_statistics_declaration.o +a - obj/Functionnal_unit_transition.o +a - obj/Functionnal_unit_vhdl_body.o +a - obj/Functionnal_unit_vhdl.o +a - obj/Functionnal_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Queue_Control +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Load_store_unit_genMealy_Compilation : Load_store_unit_genMealCompilation : Load_store_unit_function_speculative_load_commit_genMealy_dcache +Archive : libLoad_store_unit +ar: creating lib/libLoad_store_unit.a +a - obj/Load_store_unit_allocation.o +a - obj/Load_store_unit.o +a - obj/Load_store_unit_deallocation.o +a - obj/Load_store_unit_end_cycle.o +a - obj/Load_store_unit_function_speculative_load_commit_genMealy_dcache.o +a - obj/Load_store_unit_function_speculative_load_commit_genMealy_insert.o +a - obj/Load_store_unit_function_speculative_load_commit_genMealy_retire.o +a - obj/Load_store_unit_function_speculative_load_commit_genMoore.o +a - obj/Load_store_unit_function_speculative_load_commit_transition.o +a - obj/Load_store_unit_genMealy_dcache.o +a - obj/Load_store_unit_genMealy_insert.o +a - obj/Load_store_unit_genMealy_retire.o +a - obj/Load_store_unit_genMoore.o +a - obj/Load_store_unit_statistics_declaration.o +a - obj/Load_store_unit_transition.o +a - obj/Load_store_unit_vhdl_body.o +a - obj/Load_store_unit_vhdl.o +a - obj/Load_store_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Write_queue_genMoCreate directory Compilation : Parameters_print +Archive : libWrite_queue +ar: creating lib/libWrite_queue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Write_queue_allocation.o +a - obj/Write_queue.o +a - obj/Write_queue_deallocation.o +a - obj/Write_queue_end_cycle.o +a - obj/Write_queue_genMoore.o +a - obj/Write_queue_statistics_declaration.o +a - obj/Write_queue_transition.o +a - obj/Write_queue_vhdl_body.o +a - obj/Write_queue_vhdl.o +a - obj/Write_queue_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Execute_queue_allocation +Compilation : Execute_queue_vhdCompila-------------------| Execute_queue +CompilCompilation : Parameters +Archive : libExecute_queue +ar: creating lib/libExecute_queue.a +a - obj/Execute_queue_allocation.o +a - obj/Execute_queue.o +a - obj/Execute_queue_deallocation.o +a - obj/Execute_queue_end_cycle.o +a - obj/Execute_queue_genMoore.o +a - obj/Execute_queue_statistics_declaration.o +a - obj/Execute_queue_transition.o +a - obj/Execute_queue_vhdl_body.o +a - obj/Execute_queue_vhdl.o +a - obj/Execute_queue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Write_unit_deallC-------------------| Write_unit +Archive : libWrite_unit +ar: creating lib/libWrite_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Write_unit_allocation.o +a - obj/Write_unit.o +a - obj/Write_unit_deallocation.o +a - obj/Write_unit_end_cycle.o +a - obj/Write_unit_statistics_declaration.o +a - obj/Write_unit_transition.o +a - obj/Write_unit_vhdl.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : RegisterFile_Monolithic_statiCompilation Compilation : RegisterFile_Monolithic_vhdl_body +Archive : libRegisterFile_Monolithic +ar: creating lib/libRegisterFile_Monolithic.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/RegisterFile_Monolithic_allocation.o +a - obj/RegisterFile_Monolithic.o +a - obj/RegisterFile_Monolithic_deallocation.o +a - obj/RegisterFile_Monolithic_end_cycle.o +a - obj/RegisterFile_Monolithic_genMealy_read.o +a - obj/RegisterFile_Monolithic_statistics_declaration.o +a - obj/RegisterFile_Monolithic_transition.o +a - obj/RegisterFile_Monolithic_vhdl_body.o +a - obj/RegisterFile_Monolithic_vhdl.o +a - obj/RegisterFile_Monolithic_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +-------------------| Common +-------------------| Behavioural +-------------------| RegisterFile_Monolithic +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Select_Priority_Fixed_transCompiCompilation : Select_Priority_Fixed_genMeaCompilation : Select_Priority_Fixed_end_cycle +Compilation : Select_Priority_Fixed_deallocation +Compilation : Parameters +Archive : libSelect_Priority_Fixed +ar: creating lib/libSelect_Priority_Fixed.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Select_Priority_Fixed_allocation.o +a - obj/Select_Priority_Fixed.o +a - obj/Select_Priority_Fixed_deallocation.o +a - obj/Select_Priority_Fixed_end_cycle.o +a - obj/Select_Priority_Fixed_genMealy_entity.o +a - obj/Select_Priority_Fixed_statistics_declaration.o +a - obj/Select_Priority_Fixed_transition.o +a - obj/Select_Priority_Fixed_vhdl_body.o +a - obj/Select_Priority_Fixed_vhdl.o +a - obj/Select_Priority_Fixed_vhdl_declaration.o +Create directory : obj +Compilation : Para-------------------| RegisterFile_Multi_Banked +Archive : libRegisterFile_Multi_Banked +ar: creating lib/libRegisterFile_Multi_Banked.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/RegisterFile_Multi_Banked_address_xxx.o +a - obj/RegisterFile_Multi_Banked_allocation.o +a - obj/RegisterFile_Multi_Banked.o +a - obj/RegisterFile_Multi_Banked_deallocation.o +a - obj/RegisterFile_Multi_Banked_end_cycle.o +a - obj/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.o +a - obj/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.o +a - obj/RegisterFile_Multi_Banked_full_crossbar_transition.o +a - obj/RegisterFile_Multi_Banked_genMealy_read.o +a - obj/RegisterFile_Multi_Banked_genMealy_write.o +a - obj/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.o +a - obj/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.o +a - obj/RegisterFile_Multi_Banked_partial_crossbar_transition.o +a - obj/RegisterFile_Multi_Banked_statistics_declaration.o +a - obj/RegisterFile_Multi_Banked_transition.o +a - obj/RegisterFile_Multi_Banked_vhdl_body.o +a - obj/RegisterFile_Multi_Banked_vhdl.o +a - obj/RegisterFile_Multi_Banked_vhdl_declaration.o +Create directory : obj +Compilation : RegisterFile +g_error +tion +Create directory : lib +Compilation : Parameters +-------------------| RegisterFile +Archive : libRegisterFile +ar: creating lib/libRegisterFile.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/RegisterFile_allocation.o +a - obj/RegisterFile.o +a - obj/RegisterFile_deallocation.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Register_unit_Glue_genMealy_sCompilation -------------------| Register_unit_Glue +Archive : libRegister_unit_Glue +ar: creating lib/libRegister_unit_Glue.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Register_unit_Glue_allocation.o +a - obj/Register_unit_Glue.o +a - obj/Register_unit_Glue_deallocation.o +a - obj/Register_unit_Glue_end_cycle.o +a - obj/Register_unit_Glue_genMealy_gpr_read.o +a - obj/Register_unit_Glue_genMealy_gpr_read_registerfile.o +a - obj/Register_unit_Glue_genMealy_gpr_read_status.o +a - obj/Register_unit_Glue_genMealy_gpr_registerfile.o +a - obj/Register_unit_Glue_genMealy_gpr_write.o +a - obj/Register_unit_Glue_genMealy_gpr_write_status.o +a - obj/Register_unit_Glue_genMealy_insert.o +a - obj/Register_unit_Glue_genMealy_retire.o +a - obj/Register_unit_Glue_genMealy_spr_read.o +a - obj/Register_unit_Glue_genMealy_spr_read_registerfile.o +a - obj/Register_unit_Glue_genMealy_spr_read_status.o +a - obj/Register_unit_Glue_genMealy_spr_registerfile.o +a - obj/Register_unit_Glue_genMealy_spr_write.o +a - obj/Register_unit_Glue_genMealy_spr_write_status.o +a - obj/Register_unit_Glue_statistics_declaration.o +a - obj/Register_unit_Glue_transition.o +a - obj/Register_unit_Glue_vhdl_body.o +a - obj/Register_unit_Glue_vhdl.o +a - obj/Register_unit_Glue_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Parameters_msg_error +ion +Compilation : Parameters +Archive : libRegister_unit +ar: creating lib/libRegister_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Register_unit_allocation.o +a - obj/Register_unit.o +a - obj/Register_unit_deallocation.o +a - obj/Register_unit_end_cycle.o +a - obj/Register_unit_statistics_declaration.o +a - obj/Register_unit_transition.o +a - obj/Register_unit_vhdl_body.o +a - obj/Register_unit_vhdl.o +a - obj/Register_unit_vhdl_declaration.o +-------------------| Common +-------------------| Behavioural +Create directory : obj +Compilation : Read_unit_to_ExecCompilation : Read_unit_to_Execution_unit_vhdl_declaration +-------------------| Read_unit_to_Execution_unit +Archive : libRead_unit_to_Execution_unit +ar: creating lib/libRead_unit_to_Execution_unit.a +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +a - obj/Read_unit_to_Execution_unit_allocation.o +a - obj/Read_unit_to_Execution_unit.o +a - obj/Read_unit_to_Execution_unit_deallocation.o +a - obj/Read_unit_to_Execution_unit_end_cycle.o +a - obj/Read_unit_to_Execution_unit_genMealy.o +a - obj/Read_unit_to_Execution_unit_statistics_declaration.o +a - obj/Read_unit_to_Execution_unit_transition.o +a - obj/Read_unit_to_Execution_unit_vhdl_body.o +a - obj/Read_unit_to_Execution_unit_vhdl.o +a - obj/Read_unit_to_Execution_unit_vhdl_declaration.o +-------------------| Behavioural +Create directory : obj +Compilation : Execution_uCompilation : ParametersCompilation : Executio-------------------| Execution_unit_to_Write_unit +Archive : libExecution_unit_to_Write_unit +ar: creating lib/libExecution_unit_to_Write_unit.a +a - obj/Execution_unit_to_Write_unit_allocation.o +a - obj/Execution_unit_to_Write_unit.o +a - obj/Execution_unit_to_Write_unit_deallocation.o +a - obj/Execution_unit_to_Write_unit_end_cycle.o +a - obj/Execution_unit_to_Write_unit_genMealy.o +a - obj/Execution_unit_to_Write_unit_statistics_declaration.o +a - obj/Execution_unit_to_Write_unit_transition.o +a - obj/Execution_unit_to_Write_unit_vhdl_body.o +a - obj/Execution_unit_to_Write_unit_vhdl.o +a - obj/Execution_unit_to_Write_unit_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Create directory : lib +Compilation : Execute_loop_end_CCompilation : Execute_loop_allocation +Archive : libExecute_loop +ar: creating lib/libExecute_loop.a +a - obj/Execute_loop_allocation.o +a - obj/Execute_loop.o +a - obj/Execute_loop_deallocation.o +a - obj/Execute_loop_end_cycle.o +a - obj/Execute_loop_statistics_declaration.o +a - obj/Execute_loop_transition.o +a - obj/Execute_loop_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +-------------------| Common +-------------------| Behavioural +-------------------| Priority +-------------------| Common +Create directory : obj +Compilation : Core_Glue +-------------------| Core_Glue +Archive : libCore_Glue +ar: creating lib/libCore_Glue.a +a - obj/Core_Glue_allocation.o +a - obj/Core_Glue.o +a - obj/Core_Glue_deallocation.o +a - obj/Core_Glue_end_cycle.o +a - obj/Core_Glue_genMealy_branch_complete.o +a - obj/Core_Glue_genMealy_commit_event.o +a - obj/Core_Glue_genMealy_execute.o +a - obj/Core_Glue_genMealy_insert.o +a - obj/Core_Glue_genMealy_issue.o +a - obj/Core_Glue_statistics_allocation.o +a - obj/Core_Glue_statistics_deallocation.o +a - obj/Core_Glue_transition.o +a - obj/Core_Glue_vhdl_body.o +a - obj/Core_Glue_vhdl.o +a - obj/Core_Glue_vhdl_declaration.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Create directory : lib +Compilation : Core_deallocation +---Compilation : Core_transition +Compilation : Core_end_cycle +Archive : libCore +ar: creating lib/libCore.a +a - obj/Core_allocation.o +a - obj/Core.o +a - obj/Core_deallocation.o +a - obj/Core_end_cycle.o +a - obj/Core_statistics_allocation.o +a - obj/Core_statistics_deallocation.o +a - obj/Core_transition.o +a - obj/Core_vhdl.o +a - obj/Parameters.o +a - obj/Parameters_msg_error.o +a - obj/Parameters_print.o +Create directory : obj +Compilation : Morpheo_statistics_deallocation +Create directory : lib +-------------------| TopLevel +Archive : libMorpheo +ar: creating lib/libMorpheo.a +a - obj/Morpheo_allocation.o +a - obj/Morpheo_configuration.o +a - obj/Morpheo.o +a - obj/Morpheo_deallocation.o +a - obj/Morpheo_end_cycle.o +a - obj/Morpheo_header.o +a - obj/Morpheo_simulation_end.o +a - obj/Morpheo_statistics_allocation.o +a - obj/Morpheo_statistics_deallocation.o +a - obj/Morpheo_transition.o +a - obj/Morpheo_vhdl.o +Compilation : main +Compilation : test +src/test.cpp: In function 'void test(std::string, std::string, std::string, std::string, morpheo::behavioural::custom::custom_information_t (*)())': +src/test.cpp:45: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:46: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:47: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:48: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:49: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:50: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:52: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:53: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:54: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:55: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:56: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:57: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:59: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:60: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:61: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:62: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:63: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:64: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:65: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:67: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:68: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:69: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:70: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:71: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:72: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:74: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:85: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:85: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:86: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:86: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:88: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:88: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:90: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:90: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:91: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:91: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:92: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:92: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:94: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:94: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:95: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:95: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:97: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:97: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:99: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:99: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:100: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:100: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:101: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:101: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:103: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:103: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:104: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:104: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:106: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:106: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:108: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:108: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:109: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:109: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:110: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:110: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:111: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:111: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:113: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:113: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:114: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision +src/test.cpp:114: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:116: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:116: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:118: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:118: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:119: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:119: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:120: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:120: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +src/test.cpp:122: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision +src/test.cpp:122: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision +distcc[16160] ERROR: compile src/test.cpp on fox/8,lzo failed +make[2]: *** [obj/test.o] Erreur 1 +make[1]: *** [all_selftest] Erreur 2 +make: *** [all] Erreur 2 +Command exited with non-zero status 2 +94.15user 117.94system 6:41.60elapsed 52%CPU (0avgtext+0avgdata 0maxresident)k +0inputs+0outputs (0major+3715681minor)pagefaults 0swaps Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Makefile (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Makefile (revision 88) @@ -0,0 +1,19 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ Directory ]---------------------------------------- +DIR_COMPONENT = ../ +include $(DIR_COMPONENT)/Makefile.defs + +#-----[ include ]------------------------------------------ + +all : + $(MAKE) all_documentation + +include $(DIR_MORPHEO)/Behavioural/Makefile.Common +include $(DIR_MORPHEO)/Behavioural/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Morpheo.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Morpheo.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/Morpheo.tex (revision 88) @@ -0,0 +1,42 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\dirdoc{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../../../Behavioural/doc/sty/doc-style} +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +% Créez une page de titre +\maketitle +\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{tex/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/sty/header.sty (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/sty/header.sty (revision 88) @@ -0,0 +1,16 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\title{Morpheo} + +\author{} + +\affiliation{} + +\email{} + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/01_introduction.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/01_introduction.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/01_introduction.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Introduction} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/02_features.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/02_features.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/02_features.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Features} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/03_description.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/03_description.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/03_description.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Functional Description} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/04_pinout.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/04_pinout.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/04_pinout.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Pin out} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/05_parameters.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/05_parameters.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/05_parameters.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Parameters} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/06_performance.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/06_performance.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/06_performance.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Performance} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/07_details.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/07_details.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/07_details.tex (revision 88) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Details} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/08_history.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/08_history.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/08_history.tex (revision 88) @@ -0,0 +1,14 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Revision History} + +\begin{tabular}{|c|c|c|} +\hline +Revision Date & By & Modifications\\ +\hline +\hline +yyyy/mm/dd & xxx & Initial document \\ +\hline +\end{tabular} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/root.tex (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/doc/tex/root.tex (revision 88) @@ -0,0 +1,12 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\input{\dirdoc/01_introduction} +\input{\dirdoc/02_features} +\input{\dirdoc/03_description} +\input{\dirdoc/04_pinout} +\input{\dirdoc/05_parameters} +\input{\dirdoc/06_performance} +\input{\dirdoc/07_details} +\input{\dirdoc/08_history} Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h (revision 88) @@ -0,0 +1,193 @@ +#ifndef morpheo_Morpheo_h +#define morpheo_Morpheo_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#ifdef SYSTEMC +#include "systemc.h" +#endif + +#include "Behavioural/Core/include/Core.h" +#include "Behavioural/Custom/include/Custom.h" +#include "Behavioural/Core/include/Parameters.h" +#include "Behavioural/Configuration/include/Configuration.h" + +#include "TopLevel/include/Types.h" + +#ifdef STATISTICS +#include "Behavioural/include/Stat.h" +#endif +#include "Behavioural/include/Component.h" +#ifdef VHDL +#include "Behavioural/include/Vhdl.h" +#endif +#include "Behavioural/include/Usage.h" + +#include "Common/include/ToString.h" +#include "Common/include/Debug.h" + + +#include + +namespace morpheo { + + class Morpheo +#if SYSTEMC + : public sc_module +#endif + { + // -----[ fields ]---------------------------------------------------- + // Parameters + private : std::string _name; + private : behavioural::Tusage_t _usage; + private : morpheo::behavioural::configuration::Configuration * _config; + private : morpheo::behavioural::core::Parameters * _param_core; +#ifdef STATISTICS + private : morpheo::behavioural::Parameters_Statistics * _param_statistics; + private : behavioural::Stat * _stat; +#endif + + private : behavioural::Component * _component; + private : behavioural::Interfaces * _interfaces; + + // -----[ interface parameters ]-------------------------------------- + public : uint32_t _nb_thread ; + + public : uint32_t _nb_icache_port ; + public : uint32_t _size_icache_thread_id ; + public : uint32_t _size_icache_packet_id ; + public : uint32_t _size_icache_address ; + public : uint32_t _size_icache_type ; + public : uint32_t _size_icache_error ; + public : uint32_t * _icache_nb_instruction ;//[nb_icache_port] + public : uint32_t _size_icache_instruction ; + + public : uint32_t _nb_dcache_port ; + public : uint32_t _size_dcache_thread_id ; + public : uint32_t _size_dcache_packet_id ; + public : uint32_t _size_dcache_address ; + public : uint32_t _size_dcache_data ; + public : uint32_t _size_dcache_type ; + public : uint32_t _size_dcache_error ; + + public : bool _have_port_icache_thread_id; + public : bool _have_port_icache_packet_id; + public : bool _have_port_dcache_thread_id; + public : bool _have_port_dcache_packet_id; + +#ifdef SYSTEMC + // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_CLOCK * in_CLOCK ; + public : SC_IN (Tcontrol_t) * in_NRESET ; + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_REQ_VAL ;//[nb_icache_port] + public : SC_IN (Tcontrol_t ) ** in_ICACHE_REQ_ACK ;//[nb_icache_port] + public : SC_OUT(Ticache_context_t ) ** out_ICACHE_REQ_THREAD_ID ;//[nb_icache_port] + public : SC_OUT(Ticache_packet_t ) ** out_ICACHE_REQ_PACKET_ID ;//[nb_icache_port] + public : SC_OUT(Ticache_address_t ) ** out_ICACHE_REQ_ADDRESS ;//[nb_icache_port] + public : SC_OUT(Ticache_type_t ) ** out_ICACHE_REQ_TYPE ;//[nb_icache_port] + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_ICACHE_RSP_VAL ;//[nb_icache_port] + public : SC_OUT(Tcontrol_t ) ** out_ICACHE_RSP_ACK ;//[nb_icache_port] + public : SC_IN (Ticache_context_t ) ** in_ICACHE_RSP_THREAD_ID ;//[nb_icache_port] + public : SC_IN (Ticache_packet_t ) ** in_ICACHE_RSP_PACKET_ID ;//[nb_icache_port] + public : SC_IN (Ticache_instruction_t) *** in_ICACHE_RSP_INSTRUCTION ;//[nb_icache_port][icache_nb_instruction] + public : SC_IN (Ticache_error_t ) ** in_ICACHE_RSP_ERROR ;//[nb_icache_port] + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_dcache_port] + public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_dcache_port] + public : SC_OUT(Tdcache_context_t ) ** out_DCACHE_REQ_THREAD_ID ;//[nb_dcache_port] + public : SC_OUT(Tdcache_packet_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_dcache_port] + public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_dcache_port] + public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_dcache_port] + public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_dcache_port] + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_dcache_port] + public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_dcache_port] + public : SC_IN (Tdcache_context_t ) ** in_DCACHE_RSP_THREAD_ID ;//[nb_dcache_port] + public : SC_IN (Tdcache_packet_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_dcache_port] + public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_dcache_port] + public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_dcache_port] + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tcontrol_t ) ** in_INTERRUPT_ENABLE ;//[nb_thread] - Interrupt Exception + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + private : morpheo::behavioural::core::Core * _component_core ; + + // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +#endif + + // -----[ Methods ]--------------------------------------------------- + +#ifdef SYSTEMC + SC_HAS_PROCESS (Morpheo); +#endif + public : Morpheo + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif + std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) + ); + public : ~Morpheo (void); + + private : std::string header (void); + + private : void configuration (std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void)); + + private : void allocation ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ); + private : void deallocation (void); + +#ifdef SYSTEMC +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void transition (void); +# endif +#endif + +#if VHDL + private : void vhdl (void); +#endif + +#ifdef STATISTICS + private : void statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics); + private : void statistics_deallocation (void); +#endif +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + private : void end_cycle (void); +#endif + +#ifdef SYSTEMC + public : bool simulation_end (void); +#endif + }; + +}; // end namespace morpheo + +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Types.h (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Types.h (revision 88) @@ -0,0 +1,34 @@ +#ifndef morpheo_Types_h +#define morpheo_Types_h + +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/include/Types.h" + +namespace morpheo { + + // typedef (change namespace) + typedef behavioural::Tcontrol_t Tcontrol_t ; + + typedef behavioural::Tcontext_t Ticache_context_t ; + typedef behavioural::Tpacket_t Ticache_packet_t ; + typedef behavioural::Ticache_address_t Ticache_address_t ; + typedef behavioural::Ticache_instruction_t Ticache_instruction_t; + typedef behavioural::Ticache_type_t Ticache_type_t ; + typedef behavioural::Ticache_error_t Ticache_error_t ; + typedef behavioural::Tcontext_t Ticache_context_t ; + + typedef behavioural::Tcontext_t Tdcache_context_t ; + typedef behavioural::Tpacket_t Tdcache_packet_t ; + typedef behavioural::Tdcache_address_t Tdcache_address_t ; + typedef behavioural::Tdcache_data_t Tdcache_data_t ; + typedef behavioural::Tdcache_type_t Tdcache_type_t ; + typedef behavioural::Tdcache_error_t Tdcache_error_t ; + +}; +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp (revision 88) @@ -0,0 +1,110 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Common/include/Translation.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::Morpheo" + Morpheo::Morpheo + ( +#ifdef SYSTEMC + sc_module_name name, +#else + std::string name, +#endif + std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) + ) + { + translation (); + + log_begin(Morpheo,FUNCTION); + + log_printf(INFO,Morpheo,FUNCTION,_("Configuration")); + configuration (filename_simulator, + filename_generator, + filename_instance, + get_custom_information); + + if (usage_is_set(_usage,USE_HEADER)) + std::cout << header(); + + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Allocation"),_name.c_str()); + + allocation ( +#ifdef STATISTICS + _param_statistics +#endif + ); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Allocation of statistics"),_name.c_str()); + + statistics_allocation(_param_statistics); + } +#endif + +#ifdef VHDL + if (usage_is_set(_usage,USE_VHDL)) + { + // generate the vhdl + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Generate the vhdl"),_name.c_str()); + + vhdl(); + } +#endif + +#ifdef SYSTEMC + if (usage_is_set(_usage,USE_SYSTEMC)) + { + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Method - transition"),_name.c_str()); + + SC_METHOD (transition); + dont_initialize (); + sensitive << (*(in_CLOCK)).pos(); + +# ifdef SYSTEMCASS_SPECIFIC + // List dependency information +# endif + +#endif + } + log_end(Morpheo,FUNCTION); + }; + +#undef FUNCTION +#define FUNCTION "Morpheo::~Morpheo" + Morpheo::~Morpheo (void) + { + log_begin(Morpheo,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + statistics_deallocation(); + } +#endif + + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Deallocation"),_name.c_str()); + deallocation (); + + delete _param_core; + delete _config; + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_allocation.cpp (revision 88) @@ -0,0 +1,294 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { + +#undef FUNCTION +#define FUNCTION "Morpheo::allocation" + void Morpheo::allocation + ( +#ifdef STATISTICS + morpheo::behavioural::Parameters_Statistics * param_statistics +#else + void +#endif + ) + { + log_begin(Morpheo,FUNCTION); + + _component = new behavioural::Component (_usage); + + behavioural::Entity * entity = _component->set_entity (_name + ,"Morpheo" +#ifdef POSITION + ,COMBINATORY +#endif + ); + + _interfaces = entity->set_interfaces(); + + // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + behavioural::Interface * interface = _interfaces->set_interface("" +#ifdef POSITION + ,IN + ,SOUTH, + "Generalist interface" +#endif + ); + + in_CLOCK = interface->set_signal_clk ("clock" ,1, behavioural::CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, behavioural::RESET_VHDL_YES); + } + + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_req",WEST,OUT,_("Request to instruction cache"),_nb_icache_port); + + ALLOC1_VALACK_OUT(out_ICACHE_REQ_VAL ,behavioural::VAL); + ALLOC1_VALACK_IN ( in_ICACHE_REQ_ACK ,behavioural::ACK); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID ,"thread_id",Ticache_context_t ,_size_icache_thread_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID ,"packet_id",Ticache_packet_t ,_size_icache_packet_id); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_address_t ,_size_icache_address ); + ALLOC1_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_size_icache_type ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port); + + ALLOC1_VALACK_IN ( in_ICACHE_RSP_VAL ,behavioural::VAL); + ALLOC1_VALACK_OUT(out_ICACHE_RSP_ACK ,behavioural::ACK); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Ticache_context_t ,_size_icache_thread_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Ticache_packet_t ,_size_icache_packet_id); + ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_size_icache_error); + } + { + ALLOC2_INTERFACE("icache_rsp",WEST,IN ,_("Respons from instruction cache"),_nb_icache_port,_icache_nb_instruction[it1]); + + _ALLOC2_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION ,"instruction",Ticache_instruction_t,_size_icache_instruction,_nb_icache_port,_icache_nb_instruction[it1]); + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_req", OUT, NORTH, _("Request to data cache"),_nb_dcache_port); + + ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,behavioural::VAL); + ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,behavioural::ACK); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t ,_size_dcache_address); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_size_dcache_data); + ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_size_dcache_type); + } + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("dcache_rsp", IN , NORTH, _("Respons from data cache"),_nb_dcache_port); + + ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,behavioural::VAL); + ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,behavioural::ACK); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_THREAD_ID ,"thread_id",Tdcache_context_t ,_size_dcache_thread_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id",Tdcache_packet_t ,_size_dcache_packet_id); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_size_dcache_data); + ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t ,_size_dcache_error); + } + + // ~~~~~[ Interface : "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("interrupt", IN , NORTH, _("Interruption line"),_nb_thread); + + ALLOC1_SIGNAL_IN ( in_INTERRUPT_ENABLE ,"enable",Tcontrol_t ,1); + } + + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + std::string name; + + { + name = _name+"_core"; + log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str()); + + _component_core = new morpheo::behavioural::core::Core + (name.c_str() +#ifdef STATISTICS + ,param_statistics +#endif + ,_param_core + ,_usage); + + _component->set_component (_component_core->_component +#ifdef POSITION + , 50, 50, 10, 10 +#endif + ); + } + + // ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + std::string src,dest; + + // =================================================================== + // =====[ core ]====================================================== + // =================================================================== + { + src = _name+"_core"; + log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); + + // ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"", + dest,""); +#endif + PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK"); + PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET"); + } + + // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_nb_icache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_req_"+toString(i), + dest,"icache_req_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_VAL" , + dest,"out_ICACHE_REQ_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_ICACHE_REQ_"+toString(i)+"_ACK" , + dest, "in_ICACHE_REQ_"+toString(i)+"_ACK" ); + if (_have_port_icache_thread_id) + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID", + dest,"out_ICACHE_REQ_"+toString(i)+"_THREAD_ID"); + if (_have_port_icache_packet_id) + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID", + dest,"out_ICACHE_REQ_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" , + dest,"out_ICACHE_REQ_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_ICACHE_REQ_"+toString(i)+"_TYPE" , + dest,"out_ICACHE_REQ_"+toString(i)+"_TYPE" ); + } + + // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_nb_icache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_rsp_"+toString(i), + dest,"icache_rsp_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_VAL" , + dest, "in_ICACHE_RSP_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_ICACHE_RSP_"+toString(i)+"_ACK" , + dest,"out_ICACHE_RSP_"+toString(i)+"_ACK" ); + if (_have_port_icache_thread_id) + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID", + dest, "in_ICACHE_RSP_"+toString(i)+"_THREAD_ID"); + if (_have_port_icache_packet_id) + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID", + dest, "in_ICACHE_RSP_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_ERROR" , + dest, "in_ICACHE_RSP_"+toString(i)+"_ERROR" ); + + for (uint32_t j=0; j<_icache_nb_instruction[i]; ++j) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"icache_rsp_"+toString(i)+"_"+toString(j), + dest,"icache_rsp_"+toString(i)+"_"+toString(j)); +#endif + + PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION", + dest, "in_ICACHE_RSP_"+toString(i)+"_"+toString(j)+"_INSTRUCTION"); + } + } + + // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_nb_dcache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"dcache_req_"+toString(i), + dest,"dcache_req_"+toString(i)); +#endif + + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_VAL" , + dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_DCACHE_REQ_"+toString(i)+"_ACK" , + dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" ); + if (_have_port_dcache_thread_id) + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID", + dest,"out_DCACHE_REQ_"+toString(i)+"_THREAD_ID"); + if (_have_port_dcache_packet_id) + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID", + dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" , + dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" ); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_WDATA" , + dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" ); + PORT_MAP(_component,src ,"out_DCACHE_REQ_"+toString(i)+"_TYPE" , + dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" ); + } + + // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_nb_dcache_port; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"dcache_rsp_"+toString(i), + dest,"dcache_rsp_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_VAL" , + dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_DCACHE_RSP_"+toString(i)+"_ACK" , + dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" ); + if (_have_port_dcache_thread_id) + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID", + dest, "in_DCACHE_RSP_"+toString(i)+"_THREAD_ID"); + if (_have_port_dcache_packet_id) + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID", + dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID"); + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_RDATA" , + dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" ); + PORT_MAP(_component,src , "in_DCACHE_RSP_"+toString(i)+"_ERROR" , + dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" ); + } + + // ~~~~~[ Interface "interrupt" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_nb_thread; ++i) + { + dest = _name; +#ifdef POSITION + _component->interface_map (src ,"interrupt_"+toString(i), + dest,"interrupt_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_INTERRUPT_"+toString(i)+"_ENABLE", + dest, "in_INTERRUPT_"+toString(i)+"_ENABLE"); + } + } + + + // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + if (DEBUG_Morpheo == true) + _component->test_map(); + +#ifdef POSITION + if (usage_is_set(_usage,USE_POSITION)) + _component->generate_file(); +#endif + + log_end(Morpheo,FUNCTION); + }; +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 88) @@ -0,0 +1,204 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" + +namespace morpheo { + + using namespace behavioural; +// using namespace behavioural::configuration; +// using namespace behavioural::custom; + +#undef FUNCTION +#define FUNCTION "Morpheo::configuration" + void Morpheo::configuration (std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + behavioural::custom::custom_information_t (*get_custom_information) (void)) + { + log_begin(Morpheo,FUNCTION); + + _config = new behavioural::configuration::Configuration (filename_simulator, + filename_generator, + filename_instance, + get_custom_information); + + _name = _config->getName (); + _usage = _config->getUsage(); + + // Test usage + usage_environment(_usage); + +#ifdef STATISTICS + _param_statistics = _config->getParamStatistics(); +#endif + + configuration::Parameters * param = _config->getParam(); + + _param_core = new core::Parameters + ( + param->_size_general_data , + param->_size_special_data , + param->_get_custom_information , + + param->_nb_thread , + param->_size_ifetch_queue , + param->_nb_inst_fetch , + param->_implement_group , + param->_ras_size_queue , + param->_upt_size_queue , + + param->_nb_decod_bloc , + param->_size_decod_queue , + param->_nb_inst_decod , + param->_nb_context_select , + param->_context_select_priority , + param->_context_select_load_balancing , + + param->_nb_rename_bloc , + param->_nb_inst_insert , + param->_nb_inst_retire , + param->_rename_select_priority , + param->_rename_select_load_balancing , + param->_rename_select_nb_front_end_select , + param->_nb_general_register , + param->_nb_special_register , + param->_nb_reg_free , + param->_nb_rename_unit_bank , + param->_size_read_counter , + + param->_nb_read_bloc , + param->_size_read_queue , + param->_size_reservation_station , + param->_nb_inst_retire_reservation_station , + + param->_nb_write_bloc , + param->_size_write_queue , + param->_size_execute_queue , + param->_nb_bypass_write , + + param->_nb_load_store_unit , + param->_size_store_queue , + param->_size_load_queue , + param->_size_speculative_access_queue , + param->_nb_port_check , + param->_speculative_load , + param->_nb_bypass_memory , + param->_nb_cache_port , + param->_nb_inst_memory , + + param->_nb_functionnal_unit , + param->_nb_inst_functionnal_unit , + param->_timing , + + param->_nb_icache_port , + param->_icache_port_priority , + param->_icache_port_load_balancing , + + param->_nb_dcache_port , + param->_dcache_port_priority , + param->_dcache_port_load_balancing , + + param->_nb_front_end , + param->_nb_context , + param->_nb_decod_unit , + param->_nb_inst_branch_predict , + param->_nb_inst_branch_decod , + param->_nb_inst_branch_update , + param->_btb_size_queue , + param->_btb_associativity , + param->_btb_size_counter , + param->_btb_victim_scheme , + param->_dir_predictor_scheme , + param->_dir_have_bht , + param->_dir_bht_size_shifter , + param->_dir_bht_nb_shifter , + param->_dir_have_pht , + param->_dir_pht_size_counter , + param->_dir_pht_nb_counter , + param->_dir_pht_size_address_share , + + param->_nb_ooo_engine , + param->_nb_rename_unit , + param->_nb_inst_issue , + param->_nb_inst_reexecute , + param->_nb_inst_commit , + param->_nb_inst_branch_complete , + param->_nb_rename_unit_select , + param->_nb_execute_loop_select , + param->_size_re_order_buffer , + param->_nb_re_order_buffer_bank , + param->_commit_priority , + param->_commit_load_balancing , + param->_size_issue_queue , + param->_nb_issue_queue_bank , + param->_issue_priority , + param->_issue_load_balancing , + param->_size_reexecute_queue , + param->_reexecute_priority , + param->_reexecute_load_balancing , + + param->_nb_execute_loop , + param->_nb_read_unit , + param->_nb_execute_unit , + param->_nb_write_unit , + param->_nb_gpr_bank , + param->_nb_gpr_port_read_by_bank , + param->_nb_gpr_port_write_by_bank , + param->_nb_spr_bank , + param->_nb_spr_port_read_by_bank , + param->_nb_spr_port_write_by_bank , + param->_execution_unit_to_write_unit_priority , + param->_read_unit_to_execution_unit_priority , + + param->_link_context_with_thread , + param->_link_decod_unit_with_decod_bloc , + param->_link_rename_unit_with_rename_bloc , + param->_link_read_unit_with_read_bloc , + param->_link_write_unit_with_write_bloc , + param->_link_execute_unit_with_functionnal_unit , + param->_link_execute_unit_with_load_store_unit , + param->_link_decod_bloc_with_thread , + param->_link_rename_bloc_with_front_end , + param->_table_dispatch , + param->_link_read_bloc_and_load_store_unit , + param->_link_read_bloc_and_functionnal_unit , + param->_link_write_bloc_and_load_store_unit , + param->_link_write_bloc_and_functionnal_unit , + param->_link_load_store_unit_with_thread , + param->_link_thread_and_functionnal_unit , + param->_link_icache_port_with_thread , + param->_link_dcache_port_with_load_store_unit , + + param->_dispatch_priority , + param->_dispatch_load_balancing ); + + // interface parameters + _nb_thread = _param_core->_nb_thread ; + _nb_icache_port = _param_core->_nb_icache_port ; + _size_icache_thread_id = _param_core->_size_icache_thread_id ; + _size_icache_packet_id = _param_core->_size_icache_packet_id ; + _size_icache_address = _param_core->_size_icache_address ; + _size_icache_type = _param_core->_size_icache_type ; + _size_icache_error = _param_core->_size_icache_error ; + _icache_nb_instruction = _param_core->_icache_nb_instruction ; + _size_icache_instruction = _param_core->_size_instruction ; + _nb_dcache_port = _param_core->_nb_dcache_port ; + _size_dcache_thread_id = _param_core->_size_dcache_thread_id ; + _size_dcache_packet_id = _param_core->_size_dcache_packet_id ; + _size_dcache_address = _param_core->_size_dcache_address ; + _size_dcache_data = _param_core->_size_dcache_data ; + _size_dcache_type = _param_core->_size_dcache_type ; + _size_dcache_error = _param_core->_size_dcache_error ; + _have_port_icache_thread_id = _param_core->_have_port_icache_thread_id; + _have_port_icache_packet_id = _param_core->_have_port_icache_packet_id; + _have_port_dcache_thread_id = _param_core->_have_port_dcache_thread_id; + _have_port_dcache_packet_id = _param_core->_have_port_dcache_packet_id; + + log_end(Morpheo,FUNCTION); + }; +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_deallocation.cpp (revision 88) @@ -0,0 +1,65 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Allocation.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::deallocation" + void Morpheo::deallocation (void) + { + log_begin(Morpheo,FUNCTION); + + if (usage_is_set(_usage,USE_SYSTEMC)) + { + delete in_CLOCK ; + delete in_NRESET; + + DELETE1_SIGNAL(out_ICACHE_REQ_VAL ,_param_core->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_REQ_ACK ,_param_core->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_REQ_THREAD_ID ,_param_core->_nb_icache_port,_param_core->_size_icache_thread_id); + DELETE1_SIGNAL(out_ICACHE_REQ_PACKET_ID ,_param_core->_nb_icache_port,_param_core->_size_icache_packet_id); + DELETE1_SIGNAL(out_ICACHE_REQ_ADDRESS ,_param_core->_nb_icache_port,_param_core->_size_icache_address); + DELETE1_SIGNAL(out_ICACHE_REQ_TYPE ,_param_core->_nb_icache_port,_param_core->_size_icache_type); + + DELETE1_SIGNAL( in_ICACHE_RSP_VAL ,_param_core->_nb_icache_port,1); + DELETE1_SIGNAL(out_ICACHE_RSP_ACK ,_param_core->_nb_icache_port,1); + DELETE1_SIGNAL( in_ICACHE_RSP_THREAD_ID ,_param_core->_nb_icache_port,_param_core->_size_icache_thread_id); + DELETE1_SIGNAL( in_ICACHE_RSP_PACKET_ID ,_param_core->_nb_icache_port,_param_core->_size_icache_packet_id); + DELETE1_SIGNAL( in_ICACHE_RSP_ERROR ,_param_core->_nb_icache_port,_param_core->_size_icache_error); + DELETE2_SIGNAL( in_ICACHE_RSP_INSTRUCTION ,_param_core->_nb_icache_port,_param_core->_icache_nb_instruction[it1],_param_core->_size_instruction); + + DELETE1_SIGNAL(out_DCACHE_REQ_VAL ,_param_core->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_REQ_ACK ,_param_core->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_REQ_THREAD_ID ,_param_core->_nb_dcache_port,_param_core->_size_dcache_thread_id); + DELETE1_SIGNAL(out_DCACHE_REQ_PACKET_ID ,_param_core->_nb_dcache_port,_param_core->_size_dcache_packet_id); + DELETE1_SIGNAL(out_DCACHE_REQ_ADDRESS ,_param_core->_nb_dcache_port,_param_core->_size_dcache_address); + DELETE1_SIGNAL(out_DCACHE_REQ_WDATA ,_param_core->_nb_dcache_port,_param_core->_size_dcache_data); + DELETE1_SIGNAL(out_DCACHE_REQ_TYPE ,_param_core->_nb_dcache_port,_param_core->_size_dcache_type); + + DELETE1_SIGNAL( in_DCACHE_RSP_VAL ,_param_core->_nb_dcache_port,1); + DELETE1_SIGNAL(out_DCACHE_RSP_ACK ,_param_core->_nb_dcache_port,1); + DELETE1_SIGNAL( in_DCACHE_RSP_THREAD_ID ,_param_core->_nb_dcache_port,_param_core->_size_dcache_thread_id); + DELETE1_SIGNAL( in_DCACHE_RSP_PACKET_ID ,_param_core->_nb_dcache_port,_param_core->_size_dcache_packet_id); + DELETE1_SIGNAL( in_DCACHE_RSP_RDATA ,_param_core->_nb_dcache_port,_param_core->_size_dcache_data); + DELETE1_SIGNAL( in_DCACHE_RSP_ERROR ,_param_core->_nb_dcache_port,_param_core->_size_dcache_error); + + DELETE1_SIGNAL( in_INTERRUPT_ENABLE ,_param_core->_nb_thread,1); + } + // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + delete _component; + delete _component_core; + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_end_cycle.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_end_cycle.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_end_cycle.cpp (revision 88) @@ -0,0 +1,37 @@ +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::end_cycle" +void Morpheo::end_cycle () + { + log_begin(Morpheo,FUNCTION); + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + _stat->end_cycle(); +#endif + +#ifdef VHDL_TESTBENCH + // Evaluation before read the ouput signal +// sc_start(0); + if (usage_is_set(_usage,USE_VHDL_TESTBENCH)) + _interfaces->testbench(); +#endif + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_header.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_header.cpp (revision 88) @@ -0,0 +1,66 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Version.h" + +namespace morpheo { + +#undef FUNCTION +#define FUNCTION "Morpheo::header" + std::string Morpheo::header (void) + { + log_begin(Morpheo,FUNCTION); + + std::string str = ""; + + /* + _ + | | + _ __ ___ ___ _ __ _ __ | |__ ___ ___ + | '_ ` _ \ / _ \| '__| '_ \| '_ \ / _ \/ _ \ + | | | | | | (_) | | | |_) | | | | __/ (_) | + |_| |_| |_|\___/|_| | .__/|_| |_|\___|\___/ + | | + |_| + __ + /\ \ + ___ ___ ___ _ __ _____\ \ \___ __ ___ + /' __` __`\ / __`\/\`'__\/\ '__`\ \ _ `\ /'__`\ / __`\ + /\ \/\ \/\ \/\ \L\ \ \ \/ \ \ \L\ \ \ \ \ \/\ __//\ \L\ \ + \ \_\ \_\ \_\ \____/\ \_\ \ \ ,__/\ \_\ \_\ \____\ \____/ + \/_/\/_/\/_/\/___/ \/_/ \ \ \/ \/_/\/_/\/____/\/___/ + \ \_\ + \/_/ + +*/ + + str += toString(MSG_INFORMATION)+" __ \n"; + str += toString(MSG_INFORMATION)+" /\\ \\ \n"; + str += toString(MSG_INFORMATION)+" ___ ___ ___ _ __ _____\\ \\ \\___ __ ___ \n"; + str += toString(MSG_INFORMATION)+" /' __` __`\\ / __`\\/\\`'__\\/\\ '__`\\ \\ _ `\\ /'__`\\ / __`\\ \n"; + str += toString(MSG_INFORMATION)+" /\\ \\/\\ \\/\\ \\/\\ \\L\\ \\ \\ \\/ \\ \\ \\L\\ \\ \\ \\ \\ \\/\\ __//\\ \\L\\ \\\n"; + str += toString(MSG_INFORMATION)+" \\ \\_\\ \\_\\ \\_\\ \\____/\\ \\_\\ \\ \\ ,__/\\ \\_\\ \\_\\ \\____\\ \\____/\n"; + str += toString(MSG_INFORMATION)+" \\/_/\\/_/\\/_/\\/___/ \\/_/ \\ \\ \\/ \\/_/\\/_/\\/____/\\/___/ \n"; + str += toString(MSG_INFORMATION)+" \\ \\_\\ \n"; + str += toString(MSG_INFORMATION)+" \\/_/ \n"; + str += toString(MSG_INFORMATION)+"\n"; + str += toString(MSG_INFORMATION)+_(" * Multiple ORganization of a Processor with HEterogeneous and Open architecture\n"); + str += toString(MSG_INFORMATION)+_(" * Version : ")+toString(MORPHEO_HEADER)+"\n"; + str += toString(MSG_INFORMATION)+_(" * Last change : ")+toString(MORPHEO_DATE )+"\n"; + str += toString(MSG_INFORMATION)+_(" * E-mail support : mathieu.rosiere@lip6.fr\n" ); + str += toString(MSG_INFORMATION)+_(" * Original author(s) : Mathieu Rosière\n" ); + str += toString(MSG_INFORMATION)+_(" * Contributor(s) : Stéphane Dubuisson - XMLLight\n"); + str += toString(MSG_INFORMATION)+_(" Vincent Moulu - VHDL\n" ); + str += toString(MSG_INFORMATION)+"\n"; + + log_end(Morpheo,FUNCTION); + + return str; + }; + +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_simulation_end.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_simulation_end.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_simulation_end.cpp (revision 88) @@ -0,0 +1,24 @@ +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Simulation.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::simulation_end" + bool Morpheo::simulation_end (void) + { + return simulation_test_end(); + }; + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_allocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_allocation.cpp (revision 88) @@ -0,0 +1,31 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::statistics_allocation" + void Morpheo::statistics_allocation (morpheo::behavioural::Parameters_Statistics * param_statistics) + { + log_begin(Morpheo,FUNCTION); + + _stat = new Stat (static_cast(_name), + "Morpheo", + param_statistics); + + _stat->add_stat(_component_core->_stat); + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_deallocation.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_statistics_deallocation.cpp (revision 88) @@ -0,0 +1,29 @@ +#ifdef STATISTICS +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::statistics_deallocation" + void Morpheo::statistics_deallocation (void) + { + log_begin(Morpheo,FUNCTION); + + log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Generate Statistics file"),_name.c_str()); + + delete _stat; + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_transition.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_transition.cpp (revision 88) @@ -0,0 +1,36 @@ +# if defined(STATISTICS) or defined(VHDL_TESTBENCH) +#ifdef SYSTEMC +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Simulation.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::transition" + void Morpheo::transition (void) + { + log_begin(Morpheo,FUNCTION); + +#if defined(STATISTICS) or defined(VHDL_TESTBENCH) + end_cycle (); +#endif + + // Test stop condition + if (simulation_test_end()) + sc_stop(); + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo +# endif +#endif Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_vhdl.cpp (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_vhdl.cpp (revision 88) @@ -0,0 +1,35 @@ +#ifdef VHDL +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "TopLevel/include/Morpheo.h" +#include "Behavioural/include/Vhdl.h" + +namespace morpheo { + + using namespace behavioural; + +#undef FUNCTION +#define FUNCTION "Morpheo::vhdl" + void Morpheo::vhdl (void) + { + log_begin(Morpheo,FUNCTION); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl->generate_file(); + + delete vhdl; + + log_end(Morpheo,FUNCTION); + }; + +}; // end namespace morpheo +#endif Index: trunk/IPs/systemC/processor/Morpheo/locale/en/LC_MESSAGES/morpheo.po =================================================================== --- trunk/IPs/systemC/processor/Morpheo/locale/en/LC_MESSAGES/morpheo.po (revision 88) +++ trunk/IPs/systemC/processor/Morpheo/locale/en/LC_MESSAGES/morpheo.po (revision 88) @@ -0,0 +1,2 @@ +msgid "Read file \"%s\"." +msgstr "Read file \"%s\"." Index: trunk/IPs/systemC/processor/Morpheo/locale/fr/LC_MESSAGES/morpheo.po =================================================================== --- trunk/IPs/systemC/processor/Morpheo/locale/fr/LC_MESSAGES/morpheo.po (revision 87) +++ trunk/IPs/systemC/processor/Morpheo/locale/fr/LC_MESSAGES/morpheo.po (revision 88) @@ -0,0 +1,2 @@ +msgid "Read file \"%s\"." +msgstr "Lecture du fichier \"%s\"." Index: trunk/IPs/systemC/shared/loadexec.c =================================================================== --- trunk/IPs/systemC/shared/loadexec.c (revision 87) +++ (revision ) @@ -1,142 +1,0 @@ -/* - * File : loadexec.c - * Author : Frédéric Pétrot - * - * Load an executable into an array using the GNU BFD - * - * $Log: loadexec.c,v $ - * Revision 1.1.1.1 2006/09/24 23:09:24 kane - * Initalisation de l'arborescence CVS - * - * Revision 1.1 2005/09/20 20:43:43 kane - * Init CVS - * - * Revision 1.1 2003/03/10 10:38:05 fred - * Adding the bfd loader for good. - * - */ - -#include -#include -#include -#include - -#ifndef TRUE -#define TRUE true -#endif - -#ifndef FALSE -#define FALSE false -#endif - -/* Loading the sections sections of file file into the array - * pointed to by emem. - * esize is the expected size, but it can be modified by the function if it too - * small for the sections - * All sizes and addresses are given in bytes - * eoffset is the address of the section with the lowest address among - * all required sections. - * Code should be self explanatory once you've read the 230 pages of - * the BFD documentation :) */ - -typedef struct raminfo { - void *mem; - unsigned int size; - unsigned int ladr; - unsigned int hadr; - const char *file; - const char **sections; -} raminfo; - -static void bindsection(bfd *exec, asection *sect, PTR x) -{ - int i; - raminfo *rinfo = x; - - for (i = 0; rinfo->sections[i]; i++) - if (!strcmp(sect->name, rinfo->sections[i])) - break; - if (!rinfo->sections[i]) - return; - - if ((sect->flags & SEC_LOAD) && !(sect->flags & SEC_IN_MEMORY)) { - bfd_get_section_contents(exec, sect, - rinfo->mem + (sect->vma - rinfo->ladr), - 0, bfd_section_size(exec, sect)); - sect->contents = rinfo->mem; - } -} - -static void sectionssize(bfd *exec, asection *sect, PTR x) -{ - int i; - raminfo *rinfo = x; - - for (i = 0; rinfo->sections[i]; i++) - if (!strcmp(sect->name, rinfo->sections[i])) - break; - if (!rinfo->sections[i]) - return; - - rinfo->size += bfd_section_size(exec, sect); - rinfo->ladr = sect->vma < rinfo->ladr ? sect->vma : rinfo->ladr; - rinfo->hadr = sect->vma + rinfo->size > rinfo->hadr ? - sect->vma + rinfo->size : rinfo->hadr; -} - -void loadexec(void **emem, int *esize, int *eoffset, const char *file, const char **sections) -{ - bfd *exec; - static int x; - int i; - raminfo ringo; - - if (!x) - bfd_init(); - - exec = bfd_openr(file, NULL); - - if (!exec) { - fprintf(stderr, "Cannot open File '%s'\n", file); - exit(1); - } - - if (bfd_check_format(exec, bfd_object) != TRUE && !(exec->flags & EXEC_P)) { - fprintf(stderr, "File %s is not an executable file\n", - bfd_get_filename(exec)); - exit(1); - } - -#if 1 - printf("Loading sections "); - for (i = 0; sections[i]; i++) - printf("%s%s", sections[i], sections[i+1] ? ", " : " "); - printf("from \"%s\"\n",bfd_get_filename(exec)); - //printf("of executable '%s' for '%s' architecture in format '%s'\n", - // bfd_get_filename(exec), bfd_printable_name(exec), exec->xvec->name); -#endif - - /* Set input parameters to bindsection */ - ringo.file = file; - ringo.sections = sections; - ringo.size = 0; - ringo.ladr = ~0; - ringo.hadr = 0; - bfd_map_over_sections(exec, sectionssize, &ringo); - /* Get output parameters from sectionssize */ - if (ringo.size < ringo.hadr - ringo.ladr) - ringo.size = ringo.hadr - ringo.ladr; - *esize = ringo.size > *esize ? ringo.size : *esize; - *eoffset = ringo.ladr; - ringo.mem = malloc(*esize * sizeof(char)); - /* Start over again from the start of the memory */ - bfd_map_over_sections(exec, bindsection, &ringo); - /* Get output parameters from bindsection */ - - *emem = ringo.mem; - - if (bfd_close(exec) == FALSE) { - bfd_perror(exec->filename); - exit(1); - } -} Index: trunk/IPs/systemC/shared/macro.h =================================================================== --- trunk/IPs/systemC/shared/macro.h (revision 87) +++ (revision ) @@ -1,9 +1,0 @@ -#ifndef MACRO_H -#define MACRO_H - -#include "processor/M_CPU/Include/debug.h" -#include "processor/M_CPU/Include/log2.h" - -#define ERROR(msg) do {fprintf(stderr,"<%s> : %s\n",NAME,msg);sc_stop();exit(0);} while(0); - -#endif // !MACRO_H Index: trunk/IPs/systemC/shared/mapping_memory.h =================================================================== --- trunk/IPs/systemC/shared/mapping_memory.h (revision 87) +++ (revision ) @@ -1,1 +1,0 @@ -link /users/cao/kane/Project/Morpheo/Tools/newlib/libgloss/or32/include/mapping_memory.h Index: trunk/IPs/systemC/shared/soclib_caches_interfaces.h =================================================================== --- trunk/IPs/systemC/shared/soclib_caches_interfaces.h (revision 87) +++ (revision ) @@ -1,622 +1,0 @@ - -/************************************************************************************* - * File : caches_interfaces.h - * Date : 27/06/2005 - * Authors : F.Arzel - * Release ; V0.0 - * It is released under the GNU Public License (hopefully). - * - * This file defines a standard "non-blocking cache interface"; separate interfaces - * are defined for non-blocking instruction cache and non-blocking data cache. - *************************************************************************************/ - -#ifndef CACHES_INTERFACES_H -#define CACHES_INTERFACES_H - -#include - -/************************************************************************************* - ******************************** Type ****************************** - *************************************************************************************/ - -// ===== Type Icache ===== -#define ITYPE_READ 0 // 00 -#define ITYPE_LOCK 1 // 01 -#define ITYPE_INVALIDATE 2 // 10 -#define ITYPE_PREFETCH 3 // 11 - -// ===== Type Dcache ===== -#define DTYPE_READ 0 // 000 -#define DTYPE_LOCK 1 // 001 -#define DTYPE_INVALIDATE 2 // 010 -#define DTYPE_PREFETCH 3 // 011 -#define DTYPE_WRITE 4 // 100 -#define DTYPE_WRITE_ACK 5 // 101 -#define DTYPE_FLUSH 6 // 110 - // 111 - -// ===== Size access ===== -#define ACCESS_SIZE 2 -#define ACCESS_8 0 -#define ACCESS_16 1 -#define ACCESS_32 2 -#define ACCESS_64 3 - -// ===== Error ===== -#define ERR_NO 0 // 00 -#define ERR_BUS 1 // 01 -#define ERR_TLB 2 // 10 -#define ERR_UNKNOW 3 // 11 - -// Return the number of bytes of a access -unsigned int access_nb_bytes(sc_uint access) -{ - return 1< - -struct ICACHE_SIGNALS -{ - sc_signal REQ_VAL; - sc_signal REQ_ACK; - sc_signal > REQ_TRDID; - sc_signal > REQ_PKTID; - sc_signal > REQ_ADDR; - sc_signal > REQ_TYPE; - - sc_signal RSP_VAL; - sc_signal RSP_ACK; - sc_signal > RSP_TRDID; - sc_signal > RSP_PKTID; - sc_signal > RSP_INS [NB_ICACHE]; - sc_signal > RSP_ERR; - -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++) - { - sprintf(rename,"%s_RSP_INS [%d]",prefixe,it_nb_icache); - RSP_INS [it_nb_icache].rename(rename); - }//it_nb_icache - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -/*** ICACHE cache ports ***/ - -template< unsigned short TRDID_SIZE, - unsigned short PKTID_SIZE, - unsigned short ADDR_SIZE , - unsigned short INS_SIZE , - unsigned short NB_ICACHE > - -struct ICACHE_CACHE_PORTS -{ - - sc_in REQ_VAL; - sc_out REQ_ACK; - sc_in > REQ_TRDID; - sc_in > REQ_PKTID; - sc_in > REQ_ADDR; - sc_in > REQ_TYPE; - - sc_out RSP_VAL; - sc_in RSP_ACK; - sc_out > RSP_TRDID; - sc_out > RSP_PKTID; - sc_out > RSP_INS [NB_ICACHE]; - sc_out > RSP_ERR; - - void operator () - (ICACHE_SIGNALS &signals) - { - REQ_VAL (signals.REQ_VAL); - REQ_ACK (signals.REQ_ACK); - REQ_TRDID (signals.REQ_TRDID); - REQ_PKTID (signals.REQ_PKTID); - REQ_ADDR (signals.REQ_ADDR); - REQ_TYPE (signals.REQ_TYPE); - - RSP_VAL (signals.RSP_VAL); - RSP_ACK (signals.RSP_ACK); - RSP_TRDID (signals.RSP_TRDID); - RSP_PKTID (signals.RSP_PKTID); - for (unsigned int i = 0; i < NB_ICACHE; i++) - RSP_INS[i] (signals.RSP_INS[i]); - RSP_ERR (signals.RSP_ERR); - }; - - void operator () - (ICACHE_CACHE_PORTS &ports) - { - - REQ_VAL (ports.REQ_VAL); - REQ_ACK (ports.REQ_ACK); - REQ_TRDID (ports.REQ_TRDID); - REQ_PKTID (ports.REQ_PKTID); - REQ_ADDR (ports.REQ_ADDR); - REQ_TYPE (ports.REQ_TYPE); - - RSP_VAL (ports.RSP_VAL); - RSP_ACK (ports.RSP_ACK); - RSP_TRDID (ports.RSP_TRDID); - RSP_PKTID (ports.RSP_PKTID); - for (unsigned int i = 0; i < NB_ICACHE; i++) - RSP_INS[i] (ports.RSP_INS[i]); - RSP_ERR (ports.RSP_ERR); - }; - -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++) - { - sprintf(rename,"%s_RSP_INS [%d]",prefixe,it_nb_icache); - RSP_INS [it_nb_icache].rename(rename); - }//it_nb_icache - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -/*** ICACHE processor ports ***/ - -template< unsigned short TRDID_SIZE, - unsigned short PKTID_SIZE, - unsigned short ADDR_SIZE , - unsigned short INS_SIZE , - unsigned short NB_ICACHE > - -struct ICACHE_PROCESSOR_PORTS -{ - - sc_out REQ_VAL; - sc_in REQ_ACK; - sc_out > REQ_TRDID; - sc_out > REQ_PKTID; - sc_out > REQ_ADDR; - sc_out > REQ_TYPE; - - sc_in RSP_VAL; - sc_out RSP_ACK; - sc_in > RSP_TRDID; - sc_in > RSP_PKTID; - sc_in > RSP_INS [NB_ICACHE]; - sc_in > RSP_ERR; - - void operator () - (ICACHE_SIGNALS &signals) - { - - REQ_VAL (signals.REQ_VAL); - REQ_ACK (signals.REQ_ACK); - REQ_TRDID (signals.REQ_TRDID); - REQ_PKTID (signals.REQ_PKTID); - REQ_ADDR (signals.REQ_ADDR); - REQ_TYPE (signals.REQ_TYPE); - - RSP_VAL (signals.RSP_VAL); - RSP_ACK (signals.RSP_ACK); - RSP_TRDID (signals.RSP_TRDID); - RSP_PKTID (signals.RSP_PKTID); - for (unsigned int i = 0; i < NB_ICACHE; i++) - RSP_INS[i] (signals.RSP_INS[i]); - RSP_ERR (signals.RSP_ERR); - - }; - - void operator () - (ICACHE_PROCESSOR_PORTS &ports) - { - - REQ_VAL (ports.REQ_VAL); - REQ_ACK (ports.REQ_ACK); - REQ_TRDID (ports.REQ_TRDID); - REQ_PKTID (ports.REQ_PKTID); - REQ_ADDR (ports.REQ_ADDR); - REQ_TYPE (ports.REQ_TYPE); - - RSP_VAL (ports.RSP_VAL); - RSP_ACK (ports.RSP_ACK); - RSP_TRDID (ports.RSP_TRDID); - RSP_PKTID (ports.RSP_PKTID); - for (unsigned int i = 0; i < NB_ICACHE; i++) - RSP_INS[i] (ports.RSP_INS[i]); - RSP_ERR (ports.RSP_ERR); - - }; -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - for (unsigned int it_nb_icache = 0; it_nb_icache < NB_ICACHE; it_nb_icache ++) - { - sprintf(rename,"%s_RSP_INS [%d]",prefixe,it_nb_icache); - RSP_INS [it_nb_icache].rename(rename); - }//it_nb_icache - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -/************************************************************************************* - ******************************** DCACHE interface ****************************** - *************************************************************************************/ - -/*** DCACHE signals ***/ - -template< unsigned short TRDID_SIZE, - unsigned short PKTID_SIZE, - unsigned short ADDR_SIZE , - unsigned short DATA_SIZE > - -struct DCACHE_SIGNALS -{ - - sc_signal REQ_VAL; - sc_signal REQ_ACK; - sc_signal > REQ_TRDID; - sc_signal > REQ_PKTID; - sc_signal > REQ_ADDR; - sc_signal > REQ_TYPE; - sc_signal REQ_UNC; - sc_signal > REQ_ACCESS; - sc_signal > REQ_WDATA; - - sc_signal RSP_VAL; - sc_signal RSP_ACK; - sc_signal > RSP_TRDID; - sc_signal > RSP_PKTID; - sc_signal > RSP_RDATA; - sc_signal > RSP_ERR; - -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - sprintf(rename,"%s_REQ_UNC" ,prefixe); - REQ_UNC .rename(rename); - sprintf(rename,"%s_REQ_ACCESS" ,prefixe); - REQ_ACCESS .rename(rename); - sprintf(rename,"%s_REQ_WDATA" ,prefixe); - REQ_WDATA .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - sprintf(rename,"%s_RSP_RDATA" ,prefixe); - RSP_RDATA .rename(rename); - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -/*** DCACHE cache ports ***/ - -template< unsigned short TRDID_SIZE, - unsigned short PKTID_SIZE, - unsigned short ADDR_SIZE, - unsigned short DATA_SIZE > - -struct DCACHE_CACHE_PORTS -{ - sc_in REQ_VAL; - sc_out REQ_ACK; - sc_in > REQ_TRDID; - sc_in > REQ_PKTID; - sc_in > REQ_ADDR; - sc_in > REQ_TYPE; - sc_in REQ_UNC; - sc_in > REQ_ACCESS; - sc_in > REQ_WDATA; - - sc_out RSP_VAL; - sc_in RSP_ACK; - sc_out > RSP_TRDID; - sc_out > RSP_PKTID; - sc_out > RSP_RDATA; - sc_out > RSP_ERR; - - void operator () - (DCACHE_SIGNALS &signals) - { - - REQ_VAL (signals.REQ_VAL); - REQ_ACK (signals.REQ_ACK); - REQ_TRDID (signals.REQ_TRDID); - REQ_PKTID (signals.REQ_PKTID); - REQ_ADDR (signals.REQ_ADDR); - REQ_TYPE (signals.REQ_TYPE); - REQ_UNC (signals.REQ_UNC); - REQ_ACCESS (signals.REQ_ACCESS); - REQ_WDATA (signals.REQ_WDATA); - - RSP_VAL (signals.RSP_VAL); - RSP_ACK (signals.RSP_ACK); - RSP_TRDID (signals.RSP_TRDID); - RSP_PKTID (signals.RSP_PKTID); - RSP_RDATA (signals.RSP_RDATA); - RSP_ERR (signals.RSP_ERR); - - }; - - void operator () - (DCACHE_CACHE_PORTS &ports) - { - - REQ_VAL (ports.REQ_VAL); - REQ_ACK (ports.REQ_ACK); - REQ_TRDID (ports.REQ_TRDID); - REQ_PKTID (ports.REQ_PKTID); - REQ_ADDR (ports.REQ_ADDR); - REQ_TYPE (ports.REQ_TYPE); - REQ_UNC (ports.REQ_UNC); - REQ_ACCESS (ports.REQ_ACCESS); - REQ_WDATA (ports.REQ_WDATA); - - RSP_VAL (ports.RSP_VAL); - RSP_ACK (ports.RSP_ACK); - RSP_TRDID (ports.RSP_TRDID); - RSP_PKTID (ports.RSP_PKTID); - RSP_RDATA (ports.RSP_RDATA); - RSP_ERR (ports.RSP_ERR); - - }; - -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - sprintf(rename,"%s_REQ_UNC" ,prefixe); - REQ_UNC .rename(rename); - sprintf(rename,"%s_REQ_ACCESS" ,prefixe); - REQ_ACCESS .rename(rename); - sprintf(rename,"%s_REQ_WDATA" ,prefixe); - REQ_WDATA .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - sprintf(rename,"%s_RSP_RDATA" ,prefixe); - RSP_RDATA .rename(rename); - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -/*** DCACHE processor ports ***/ - -template< unsigned short TRDID_SIZE, - unsigned short PKTID_SIZE, - unsigned short ADDR_SIZE , - unsigned short DATA_SIZE > - -struct DCACHE_PROCESSOR_PORTS -{ - - sc_out REQ_VAL; - sc_in REQ_ACK; - sc_out > REQ_TRDID; - sc_out > REQ_PKTID; - sc_out > REQ_ADDR; - sc_out > REQ_TYPE; - sc_out REQ_UNC; - sc_out > REQ_ACCESS; - sc_out > REQ_WDATA; - - sc_in RSP_VAL; - sc_out RSP_ACK; - sc_in > RSP_TRDID; - sc_in > RSP_PKTID; - sc_in > RSP_RDATA; - sc_in > RSP_ERR; - - void operator () - (DCACHE_SIGNALS &signals) - { - - REQ_VAL (signals.REQ_VAL); - REQ_ACK (signals.REQ_ACK); - REQ_TRDID (signals.REQ_TRDID); - REQ_PKTID (signals.REQ_PKTID); - REQ_ADDR (signals.REQ_ADDR); - REQ_TYPE (signals.REQ_TYPE); - REQ_UNC (signals.REQ_UNC); - REQ_ACCESS (signals.REQ_ACCESS); - REQ_WDATA (signals.REQ_WDATA); - - RSP_VAL (signals.RSP_VAL); - RSP_ACK (signals.RSP_ACK); - RSP_TRDID (signals.RSP_TRDID); - RSP_PKTID (signals.RSP_PKTID); - RSP_RDATA (signals.RSP_RDATA); - RSP_ERR (signals.RSP_ERR); - - }; - - void operator () - (DCACHE_PROCESSOR_PORTS &ports) - { - - REQ_VAL (ports.REQ_VAL); - REQ_ACK (ports.REQ_ACK); - REQ_TRDID (ports.REQ_TRDID); - REQ_PKTID (ports.REQ_PKTID); - REQ_ADDR (ports.REQ_ADDR); - REQ_TYPE (ports.REQ_TYPE); - REQ_UNC (ports.REQ_UNC); - REQ_ACCESS (ports.REQ_ACCESS); - REQ_WDATA (ports.REQ_WDATA); - - RSP_VAL (ports.RSP_VAL); - RSP_ACK (ports.RSP_ACK); - RSP_TRDID (ports.RSP_TRDID); - RSP_PKTID (ports.RSP_PKTID); - RSP_RDATA (ports.RSP_RDATA); - RSP_ERR (ports.RSP_ERR); - - }; - -#ifdef NONAME_RENAME - void rename (char * prefixe) - { - char rename [100]; - - sprintf(rename,"%s_REQ_VAL" ,prefixe); - REQ_VAL .rename(rename); - sprintf(rename,"%s_REQ_ACK" ,prefixe); - REQ_ACK .rename(rename); - sprintf(rename,"%s_REQ_TRDID" ,prefixe); - REQ_TRDID .rename(rename); - sprintf(rename,"%s_REQ_PKTID" ,prefixe); - REQ_PKTID .rename(rename); - sprintf(rename,"%s_REQ_ADDR" ,prefixe); - REQ_ADDR .rename(rename); - sprintf(rename,"%s_REQ_TYPE" ,prefixe); - REQ_TYPE .rename(rename); - sprintf(rename,"%s_REQ_UNC" ,prefixe); - REQ_UNC .rename(rename); - sprintf(rename,"%s_REQ_ACCESS" ,prefixe); - REQ_ACCESS .rename(rename); - sprintf(rename,"%s_REQ_WDATA" ,prefixe); - REQ_WDATA .rename(rename); - - sprintf(rename,"%s_RSP_VAL" ,prefixe); - RSP_VAL .rename(rename); - sprintf(rename,"%s_RSP_ACK" ,prefixe); - RSP_ACK .rename(rename); - sprintf(rename,"%s_RSP_TRDID" ,prefixe); - RSP_TRDID .rename(rename); - sprintf(rename,"%s_RSP_PKTID" ,prefixe); - RSP_PKTID .rename(rename); - sprintf(rename,"%s_RSP_RDATA" ,prefixe); - RSP_RDATA .rename(rename); - sprintf(rename,"%s_RSP_ERR" ,prefixe); - RSP_ERR .rename(rename); - } -#endif //NONAME_RENAME -}; - -#endif Index: trunk/IPs/systemC/shared/soclib_generic_fifo.h =================================================================== --- trunk/IPs/systemC/shared/soclib_generic_fifo.h (revision 87) +++ (revision ) @@ -1,126 +1,0 @@ - -/************************************************************************** - * File : soclib_generic_fifo.h - * Date : 28/08/2003 - * author : Alain Greiner - * This program is released under the GNU public license - * Copyright : UPMC - LIP6 - * - * This model describes a generic snchronous FIFO. - * The two parameters are the number of bit per word (NBIT) and - * the number of word (NWORD) - * - The 4 methods init(), simple_put(), simple_get(), put_and_get() - * change the internal state of the FIFO, but return no data or status ! - * - The 4 methods rok(), wok(), filled_status() and read() return a - * status or a data, but does not change the FIFO internal state! -***************************************************************************/ - -#ifndef SOCLIB_GENERIC_FIFO_H -#define SOCLIB_GENERIC_FIFO_H - -template - -struct soclib_generic_fifo { - -//////////////////////////// -// internal FIFO registers -//////////////////////////// - -sc_signal > DATA[NWORD]; -sc_signal PTR; -sc_signal PTW; -sc_signal STATE; - -/////////////////////// -// method init() -/////////////////////// -void init() -{ - PTR = 0; - PTW = 0; - STATE = 0; -}; // end init() - -/////////////////////// -// method filled_status() -/////////////////////// - -int filled_status() -{ - return (int)STATE; -}; -//end filled_status() - -/////////////////////// -// method simple_put() -/////////////////////// - -void simple_put(sc_uint din) -{ - if (STATE != NWORD) { - STATE = STATE + 1; - PTW = (PTW + 1) % NWORD; - DATA[PTW] = din; - } -}; // end simple_put() - -/////////////////////// -// method simple_get() -/////////////////////// -void simple_get() -{ - if (STATE != 0) { - STATE = STATE - 1; - PTR = (PTR + 1) % NWORD; - } -}; // end simple_get() - -////////////////////////// -// method put_and_get() -////////////////////////// -void put_and_get(sc_uint din) -{ - if (STATE == NWORD) { - STATE = STATE - 1; - PTR = (PTR + 1) % NWORD; - } else if (STATE == 0) { - STATE = STATE + 1; - PTW = (PTW + 1) % NWORD; - DATA[PTW] = din; - } else { - PTR = (PTR + 1) % NWORD; - PTW = (PTW + 1) % NWORD; - DATA[PTW] = din; - } -}; // end put_and_get() - -//////////////////////// -// method rok() -/////////////////////// -bool rok() -{ - if(STATE != 0) return(true); - else return(false); -}; // end rok() - -//////////////////////// -// method wok() -/////////////////////// -bool wok() -{ - if(STATE != NWORD) return(true); - else return(false); -}; // end wok() - -//////////////////////// -// method read() -/////////////////////// -sc_uint read() -{ - return(DATA[PTR]); -}; // end read() - -}; // end struct generic_fifo - -#endif Index: trunk/IPs/systemC/shared/soclib_segment_table.h =================================================================== --- trunk/IPs/systemC/shared/soclib_segment_table.h (revision 87) +++ trunk/IPs/systemC/shared/soclib_segment_table.h (revision 88) @@ -122,5 +122,5 @@ { printf("segment : %s , base = %.8x , size = %.8x , Global target = %d , Local Target = %d , unc = %d, addr_alloc : %.8x\n", - name, base, size, globalTarget, localTarget, uncached, (unsigned int) addr_alloc); + name, base, size, globalTarget, localTarget, uncached, (unsigned int)((long long)addr_alloc)); }; @@ -295,5 +295,5 @@ { unsigned int offset = (addr-addr_min); - return (void*)((unsigned int)(*segIterator).getAddrAlloc() + offset); + return (void*)((unsigned int)(long long)((*segIterator).getAddrAlloc()) + offset); } } Index: trunk/Makefile.flags =================================================================== --- trunk/Makefile.flags (revision 88) +++ trunk/Makefile.flags (revision 88) @@ -0,0 +1,46 @@ +# +# $Id$ +# +# [ Description ] +# + +#-----[ Simulator ]---------------------------------------- +SIMULATOR = systemcass + +# 3 simulators : +# systemc - SystemC +# systemcass - SystemCASS +# systemcass_deps - Systemcass, and use port dependency information instead of sensitivity list + +#-----[ Flags ]-------------------------------------------- +MORPHEO_FLAGS = -DSYSTEMC \ + -DDEBUG=DEBUG_TRACE \ + -DSTATISTICS \ + -DVHDL \ + -DVHDL_TESTBENCH \ + -DVHDL_TESTBENCH_ASSERT \ + -DTRANSLATION + +# -DPRINT_COLOR \ +# -DLOG_FILE \ +# -DPOSITION \ +# -DREGISTER_INIT \ + +# Flags : +# DEBUG={level} - Print Debug Message +# LOG_FILE - Print Message in a log file +# SYSTEMC - To generate a systemc's model +# VHDL - To generate a vhdl's models +# VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model +# VHDL_TESTBENCH_ASSERT (need VHDL_TESTBENCH) - In the simulation, generate in testbench's file an serie of assert +# POSITION - To generate a position's files (it's input of viewer) +# STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file +# INFORMATION (need STATISTICS) - Instance Information : +# * Static : at the instance creation +# * register number +# * worst way +# * Dynamique : at the runtime +# * consomation +# TRANSLATION - Translate message +# REGISTER_INIT - Init a lot of register +# PRINT_COLOR - Print with colors Index: trunk/Makefile.tools =================================================================== --- trunk/Makefile.tools (revision 87) +++ trunk/Makefile.tools (revision 88) @@ -1,2 +1,10 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile tools +# + #---------------------------------------------------------- #-----[ Unix Commands ]------------------------------------ @@ -6,4 +14,5 @@ ECHO = echo +PRINTF = printf MKDIR = mkdir -p TEST = test @@ -20,25 +29,28 @@ RANLIB = ranlib BASENAME = basename +DIRNAME = dirname GREP = grep GREP_NOT = egrep -v TR = tr UPPERtoLOWER = $(TR) [:lower:] [:upper:] +MSGFMT = msgfmt DISTCC = distcc -CC_FLAGS_COMMON = -O3 \ +CC_FLAGS_COMMON = -O0 \ -g3 \ -Wall \ - -Wunused \ - -m32 + -Wunused \ + -m32 DIST_CXX = export LANG=C; $(DISTCC) g++ -SEQ_CXX = export LANG=C; g++ +SEQ_CXX = export LANG=C; g++ CXX = $(DIST_CXX) CXX_FLAGS = $(CC_FLAGS_COMMON) DIST_CC = export LANG=C; $(DISTCC) gcc -SEQ_CC = export LANG=C; gcc +SEQ_CC = export LANG=C; gcc CC = $(DIST_CC) CC_FLAGS = $(CC_FLAGS_COMMON) SED = sed TOUCH = touch -VALGRIND = valgrind --tool=memcheck --leak-check=yes --show-reachable=yes --leak-resolution=high +#VALGRIND = valgrind --tool=memcheck --leak-check=yes --show-reachable=yes --leak-resolution=high +VALGRIND = valgrind --tool=memcheck # Commands to generate all documents FIG2EPS = fig2dev -L eps @@ -50,4 +62,5 @@ PS2PDF = ps2pdf GNUPLOT = gnuplot +DOT = dot # Commands to view the document VIEWDVI = evince @@ -60,5 +73,9 @@ #---------------------------------------------------------- -include $(MORPHEO_TOPLEVEL)/Makefile.tools_path +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools_path +endif #-----[ systemc ]------------------------------------------ Index: trunk/Makefile.tools_path =================================================================== --- trunk/Makefile.tools_path (revision 87) +++ trunk/Makefile.tools_path (revision 88) @@ -1,27 +1,36 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile path's tools +# + #---------------------------------------------------------- -# kane@HOME +# HOME +#-----[ path ]--------------------------------------------- +#ENV = export PATH=$$PATH:/bin:/usr/bin +#SYSTEMC_systemc = /home/data/Tools/systemc-2.2.0 +#SYSTEMC_systemcass = /home/data/Tools/systemcass +#SYSTEMC_systemcass_deps = $(SYSTEMC_systemcass) +#XILINX = /home/data/Tools/Xilinx91i +#MODELTECH = /home/data/Tools/modelsim/modeltech-6.2b +#MODELTECH_LICENCE = /home/data/Tools/modelsim/license/license_modelsim-SE-6.2b +#OR1K = /home/data/Tools/or32-elf +#NEWLIB = +#QT = + +#---------------------------------------------------------- +# LABS #-----[ path ]--------------------------------------------- ENV = export PATH=$$PATH:/bin:/usr/bin -SYSTEMC_systemc = /home/data/Tools/systemc-2.2.0 -SYSTEMC_systemcass = /home/data/Tools/systemcass +SYSTEMC_systemc = /users/outil/systemc/systemc-2.1.v1 +SYSTEMC_systemcass = /users/outil/systemc/systemcass/systemcass/latest/i686-Linux.SLA4x SYSTEMC_systemcass_deps = $(SYSTEMC_systemcass) -XILINX = /home/data/Tools/Xilinx91i -MODELTECH = /home/data/Tools/modelsim/modeltech-6.2b -MODELTECH_LICENCE = /home/data/Tools/modelsim/license/license_modelsim-SE-6.2b -OR1K = /home/data/Tools/or32-elf +XILINX = /dsk/l1/misc/Xilinx91i +MODELTECH = /users/outil/m1archi/modeltech +#MODELTECH_LICENCE = /users/soft/mentor/mgls_v8-1_0-3-1.ss5/etc/cust/mgc/license.anacad.20070720 +MODELTECH_LICENCE = /users/soft/mentor/mgls_v8-5_0-5-0.ss5/etc/cust/mgc/license.anacad.2008 +OR1K = /users/cao/kane/Softwares/or32-elf NEWLIB = -QT = - -#---------------------------------------------------------- -# kane@LABS -#-----[ path ]--------------------------------------------- -#ENV = export PATH=$$PATH:/bin:/usr/bin -#SYSTEMC_systemc = /users/outil/systemc/systemc-2.1.v1 -#SYSTEMC_systemcass = /users/outil/systemc/systemcass/systemcass/latest/i686-Linux.SLA4x -#SYSTEMC_systemcass_deps = $(SYSTEMC_systemcass) -#XILINX = /dsk/l1/misc/Xilinx91i -#MODELTECH = /users/outil/m1archi/modeltech -#MODELTECH_LICENCE = /users/soft/mentor/mgls_v8-1_0-3-1.ss5/etc/cust/mgc/license.anacad.20070720 -#OR1K = -#NEWLIB = -#QT = /dsk/l1/misc/kane/qt-x11-opensource-4.2.3 +QT = /dsk/l1/misc/kane/qt-x11-opensource-4.2.3 Index: trunk/Platforms/Test/Makefile =================================================================== --- trunk/Platforms/Test/Makefile (revision 88) +++ trunk/Platforms/Test/Makefile (revision 88) @@ -0,0 +1,210 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#---------------------------------------------------------- +#---------------------------------------------------------- +#-----[ Environment ]-------------------------------------- +#---------------------------------------------------------- +#---------------------------------------------------------- +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined") +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools + include $(MORPHEO_TOPLEVEL)/Makefile.flags +endif + +ifeq ($(origin MORPHEO_TMP), undefined) + $(error "variable MORPHEO_TMP is undefined") +endif + +#---------------------------------------------------------- +#---------------------------------------------------------- +#-----[ Directory ]---------------------------------------- +#---------------------------------------------------------- +#---------------------------------------------------------- +ENTITY = Test + +DIR_TMP = $(MORPHEO_TMP) +DIR_INC = include +DIR_SRC = src +DIR_OBJ = $(DIR_TMP)/obj +DIR_BIN = $(DIR_TMP)/bin +DIR_LOG = ./log +DIR_DATA = ./data +DIR_SOFT = $(MORPHEO_TOPLEVEL)/Softwares + +#MORPHEO - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps +#MORPHEO_DIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps +#MORPHEO_INCDIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps +#MORPHEO_LIBDIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps +#MORPHEO_LIBNAME - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps + +#ENVIRONMENT_DIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment/Makefile.deps +#ENVIRONMENT_INCDIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment/Makefile.deps +#ENVIRONMENT_LIBDIR - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment/Makefile.deps +#ENVIRONMENT_LIBNAME - define in $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment/Makefile.deps + +#---------------------------------------------------------- +#---------------------------------------------------------- +#-----[ Variables ]---------------------------------------- +#---------------------------------------------------------- +#---------------------------------------------------------- + +OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) +LOGS = $(patsubst $(DIR_DATA)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA)/*.cfg)) + +EXEC = $(DIR_BIN)/soft.x +EXEC_PREFIX = +#$(VALGRIND) + +#-----[ Compilation ]-------------------------------------- +INCDIR = $(SYSTEMC_INCDIR_$(SIMULATOR)) \ + $(MORPHEO_INCDIR) \ + $(ENVIRONMENT_INCDIR) \ + -I$(DIR_INC) + +LIBDIR = $(SYSTEMC_LIBDIR_$(SIMULATOR)) \ + $(ENVIRONMENT_LIBDIR) \ + $(MORPHEO_LIBDIR) + +LIBNAME = $(ENVIRONMENT_LIBNAME) \ + $(MORPHEO_LIBNAME) \ + $(SYSTEMC_LIBNAME_$(SIMULATOR)) + +FLAGS = $(SYSTEMC_CFLAGS_$(SIMULATOR)) + +PLATFORMS_CXX_FLAGS = $(MORPHEO_FLAGS) $(CXX_FLAGS) $(FLAGS) $(INCDIR) +PLATFORMS_L_FLAGS = $(MORPHEO_FLAGS) $(CXX_FLAGS) $(FLAGS) $(LIBDIR) + +#---------------------------------------------------------- +#---------------------------------------------------------- +#-----[ Rules ]-------------------------------------------- +#---------------------------------------------------------- +#---------------------------------------------------------- + +vpath %.h $(DIR_INC) +vpath %.cpp $(DIR_SRC) +vpath %.o $(DIR_OBJ) +vpath %.cfg $(DIR_DATA) + +.PRECIOUS : $(DIR_OBJ)/%.o $(DIR_BIN)/%.x $(DIR_LOG)/%.log + +all : $(DIR_OBJ) $(DIR_BIN) + @\ + $(MAKE) $(EXEC) + +$(DIR_BIN)/%.x : $(OBJECTS) + @\ + $(ECHO) "Compilation : $*";\ + $(CXX) $(PLATFORMS_L_FLAGS) -o $@ $^ $(LIBNAME); + +run : $(DIR_LOG) all + @\ + $(MAKE) $(LOGS); \ + declare -i have_test_ko=0; \ + for log in $(LOGS); do \ + $(GREP) -q "Test OK" $$log; \ + declare -i test_ok=$$?; \ + $(GREP) -q "Test KO" $$log; \ + declare -i test_ko=$$?; \ + if $(TEST) $$test_ko -eq 0 -o $$test_ok -ne 0; \ + then have_test_ko=1; \ + fi; \ + done; \ + if $(TEST) $$have_test_ko -ne 0; \ + then $(ECHO) "-------------------| Test KO"; exit 1; \ + else $(ECHO) "-------------------| Test OK"; exit 0; \ + fi; + +execute : run + + +$(DIR_LOG)/%.log : %.cfg + @\ + file=$$($(BASENAME) $<); \ + data=$$($(CAT) $<); \ + log=$@; \ + $(ECHO) "Run : $$file"; \ + $(EXEC_PREFIX) $(EXEC) $${data} &> $$log; \ + $(GREP) -q "Test OK" $$log; \ + declare -i test_ok=$$?; \ + $(GREP) -q "Test KO" $$log; \ + declare -i test_ko=$$?; \ + declare timing=$$($(GREP) -h "Timing" $$log); \ + if $(TEST) $$test_ko -ne 0 -a $$test_ok -eq 0; \ + then $(ECHO) -e " $$file ... OK\t$$timing"; \ + else $(ECHO) -e " $$file ... KO\t$$timing"; \ + have_test_ko=1; \ + fi; \ + + +#-----[ Library + Software ]------------------------------- + +lib : + @\ + $(MAKE) --directory=$(ENVIRONMENT_DIR) --makefile=Makefile;\ + $(MAKE) --directory=$(MORPHEO_DIR) --makefile=Makefile; + +soft : + @\ + $(MAKE) --directory=$(DIR_SOFT) --makefile=Makefile; + +#-----[ Rules ]-------------------------------------------- + +$(DIR_OBJ)/%.o : %.cpp + @\ + $(ECHO) "Compilation : $*";\ + $(CXX) $(PLATFORMS_CXX_FLAGS) -c -o $@ $<; + +$(DIR_OBJ) : + @\ + $(ECHO) "Create directory : $@";\ + $(MKDIR) $@ + +$(DIR_BIN) : + @\ + $(ECHO) "Create directory : $@";\ + $(MKDIR) $@ + +$(DIR_LOG) : + @\ + $(ECHO) "Create directory : $@";\ + $(MKDIR) $@ + +#-----[ Clean + help ]------------------------------------- + +clean : + @\ + $(ECHO) "Delete temporary files in directory $(PWD)";\ + $(RM) *~ $(DIR_SRC)/*~ $(DIR_INC)/*~ $(DIR_DATA)/*~ core* tty* \ + $(DIR_OBJ) $(DIR_BIN) $(DIR_LOG); + +clean_all : clean + @\ + $(ECHO) "Delete generated files in directory $(PWD)";\ + $(MAKE) --directory=$(ENVIRONMENT_DIR) --makefile=Makefile clean_all; \ + $(MAKE) --directory=$(MORPHEO_DIR) --makefile=Makefile clean_all; \ + $(MAKE) --directory=$(DIR_SOFT) --makefile=Makefile clean_all; + + +help : + @\ + $(ECHO) " -----[ Common ]-------------------------------------";\ + $(ECHO) "";\ + $(ECHO) " * all (default rules) : create software";\ + $(ECHO) " * run : execute platforms";\ + $(ECHO) " * lib : make library";\ + $(ECHO) " * soft : make software";\ + $(ECHO) " * execute : cf 'make run'";\ + $(ECHO) " * clean : erase temporary files";\ + $(ECHO) " * clean_all : erase generated files";\ + $(ECHO) " * help : print this message";\ + $(ECHO) ""; + +include $(MORPHEO_TOPLEVEL)/IPs/systemC/processor/Morpheo/Makefile.deps +include $(MORPHEO_TOPLEVEL)/IPs/systemC/Environment/Makefile.deps Index: trunk/Platforms/Test/data/Test_000.cfg =================================================================== --- trunk/Platforms/Test/data/Test_000.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_000.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_000/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_001.cfg =================================================================== --- trunk/Platforms/Test/data/Test_001.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_001.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_001/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_002.cfg =================================================================== --- trunk/Platforms/Test/data/Test_002.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_002.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_002/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_003.cfg =================================================================== --- trunk/Platforms/Test/data/Test_003.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_003.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_003/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_004.cfg =================================================================== --- trunk/Platforms/Test/data/Test_004.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_004.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_004/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_005.cfg =================================================================== --- trunk/Platforms/Test/data/Test_005.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_005.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_005/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/data/Test_006.cfg =================================================================== --- trunk/Platforms/Test/data/Test_006.cfg (revision 88) +++ trunk/Platforms/Test/data/Test_006.cfg (revision 88) @@ -0,0 +1,8 @@ +../../IPs/systemC/processor/Morpheo/Files/Morpheo.sim +../../IPs/systemC/processor/Morpheo/Files/Morpheo.gen +../../IPs/systemC/processor/Morpheo/Files/Instance_min.cfg +../../Softwares/Test/Test_006/bin/soft.x +0 +0 +4096 +2 Index: trunk/Platforms/Test/include/test.h =================================================================== --- trunk/Platforms/Test/include/test.h (revision 88) +++ trunk/Platforms/Test/include/test.h (revision 88) @@ -0,0 +1,25 @@ +#ifndef Plateforms_Test_h +#define Plateforms_Test_h +/* + * $Id$ + * + * [ Description ] + * + * Platforms : Morpheo + Environment + */ + +#include "Morpheo.h" +#include + +int test(std::string filename_simulator, + std::string filename_generator, + std::string filename_instance , + std::string filename_software , + uint32_t nb_cache_dedicated, + uint32_t nb_cache_shared , + uint32_t cache_size , + uint32_t cache_ratio , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) + ); + +#endif Index: trunk/Platforms/Test/src/sc_main.cpp =================================================================== --- trunk/Platforms/Test/src/sc_main.cpp (revision 88) +++ trunk/Platforms/Test/src/sc_main.cpp (revision 88) @@ -0,0 +1,69 @@ +/* + * $Id$ + * + * [ Description ] + * + * Platforms : Morpheo + Environment + */ + +#include "../include/test.h" + +using namespace std; +using namespace morpheo; + +void usage (int argc, char * argv[]) +{ + cerr << " " << argv[0] << " list_params." << endl + << "list_params is :" << endl + << " * filename_simulator (string )" << endl + << " * filename_generator (string )" << endl + << " * filename_instance (string )" << endl + << " * filename_software (string )" << endl + << " * nb_cache_dedicated (uint32_t)" << endl + << " * nb_cache_shared (uint32_t)" << endl + << " * size cache L1 (byte) (uint32_t)" << endl + << " * ratio cache (uint32_t)" << endl; + exit (EXIT_FAILURE); +} + +int sc_main (int argc, char * argv[]) +{ + cout << " Begin" << endl; + + for (int32_t i=0; i(argv[x++]); + uint32_t nb_cache_shared = fromString(argv[x++]); + uint32_t cache_size = fromString(argv[x++]); + uint32_t cache_ratio = fromString(argv[x++]); + + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) = NULL; + + int _return = test (filename_simulator , + filename_generator , + filename_instance , + filename_software , + nb_cache_dedicated , + nb_cache_shared , + cache_size , + cache_ratio , + get_custom_information); + + cout << " End" << endl; + + return _return; +} Index: trunk/Platforms/Test/src/test.cpp =================================================================== --- trunk/Platforms/Test/src/test.cpp (revision 88) +++ trunk/Platforms/Test/src/test.cpp (revision 88) @@ -0,0 +1,613 @@ +/* + * $Id$ + * + * [ Description ] + * + * Platforms : Morpheo + Environment + */ + +#define CYCLE_MAX 0 + +#include "../include/test.h" + +#include "Environment.h" +#include "Behavioural/include/Allocation.h" +#include "Common/include/Time.h" +#include "../../../IPs/systemC/shared/mapping_memory.h" +#include "../../../IPs/systemC/processor/Morpheo/Common/include/Test.h" + +using namespace std; +using namespace environment; +using namespace morpheo; + +int test(string filename_simulator, + string filename_generator, + string filename_instance , + string filename_software , + uint32_t nb_cache_dedicated, + uint32_t nb_cache_shared , + uint32_t cache_size , + uint32_t cache_ratio , + morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) + ) +{ + //============================================================================== + //===== [ DECLARATION ]========================================================= + //============================================================================== + + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + // 1) Translation + if (setlocale (LC_ALL, "") == NULL) + { + cerr << "Error setlocale." << endl; + exit (EXIT_FAILURE); + } + + // 2) Morpheo Construction + Morpheo * morpheo = new Morpheo + ("morpheo", + filename_simulator, + filename_generator, + filename_instance , + get_custom_information + ); + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + uint32_t nb_entity = 1; + + // Cache access + uint32_t * iaccess_nb_context = new uint32_t [nb_entity]; + uint32_t * iaccess_nb_instruction= new uint32_t [nb_entity]; + uint32_t * iaccess_nb_packet = new uint32_t [nb_entity]; + uint32_t * iaccess_size_address = new uint32_t [nb_entity]; + uint32_t * iaccess_size_data = new uint32_t [nb_entity]; + + uint32_t * daccess_nb_context = new uint32_t [nb_entity]; + uint32_t * daccess_nb_packet = new uint32_t [nb_entity]; + uint32_t * daccess_size_address = new uint32_t [nb_entity]; + uint32_t * daccess_size_data = new uint32_t [nb_entity]; + + uint32_t * buffer_irsp_size = new uint32_t [nb_entity]; + uint32_t * buffer_drsp_size = new uint32_t [nb_entity]; + + for (uint32_t i=0; i_nb_thread; + iaccess_nb_instruction [i] = max(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port); + iaccess_nb_packet [i] = 1<_size_icache_packet_id; + iaccess_size_address [i] = morpheo->_size_icache_address; + iaccess_size_data [i] = morpheo->_size_icache_instruction; + + daccess_nb_context [i] = morpheo->_nb_thread; + daccess_nb_packet [i] = 1<_size_dcache_packet_id; + daccess_size_address [i] = morpheo->_size_dcache_address; + daccess_size_data [i] = morpheo->_size_dcache_data; + + buffer_irsp_size [i] = 8; + buffer_drsp_size [i] = 8; + } + + uint32_t cache_nb_line ; + uint32_t cache_size_line ; + uint32_t cache_size_word ; + uint32_t cache_associativity ; + uint32_t cache_hit_latence ; + uint32_t cache_miss_penality ; + + // Instruction/Data cache + uint32_t * icache_nb_level = new uint32_t [nb_entity]; + uint32_t * icache_nb_port = new uint32_t [nb_entity]; + uint32_t ** icache_nb_line = new uint32_t * [nb_entity]; + uint32_t ** icache_size_line = new uint32_t * [nb_entity]; + uint32_t ** icache_size_word = new uint32_t * [nb_entity]; + uint32_t ** icache_associativity = new uint32_t * [nb_entity]; + uint32_t ** icache_hit_latence = new uint32_t * [nb_entity]; + uint32_t ** icache_miss_penality = new uint32_t * [nb_entity]; + + uint32_t * dcache_nb_level = new uint32_t [nb_entity]; + uint32_t * dcache_nb_port = new uint32_t [nb_entity]; + uint32_t ** dcache_nb_line = new uint32_t * [nb_entity]; + uint32_t ** dcache_size_line = new uint32_t * [nb_entity]; + uint32_t ** dcache_size_word = new uint32_t * [nb_entity]; + uint32_t ** dcache_associativity = new uint32_t * [nb_entity]; + uint32_t ** dcache_hit_latence = new uint32_t * [nb_entity]; + uint32_t ** dcache_miss_penality = new uint32_t * [nb_entity]; + + for (uint32_t i=0; i(morpheo->_icache_nb_instruction,morpheo->_nb_icache_port)*morpheo->_size_icache_instruction,morpheo->_size_dcache_data)/8; + cache_size_line = 8; + + if (cache_size<(cache_size_line*cache_size_word)) + { + cerr << "cache is too small" << endl; + exit(EXIT_FAILURE); + } + + cache_nb_line = cache_size/(cache_size_line*cache_size_word); + cache_associativity = 1; + cache_hit_latence = 1; + cache_miss_penality = 5; + + icache_nb_level [i] = nb_cache_dedicated; + icache_nb_port [i] = morpheo->_nb_icache_port; + icache_nb_line [i] = new uint32_t [icache_nb_level[i]]; + icache_size_line [i] = new uint32_t [icache_nb_level[i]]; + icache_size_word [i] = new uint32_t [icache_nb_level[i]]; + icache_associativity [i] = new uint32_t [icache_nb_level[i]]; + icache_hit_latence [i] = new uint32_t [icache_nb_level[i]]; + icache_miss_penality [i] = new uint32_t [icache_nb_level[i]]; + + dcache_nb_level [i] = icache_nb_level [i]; + dcache_nb_port [i] = morpheo->_nb_dcache_port; + dcache_nb_line [i] = new uint32_t [dcache_nb_level[i]]; + dcache_size_line [i] = new uint32_t [dcache_nb_level[i]]; + dcache_size_word [i] = new uint32_t [dcache_nb_level[i]]; + dcache_associativity [i] = new uint32_t [dcache_nb_level[i]]; + dcache_hit_latence [i] = new uint32_t [dcache_nb_level[i]]; + dcache_miss_penality [i] = new uint32_t [dcache_nb_level[i]]; + + for (uint32_t j=0; jsetMSBNumber (8); + segtable->setDefaultTarget(0,0); + + // Add a segment ,name ,address of base ,size ,global index,local index,uncache + segtable->addSegment("text" ,TEXT_BASE ,TEXT_SIZE ,0 ,0 ,false); + segtable->addSegment("data" ,DATA_CACHED_BASE ,DATA_CACHED_SIZE ,0 ,0 ,false); + segtable->addSegment("data_unc",DATA_UNCACHED_BASE,DATA_UNCACHED_SIZE,0 ,0 ,true ); + + Parameters * param_environment = new Parameters + (nb_entity, + + iaccess_nb_context, + iaccess_nb_instruction, + iaccess_nb_packet, + iaccess_size_address, + iaccess_size_data, + + daccess_nb_context, + daccess_nb_packet, + daccess_size_address, + daccess_size_data, + + buffer_irsp_size, + buffer_drsp_size, + + icache_nb_level , + icache_nb_port , + icache_nb_line , + icache_size_line , + icache_size_word , + icache_associativity, + icache_hit_latence , + icache_miss_penality, + dcache_nb_level , + dcache_nb_port , + dcache_nb_line , + dcache_size_line , + dcache_size_word , + dcache_associativity, + dcache_hit_latence , + dcache_miss_penality, + + nb_cache_shared , +// cache_shared_nb_port , + cache_shared_nb_line , + cache_shared_size_line , + cache_shared_size_word , + cache_shared_associativity , + cache_shared_hit_latence , + cache_shared_miss_penality , + + nb_component_tty, + tty_address, + nb_tty, + name_tty, + false, + + nb_component_ramlock, + ramlock_address, + nb_lock, + + sim2os_address, + sim2os_size, + segtable + ); + + cout << param_environment->print(0) << endl; + + segtable->print(); + + Environment * environment = new Environment ("environment",param_environment); + + const char * sections_text [] = {".text",NULL}; + const char * sections_data [] = {".data",".rodata",".bss",".sdata",".sbss", NULL}; + + if (environment->init("text" , filename_software.c_str(), sections_text) == false) exit (EXIT_FAILURE); + if (environment->init("data" , filename_software.c_str(), sections_data) == false) exit (EXIT_FAILURE); + + //============================================================================== + //===== [ SIGNAL ]============================================================== + //============================================================================== + + sc_clock * CLOCK = new sc_clock ("clock", 1.0, 0.5); + sc_signal * NRESET = new sc_signal ("NRESET"); + + ALLOC1_SC_SIGNAL(ICACHE_REQ_VAL ,"ICACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_REQ_ACK ,"ICACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,"ICACHE_REQ_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,"ICACHE_REQ_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,"ICACHE_REQ_ADDRESS ",Ticache_address_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_REQ_TYPE ,"ICACHE_REQ_TYPE ",Ticache_type_t ,morpheo->_nb_icache_port); + + ALLOC1_SC_SIGNAL(ICACHE_RSP_VAL ,"ICACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_RSP_ACK ,"ICACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,"ICACHE_RSP_THREAD_ID ",Ticache_context_t ,morpheo->_nb_icache_port); + ALLOC1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,"ICACHE_RSP_PACKET_ID ",Ticache_packet_t ,morpheo->_nb_icache_port); + ALLOC2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,"ICACHE_RSP_INSTRUCTION",Ticache_instruction_t,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]); + ALLOC1_SC_SIGNAL(ICACHE_RSP_ERROR ,"ICACHE_RSP_ERROR ",Ticache_error_t ,morpheo->_nb_icache_port); + + ALLOC1_SC_SIGNAL(DCACHE_REQ_VAL ,"DCACHE_REQ_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_ACK ,"DCACHE_REQ_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,"DCACHE_REQ_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,"DCACHE_REQ_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,"DCACHE_REQ_ADDRESS ",Tdcache_address_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_WDATA ,"DCACHE_REQ_WDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_REQ_TYPE ,"DCACHE_REQ_TYPE ",Tdcache_type_t ,morpheo->_nb_dcache_port); + + ALLOC1_SC_SIGNAL(DCACHE_RSP_VAL ,"DCACHE_RSP_VAL ",Tcontrol_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_RSP_ACK ,"DCACHE_RSP_ACK ",Tcontrol_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,"DCACHE_RSP_THREAD_ID ",Tdcache_context_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,"DCACHE_RSP_PACKET_ID ",Tdcache_packet_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_RSP_RDATA ,"DCACHE_RSP_RDATA ",Tdcache_data_t ,morpheo->_nb_dcache_port); + ALLOC1_SC_SIGNAL(DCACHE_RSP_ERROR ,"DCACHE_RSP_ERROR ",Tdcache_error_t ,morpheo->_nb_dcache_port); + + ALLOC1_SC_SIGNAL(INTERRUPT_ENABLE ,"INTERRUPT_ENABLE ",Tcontrol_t ,morpheo->_nb_thread); + + //============================================================================== + //===== [ INSTANCE ]============================================================ + //============================================================================== + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~ [ Morpheo ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + (*(morpheo->in_CLOCK)) (*(CLOCK)); + (*(morpheo->in_NRESET)) (*(NRESET)); + + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_VAL ,ICACHE_REQ_VAL ,morpheo->_nb_icache_port); + _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_REQ_ACK ,ICACHE_REQ_ACK ,morpheo->_nb_icache_port); + if (morpheo->_have_port_icache_thread_id) + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_THREAD_ID ,ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port); + if (morpheo->_have_port_icache_packet_id) + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_PACKET_ID ,ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_ADDRESS ,ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_REQ_TYPE ,ICACHE_REQ_TYPE ,morpheo->_nb_icache_port); + + _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_VAL ,ICACHE_RSP_VAL ,morpheo->_nb_icache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_ICACHE_RSP_ACK ,ICACHE_RSP_ACK ,morpheo->_nb_icache_port); + if (morpheo->_have_port_icache_thread_id) + _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_THREAD_ID ,ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port); + if (morpheo->_have_port_icache_packet_id) + _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_PACKET_ID ,ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port); + _INSTANCE2_SC_SIGNAL(morpheo, in_ICACHE_RSP_INSTRUCTION ,ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]); + _INSTANCE1_SC_SIGNAL(morpheo, in_ICACHE_RSP_ERROR ,ICACHE_RSP_ERROR ,morpheo->_nb_icache_port); + + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_VAL ,DCACHE_REQ_VAL ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_REQ_ACK ,DCACHE_REQ_ACK ,morpheo->_nb_dcache_port); + if (morpheo->_have_port_dcache_thread_id) + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_THREAD_ID ,DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port); + if (morpheo->_have_port_dcache_packet_id) + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_PACKET_ID ,DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_ADDRESS ,DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_WDATA ,DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_REQ_TYPE ,DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port); + + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_VAL ,DCACHE_RSP_VAL ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo,out_DCACHE_RSP_ACK ,DCACHE_RSP_ACK ,morpheo->_nb_dcache_port); + if (morpheo->_have_port_dcache_thread_id) + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_THREAD_ID ,DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port); + if (morpheo->_have_port_dcache_packet_id) + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_PACKET_ID ,DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_RDATA ,DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port); + _INSTANCE1_SC_SIGNAL(morpheo, in_DCACHE_RSP_ERROR ,DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port); + + _INSTANCE1_SC_SIGNAL(morpheo, in_INTERRUPT_ENABLE ,INTERRUPT_ENABLE ,morpheo->_nb_thread); + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~ [ Environment ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + (*(environment->CLOCK)) (*(CLOCK)); + (*(environment->NRESET)) (*(NRESET)); + + for (uint32_t i=0; i_nb_icache_port; ++i) + { + (*(environment->ICACHE_REQ_VAL [0][i] )) (*(ICACHE_REQ_VAL [i] )); + (*(environment->ICACHE_REQ_ACK [0][i] )) (*(ICACHE_REQ_ACK [i] )); + (*(environment->ICACHE_REQ_CONTEXT_ID [0][i] )) (*(ICACHE_REQ_THREAD_ID [i] )); + (*(environment->ICACHE_REQ_PACKET_ID [0][i] )) (*(ICACHE_REQ_PACKET_ID [i] )); + (*(environment->ICACHE_REQ_ADDRESS [0][i] )) (*(ICACHE_REQ_ADDRESS [i] )); + (*(environment->ICACHE_REQ_TYPE [0][i] )) (*(ICACHE_REQ_TYPE [i] )); + + (*(environment->ICACHE_RSP_VAL [0][i] )) (*(ICACHE_RSP_VAL [i] )); + (*(environment->ICACHE_RSP_ACK [0][i] )) (*(ICACHE_RSP_ACK [i] )); + (*(environment->ICACHE_RSP_CONTEXT_ID [0][i] )) (*(ICACHE_RSP_THREAD_ID [i] )); + (*(environment->ICACHE_RSP_PACKET_ID [0][i] )) (*(ICACHE_RSP_PACKET_ID [i] )); + (*(environment->ICACHE_RSP_ERROR [0][i] )) (*(ICACHE_RSP_ERROR [i] )); + + for (uint32_t j=0; j_icache_nb_instruction[i]; ++j) + (*(environment->ICACHE_RSP_INSTRUCTION [0][i][j])) (*(ICACHE_RSP_INSTRUCTION [i][j])); + } + for (uint32_t i=0; i_nb_dcache_port; ++i) + { + (*(environment->DCACHE_REQ_VAL [0][i] )) (*(DCACHE_REQ_VAL [i] )); + (*(environment->DCACHE_REQ_ACK [0][i] )) (*(DCACHE_REQ_ACK [i] )); + (*(environment->DCACHE_REQ_CONTEXT_ID [0][i] )) (*(DCACHE_REQ_THREAD_ID [i] )); + (*(environment->DCACHE_REQ_PACKET_ID [0][i] )) (*(DCACHE_REQ_PACKET_ID [i] )); + (*(environment->DCACHE_REQ_ADDRESS [0][i] )) (*(DCACHE_REQ_ADDRESS [i] )); + (*(environment->DCACHE_REQ_WDATA [0][i] )) (*(DCACHE_REQ_WDATA [i] )); + (*(environment->DCACHE_REQ_TYPE [0][i] )) (*(DCACHE_REQ_TYPE [i] )); + + (*(environment->DCACHE_RSP_VAL [0][i] )) (*(DCACHE_RSP_VAL [i] )); + (*(environment->DCACHE_RSP_ACK [0][i] )) (*(DCACHE_RSP_ACK [i] )); + (*(environment->DCACHE_RSP_CONTEXT_ID [0][i] )) (*(DCACHE_RSP_THREAD_ID [i] )); + (*(environment->DCACHE_RSP_PACKET_ID [0][i] )) (*(DCACHE_RSP_PACKET_ID [i] )); + (*(environment->DCACHE_RSP_RDATA [0][i] )) (*(DCACHE_RSP_RDATA [i] )); + (*(environment->DCACHE_RSP_ERROR [0][i] )) (*(DCACHE_RSP_ERROR [i] )); + } + +//_INSTANCE2_SC_SIGNAL(environment,INTERRUPT_ENABLE ,1,morpheo->_nb_thread); + + //============================================================================== + //===== [ SIMULATION ]========================================================== + //============================================================================== + + // initialisation + cerr << " Simulation Init" << endl; + + sc_start(0); + + cerr << " Simulation Start" << endl; + + Time * _time_global = new Time(); + + for (uint32_t i=0; i_nb_thread; ++i) + INTERRUPT_ENABLE[i]->write(0); + + NRESET->write(0); + SC_START(5); + NRESET->write(1); + + // Infinite loop + do + { +// Time * _time_local = new Time(); + SC_START(100000); +// delete _time_local; + } while (not morpheo ->simulation_end() and // morpheo condition stop + not environment->simulation_end()); // test ok + delete _time_global; + + bool morpheo_end = morpheo->simulation_end(); + bool environment_end = environment->simulation_end(); + + + //============================================================================== + //===== [ DESTRUCTION ]========================================================= + //============================================================================== + + delete CLOCK; + delete NRESET; + + DELETE1_SC_SIGNAL(ICACHE_REQ_VAL ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_REQ_ACK ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_REQ_THREAD_ID ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_REQ_PACKET_ID ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_REQ_ADDRESS ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_REQ_TYPE ,morpheo->_nb_icache_port); + + DELETE1_SC_SIGNAL(ICACHE_RSP_VAL ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_RSP_ACK ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_RSP_THREAD_ID ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_RSP_PACKET_ID ,morpheo->_nb_icache_port); + DELETE1_SC_SIGNAL(ICACHE_RSP_ERROR ,morpheo->_nb_icache_port); + DELETE2_SC_SIGNAL(ICACHE_RSP_INSTRUCTION ,morpheo->_nb_icache_port,morpheo->_icache_nb_instruction[it1]); + + DELETE1_SC_SIGNAL(DCACHE_REQ_VAL ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_ACK ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_THREAD_ID ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_PACKET_ID ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_ADDRESS ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_WDATA ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_REQ_TYPE ,morpheo->_nb_dcache_port); + + DELETE1_SC_SIGNAL(DCACHE_RSP_VAL ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_RSP_ACK ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_RSP_THREAD_ID ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_RSP_PACKET_ID ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_RSP_RDATA ,morpheo->_nb_dcache_port); + DELETE1_SC_SIGNAL(DCACHE_RSP_ERROR ,morpheo->_nb_dcache_port); + + DELETE1_SC_SIGNAL(INTERRUPT_ENABLE ,morpheo->_nb_thread); + + delete morpheo; + + delete environment; + + delete param_environment; + delete segtable; + + delete [] nb_lock ; + delete [] ramlock_address; + for (uint32_t i=0;i Simulation End : Unknow" << endl; + } + else + { + if (morpheo_end) + cout << " Simulation End : MORPHEO" << endl; + if (environment_end) + { + cout << " Simulation End : ENVIRONMENT" << endl; + test_ok = true; + } + } + + if (test_ok) + { + cout << STR_OK << endl; + return EXIT_SUCCESS; + } + else + { + cout << STR_KO << endl; + return EXIT_FAILURE; + } +} Index: trunk/Softwares/Basic_test/Makefile =================================================================== --- trunk/Softwares/Basic_test/Makefile (revision 88) +++ trunk/Softwares/Basic_test/Makefile (revision 88) @@ -0,0 +1,130 @@ +# common definition +include Makefile.morpheo + +#-----[ Directory ]--------------------------------------------------------------- + +DIR_LOCAL = . +DIR_LOCAL_C = $(DIR_LOCAL)/src/c +DIR_LOCAL_ASM = $(DIR_LOCAL)/src/asm +DIR_LOCAL_SYS = $(DIR_LOCAL)/src/sys +DIR_LOCAL_INC = $(DIR_LOCAL)/src/c/include + +DIR_GLOBAL = $(SOFT)/Global.or32 +DIR_GLOBAL_C = $(DIR_GLOBAL)/src/c +DIR_GLOBAL_ASM = $(DIR_GLOBAL)/src/asm +DIR_GLOBAL_SYS = $(DIR_GLOBAL)/src/sys +DIR_GLOBAL_INC = $(DIR_GLOBAL)/include + +DIR_INC = -I$(DIR_LOCAL_INC) -I$(DIR_GLOBAL_INC) +DIR_OBJ = obj +DIR_BIN = bin + +EXE = soft + +#-----[ Files ]------------------------------------------------------------------- +OBJ_ASM = $(patsubst $(DIR_LOCAL_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_ASM)/*.s)) \ + $(patsubst $(DIR_GLOBAL_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_ASM)/*.s)) +OBJ_SYS = $(patsubst $(DIR_LOCAL_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_SYS)/*.s)) \ + $(patsubst $(DIR_GLOBAL_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_SYS)/*.s)) +OBJ_C = $(patsubst $(DIR_LOCAL_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_LOCAL_C)/*.c)) \ + $(patsubst $(DIR_GLOBAL_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_GLOBAL_C)/*.c)) + +OBJ = $(OBJ_SYS) $(OBJ_ASM) $(OBJ_C) + +#-----[ Rules ]------------------------------------------------------------------- +.PRECIOUS : $(DIR_BIN)/%.x $(DIR_OBJ)/%.o $(DIR_OBJ)/%.a + +all : test_env $(DIR_BIN)/$(EXE).x.txt + +$(DIR_BIN)/%.x.txt : $(DIR_BIN)/%.x + @\ + $(ECHO) "List symbols of $*";\ + $(NM) $(NM_OPT) $^ > $@.nm;\ + $(ECHO) "Display information of $*";\ + $(OBJDUMP) $(OBJDUMP_OPT) $^ > $@; + +$(DIR_BIN)/%.x : $(OBJ_SYS) $(OBJ) + @\ + $(ECHO) "Linkage of $*";\ + $(LD) -o $@ $^ $(LD_OPT); + +$(DIR_OBJ)/%.o : $(DIR_LOCAL_ASM)/%.s + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; +# @$(AS) $(AS_OPT) $^ -o $@ + +$(DIR_OBJ)/%.o : $(DIR_LOCAL_SYS)/%.s + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; +# @$(AS) $(AS_OPT) $^ -o $@ + +$(DIR_OBJ)/%.o : $(DIR_LOCAL_C)/%.c + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; + +$(DIR_OBJ)/%.o : $(DIR_GLOBAL_ASM)/%.s + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; +# @$(AS) $(AS_OPT) $^ -o $@ + +$(DIR_OBJ)/%.o : $(DIR_GLOBAL_SYS)/%.s + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; +# @$(AS) $(AS_OPT) $^ -o $@ + +$(DIR_OBJ)/%.o : $(DIR_GLOBAL_C)/%.c + @\ + $(ECHO) "Compile of $*";\ + $(CC) $(CC_OPT) $(DIR_INC) -o $@ -c $^ ;\ + $(CC) $(CC_OPT) $(DIR_INC) -S -o $@.s -c $^ ; + +#-----[ Environement ]------------------------------------------------------------ +test_env : +# ifeq ($(origin TOOLS), undefined) +# $(error "variable TOOLS is undefined"); +# endif +# ifeq ($(origin SOFT), undefined) +# $(error "variable SOFT is undefined"); +# endif + @$(MKDIR) $(DIR_OBJ) $(DIR_BIN) + +#-----[ Maintenance ]------------------------------------------------------------- +clean : + @\ + $(ECHO) "Delete temporary files "`$(PWD)`;\ + $(RM) $(DIR_OBJ) $(DIR_BIN);\ + $(MAKE) clean_rec DIR_CLEAN=.; + +#Clean recursive +clean_rec : + @\ + $(ECHO) "Delete temporary files in directory $(DIR_CLEAN)";\ + $(RM) -f $(DIR_CLEAN)/*~;\ + for files in `$(LS) $(DIR_CLEAN)`; do \ + if $(TEST) -d $(DIR_CLEAN)/$$files; \ + then \ + $(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files; \ + fi; \ + done; + +#-----[ Help ]-------------------------------------------------------------------- +help : + @\ + $(ECHO) "";\ + $(ECHO) "List of directive : ";\ + $(ECHO) " * make : Compile the software";\ + $(ECHO) " * make clean : Erase all files generates";\ + $(ECHO) " * make bench_list : View all benchmark";\ + $(ECHO) " * make bench_exec : Print the file \"$(FILE_BENCH)\" - it's the Workload";\ + $(ECHO) " * make bench : Compile the Benchmark Suite";\ + $(ECHO) ""; Index: trunk/Softwares/Basic_test/Makefile.morpheo =================================================================== --- trunk/Softwares/Basic_test/Makefile.morpheo (revision 88) +++ trunk/Softwares/Basic_test/Makefile.morpheo (revision 88) @@ -0,0 +1,53 @@ +#-----[ Usual commands ]---------------------------------------------------------- +RM = rm -fr +MKDIR = mkdir -p +ECHO = echo +CCACHE = +LS = ls +TEST = test +CAT = cat +READ = read +SED = sed +MAKE = make -s +CD = cd +PWD = pwd + +#-----[ Directory ]--------------------------------------------------------------- +DIR_LDSCRIPT = $(TOOLS)/newlib/libgloss/or32 + +DIR_INCLUDE = -I$(TOOLS)/newlib/newlib/libc/include/ \ + -I$(TOOLS)/newlib/libgloss/or32/include/ +DIR_LIBRARY = -L$(TOOLS)/newlib/or32-elf/newlib/ \ + -L$(TOOLS)/newlib/or32-elf/libgloss/or32/ \ + -L$(TOOLS)/or1k/lib/gcc/or32-elf/3.4.4/ + +#-----[ To the compilation ]------------------------------------------------------ +OPTIMIZE = -O3 -fomit-frame-pointer -fdelayed-branch -mror -mcmov -msext -mhard-mul -msoft-div -msoft-float +#Option : +# -fomit-frame-pointer : n'utilise pas le pointeur de frame +# -fdelayed-branch : utilise les delayed slot +# ON OFF +# -mror -mno-ror : utilisation de l'instruction l.ror +# -mcmov -mno-cmov : utilisation de l'instruction l.cmov +# -msext -mno-sext : utilisation des instructions l.extXX +# -mhard-mul -msoft-mul : utilisation du multiplieur materiel +# -mhard-div -msoft-div : utilisation du diviseur materiel +# -mhard-float -msoft-float : utilisation du flottant materiel +# -msibcall -mno-sibcall : Enable sibcall optimization +# -mlogue -mno-logue : Schedule pro/epi-logue. +# -maj -mno-aj : Use aligned jumps. + +# Tools +CC = $(CCACHE) or32-elf-gcc +AS = or32-elf-as +LD = or32-elf-ld +OBJDUMP = or32-elf-objdump +NM = or32-elf-nm + +# Tools's option +CC_OPT = $(DIR_INCLUDE) $(OPTIMIZE) -Wlong-long -D__or32__ -DHAVE_LIBC -D__DYNAMIC_REENT__ +# -DHAVE_LIBC +AS_OPT = +LD_OPT = -T$(DIR_LDSCRIPT)/or32.ld $(DIR_LIBRARY) -lor32 -lc -lor32 -lc -lm -lgcc +OBJDUMP_OPT = -D +NM_OPT = -n Index: trunk/Softwares/Basic_test/src/asm/asm_000_none.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_000_none.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_000_none.s (revision 88) @@ -0,0 +1,36 @@ +/******************************************** + * files : asm_000_none.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : + * warning : instruction ok + * l.addi + * l.and + * l.jal + * l.jr + ******************************************** + */ + .file "asm_000_none.s" + .section .text + .align 4 + + .global _asm_000_none +_asm_000_none : + /* save context */ + l.addi r1,r1,0 + + /* Return is KO (default)*/ + l.and r11,r0,r0 + +_asm_000_none_ok : + l.addi r11,r0,1 +_asm_000_none_ko : + + /* load context */ + l.jr r9 + l.addi r1,r1,0 Index: trunk/Softwares/Basic_test/src/asm/asm_001_add.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_001_add.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_001_add.s (revision 88) @@ -0,0 +1,71 @@ +/******************************************** + * files : asm_001_add.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : Addition + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.jal + * l.jr + * l.lwz + * l.movhi + * l.ori + * l.sfne + * l.sw + ******************************************** + */ + .file "asm_001_add.s" + .section .text + .align 4 + + .global _asm_001_add +_asm_001_add : + /* save context */ + l.addi r1,r1,-8 + l.sw 0(r1),r20 + l.sw 4(r1),r21 + + /* Return is KO (default)*/ + l.and r11,r0,r0 + + l.add r20,r0,r0 /* e + e = e */ + + l.sfne r20,r0 + l.bf _asm_001_add_ko + l.addi r20,r0,1 + + l.addi r21,r0,-1 + l.add r21,r21,r20 /* -1 + 1 */ + + l.sfne r21,r0 + l.bf _asm_001_add_ko + l.movhi r20,0xdead + l.ori r20,r0,0xbeaf + + l.add r21,r20,r0 /* X + e = X */ + l.sfne r21,r20 + l.bf _asm_001_add_ko + l.nop 0 + + l.add r21,r0,r20 /* e + X = X */ + l.sfne r21,r20 + l.bf _asm_001_add_ko + l.nop 0 + +_asm_001_add_ok : + l.addi r11,r0,1 +_asm_001_add_ko : + + /* load context */ + l.lwz r21, 4(r1) + l.lwz r20, 0(r1) + + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_002_addc.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_002_addc.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_002_addc.s (revision 88) @@ -0,0 +1,60 @@ +/******************************************** + * files : asm_002_addc.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : Test the carry + * warning : instructions used + * l.add + * l.addi + * l.and + * l.bf + * l.jal + * l.jr + * l.sfne + ******************************************** + */ + .file "asm_002_addc.s" + .section .text + .align 4 + + .global _asm_002_addc +_asm_002_addc : + /* save context */ + l.addi r1,r1,-12 + l.sw 0(r1),r20 + l.sw 4(r1),r21 + l.sw 8(r1),r22 + /* Return is KO (default) */ + l.and r11,r0,r0 + + /* + * R20 = 0x00000001 + * R21 = 0xFFFFFFFF + * R22 = 0x00000000 and carry is set + */ + l.addi r20,r0, 1 + l.addi r21,r0,-1 + l.add r22,r20,r21 + + /* Add the carry */ + l.addc r22,r0,r0 + + l.sfne r22,r20 + l.bf _asm_002_addc_ko + l.nop 0 + +_asm_002_addc_ok : + l.addi r11,r0,1 + +_asm_002_addc_ko : + /* load context */ + l.lwz r22,8(r1) + l.lwz r21,4(r1) + l.lwz r20,0(r1) + l.jr r9 + l.addi r1,r1,12 Index: trunk/Softwares/Basic_test/src/asm/asm_003_extend.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_003_extend.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_003_extend.s (revision 88) @@ -0,0 +1,110 @@ +/******************************************** + * files : asm_003_extend.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : l.extbs, l.extbz, l.exthz, l.exths + * warning : instruction ok + * l.addi + * l.and + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_003_extend.s" + .section .text + .align 4 + + .global _asm_003_extend +_asm_003_extend : + /* save context */ + l.addi r1,r1,-12 + l.sw 0 (r1),r20 + l.sw 4 (r1),r21 + l.sw 8 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* WARNING : gcc don't compile if l.extXX have not two source register */ + + /* step 1 : test extend byte */ + + /* step 1.1 : test with a variable not signed */ + + l.ori r20,r0,0x007F + + l.extbz r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 1 + + l.extbs r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 2 + + /* step 1.2 : test with a varibale signed */ + l.ori r20,r0,0x0080 + + l.movhi r21,0xFFFF + l.ori r21,r21,0xFF80 + + l.extbz r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 3 + + l.extbs r22,r20 + l.sfeq r22,r21 + l.bnf _asm_003_extend_ko + l.nop 4 + + /* step 2 : test extend half word */ + + /* step 2.1 : test with a variable not signed */ + + l.ori r20,r0,0x7FFF + + l.exthz r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 5 + + l.exths r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 6 + + /* step 2.2 : test with a variable signed */ + l.ori r20,r0,0x8000 + + l.movhi r21,0xFFFF + l.ori r21,r21,0x8000 + + l.exthz r22,r20 + l.sfeq r22,r20 + l.bnf _asm_003_extend_ko + l.nop 7 + + l.exths r22,r20 + l.sfeq r22,r21 + l.bnf _asm_003_extend_ko + l.nop 8 + +_asm_003_extend_ok : + l.addi r11,r0,1 +_asm_003_extend_ko : + + /* load context */ + l.lwz r22,8 (r1) + l.lwz r21,4 (r1) + l.lwz r20,0 (r1) + l.jr r9 + l.addi r1,r1,12 Index: trunk/Softwares/Basic_test/src/asm/asm_004_sfeq.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_004_sfeq.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_004_sfeq.s (revision 88) @@ -0,0 +1,221 @@ +/******************************************** + * files : asm_004_sfeq.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_004_sfeq.s" + .section .text + .align 4 + + .global _asm_004_sfeq +_asm_004_sfeq : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 1 0 1 + + +> | 0 0 0 + + +< | 0 0 0 + + - | 0 0 0 + - -= | 1 1 0 + - -> | 0 0 0 + - -< | 0 0 0 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfeq r21,r22 + l.bnf _asm_004_sfeq_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfeq r21,r22 + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfeq r21,r22 + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfeq r21,r22 + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfeq r21,r22 + l.bnf _asm_004_sfeq_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfeq r21,r22 + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfeq r21,r22 + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfeqi r21,0x7ead + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfeqi r21,0x7ebd + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfeqi r21,0x7e9d + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfeqi r21,0xdead + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfeqi r21,0xdead + l.bnf _asm_004_sfeq_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfeqi r21,0xdebd + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfeqi r21,0xde9d + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfeqi r21,0x7ead + l.bnf _asm_004_sfeq_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfeqi r21,0x7ebd + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfeqi r21,0x7e9d + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfeqi r21,0xdead + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfeqi r21,0xdead + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfeqi r21,0xdebd + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfeqi r21,0xde9d + l.bf _asm_004_sfeq_ko /* if set : error */ + l.nop 7 + + +_asm_004_sfeq_ok : + l.addi r11,r0,1 +_asm_004_sfeq_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_005_sfne.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_005_sfne.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_005_sfne.s (revision 88) @@ -0,0 +1,221 @@ +/******************************************** + * files : asm_005_sfne.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_005_sfne.s" + .section .text + .align 4 + + .global _asm_005_sfne +_asm_005_sfne : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 0 1 0 + + +> | 1 1 1 + + +< | 1 1 1 + + - | 1 1 1 + - -= | 0 0 1 + - -> | 1 1 1 + - -< | 1 1 1 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfne r21,r22 + l.bf _asm_005_sfne_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfne r21,r22 + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfne r21,r22 + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfne r21,r22 + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfne r21,r22 + l.bf _asm_005_sfne_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfne r21,r22 + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfne r21,r22 + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfnei r21,0x7ead + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfnei r21,0x7ebd + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfnei r21,0x7e9d + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfnei r21,0xdead + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfnei r21,0xdead + l.bf _asm_005_sfne_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfnei r21,0xdebd + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfnei r21,0xde9d + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfnei r21,0x7ead + l.bf _asm_005_sfne_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfnei r21,0x7ebd + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfnei r21,0x7e9d + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfnei r21,0xdead + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfnei r21,0xdead + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfnei r21,0xdebd + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfnei r21,0xde9d + l.bnf _asm_005_sfne_ko /* if not set : error */ + l.nop 7 + + +_asm_005_sfne_ok : + l.addi r11,r0,1 +_asm_005_sfne_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_006_sfges.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_006_sfges.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_006_sfges.s (revision 88) @@ -0,0 +1,221 @@ +/******************************************** + * files : asm_006_sfges.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_006_sfges.s" + .section .text + .align 4 + + .global _asm_006_sfges +_asm_006_sfges : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 1 0 1 + + +> | 0 0 0 + + +< | 1 0 1 + + - | 1 0 1 + - -= | 1 1 1 + - -> | 0 0 1 + - -< | 1 1 1 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfges r21,r22 + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfges r21,r22 + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfges r21,r22 + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfges r21,r22 + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfges r21,r22 + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfges r21,r22 + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfges r21,r22 + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgesi r21,0x7ead + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgesi r21,0x7ebd + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgesi r21,0x7e9d + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgesi r21,0xdead + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgesi r21,0xdead + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgesi r21,0xdebd + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgesi r21,0xde9d + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgesi r21,0x7ead + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgesi r21,0x7ebd + l.bf _asm_006_sfges_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgesi r21,0x7e9d + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgesi r21,0xdead + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgesi r21,0xdead + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgesi r21,0xdebd + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgesi r21,0xde9d + l.bnf _asm_006_sfges_ko /* if not set : error */ + l.nop 7 + + +_asm_006_sfges_ok : + l.addi r11,r0,1 +_asm_006_sfges_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_007_sfgeu.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_007_sfgeu.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_007_sfgeu.s (revision 88) @@ -0,0 +1,221 @@ +/******************************************** + * files : asm_007_sfgeu.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_007_sfgeu.s" + .section .text + .align 4 + + .global _asm_007_sfgeu +_asm_007_sfgeu : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 1 1 1 + + +> | 0 1 0 + + +< | 1 1 1 + + - | 0 0 0 + - -= | 1 1 0 + - -> | 0 0 0 + - -< | 1 1 0 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfgeu r21,r22 + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfgeu r21,r22 + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfgeu r21,r22 + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfgeu r21,r22 + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfgeu r21,r22 + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfgeu r21,r22 + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfgeu r21,r22 + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgeui r21,0x7ead + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgeui r21,0x7ebd + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgeui r21,0x7e9d + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgeui r21,0xdead + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgeui r21,0xdead + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgeui r21,0xdebd + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgeui r21,0xde9d + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgeui r21,0x7ead + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgeui r21,0x7ebd + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgeui r21,0x7e9d + l.bnf _asm_007_sfgeu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgeui r21,0xdead + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgeui r21,0xdead + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgeui r21,0xdebd + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgeui r21,0xde9d + l.bf _asm_007_sfgeu_ko /* if set : error */ + l.nop 7 + + +_asm_007_sfgeu_ok : + l.addi r11,r0,1 +_asm_007_sfgeu_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_008_sfgts.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_008_sfgts.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_008_sfgts.s (revision 88) @@ -0,0 +1,221 @@ +/******************************************** + * files : asm_008_sfgts.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_008_sfgts.s" + .section .text + .align 4 + + .global _asm_008_sfgts +_asm_008_sfgts : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 0 0 0 + + +> | 0 0 0 + + +< | 1 0 1 + + - | 1 0 1 + - -= | 0 0 1 + - -> | 0 0 1 + - -< | 1 1 1 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfgts r21,r22 + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfgts r21,r22 + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfgts r21,r22 + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfgts r21,r22 + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfgts r21,r22 + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfgts r21,r22 + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfgts r21,r22 + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgtsi r21,0x7ead + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgtsi r21,0x7ebd + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgtsi r21,0x7e9d + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgtsi r21,0xdead + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgtsi r21,0xdead + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgtsi r21,0xdebd + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgtsi r21,0xde9d + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgtsi r21,0x7ead + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgtsi r21,0x7ebd + l.bf _asm_008_sfgts_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgtsi r21,0x7e9d + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgtsi r21,0xdead + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgtsi r21,0xdead + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgtsi r21,0xdebd + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgtsi r21,0xde9d + l.bnf _asm_008_sfgts_ko /* if not set : error */ + l.nop 7 + + +_asm_008_sfgts_ok : + l.addi r11,r0,1 +_asm_008_sfgts_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_009_sfgtu.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_009_sfgtu.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_009_sfgtu.s (revision 88) @@ -0,0 +1,220 @@ +/******************************************** + * files : asm_009_sfgtu.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfeq + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_009_sfgtu.s" + .section .text + .align 4 + + .global _asm_009_sfgtu +_asm_009_sfgtu : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 0 1 0 + + +> | 0 1 0 + + +< | 1 1 1 + + - | 0 0 0 + - -= | 0 0 0 + - -> | 0 0 0 + - -< | 1 1 0 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfgtu r21,r22 + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfgtu r21,r22 + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfgtu r21,r22 + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfgtu r21,r22 + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfgtu r21,r22 + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfgtu r21,r22 + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfgtu r21,r22 + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgtui r21,0x7ead + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgtui r21,0x7ebd + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgtui r21,0x7e9d + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgtui r21,0xdead + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgtui r21,0xdead + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgtui r21,0xdebd + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgtui r21,0xde9d + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfgtui r21,0x7ead + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfgtui r21,0x7ebd + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfgtui r21,0x7e9d + l.bnf _asm_009_sfgtu_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfgtui r21,0xdead + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfgtui r21,0xdead + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfgtui r21,0xdebd + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfgtui r21,0xde9d + l.bf _asm_009_sfgtu_ko /* if set : error */ + l.nop 7 + +_asm_009_sfgtu_ok : + l.addi r11,r0,1 +_asm_009_sfgtu_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_010_sfles.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_010_sfles.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_010_sfles.s (revision 88) @@ -0,0 +1,220 @@ +/******************************************** + * files : asm_010_sfles.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfles + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_010_sfles.s" + .section .text + .align 4 + + .global _asm_010_sfles +_asm_010_sfles : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 1 1 1 + + +> | 1 1 1 + + +< | 0 1 0 + + - | 0 1 0 + - -= | 1 1 0 + - -> | 1 1 0 + - -< | 0 0 0 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfles r21,r22 + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfles r21,r22 + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfles r21,r22 + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfles r21,r22 + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfles r21,r22 + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfles r21,r22 + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfles r21,r22 + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sflesi r21,0x7ead + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sflesi r21,0x7ebd + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sflesi r21,0x7e9d + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sflesi r21,0xdead + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sflesi r21,0xdead + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sflesi r21,0xdebd + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sflesi r21,0xde9d + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sflesi r21,0x7ead + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sflesi r21,0x7ebd + l.bnf _asm_010_sfles_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sflesi r21,0x7e9d + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sflesi r21,0xdead + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sflesi r21,0xdead + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sflesi r21,0xdebd + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sflesi r21,0xde9d + l.bf _asm_010_sfles_ko /* if set : error */ + l.nop 7 + +_asm_010_sfles_ok : + l.addi r11,r0,1 +_asm_010_sfles_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_011_sfleu.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_011_sfleu.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_011_sfleu.s (revision 88) @@ -0,0 +1,220 @@ +/******************************************** + * files : asm_011_sfleu.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfleu + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_011_sfleu.s" + .section .text + .align 4 + + .global _asm_011_sfleu +_asm_011_sfleu : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 1 0 1 + + +> | 1 0 1 + + +< | 0 0 0 + + - | 1 1 1 + - -= | 1 1 1 + - -> | 1 1 1 + - -< | 0 0 1 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfleu r21,r22 + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfleu r21,r22 + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfleu r21,r22 + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfleu r21,r22 + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfleu r21,r22 + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfleu r21,r22 + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfleu r21,r22 + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfleui r21,0x7ead + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfleui r21,0x7ebd + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfleui r21,0x7e9d + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfleui r21,0xdead + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfleui r21,0xdead + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfleui r21,0xdebd + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfleui r21,0xde9d + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfleui r21,0x7ead + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfleui r21,0x7ebd + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfleui r21,0x7e9d + l.bf _asm_011_sfleu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfleui r21,0xdead + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfleui r21,0xdead + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfleui r21,0xdebd + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfleui r21,0xde9d + l.bnf _asm_011_sfleu_ko /* if not set : error */ + l.nop 7 + +_asm_011_sfleu_ok : + l.addi r11,r0,1 +_asm_011_sfleu_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_012_sflts.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_012_sflts.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_012_sflts.s (revision 88) @@ -0,0 +1,220 @@ +/******************************************** + * files : asm_012_sflts.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sflts + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_012_sflts.s" + .section .text + .align 4 + + .global _asm_012_sflts +_asm_012_sflts : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 0 1 0 + + +> | 1 1 1 + + +< | 0 1 0 + + - | 0 1 0 + - -= | 0 0 0 + - -> | 1 1 0 + - -< | 0 0 0 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sflts r21,r22 + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sflts r21,r22 + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sflts r21,r22 + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sflts r21,r22 + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sflts r21,r22 + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sflts r21,r22 + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sflts r21,r22 + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfltsi r21,0x7ead + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfltsi r21,0x7ebd + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfltsi r21,0x7e9d + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfltsi r21,0xdead + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfltsi r21,0xdead + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfltsi r21,0xdebd + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfltsi r21,0xde9d + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfltsi r21,0x7ead + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfltsi r21,0x7ebd + l.bnf _asm_012_sflts_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfltsi r21,0x7e9d + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfltsi r21,0xdead + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfltsi r21,0xdead + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfltsi r21,0xdebd + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfltsi r21,0xde9d + l.bf _asm_012_sflts_ko /* if set : error */ + l.nop 7 + +_asm_012_sflts_ok : + l.addi r11,r0,1 +_asm_012_sflts_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_013_sfltu.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_013_sfltu.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_013_sfltu.s (revision 88) @@ -0,0 +1,220 @@ +/******************************************** + * files : asm_013_sfltu.s + * authors : Rosiere Mathieu + * date : 2006/06/22 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : test l.sfltu + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.bnf + * l.movhi + * l.jal + * l.jr + * l.lwz + * l.ori + * l.sw + ******************************************** + */ + .file "asm_013_sfltu.s" + .section .text + .align 4 + + .global _asm_013_sfltu +_asm_013_sfltu : + /* save context */ + l.addi r1,r1,-8 + l.sw 0 (r1),r21 + l.sw 4 (r1),r22 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Listing of test + | R I I + Op1 Op2 | F1 F2 F3 + ----------------+------------------------------- + + += | 0 0 0 + + +> | 1 0 1 + + +< | 0 0 0 + + - | 1 1 1 + - -= | 0 0 1 + - -> | 1 1 1 + - -< | 0 0 1 + + Op1 with : + Value on 32 bits (result F1) + Value on 16 bits - extend 1 (result F2) + - extend 0 (result F3) + */ + + /*************************/ + /* F1 : VALUE ON 32 BITS */ + /*************************/ + + /* Op1 : + */ + l.movhi r21,0x7ead + l.ori r21,r21,0xbeaf + + /* Op2 : += */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbeaf + + l.sfltu r21,r22 + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbfaf + + l.sfltu r21,r22 + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.movhi r22,0x7ead + l.ori r22,r22,0xbdaf + + l.sfltu r21,r22 + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.movhi r22,0xdead + l.ori r22,r22,0xbeaf + + l.sfltu r21,r22 + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Op2 : -= */ + + l.sfltu r21,r22 + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.movhi r22,0xdead + l.ori r22,r22,0xbfaf + + l.sfltu r21,r22 + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.movhi r22,0xdead + l.ori r22,r22,0xbdaf + + l.sfltu r21,r22 + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F2 : VALUE ON 16 BITS - extend 1 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0xFFFF + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfltui r21,0x7ead + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfltui r21,0x7ebd + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfltui r21,0x7e9d + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfltui r21,0xdead + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0xFFFF + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfltui r21,0xdead + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfltui r21,0xdebd + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfltui r21,0xde9d + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 7 + + /************************************/ + /* F3 : VALUE ON 16 BITS - extend 0 */ + /************************************/ + /* Op1 : + */ + l.movhi r21,0x0000 + l.ori r21,r21,0x7ead + + /* Op2 : += */ + l.sfltui r21,0x7ead + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 1 + + /* Op2 : +> */ + l.sfltui r21,0x7ebd + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 2 + + /* Op2 : +< */ + l.sfltui r21,0x7e9d + l.bf _asm_013_sfltu_ko /* if set : error */ + l.nop 3 + + /* Op2 : - */ + l.sfltui r21,0xdead + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 4 + + /* Op1 : - */ + l.movhi r21,0x0000 + l.ori r21,r21,0xdead + + /* Op2 : -= */ + l.sfltui r21,0xdead + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 5 + + /* Op2 : -> */ + l.sfltui r21,0xdebd + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 6 + + /* Op2 : -< */ + l.sfltui r21,0xde9d + l.bnf _asm_013_sfltu_ko /* if not set : error */ + l.nop 7 + +_asm_013_sfltu_ok : + l.addi r11,r0,1 +_asm_013_sfltu_ko : + /* load context */ + l.lwz r22,4 (r1) + l.lwz r21,0 (r1) + l.jr r9 + l.addi r1,r1,8 Index: trunk/Softwares/Basic_test/src/asm/asm_014_cmov.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_014_cmov.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_014_cmov.s (revision 88) @@ -0,0 +1,69 @@ +/******************************************** + * files : asm_014_cmov.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : + * warning : instruction ok + * l.addi + * l.and + * l.jal + * l.jr + * l.lwz + * l.or + * l.ori + * l.sfeq + * l.sw + ******************************************** + */ + .file "asm_014_cmov.s" + .section .text + .align 4 + + .global _asm_014_cmov +_asm_014_cmov : + /* save context */ + l.addi r1,r1,-16 + l.sw 0 (r1),r20 + l.sw 4 (r1),r21 + l.sw 8 (r1),r22 + l.sw 12(r1),r23 + /* Return is KO (default)*/ + l.and r11,r0,r0 + + l.and r20,r0,r0 + l.movhi r21,0x5555 + l.ori r21,r21,0x5555 + l.movhi r22,0xaaaa + l.ori r22,r22,0xaaaa + + /* set flag 1 */ + l.sfeq r0,r0 + l.cmov r20,r21,r0 + + /* set flag 0 */ + l.sfne r0,r0 + l.cmov r23,r0,r22 + + l.or r20,r20,r23 + + l.sfeqi r20,-1 + l.bnf _asm_014_cmov_ko + l.nop 0 + +_asm_014_cmov_ok : + l.addi r11,r0,1 +_asm_014_cmov_ko : + + /* load context */ + l.lwz r23,12(r1) + l.lwz r22,8 (r1) + l.lwz r21,4 (r1) + l.lwz r20,0 (r1) + l.jr r9 + l.addi r1,r1,16 + Index: trunk/Softwares/Basic_test/src/asm/asm_015_shift_rotate.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_015_shift_rotate.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_015_shift_rotate.s (revision 88) @@ -0,0 +1,214 @@ +/******************************************** + * files : asm_015_shift_rotate.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : + * warning : instruction ok + * l.addi + * l.and + * l.bnf + * l.jal + * l.jr + * l.movhi + * l.ori + * l.sfeq + ******************************************** + */ + .file "asm_015_shift_rotate.s" + .section .text + .align 4 + + .global _asm_015_shift_rotate +_asm_015_shift_rotate : + /* save context */ + l.addi r1,r1,-16 + l.sw 0 (r1),r20 + l.sw 4 (r1),r21 + l.sw 8 (r1),r22 + l.sw 12(r1),r23 + + /* Return is KO (default)*/ + l.and r11,r0,r0 + + l.movhi r20, 0x2b3c + l.ori r20,r20,0x4d1a + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + l.rori r22,r21, 4 + l.rori r22,r22, 2 + l.rori r22,r22, 0 + l.rori r22,r22, 3 + l.rori r22,r22, 5 + l.rori r22,r22, 7 + l.rori r22,r22, 3 + + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.ori r23,r0,1 + l.ror r22,r21,r23 + l.and r23,r0,r0 + l.ror r22,r22,r23 + l.ori r23,r0,5 + l.ror r22,r22,r23 + l.ori r23,r0,2 + l.ror r22,r22,r23 + l.ori r23,r0,5 + l.ror r22,r22,r23 + l.ori r23,r0,3 + l.ror r22,r22,r23 + l.ori r23,r0,8 + l.ror r22,r22,r23 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 2 + + l.movhi r20, 0x4d00 + l.ori r20,r20,0x0000 + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.slli r22,r21,4 + l.slli r22,r22,0 + l.slli r22,r22,10 + l.slli r22,r22,7 + l.slli r22,r22,3 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.ori r23,r0,4 + l.sll r22,r21,r23 + l.ori r23,r0,0 + l.sll r22,r22,r23 + l.ori r23,r0,10 + l.sll r22,r22,r23 + l.ori r23,r0,7 + l.sll r22,r22,r23 + l.ori r23,r0,3 + l.sll r22,r22,r23 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r20, 0x0000 + l.ori r20,r20,0x001a + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.srli r22,r21,4 + l.srli r22,r22,0 + l.srli r22,r22,10 + l.srli r22,r22,7 + l.srli r22,r22,3 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.ori r23,r0,4 + l.srl r22,r21,r23 + l.ori r23,r0,0 + l.srl r22,r22,r23 + l.ori r23,r0,10 + l.srl r22,r22,r23 + l.ori r23,r0,7 + l.srl r22,r22,r23 + l.ori r23,r0,3 + l.srl r22,r22,r23 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r20, 0x0000 + l.ori r20,r20,0x001a + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.srai r22,r21,4 + l.srai r22,r22,0 + l.srai r22,r22,10 + l.srai r22,r22,7 + l.srai r22,r22,3 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r21, 0x1a2b + l.ori r21,r21,0x3c4d + + l.ori r23,r0,4 + l.sra r22,r21,r23 + l.ori r23,r0,0 + l.sra r22,r22,r23 + l.ori r23,r0,10 + l.sra r22,r22,r23 + l.ori r23,r0,7 + l.sra r22,r22,r23 + l.ori r23,r0,3 + l.sra r22,r22,r23 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r20, 0xffff + l.ori r20,r20,0xff8a + + l.movhi r21, 0x8a2b + l.ori r21,r21,0x3c4d + + l.srai r22,r21,4 + l.srai r22,r22,0 + l.srai r22,r22,10 + l.srai r22,r22,7 + l.srai r22,r22,3 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + + l.movhi r21, 0x8a2b + l.ori r21,r21,0x3c4d + + l.ori r23,r0,4 + l.sra r22,r21,r23 + l.ori r23,r0,0 + l.sra r22,r22,r23 + l.ori r23,r0,10 + l.sra r22,r22,r23 + l.ori r23,r0,7 + l.sra r22,r22,r23 + l.ori r23,r0,3 + l.sra r22,r22,r23 + l.sfeq r20,r22 + l.bnf _asm_015_shift_rotate_ko + l.nop 1 + +_asm_015_shift_rotate_ok : + l.addi r11,r0,1 +_asm_015_shift_rotate_ko : + + /* load context */ + l.lwz r23,12(r1) + l.lwz r22,8 (r1) + l.lwz r21,4 (r1) + l.lwz r20,0 (r1) + l.jr r9 + l.addi r1,r1,16 Index: trunk/Softwares/Basic_test/src/asm/asm_016_load.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_016_load.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_016_load.s (revision 88) @@ -0,0 +1,150 @@ +/******************************************** + * files : asm_016_load.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : + * warning : instruction ok + * l.addi + * l.and + * l.bf + * l.jal + * l.jr + * l.sw + ******************************************** + */ + .file "asm_016_load.s" + .section .text + .align 4 + + .global _asm_016_load +_asm_016_load : + /* save context */ + l.addi r1,r1,-16 + /* 0 (r1) is reserved */ + l.sw 4 (r1),r20 + l.sw 8 (r1),r21 + l.sw 12(r1),r22 + + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* Value Not Signed */ + l.movhi r20,0x1234 + l.ori r20,r20,0x5678 + + /* TEST BYTES */ + l.sb 0 (r1), r20 + l.lbz r21, 0 (r1) + l.extbz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lbs r21, 0 (r1) + l.extbs r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + /* TEST HALF WORD */ + l.sh 0 (r1), r20 + l.lhz r21, 0 (r1) + l.exthz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lhs r21, 0 (r1) + l.exths r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + /* TEST WORD */ + l.sw 0 (r1), r20 + l.lwz r21, 0 (r1) + l.extwz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lws r21, 0 (r1) + l.extws r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + /* Value Signed */ + l.movhi r20,0xdead + l.ori r20,r20,0xbeaf + + /* TEST BYTES */ + l.sb 0 (r1), r20 + l.lbz r21, 0 (r1) + l.extbz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lbs r21, 0 (r1) + l.extbs r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + /* TEST HALF WORD */ + l.sh 0 (r1), r20 + l.lhz r21, 0 (r1) + l.exthz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lhs r21, 0 (r1) + l.exths r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + /* TEST WORD */ + l.sw 0 (r1), r20 + l.lwz r21, 0 (r1) + l.extwz r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + + l.lws r21, 0 (r1) + l.extws r22,r20 + + l.sfeq r21,r22 + l.bnf _asm_016_load_ko + l.nop 1 + +_asm_016_load_ok : + l.addi r11,r0,1 +_asm_016_load_ko : + + /* load context */ + l.lwz r22,12(r1) + l.lwz r21,8 (r1) + l.lwz r20,4 (r1) + /* 0 (r1) is reserved */ + l.jr r9 + l.addi r1,r1,16 Index: trunk/Softwares/Basic_test/src/asm/asm_017_mul.s =================================================================== --- trunk/Softwares/Basic_test/src/asm/asm_017_mul.s (revision 88) +++ trunk/Softwares/Basic_test/src/asm/asm_017_mul.s (revision 88) @@ -0,0 +1,341 @@ +/******************************************** + * files : asm_017_mul.s + * authors : Rosiere Mathieu + * date : 2006/06/20 + ******************************************** + * input : - + * output : 1 test OK + * 0 test KO + ******************************************** + * test : + * warning : instruction ok + * l.addi + * l.and + * l.jal + * l.jr + ******************************************** + */ + .file "asm_017_mul.s" + .section .text + .align 4 + + .global _asm_017_mul +_asm_017_mul : + /* save context */ + l.addi r1,r1,-16 + l.sw 0 (r1),r20 + l.sw 4 (r1),r21 + l.sw 8 (r1),r22 + l.sw 12(r1),r23 + + /* Return is KO (default)*/ + l.and r11,r0,r0 + + /* + r20 : result + r21 : operand 1 + r22 : operand 2 + r23 : result waited + */ + + /* Operand 1 : positive */ + l.movhi r21,0x1234 + l.ori r21,r21,0x5678 + + /* Test 1.1 */ + l.and r22,r0,r0 + l.and r23,r0,r0 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,0 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 1.2 */ + + l.ori r22,r0,1 + l.or r23,r0,r21 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,1 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 1.3 */ + + l.ori r22,r0,2 + l.slli r23,r21, 1 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,2 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 1.4 */ + + l.ori r22,r0,0x11 + l.movhi r23,0x3579 + l.ori r23,r23,0xbdf8 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,0x11 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 1.4 */ + + l.addi r22,r0,-1 + l.movhi r23,0xedcb + l.ori r23,r23,0xa988 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +/* + l.muli r20,r21,-1 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +*/ + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 1.5 */ + + l.addi r22,r0,-2 + + l.movhi r23,0xdb97 + l.ori r23,r23,0x5310 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +/* + l.muli r20,r21,-2 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +*/ + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Operand 2 : negative */ + l.movhi r21,0xdead + l.ori r21,r21,0xbeaf + + /* Test 2.1 */ + l.and r22,r0,r0 + l.and r23,r0,r0 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,0 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 2.2 */ + + l.ori r22,r0,1 + l.or r23,r0,r21 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,1 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 2.3 */ + + l.ori r22,r0,2 + l.slli r23,r21, 1 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,2 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 2.4 */ + + l.ori r22,r0,0x11 + l.movhi r23,0xc989 + l.ori r23,r23,0xa99f + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.muli r20,r21,0x11 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 2.4 */ + + l.addi r22,r0,-1 + l.movhi r23,0x2152 + l.ori r23,r23,0x4151 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +/* + l.muli r20,r21,-1 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +*/ + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + + /* Test 2.5 */ + + l.addi r22,r0,-2 + + l.movhi r23,0x42a4 + l.ori r23,r23,0x82a2 + + l.mul r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +/* + l.muli r20,r21,-2 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 +*/ + l.mulu r20,r21,r22 + + l.sfeq r20,r23 + l.bnf _asm_017_mul_ko + l.nop 1 + +_asm_017_mul_ok : + l.addi r11,r0,1 +_asm_017_mul_ko : + + /* load context */ + l.lwz r20,0 (r1) + l.lwz r21,4 (r1) + l.lwz r22,8 (r1) + l.lwz r23,12(r1) + l.jr r9 + l.addi r1,r1,16 Index: trunk/Softwares/Basic_test/src/c/bottles.c =================================================================== --- trunk/Softwares/Basic_test/src/c/bottles.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/bottles.c (revision 88) @@ -0,0 +1,37 @@ +/* + * 99 bottles of beer in ansi c + * + * by Bill Wein: bearheart@bearnet.com + * + */ +#include "bottles.h" +#include +#include +#include + +void chug(int beers); + +void bottles(int nb_beers) +{ + register int beers; + + for(beers = nb_beers; beers; chug(beers--)) + puts(""); + + puts("\nTime to buy more beer!\n"); +} + +void chug(register int beers) +{ + char howmany[8], *s; + + s = beers != 1 ? "s" : ""; + printf("%d bottle%s of beer on the wall,\n", beers, s); + printf("%d bottle%s of beeeeer . . . ,\n", beers, s); + printf("Take one down, pass it around,\n"); + + if(--beers) sprintf(howmany, "%d", beers); else strcpy(howmany, "No more"); + s = beers != 1 ? "s" : ""; + + printf("%s bottle%s of beer on the wall.\n", howmany, s); +} Index: trunk/Softwares/Basic_test/src/c/dhry21a.c =================================================================== --- trunk/Softwares/Basic_test/src/c/dhry21a.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/dhry21a.c (revision 88) @@ -0,0 +1,398 @@ +/* + ************************************************************************* + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + ************************************************************************* + */ + +#include +#include +#include +#include "dhry.h" +#include "dhry21.h" + +/* Global Variables: */ + +Rec_Pointer Ptr_Glob, + Next_Ptr_Glob; +int Int_Glob; +Boolean Bool_Glob; +char Ch_1_Glob, + Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +char Reg_Define[] = "Register option selected."; + +//extern char *malloc (); +//Enumeration Func_1 (); + /* + forward declaration necessary since Enumeration may not simply be int + */ + +#ifndef ROPT +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else +#define REG register +#endif + + +/* variables for time measurement: */ + +#define Too_Small_Time 2 + /* Measurements should last at least 2 seconds */ + +DOUBLE Begin_Time, + End_Time, + User_Time; + +DOUBLE Microseconds, + Dhrystones_Per_Second, + Vax_Mips; + +/* end of variables for time measurement */ + +int main_dhry21 (unsigned int NUMBER_OF_RUNS) +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + DOUBLE dtime(); + + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + REG int Number_Of_Runs; + + FILE *Ap; + + /* Initializations */ + + if ((Ap = fopen("dhry.res","a+")) == NULL) + { + printf("Can not open dhry.res\n\n"); + exit(1); + } + + Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + + /* + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + */ + +//********************************************************************** +// printf ("Please give the number of runs through the benchmark: "); +// { +// int n; +// scanf ("%d", &n); +// Number_Of_Runs = n; +// } +// printf ("\n"); +//********************************************************************** + + Number_Of_Runs = NUMBER_OF_RUNS; + + printf ("Execution starts, %d runs through Dhrystone\n",Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + + Begin_Time = dtime(); + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + + End_Time = dtime(); + + printf ("Execution ends\n"); + /******************************************************************* + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: Number_Of_Runs + 10\n"); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + ********************************************************************/ + + User_Time = End_Time - Begin_Time; + + if (User_Time < Too_Small_Time) + { + printf ("Measured time too small to obtain meaningful results : %f\n",User_Time); + printf ("Please increase number of runs\n"); + printf ("\n"); + } + else + { + Microseconds = User_Time * Mic_secs_Per_Second / (DOUBLE) Number_Of_Runs; + Dhrystones_Per_Second = (DOUBLE) Number_Of_Runs / User_Time; + Vax_Mips = Dhrystones_Per_Second / 1757.0; + +#ifdef ROPT + printf ("Register option selected? YES\n"); +#else + printf ("Register option selected? NO\n"); + strcpy(Reg_Define, "Register option not selected."); +#endif + + printf ("Microseconds for one run through Dhrystone : %.1lf \n",Microseconds); + printf ("Dhrystones per Second : %.1lf \n",Dhrystones_Per_Second); + printf ("VAX MIPS rating : %.3lf \n",Vax_Mips); + printf ("\n"); + + fprintf(Ap,"\n"); + fprintf(Ap,"Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + fprintf(Ap,"%s\n",Reg_Define); + + fprintf(Ap,"Microseconds for one loop : %.1lf\n",Microseconds); + fprintf(Ap,"Dhrystones per second : %.1lf\n",Dhrystones_Per_Second); + fprintf(Ap,"VAX MIPS rating : %.3lf\n",Vax_Mips); + } + fclose(Ap); + return 0; + +} + +void +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ + +void +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + +void +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + +void +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + +void +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif Index: trunk/Softwares/Basic_test/src/c/dhry21b.c =================================================================== --- trunk/Softwares/Basic_test/src/c/dhry21b.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/dhry21b.c (revision 88) @@ -0,0 +1,195 @@ +/* + ************************************************************************* + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + ************************************************************************* + */ + +#include "dhry.h" +#include "dhry21.h" +#include + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else +#define REG register +#endif + +int Int_Glob; +char Ch_1_Glob; + +void +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ +} /* Proc_6 */ + +void +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + +void +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc ; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ Index: trunk/Softwares/Basic_test/src/c/exec_0.c =================================================================== --- trunk/Softwares/Basic_test/src/c/exec_0.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/exec_0.c (revision 88) @@ -0,0 +1,32 @@ +#include "bool.h" +#include "func_test.h" + +bool exec_0() +{ + bool res = false; + + printf(" \n"); + + res = (test_01() && + test_02() && + test_03() && + test_04() && + test_05() && + test_06() && + test_07() && + test_08() && + test_09() && + test_10() && + test_11() && + test_12() && + test_13() && + 1); + + if (res == false) + printf(" Ko\n"); + else + printf(" Ok\n"); + + return (res); +} + Index: trunk/Softwares/Basic_test/src/c/exec_1.c =================================================================== --- trunk/Softwares/Basic_test/src/c/exec_1.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/exec_1.c (revision 88) @@ -0,0 +1,31 @@ +#include "bool.h" +#include "func_test.h" + +bool exec_1() +{ + bool res = false; + + printf("\n"); + + res = (test_10() && + test_13() && + test_12() && + test_11() && + test_01() && + test_02() && + test_03() && + test_06() && + test_07() && + test_04() && + test_05() && + test_08() && + test_09() && + 1); + + if (res == false) + printf(" Ko\n"); + else + printf(" Ok\n"); + + return res; +} Index: trunk/Softwares/Basic_test/src/c/exec_2.c =================================================================== --- trunk/Softwares/Basic_test/src/c/exec_2.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/exec_2.c (revision 88) @@ -0,0 +1,31 @@ +#include "bool.h" +#include "func_test.h" + +bool exec_2() +{ + bool res = false; + + printf("\n"); + + res = (test_07() && + test_02() && + test_10() && + test_01() && + test_13() && + test_03() && + test_12() && + test_06() && + test_08() && + test_04() && + test_11() && + test_05() && + test_09() && + 1); + + if (res == false) + printf(" Ko\n"); + else + printf(" Ok\n"); + + return res; +} Index: trunk/Softwares/Basic_test/src/c/exec_3.c =================================================================== --- trunk/Softwares/Basic_test/src/c/exec_3.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/exec_3.c (revision 88) @@ -0,0 +1,31 @@ +#include "bool.h" +#include "func_test.h" + +bool exec_3() +{ + bool res = false; + + printf("\n"); + + res = (test_05() && + test_09() && + test_01() && + test_10() && + test_03() && + test_12() && + test_02() && + test_07() && + test_13() && + test_04() && + test_11() && + test_08() && + test_06() && + 1); + + if (res == false) + printf(" Ko\n"); + else + printf(" Ok\n"); + + return res; +} Index: trunk/Softwares/Basic_test/src/c/func_array.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_array.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_array.c (revision 88) @@ -0,0 +1,136 @@ +#include "func_array.h" + +//-----[ Selection_sort ]-------------------------------------------------- + +void selection_sort (int array[], int size) +{ + int i, min, j , tmp; + for(i = 0 ; i < size - 1 ; i++) + { + min = i; + + // Find indice min + for(j = i+1 ; j < size ; j++) + if(array[j] < array[min]) + min = j; + + if(min != i) // find or not. + { + tmp = array[i]; + array[i] = array[min]; + array[min] = tmp; + } + } +} + +//-----[ insertion_sort ]-------------------------------------------------- +void insertion_sort (int array[], int size) +{ + /* Spécifications externes : Tri du tableau t par insertion séquentielle */ + int i,pos,j,tmp; + + for (i = 1 ; i < size ; i++) + { + /* Calcul de la position d'insertion pos : */ + /* détermine le plus petit indice pos / 0 <= pos <= i */ + /* qui vérifie array[pos] >= array[i] */ + pos = 0; + + while(array[pos] < array[i]) + pos++; + + tmp = array[i]; /* Sauvegarde de t[i] */ + + for(j = i-1 ; j >= pos ; j--) + array[j+1] = array[j]; /* translation de t[pos..i-1] vers t[pos+1..i] */ + + array[pos] = tmp; /* insertion de t[pos] */ + } +} + +//-----[ QuickSort ]------------------------------------------------------- + +// QuickSort +void quick_sort (int * array, int debut, int fin) +{ + int gauche, droite; + int pivot; + + pivot = array[debut]; + + for(gauche = debut, droite = fin; gauche < droite; ) + { + + for(;array[droite] > pivot; droite--); + + if(gauche != droite) + { + array[gauche] = array[droite]; + array[droite] = pivot; + gauche++; + } + + for(; array[gauche] < pivot; gauche++); + + if(gauche != droite) + { + array[droite] = array[gauche]; + array[gauche] = pivot; + droite--; + } + } + + if(debut < gauche-1) quick_sort(array, debut , gauche-1); + if(fin > gauche+1) quick_sort(array, gauche+1, fin ); +} + +//-----[ BubbleSort ]------------------------------------------------------ + +void bubble_sort (int array[], unsigned int size) +{ + int i = 0; /* Indice de répétition du tri */ + int j = 0; /* Variable de boucle */ + int tmp = 0; /* Variable de stockage temporaire */ + + /* Booléen marquant l'arrêt du tri si le tableau est ordonné */ + int en_desordre = 1; + + /* Boucle de répétition du tri et le test qui + arrête le tri dès que le tableau est ordonné */ + for(i = 0 ; (i < size) && (en_desordre == 1); i++) + { + /* Supposons le tableau ordonné */ + en_desordre = 0; + + /* Vérification des éléments des places j et j-1 */ + for(j = 1 ; j < size - i ; j++) + { + /* Si les 2 éléments sont mal triés */ + if(array[j] < array[j-1]) + { + /* Inversion des 2 éléments */ + tmp = array[j-1]; + array[j-1] = array[j]; + array[j] = tmp; + + /* Le tableau n'est toujours pas trié */ + en_desordre = 1; + } + } + } +} + +//-----[ Algo ]------------------------------------------------------------ + +void array_tri_croissant (int * array, unsigned int size,int algo) +{ + switch (algo) + { + case 0 : bubble_sort (array,size); break; + case 1 : selection_sort (array,size); break; + case 2 : insertion_sort (array,size); break; + case 3 : quick_sort (array,0,size-1); break; + default : break; + } +} + Index: trunk/Softwares/Basic_test/src/c/func_endianness.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_endianness.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_endianness.c (revision 88) @@ -0,0 +1,20 @@ +#include +#include "func_endianness.h" + +bool endianness () +{ + union TestEndian test_endian; + + test_endian.total = 0xFF; + + if (test_endian.octets.octet1 == 0xFF) + { + printf("Little Endian\n"); + return LittleEndian; + } + else + { + printf("Big Endian\n"); + return BigEndian; + } +} Index: trunk/Softwares/Basic_test/src/c/func_factoriel.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_factoriel.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_factoriel.c (revision 88) @@ -0,0 +1,24 @@ +#include "func_factoriel.h" +#include "func_math.h" + +//-----[ Factoriel ]------------------------------------------------------- + +unsigned int fact_recursif (unsigned int x) +{ + if ( x <= 1) + return 1; + + return (mul_soft (x , fact_recursif (x-1) ) ); +} + +unsigned int fact_iteratif (unsigned int x) +{ + unsigned int res= 1; + + while (x > 1) + { + res = mul_soft(res,x); + x --; + } + return res; +} Index: trunk/Softwares/Basic_test/src/c/func_fibonnacci.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_fibonnacci.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_fibonnacci.c (revision 88) @@ -0,0 +1,18 @@ +#include "func_fibonnacci.h" + +int fibonnacci(int x) +{ + int i; + int xn = 0; + int xn_1 = 1; + int xn_2 = 0; + + for (i=0;i<=x;i++) + { + xn = xn_1 + xn_2; + xn_2 = xn_1; + xn_1 = xn; + } + + return xn; +} Index: trunk/Softwares/Basic_test/src/c/func_hanoi.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_hanoi.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_hanoi.c (revision 88) @@ -0,0 +1,24 @@ +#include "func_hanoi.h" + +int hanoi_recursif(char pic_depart, char pic_destination, char pic_transition, int nb_disques) +{ + unsigned int nb_move = 0; + + if (nb_disques == 1) + { + nb_move = 1; + } + else + { + //on modifie les positions des palets + nb_move += hanoi_recursif(pic_depart , pic_transition , pic_destination, nb_disques - 1); + nb_move += hanoi_recursif(pic_depart , pic_destination , pic_transition , 1 ); + nb_move += hanoi_recursif(pic_transition , pic_destination , pic_depart , nb_disques - 1); + } + return nb_move; +} + +int hanoi(int nb_disques) +{ + return(hanoi_recursif('1', '2', '3', nb_disques)); +} Index: trunk/Softwares/Basic_test/src/c/func_integrity.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_integrity.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_integrity.c (revision 88) @@ -0,0 +1,60 @@ +#include +#include "func_integrity.h" +#include "func_io.h" + +extern bool asm_001_add (); +extern bool asm_002_addc (); +extern bool asm_003_extend (); +extern bool asm_004_sfeq (); +extern bool asm_005_sfne (); +extern bool asm_006_sfges (); +extern bool asm_007_sfgeu (); +extern bool asm_008_sfgts (); +extern bool asm_009_sfgtu (); +extern bool asm_010_sfles (); +extern bool asm_011_sfleu (); +extern bool asm_012_sflts (); +extern bool asm_013_sfltu (); +extern bool asm_014_cmov (); +extern bool asm_015_shift_rotate (); +extern bool asm_016_load (); +extern bool asm_017_mul (); + +bool test_integrity () +{ + bool res; + + res = + asm_001_add () && + asm_002_addc () && + asm_003_extend () && + asm_004_sfeq () && + asm_005_sfne () && + asm_006_sfges () && + asm_007_sfgeu () && + asm_008_sfgts () && + asm_009_sfgtu () && + asm_010_sfles () && + asm_011_sfleu () && + asm_012_sflts () && + asm_013_sfltu () && + asm_014_cmov () && + asm_015_shift_rotate () && + asm_016_load () && + asm_017_mul () && + 1; + + if (res == true) + { + print(1); + printf(" Test is Ok\n"); + } + + else + { + quit(-1); + printf(" Test is Ko\n"); + } + + return res; +} Index: trunk/Softwares/Basic_test/src/c/func_math.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_math.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_math.c (revision 88) @@ -0,0 +1,68 @@ +#include "func_math.h" + +//-----[ Multiplication ]-------------------------------------------------- + +// Multiplication rapide +unsigned int mul_soft(unsigned int op1, + unsigned int op2) +{ + unsigned int num_bit,carry; + unsigned int op2_aux = op2; + unsigned int res = 0; + + for(num_bit=0;num_bit<32; num_bit++) + { + if (op2_aux == 0) + break; + + carry = op2_aux & 1; + op2_aux = op2_aux >> 1; + + if (carry!=0) + res += (op1 << num_bit); + } + return res; +} + +unsigned int mul_hard(unsigned int op1, + unsigned int op2) +{ + return op1*op2; +} + +//-----[ Division ]-------------------------------------------------------- + +unsigned int div_soft( unsigned int op1, + unsigned int op2) +{ + unsigned res; + + if (op2 == 0) + return 0; + + for (res = 0; op1 >= op2; res ++) + op1 -= op2; + + return res; +} + +unsigned int div_hard( unsigned int op1, + unsigned int op2) +{ +//return (op1/op2); + return div_soft(op1,op2); +} + +//-----[ Modulo ]---------------------------------------------------------- + +unsigned int modulo( unsigned int x, + unsigned int base) +{ + if (base==0) + return 0; + + while(x >= base) + x -= base; + + return x; +} Index: trunk/Softwares/Basic_test/src/c/func_mm.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_mm.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_mm.c (revision 88) @@ -0,0 +1,102 @@ +#include "func_mm.h" + +void mm_algo1 ( unsigned int size_matrix + ,unsigned int ** matrix_a + ,unsigned int ** matrix_b + ,unsigned int ** matrix_d) +{ + unsigned int index_i, index_j, index_k; + + for (index_i = 0; index_i < size_matrix; index_i ++) + for (index_j = 0; index_j < size_matrix; index_j ++) + { + matrix_d [index_i][index_j] = 0; + + for (index_k = 0; index_k < size_matrix; index_k ++) + matrix_d [index_i][index_j] += matrix_a[index_i][index_k] * matrix_b[index_k][index_j]; + } +} + +int mm(unsigned int size_matrix, unsigned int algo) +{ + unsigned int matrix_a [size_matrix][size_matrix]; + unsigned int matrix_b [size_matrix][size_matrix]; + unsigned int matrix_d [size_matrix][size_matrix]; + unsigned int sum , sum_ok; + unsigned int index_i, index_j; + + /* + * PHASE 1 : Initialisation + */ + + /* Flush matrix_d */ + for (index_i = 0; index_i < size_matrix; index_i ++) + for (index_j = 0; index_j < size_matrix; index_j ++) + { + matrix_a [index_i][index_j] = index_i+1; + matrix_b [index_i][index_j] = index_i+1; + matrix_d [index_i][index_j] = 0; + } + + sum = (size_matrix*(size_matrix+1))>>1; + /* + sum = (N*(N+1))/2; + ici sum = (4*5)/2 = 10 + + ( 1 1 1 1 ) + ( 2 2 2 2 ) + ( 3 3 3 3 ) + ( 4 4 4 4 ) + ( 1 1 1 1 ) 10 10 10 10 -> 1*sum + ( 2 2 2 2 ) 20 20 20 20 -> 2*sum + ( 3 3 3 3 ) 30 30 30 30 -> 3*sum + ( 4 4 4 4 ) 40 40 40 40 -> 4*sum + */ + + /* + * PHASE 2 : Execution + */ + + switch (algo) + { + case 1 : + { + /* méthode classique */ + + unsigned int index_i, index_j, index_k; + + for (index_i=0;index_i> 1; + } + + return res; +} + + +extern unsigned int find_first_one (int x); + +bool parite2(int x,int val_parite) +{ + unsigned int mask = 1; + unsigned int pos; + bool res = ( (val_parite & mask) ^ mask); //si bit de poids faible à zero alors parité pair + + while ((pos = find_first_one(x)) != 0) + { + res ^= 1; + x = x >> pos; + } + + return res; +} Index: trunk/Softwares/Basic_test/src/c/func_premier.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_premier.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_premier.c (revision 88) @@ -0,0 +1,35 @@ +#include "func_math.h" +#include "func_premier.h" + +//-----[ Premier ]--------------------------------------------------------- + +unsigned int premier(unsigned int x) +{ + unsigned int it; + + if (x <= 0) + return 0; + + if (x <= 2) + return 1; + + for(it=2; it <= (x/2); it++) + if (modulo(x,it) == 0) + return 0; + + return 1; +} + +unsigned int n_premier(unsigned int nieme_premier) +{ + unsigned int nb_find = 0; + unsigned int res = 1; + while (nb_find < nieme_premier) + { + res ++; + if (premier(res) == 1) + nb_find ++; + } + return res; +} + Index: trunk/Softwares/Basic_test/src/c/func_test.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_test.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_test.c (revision 88) @@ -0,0 +1,617 @@ +#include "func_test.h" +#include "func_array.h" +#include "func_endianness.h" +#include "func_factoriel.h" +#include "func_fibonnacci.h" +#include "func_hanoi.h" +#include "func_integrity.h" +#include "func_io.h" +#include "func_math.h" +#include "func_mm.h" +#include "func_parite.h" +#include "func_premier.h" +#include "func_test.h" +#include "func_test_io.h" + + + // mul_soft + // div_soft + // mul_hard + // div_hard + // modulo +#define PARAM_06 30 // fibonnacci max : 43 +#define PARAM_07 15 // n_premier max : 30 +#define PARAM_08 100 // tri_croissant max : unlimited (200) +#define PARAM_09 10 // hanoi max : 12 +#define PARAM_10 15 // mul matrix max : unlimited (30) +#define PARAM_11 12 // factoriel_rec max : 12 +#define PARAM_12 12 // factoriel_it max : 12 +#define PARAM_13 50 // parite max : unlimited (200) + +//---------------------------------- +// TEST 1 +// multiplication software +//---------------------------------- +int test_01 () +{ + int op1, op2, wait, res, test1; +#ifdef HAVE_LIBC + printf("Test_01 - mult_soft\n"); +#else + print(0xABCD0001); +#endif + + test1 = 1; + { +#ifdef HAVE_LIBC + printf(" * Test_01a\n"); +#else + print(0xABCD001A); +#endif + + op1 = 40; + op2 = 17; + wait = 680; // 0x2a8 + res = mul_soft(op1,op2); + + print(res); + test1 &= (wait == res); + } + { +#ifdef HAVE_LIBC + printf(" * Test_01b\n"); +#else + print(0xABCD001B); +#endif + + op1 = 1569; + op2 = 9835; + wait = 15431115; // 0xEB75CB + res = mul_soft(op1,op2); + + print(res); + test1 &= (wait == res); + } + + return test1; +} + +//---------------------------------- +// TEST 2 +// division software +//---------------------------------- +int test_02 () +{ + int op1, op2, wait, res, test2; +#ifdef HAVE_LIBC + printf("Test_02 - div_soft\n"); +#else + print(0xABCD0002); +#endif + + test2 = 1; + { +#ifdef HAVE_LIBC + printf(" * Test_02a\n"); +#else + print(0xABCD002A); +#endif + + op1 = 680; + op2 = 40; + wait = 17; // 0x11 + res = div_soft(op1,op2); + + print(res); + test2 &= (wait == res); + } + { +#ifdef HAVE_LIBC + printf(" * Test_02b\n"); +#else + print(0xABCD002B); +#endif + + op1 = 15431115; // eb75cb + op2 = 9835; // 266b + wait = 1569; // 621 + res = div_soft(op1,op2); + + print(res); + test2 &= (wait == res); + } + + return test2; +} + +//---------------------------------- +// TEST 3 +// multiplication hardware (*) +//---------------------------------- +int test_03 () +{ + int op1, op2, wait, res; +#ifdef HAVE_LIBC + printf("Test_03 - mul_hard\n"); +#else + print(0xABCD0003); +#endif + + op1 = 1569; + op2 = 9835; + wait = 15431115; // 0xEB75CB + res = mul_hard(op1,op2); + + print(res); + return (wait == res); +} + +//---------------------------------- +// TEST 4 +// division hardware (/) +//---------------------------------- +int test_04 () +{ + int op1, op2, wait, res; +#ifdef HAVE_LIBC + printf("Test_04 - div_hard\n"); +#else + print(0xABCD0004); +#endif + + op1 = 15431115; + op2 = 9835; + wait = 1569; // 0x621 + res = div_hard(op1,op2); + + print(res); + return (wait == res); +} + + +//---------------------------------- +// TEST 5 +// modulo +//---------------------------------- +int test_05 () +{ + int op1, op2, wait, res; +#ifdef HAVE_LIBC + printf("Test_05 - modulo\n"); +#else + print(0xABCD0005); +#endif + + op1 = 16834; + op2 = 563; + wait = 507; // 0x1fb + res = modulo(op1,op2); + + print(res); + return (wait == res); +} + +//---------------------------------- +// TEST 6 +// fibonnacci +//---------------------------------- +int test_06 () +{ + int it, test; + int x = PARAM_06; + int x_max = 43; + + int res [x_max+1]; + int wait [x_max+1]; +#ifdef HAVE_LIBC + printf("Test_06 - fibonnacci\n"); +#else + print(0xABCD0006); +#endif + wait [0] = 1; // 1 + wait [1] = 2; // 2 + wait [2] = 3; // 3 + wait [3] = 5; // 5 + wait [4] = 8; // 8 + wait [5] = 13; // d + wait [6] = 21; // 15 + wait [7] = 34; // 22 + wait [8] = 55; // 37 + wait [9] = 89; // 59 + wait [10] = 144; // 90 + wait [11] = 233; // e9 + wait [12] = 377; // 179 + wait [13] = 610; // 262 + wait [14] = 987; // 3db + wait [15] = 1597; // 63d + wait [16] = 2584; // a18 + wait [17] = 4181; // 1055 + wait [18] = 6765; // 1a6d + wait [19] = 10946; // 2ac2 + wait [20] = 17711; // 452f + wait [21] = 28657; // 6ff1 + wait [22] = 46368; // b520 + wait [23] = 75025; // 12511 + wait [24] = 121393; // 1da31 + wait [25] = 196418; // 2ff42 + wait [26] = 317811; // 4d973 + wait [27] = 514229; // 7d8b5 + wait [28] = 832040; // cb228 + wait [29] = 1346269; // 148add + wait [30] = 2178309; // 213d05 + wait [31] = 3524578; // 35c7e2 + wait [32] = 5702887; // 5704e7 + wait [33] = 9227465; // 8cccc9 + wait [34] = 14930352; // e3d1b0 + wait [35] = 24157817; // 1709e79 + wait [36] = 39088169; // 2547029 + wait [37] = 63245986; // 3c50ea2 + wait [38] = 102334155; // 6197ecb + wait [39] = 165580141; // 9de8d6d + wait [40] = 267914296; // ff80c38 + wait [41] = 433494437; // 19d699a5 + wait [42] = 701408733; // 29cea5dd + wait [43] = 1134903170; // 43a53f82 + + for (it = 0; it <= x ; it ++) + { + res [it] = fibonnacci (it); + } + + test = 1; + + for (it = 0; it <= x ; it ++) + test &= (res [it] == wait [it]); + + print(test); + return (test); +} + +//---------------------------------- +// TEST 7 +// n_premier +// * +//---------------------------------- +int test_07 () +{ + unsigned int it, test; + unsigned int x = PARAM_07; + unsigned int x_max = 30; + unsigned int res [x_max+1]; + unsigned int wait [x_max+1]; +#ifdef HAVE_LIBC + printf("Test_07 - n_premier\n"); +#else + print(0xABCD0007); +#endif + + wait [0] = 1; // 1 + wait [1] = 2; // 2 + wait [2] = 3; // 3 + wait [3] = 5; // 5 + wait [4] = 7; // 7 + wait [5] = 11; // b + wait [6] = 13; // d + wait [7] = 17; // 11 + wait [8] = 19; // 13 + wait [9] = 23; // 17 + wait [10] = 29; // 1d + wait [11] = 31; // 1f + wait [12] = 37; // 25 + wait [13] = 41; // 29 + wait [14] = 43; // 2b + wait [15] = 47; // 2f + wait [16] = 53; // 35 + wait [17] = 59; // 3b + wait [18] = 61; // 3d + wait [19] = 67; // 43 + wait [20] = 71; // 47 + wait [21] = 73; // 49 + wait [22] = 79; // 4f + wait [23] = 83; // 53 + wait [24] = 89; // 59 + wait [25] = 97; // 61 + wait [26] = 101; // 65 + wait [27] = 103; // 67 + wait [28] = 107; // 6b + wait [29] = 109; // 6d + wait [30] = 113; // 71 + + for (it = 0; it <= x ; it ++) + { + res [it] = n_premier(it); + print (res [it]); + } + + test = 1; + + for (it = 0; it <= x ; it ++) + test &= (res [it] == wait [it]); + + print(test); + return (test); +} + +//---------------------------------- +// TEST 8 +// tri_croissant (tableau d'int) +// tri_croissant (tableau de short) +// tri_croissant (tableau de char) +// * +//---------------------------------- +#include +#include + +int test_08 () +{ + int x = PARAM_08; + const int size = x; + const int nb_algo_max = 4; + + int array_ref [size]; + int array [nb_algo_max][size]; + int it; + int nb_algo; + + /* + * PHASE 1 : Initialisation + */ + + // Remplir le tableau + + srand(0); + + for (it = 0; it < size ; it++) + { + array_ref [it] = rand(); + for (nb_algo = 0; nb_algo < nb_algo_max; nb_algo ++) + array[nb_algo][it] = array_ref [it]; + } + + { +#ifdef HAVE_LIBC + printf("Test_08 - tri_croissant\n"); +#else + print(0xABCD0008); +#endif + + for (nb_algo = 0; nb_algo < nb_algo_max; nb_algo ++) + { +// for (it = 0; it < size ; it++) +// printf("%d ",array [it]); +// printf("\n"); + + /* + * PHASE 2 : Exécution + */ +#ifdef HAVE_LIBC + printf(" * tri_croissant - algo %d\n",nb_algo); +#endif + print(0xABCD08a0 | nb_algo); + array_tri_croissant (array[nb_algo] ,size,nb_algo); + print(0xABCD08b0 | nb_algo); + +// for (it = 0; it < size ; it++) +// printf("%d ",array [it]); +// printf("\n"); + } + } + + /* + * PHASE 3 : Vérification des résultats + */ + + // Vérifier le résultat : compte le nombre de case identique par algoritme + for (it = 0; it < size ; it++) + { + int val = array[0][it]; + + for (nb_algo = 1; nb_algo < nb_algo_max; nb_algo ++) + if (val != array[nb_algo][it]) + return 0; + } + + return (1); +} + +//---------------------------------- +// TEST 9 - hanoi +// +//---------------------------------- +int test_09 () +{ + unsigned int it, test; + unsigned int x = PARAM_09; + unsigned int x_max = 12; + + unsigned int res [x_max+1]; + unsigned int wait [x_max+1]; +#ifdef HAVE_LIBC + printf("Test_09 - hanoi\n"); +#else + print(0xABCD0009); +#endif + + wait [1] = 1; // 1 + wait [2] = 3; // 3 + wait [3] = 7; // 7 + wait [4] = 15; // f + wait [5] = 31; // 1f + wait [6] = 63; // 3f + wait [7] = 127; // 7f + wait [8] = 255; // ff + wait [9] = 511; // 1ff + wait [10] = 1023; // 3ff + wait [11] = 2047; // 7ff + wait [12] = 4095; // fff + + for (it = 1; it <= x ; it ++) + { + res [it] = hanoi (it); + + print(res [it]); + } + + test = 1; + + for (it = 1; it <= x ; it ++) + test &= (res [it] == wait [it]); + + print(test); + return (test); + +} + +//---------------------------------- +// TEST 10 +// multiplication de matrice +// * +//---------------------------------- +int test_10 () +{ + int op1, op2, res; + int x = PARAM_10; +#ifdef HAVE_LIBC + printf("Test_10 - multiplication de matrice\n"); +#else + print(0xABCD0010); +#endif + + op1 = x; + op2 = 1; + res = mm(op1,op2); + + print(res); + return (res); +} + +//---------------------------------- +// TEST 11 +// factoriel_recursif +//---------------------------------- +int test_11 () +{ + unsigned int it, test; + unsigned int x = PARAM_11; + unsigned int x_max = 12; + + unsigned int res [x_max+1]; + unsigned int wait [x_max+1]; +#ifdef HAVE_LIBC + printf("Test_11 - factoriel recursif\n"); +#else + print(0xABCD0011); +#endif + + wait[0] = 1; // 1 + wait[1] = 1; // 1 + wait[2] = 2; // 2 + wait[3] = 6; // 6 + wait[4] = 24; // 18 + wait[5] = 120; // 78 + wait[6] = 720; // 2d0 + wait[7] = 5040; // 13b0 + wait[8] = 40320; // 9d80 + wait[9] = 362880; // 58980 + wait[10] = 3628800; // 375f00 + wait[11] = 39916800; // 2611500 + wait[12] = 479001600; // 1c8cfc00 + + for (it = 0; it <= x ; it ++) + res [it] = fact_recursif (it); + + test = 1; + + for (it = 0; it <= x ; it ++) + test &= (res [it] == wait [it]); + + print(test); + return (test); +} + +//---------------------------------- +// TEST 12 +// factoriel_iteratif +//---------------------------------- +int test_12 () +{ + unsigned int it, test; + + unsigned int x = PARAM_12; + unsigned int x_max = 12; + + unsigned int res [x_max+1]; + unsigned int wait [x_max+1]; +#ifdef HAVE_LIBC + printf("Test_12 - factoriel_iteratif\n"); +#else + print(0xABCD0012); +#endif + + wait[0] = 1; // 1 + wait[1] = 1; // 1 + wait[2] = 2; // 2 + wait[3] = 6; // 6 + wait[4] = 24; // 18 + wait[5] = 120; // 78 + wait[6] = 720; // 2d0 + wait[7] = 5040; // 13b0 + wait[8] = 40320; // 9d80 + wait[9] = 362880; // 58980 + wait[10] = 3628800; // 375f00 + wait[11] = 39916800; // 2611500 + wait[12] = 479001600; // 1c8cfc00 + + for (it = 0; it <= x ; it ++) + res [it] = fact_iteratif (it); + + test = 1; + + for (it = 0; it <= x ; it ++) + test &= (res [it] == wait [it]); + + print(test); + return (test); +} + +//---------------------------------- +// TEST 13 +// parite +//---------------------------------- +int test_13 () +{ + unsigned int it; + unsigned int x = PARAM_13; + unsigned int pair,test; + +#define TEST(a,b) ( ( (a) ^ (b) ) == 0)?1:0 +#ifdef HAVE_LIBC + printf("Test_13 - parite\n"); +#else + print(0xABCD0013); +#endif + + test = 1; + + pair = 1; + srand(0); + for (it = 0; (it < x) && (test == 1); it ++) + { + unsigned int val = (unsigned int) rand(); + unsigned int val1 = parite1(val,pair); + unsigned int val2 = parite2(val,pair); + test &= TEST(val1,val2); // Test if 2 implementation produced the same result + } + print(test); + + pair ^= 1; + for (it = 0; (it < x) && (test == 1); it ++) + { + unsigned int val = (unsigned int) rand(); + unsigned int val1 = parite1(val,pair); + unsigned int val2 = parite2(val,pair); + test &= TEST(val1,val2); // Test if 2 implementation produced the same result + } + print(test); + return (test); +} Index: trunk/Softwares/Basic_test/src/c/func_test_io.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_test_io.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_test_io.c (revision 88) @@ -0,0 +1,72 @@ +#include "func_test_io.h" +#include +#include +#include +#include + +//-----[ func_test_io ]--------------------------------------------------------- + +bool func_test_io() +{ + /* + { + FILE * file; + const char * filename = "files/write.txt"; + const char * string = "La technologie au service de la paix\n"; + + printf("Test write in file\n"); + + if ((file = fopen (filename,"w")) == NULL) + printf("fopen : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + { + printf("fopen : Ok\n"); + + if (fputs (string,file) == EOF) + printf("fputs : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + printf("fputs : Ok\n"); + + if (fputs ("La paix par le pouvoir\n",file) == EOF) + printf("fputs : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + printf("fputs : Ok\n"); + + if (fclose (file) == EOF) + printf("fclose : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + printf("fclose : Ok\n"); + } + } + */ + { + FILE * file; + const char * filename = "files/read.txt"; + char * string = (char *) malloc (100); + + printf("Test read in file\n"); + + if ((file = fopen (filename,"r")) == NULL) + printf("fopen : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + { + printf("fopen : Ok\n"); + string = fgets (string,50,file); + + while (string != NULL) + { + print (string); + printf("fputs : %s\n",string); + string = fgets (string,50,file); + } + + print(string); + + if (fclose (file) == EOF) + printf("fclose : Ko - errno : %x - %s\n",errno,strerror(errno)); + else + printf("fclose : Ok\n"); + } + } + return true; +}// end fct func_test_io Index: trunk/Softwares/Basic_test/src/c/func_test_lock.c =================================================================== --- trunk/Softwares/Basic_test/src/c/func_test_lock.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/func_test_lock.c (revision 88) @@ -0,0 +1,86 @@ +#include "func_test_lock.h" +#include +__LOCK_INIT(static,lock1); +static int val1 = 0; +void test_lock1 () +{ + __lock_init (lock1); + print((unsigned int)lock1.mutex); + + while (val1 < 100) + { + __lock_acquire (lock1); + print(val1); + val1 ++; + __lock_release (lock1); + } + + __lock_close (lock1); +} + +__LOCK_INIT(static,lock2); +static int val2 = 0; +void test_lock2 () +{ + __lock_init (lock2); + print((unsigned int)lock2.mutex); + while (val2 < 100) + { + if (__lock_try_acquire (lock2) == 1) + { + print(val2); + val2 ++; + __lock_release (lock2); + } + } + + __lock_close (lock2); +} + +__LOCK_INIT_RECURSIVE(static,lock_recursive1); +static int val_recursive1 = 0; +void test_lock_recursive1 () +{ + __lock_init_recursive (lock_recursive1); + print((unsigned int)lock_recursive1.mutex); + + while (val_recursive1 < 100) + { + __lock_acquire_recursive (lock_recursive1); + __lock_acquire_recursive (lock_recursive1); + print(val_recursive1); + val_recursive1 ++; + __lock_release_recursive (lock_recursive1); + print(val_recursive1); + val_recursive1 ++; + __lock_release_recursive (lock_recursive1); + } + + __lock_close_recursive (lock_recursive1); +} + +__LOCK_INIT_RECURSIVE(static,lock_recursive2); +static int val_recursive2 = 0; +void test_lock_recursive2 () +{ + __lock_init_recursive (lock_recursive2); + print((unsigned int)lock_recursive2.mutex); + + while (val_recursive2 < 100) + { + if (__lock_try_acquire_recursive (lock_recursive2) == 1) + { + if (__lock_try_acquire_recursive (lock_recursive2) == 1) + { + print(val_recursive2); + val_recursive2 ++; + __lock_release_recursive (lock_recursive2); + } + print(val_recursive2); + val_recursive2 ++; + __lock_release_recursive (lock_recursive2); + } + } + + __lock_close_recursive (lock_recursive2); +} Index: trunk/Softwares/Basic_test/src/c/include/bottles.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/bottles.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/bottles.h (revision 88) @@ -0,0 +1,2 @@ + +void bottles(); Index: trunk/Softwares/Basic_test/src/c/include/dhry.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/dhry.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/dhry.h (revision 88) @@ -0,0 +1,408 @@ +/* + ************************************************************************* + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens Nixdorf Inf. Syst. + * STM OS 32 + * Otto-Hahn-Ring 6 + * W-8000 Muenchen 83 + * Germany + * Phone: [+49]-89-636-42436 + * (8-17 Central European Time) + * UUCP: weicker@ztivax.uucp@unido.uucp + * Internet: weicker@ztivax.siemens.com + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are + * used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 834-1378 (9-17 EST) + * UUCP: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software + * used. Hardware information includes: Machine type, CPU, type and + * size of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). Software information includes: Compiler + * (and runtime library) manufacturer and version, compilation + * switches, OS version. The Operating System version may give an + * indication about the compiler; Dhrystone itself performs no OS + * calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + ************************************************************************* + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used + * most. There should be, as far as possible, only one C + * version of Dhrystone such that results can be compared + * without restrictions. In the past, the C versions + * distributed by Rick Richardson (Version 1.1) and by + * Reinhold Weicker had small (though not significant) + * differences. + * + * 2) As far as it is possible without changes to the + * Dhrystone statistics, optimizing compilers should be + * prevented from removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold + * Weicker. As a concession to older compilers, names have + * been made unique within the first 8 characters. Inside the + * measurement loop, this version follows the version + * previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing + * compilers should be prevented from moving code out of the + * measurement loop, or from removing code altogether. Since + * the statements that are executed within the measurement + * loop have NOT been changed, the numbers defining the + * "Dhrystone distribution" (distribution of statements, + * operand types and locality) still hold. Except for + * sophisticated optimizing compilers, execution times for + * this version should be the same as for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic + * benchmarks. Users of the benchmark are advised to check + * code listings whether code is generated for all statements + * of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it + * corrects some minor deficiencies that were found by users + * of version 2.0. The only change within the measurement + * loop is that a non-executed "else" part was added to the + * "if" statement in Func_3, and a non-executed "else" part + * removed from Proc_3. + * + ************************************************************************* + * + * Defines: The following "Defines" are possible: + * -DROPT (default: Not defined) + * As an approximation to what an average C + * programmer might do, the "register" storage class + * is applied (if enabled by -DROPT) + * - for local variables, if they are used + * (dynamically) five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" + * declarations do not necessarily lead to faster + * execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * + ************************************************************************* + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be + * indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system + * used. + * + ************************************************************************* + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values as implicit parameters). + * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a + * record component), only the final data type on the access path is + * counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is + * syntactically and semantically correct. All variables have a value + * assigned to them before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code + * or data. + * + ************************************************************************* + */ + +#ifndef DHRY +#define DHRY + +/* Compiler and system dependent definitions: */ + +// #ifdef SIM2OS +// #define DOUBLE unsigned int +// #define Mic_secs_Per_Second 1000000 +// #else +#define DOUBLE float +#define Mic_secs_Per_Second 1000000.0 +// #endif //SIM2OS + + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + +#endif //!DHRY Index: trunk/Softwares/Basic_test/src/c/include/dhry21.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/dhry21.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/dhry21.h (revision 88) @@ -0,0 +1,15 @@ +#include "dhry.h" + +int main_dhry21 (); + +void Proc_1 (Rec_Pointer); +void Proc_2 (One_Fifty *); +void Proc_3 (Rec_Pointer *); +void Proc_4 (); +void Proc_5 (); +void Proc_6 (Enumeration, Enumeration*); +void Proc_7 (One_Fifty,One_Fifty,One_Fifty*); +void Proc_8 (Arr_1_Dim,Arr_2_Dim,int,int); +Enumeration Func_1 (Capital_Letter,Capital_Letter); +Boolean Func_2 (Str_30,Str_30); +Boolean Func_3 (Enumeration); Index: trunk/Softwares/Basic_test/src/c/include/dico.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/dico.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/dico.h (revision 88) @@ -0,0 +1,32 @@ +#ifndef DICO_H +#define DICO_H + +#include "bool.h" + +//=====[ dico_t ]========================================== + +typedef struct dico_st +{ + void * key; + void * data; + + struct dico_st * previous; + struct dico_st * next; +} dico_t; + +//=====[ function ]======================================== + +dico_t * dico_add (dico_t * dico, + void * key , + void * data); + +dico_t * dico_del (dico_t * dico, + void * key ); + +bool dico_present (dico_t * dico, + void * key ); + +void * dico_give (dico_t * dico, + void * key ); + +#endif //!DICO_H Index: trunk/Softwares/Basic_test/src/c/include/exec.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/exec.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/exec.h (revision 88) @@ -0,0 +1,6 @@ +#include "bool.h" + +bool exec_0(); +bool exec_1(); +bool exec_2(); +bool exec_3(); Index: trunk/Softwares/Basic_test/src/c/include/func_array.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_array.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_array.h (revision 88) @@ -0,0 +1,2 @@ + +void array_tri_croissant (int * array, unsigned int size,int algo); Index: trunk/Softwares/Basic_test/src/c/include/func_endianness.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_endianness.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_endianness.h (revision 88) @@ -0,0 +1,18 @@ +#include "bool.h" + +#define LittleEndian false +#define BigEndian true + +union TestEndian +{ + unsigned long total; + struct + { + unsigned char octet1; + unsigned char octet2; + unsigned char octet3; + unsigned char octet4; + } octets; +}; + +bool endianness (); Index: trunk/Softwares/Basic_test/src/c/include/func_factoriel.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_factoriel.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_factoriel.h (revision 88) @@ -0,0 +1,2 @@ +unsigned int fact_recursif (unsigned int x); +unsigned int fact_iteratif (unsigned int x); Index: trunk/Softwares/Basic_test/src/c/include/func_fibonnacci.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_fibonnacci.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_fibonnacci.h (revision 88) @@ -0,0 +1,1 @@ +int fibonnacci(int x); Index: trunk/Softwares/Basic_test/src/c/include/func_hanoi.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_hanoi.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_hanoi.h (revision 88) @@ -0,0 +1,1 @@ +int hanoi(int nb_disques); Index: trunk/Softwares/Basic_test/src/c/include/func_integrity.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_integrity.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_integrity.h (revision 88) @@ -0,0 +1,3 @@ +#include "bool.h" + +bool test_integrity (); Index: trunk/Softwares/Basic_test/src/c/include/func_math.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_math.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_math.h (revision 88) @@ -0,0 +1,10 @@ +unsigned int mul_soft ( unsigned int op1, + unsigned int op2); +unsigned int mul_hard ( unsigned int op1, + unsigned int op2); +unsigned int div_soft ( unsigned int op1, + unsigned int op2); +unsigned int div_hard ( unsigned int op1, + unsigned int op2); +unsigned int modulo ( unsigned int x, + unsigned int base); Index: trunk/Softwares/Basic_test/src/c/include/func_mm.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_mm.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_mm.h (revision 88) @@ -0,0 +1,1 @@ +int mm(unsigned int size_matrix, unsigned int algo); Index: trunk/Softwares/Basic_test/src/c/include/func_parite.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_parite.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_parite.h (revision 88) @@ -0,0 +1,7 @@ +#include "bool.h" + +// Renvoye 1 si le nombre de bit a 1 est impaire +// 0 paire + +bool parite1(int x,int val_parite); +bool parite2(int x,int val_parite); Index: trunk/Softwares/Basic_test/src/c/include/func_premier.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_premier.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_premier.h (revision 88) @@ -0,0 +1,2 @@ +unsigned int premier(unsigned int x); +unsigned int n_premier(unsigned int nieme_premier); Index: trunk/Softwares/Basic_test/src/c/include/func_test.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_test.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_test.h (revision 88) @@ -0,0 +1,16 @@ +#include +#include + +int test_01(); +int test_02(); +int test_03(); +int test_04(); +int test_05(); +int test_06(); +int test_07(); +int test_08(); +int test_09(); +int test_10(); +int test_11(); +int test_12(); +int test_13(); Index: trunk/Softwares/Basic_test/src/c/include/func_test_io.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_test_io.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_test_io.h (revision 88) @@ -0,0 +1,4 @@ +#include "bool.h" + + +bool func_test_io(); Index: trunk/Softwares/Basic_test/src/c/include/func_test_lock.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/func_test_lock.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/func_test_lock.h (revision 88) @@ -0,0 +1,4 @@ +void test_lock1 (); +void test_lock2 (); +void test_lock_recursive1 (); +void test_lock_recursive2 (); Index: trunk/Softwares/Basic_test/src/c/include/test_setjmp.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/test_setjmp.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/test_setjmp.h (revision 88) @@ -0,0 +1,2 @@ + +void test_setjmp (); Index: trunk/Softwares/Basic_test/src/c/include/workload.h =================================================================== --- trunk/Softwares/Basic_test/src/c/include/workload.h (revision 88) +++ trunk/Softwares/Basic_test/src/c/include/workload.h (revision 88) @@ -0,0 +1,16 @@ +#include "dhry21.h" +#include "exec.h" + +/* + * Array of function's pointer + */ + +void (*WorkLoad[])() = +{ + (void *)exec_0 , + (void *)exec_1 , + (void *)exec_2 , + (void *)exec_3 +}; + +#define NB_WORKLOAD (sizeof(WorkLoad)/sizeof(void *)) Index: trunk/Softwares/Basic_test/src/c/main.c =================================================================== --- trunk/Softwares/Basic_test/src/c/main.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/main.c (revision 88) @@ -0,0 +1,242 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bool.h" +#include "test_setjmp.h" +#include "func_io.h" +#include "func_test_io.h" +#include "func_test_lock.h" +#include "func_integrity.h" +#include "thread_info.h" +#include "cpu_info.h" +#include "uncached_mask.h" +#include "bottles.h" + +#include "workload.h" + +#define verbose_none 0 +#define verbose_low 1 +#define verbose_medium 2 +#define verbose_high 3 +#define VERBOSE_SYSTEM verbose_none +#define HAVE_SYSTEM 1 + +void init_thread (); +void exit_thread (); +#if (HAVE_SYSTEM != 0) +void init_system (); +void exit_system (); +#endif //HAVE_SYSTEM + +//~~~~~[ global variable ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +__LOCK_INIT(static,system_lock); + +#if (HAVE_SYSTEM != 0) +static volatile bool system_init = false; +#endif //HAVE_SYSTEM +static volatile unsigned int nb_thread_run = 0; + +//=====[ main ]================================================================= +/* + * All thread execute this routine + * Initialize the thread and attribute a Workload at each thread + */ + +int main() +{ + init_thread(); + +/* test_integrity (); */ +/* test_setjmp(); */ +/* func_test_io(); */ +/* test_lock1(); */ +/* test_lock2(); */ +/* test_lock_recursive1(); */ +/* test_lock_recursive2(); */ + + /* + * Lunch thread with a Workload + */ +#if (VERBOSE_SYSTEM >= verbose_medium) + printf("
: lunch workload\n"); +#endif //VERBOSE_SYSTEM + + { + int pid = (int)getpid(); + + if (pid < NB_WORKLOAD) + (*WorkLoad[pid])(); + else + printf("
pid is %d but the number of function in the workload is %d\n",pid,(int)NB_WORKLOAD); + } + +#if (VERBOSE_SYSTEM >= verbose_medium) + printf("
: exit workload\n"); +#endif //VERBOSE_SYSTEM + + exit (0); +} + +//-----[ init_thread ]---------------------------------------------------------- +/* + * Initialize all thread + */ + +void init_thread() +{ + unsigned int pid; + + set_uncached_mask (0x80000000); + + __lock_init (system_lock); + + // Test if is the first thread -> initialization of system + __lock_acquire (system_lock); + pid = nb_thread_run ++; + __lock_release (system_lock); + + // Change parameters of thread + // * Identificator + // * Priority + set_thread_id (pid); + set_thread_priority (0xF); + + // Initialize Reentrant structure + _REENT_INIT_PTR(_REENT); + +#if (HAVE_SYSTEM != 0) + if (pid == 0) + init_system(); + + while (system_init == false); +#endif //HAVE_SYSTEM + + + // Test if is the first thread -> initialization of system + atexit (exit_thread); + + print((get_thread_id() << 16) | get_cpu_id()); + +#if (VERBOSE_SYSTEM >= verbose_low) + printf(" Thread[%d] executed on CPU[%d]\n",getpid(),get_cpu_id()); +#endif //VERBOSE_SYSTEM +} + +//-----[ exit_thread ]---------------------------------------------------------- +/* + * Free all ressource + */ + +void exit_thread() +{ + bool last = false; + +#if (VERBOSE_SYSTEM >= verbose_low) + printf(" Thread[%d] is finish\n",getpid()); +#endif //VERBOSE_SYSTEM + + __lock_acquire (system_lock); + + nb_thread_run --; + last = (nb_thread_run == 0)?true:false; + + __lock_release (system_lock); + +#if (HAVE_SYSTEM != 0) + if (last == true) + exit_system(); +#endif //HAVE_SYSTEM + + quit(getpid()); + + while(1); +} + + +#if (HAVE_SYSTEM != 0) +//-----[ init_system ]---------------------------------------------------------- +/* + * Initialize all system + */ + +void init_system() +{ +#if (VERBOSE_SYSTEM >= verbose_high) + time_t * my_time = (time_t *) malloc (sizeof (time_t)); + + if (my_time == NULL) + { + printf(" {error} malloc\n"); + exit(-1); + } + + if (time(my_time) == ((time_t)-1)) + { + printf(" {error} time\n"); + exit (-1); + } + + printf(" System boot - %s",ctime(my_time)); + + free(my_time); +#else +#if (VERBOSE_SYSTEM >= verbose_low) + printf(" System boot\n"); +#endif //VERBOSE_SYSTEM +#endif //VERBOSE_SYSTEM + +#if (VERBOSE_SYSTEM >= verbose_medium) + printf("\n"); + printf("@ @ @@@@ @@@@@ @@@@@ @ @ @@@@@@ @@@@ \n"); + printf("@@ @@ @ @ @ @ @ @ @ @ @ @ @ \n"); + printf("@ @@@ @ @ @ @@@@@ @@@@@ @@@@@@ @@@@ @ @ \n"); + printf("@ @ @ @ @ @ @ @ @ @ @ @ \n"); + printf("@ @ @@@@ @ @ @ @ @ @@@@@@ @@@@ \n"); + printf("@ @utiple ORganization for a Processor HEterogenous and Open.\n"); + printf("\n"); +#endif //VERBOSE_SYSTEM + + system_init = true; +} + +//-----[ exit_system ]---------------------------------------------------------- +/* + * Free all ressource + */ + +void exit_system() +{ +#if (VERBOSE_SYSTEM >= verbose_high) + time_t * my_time = (time_t *) malloc (sizeof (time_t)); + + if (my_time == NULL) + { + printf(" {error} malloc\n"); + exit(-1); + } + + if (time(my_time) == ((time_t)-1)) + { + printf(" {error} time\n"); + exit (-1); + } + + printf(" System shutdown - %s",ctime(my_time)); + + free (my_time); +#else +#if (VERBOSE_SYSTEM >= verbose_medium) + printf(" System shutdown\n"); +#endif //VERBOSE_SYSTEM +#endif //VERBOSE_SYSTEM +} +#endif //HAVE_SYSTEM Index: trunk/Softwares/Basic_test/src/c/test_setjmp.c =================================================================== --- trunk/Softwares/Basic_test/src/c/test_setjmp.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/test_setjmp.c (revision 88) @@ -0,0 +1,49 @@ +#include +#include +#include +#include +jmp_buf env; + +int exec_setjmp (int val_max, int base) +{ + int res = -2; + int val = setjmp(env); // 1 call = 0, first return of longjmp -> 1, après renvoye X^N + + if (val < val_max) + { + print(val); + res ++; + longjmp (env,base*val); + } + + return res; +} + +int test_setjmp () +{ + quit(exec_setjmp (366,2)); + + return (1); + + /* + int base = 2; + int val,res,it; + + srand(0); + + for (it = 0; it < 10; it ++) + { + val = (rand()%1500); + + res = exec_setjmp (val,base); + + print(res); + + //printf("test_setjmp : log2(%d)=%d (%d)\n",val,res,(unsigned int)log2((double)val)); + + if ((unsigned int)log2(val) != res) + return 0; + } + return 1; + */ +} Index: trunk/Softwares/Basic_test/src/c/timers_b.c =================================================================== --- trunk/Softwares/Basic_test/src/c/timers_b.c (revision 88) +++ trunk/Softwares/Basic_test/src/c/timers_b.c (revision 88) @@ -0,0 +1,489 @@ +/*****************************************************/ +/* Various timer routines. */ +/* Al Aburto, aburto@nosc.mil, 18 Feb 1997 */ +/* */ +/* t = dtime() outputs the current time in seconds. */ +/* Use CAUTION as some of these routines will mess */ +/* up when timing across the hour mark!!! */ +/* */ +/* For timing I use the 'user' time whenever */ +/* possible. Using 'user+sys' time is a separate */ +/* issue. */ +/* */ +/* Example Usage: */ +/* [timer options added here] */ +/* main() */ +/* { */ +/* double starttime,benchtime,dtime(); */ +/* */ +/* starttime = dtime(); */ +/* [routine to time] */ +/* benchtime = dtime() - starttime; */ +/* } */ +/* */ +/* [timer code below added here] */ +/*****************************************************/ + +/***************************************************************/ +/* Timer options. You MUST uncomment one of the options below */ +/* or compile, for example, with the '-DUNIX' option. */ +/***************************************************************/ +/* #define Amiga */ +/* #define UNIX */ +/* #define UNIX_Old */ +/* #define VMS */ +/* #define BORLAND_C */ +/* #define MSC */ +/* #define MAC */ +/* #define IPSC */ +/* #define FORTRAN_SEC */ +/* #define GTODay */ +/* #define CTimer */ +/* #define UXPM */ +/* #define MAC_TMgr */ +/* #define PARIX */ +/* #define POSIX */ +/* #define WIN32 */ +/* #define POSIX1 */ +/***********************/ + +/*********************************/ +/* Timer code. */ +/*********************************/ + +/***************************************************/ +/* SIM2OS dtime(). */ +/***************************************************/ +#ifdef SIM2OS + +#include +#include "dhry.h" +#include "service_clock.h" + +#ifndef MHZ +#define MHZ (1000000) +#endif //!MHZ + +#ifndef FRQ +#define FRQ (1*MHZ) +#endif //!FRQ + +DOUBLE dtime() +{ + DOUBLE dtime; + + dtime = (DOUBLE)(service_clock())/(DOUBLE)FRQ; + + return (dtime); +} +#endif + +/*******************/ +/* Amiga dtime() */ +/*******************/ +#ifdef Amiga +#include +#define HZ 50 + +double dtime() +{ + double q; + + struct tt + { + long days; + long minutes; + long ticks; + } tt; + + DateStamp(&tt); + + q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ; + + return q; +} +#endif + +/*****************************************************/ +/* UNIX dtime(). This is the preferred UNIX timer. */ +/* Provided by: Markku Kolkka, mk59200@cc.tut.fi */ +/* HP-UX Addition by: Bo Thide', bt@irfu.se */ +/*****************************************************/ +#ifdef UNIX +#include +#include + +#ifdef hpux +#include +#define getrusage(a,b) syscall(SYS_getrusage,a,b) +#endif + +struct rusage rusage; + +double dtime() +{ + double q; + getrusage(RUSAGE_SELF,&rusage); + q = (double)(rusage.ru_utime.tv_sec); + q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06; + return q; +} +#endif + +/***************************************************/ +/* UNIX_Old dtime(). This is the old UNIX timer. */ +/* Make sure HZ is properly defined in param.h !! */ +/***************************************************/ +#ifdef UNIX_Old +#include +#include +#include + +#ifndef HZ +#define HZ 60 +#endif + +struct tms tms; + +double dtime() +{ + double q; + + times(&tms); + + q = (double)(tms.tms_utime) / (double)HZ; + + return q; +} +#endif + +/*********************************************************/ +/* VMS dtime() for VMS systems. */ +/* Provided by: RAMO@uvphys.phys.UVic.CA */ +/* Some people have run into problems with this timer. */ +/*********************************************************/ +#ifdef VMS +#include time + +#ifndef HZ +#define HZ 100 +#endif + +struct tbuffer_t + { + int proc_user_time; + int proc_system_time; + int child_user_time; + int child_system_time; + }; + +struct tbuffer_t tms; + +double dtime() +{ + double q; + + times(&tms); + + q = (double)(tms.proc_user_time) / (double)HZ; + + return q; +} +#endif + +/******************************/ +/* BORLAND C dtime() for DOS */ +/******************************/ +#ifdef BORLAND_C +#include +#include +#include + +#define HZ 100 +struct time tnow; + +double dtime() +{ + double q; + + gettime(&tnow); + + q = 60.0 * (double)(tnow.ti_min); + q = q + (double)(tnow.ti_sec); + q = q + (double)(tnow.ti_hund)/(double)HZ; + + return q; +} +#endif + +/**************************************/ +/* Microsoft C (MSC) dtime() for DOS */ +/**************************************/ +#ifdef MSC +#include +#include + +#define HZ CLOCKS_PER_SEC +clock_t tnow; + +double dtime() +{ + double q; + + tnow = clock(); + + q = (double)tnow / (double)HZ; + + return q; +} +#endif + +/*************************************/ +/* Macintosh (MAC) Think C dtime() */ +/*************************************/ +#ifdef MAC +#include + +#define HZ 60 + +double dtime() +{ + double q; + + q = (double)clock() / (double)HZ; + + return q; +} +#endif + +/************************************************************/ +/* iPSC/860 (IPSC) dtime() for i860. */ +/* Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU */ +/************************************************************/ +#ifdef IPSC +extern double dclock(); + +double dtime() +{ + double q; + + q = dclock(); + + return q; +} +#endif + +/**************************************************/ +/* FORTRAN dtime() for Cray type systems. */ +/* This is the preferred timer for Cray systems. */ +/**************************************************/ +#ifdef FORTRAN_SEC + +fortran double second(); + +double dtime() +{ + double q; + + second(&q); + + return q; +} +#endif + +/***********************************************************/ +/* UNICOS C dtime() for Cray UNICOS systems. Don't use */ +/* unless absolutely necessary as returned time includes */ +/* 'user+system' time. Provided by: R. Mike Dority, */ +/* dority@craysea.cray.com */ +/***********************************************************/ +#ifdef CTimer +#include + +double dtime() +{ + double q; + clock_t clock(void); + + q = (double)clock() / (double)CLOCKS_PER_SEC; + + return q; +} +#endif + +/********************************************/ +/* Another UNIX timer using gettimeofday(). */ +/* However, getrusage() is preferred. */ +/********************************************/ +#ifdef GTODay +#include + +struct timeval tnow; + +double dtime() +{ + double q; + + gettimeofday(&tnow,NULL); + q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6; + + return q; +} +#endif + +/*****************************************************/ +/* Fujitsu UXP/M timer. */ +/* Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */ +/*****************************************************/ +#ifdef UXPM +#include +#include +struct tmsu rusage; + +double dtime() +{ + double q; + + timesu(&rusage); + + q = (double)(rusage.tms_utime) * 1.0e-06; + + return q; +} +#endif + +/**********************************************/ +/* Macintosh (MAC_TMgr) Think C dtime() */ +/* requires Think C Language Extensions or */ +/* #include in the prefix */ +/* provided by Francis H Schiffer 3rd (fhs) */ +/* skipschiffer@genie.geis.com */ +/**********************************************/ +#ifdef MAC_TMgr +#include +#include + +static TMTask mgrTimer; +static Boolean mgrInited = false; +static double mgrClock; + +#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer ) +#define MAX_TIME 1800000000L +/* MAX_TIME limits time between calls to */ +/* dtime( ) to no more than 30 minutes */ +/* this limitation could be removed by */ +/* creating a completion routine to sum */ +/* 30 minute segments (fhs 1994 feb 9) */ + +static void Remove_timer( ) +{ + RMV_TIMER; + mgrInited = false; +} + +double dtime( ) +{ + if( mgrInited ) { + RMV_TIMER; + mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6; + } else { + if( _atexit( &Remove_timer ) == 0 ) mgrInited = true; + mgrClock = 0.0; + } + + if ( mgrInited ) + { + mgrTimer.tmAddr = NULL; + mgrTimer.tmCount = 0; + mgrTimer.tmWakeUp = 0; + mgrTimer.tmReserved = 0; + InsTime( (QElemPtr)&mgrTimer ); + PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME ); + } + return( mgrClock ); +} +#endif + +/***********************************************************/ +/* Parsytec GCel timer. */ +/* Provided by: Georg Wambach, gw@informatik.uni-koeln.de */ +/***********************************************************/ +#ifdef PARIX +#include + +double dtime() +{ + double q; + + q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH; + + return q; +} +#endif + +/************************************************/ +/* Sun Solaris POSIX dtime() routine */ +/* Provided by: Case Larsen, CTLarsen.lbl.gov */ +/************************************************/ +#ifdef POSIX +#include +#include +#include + +#ifdef __hpux +#include +#endif + +struct rusage rusage; + +double dtime() +{ + double q; + + getrusage(RUSAGE_SELF,&rusage); + + q = (double)(rusage.ru_utime.tv_sec); + q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09; + + return q; +} +#endif + + +/****************************************************/ +/* Windows NT (32 bit) dtime() routine */ +/* Provided by: Piers Haken, piersh@microsoft.com */ +/****************************************************/ +#ifdef WIN32 +#include + +double dtime(void) +{ + double q; + + q = (double)GetTickCount() * 1.0e-03; + + return q; +} +#endif + +/*****************************************************/ +/* Time according to POSIX.1 - */ +/* Ref: "POSIX Programmer's Guide" O'Reilly & Assoc.*/ +/*****************************************************/ +#ifdef POSIX1 +#define _POSIX_SOURCE 1 +#include +#include +#include + +struct tms tms; + +double dtime() +{ + double q; + times(&tms); + q = (double)tms.tms_utime / (double)CLK_TCK; + return q; +} +#endif Index: trunk/Softwares/Global/include/bool.h =================================================================== --- trunk/Softwares/Global/include/bool.h (revision 88) +++ trunk/Softwares/Global/include/bool.h (revision 88) @@ -0,0 +1,30 @@ +#ifndef BOOL_H +#define BOOL_H + +// typedef enum{false,true} bool; + +#ifndef BOOL +#define BOOL int +#endif + +#ifndef bool +#define bool int +#endif + +#ifndef false +#define false 0 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef true +#define true 1 +#endif + +#endif //!BOOL_H Index: trunk/Softwares/Global/include/cpu_info.h =================================================================== --- trunk/Softwares/Global/include/cpu_info.h (revision 88) +++ trunk/Softwares/Global/include/cpu_info.h (revision 88) @@ -0,0 +1,3 @@ + +extern unsigned int get_cpu_id(); +extern void set_cpu_id(unsigned int); Index: trunk/Softwares/Global/include/find_one.h =================================================================== --- trunk/Softwares/Global/include/find_one.h (revision 88) +++ trunk/Softwares/Global/include/find_one.h (revision 88) @@ -0,0 +1,1 @@ +unsigned int find_first_one (unsigned int val); Index: trunk/Softwares/Global/include/func_io.h =================================================================== --- trunk/Softwares/Global/include/func_io.h (revision 88) +++ trunk/Softwares/Global/include/func_io.h (revision 88) @@ -0,0 +1,4 @@ +#include "mapping_memory.h" + +void print(int data); +void quit (int data); Index: trunk/Softwares/Global/include/mapping_memory.h =================================================================== --- trunk/Softwares/Global/include/mapping_memory.h (revision 88) +++ trunk/Softwares/Global/include/mapping_memory.h (revision 88) @@ -0,0 +1,1 @@ +#include "../../../IPs/systemC/shared/mapping_memory.h" Index: trunk/Softwares/Global/include/service_clock.h =================================================================== --- trunk/Softwares/Global/include/service_clock.h (revision 88) +++ trunk/Softwares/Global/include/service_clock.h (revision 88) @@ -0,0 +1,1 @@ +unsigned int service_clock (); Index: trunk/Softwares/Global/include/thread_info.h =================================================================== --- trunk/Softwares/Global/include/thread_info.h (revision 88) +++ trunk/Softwares/Global/include/thread_info.h (revision 88) @@ -0,0 +1,5 @@ + +extern unsigned int get_thread_id (); +extern void set_thread_id (unsigned int); +extern unsigned int get_thread_priority (); +extern void set_thread_priority (unsigned int); Index: trunk/Softwares/Global/include/uncached_mask.h =================================================================== --- trunk/Softwares/Global/include/uncached_mask.h (revision 88) +++ trunk/Softwares/Global/include/uncached_mask.h (revision 88) @@ -0,0 +1,3 @@ + +extern unsigned int get_uncached_mask (); +extern void set_uncached_mask (unsigned int); Index: trunk/Softwares/Global/ldscript/or32.ld =================================================================== --- trunk/Softwares/Global/ldscript/or32.ld (revision 88) +++ trunk/Softwares/Global/ldscript/or32.ld (revision 88) @@ -0,0 +1,94 @@ +ENTRY(_start) +OUTPUT_ARCH(or32) +/* +__DYNAMIC = 0; +*/ + +/* + * Memory Mapping + */ + +MEMORY +{ + iram : ORIGIN = 0x00000000, LENGTH = 0x01000000 + dram : ORIGIN = 0x10000000, LENGTH = 0x10000000 + dram_unc : ORIGIN = 0x40000000, LENGTH = 0x01000000 +} + +/* + * Allocate the stack to be at the top of memory, since the stack + * grows down. + */ +PROVIDE (_stack = 0x52000000 - 4); +PROVIDE (__stack = 0x52000000 - 4); +PROVIDE (_stack_alloc = 0x00500000 ); +PROVIDE (_tty = 0xa0000000 ); + +SECTIONS +{ + /* + * Code + */ + + .text : + { + *(.text) + } > iram + + /* + * Data + */ + + .rodata : + { + *(.rodata); + *(.rodata.*); + } > dram + + .data : + { + sdata = .; + _sdata = .; + *(.data) + edata = .; + _edata = .; + } > dram + .bss SIZEOF(.data) + ADDR(.data) : + { + sbss = . ; + _sbss = . ; + __bss_start = ALIGN(0x8); + ___bss_start = ALIGN(0x8); + *(.bss) + *(COMMON) + end = ALIGN(0x8); + _end = ALIGN(0x8); + __end = ALIGN(0x8); + ebss = .; + _ebss = .; + } +/* + .stab 0 (NOLOAD) : + { + [ .stab ] + } + + .stabstr 0 (NOLOAD) : + { + [ .stabstr ] + } +*/ + + + /* + * Suppression de la section comment + */ + + /DISCARD/ : + { + *(.comment) + *(.gnu.*) + *(.stab*) + } +} + Index: trunk/Softwares/Global/src/asm/cpu_info.s =================================================================== --- trunk/Softwares/Global/src/asm/cpu_info.s (revision 88) +++ trunk/Softwares/Global/src/asm/cpu_info.s (revision 88) @@ -0,0 +1,18 @@ +/* + * Manipulation of processor information + */ + + .file "cpu_info.s" + .section .text + .align 4 + + .global _get_cpu_id +_get_cpu_id : + l.jr r9 + l.mfspr r11,r0,0xF800 /* R11 <- SPR[31][0] */ + + .global _set_cpu_id +_set_cpu_id : + l.jr r9 + l.mtspr r0 ,r3,0xF800 /* SPR[31][0] <- r3 */ + Index: trunk/Softwares/Global/src/asm/find_one.s =================================================================== --- trunk/Softwares/Global/src/asm/find_one.s (revision 88) +++ trunk/Softwares/Global/src/asm/find_one.s (revision 88) @@ -0,0 +1,19 @@ +/* + * Manipulation of bits + */ + + .file "find_one.s" + .section .text + .align 4 + + .global _find_first_one +_find_first_one : + l.jr r9 + l.ff1 r11,r3 + +/* + .global _find_last_one +_find_last_one : + l.jr r9 + l.fl1 r11,r3,r0 +*/ Index: trunk/Softwares/Global/src/asm/thread_info.s =================================================================== --- trunk/Softwares/Global/src/asm/thread_info.s (revision 88) +++ trunk/Softwares/Global/src/asm/thread_info.s (revision 88) @@ -0,0 +1,28 @@ +/* + * Manipulation of thread information + */ + + .file "thread_info.s" + .section .text + .align 4 + + .global _get_thread_id +_get_thread_id : + l.jr r9 + l.mfspr r11,r0,0xF801 /* R11 <- SPR[31][1] */ + + .global _set_thread_id +_set_thread_id : + l.jr r9 + l.mtspr r0 ,r3,0xF801 /* SPR[31][1] <- r3 */ + + .global _get_thread_priority +_get_thread_priority : + l.jr r9 + l.mfspr r11,r0,0xF802 /* R11 <- SPR[31][2] */ + + .global _set_thread_priority +_set_thread_priority : + l.jr r9 + l.mtspr r0 ,r3,0xF802 /* SPR[31][2] <- r3 */ + Index: trunk/Softwares/Global/src/asm/uncached_mask.s =================================================================== --- trunk/Softwares/Global/src/asm/uncached_mask.s (revision 88) +++ trunk/Softwares/Global/src/asm/uncached_mask.s (revision 88) @@ -0,0 +1,17 @@ +/* + * Manipulation of thread information + */ + + .file "uncached_mask.s" + .section .text + .align 4 + + .global _get_uncached_mask +_get_uncached_mask : + l.jr r9 + l.mfspr r11,r0,0xF803 /* R11 <- SPR[31][3] */ + + .global _set_uncached_mask +_set_uncached_mask : + l.jr r9 + l.mtspr r0 ,r3,0xF803 /* SPR[31][1] <- r3 */ Index: trunk/Softwares/Global/src/c/func_io.c =================================================================== --- trunk/Softwares/Global/src/c/func_io.c (revision 88) +++ trunk/Softwares/Global/src/c/func_io.c (revision 88) @@ -0,0 +1,16 @@ +#include "func_io.h" +#include "thread_info.h" + +void print(int data) +{ + int *show =(int*)(TTY_BASE + (get_thread_id() << 4) + 8); + + *(show) = data; +} + +void quit (int data) +{ + int *stop =(int*)(TTY_BASE + (get_thread_id() << 4) + 4); + + *(stop) = data; +} Index: trunk/Softwares/Global/src/c/service_clock.c =================================================================== --- trunk/Softwares/Global/src/c/service_clock.c (revision 88) +++ trunk/Softwares/Global/src/c/service_clock.c (revision 88) @@ -0,0 +1,31 @@ +#include +#include +#include +#include "mapping_memory.h" +#include "sim2os.h" +#include "service_clock.h" + +unsigned int service_clock () +{ + unsigned int * addr = (unsigned int *)(SIM2OS_BASE); + unsigned int result = -1; + + __lock_init (service_lock); + + __lock_acquire (service_lock); + + *(addr+0) = (unsigned int)SERVICE_CLOCK; + + // memory synchronisation + // (else read (with an address that depend not of store address) can be lunch before a store) + asm("l.msync;"); + + result = (clock_t) *(addr+1); + + if (result == (clock_t)-1) + errno = (int) *(addr+2); + + __lock_release (service_lock); + + return result; +} Index: trunk/Softwares/Global/src/sys/crt0.s =================================================================== --- trunk/Softwares/Global/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Global/src/sys/crt0.s (revision 88) @@ -0,0 +1,1 @@ +link /users/cao/kane/Project/Morpheo/Tools/newlib/libgloss/or32/crt0.S Index: trunk/Softwares/Makefile =================================================================== --- trunk/Softwares/Makefile (revision 88) +++ trunk/Softwares/Makefile (revision 88) @@ -0,0 +1,52 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined") +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif + +#-----[ Variables ]--------------------------------------------------------------- + +SOFT = Min \ + Test/* + +#-----[ Rules ]------------------------------------------------------------------- + +all : + @\ + for i in $(SOFT); do \ + $(ECHO) "-------------------| $$i"; \ + $(MAKE) --directory=$$i --makefile=Makefile; \ + done; + +clean : + @\ + $(RM) *~; \ + for i in $(SOFT); do \ + $(ECHO) "-------------------| $$i"; \ + $(MAKE) --directory=$$i --makefile=Makefile clean; \ + done; + +clean_all : + @\ + for i in $(SOFT); do \ + $(ECHO) "-------------------| $$i"; \ + $(MAKE) --directory=$$i --makefile=Makefile clean_all; \ + done; + +#-----[ Help ]-------------------------------------------------------------------- +help : + @\ + $(ECHO) "";\ + $(ECHO) "List of directive : ";\ + $(ECHO) " * all : Compile all softwares";\ + $(ECHO) " * clean : Erase all files generates";\ + $(ECHO) " * clean_all : Erase all files generates";\ + $(ECHO) ""; Index: trunk/Softwares/Makefile.Software =================================================================== --- trunk/Softwares/Makefile.Software (revision 87) +++ trunk/Softwares/Makefile.Software (revision 88) @@ -1,12 +1,21 @@ -include $(MORPHEO_TOPLEVEL)/Makefile.tools +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined") +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif #-----[ Directory ]--------------------------------------------------------------- -DIRECTORY_OBJ = obj -DIRECTORY_BIN = bin +DIR_OBJ = obj +DIR_BIN = bin EXE = soft - -#-----[ Files ]------------------------------------------------------------------- -OBJECTS = $(OBJECTS_SYS) $(OBJECTS_ASM) $(OBJECTS_C) #-----[ To the compilation ]------------------------------------------------------ @@ -37,72 +46,58 @@ # -DHAVE_LIBC OR32_AS_OPT = -OR32_LD_OPT = -T$(DIRECTORY_LDSCRIPT)/or32.ld $(LIBRARY) +OR32_LD_OPT = -T$(DIR_LDSCRIPT)/or32.ld $(LIBRARY) OR32_OBJDUMP_OPT = -D OR32_NM_OPT = -n #-----[ Rules ]------------------------------------------------------------------- -.PRECIOUS : $(DIRECTORY_BIN)/%.x.txt $(DIRECTORY_BIN)/%.x $(DIRECTORY_OBJ)/%.o +.PRECIOUS : $(DIR_BIN)/%.x.txt $(DIR_BIN)/%.x $(DIR_OBJ)/%.o -all : test_env $(DIRECTORY_BIN)/$(EXE).x.txt +vpath %.h $(DIR_INC) +vpath %.c $(DIR_C) +vpath %.s $(DIR_ASM):$(DIR_SYS) +vpath %.o $(DIR_OBJ) +vpath %.x $(DIR_BIN) -$(DIRECTORY_BIN)/%.x.txt : $(DIRECTORY_BIN)/%.x +all : @\ - $(ECHO) "List symbols : $*"; \ - $(OR32_NM) $(OR32_NM_OPT) $^ > $@.nm; \ - $(ECHO) "Display info : $*"; \ - $(OR32_OBJDUMP) $(OR32_OBJDUMP_OPT) $^ > $@; + $(MKDIR) $(DIR_BIN) $(DIR_OBJ); \ + $(MAKE) $(DIR_BIN)/$(EXE).x; -$(DIRECTORY_BIN)/%.x : $(OBJECTS) - @ \ - $(ECHO) "Linkage : $*"; \ - $(OR32_LD) -o $@ $^ $(OR32_LD_OPT); +$(DIR_BIN)/%.x : $(OBJECTS) + @\ + $(ECHO) "Linkage : $*.x"; \ + $(OR32_LD) -o $@ $^ $(OR32_LD_OPT); \ + $(ECHO) "List symbols : $*.x.nm"; \ + $(OR32_NM) $(OR32_NM_OPT) $^ > $@.nm; \ + $(ECHO) "Display info : $*.x.txt"; \ + $(OR32_OBJDUMP) $(OR32_OBJDUMP_OPT) $^ > $@.txt; -$(DIRECTORY_OBJ)/%.o : $(DIRECTORY_ASM)/%.s - @ \ - $(ECHO) "Compilation : $*"; \ - $(OR32_CC) $(OR32_CC_OPT) -o $@ -c $^ ; \ +$(DIR_OBJ)/%.o : %.s + @\ + $(ECHO) "Compilation : $*.s"; \ + $(OR32_CC) $(OR32_CC_OPT) -o $@ -c $^ ; \ $(OR32_CC) $(OR32_CC_OPT) -S -o $@.s -c $^ ; # @$(OR32_AS) $(OR32_AS_OPT) $^ -o $@ -$(DIRECTORY_OBJ)/%.o : $(DIRECTORY_SYS)/%.s - @ \ - $(ECHO) "Compilation : $*"; \ - $(OR32_CC) $(OR32_CC_OPT) -o $@ -c $^ ; \ +$(DIR_OBJ)/%.o : %.c + @\ + $(ECHO) "Compilation : $*.c"; \ + $(OR32_CC) $(OR32_CC_OPT) -o $@ -c $^ ; \ $(OR32_CC) $(OR32_CC_OPT) -S -o $@.s -c $^ ; -# @$(OR32_AS) $(OR32_AS_OPT) $^ -o $@ - -$(DIRECTORY_OBJ)/%.o : $(DIRECTORY_C)/%.c - @ \ - $(ECHO) "Compilation : $*"; \ - $(OR32_CC) $(OR32_CC_OPT) -o $@ -c $^ ; \ - $(OR32_CC) $(OR32_CC_OPT) -S -o $@.s -c $^ ; - -#-----[ Environement ]------------------------------------------------------------ -test_env : -# ifeq ($(origin TOOLS), undefined) -# $(error "variable TOOLS is undefined"); -# endif -# ifeq ($(origin SOFT), undefined) -# $(error "variable SOFT is undefined"); -# endif - @$(MKDIR) $(DIRECTORY_OBJ) $(DIRECTORY_BIN) #-----[ Maintenance ]------------------------------------------------------------- clean : @\ - $(ECHO) "Delete temporary files "`$(PWD)`; \ - $(RM) $(DIRECTORY_OBJ) $(DIRECTORY_BIN); \ - $(MAKE) clean_rec DIRECTORY_CLEAN=.; + $(ECHO) "Delete temporary files"; \ + $(RM) $(DIR_OBJ) $(DIR_BIN) \ + *~ \ + $(DIR_SRC)/*~ \ + $(DIR_C)/*~ \ + $(DIR_ASM)/*~ \ + $(DIR_SYS)/*~ \ + $(DIR_INC)/*~ \ + $(DIR_LDSCRIPT)/*~ \ -clean_rec : - @\ - $(ECHO) "Delete temporary files in directory $(DIRECTORY_CLEAN)"; \ - $(RM) -f $(DIRECTORY_CLEAN)/*~; \ - for files in `$(LS) $(DIRECTORY_CLEAN)`; do \ - if $(TEST) -d $(DIRECTORY_CLEAN)/$$files; \ - then \ - $(MAKE) clean_rec DIRECTORY_CLEAN=$(DIRECTORY_CLEAN)/$$files; \ - fi; \ - done; +clean_all : clean #-----[ Help ]-------------------------------------------------------------------- @@ -111,5 +106,6 @@ $(ECHO) "";\ $(ECHO) "List of directive : ";\ - $(ECHO) " * make : Compile the software";\ - $(ECHO) " * make clean : Erase all files generates";\ + $(ECHO) " * all : Compile the software";\ + $(ECHO) " * clean : Erase all files generates";\ + $(ECHO) " * clean_all : Erase all files generates";\ $(ECHO) ""; Index: trunk/Softwares/Min/Makefile =================================================================== --- trunk/Softwares/Min/Makefile (revision 88) +++ trunk/Softwares/Min/Makefile (revision 88) @@ -0,0 +1,26 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = ../Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include ../Makefile.Software + Index: trunk/Softwares/Min/src/asm/cpu_info.s =================================================================== --- trunk/Softwares/Min/src/asm/cpu_info.s (revision 88) +++ trunk/Softwares/Min/src/asm/cpu_info.s (revision 88) @@ -0,0 +1,18 @@ +/* + * Manipulation of processor information + */ + + .file "cpu_info.s" + .section .text + .align 4 + + .global _get_cpu_id +_get_cpu_id : + l.jr r9 + l.mfspr r11,r0,0xF800 /* R11 <- SPR[31][0] */ + + .global _set_cpu_id +_set_cpu_id : + l.jr r9 + l.mtspr r0 ,r3,0xF800 /* SPR[31][0] <- r3 */ + Index: trunk/Softwares/Min/src/asm/find_one.s =================================================================== --- trunk/Softwares/Min/src/asm/find_one.s (revision 88) +++ trunk/Softwares/Min/src/asm/find_one.s (revision 88) @@ -0,0 +1,19 @@ +/* + * Manipulation of bits + */ + + .file "find_one.s" + .section .text + .align 4 + + .global _find_first_one +_find_first_one : + l.jr r9 + l.ff1 r11,r3 + +/* + .global _find_last_one +_find_last_one : + l.jr r9 + l.fl1 r11,r3,r0 +*/ Index: trunk/Softwares/Min/src/asm/thread_info.s =================================================================== --- trunk/Softwares/Min/src/asm/thread_info.s (revision 88) +++ trunk/Softwares/Min/src/asm/thread_info.s (revision 88) @@ -0,0 +1,28 @@ +/* + * Manipulation of thread information + */ + + .file "thread_info.s" + .section .text + .align 4 + + .global _get_thread_id +_get_thread_id : + l.jr r9 + l.mfspr r11,r0,0xF801 /* R11 <- SPR[31][1] */ + + .global _set_thread_id +_set_thread_id : + l.jr r9 + l.mtspr r0 ,r3,0xF801 /* SPR[31][1] <- r3 */ + + .global _get_thread_priority +_get_thread_priority : + l.jr r9 + l.mfspr r11,r0,0xF802 /* R11 <- SPR[31][2] */ + + .global _set_thread_priority +_set_thread_priority : + l.jr r9 + l.mtspr r0 ,r3,0xF802 /* SPR[31][2] <- r3 */ + Index: trunk/Softwares/Min/src/c/include/cpu_info.h =================================================================== --- trunk/Softwares/Min/src/c/include/cpu_info.h (revision 88) +++ trunk/Softwares/Min/src/c/include/cpu_info.h (revision 88) @@ -0,0 +1,3 @@ + +extern unsigned int get_cpu_id(); +extern void set_cpu_id(unsigned int); Index: trunk/Softwares/Min/src/c/include/thread_info.h =================================================================== --- trunk/Softwares/Min/src/c/include/thread_info.h (revision 88) +++ trunk/Softwares/Min/src/c/include/thread_info.h (revision 88) @@ -0,0 +1,5 @@ + +extern unsigned int get_thread_id (); +extern void set_thread_id (unsigned int); +extern unsigned int get_thread_priority (); +extern void set_thread_priority (unsigned int); Index: trunk/Softwares/Min/src/c/main.c =================================================================== --- trunk/Softwares/Min/src/c/main.c (revision 88) +++ trunk/Softwares/Min/src/c/main.c (revision 88) @@ -0,0 +1,13 @@ +#include "thread_info.h" +#include "cpu_info.h" + +//=====[ main ]================================================================= +/* + * All thread execute this routine + * Initialize the thread and attribute a Workload at each thread + */ + +int main() +{ + while (1); +} Index: trunk/Softwares/Min/src/sys/crt0.s =================================================================== --- trunk/Softwares/Min/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Min/src/sys/crt0.s (revision 88) @@ -0,0 +1,580 @@ +/* + * Routine system dependant + * - reset + * - exception handler + * - start / exit + */ + +/* +#define DEFAULT_EXCEPTION_HANDLER \ + l.addi r1, r1, -128 ;\ + l.sw 4(r1), r3 ;\ + l.sw 8(r1), r4 ;\ + l.mfspr r3,r0,16 ;\ + l.mfspr r4,r0,32 ;\ + l.j default_exception_handler;\ + l.nop 0 ; +*/ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 + + l.movhi r3, 0xdead + l.jal _quit + l.ori r3,r3,0xdead + + /* + l.nop -0 + l.nop -1 + l.nop -2 + l.nop -3 + l.nop -4 + l.nop -5 + l.nop -6 + l.nop -7 + l.nop -8 + l.nop -9 + l.nop -10 + l.nop -11 + l.nop -12 + l.nop -13 + l.nop -14 + l.nop -15 + l.nop -16 + l.nop -17 + l.nop -18 + l.nop -19 + l.nop -20 + l.nop -21 + l.nop -22 + l.nop -23 + l.nop -24 + l.nop -25 + l.nop -26 + l.nop -27 + l.nop -28 + l.nop -29 + l.nop -30 + l.nop -31 + l.nop -32 + l.nop -33 + l.nop -34 + l.nop -35 + l.nop -36 + l.nop -37 + l.nop -38 + l.nop -39 + l.nop -40 + l.nop -41 + l.nop -42 + l.nop -43 + l.nop -44 + l.nop -45 + l.nop -46 + l.nop -47 + l.nop -48 + l.nop -49 + l.nop -50 + l.nop -51 + l.nop -52 + l.nop -53 + l.nop -54 + l.nop -55 + l.nop -56 + l.nop -57 + l.nop -58 + l.nop -59 + l.nop -60 + l.nop -61 + l.nop -62 + l.nop -63 + */ + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _exception_reset +_exception_reset: + + l.movhi r2, hi(_start) + l.ori r2,r2,lo(_start) + l.jr r2 /* Go _start */ + l.nop 0 + +/* ---[ 0x200: BUS exception ]------------------------------------------- */ + .org 0x200 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x300: Data Page Fault exception ]------------------------------- */ + .org 0x300 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ + .org 0x400 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x500: Timer exception ]----------------------------------------- */ + .org 0x500 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x600: Aligment exception ]-------------------------------------- */ + .org 0x600 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x700: Illegal insn exception ]---------------------------------- */ + .org 0x700 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x800: External interrupt exception ]---------------------------- */ + .org 0x800 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0x900: DTLB miss exception ]------------------------------------- */ + .org 0x900 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ + .org 0xa00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + +/* ---[ 0xb00: Range exception ]----------------------------------------- */ + .org 0xb00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + +/* ---[ 0xc00: Syscall exception ]--------------------------------------- */ + .org 0xc00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + +/* ---[ 0xd00: Trap exception ]------------------------------------------ */ + .org 0xd00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + +/* ---[ 0xe00: Trap exception ]------------------------------------------ */ + .org 0xe00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + +/* ---[ 0xf00: Reserved exceptions ]------------------------------------- */ + .org 0xf00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1000 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1100 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1200 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1300 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1400 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1500 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1600 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1700 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1800 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1900 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1a00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1b00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1c00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1d00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1e00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + + .org 0x1f00 + /*DEFAULT_EXCEPTION_HANDLER*/ + l.addi r1, r1, -128 + l.sw 4(r1), r3 + l.sw 8(r1), r4 + l.mfspr r3,r0,16 + l.mfspr r4,r0,32 + l.j default_exception_handler + l.nop 0 + + +/* ========================================================= [ entry ] === */ + + .org 0x2000 + .global _start + +_start: + /* Initialise stack */ + + l.movhi r1, hi(_stack) + l.ori r1, r1, lo(_stack) + l.addi r2, r0, -3 /* 0xFFFF_FFFC */ + + l.jal _get_cpu_id /* give the id of the cpu */ + l.and r1, r1, r2 + + l.movhi r4, hi(_stack_alloc) + l.ori r4, r4, lo(_stack_alloc) + + l.mul r4, r11,r4 + l.sub r1, r1 ,r4 /* each thread have a <<_stack>> with a size <<_stack_alloc>> */ + l.or r2, r1, r0 /* copy in frame_pointer register */ + + /* Clear BSS */ +/* + l.movhi r28, hi(___bss_start) + l.ori r28, r28, lo(___bss_start) + l.movhi r30, hi(__end) + l.ori r30, r30, lo(__end) +1: + l.sw (0)(r28), r0 + l.sfltu r28, r30 + l.bf 1b + l.addi r28, r28, 4 +*/ + /* Jump to main program entry point (argc = argv = 0) */ + l.and r3,r0,r0 + l.jal _main + l.and r4,r0,r0 + + /* If program exits, call exit routine */ +/* + l.addi r3, r11, 0 + l.jal __exit + l.nop 0 +*/ +/* ====================================== [ default exception handler ] === */ + +default_exception_handler: + l.sw 0x00(r1), r2 + l.sw 0x0c(r1), r5 + l.sw 0x10(r1), r6 + l.sw 0x14(r1), r7 + l.sw 0x18(r1), r8 + l.sw 0x1c(r1), r9 + l.sw 0x20(r1), r10 + l.sw 0x24(r1), r11 + l.sw 0x28(r1), r12 + l.sw 0x2c(r1), r13 + l.sw 0x30(r1), r14 + l.sw 0x34(r1), r15 + l.sw 0x38(r1), r16 + l.sw 0x3c(r1), r17 + l.sw 0x40(r1), r18 + l.sw 0x44(r1), r19 + l.sw 0x48(r1), r20 + l.sw 0x4c(r1), r21 + l.sw 0x50(r1), r22 + l.sw 0x54(r1), r23 + l.sw 0x58(r1), r24 + l.sw 0x5c(r1), r25 + l.sw 0x60(r1), r26 + l.sw 0x64(r1), r27 + l.sw 0x68(r1), r28 + l.sw 0x6c(r1), r29 + l.sw 0x70(r1), r30 + l.sw 0x74(r1), r31 + l.sw 0x78(r1), r32 + + /* + * Jump to a handler (write in C by example) + */ + + l.jal _exception_handler + l.nop 0 + + l.lwz r2 , 0x00(r1) + l.lwz r3 , 0x04(r1) + l.lwz r4 , 0x08(r1) + l.lwz r5 , 0x0c(r1) + l.lwz r6 , 0x10(r1) + l.lwz r7 , 0x14(r1) + l.lwz r8 , 0x18(r1) + l.lwz r9 , 0x1c(r1) + l.lwz r10, 0x20(r1) + l.lwz r11, 0x24(r1) + l.lwz r12, 0x28(r1) + l.lwz r13, 0x2c(r1) + l.lwz r14, 0x30(r1) + l.lwz r15, 0x34(r1) + l.lwz r16, 0x38(r1) + l.lwz r17, 0x3c(r1) + l.lwz r18, 0x40(r1) + l.lwz r19, 0x44(r1) + l.lwz r20, 0x48(r1) + l.lwz r21, 0x4c(r1) + l.lwz r22, 0x50(r1) + l.lwz r23, 0x54(r1) + l.lwz r24, 0x58(r1) + l.lwz r25, 0x5c(r1) + l.lwz r26, 0x60(r1) + l.lwz r27, 0x64(r1) + l.lwz r28, 0x68(r1) + l.lwz r29, 0x6c(r1) + l.lwz r30, 0x70(r1) + l.lwz r31, 0x74(r1) + l.lwz r32, 0x78(r1) + + l.addi r1, r1, 128 + + l.rfe + l.nop 0 Index: trunk/Softwares/Test/Test_000/Makefile =================================================================== --- trunk/Softwares/Test/Test_000/Makefile (revision 88) +++ trunk/Softwares/Test/Test_000/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_000/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_000/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_000/src/sys/crt0.s (revision 88) @@ -0,0 +1,66 @@ +/* + * Test_000 : minimal test + * + * Take in R1 the stop address and stop an data + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_infinite_loop : + l.j _infinite_loop + l.nop + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.j _infinite_loop + l.nop + Index: trunk/Softwares/Test/Test_001/Makefile =================================================================== --- trunk/Softwares/Test/Test_001/Makefile (revision 88) +++ trunk/Softwares/Test/Test_001/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_001/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_001/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_001/src/sys/crt0.s (revision 88) @@ -0,0 +1,70 @@ +/* + * Test_000 : minimal test + * + * Take in R1 the stop address and stop an data + * The store in the destination of an jump + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop +_infinite_loop : + l.j _infinite_loop + l.nop + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.j _end_ok + l.nop + Index: trunk/Softwares/Test/Test_002/Makefile =================================================================== --- trunk/Softwares/Test/Test_002/Makefile (revision 88) +++ trunk/Softwares/Test/Test_002/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_002/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_002/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_002/src/sys/crt0.s (revision 88) @@ -0,0 +1,46 @@ +/* + * Test_002 + * + * end_ko : infinite_loop + * end_ok : Write in R1 the stop address and stop an data + * The store in the destination of an jump + * start : write in r1 and r2 the same value and compare this both register + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ko : +_infinite_loop : + l.j _infinite_loop + l.nop + +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.movhi r1, hi(0x12345678) + l.ori r1, r1, lo(0x12345678) + l.movhi r2, hi(0x12345678) + l.ori r2, r2, lo(0x12345678) + l.sfeq r1, r2 + l.bf _end_ok + l.nop + l.j _end_ko + l.nop + Index: trunk/Softwares/Test/Test_003/Makefile =================================================================== --- trunk/Softwares/Test/Test_003/Makefile (revision 88) +++ trunk/Softwares/Test/Test_003/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_003/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_003/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_003/src/sys/crt0.s (revision 88) @@ -0,0 +1,44 @@ +/* + * Test_003 + * + * end_ko : infinite_loop + * end_ok : Write in R1 the stop address and stop an data + * The store in the destination of an jump + * start : place an value on 16 bits in a register. Test register with an immediat (no sign extension) + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ko : +_infinite_loop : + l.j _infinite_loop + l.nop + +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.movhi r1, hi(0x00001981) + l.ori r1, r1, lo(0x00001981) + l.sfeqi r1, 0x1981 + l.bf _end_ok + l.nop + l.j _end_ko + l.nop + Index: trunk/Softwares/Test/Test_004/Makefile =================================================================== --- trunk/Softwares/Test/Test_004/Makefile (revision 88) +++ trunk/Softwares/Test/Test_004/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_004/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_004/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_004/src/sys/crt0.s (revision 88) @@ -0,0 +1,45 @@ +/* + * Test_004 + * + * end_ko : infinite_loop + * end_ok : Write in R1 the stop address and stop an data + * The store in the destination of an jump + * start : place an value on 16 bits in a register. Test register with an immediat (no sign extension) + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ko : +_infinite_loop : + l.j _infinite_loop + l.nop + + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.movhi r1, hi(0x00001981) + l.ori r1, r1, lo(0x00001981) + l.sfeqi r1, 0x1981 + l.bf _end_ok + l.nop + l.j _end_ko + l.nop + + .org 0x180 +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + Index: trunk/Softwares/Test/Test_005/Makefile =================================================================== --- trunk/Softwares/Test/Test_005/Makefile (revision 88) +++ trunk/Softwares/Test/Test_005/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_005/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_005/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_005/src/sys/crt0.s (revision 88) @@ -0,0 +1,44 @@ +/* + * Test_005 + * + * end_ko : infinite_loop + * end_ok : Write in R1 the stop address and stop an data + * The store in the destination of an jump + * start : place an value on 16 bits in a register. Test register with an immediat (sign extension) + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ko : +_infinite_loop : + l.j _infinite_loop + l.nop + +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.movhi r1, hi(0xffffdead) + l.ori r1, r1, lo(0xffffdead) + l.sfeqi r1, 0xdead + l.bf _end_ok + l.nop + l.j _end_ko + l.nop + Index: trunk/Softwares/Test/Test_006/Makefile =================================================================== --- trunk/Softwares/Test/Test_006/Makefile (revision 88) +++ trunk/Softwares/Test/Test_006/Makefile (revision 88) @@ -0,0 +1,27 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +# common definition +DIR_SOFT = ../.. +DIR_SRC = ./src +DIR_C = $(DIR_SRC)/c +DIR_ASM = $(DIR_SRC)/asm +DIR_SYS = $(DIR_SRC)/sys +DIR_INC = $(DIR_C)/include +DIR_LDSCRIPT = $(DIR_SOFT)/Global/ldscript/ + +INCLUDE = -I$(DIR_INC) +LIBRARY = + +#-----[ Files ]------------------------------------------------------------------- +OBJECTS = $(patsubst $(DIR_ASM)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_ASM)/*.s)) \ + $(patsubst $(DIR_SYS)/%.s,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SYS)/*.s)) \ + $(patsubst $(DIR_C)/%.c,$(DIR_OBJ)/%.o,$(wildcard $(DIR_C)/*.c)) + +include $(DIR_SOFT)/Makefile.Software + Index: trunk/Softwares/Test/Test_006/src/sys/crt0.s =================================================================== --- trunk/Softwares/Test/Test_006/src/sys/crt0.s (revision 88) +++ trunk/Softwares/Test/Test_006/src/sys/crt0.s (revision 88) @@ -0,0 +1,44 @@ +/* + * Test_005 + * + * end_ko : infinite_loop + * end_ok : Write in R1 the stop address and stop an data + * The store in the destination of an jump + * start : place an value on 16 bits in a register. Test register with an immediat (sign extension) + */ + + .file "crt0.s" + /* + .section .vector + */ + .section .text + .align 4 + +/* ---[ 0x0 : Print a error ]------------------------------------------- */ + + .org 0x0 +_end_ko : +_infinite_loop : + l.j _infinite_loop + l.nop + +_end_ok : + l.movhi r1, hi(_tty) + l.ori r1, r1, lo(_tty) + l.sw 4(r1), r1 /* stop address */ + + +/* ---[ 0x100: RESET exception ]----------------------------------------- */ + .org 0x100 + .global _start +_start: + l.nop + l.nop + l.movhi r1, hi(0x0000dead) + l.ori r1, r1, lo(0x0000dead) + l.sfeqi r1, 0xdead + l.bf _end_ko + l.nop + l.j _end_ok + l.nop + Index: trunk/environment.sh =================================================================== --- trunk/environment.sh (revision 87) +++ trunk/environment.sh (revision 88) @@ -26,31 +26,28 @@ # Export environement export MORPHEO_TOPLEVEL=${PWD} -#export MORPHEO_PLATFORMS=${MORPHEO_TOPLEVEL}/Platforms -#export MORPHEO_SOFTWARE=${MORPHEO_TOPLEVEL}/Softwares -#export MORPHEO_IPS=${MORPHEO_TOPLEVEL}/IPs/systemC export MORPHEO_SCRIPT=${MORPHEO_TOPLEVEL}/IPs/systemC/processor/Morpheo/Script -export MORPHEO_HOME=${HOME}/.morpheo +export MORPHEO_HOME=${HOME}/.Morpheo +export MORPHEO_TMP=/tmp/Morpheo + MORPHEO_XTTY=${MORPHEO_TOPLEVEL}/IPs/systemC/Environment/TTY/xtty echo "" -echo "OS found : $OS_FOUND" +echo "OS found : ${OS_FOUND}" echo "" -echo "Modification of environement's variable : " -echo " - MORPHEO_TOPLEVEL is set to ${MORPHEO_TOPLEVEL} " -#echo " - MORPHEO_PLATFORMS is set to ${MORPHEO_PLATFORMS}" -#echo " - MORPHEO_SOFTWARE is set to ${MORPHEO_SOFTWARE} " -#echo " - MORPHEO_IPS is set to ${MORPHEO_IPS} " -echo " - MORPHEO_SCRIPT is set to ${MORPHEO_SCRIPT} " -echo " - MORPHEO_HOME is set to ${MORPHEO_HOME} " +echo "Modification of environement's variable :" +echo " - MORPHEO_TOPLEVEL is set to ${MORPHEO_TOPLEVEL}" +echo " - MORPHEO_SCRIPT is set to ${MORPHEO_SCRIPT}" +echo " - MORPHEO_HOME is set to ${MORPHEO_HOME}" +echo " - MORPHEO_TMP is set to ${MORPHEO_TMP}" +#---------- +# Path : add xtty and script directory. +# test if already in path : no multiple addition +#---------- -# PATH : No multiple add echo ${PATH} |grep -q ${MORPHEO_SCRIPT}; - if test $? -eq 1; then export PATH=${PATH}:${MORPHEO_SCRIPT} - echo " - PATH add ${MORPHEO_SCRIPT} " + echo " - PATH add ${MORPHEO_SCRIPT}" fi; - -MORPHEO_XTTY=${MORPHEO_TOPLEVEL}/IPs/systemC/Environment/TTY/xtty echo ${PATH} |grep -q ${MORPHEO_XTTY}; @@ -58,12 +55,5 @@ if test $? -eq 1; then export PATH=${PATH}:${MORPHEO_XTTY} - echo " - PATH add ${MORPHEO_XTTY} " -fi; - - -# test if "first run" -if test ! -d ${MORPHEO_HOME}; then - echo " - MORPHEO_HOME don't exist : first run " - . ${MORPHEO_SCRIPT}/first_run.sh + echo " - PATH add ${MORPHEO_XTTY}" fi;