Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 90) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 91) @@ -10,5 +10,5 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "90" +#define MORPHEO_REVISION "91" #define MORPHEO_CODENAME "Castor" Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile (revision 91) @@ -0,0 +1,31 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = . +DIR_ALL_DOCUMENTS = doc + +#-----[ include ]------------------------------------------ + +all : + @\ + for doc in $(DIR_ALL_DOCUMENTS)/*; do \ + $(MAKE) --directory=$${doc} --makefile=Makefile; \ + done; + +view : view_global + +local_clean : + @\ + $(RM) $(DIR_TOPLEVEL_PDF); \ + for doc in $(DIR_ALL_DOCUMENTS)/*; do \ + $(MAKE) --directory=$${doc} --makefile=Makefile clean; \ + done; + + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile.Documentation =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile.Documentation (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/Makefile.Documentation (revision 91) @@ -0,0 +1,321 @@ +ifeq ($(origin MORPHEO_TOPLEVEL), undefined) + $(error "variable MORPHEO_TOPLEVEL is undefined"); +else + include $(MORPHEO_TOPLEVEL)/Makefile.tools +endif + +#-------------------------------------------------------------------------------- +#-----[ Variable ]--------------------------------------------------------------- +#-------------------------------------------------------------------------------- + +ENV_LATEX = export TEXINPUTS=$(DIR_INCLUDE):$$TEXINPUTS +LATEX_WITH_ENV = $(ENV_LATEX); $(LATEX) + +#-------------------------------------------------------------------------------- +#-----[ Directory ]-------------------------------------------------------------- +#-------------------------------------------------------------------------------- + +# DIR_DOCUMENTATION must be set previously + +DIR_TOPLEVEL = $(DIR_DOCUMENTATION) +DIR_TOPLEVEL_SCHEMA = $(DIR_TOPLEVEL)/fig +DIR_TOPLEVEL_GRAPH = $(DIR_TOPLEVEL)/dot +DIR_TOPLEVEL_PDF = $(DIR_TOPLEVEL)/pdf +DIR_DOC = . +DIR_TEX = ./tex +DIR_SCHEMA = ./fig +DIR_GRAPH = ./dot +DIR_SCHEMA_EPS = ./eps + +#-------------------------------------------------------------------------------- +#-----[ Files ]------------------------------------------------------------------ +#-------------------------------------------------------------------------------- + +TEX_FILES = $(wildcard $(DIR_DOC)/*.tex) +DVI_FILES = $(patsubst $(DIR_DOC)/%.tex,%.dvi,$(TEX_FILES)) +PS_FILES = $(patsubst $(DIR_DOC)/%.tex,%.ps ,$(TEX_FILES)) +PDF_FILES = $(patsubst $(DIR_DOC)/%.tex,%.pdf,$(TEX_FILES)) +EPS_FILES = $(patsubst $(DIR_GRAPH)/%.dot,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_GRAPH)/*.dot)) \ + $(patsubst $(DIR_SCHEMA)/%.fig,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.fig)) \ + $(patsubst $(DIR_SCHEMA)/%.eps,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_SCHEMA)/*.eps)) \ + $(patsubst $(DIR_TOPLEVEL_GRAPH)/%.dot,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_TOPLEVEL_GRAPH)/*.dot)) \ + $(patsubst $(DIR_TOPLEVEL_SCHEMA)/%.fig,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_TOPLEVEL_SCHEMA)/*.fig)) \ + $(patsubst $(DIR_TOPLEVEL_SCHEMA)/%.eps,$(DIR_SCHEMA_EPS)/%.eps,$(wildcard $(DIR_TOPLEVEL_SCHEMA)/*.eps)) + +#-------------------------------------------------------------------------------- +#-----[ Rules ]------------------------------------------------------------------ +#-------------------------------------------------------------------------------- + +#-------------------------------------------------------------------------------- +# The reset of this file shall not be editted +#-------------------------------------------------------------------------------- + +vpath %.tex $(DIR_TEX) +vpath %.dot $(DIR_GRAPH):$(DIR_TOPLEVEL_GRAPH) +vpath %.fig $(DIR_SCHEMA):$(DIR_TOPLEVEL_SCHEMA) +vpath %.eps $(DIR_SCHEMA):$(DIR_TOPLEVEL_SCHEMA) + + +.PHONY : all view view_global view_local clean help +.SECONDARY : $(DVI_FILES) $(PS_FILES) $(PDF_FILES) $(EPS_FILES) $(DIR_SCHEMA_EPS) + +all_documentation : $(EPS_FILES) + @\ + $(MAKE) $(PDF_FILES) + +#-------------------------------------------------------------------------------- +# Generation of the formatted text: +# regular flow tex -> dvi -> ps -> pdf. +#-------------------------------------------------------------------------------- + +%.pdf : %.ps $(DIR_TOPLEVEL_PDF) + @\ + $(ECHO) "Generate files : $*.pdf"; \ + $(PS2PDF) $< $@; \ + $(CP) $@ $(DIR_TOPLEVEL_PDF); + +%.ps : %.dvi + @\ + $(ECHO) "Generate files : $*.ps"; \ + $(DVIPS) -o $@ $<; + +%.dvi : %.tex $(DIR_TEX)/* + @\ + $(ECHO) "Generate files : $*.dvi"; \ + $(LATEX_WITH_ENV) $<; \ + if $(TEST) $$? -eq 0; then \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + citation=`$(GREP) "citation" $*.aux`; \ + if $(TEST) -n "$$citation" ; then \ + $(BIBTEX) $* ; \ + fi; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + $(LATEX_WITH_ENV) $< > /dev/null; \ + fi; + +#-------------------------------------------------------------------------------- +# The figures directory +#-------------------------------------------------------------------------------- +$(DIR_SCHEMA_EPS) : + @\ + $(ECHO) "Make directory : $@"; \ + $(MKDIR) $@; + +$(DIR_TOPLEVEL_PDF) : + @\ + $(ECHO) "Make directory : $@"; \ + $(MKDIR) $@; + +$(DIR_SCHEMA_EPS)/%.eps : %.eps $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(CP) $< $(DIR_SCHEMA_EPS); + +$(DIR_SCHEMA_EPS)/%.eps : %.fig $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(FIG2EPS) $< $@; + +$(DIR_SCHEMA_EPS)/%.eps : %.dot $(DIR_SCHEMA_EPS) + @\ + $(ECHO) "Generate files : $*.eps"; \ + $(DOT) -Tfig -o $(DIR_SCHEMA_EPS)/${*}.fig $<; \ + $(FIG2EPS) $(DIR_SCHEMA_EPS)/${*}.fig $@; \ + $(RM) $(DIR_SCHEMA_EPS)/${*}.fig; + +#-------------------------------------------------------------------------------- +# View +#-------------------------------------------------------------------------------- +view_local : all + @\ + declare SELECT_FILE; \ + declare SELECT_FORMAT; \ + declare SELECT_VIEWER; \ + \ + \ + $(ECHO) ""; \ + $(ECHO) "Choose a document : (0 by default)"; \ + \ + declare -i CPT; \ + declare -i NUM_FILE; \ + declare -a FILES; \ + \ + CPT=0; \ + for files in $(PDF_FILES); do \ + files=`$(BASENAME) $$files .pdf`; \ + $(ECHO) "$$CPT) $$files"; \ + FILES[$$CPT]=$$files; \ + CPT=$$(($$CPT+1)); \ + done; \ + \ + if $(TEST) "$$CPT" -eq "0"; then \ + $(ECHO) "None document found"; \ + exit; \ + fi; \ + \ + read NUM_FILE; \ + \ + if $(TEST) "$$NUM_FILE" -ge "$$CPT"; then \ + NUM_FILE=0; \ + fi; \ + \ + SELECT_FILE=$${FILES[$$NUM_FILE]}; \ + \ + \ + $(ECHO) "Document selected : $$SELECT_FILE"; \ + $(ECHO) ""; \ + $(ECHO) "Choose a format : (0 by default)"; \ + \ + declare -i NUM_FORMAT; \ + declare -a FORMAT; \ + declare -a VIEWER; \ + \ + PRINT=( "pdf (fullscreen)" "pdf" "ps" "dvi"); \ + FORMAT=("pdf" "pdf" "ps" "dvi"); \ + VIEWER=("$(VIEWPDF_FS)" "$(VIEWPDF)" "$(VIEWPS)" "$(VIEWDVI)"); \ + \ + CPT=0; \ + while [ $$CPT -lt $${#FORMAT[*]} ]; do \ + $(ECHO) "$$CPT) $${PRINT[$$CPT]}"; \ + CPT=$$(($$CPT+1)); \ + done; \ + read NUM_FORMAT; \ + \ + if $(TEST) "$$NUM_FORMAT" -ge "$$CPT"; then \ + NUM_FORMAT=0; \ + fi; \ + \ + SELECT_FORMAT=$${FORMAT[$$NUM_FORMAT]}; \ + SELECT_VIEWER=$${VIEWER[$$NUM_FORMAT]}; \ + $(ECHO) "Format selected : $$SELECT_FORMAT"; \ + $(ECHO) ""; \ + \ + $$SELECT_VIEWER "$$SELECT_FILE.$$SELECT_FORMAT" & \ + \ + $(ECHO) ""; + +view_global : all + @\ + declare SELECT_FILE; \ + declare SELECT_FORMAT; \ + declare SELECT_VIEWER; \ + \ + \ + $(ECHO) ""; \ + $(ECHO) "Choose a document : (0 by default)"; \ + \ + declare -i CPT; \ + declare -i NUM_FILE; \ + declare -a FILES; \ + \ + CPT=0; \ + for files in $(wildcard $(DIR_TOPLEVEL_PDF)/*.pdf); do \ + files=`$(BASENAME) $$files .pdf`; \ + $(ECHO) "$$CPT) $$files"; \ + FILES[$$CPT]=$(DIR_TOPLEVEL_PDF)/$$files; \ + CPT=$$(($$CPT+1)); \ + done; \ + \ + if $(TEST) "$$CPT" -eq "0"; then \ + $(ECHO) "None document found"; \ + exit; \ + fi; \ + \ + read NUM_FILE; \ + \ + if $(TEST) "$$NUM_FILE" -ge "$$CPT"; then \ + NUM_FILE=0; \ + fi; \ + \ + SELECT_FILE=$${FILES[$$NUM_FILE]}; \ + \ + \ + $(ECHO) "Document selected : $$SELECT_FILE"; \ + $(ECHO) ""; \ + $(ECHO) "Choose a format : (0 by default)"; \ + \ + declare -i NUM_FORMAT; \ + declare -a FORMAT; \ + declare -a VIEWER; \ + \ + PRINT=( "pdf (fullscreen)" "pdf" ); \ + FORMAT=("pdf" "pdf" ); \ + VIEWER=("$(VIEWPDF_FS)" "$(VIEWPDF)"); \ + \ + CPT=0; \ + while [ $$CPT -lt $${#FORMAT[*]} ]; do \ + $(ECHO) "$$CPT) $${PRINT[$$CPT]}"; \ + CPT=$$(($$CPT+1)); \ + done; \ + read NUM_FORMAT; \ + \ + if $(TEST) "$$NUM_FORMAT" -ge "$$CPT"; then \ + NUM_FORMAT=0; \ + fi; \ + \ + SELECT_FORMAT=$${FORMAT[$$NUM_FORMAT]}; \ + SELECT_VIEWER=$${VIEWER[$$NUM_FORMAT]}; \ + $(ECHO) "Format selected : $$SELECT_FORMAT"; \ + $(ECHO) ""; \ + \ + $$SELECT_VIEWER "$$SELECT_FILE.$$SELECT_FORMAT" & \ + \ + $(ECHO) ""; + + +#-------------------------------------------------------------------------------- +# Cleaning +#-------------------------------------------------------------------------------- + +clean : local_clean + @\ + $(ECHO) "Delete temporary files "$(PWD); \ + $(RM) $(DIR_SCHEMA_EPS); \ + $(RM) $(DVI_FILES) $(PS_FILES) $(PDF_FILES); \ + $(MAKE) clean_rec DIR_CLEAN=.; + +clean_all : clean + +#Clean recursive +clean_rec : + @\ + $(ECHO) "Delete temporary files in directory $(DIR_CLEAN)"; \ + $(RM) $(DIR_CLEAN)/*~ \ + $(DIR_CLEAN)/*.bak \ + $(DIR_CLEAN)/*.aux \ + $(DIR_CLEAN)/*.bbl \ + $(DIR_CLEAN)/*.blg \ + $(DIR_CLEAN)/*.bmt \ + $(DIR_CLEAN)/*.log \ + $(DIR_CLEAN)/*.mtc* \ + $(DIR_CLEAN)/*.toc \ + $(DIR_CLEAN)/*.idx \ + $(DIR_CLEAN)/*.ilg \ + $(DIR_CLEAN)/*.ind \ + $(DIR_CLEAN)/*.out \ + $(DIR_CLEAN)/*.nav \ + $(DIR_CLEAN)/*.maf \ + $(DIR_CLEAN)/*.snm \ + $(DIR_CLEAN)/missfont.log; \ + for files in `$(LS) $(DIR_CLEAN)`; do \ + if $(TEST) -d $(DIR_CLEAN)/$$files; \ + then \ + $(MAKE) clean_rec DIR_CLEAN=$(DIR_CLEAN)/$$files; \ + fi; \ + done; + +#-------------------------------------------------------------------------------- +# Help +#-------------------------------------------------------------------------------- + +help : + @\ + $(ECHO) " -----[ Documentation ]------------------------------";\ + $(ECHO) ""; \ + $(ECHO) " * all_documentation : Generate all documents"; \ + $(ECHO) " * clean : Erase all generated files"; \ + $(ECHO) " * clean_all : cf clean"; \ + $(ECHO) " * help : Print this message"; \ + $(ECHO) " * view : View local documents"; \ + $(ECHO) " * view_view : View all documents"; \ + $(ECHO) ""; Index: trunk/IPs/systemC/processor/Morpheo/Documentation/common/bibliography.bib =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/common/bibliography.bib (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/common/bibliography.bib (revision 91) @@ -0,0 +1,1046 @@ +@conference{1981_smith, + title={{A study of branch prediction strategies}}, + author={Smith, J.E.}, + booktitle={Proc. Computer Architecture}, + pages={135-148}, + year={1981}, + organization={IEEE} +} +@conference{1983_fisher, + title={{Very Long Instruction Word architectures and the ELI-512}}, + author={Fisher, J.A.}, + booktitle={Proceedings of the 10th annual international symposium on Computer architecture}, + pages={140--150}, + year={1983}, + organization={IEEE Computer Society Press Los Alamitos, CA, USA} +} +@book{1983_Lee, + title={{Analysis of Branch Prediction Strategies and Branch Target Buffer Design}}, + author={Lee, J.K.F. and Smith, A.J.}, + year={1983}, + publisher={Computer Science Division (EECS), University of California} +} +@article{lee1984bps, + title={{Branch Prediction Strategies and Branch Target Buffer Design}}, + author={Lee, JKF and Smith, AJ}, + journal={Computer}, + volume={17}, + number={1}, + pages={6--22}, + year={1984} +} +@article{smith1984dae, + title={{Decoupled Access/Execute Computer Architectures}}, + author={SMITH, J.E.}, + journal={ACM Transactions on Computer Systems}, + volume={2}, + number={4}, + pages={289--308}, + year={1984} +} +@conference{ditzel1987bfc, + title={{Branch folding in the CRISP microprocessor: reducing branch delay to zero}}, + author={Ditzel, DR and McLellan, HR}, + booktitle={Proceedings of the 14th annual international symposium on Computer architecture}, + pages={2--8}, + year={1987}, + organization={ACM New York, NY, USA} +} +@article{1990_alverson, + title={{The Tera Computer System}}, + author={Alverson, R. and Callahan, D. and Cummings, D. and Porterfield, A. and Smith, B. and Koblenz, B.} +} +@article{1991_kaeli, + title={{Branch history table prediction of moving target branches due to subroutine returns}}, + author={Kaeli, D.R. and Emma, P.G.}, + journal={Proceedings of the 18th annual international symposium on Computer architecture}, + pages={34--42}, + year={1991}, + publisher={ACM Press New York, NY, USA} +} +@article{scherson1991ogc, + title={{Orthogonal graphs for the construction of a class ofinterconnection networks}}, + author={Scherson, ID}, + journal={Parallel and Distributed Systems, IEEE Transactions on}, + volume={2}, + number={1}, + pages={3--19}, + year={1991} +} +@article{1991_wall, + title={{Limits of instruction-level parallelism}}, + author={David W. Wall}, + journal={Proceedings of the fourth international conference on Architectural support for programming languages and operating systems}, + pages={176--188}, + year={1991} +} +@article{1992_pan, + title={{Improving the accuracy of dynamic branch prediction using branch correlation}}, + author={Pan, S.T. and So, K. and Rahmeh, J.T.}, + journal={Proceedings of the fifth international conference on Architectural support for programming languages and operating systems}, + pages={76--84}, + year={1992}, + publisher={ACM Press New York, NY, USA} +} +@article{1992_yeh, + title={{Alternative Implementations of Two-Level Adaptive Branch Prediction}}, + author={Yeh, T.Y. and Patt, YN}, + journal={Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on}, + pages={124--134}, + year={1992} +} +@techreport{1993_mcfarling, + title={{Combining Branch Predictors}}, + author={McFarling, S.}, + institution={Technical Report WRL Technical Note TN-36, Digital Equipment Corporation, June 1993} +} +@article{mclellan1993aaa, + title={{The Alpha AXP architecture and 21064 processor}}, + author={McLellan, E.}, + journal={IEEE Micro}, + volume={13}, + number={3}, + pages={36--47}, + year={1993} +} +@conference{moudgill1993rra, + title={{Register renaming and dynamic speculation: an alternative approach}}, + author={Moudgill, M. and Pingali, K. and Vassiliadis, S.}, + booktitle={Proceedings of the 26th annual international symposium on Microarchitecture}, + pages={202--213}, + year={1993}, + organization={IEEE Computer Society Press Los Alamitos, CA, USA} +} +@article{1993_Perleberg, + title={{Branch target buffer design and optimization}}, + author={Perleberg, CH and Smith, AJ}, + journal={Computers, IEEE Transactions on}, + volume={42}, + number={4}, + pages={396--412}, + year={1993} +} +@article{1993_yeh, + title={{A comparison of dynamic branch predictors that use two levels of branch history}}, + author={Yeh, T.Y. and Patt, Y.N.}, + journal={Proceedings of the 20th annual international symposium on Computer architecture}, + pages={257--266}, + year={1993}, + publisher={ACM Press New York, NY, USA} +} +@article{gallagher1994dmd, + title={{Dynamic memory disambiguation using the memory conflict buffer}}, + author={Gallagher, D.M. and Chen, W.Y. and Mahlke, S.A. and Gyllenhaal, J.C. and Wen-mei, W.H.}, + journal={Proceedings of the sixth international conference on Architectural support for programming languages and operating systems}, + pages={183--193}, + year={1994}, + publisher={ACM Press New York, NY, USA} +} +@article{song1994prm, + title={{The PowerPC 604 RISC microprocessor.}}, + author={Song, SP and Denman, M. and Chang, J.}, + journal={Micro, IEEE}, + volume={14}, + number={5}, + year={1994} +} +@article{diep1995pep, + title={{Performance evaluation of the PowerPC 620 microarchitecture}}, + author={Diep, T.A. and Nelson, C. and Shen, J.P.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={23}, + number={2}, + pages={163--174}, + year={1995}, + publisher={ACM New York, NY, USA} +} +@article{1995_edmondson, + title={{Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor}}, + author={Edmondson, J.H. and Rubinfeld, P.I. and Bannon, P.J. and Benschneider, B.J. and Bernstein, D. and Castelino, R.W. and Cooper, E.M. and Dever, D.E. and Donchin, D.R. and Fischer, T.C. and others}, + journal={Digital Technical Journal}, + volume={7}, + number={1}, + pages={0}, + year={1995} +} +@InProceedings{1995_sohi, + author = {Sohi, G.S. and + Breach, S.E. and + Vijaykumar, T.N. }, + title = {Multiscalar processors}, + OPTcrossref = {}, + OPTkey = {}, + OPTbooktitle = {Computer Architecture, 1995. Proceedings. 22nd Annual International Symposium on}, + OPTpages = {414-425}, + OPTyear = {1995}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {Santa Margherita Ligure , Italy}, + OPTmonth = {22-24 Jun}, + OPTorganization = {}, + OPTpublisher = {}, + OPTnote = {}, + OPTannote = {} +} +@conference{1995_tullsen, + title={{Simultaneous multithreading: maximizing on-chip parallelism}}, + author={Tullsen, D.M. and Eggers, S.J. and Levy, H.M.}, + booktitle={Proceedings of the 22nd annual international symposium on Computer architecture}, + pages={392--403}, + year={1995}, + organization={ACM New York, NY, USA} +} +@article{adve1996smc, + title={{Shared Memory Consistency Models: A Tutorial}}, + author={Adve, S.V. and Gharachorloo, K.}, + journal={COMPUTER}, + pages={66--76}, + year={1996}, + publisher={IEEE Computer Society} +} +@conference{farkas1996rfd, + title={{Register File Design Considerations in Dynamically Scheduled Processors}}, + author={Farkas, K.I. and Jouppi, N.P. and Chow, P.}, + booktitle={Proceedings of the Second IEEE Symposium on High-Performance Computer Architecture}, + pages={40--51}, + year={1996} +} +@InBook{ 1996_mudge, + ALTauthor = {trevor mudge}, + ALTeditor = {}, + title = {ACM Computing Surveys (CSUR)}, + chapter = { Special ACM 50th-anniversary issue: strategic directions in computing research}, + publisher = {ACM Press New York, NY, USA }, + year = {1996}, + OPTkey = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTtype = {}, + OPTaddress = {}, + OPTedition = {}, + OPTmonth = {december}, + OPTpages = {671 - 678}, + OPTnote = {}, + OPTannote = {} +} +@InProceedings{1996_olukotun, + author = { Kunle Olukotun and + Basem A. Nayfeh and + Lance Hammond and + Ken Wilson and + Kunyung Chang + }, + title = {the case for a single-chip multiprocessor}, + OPTcrossref = {ISBN:0-89791-767-7}, + OPTkey = {}, + OPTbooktitle = {Proceedings of the seventh international conference on Architectural support for programming languages and operating systems}, + OPTpages = {2-11}, + OPTyear = {1996}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {Cambridge, Massachusetts, United States}, + OPTmonth = {}, + OPTorganization = {}, + OPTpublisher = {ACM Press}, + OPTnote = {}, + OPTannote = {} +} +@article{1996_tullsen, + title={{Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor}}, + author={Tullsen, D.M. and Eggers, S.J. and Emer, J.S. and Levy, H.M. and Lo, J.L. and Stamm, R.L.}, + journal={Proceedings of the 23rd annual international symposium on Computer architecture}, + pages={191--202}, + year={1996}, + publisher={ACM Press New York, NY, USA} +} +@InProceedings{1996_wallace, + author = {Wallace, S. and + Bagherzadeh, N. }, + title = {A scalable register file architecture for dynamically scheduled processors}, + OPTcrossref = {}, + OPTkey = {}, + OPTbooktitle = {Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on}, + OPTpages = {179-184}, + OPTyear = {1996}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {Boston, MA, USA}, + OPTmonth = {Oct}, + OPTorganization = {}, + OPTpublisher = {}, + OPTnote = {}, + OPTannote = {} +} +@conference{wallace1996srf, + title={{A Scalable Register File Architecture for Dynamically Scheduled Processors}}, + author={Wallace, S. and Bagherzadeh, N.}, + booktitle={Proceedings of PACT}, + year={1996} +} +@article{1996_yeager, + title={{The Mips R10000 superscalar microprocessor}}, + author={Yeager, KC}, + journal={Micro, IEEE}, + volume={16}, + number={2}, + pages={28--41}, + year={1996} +} +@article{burger1997sts, + title={{The SimpleScalar tool set, version 2.0}}, + author={Burger, D. and Austin, T.M.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={25}, + number={3}, + pages={13--25}, + year={1997}, + publisher={ACM Press New York, NY, USA} +} +@InProceedings{1997_palacharla, + author = {Palacharla, S. and + Jouppi, N.P. and + Smith, J.E. }, + title = {Complexity-Effective Superscalar Processors}, + OPTcrossref = {}, + OPTkey = {}, + OPTbooktitle = {Computer Architecture, 1997. Conference Proceedings. The 24th Annual International Symposium on}, + OPTpages = {206 - 218}, + OPTyear = {1997}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {}, + OPTmonth = {Jun}, + OPTorganization = {}, + OPTpublisher = {}, + OPTnote = {}, + OPTannote = {} +} +@InProceedings{1998a_hammond, + author = {Lance Hammond and + Mark Willey and + Kunle Olukotun}, + title = {}, + OPTcrossref = {SSN:0163-5980}, + OPTkey = {}, + OPTbooktitle = {Proceedings of the eighth international conference on Architectural support for programming languages and operating systems}, + OPTpages = {58-69}, + OPTyear = {1998}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = { San Jose, California, United States}, + OPTmonth = {}, + OPTorganization = {}, + OPTpublisher = {ACM Press}, + OPTnote = {}, + OPTannote = {} +} +@TechReport{1998b_hammond, + author = {Lance Hammond and + Kunle Olukotun}, + title = {Considerations in the design of hydra : a multiprocessor-on-a-chip microarchitecture}, + institution = {Stanford University}, + year = {1998}, + OPTkey = {CSL-TR-98-749}, + OPTtype = {}, + OPTnumber = {}, + OPTaddress = {}, + OPTmonth = {February}, + OPTnote = {}, + OPTannote = {} +} +@article{chrysos1998mdp, + title={{Memory dependence prediction using store sets}}, + author={Chrysos, G.Z. and Emer, J.S.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={26}, + number={3}, + pages={142--153}, + year={1998} +} +@article{1998_kessler, + title={{The Alpha 21264 microprocessor architecture}}, + author={Kessler, RE and McLellan, EJ and Webb, DA}, + journal={Computer Design: VLSI in Computers and Processors, 1998. ICCD'98. Proceedings., International Conference on}, + pages={90--95}, + year={1998} +} +@InProceedings{1998_krishnan, + author = {Krishnan, V. and + Torrellas, J. }, + title = {A clustered approach to multithreaded processors}, + OPTcrossref = {}, + OPTkey = {}, + OPTbooktitle = {Parallel Processing Symposium, 1998. 1998 IPPS/SPDP. Proceedings of the First Merged International...and Symposium on Parallel and Distributed Processing 1998}, + OPTpages = {627-634}, + OPTyear = {1998}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {Orlando, FL , USA}, + OPTmonth = {30 Mar - 3 Apr}, + OPTorganization = {}, + OPTpublisher = {}, + OPTnote = {}, + OPTannote = {} +} +@article{mikhail1001dmo, + title={{Design of a 290 MHz Out of Order Microprocessor with Register Renaming and Speculative Memory Access}}, + author={Mikhail, J. and Karl, E. and Dreslinski, R. and Davidson, G.}, + journal={Ann Arbor}, + volume={1001}, + pages={48109} +} +@conference{1998_skadron, + title={{Improving Prediction for Procedure Returns with Return-Address-Stack Repair Mechanisms}}, + author={Skadron, K. and Ahuja, P.S. and Martonosi, M. and Clark, D.W.}, + booktitle={MICRO-ANNUAL WORKSHOP THEN ANNUAL INTERNATIONAL SYMPOSIUM-}, + volume={31}, + pages={259--271}, + year={1998}, + organization={THE ASSOCIATION FOR COMPUTING MACHINERY} +} +@article{farkas1999mar, + title={{The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning}}, + author={Farkas, K.I. and Chow, P. and Jouppi, N.P. and Vranesic, Z.}, + journal={International Journal of Parallel Programming}, + volume={27}, + number={5}, + pages={327--356}, + year={1999}, + publisher={Springer} +} +@article{1999_schlansker, + title={{EPIC: An Architecture for Instruction-Level Parallel Processors}}, + author={Schlansker, M.S. and Rau, B.R. and Hewlett-Packard Laboratories}, + journal={HP LABORATORIES TECHNICAL REPORT HPL}, + year={1999}, + publisher={HEWLETT-PACKARD LABORATORIES} +} +@article{skadron1999bpi, + title={{Branch prediction, instruction-window size, and cache size: performance trade-offs and simulation techniques}}, + author={Skadron, K. and Ahuja, PS and Martonosi, M. and Clark, DW}, + journal={Transactions on Computers}, + volume={48}, + number={11}, + pages={1260--1281}, + year={1999} +} + +@article{2000_barroso, + title={{Piranha: a scalable architecture based on single-chip multiprocessing}}, + author={Barroso, L.A. and Gharachorloo, K. and McNamara, R. and Nowatzyk, A. and Qadeer, S. and Sano, B. and Smith, S. and Stets, R. and Verghese, B.}, + journal={Proceedings of the 27th annual international symposium on Computer architecture}, + pages={282--293}, + year={2000}, + publisher={ACM Press New York, NY, USA} +} +@article{borkenhagen2000mpp, + title={{A multithreaded PowerPC processor for commercial servers}}, + author={Borkenhagen, JM and Eickemeyer, RJ and Kalla, RN and Kunkel, SR}, + journal={IBM J. RES. DEV}, + volume={44}, + number={6}, + pages={885--898}, + year={2000} +} +@article{cruz2000mbr, + title={{Multiple-banked register file architectures}}, + author={Cruz, J.L. and Gonzalez, A. and Valero, M. and Topham, N.P.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={28}, + number={2}, + pages={316--325}, + year={2000} +} +@article{2000_cvetanovic, + title={{Performance analysis of the Alpha 21264-based Compaq ES40 system}}, + author={Cvetanovic, Z. and Kessler, RE}, + journal={ACM SIGARCH Computer Architecture News}, + volume={28}, + number={2}, + pages={192--202}, + year={2000}, + publisher={ACM New York, NY, USA} +} +@article{2000_hammond, + title={{The Stanford Hydra CMP}}, + author={Hammond, L. and Hubbert, B.A. and Siu, M. and Prabhu, M.K. and Chen, M. and Olukotun, K.}, + journal = {Micro, IEEE}, + year = {2000} +} +@article{klaiber2000tbc, + title={{The Technology Behind Crusoe Processors}}, + author={Klaiber, A. and others}, + journal={Transmeta Technical Brief}, + year={2000} +} +@article{2000_schlansker, + title={{EPIC: Explicitly Parallel Instruction Computing}}, + author={Schlansker, M.S. and Rau, B.R.}, + journal={COMPUTER}, + pages={37--45}, + year={2000}, + publisher={IEEE Computer Society} +} +@article{2000_sharangpani, + title={{Itanium processor microarchitecture}}, + author={Sharangpani, H. and Arora, H.}, + journal={Micro, IEEE}, + volume={20}, + number={5}, + pages={24--43}, + year={2000} +} +@article{2000_sima, + title={{The design space of register renaming techniques}}, + author={Sima, D. and Polytech, B.}, + journal={Micro, IEEE}, + volume={20}, + number={5}, + pages={70--83}, + year={2000} +} +@article{sima2000dsr, + title={{The design space of register renaming techniques}}, + author={Sima, D. and Polytech, B.}, + journal={Micro, IEEE}, + volume={20}, + number={5}, + pages={70--83}, + year={2000} +} +@conference{balasubramonian2001rcr, + title={{Reducing the complexity of the register file in dynamic superscalar processors}}, + author={Balasubramonian, R. and Dwarkadas, S. and Albonesi, D.H.}, + booktitle={Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture}, + pages={237--248}, + year={2001}, + organization={IEEE Computer Society Washington, DC, USA} +} +@article{2001_burns, + title={{Area and system clock effects on SMT/CMP processors}}, + author={Burns, J. and Gaudiot, J.L.}, + journal={Parallel Architectures and Compilation Techniques, 2001. Proceedings. 2001 International Conference on}, + pages={211--218}, + year={2001} +} +@article{guthaus2001mfc, + title={{MiBench: A free, commercially representative embedded benchmark suite}}, + author={Guthaus, MR and Ringenberg, JS and Ernst, D. and Austin, TM and Mudge, T. and Brown, RB}, + journal={Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on}, + pages={3--14}, + year={2001} +} +@article{2001_hinton, + title={{The microarchitecture of the Pentium 4 processor}}, + author={Hinton, G. and Sager, D. and Upton, M. and Boggs, D. and Carmean, D. and Kyker, A. and Roussel, P.}, + journal={Intel Technology Journal}, + volume={1}, + pages={2001}, + year={2001} +} +@InProceedings{2001_nagarajan, + author = { Ramadass Nagarajan and + Karthikeyan Sankaralingam and + Doug Burger and + Stephen W. Keckler}, + title = {A design space evaluation of grid processor architectures}, + OPTcrossref = {SBN ~ ISSN:1072-4451 , 0-7695-1369-7}, + OPTkey = {}, + OPTbooktitle = {Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture }, + OPTpages = {40-51}, + OPTyear = {2001}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = { Austin, Texas}, + OPTmonth = {}, + OPTorganization = {}, + OPTpublisher = { IEEE Computer Society }, + OPTnote = {}, + OPTannote = {} +} +@article{ernst2002eds, + title={{Efficient dynamic scheduling through tag elimination}}, + author={Ernst, D. and Austin, T.}, + journal={Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on}, + pages={37--46}, + year={2002} +} +@article{akkary2003cpa, + title={{Checkpoint processing and recovery: towards scalable large instruction window processors}}, + author={Akkary, H. and Rajwar, R. and Srinivasan, ST}, + journal={Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on}, + pages={423--434}, + year={2003} +} +@article{2002_mukherjee, + title={{The Alpha 21364 network architecture}}, + author={Mukherjee, SS and Bannon, P. and Lang, S. and Spink, A. and Webb, D.}, + journal={Micro, IEEE}, + volume={22}, + number={1}, + pages={26--35}, + year={2002} +} +@article{2002_sprangle, + title={{Increasing processor performance by implementing deeper pipelines}}, + author={Sprangle, E. and Carmean, D.}, + journal={Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on}, + pages={25--34}, + year={2002} +} +@article{2002_tendler, + title={{POWER4 system microarchitecture}}, + author={Tendler, J.M. and Dodson, J.S. and Fields Jr, J.S. and Le, H. and Sinharoy, B.}, + journal={IBM Journal of Research and Development}, + volume={46}, + number={1}, + pages={5--25}, + year={2002} +} +@Article{2002_ungerer, + author = {T. Ungerer and + B. Robic and + J. Silc }, + title = {Multithreaded processors}, + journal = {The Computer Journal}, + year = {2002}, + OPTkey = {}, + OPTvolume = {45}, + OPTnumber = {3}, + OPTpages = {320-348}, + OPTmonth = {}, + OPTnote = {}, + OPTannote = {} +} +@article{darsch2003oop, + title={{Out-of-order Predicated Execution with Translation Register Buffer}}, + author={Darsch, A. and Seznec, A.}, + journal={Rapport technique RR-1573}, + year={2003} +} +@conference{dehnert2003tcm, + title={{The Transmeta Code Morphing Software: using speculation, recovery, and adaptive retranslation to address real-life challenges}}, + author={Dehnert, J.C. and Grant, B.K. and Banning, J.P. and Johnson, R. and Kistler, T. and Klaiber, A. and Mattson, J.}, + booktitle={ACM International Conference Proceeding Series}, + volume={37}, + pages={15--24}, + year={2003} +} +@article{heinrich:smt, + title={{Scalable Multi-threaded Multiprocessor Architectures}}, + author={Heinrich, M.} +} +@article{2003_jeong, + title={{Cost-sensitive cache replacement algorithms}}, + author={Jeong, J. and Dubois, M.}, + journal={High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on}, + pages={327--337}, + year={2003} +} +@article{keltcher2003aop, + title={{The AMD Opteron Processor for Multiprocessor Servers}}, + author={Keltcher, C.N. and McGrath, K.J. and Ahmed, A. and Conway, P.}, + journal={IEEE MICRO}, + pages={66--76}, + year={2003}, + publisher={IEEE Computer Society} +} +@article{2003_koufaty, + title={{Hyperthreading technology in the netburst microarchitecture}}, + author={Koufaty, D. and Marr, DT}, + journal={Micro, IEEE}, + volume={23}, + number={2}, + pages={56--65}, + year={2003} +} +@conference{kumar2003sih, + title={{Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction}}, + author={Kumar, R. and Farkas, KI and Jouppi, NP and Ranganathan, P. and Tullsen, DM}, + booktitle={Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on}, + pages={81--92}, + year={2003} +} +@article{2003_mcnairy, + title={{Itanium 2 processor microarchitecture}}, + author={McNairy, C. and Soltis, D.}, + journal={Micro, IEEE}, + volume={23}, + number={2}, + pages={44--55}, + year={2003} +} +@conference{park2003rdc, + title={{Reducing Design Complexity of the Load/Store Queue}}, + author={Park, I. and Ooi, C.L. and Vijaykumar, TN}, + booktitle={Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture}, + year={2003}, + organization={IEEE Computer Society Washington, DC, USA} +} +@article{park2003rdc, + title={{Reducing design complexity of the load/store queue}}, + author={Park, I. and Ooi, C.L. and Vijaykumar, TN}, + journal={Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on}, + pages={411--422}, + year={2003} +} +@InProceedings{2003_sankaralingam, + author = { Karthikeyan Sankaralingam and + Ramadass Nagarajan and + Haiming Liu and + Changkyu Kim and + Jaehyuk Huh and + Doug Burger and + Stephen W. Keckler and + Charles R. Moore}, + title = {Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture}, + OPTcrossref = { ISBN:0-7695-1945-8}, + OPTkey = {}, + OPTbooktitle = {Proceedings of the 30th annual international symposium on Computer architecture}, + OPTpages = {422-433}, + OPTyear = {2003}, + OPTeditor = {}, + OPTvolume = {Volume 31 Issue 2}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {San Diego, California}, + OPTmonth = {May}, + OPTorganization = {}, + OPTpublisher = {ACM Press}, + OPTnote = {}, + OPTannote = {} +} +@article{sethumadhavan2003shm, + title={{Scalable hardware memory disambiguation for high ILP processors}}, + author={Sethumadhavan, S. and Desikan, R. and Burger, D. and Moore, CR and Keckler, SW}, + journal={Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on}, + pages={399--410}, + year={2003} +} +@InProceedings{2004_chaudhuri, + author = {Mainak Chaudhuri and + Mark Heinrich}, + title = {SMTp: An Architecture for Next-generation Scalable Multi-threading}, + OPTcrossref = {}, + OPTkey = {}, + OPTbooktitle = {Proceedings of the 31st annual international symposium on Computer architecture}, + OPTpages = {124-136}, + OPTyear = {2004}, + OPTeditor = {}, + OPTvolume = {0}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {München, Germany}, + OPTmonth = {}, + OPTorganization = {}, + OPTpublisher = {IEEE Computer Society}, + OPTnote = {}, + OPTannote = {} +} +@article{2004_collins, + title={{Clustered multithreaded architectures-pursuing both IPC and cycle time}}, + author={Collins, JD and Tullsen, DM}, + journal={Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International}, + year={2004} +} +@conference{cristal2004ooc, + title={{Out-of-Order Commit Processors}}, + author={Cristal, A. and Ortega, D. and Llosa, J. and Valero, M.}, + booktitle={Proceedings of the 10th International Symposium on High Performance Computer Architecture}, + pages={48}, + year={2004}, + organization={IEEE Computer Society Washington, DC, USA} +} +@article{2004_dolbeau, + title={{CASH: Revisiting hardware sharing in single-chip parallel processor}}, + author={Dolbeau, R. and Seznec, A.}, + journal={Journal of Instruction-Level Parallelism}, + volume={6}, + pages={1--16}, + year={2004} +} +@article{2004_kalla, + title={{IBM Power5 chip: a dual-core multithreaded processor}}, + author={Kalla, R. and Sinharoy, B. and Tendler, JM}, + journal={Micro, IEEE}, + volume={24}, + number={2}, + pages={40--47}, + year={2004} +} +@article{2004_kumar, + title={{Conjoined-Core Chip Multiprocessing}}, + author={Kumar, R. and Jouppi, N.P. and Tullsen, D.M.}, + journal={Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture}, + pages={195--206}, + year={2004}, + publisher={IEEE Computer Society Washington, DC, USA} +} +@article{kumar2004sih, + title={{Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance}}, + author={Kumar, R. and Tullsen, D.M. and Ranganathan, P. and Jouppi, N.P. and Farkas, K.I.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={32}, + number={2}, + year={2004}, + publisher={ACM New York, NY, USA} +} +@book{mattsson:esc, + title={{Evaluation of synthesizable CPU cores}}, + author={Mattsson, D. and Christensson, M.}, + publisher={Chalmers tekniska h{\"o}gskola} +} +@article{tune2004bmi, + title={{Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy}}, + author={Tune, E. and Kumar, R. and Tullsen, D.M. and Calder, B.}, + journal={Proceedings of the 37th International Symposium on Microarchitecture. IEEE}, + year={2004} +} + +@InProceedings{ 2004_wang, + author = {Nicholas J. Wang and + Justin Quek and + Todd M. Rafacz and + Sanjay J. Pate}, + title = {Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline}, + OPTcrossref = {In the Proceedings of the 2004 International Conference on Dependable Systems and Networks}, + OPTkey = {}, + OPTbooktitle = {}, + OPTpages = {}, + OPTyear = {2004}, + OPTeditor = {}, + OPTvolume = {}, + OPTnumber = {}, + OPTseries = {}, + OPTaddress = {Florence , ITALY}, + OPTmonth = {june}, + OPTorganization = {}, + OPTpublisher = {}, + OPTnote = {}, + OPTannote = {} +} +@techreport{2005_ARM, + title={{Architecture and Implementation of the ARM Cortex-A8 Microprocessor}}, + author={ARM}, + institution={ARM} +} +@article{constantinou2005pis, + title={{Performance implications of single thread migration on a chip multi-core}}, + author={Constantinou, T. and Sazeides, Y. and Michaud, P. and Fetis, D. and Seznec, A.}, + journal={ACM SIGARCH Computer Architecture News}, + volume={33}, + number={4}, + pages={80--91}, + year={2005}, + publisher={ACM New York, NY, USA} +} +@article{dimond2005cct, + title={{CUSTARD-A Customisable Threaded FPGA Soft Processor and Tools}}, + author={Dimond, R. and Mencer, O. and Luk, W.}, + journal={International Conference on Field Programmable Logic (FPL)}, + year={2005} +} +@book{2005_fisher, + title={{Embedded Computing: A Vliw Approach To Architecture, Compilers And Tools}}, + author={Joseph A. Fisher, Paolo Faraboschi and Cliff Young}, + year={2005}, + publisher={Morgan Kaufmann Publishers} +} +@article{2005_kahle, + title={{Introduction to the Cell multiprocessor}}, + author={Kahle, J. and others}, + journal={IBM Journal of Research and Development}, + volume={49}, + number={4}, + pages={589--604}, + year={2005} +} +@article{2005_kongetira, + title={{Niagara: a 32-way multithreaded Sparc processor}}, + author={Kongetira, P. and Aingaran, K. and Olukotun, K.}, + journal={IEEE Micro}, + volume={25}, + number={2}, + pages={21--29}, + year={2005} +} +@article{2005_kumar, + title={{Heterogeneous Chip Multiprocessors}}, + author={Kumar, R. and Tullsen, D.M. and Jouppi, N.P. and Ranganathan, P.}, + journal={COMPUTER}, + pages={32--38}, + year={2005}, + publisher={IEEE Computer Society} +} +@article{2005_mcnairy, + title={{Montecito: a dual-core, dual-thread Itanium processor}}, + author={McNairy, C. and Bhatia, R.}, + journal={Micro, IEEE}, + volume={25}, + number={2}, + pages={10--20}, + year={2005} +} +@article{percival2005cmf, + title={{Cache missing for fun and profit}}, + author={Percival, C.}, + journal={BSDCan 2005}, + year={2005} +} +@article{siddiqui:pap, + title={{POWER4 and POWER5 Scalability}}, + author={Siddiqui, W. and VanBuren, B.G.} +} +@article{2005_sinharoy, + title={{POWER5 system microarchitecture}}, + author={Sinharoy, B. and Kalla, R.N. and Tendler, J.M. and Eickemeyer, R.J. and Joyner, J.B.}, + journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, + volume={49}, + number={4/5}, + pages={505}, + year={2005}, + publisher={IBM CORPORATION} +} +@book{yiannacouras2005mfb, + title={{The microarchitecture of FPGA-based soft processors}}, + author={Yiannacouras, P. and Rose, J. and Steffan, J.G.}, + year={2005}, + publisher={ACM New York, NY, USA} +} +@book{yiannacouras2005mfb, + title={{The microarchitecture of FPGA-based soft processors}}, + author={Yiannacouras, P. and Rose, J. and Steffan, J.G.}, + year={2005}, + publisher={ACM New York, NY, USA} +} +@article{2006_ghasemzadeh, + title={{Modified Pseudo LRU Replacement Algorithm}}, + author={Ghasemzadeh, H. and Mazrouee, SS and Kakoee, MR}, + journal={Engineering of Computer Based Systems, 2006. ECBS 2006. 13th Annual IEEE International Symposium and Workshop on}, + pages={368--376}, + year={2006} +} +@article{2006_gochman, + title={{Introduction to Intel Core Duo processor architecture}}, + author={Gochman, S. and Mendelson, A. and Naveh, A. and Rotem, E.}, + journal={Intel Technology Journal}, + volume={10}, + number={2}, + pages={89--97}, + year={2006} +} +@conference{kumar2006cao, + title={{Core architecture optimization for heterogeneous chip multiprocessors}}, + author={Kumar, R. and Tullsen, D.M. and Jouppi, N.P.}, + booktitle={Proceedings of the 15th international conference on Parallel architectures and compilation techniques}, + pages={23--32}, + year={2006}, + organization={ACM New York, NY, USA} +} +@article{mcghan2006nof, + title={{Niagara 2 Opens the Floodgates}}, + author={McGhan, H.}, + journal={Microprocessor Report}, + volume={20}, + number={11}, + year={2006} +} +@article{mendelson2006cis, + title={{CMP Implementation in Systems Based on the Intel Core Duo Processor}}, + author={Mendelson, A. and others}, + journal={Intel Tech. Journal}, + volume={10}, + number={2}, + year={2006} +} +@article{sangireddy2006rrl, + title={{Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures}}, + author={Sangireddy, R.}, + journal={IEEE TRANSACTIONS ON COMPUTERS}, + pages={672--685}, + year={2006}, + publisher={IEEE Computer Society} +} +@misc{microsystems2006otm, + title={{OpenSPARC T1 Microarchitecture Specification}}, + author={Microsystems, S.}, + year={2006}, + publisher={August} +} +@article{yiannacouras2006asc, + title={{Application-specific customization of soft processor microarchitecture}}, + author={Yiannacouras, P. and Steffan, J.G. and Rose, J.}, + journal={Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays}, + pages={201--210}, + year={2006}, + publisher={ACM New York, NY, USA} +} +@techreport{2007_ARM, + title={{The ARM Cortex-A9 Processor}}, + author={ARM}, + institution={ARM} +} +@phdthesis{bingham2007mrl, + title={{A MIPS R10000-Like Out-Of-Order Microprocessor Implementation in verilog HDL}}, + author={Bingham, S.T.}, + year={2007}, + school={Cornell University} +} +@article{eisen:ipa, + title={{IBM POWER6 accelerators: VMX and DFU-References}}, + author={Eisen, L. and Ward III, JW and Tast, HW and M{\"a}ding, N. and Leenstra, J. and Mueller, SM and Jacobi, C. and Preiss, J. and Schwarz, EM and Carlough, SR} +} +@article{2007_le, + title={{IBM POWER6 microarchitecture}}, + author={Le, HQ and Starke, WJ and Fields, JS and O Connell, FP and Nguyen, DQ and Ronchetti, BJ and Sauer, WM and Schwarz, EM and Vaden, MT}, + journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, + volume={51}, + number={6}, + pages={639}, + year={2007}, + publisher={IBM CORPORATION} +} +@conference{li2007map, + title={{Microarchitecture and Performance Analysis of Godson-2 SMT Processor}}, + author={Li, Z. and Xu, X. and Hu, W. and Tang, Z.}, + booktitle={Computer Design, 2006. ICCD 2006. International Conference on}, + pages={485--490}, + year={2007} +} +@article{hardware6mom, + title={{Memory Ordering in Modern Microprocessors}}, + author={Hardware, S. and Accesses, W.R.M.}, + journal={Interface}, + volume={6}, + pages={6} +} +@article{sethumadhavan2007lbe, + title={{Late-binding: enabling unordered load-store queues}}, + author={Sethumadhavan, S. and Roesner, F. and Emer, J.S. and Burger, D. and Keckler, S.W.}, + journal={Proceedings of the 34th annual international conference on Computer architecture}, + pages={347--357}, + year={2007}, + publisher={ACM Press New York, NY, USA} +} +@conference{williams2008lbs, + title={{Lattice Boltzmann simulation optimization on leading multicore platforms}}, + author={Williams, S. and Carter, J. and Oliker, L. and Shalf, J. and Yelick, K.}, + booktitle={Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on}, + pages={1--14}, + year={2008} +} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/Makefile (revision 91) @@ -0,0 +1,22 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = ../.. + +#-----[ include ]------------------------------------------ + +all : + @\ + $(MAKE) all_documentation + +view : view_local + +local_clean : + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/document-morpheo-input_files-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/document-morpheo-input_files-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/document-morpheo-input_files-fr.tex (revision 91) @@ -0,0 +1,46 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,onecolumn]{article} + +\def\lang{fr} +\def\dirroot{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../sty/doc-style} + +%document-style list language (Change this file to add language) +\langFRtrue + +\usepackage{sty/header} + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{fancy} % default style + +\begin{document} + +% Créez une page de titre +\maketitle +%\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{\dirroot/root-fr} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/sty/header.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/sty/header.sty (revision 91) @@ -0,0 +1,22 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\cpu{MORPHEO~} +\def\CPU{\cpu} + +%\def\review{YYYY/MM/DD} +\def\review{\number\day/\number\month/\number\year\xspace} +\date{\review} + +\iflangFR % Français + \title{\cpu\\Format des fichiers d'entrée} + \author{} + \affiliation{Département ALSOC - Laboratoire d'informatique de Paris VI - France} + \email{} +\else % Others language + \title{} + \author{} + \affiliation{} + \email{} +\fi Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.cfg (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.cfg (revision 91) @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.sim (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/example_1.sim (revision 91) @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/generator_configuration_file-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/generator_configuration_file-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/generator_configuration_file-fr.tex (revision 91) @@ -0,0 +1,201 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Fichier de configuration du générateur} + +\subSection{Description} + +Ce fichier contient la liste des paramètres et de leur évolution. C'est-à-dire les valeurs minimales, maximales... Ce fichier n'est utilisé qu'en lecture par les différents outils de \cpu. + +Si un concepteur modifie le générateur \cpu et ajoute des paramètres, il devra rajouter une entrée dans ce fichier. + +Ce fichier est écrit au format XML. + +\subSection{Syntaxe} + +\verbatiminput{\dirroot/syntax.gen} + +\begin{description} +\item[balise parameters :] {\it (Obligatoire et unique)} Balise englobante. + \begin{description} + \item[balise parameter :] {\it (Nombre quelconque d'occurrences)} Décris un paramètre du générateur. + \begin{description} + \item[attribut name :] {\it (Obligatoire)} Nom du paramètre. + \item[attribut min :] {\it (Obligatoire si attribut max ou step est présent)} Valeur minimale du paramètre. + \item[attribut max :] {\it (Obligatoire si attribut min ou step est présent)} Valeur maximale du paramètre. + \item[attribut step :] {\it (Obligatoire si attribut min ou max est présent)} Pas entre deux valeurs de paramètres (par exemple +1 ou *2). + \item[attribut default :] {\it (Obligatoire)} Valeur par défaut de ce paramètre. + \item[attribut level :] {\it (Optionnel )} Niveau requis pour que l'utilisateur puisse voir ce paramètre. Le niveau varie de 0 (paramètre jamais affiché) 1 (affichage de presque aucun des paramètres (mode néophyte) à 5 (affichage de tous les paramètres (mode expert)). La valeur par défaut de cet attribut est 3. + \item[attribut description :] {\it (Optionnel )} Description du paramètre. La valeur par défaut de cet attribut est une chaîne vide. + \end{description} + \item[balise link :] {\it (Nombre quelconque d'occurrences)} Lien entre deux composants du processeur. + \begin{description} + \item[attribut name :] {\it (Obligatoire)} Nom du paramètre. + \item[attribut src :] {\it (Obligatoire)} Source du lien. + \item[attribut dest :] {\it (Optionnel )} Destination du lien. La destination ne doit pas apparaître si c'est un lien binaire (lien présent ou non). + \item[attribut description :] {\it (Optionnel )} Description du paramètre. + \end{description} + \end{description} +\end{description} + +Si une balise {\it parameter} n'a pas les attributs {\it min}, {\it max} et {\it step}, alors il s'agit d'un paramètre qui a une valeur binaire. Ceci ce traduit comme un paramètre classique avec min=''0'', max=''1'' et step=''+ 1''. + +\subSection{Paramètres} + +\begin{description} +\item[size\_data :] +\item[dispatch\_priority :]~\\ + \begin{description} + \item[PRIORITY\_STATIC :] Les priorités sont fixes. + \item[PRIORITY\_ROUND\_ROBIN :] L'entité la plus prioritaire devient au cycle suivant l'entité la moins prioritaire. + \end{description} +\item[dispatch\_load\_balancing :]~\\ + \begin{description} + \item[LOAD\_BALANCING\_BALANCE :] Un élément de l'entité la plus prioritaire est servi, suivit des autres entités par ordre de priorité. + \item[LOAD\_BALANCING\_MAXIMUM\_FOR\_PRIORITY :] Tous les éléments de l'entité la plus prioritaire sont servis, suivirent des autres entités par ordre de priorité. + \end{description} +\item[nb\_icache\_port :] +\item[icache\_access\_priority :] +\item[icache\_access\_load\_balancing :] +\item[nb\_dcache\_port :] +\item[dcache\_access\_priority :] +\item[dcache\_access\_load\_balancing :] +\item[nb\_thread :] +\item[size\_ifetch\_queue :] +\item[nb\_inst\_fetch :] +\item[implement\_group :] +\item[ras\_size\_queue :] +\item[upt\_size\_queue :] +\item[nb\_decod\_bloc :] +\item[size\_decod\_queue :] +\item[nb\_inst\_decod :] +\item[nb\_context\_select :] +\item[context\_select\_priority :] +\item[context\_select\_load\_balancing :] +\item[nb\_rename\_bloc :] +\item[nb\_inst\_insert :] +\item[nb\_inst\_retire :] +\item[rename\_select\_priority :] +\item[rename\_select\_load\_balancing :] +\item[rename\_select\_nb\_front\_end\_select :] +\item[nb\_general\_register :] +\item[nb\_special\_register :] +\item[nb\_reg\_free :] +\item[nb\_rename\_unit\_bank :] +\item[size\_read\_counter :] +\item[nb\_read\_bloc :] +\item[size\_read\_queue :] +\item[size\_reservation\_station :] +\item[nb\_inst\_retire\_reservation\_station :] +\item[nb\_write\_bloc :] +\item[size\_write\_queue :] +\item[size\_execute\_queue :] +\item[nb\_bypass\_write :] +\item[nb\_load\_store\_unit :] +\item[size\_store\_queue :] +\item[size\_load\_queue :] +\item[size\_speculative\_access\_queue :] +\item[nb\_port\_check :] +\item[speculative\_load :]~\\ + \begin{description} + \item[NO\_SPECULATIVE\_LOAD :] Chaque lecture mémoire attend que toutes les écritures mémoires antérieures soient connues avant d'accéder au cache. + \item[SPECULATIVE\_LOAD\_ACCESS :] Chaque lecture mémoire attend que toutes les écritures mémoires antérieures soient connues avant d'écrire le résultat dans le banc de registre. L'accès au cache est préventif. + \item[SPECULATIVE\_LOAD\_COMMIT :] Les instructions mémoires n'attendent pas que toutes les écritures mémoires antérieures soient connues avec d'accéder au cache et d'écrire le résultat dans le banc de registres. + \item[SPECULATIVE\_LOAD\_BYPASS :] Les instructions mémoires n'attendent pas que toutes les écritures mémoires antérieures soient connues avec d'accéder au cache, d'écrire le résultat dans le banc de registres et de transmettre la donnée lue sur le réseau de bypass. + \end{description} +\item[nb\_bypass\_memory :] +\item[nb\_cache\_port :] +\item[nb\_inst\_memory :] +\item[nb\_functionnal\_unit :] +\item[nb\_inst\_functionnal\_unit :] +\item[nb\_front\_end :] +\item[nb\_context :] +\item[nb\_decod\_unit :] +\item[nb\_inst\_branch\_predict :] +\item[nb\_inst\_branch\_decod :] +\item[nb\_inst\_branch\_update :] +\item[btb\_size\_queue :] +\item[btb\_associativity :] +\item[btb\_size\_counter :] +\item[btb\_victim\_scheme :]~\\ + \begin{description} + \item[VICTIM\_RANDOM :] La victime est choisie de façon aléatoire. + \item[VICTIM\_ROUND\_ROBIN :] La victime est choisie de façon circulaire. + \item[VICTIM\_NLU :] La victime est choisie de façon aléatoire. Le dernier élément utilisé est un choix invalide. + \item[VICTIM\_PSEUDO\_LRU :] La victime suivant un schéma presque LRU. + \item[VICTIM\_LRU :] Les éléments sont classés par date d'utilisation. La victime choisie est la moins récemment utilisée. + \item[VICTIM\_FIFO :] Les éléments sont classés par ordre d'arrivée. La victime choisie est la plus ancienne. + \end{description} +\item[dir\_predictor\_scheme :]~\\ + \begin{description} + \item[PREDICTOR\_NEVER\_TAKE :] Le branchement n'est jamais pris. + \item[PREDICTOR\_ALWAYS\_TAKE :] Le branchement est toujours pris. + \item[PREDICTOR\_STATIC :] Si la destination du branchement se situe avant l'instruction du branchement, alors le branchement est pris. + \item[PREDICTOR\_LAST\_TAKE :] La direction sera la même que la fois précédente. Si c'est la première fois que le branchement est rencontré, alors la prédiction suit le schéma statique. + \item[PREDICTOR\_COUNTER :] Table de compteur indexé par l'adresse du branchement. La direction du branchement est déterminée par le bit de poids fort du compteur. + \item[PREDICTOR\_LOCAL :] Table de compteur indexé par une table d'historique qui est lui-même indexé par l'adresse du branchement. + \item[PREDICTOR\_GLOBAL :] Table de compteur indexé par une table d'historique à une entrée qui est lui-même indexé par l'adresse du branchement. + \item[PREDICTOR\_META :] 3 prédicteurs de branchement : une table de compteur va sélectionner entre la prédiction provenant du prédicteur local ou du prédicteur global. C'est trois prédicteurs sont indexés par l'adresse du branchement. + \item[PREDICTOR\_CUSTOM :] Il s'agit d'un méta prédicteur. Mais les 3 prédicteurs internes sont paramétrables. C'est trois prédicteurs sont indexés par l'adresse du branchement. + \end{description} +\item[dir\_have\_bht :] +\item[dir\_bht\_size\_shifter :] +\item[dir\_bht\_nb\_shifter :] +\item[dir\_have\_pht :] +\item[dir\_pht\_size\_counter :] +\item[dir\_pht\_nb\_counter :] +\item[dir\_pht\_size\_address\_share :] +\item[nb\_ooo\_engine :] +\item[nb\_rename\_unit :] +\item[nb\_inst\_issue :] +\item[nb\_inst\_reexecute :] +\item[nb\_inst\_commit :] +\item[nb\_inst\_branch\_complete :] +\item[nb\_rename\_unit\_select :] +\item[nb\_execute\_loop\_select :] +\item[size\_re\_order\_buffer :] +\item[nb\_re\_order\_buffer\_bank :] +\item[commit\_priority :] +\item[commit\_load\_balancing :] +\item[size\_issue\_queue :] +\item[nb\_issue\_queue\_bank :] +\item[issue\_priority :] +\item[issue\_load\_balancing :] +\item[size\_reexecute\_queue :] +\item[reexecute\_priority :] +\item[reexecute\_load\_balancing :] +\item[nb\_execute\_loop :] +\item[nb\_read\_unit :] +\item[nb\_execute\_unit :] +\item[nb\_write\_unit :] +\item[nb\_gpr\_bank :] +\item[nb\_gpr\_port\_read\_by\_bank :] +\item[nb\_gpr\_port\_write\_by\_bank :] +\item[nb\_spr\_bank :] +\item[nb\_spr\_port\_read\_by\_bank :] +\item[nb\_spr\_port\_write\_by\_bank :] +\item[execution\_unit\_to\_write\_unit\_priority :] +\item[read\_unit\_to\_execution\_unit\_priority :] +\item[link\_context\_with\_thread :] +\item[link\_decod\_unit\_with\_decod\_bloc :] +\item[link\_rename\_unit\_with\_rename\_bloc :] +\item[link\_read\_unit\_with\_read\_bloc :] +\item[link\_write\_unit\_with\_write\_bloc :] +\item[link\_execute\_unit\_with\_functionnal\_unit :] +\item[link\_execute\_unit\_with\_load\_store\_unit :] +\item[link\_decod\_bloc\_with\_thread :] +\item[link\_rename\_bloc\_with\_front\_end :] +\item[table\_dispatch :] +\item[link\_read\_bloc\_and\_load\_store\_unit :] +\item[link\_read\_bloc\_and\_functionnal\_unit :] +\item[link\_write\_bloc\_and\_load\_store\_unit :] +\item[link\_write\_bloc\_and\_functionnal\_unit :] +\item[link\_load\_store\_unit\_with\_thread :] +\item[link\_thread\_and\_functionnal\_unit :] +\item[link\_icache\_port\_with\_thread :] +\item[link\_dcache\_port\_with\_load\_store\_unit :] +\end{description} + +%\subSection{Exemples} + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/instance_configuration_file-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/instance_configuration_file-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/instance_configuration_file-fr.tex (revision 91) @@ -0,0 +1,75 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Fichier de configuration d'une instance} + +\subSection{Description} +Ce fichier liste les paramètres et leur valeur afin de générer une instance. Ce fichier est utilisé en lecture par le générateur de \cpu et en écriture par l'outil de visualisation architecturale. + +\subSection{Syntaxe} + +\verbatiminput{\dirroot/syntax.cfg} + +\begin{description} +\item[balise core :] {\it (Obligatoire et unique)} Balise englobante. + \begin{description} + \item[attribut name :] {\it (Obligatoire)} Nom de l'instance. + \item[balise parameter :] {\it (Nombre quelconque d'occurrences)} Un paramètre du générateur. + \begin{description} + \item [attribut name : ] {\it (obligatoire)} Nom du paramètre. + \item [attribut value : ] {\it (obligatoire)} Valeur de ce paramètre. + \end{description} + \item[balise link :] {\it (Nombre quelconque d'occurrences)} Lien entre deux composants du processeur. + \begin{description} + \item[attribut name :] {\it (Obligatoire)} Nom du paramètre. + \item[attribut src :] {\it (Optionnel )} Source du lien. Si cet attribut n'est pas présent, alors la source du lien est le composant dans lequel il est placé. Le numéro représente l'identifiant de la source. Si la source est un composant contenu dans un autre alors cet attribut prendra la liste de tous les identifiants séparés par des points permettant de cibler le bon composant. Par exemple pour le contexte 5 contenu dans le front end 3, l'attribut src prendra comme valeur : ``3.5''. + \item[attribut dest :] {\it (Obligatoire)} Destination du lien. La syntaxe est la même que pour la source du lien. + \end{description} + + \item[balise component :] {\it (Nombre quelconque d'occurrences)} {\it component} est le nom générique de la balise. En réalité il regroupe tous les blocs internes du processeur. Le nom de la balise prend alors le nom du composant. + \begin{description} + \item[attribut id : ] {\it (Obligatoire)} Identifiant du paramètre. + \item[balise component :] {\it (Nombre quelconque d'occurrences)} Entités internes au bloc courant. + \item[balise parameter :] {\it (Nombre quelconque d'occurrences)} Un paramètre du composant courant. + \item[balise link :] {\it (Nombre quelconque d'occurrences)} Un Lien entre deux entités contenu dans le bloc courant. + \item[balise timing :] {\it (Nombre quelconque d'occurrences)} Seulement si la balise {\it component} englobante est {\it functionnal\_unit}. Il s'agit des informations temporelles des opérations pouvant être exécutées par l'unité fonctionnelle. Les opérations non citées ne sont pas implémentées par l'unité fonctionnelle. + \begin{description} + \item[attribut group :] {\it (Obligatoire)} Groupe d'appartenance de l'opération. + \item[attribut operation :] {\it (Optionnel )} Numéro de l'opération. Si le champ opération n'est pas présent, alors les temps de latence et de delay sont appliquées à toutes les opérations. + \item[attribut latence :] {\it (Optionnel )} Latence avant que le résultat soit produit. Par défaut, la latence est de 1 cycle. + \item[attribut delay :] {\it (Optionnel )} Délai pendant lequel l'unité d'exécution est indisponible. Par défaut, le délai est de 1 cycle. + \end{description} + + \end{description} + \end{description} +\end{description} + +Tous les paramètres {\it parameter} et {\it link} doit être présent dans le fichier de configuration du générateur. + +\subSection{Paramètres} + +Pour les paramètres, voir le fichier de configuration du générateur. Nous allons lister les balises {\it component}: + +\begin{description} +\item[thread :] Contexte matériel + \begin{description} + \item[group :] Information sur les unités spéciales. + \end{description} +\item[decod\_bloc :] Unité de décodage. +\item[rename\_bloc :] Unité de renommage. +\item[read\_bloc :] Unité de lecture des opérandes. +\item[write\_bloc :] Unité d'écriture des résultats. +\item[load\_store\_unit :] Unité de gestion des accès mémoires. +\item[functionnal\_unit :] Unité d'exécution. +\item[front\_end :] Unité de chargement des instructions. Regroupe les contextes matériels et les unités de décodages. + \begin{description} + \item[predictor :] Unité de prédiction. + \end{description} +\item[ooo\_engine :] Unité gestion du désordonnancement des instructions. Regroupes les unités de renommage. +\item[execute\_loop :] Boucle d'exécution. Regroupe les unités de lecture et d'écriture des registres, ainsi que les unités d'exécution et de gestion des accès mémoires. +\end{description} + +\subSection{Exemples} + +\verbatiminput{\dirroot/example_1.cfg} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/root-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/root-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/root-fr.tex (revision 91) @@ -0,0 +1,19 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\SEction{Introduction} + +La librairie \cpu possède 3 fichiers d'entrée : + +\begin{description} +\item[.sim :] Configuration de la simulation. +\item[.gen :] Configuration du générateur. +\item[.cfg :] Configuration d'une instance du générateur. +\end{description} + +Dans la suite de ce document, chaque section va décrire le contenu de chacun de ces fichiers. Ces derniers sont définis suivant la syntaxe XML. + +\input{\dirroot/simulator_configuration_file-fr} +\input{\dirroot/generator_configuration_file-fr} +\input{\dirroot/instance_configuration_file-fr} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/simulator_configuration_file-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/simulator_configuration_file-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/simulator_configuration_file-fr.tex (revision 91) @@ -0,0 +1,59 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\Section{Fichier de configuration de la simulation} + +\subSection{Description} +Ce fichier permet de paramétrer les exécutions d'une simulation du générateur \cpu. +Comme tous les autres fichiers, il est écrit au format XML. + +\subSection{Syntaxe} + +\verbatiminput{\dirroot/syntax.sim} + +\begin{description} +\item [balise parameters : ] {\it (Obligatoire et unique)} Balise englobante. + \begin{description} + \item [balise parameter : ] {\it (Nombre quelconque d'occurrences)} Un paramètre du simulateur. + \begin{description} + \item [attribut name : ] {\it (Obligatoire)} Nom du paramètre. + \item [attribut value : ] {\it (Obligatoire)} Valeur de ce paramètre. + \end{description} + \end{description} +\end{description} + +\subSection{Paramètres} + +\begin{description} +\item[use\_systemc ] \{0,1\} Autorise la simulation d'un modèle cycle accurate bit accurate systemC d'une instance de \cpu. + +\item[use\_vhdl ] \{0,1\} Lors de la génération d'une instance de \cpu, le modèle VHDL de chaque composant interne est généré. + +\item[use\_vhdl\_testbench ] \{0,1\} Lors de la simulation systemC d'une instance de \cpu, les activités sur les entrées/sorties de chaque composant interne sont enregistrées. À l'arrêt de la simulation, un fichier permettant de tester si le modèle VHDL est cycle accurate/ bit accurate par rapport au modèle systemC est généré. + +\item[use\_vhdl\_testbench\_assert ] \{0,1\} Le fichier de test du modèle VHDL est agrémenté de commentaire facilitant le débogage de ce modèle. + +\item[use\_position ] \{0,1\} Un fichier de position est généré. Celui-ci est le point d'entrée de l'outil de visualisation architecturale. + +\item[use\_statistics ] \{0,1\} Lors de la simulation systemC d'une instance de \cpu, il y a une surveillance des activités des structures internes de l'instance. Lors de l'arrêt de la simulation, un fichier récapitulatif va être généré. + +\item[use\_information ] \{0,1\} Affiche des informations sur l'instance du modèle (non encore implémentés). + +\item[use\_header ] \{0,1\} Lors du début d'une simulation, un message introductif est affiché. + +\item[nb\_cycle\_before\_begin ] \{$\ge$0\} Nombre de cycle avant le commencement des statistiques. Ceci permet de faire des statistiques en ne prenant pas en compte le temps de rodage des structures internes du processeur. + +\item[period\_save ] \{$\ge$0\} Période entre deux statistiques. Ceci permet d'avoir un graphe en fonction du temps sur les utilisations des ressources internes. Ce paramètre représente le nombre de cycles entre chaque période de statistiques. Si le paramètre est à 0 alors il n'aura qu'un seul jeu de statistiques, donc un seul point sur le graphe de statistiques. + +\item[simulation\_nb\_cyle ] \{$\ge$0\} Nombre de cycles à atteindre pour mettre fin à la simulation. Une valeur de 0 indique que la simulation n'est pas limitée au nombre de cycle simulé. + +\item[simulation\_nb\_instruction ] \{$\ge$0\} Nombre instructions que chaque contexte doit valider afin d'arrêter la simulation. Une valeur de 0 indique que la simulation n'est pas limitée au nombre d'instructions validées. +Les deux conditions d'arrêt ({\bf simulation\_nb\_instruction} et {\bf simulation\_nb\_cyle}) fonctionnent en concurrence : la première condition atteinte provoque l'arrêt de la simulation. +\end{description} + +\subSection{Exemples} + +Ce fichier configure le simulateur pour effectuer une simulation systemC. La simulation s'arrêtera au bout d'un milliard de cycles. Après un million de cycles, les statistiques d'utilisation des ressources interne vont être calculées et enregistrer tous les dix mille cycles. + +\verbatiminput{\dirroot/example_1.sim} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.cfg (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.cfg (revision 91) @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + ... + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.gen (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.gen (revision 91) @@ -0,0 +1,20 @@ + + + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.sim (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-input_files/tex/syntax.sim (revision 91) @@ -0,0 +1,9 @@ + + + + + + + + + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/Makefile (revision 91) @@ -0,0 +1,22 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = ../.. + +#-----[ include ]------------------------------------------ + +all : + @\ + $(MAKE) all_documentation + +view : view_local + +local_clean : + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/presentation-morpheo-microarchitecture-fr.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/presentation-morpheo-microarchitecture-fr.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/presentation-morpheo-microarchitecture-fr.tex (revision 91) @@ -0,0 +1,45 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass{beamer} + +\usepackage{beamerthemetree} + +%\setbeameroption{show notes on second screen} + +\def\lang{fr} +\def\dirroot{tex} +\def\dirschema{eps} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../sty/ppt-style} + +%presentation-style list language (Change this file to add language) +\langFRtrue + +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\begin{document} + +%Slide de Titre +\frame{\titlepage} + +\Contents + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{\dirroot/root} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/sty/header.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/sty/header.sty (revision 91) @@ -0,0 +1,23 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{2008/07/11} +%\def\review{\number\day/\number\month/\number\year\xspace} + +\iflangFR + \title{MORPHEO \\ Spécification de la Microarchitecture} + \author + {Mathieu Rosière\newline + encadrement :\newline + Nathalie Drach-Temam\newline + Jean-Lou Desbarbieux\newline + Franck Wajsbürt} + \institute{Département ALSOC - Laboratoire d'informatique de Paris VI - France} +\else % Others language + \title{} + \author{} + \institute{} +\fi + +\date{\review} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/tex/root.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/doc/presentation-morpheo-microarchitecture/tex/root.tex (revision 91) @@ -0,0 +1,349 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\section{Introduction} +\ContentsCurrent + +\subsection{Motivations} +\slidetitle{Cadre de la thèse} + { + \begin{itemize} + \item {\it Cadre :}\newline + Collaboration avec Bull sur le projet PFC\newline + (Plate-forme de confiance totale) + \item {\it Notre contribution :}\newline + Réalisation d'un générateur de processeur ouvert. + \end{itemize} + } + { + } + +\subsection{Cahier des charges} +\slidetitle{Besoins : Cahier des charges} + { + Il faut une architecture : + \begin{description} + \item [Ouverte :] Évite les fonctionnalités cachées. + \item [Pérenne :] Évite les problèmes d'approvisionnements. + \item [Paramétrable :] S'adapte aux critères de l'application. + \item [Performante :] Applications nécessitant de la puissance de calculs. + \end{description} + } + { +% Concevoir un cpu pour PFC : +% +% ouverte, pérenne, paramétrable, performante. +% +% Applications cibles : cryptographique. + } + +%\subsection{Architecture Performante} +\slidetitle{Architecture Performante} + { + \begin{center} + {\it Exécution de plusieurs instructions simultanément} + \end{center} + + Exploitation de toutes les formes de parallélisme. + + \begin{description} + \item[ILP :] Instruction Level Parallelism + \item[TLP :] Thread Level Parallelism + \item[DLP :] Data Level Parallelism + \end{description} + } + { + } + +\section{Micro Architecture} +\ContentsCurrent + +\subsection{Vue d'ensemble} +\slidetitle{Vue d'ensemble} + { +% 3 Parties :\\ + \begin{description} + \item [Front end :] Chargement de paquets d'instructions, décodage + \item [Out Of Order Engine :] Renommage, Lancement des instructions, Maintien dans l'ordre du programme + \item [Execute Loop :] Lecture des opérandes, Execution, Ecritures des résultats + \end{description} + + \printgraph{MORPHEO_micro_architecture-part}{0.7} + } + { + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-overview}{0.48} + } + { + } + +\subsection{Front End} +\slidetitle{Front End} + { + \printgraph{MORPHEO_micro_architecture-front_end}{0.75} + } + { + } + +\slidetitle{Fetch unit} + { + \begin{description} + \item[Address\_management :] Gère le programme counter. + \item[Ifetch\_queue :] FIFO (classique) récupérant les réponses provenant du cache. + \end{description} + \printgraph{MORPHEO_micro_architecture-front_end-fetch_unit}{0.75} + } + { + } + +\slidetitle{Prediction Unit} + { + \printgraph{MORPHEO_micro_architecture-front_end-prediction_unit}{0.6} + } + { + } + +\slidetitle{Decod Unit} + { + \begin{description} + \item[Decod :] Décodage - branchement et évènement (exception, instructions spéciales) + \item[Decod\_queue :] FIFO classique, Supprime les instructions incorrects + \end{description} + \printgraph{MORPHEO_micro_architecture-front_end-decod_unit}{0.8} + } + { + } + +%\slidetitle{Context State} +% { +% \printgraph{MORPHEO_micro_architecture-front_end-context_state}{0.75} +% } +% { +% } + +\subsection{Out Of Order Engine} +\slidetitle{Out Of Order Engine} + { + \printgraph{MORPHEO_micro_architecture-out_of_order_engine}{0.8} + } + { + } + +\slidetitle{Rename Unit} + { + \printgraph{MORPHEO_micro_architecture-out_of_order_engine-rename_unit}{0.65} + } + { + } + +\slidetitle{Issue Queue} + { + Route vers les ports de sorties les instructions. + + \printgraph{MORPHEO_micro_architecture-out_of_order_engine-issue_queue-1}{0.75} + } + { + } + +\slidetitle{Reexecute Unit + SPR} + { + Des instructions doivent être réinjectés dans la boucle d'execution + \begin{itemize} + \item Accès aux registres spéciaux + \item Store en tête du Re Order Buffer + \end{itemize} + \printgraph{MORPHEO_micro_architecture-out_of_order_engine-reexecute_unit}{0.75} + } + { + } + +\slidetitle{Commit Unit} + { + \printgraph{MORPHEO_micro_architecture-out_of_order_engine-commit_unit}{0.75} + } + { + } + +\subsection{Execute Loop} +\slidetitle{Execute Loop} + { + \printgraph{MORPHEO_micro_architecture-execute_loop}{0.75} + } + { + } + +\slidetitle{Read unit} + { + \begin{description} + \item[Read\_queue :] FIFO classique, Lecture des opérandes depuis le banc de registres. + \item[Reservation\_station :] Attente de la disponibilité de toutes les opérandes. Lancement des instructions prêtes. + \end{description} + + \printgraph{MORPHEO_micro_architecture-execute_loop-read_unit}{0.75} + } + { + } + +%\slidetitle{Functionnal Unit} +% { +% \printgraph{MORPHEO_micro_architecture-execute_loop-functionnal_unit}{0.75} +% } +% { +% } +% +\slidetitle{Load Store Unit} + { + \begin{description} + \item[speculative\_access\_queue :] FIFO classique. Accès au cache + \item[load\_queue :] Attente des réponses puis vérification des dépendances RAW. + \item[store\_queue :] File stockant les écritures. Attente d'être en tête du ROB. + \end{description} + + \printgraph{MORPHEO_micro_architecture-execute_loop-load_store_unit}{0.8} + } + { + } + +\slidetitle{Write Unit} + { + \begin{description} + \item[Write\_queue :] FIFO classique, Ecriture des résultats vers le banc de registres. + \item[Execute\_queue :] (Optionnel) FIFO classique + \end{description} + + \printgraph{MORPHEO_micro_architecture-execute_loop-write_unit}{0.75} + } + { + } + +\slidetitle{Register File} + { + \begin{minipage}{0.45\textwidth} + \printgraph{MORPHEO_micro_architecture-execute_loop-register_unit}{0.75} + \end{minipage} + \begin{minipage}{0.45\textwidth} + \begin{description} + \item[RegisterFile :] Multi bancs + \item[Status List :] Registre de validité (1 bit) + \end{description} + \end{minipage} + } + { + } + +\section{Exemple d'instance} +\ContentsCurrent + +\slide + { + \printgraph{MORPHEO_micro_architecture-overview}{0.48} + } + { + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex01}{0.48} + } + { + Hypothse de dpart + + SMT 2 + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex02}{0.48} + } + { + contexte x4 prdicteur ddi + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex03}{0.48} + } + { + Select ... + } + +\slide + { + \printgraph{MORPHEO_micro_architecture-ex04}{0.48} + } + { + possibilit de CMP + } + +%\section{Custom Unit} +%\ContentsCurrent +% +%\subsection{Spécification} +%\slidetitle{Spécification} +% { +% } +% { +% } +% +%\subsection{Interface} +%\slidetitle{Interface - Decod} +% { +% } +% { +% } +% +%\slidetitle{Interface - Functionnal Unit} +% { +% } +% { +% } +% +%\subsection{Exemple} +%\slidetitle{Exemple : Pseudo Crypto unit} +% { +% } +% { +% } +% +%\slidetitle{Exemple : Random unit} +% { +% } +% { +% } +% +%\section{Optimisation future} +%\ContentsCurrent +% +%\slidetitle{Différente algorithme de priorité / équilibrage de charge} +% { +% } +% { +% } +% +%\slidetitle{Différente implémentation de la Load Store Queue} +% { +% \begin{description} +% \item[NO\_SPECULATIVE\_LOAD : ] each load wait all previous store before the data cache access +% \item[SPECULATIVE\_LOAD\_ACCESS : ] each load wait all previous store before the commiting +% \item[SPECULATIVE\_LOAD\_COMMIT : ] each load commit the result before the end of dependence's check +% \item[SPECULATIVE\_LOAD\_BYPASS : ] each load bypass the result before the end of dependence's check +% \end{description} +% } +% { +% } +% +%\slidetitle{MAC Unit - Custom Unit} +% { +% } +% { +% } +% +%\slidetitle{ICache Management} +% { +% } +% { +% } Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/GENERAL_Issue_slots_waste.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/GENERAL_Issue_slots_waste.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/GENERAL_Issue_slots_waste.fig (revision 91) @@ -0,0 +1,169 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 6450 4800 7650 5100 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 4800 7650 4800 7650 5100 6450 5100 6450 4800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 4800 6750 5100 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 5100 7050 4800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 4800 7350 5100 +-6 +6 6450 5250 7650 5550 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 5250 7650 5250 7650 5550 6450 5550 6450 5250 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5250 6750 5550 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 5550 7050 5250 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 5250 7350 5550 +-6 +6 6450 5700 7650 6000 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 5700 7650 5700 7650 6000 6450 6000 6450 5700 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5700 6750 6000 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 6000 7050 5700 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 5700 7350 6000 +-6 +6 6450 6150 7650 6450 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 6150 7650 6150 7650 6450 6450 6450 6450 6150 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 6150 6750 6450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 6450 7050 6150 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 6150 7350 6450 +-6 +6 6450 6600 7650 6900 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 6600 7650 6600 7650 6900 6450 6900 6450 6600 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 6600 6750 6900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 6900 7050 6600 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 6600 7350 6900 +-6 +6 6450 7050 7650 7350 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 7050 7650 7050 7650 7350 6450 7350 6450 7050 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 7050 6750 7350 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 7350 7050 7050 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 7050 7350 7350 +-6 +6 6450 4800 6750 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 4800 6750 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 4800 6450 5100 +-6 +6 6750 4800 7050 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 4800 7050 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 4800 6750 5100 +-6 +6 7050 4800 7350 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 4800 7350 5100 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 4800 7050 5100 +-6 +6 6750 5250 7050 5550 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5250 7050 5550 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 5250 6750 5550 +-6 +6 6450 5250 6750 5550 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 5250 6750 5550 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5250 6450 5550 +-6 +6 6450 6150 6750 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 6150 6750 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 6150 6450 6450 +-6 +6 6750 6150 7050 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 6150 7050 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 6150 6750 6450 +-6 +6 7050 6150 7350 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7050 6150 7350 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 6150 7050 6450 +-6 +6 7350 6150 7650 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7350 6150 7650 6450 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 7650 6150 7350 6450 +-6 +6 6450 7050 6750 7350 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6450 7050 6750 7350 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 7050 6450 7350 +-6 +6 8250 4350 9300 5100 +6 8250 4350 8550 4650 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 8250 4350 8550 4650 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 2 + 8550 4350 8250 4650 +-6 +2 2 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 5 + 8250 4350 8550 4350 8550 4650 8250 4650 8250 4350 +2 2 0 1 0 1 50 -1 -1 0.000 0 0 -1 0 0 5 + 8250 4800 8550 4800 8550 5100 8250 5100 8250 4800 +4 0 0 50 -1 0 8 0.0000 0 105 555 8700 4950 Empty slot\001 +4 0 0 50 -1 0 8 0.0000 0 75 450 8700 4500 Full slot\001 +-6 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 6450 4500 7650 4500 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6150 4800 6150 7350 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 6300 7800 5850 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 6300 7800 6750 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 5850 7800 4950 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 5850 7800 5400 +2 1 0 1 0 1 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 5850 7800 7200 +4 1 0 50 -1 0 8 0.0000 0 75 555 7050 4350 Issue Slots\001 +4 1 0 50 -1 0 8 1.5708 0 105 360 6000 6075 Cycles\001 +4 0 0 50 -1 0 8 0.0000 0 90 855 8250 5850 Horizontal waste\001 +4 0 0 50 -1 0 8 0.0000 0 90 735 8250 6300 Vertical waste\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_VHDL_methodologie.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_VHDL_methodologie.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_VHDL_methodologie.fig (revision 91) @@ -0,0 +1,104 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 900 -2400 2100 -2100 +2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 + 2100 -2100 900 -2100 900 -2400 2100 -2400 2100 -2100 +4 1 0 50 -1 2 8 0.0000 0 105 315 1500 -2250 D\351but\001 +-6 +6 825 -1125 2175 -450 +1 1 0 1 0 14 51 -1 20 0.000 1 0.0000 1500 -825 600 225 1500 -825 2100 -825 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 -450 ok\001 +4 1 0 50 -1 2 8 0.0000 0 75 240 1500 -825 Test\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 2025 -975 ko\001 +-6 +6 1650 450 2850 900 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 2850 900 1650 900 1650 450 2850 450 2850 900 +4 1 0 50 -1 2 8 0.0000 0 75 375 2250 825 VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 90 615 2250 600 TestBench \001 +-6 +1 1 0 1 0 14 51 -1 20 0.000 1 0.0000 1500 -75 600 225 1500 -75 2100 -300 +1 1 0 1 0 14 51 -1 20 0.000 1 0.0000 1501 1423 600 225 1501 1423 2101 1198 +1 1 0 1 0 14 51 -1 20 0.000 1 0.0000 1500 2175 600 225 1500 2175 2100 1950 +1 1 0 1 0 14 60 -1 10 0.000 1 0.0000 1575 1425 600 225 1575 1425 2175 1200 +1 1 0 1 0 14 60 -1 10 0.000 1 0.0000 1575 2175 600 225 1575 2175 2175 1950 +1 1 0 1 0 14 60 -1 10 0.000 1 0.0000 1575 -75 600 225 1575 -75 2175 -300 +1 1 0 1 0 14 60 -1 10 0.000 1 0.0000 1575 -825 600 225 1575 -825 2175 -1050 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 150 2250 450 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 750 900 1350 1200 +2 1 0 1 0 7 50 -1 20 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 900 1650 1200 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 900 2175 -150 2175 -150 -1950 1200 -1950 1200 -1800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 2100 -825 2400 -825 2400 -1950 1800 -1950 1800 -1800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -2100 1500 -1800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -1350 1500 -1050 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 2100 -1350 900 -1350 900 -1800 2100 -1800 2100 -1350 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 -600 1500 -300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 900 -75 -150 -75 +2 1 0 1 0 7 50 -1 20 0.000 0 0 7 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 150 750 450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 900 1425 0 1425 0 300 450 300 450 450 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 1650 1500 1950 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1500 2400 1500 2700 +2 4 0 1 0 30 51 -1 20 0.000 0 0 7 0 0 5 + 2100 3000 900 3000 900 2700 2100 2700 2100 3000 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 1350 900 150 900 150 450 1350 450 1350 900 +2 4 0 1 0 30 60 -1 10 0.000 0 0 7 0 0 5 + 2175 -2025 2175 -2325 975 -2325 975 -2025 2175 -2025 +2 4 0 1 0 30 60 -1 10 0.000 0 0 7 0 0 5 + 2175 3075 2175 2775 975 2775 975 3075 2175 3075 +2 4 0 1 0 11 60 -1 10 0.000 0 0 7 0 0 5 + 2925 975 2925 525 1725 525 1725 975 2925 975 +2 4 0 1 0 11 60 -1 10 0.000 0 0 7 0 0 5 + 1425 975 1425 525 225 525 225 975 1425 975 +2 4 0 1 0 11 60 -1 10 0.000 0 0 7 0 0 5 + 2175 -1275 2175 -1725 975 -1725 975 -1275 2175 -1275 +4 1 0 50 -1 2 8 0.0000 0 105 465 1500 -1425 SystemC\001 +4 1 0 50 -1 2 8 0.0000 0 105 450 1500 -1650 Mod\350le \001 +4 1 0 50 -1 2 8 0.0000 0 90 600 1500 -150 Contrainte\001 +4 1 0 50 -1 2 8 0.0000 0 90 675 1500 75 Performance\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 900 -225 ko\001 +4 1 0 50 -1 2 8 0.0000 0 75 240 1500 1425 Test\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 900 1350 ko\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 1800 ok\001 +4 0 0 51 -1 0 8 0.0000 0 75 120 1575 2550 ok\001 +4 2 0 51 -1 0 8 0.0000 0 75 120 900 2100 ko\001 +4 1 0 50 -1 2 8 0.0000 0 90 390 1500 2325 Surface\001 +4 1 0 50 -1 2 8 0.0000 0 90 600 1500 2100 Contrainte\001 +4 1 0 50 -1 2 8 0.0000 0 90 195 1500 2850 Fin\001 +4 1 0 50 -1 2 8 0.0000 0 75 375 750 825 VHDL\001 +4 1 0 50 -1 2 8 0.0000 0 105 450 750 600 Mod\350le \001 +4 1 0 51 -1 0 8 0.0000 0 75 120 1500 300 ok\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex01.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex01.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex01.fig (revision 91) @@ -0,0 +1,179 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 4770 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 +-6 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 5130 2790 5130 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 5400 12510 5400 12510 2295 1710 2295 1710 5400 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex02.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex02.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex02.fig (revision 91) @@ -0,0 +1,227 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +6 4770 3285 5490 3735 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3735 4770 3735 4770 3285 5490 3285 5490 3735 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3555 decod\001 +-6 +6 4770 2835 5490 3285 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3285 4770 3285 4770 2835 5490 2835 5490 3285 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3015 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3195 state\001 +-6 +6 3825 2655 4635 3105 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3105 3870 3105 3870 2655 4590 2655 4590 3105 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 2925 predictor\001 +-6 +6 2970 3285 3690 3735 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 3735 2970 3735 2970 3285 3690 3285 3690 3735 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3555 fetch\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2340 4230 2340 4230 2655 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3105 4410 3465 4770 3465 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3510 2610 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3105 4050 3465 3690 3465 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2475 2790 2475 2790 3915 5580 3915 5580 2475 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3555 4770 3555 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 3645 3060 3645 3060 3195 3780 3195 3780 3645 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3105 3960 3375 3780 3375 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 3645 4770 3645 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 4725 4410 4365 4770 4365 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 4320 2610 4005 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 4725 4050 4365 3690 4365 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 5355 2790 5355 2790 3915 5580 3915 5580 5355 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 4275 4770 4275 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4185 3060 4185 3060 4635 3780 4635 3780 4185 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 4725 3960 4455 3780 4455 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4185 4770 4185 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3510 5850 3780 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 4320 5843 4060 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4230 2655 4230 4725 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5130 2835 5130 4545 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 6030 2790 5130 2340 5130 2835 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 5535 12510 5535 12510 2295 1710 2295 1710 5535 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4545 4770 4545 4770 4995 5490 4995 5490 4545 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4095 4770 4095 4770 4545 5490 4545 5490 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 4725 3870 4725 3870 5175 4590 5175 4590 4725 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4095 2970 4095 2970 4545 3690 4545 3690 4095 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2430 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 4365 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 4365 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 4725 state\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 4860 context\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 4995 predictor\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex03.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex03.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex03.fig (revision 91) @@ -0,0 +1,253 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +6 5760 2610 7470 4320 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 3960 rename\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +-6 +6 2790 2880 5580 4320 +6 4770 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 3960 decod\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 +-6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +-6 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +-6 +6 1890 6300 2610 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 6660 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 6480 icache\001 +-6 +6 9810 3510 10530 3960 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3960 9810 3960 9810 3510 10530 3510 10530 3960 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 3870 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 3690 dcache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 6030 2790 5130 2790 5130 3240 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 6525 7650 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 6525 5850 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 7425 6930 7650 6030 7650 5130 7650 5130 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 7650 4230 7650 4230 7380 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 6930 4410 6570 4770 6570 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 6525 2610 6525 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 6930 4050 6570 3690 6570 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 7560 2790 7560 2790 6120 5580 6120 5580 7560 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 6480 4770 6480 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 6390 3060 6390 3060 6840 3780 6840 3780 6390 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 6930 3960 6660 3780 6660 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 6390 4770 6390 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6300 4770 6300 4770 6750 5490 6750 5490 6300 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6930 3870 6930 3870 7380 4590 7380 4590 6930 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 6300 2970 6300 2970 6750 3690 6750 3690 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 7650 6030 6750 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 6750 6390 7200 6570 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 6975 6930 6525 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 6120 5760 6120 5760 7830 7470 7830 7470 6120 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 6975 6570 6975 6570 7425 7290 7425 7290 6975 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 6300 5850 6300 5850 6750 6570 6750 6570 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 4005 10170 4500 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 4995 12150 4995 12150 4320 8010 4320 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.01 120.01 + 11430 5220 11430 5580 8820 5580 8820 5220 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 8640 5760 8640 5220 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 11790 5220 11790 5760 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 6120 11970 5760 8370 5760 8370 6120 11970 6120 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 4590 11070 5400 10710 5400 10710 4590 11070 4590 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 11070 4995 11250 4995 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 9090 4995 9270 4995 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 9630 5265 9810 5265 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 10530 5265 10710 5265 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 10530 4725 10710 4725 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.01 120.01 + 9630 4725 9810 4725 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 5490 9810 5490 9810 5040 10530 5040 10530 5490 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4950 9810 4950 9810 4500 10530 4500 10530 4950 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 5220 8370 5220 8370 4770 9090 4770 9090 5220 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5220 11250 5220 11250 4770 11970 4770 11970 5220 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 4140 12330 4140 12330 6300 8190 6300 8190 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 4995 8370 4995 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 4590 9630 5400 9270 5400 9270 4590 9630 4590 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 5220 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 6570 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 135 450 5130 6570 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 7200 predictor\001 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 7245 commit\001 +4 1 0 50 -1 -1 12 0.0000 4 90 555 6210 6525 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 6930 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 7065 state\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 4050 Execution Loop\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 4995 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 4995 select\001 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 5040 read\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 4770 memory\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 5310 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 5040 write\001 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 5985 register\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex04.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex04.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-ex04.fig (revision 91) @@ -0,0 +1,327 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 165 345 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 150 630 10170 2655 dcache\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 165 345 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 150 570 2250 3870 icache\001 +-6 +6 8190 5220 12330 7335 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 6300 11430 5940 8820 5940 8820 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 5760 8640 6300 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 6300 11790 5760 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5400 11970 5760 8370 5760 8370 5400 11970 5400 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 7335 12330 7335 12330 5220 8190 5220 8190 7335 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 6930 11070 6120 10710 6120 10710 6930 11070 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 6525 11250 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 6525 9270 6525 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 6930 9630 6120 9270 6120 9270 6930 9630 6930 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6255 9810 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6255 10710 6255 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 6795 10710 6795 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 6795 9810 6795 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6030 9810 6030 9810 6480 10530 6480 10530 6030 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 6570 9810 6570 9810 7020 10530 7020 10530 6570 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 6300 8370 6300 8370 6750 9090 6750 9090 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 6300 11250 6300 11250 6750 11970 6750 11970 6300 +4 1 0 50 -1 -1 12 0.0000 4 195 660 10170 5625 register\001 +4 1 0 50 -1 -1 12 0.0000 4 150 390 8730 6570 read\001 +4 1 0 50 -1 -1 12 0.0000 4 120 690 10170 6300 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 150 720 10170 6840 memory\001 +4 1 0 50 -1 -1 12 0.0000 4 150 450 11610 6570 write\001 +4 1 0 50 -1 -1 12 1.5708 4 150 510 10935 6525 select\001 +4 1 0 50 -1 -1 12 1.5708 4 150 510 9495 6525 select\001 +-6 +6 8190 3105 12330 5220 +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 390 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 450 11610 3960 write\001 +-6 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +4 1 0 50 -1 -1 12 0.0000 4 195 660 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 150 510 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 150 510 9495 3915 select\001 +4 1 0 50 -1 -1 12 0.0000 4 120 690 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 150 720 10170 3690 memory\001 +-6 +6 9810 7515 10530 7965 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 7965 9810 7965 9810 7515 10530 7515 10530 7965 +4 1 0 50 -1 -1 12 0.0000 4 165 345 10170 7875 port\001 +4 1 0 50 -1 -1 12 0.0000 4 150 630 10170 7695 dcache\001 +-6 +6 5760 2610 7470 4320 +6 5850 3690 6570 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +4 1 0 50 -1 -1 12 0.0000 4 105 660 6210 3960 rename\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 150 645 6930 3285 commit\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +-6 +6 2790 2880 5580 4320 +6 4770 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 525 5130 3960 decod\001 +-6 +6 4770 3240 5490 3690 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 120 645 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 120 420 5130 3600 state\001 +-6 +6 3825 3060 4635 3510 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +4 1 0 50 -1 -1 12 0.0000 4 195 780 4230 3330 predictor\001 +-6 +6 2970 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 435 3330 3960 fetch\001 +-6 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3870 4770 3870 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3870 3690 3870 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 3960 4770 3960 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 4050 3060 4050 3060 3600 3780 3600 3780 4050 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 3510 3960 3780 3780 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +-6 +6 1890 6300 2610 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 6750 1890 6750 1890 6300 2610 6300 2610 6750 +4 1 0 50 -1 -1 12 0.0000 4 165 345 2250 6660 port\001 +4 1 0 50 -1 -1 12 0.0000 4 150 570 2250 6480 icache\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 6030 2790 5130 2790 5130 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 7020 10170 7515 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 8145 12510 8145 12510 2295 1710 2295 1710 8145 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 7560 7650 7560 7650 2880 8010 2880 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6525 8370 6525 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 6525 12150 6525 12150 7200 8010 7200 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 6525 7650 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 6525 5850 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 6930 7425 6930 7650 6030 7650 5130 7650 5130 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 7650 4230 7650 4230 7380 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 6930 4410 6570 4770 6570 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 6525 2610 6525 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 6930 4050 6570 3690 6570 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 7560 2790 7560 2790 6120 5580 6120 5580 7560 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3780 6480 4770 6480 +2 4 0 1 0 11 51 -1 20 0.000 0 0 7 0 0 5 + 3780 6390 3060 6390 3060 6840 3780 6840 3780 6390 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 3960 6930 3960 6660 3780 6660 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 6390 4770 6390 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6750 4770 6750 4770 7200 5490 7200 5490 6750 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 6300 4770 6300 4770 6750 5490 6750 5490 6300 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6930 3870 6930 3870 7380 4590 7380 4590 6930 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 6300 2970 6300 2970 6750 3690 6750 3690 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 7650 6030 6750 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 6750 6390 7200 6570 7200 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 6975 6930 6525 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 6120 5760 6120 5760 7830 7470 7830 7470 6120 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 6975 6570 6975 6570 7425 7290 7425 7290 6975 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 6300 5850 6300 5850 6750 6570 6750 6570 6300 +4 0 1 50 -1 -1 12 0.0000 4 150 435 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 195 1770 5760 2520 Out Of Order Engine\001 +4 0 1 50 -1 -1 12 0.0000 4 195 1365 8190 3015 Execution Loop\001 +4 1 0 50 -1 -1 12 1.5708 4 150 510 7875 5220 select\001 +4 0 1 50 -1 -1 12 0.0000 4 150 855 2790 2790 Front End\001 +4 1 0 50 -1 -1 12 0.0000 4 150 435 3330 6570 fetch\001 +4 1 0 50 -1 -1 12 0.0000 4 150 525 5130 6570 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 195 780 4230 7200 predictor\001 +4 1 0 50 -1 -1 12 0.0000 4 150 645 6930 7245 commit\001 +4 1 0 50 -1 -1 12 0.0000 4 105 660 6210 6525 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 120 645 5130 6930 context\001 +4 1 0 50 -1 -1 12 0.0000 4 120 420 5130 7065 state\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-functionnal_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-functionnal_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-functionnal_unit.fig (revision 91) @@ -0,0 +1,135 @@ +#FIG 3.2 Produced by xfig version 3.2.5-alpha5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 7200 5895 10080 6705 +6 7560 6075 8280 6525 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 8280 6525 7560 6525 7560 6075 8280 6075 8280 6525 +4 1 0 50 -1 -1 10 0.0000 4 105 255 7920 6255 read\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 7920 6435 queue\001 +-6 +6 8640 6075 9360 6525 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9360 6525 8640 6525 8640 6075 9360 6075 9360 6525 +4 1 0 50 -1 -1 10 0.0000 4 105 690 9000 6255 reservation\001 +4 1 0 50 -1 -1 10 0.0000 4 105 435 9000 6435 station\001 +-6 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 10080 5895 10080 6705 9720 6705 9720 5895 10080 5895 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9360 6300 9720 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8280 6300 8640 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7200 6300 7560 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 1 + 7200 6300 +4 1 0 50 -1 -1 10 1.5708 4 105 360 9945 6300 select\001 +4 0 0 50 -1 -1 10 0.0000 4 75 435 7245 6030 rename\001 +-6 +6 10260 5760 10980 6210 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10980 6210 10260 6210 10260 5760 10980 5760 10980 6210 +4 1 0 50 -1 -1 10 0.0000 4 105 510 10620 6030 memory\001 +-6 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10080 6615 10260 6615 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 11070 6300 10170 6300 10170 6930 11070 6930 11070 6300 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 10170 6300 11070 6300 11070 5670 10170 5670 10170 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10980 5985 11160 5985 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10980 6615 11160 6615 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11520 5580 11520 7020 11160 7020 11160 5580 11520 5580 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11520 6300 11880 6300 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 13860 6705 11700 6705 11700 5895 13860 5895 13860 6705 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 13680 6300 14040 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 12600 6300 12960 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 13680 6525 12960 6525 12960 6075 13680 6075 13680 6525 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 12600 6525 11880 6525 11880 6075 12600 6075 12600 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 12780 6300 12780 7380 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 12780 7110 9000 7110 9000 6525 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 12240 6075 12240 5400 8820 5400 8820 6075 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10890 5445 10890 5760 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 10350 5760 10350 5490 9180 5490 9180 6075 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 10800 5760 10800 5490 10440 5490 10440 5760 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10620 5760 10620 5130 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 13680 7740 13680 7380 7560 7380 7560 7740 13680 7740 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 13680 8280 13680 7920 7560 7920 7560 8280 13680 8280 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 7380 7200 13860 7200 13860 8460 7380 8460 7380 7200 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 12780 7335 12780 7920 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7560 8100 7200 8100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8460 7380 8460 6300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8460 7380 8460 7920 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10080 5985 10260 5985 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 9540 6705 7380 6705 7380 5895 9540 5895 9540 6705 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10980 6840 10260 6840 10260 6390 10980 6390 10980 6840 +4 1 0 50 -1 -1 10 1.5708 4 105 360 11385 6300 select\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 12240 6435 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 12240 6255 write\001 +4 1 0 50 -1 -1 10 0.0000 4 90 465 13320 6255 execute\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 13320 6435 queue\001 +4 0 0 50 -1 -1 10 0.0000 4 150 405 8820 5355 bypass\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 10620 5085 Dcache\001 +4 2 0 50 -1 -1 10 0.0000 4 90 465 13995 6660 execute\001 +4 1 0 50 -1 -1 10 0.0000 4 135 480 10620 7605 register\001 +4 1 0 50 -1 -1 10 0.0000 4 105 630 10620 8145 status list\001 +4 0 0 50 -1 -1 10 0.0000 4 150 855 7290 8415 register_state\001 +4 1 0 50 -1 -1 10 0.0000 4 90 465 10620 6660 execute\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-load_store_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-load_store_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-load_store_unit.fig (revision 91) @@ -0,0 +1,126 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 1710 1620 2430 1980 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4 + 1710 1620 2430 1620 2430 1980 1710 1980 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 2250 1980 2250 1620 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 2070 1980 2070 1620 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 1890 1980 1890 1620 +-6 +6 1710 900 2430 1260 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4 + 1710 900 2430 900 2430 1260 1710 1260 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 2250 1260 2250 900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 2070 1260 2070 900 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 1890 1260 1890 900 +-6 +6 3510 1620 4230 1980 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 4 + 3510 1620 4230 1620 4230 1980 3510 1980 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4050 1980 4050 1620 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 3870 1980 3870 1620 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 3690 1980 3690 1620 +-6 +6 3150 1260 3330 1620 +2 2 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 3330 1620 3150 1620 3150 1260 3330 1260 3330 1620 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 3 + 3330 1620 3150 1440 3330 1260 +-6 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 2340 990 2610 990 2610 720 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 2340 1890 2790 1890 2790 720 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 2970 360 2970 1170 2340 1170 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 2970 1170 2970 1710 3510 1710 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2790 1890 3510 1890 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1350 1440 1710 1080 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1350 1440 1710 1800 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 1350 1440 990 1440 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 2520 720 2880 720 2880 540 2520 540 2520 720 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 2520 720 2700 540 2880 720 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2700 540 2700 360 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 2340 1080 4230 1080 4590 1440 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 4230 1800 4590 1440 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4590 1440 4950 1440 +2 4 0 1 0 17 52 -1 10 4.000 0 0 7 0 0 5 + 2565 2115 2565 1575 1665 1575 1665 2115 2565 2115 +2 4 0 1 0 6 51 -1 20 4.000 0 0 7 0 0 5 + 1620 810 1620 1350 2520 1350 2520 810 1620 810 +2 4 0 1 0 6 52 -1 10 4.000 0 0 7 0 0 5 + 1665 855 1665 1395 2565 1395 2565 855 1665 855 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3150 1440 1890 1440 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4050 1440 3330 1440 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3600 1800 3510 1440 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3690 1440 3780 1800 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 3960 1800 3870 1440 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2 + 4050 1440 4140 1800 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 1440 2160 1170 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2070 1440 1980 1170 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1890 1440 1800 1170 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2430 1440 2340 1170 +2 4 0 1 0 17 51 -1 20 0.000 0 0 7 0 0 5 + 2520 2070 1620 2070 1620 1530 2520 1530 2520 2070 +2 4 0 1 0 14 51 -1 20 0.000 0 0 7 0 0 5 + 4320 2070 3060 2070 3060 1170 4320 1170 4320 2070 +2 4 0 1 0 14 52 -1 10 0.000 0 0 7 0 0 5 + 4365 2115 3105 2115 3105 1215 4365 1215 4365 2115 +4 2 0 50 -1 0 8 0.0000 0 120 555 900 1440 memory_in\001 +4 0 0 50 -1 0 8 0.0000 0 105 630 5040 1440 memory_out\001 +4 0 0 50 -1 0 8 0.0000 0 105 555 2970 270 dcache_rsp\001 +4 2 0 50 -1 0 8 0.0000 0 105 570 2700 270 dcache_req\001 +4 1 0 50 -1 2 10 0.0000 0 150 795 2070 720 store_queue\001 +4 1 0 50 -1 2 10 0.0000 0 165 1680 2070 2295 speculative_access_queue\001 +4 1 0 50 -1 2 10 0.0000 0 150 750 3870 2295 load_queue\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-read_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-read_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-read_unit.fig (revision 91) @@ -0,0 +1,136 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +0 32 #00be00 +0 33 #0875ef +6 8730 4500 9810 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4 + 8730 4500 9810 4500 9810 5040 8730 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9630 4500 9630 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9450 4500 9450 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9270 4500 9270 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9090 4500 9090 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 8910 4500 8910 5040 +-6 +6 6750 4500 7830 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4 + 6750 4500 7830 4500 7830 5040 6750 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7650 4500 7650 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7470 4500 7470 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7290 4500 7290 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7110 4500 7110 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 6930 4500 6930 5040 +-6 +6 10890 4140 11700 5355 +4 0 0 50 -1 0 8 0.0000 0 120 495 10890 5130 gpr_write\001 +4 0 0 50 -1 0 8 0.0000 0 120 480 10890 5310 spr_write\001 +4 0 0 50 -1 0 8 0.0000 0 105 780 10890 4410 bypass_memory\001 +4 0 0 50 -1 0 8 0.0000 0 120 645 10890 4230 bypass_write\001 +4 0 0 50 -1 0 8 0.0000 0 105 690 10890 4770 read_unit_out\001 +-6 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 8910 5221 21 21 8910 5221 8924 5236 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9090 5220 21 21 9090 5220 9104 5235 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9270 5220 21 21 9270 5220 9284 5235 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9450 5220 21 21 9450 5220 9464 5235 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9630 5220 21 21 9630 5220 9644 5235 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9810 5220 21 21 9810 5220 9824 5235 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9090 4320 21 21 9090 4320 9104 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9270 4320 21 21 9270 4320 9284 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9450 4320 21 21 9450 4320 9464 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9630 4320 21 21 9630 4320 9644 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9810 4320 21 21 9810 4320 9824 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9000 4770 21 21 9000 4770 9014 4785 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9180 4770 21 21 9180 4770 9194 4785 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9360 4770 21 21 9360 4770 9374 4785 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9540 4770 21 21 9540 4770 9554 4785 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 9720 4770 21 21 9720 4770 9734 4785 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7830 4770 8730 4770 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 10800 5220 9810 5220 9720 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9810 5220 9630 5220 9540 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9630 5220 9450 5220 9360 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9450 5220 9270 5220 9180 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9270 5220 9090 5220 9000 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9090 5220 8910 5220 8820 4860 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 8910 5220 7830 5220 7740 4860 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9810 4320 9630 4320 9540 4680 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9630 4320 9450 4320 9360 4680 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9270 4320 9090 4320 9000 4680 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9090 4320 8910 4320 8820 4680 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9450 4320 9270 4320 9180 4680 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8820 4770 10080 4770 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10260 4770 10800 4770 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 10800 4320 9810 4320 9720 4680 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 4770 6750 4770 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7695 4860 7695 5760 +2 2 0 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 5 + 10080 5040 10260 5040 10260 4500 10080 4500 10080 5040 +2 1 0 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 3 + 10070 4493 10250 4763 10070 5033 +2 4 0 1 0 14 51 -1 20 4.000 0 0 7 0 0 5 + 6390 4140 6390 5400 8190 5400 8190 4140 6390 4140 +2 4 0 1 0 14 55 -1 10 4.000 0 0 7 0 0 5 + 6435 4185 6435 5445 8235 5445 8235 4185 6435 4185 +2 4 0 1 0 17 51 -1 20 4.000 0 0 7 0 0 5 + 10440 4140 10440 5400 8370 5400 8370 4140 10440 4140 +2 4 0 1 0 17 55 -1 10 4.000 0 0 7 0 0 5 + 10485 4185 10485 5445 8415 5445 8415 4185 10485 4185 +4 1 0 50 -1 2 10 0.0000 0 105 300 7290 3870 read\001 +4 1 0 50 -1 2 10 0.0000 0 105 375 7290 4050 queue\001 +4 1 0 50 -1 2 10 0.0000 0 120 765 9270 3870 reservation\001 +4 1 0 50 -1 2 10 0.0000 0 120 480 9270 4050 station\001 +4 2 0 50 -1 0 8 0.0000 0 105 615 5940 4770 read_unit_in\001 +4 1 0 50 -1 0 8 0.0000 0 105 420 7695 6030 spr_read\001 +4 1 0 50 -1 0 8 0.0000 0 105 435 7695 5850 gpr_read\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-register_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-register_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-register_unit.fig (revision 91) @@ -0,0 +1,115 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 900 180 18 18 900 180 916 189 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 990 270 18 18 990 270 1006 279 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 810 90 18 18 810 90 826 99 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 1620 630 18 18 1620 630 1636 639 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 1530 720 18 18 1530 720 1546 729 +1 3 0 1 0 0 51 -1 20 4.000 1 0.0000 1440 810 18 18 1440 810 1456 819 +2 1 0 1 0 14 51 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 990 270 990 -360 +2 1 0 1 0 0 51 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1080 1620 1080 -360 +2 1 0 1 0 14 51 -1 -1 4.000 0 0 -1 0 0 2 + 1890 270 540 270 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 1890 180 540 180 +2 1 0 1 0 0 51 -1 -1 4.000 0 0 -1 0 0 2 + 1440 -360 1440 810 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 1890 90 540 90 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 1890 630 540 630 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 1890 720 540 720 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 1890 810 540 810 +2 2 0 1 0 14 51 -1 -1 4.000 0 0 -1 0 0 5 + 720 900 0 900 0 0 720 0 720 900 +2 2 0 1 0 14 51 -1 -1 4.000 0 0 -1 0 0 5 + 2430 900 1710 900 1710 0 2430 0 2430 900 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 900 -360 900 1620 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 810 -360 810 1620 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1530 -360 1530 1620 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1620 -360 1620 1620 +2 2 0 1 0 14 51 -1 -1 4.000 0 0 -1 0 0 5 + 1710 1980 720 1980 720 1620 1710 1620 1710 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 810 2340 810 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 900 2340 900 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 990 2340 990 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1350 1350 1350 1620 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1620 2340 1620 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1530 2340 1530 1980 +2 1 0 1 0 0 51 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 1440 2340 1440 1980 +2 4 0 1 0 14 60 -1 20 0.000 0 0 7 0 0 5 + 2610 1080 2610 -180 -180 -180 -180 1080 2610 1080 +2 4 0 1 0 14 61 -1 10 0.000 0 0 7 0 0 5 + 2655 1125 2655 -135 -135 -135 -135 1125 2655 1125 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 1890 2160 1890 1440 540 1440 540 2160 1890 2160 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 1935 2205 1935 1485 585 1485 585 2205 1935 2205 +4 0 0 51 -1 0 6 0.7854 0 75 150 1620 -450 val\001 +4 0 0 51 -1 0 6 0.7854 0 75 360 1530 -450 address\001 +4 0 0 51 -1 0 6 0.7854 0 75 195 1440 -450 data\001 +4 2 0 51 -1 0 6 -0.7854 0 75 150 810 -450 val\001 +4 2 0 51 -1 0 6 -0.7854 0 75 360 900 -450 address\001 +4 2 0 51 -1 0 6 -0.7854 0 75 195 990 -450 data\001 +4 2 0 51 -1 0 6 -0.7854 0 90 405 1080 -450 data_val\001 +4 0 0 51 -1 0 8 0.0000 0 120 765 1350 -810 {gpr/spr}_write\001 +4 2 0 51 -1 0 8 0.0000 0 120 705 1080 -810 {gpr/spr}_read\001 +4 1 0 51 -1 0 8 0.0000 0 75 315 360 540 bank 0\001 +4 1 0 51 -1 0 8 0.0000 0 105 645 360 360 RegisterFile\001 +4 1 0 51 -1 0 8 0.0000 0 75 315 2070 540 bank 1\001 +4 1 0 51 -1 0 8 0.0000 0 105 645 2070 360 RegisterFile\001 +4 1 0 51 -1 0 8 0.0000 0 90 540 1215 1800 Status List\001 +4 2 0 51 -1 0 6 0.7854 0 75 360 900 2430 address\001 +4 2 0 51 -1 0 6 0.7854 0 75 150 810 2430 val\001 +4 2 0 51 -1 0 8 0.0000 0 90 285 990 2790 insert\001 +4 0 0 51 -1 0 8 0.0000 0 90 285 1440 2790 retire\001 +4 1 0 51 -1 0 6 0.0000 0 75 150 1350 1305 "1"\001 +4 0 0 51 -1 0 6 5.4978 0 90 585 1530 2430 old_address\001 +4 0 0 51 -1 0 6 5.4978 0 90 375 1620 2430 old_val\001 +4 1 0 51 -1 0 6 0.0000 0 75 150 1440 2430 "1"\001 +4 1 0 51 -1 0 6 0.0000 0 75 150 990 2430 "0"\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-write_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-write_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop-write_unit.fig (revision 91) @@ -0,0 +1,86 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +0 32 #00be00 +0 33 #0875ef +6 8730 4500 9810 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4 + 8730 4500 9810 4500 9810 5040 8730 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9630 4500 9630 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9450 4500 9450 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9270 4500 9270 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 9090 4500 9090 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 8910 4500 8910 5040 +-6 +6 6750 4500 7830 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 4 + 6750 4500 7830 4500 7830 5040 6750 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7650 4500 7650 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7470 4500 7470 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7290 4500 7290 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 7110 4500 7110 5040 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 0 0 2 + 6930 4500 6930 5040 +-6 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 7470 4320 21 21 7470 4320 7484 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 7110 4320 21 21 7110 4320 7124 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 6930 4320 21 21 6930 4320 6944 4335 +1 3 0 1 0 0 50 -1 20 4.000 1 0.0000 6750 4320 21 21 6750 4320 6764 4335 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7830 4770 8730 4770 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 4770 6750 4770 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7695 4860 7695 5760 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 7740 4635 7650 4320 6030 4320 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 2 + 7560 4635 7470 4320 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 2 + 7380 4635 7290 4320 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 2 + 7200 4635 7110 4320 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 2 + 6840 4635 6750 4320 +2 1 1 1 0 11 50 -1 -1 4.000 0 0 -1 0 0 2 + 7020 4635 6930 4320 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9810 4770 10530 4770 +2 4 0 1 0 17 51 -1 20 4.000 0 0 7 0 0 5 + 10170 4140 10170 5400 8370 5400 8370 4140 10170 4140 +2 4 0 1 0 17 55 -1 10 4.000 0 0 7 0 0 5 + 10215 4185 10215 5445 8415 5445 8415 4185 10215 4185 +2 4 0 1 0 14 51 -1 20 4.000 0 0 7 0 0 5 + 6390 4140 6390 5400 8190 5400 8190 4140 6390 4140 +2 4 0 1 0 14 55 -1 10 4.000 0 0 7 0 0 5 + 6435 4185 6435 5445 8235 5445 8235 4185 6435 4185 +4 1 0 50 -1 2 10 0.0000 0 105 375 7290 4050 queue\001 +4 1 0 50 -1 2 10 0.0000 0 120 330 7290 3870 write\001 +4 1 0 50 -1 2 10 0.0000 0 105 510 9270 3870 execute\001 +4 1 0 50 -1 2 10 0.0000 0 105 375 9270 4050 queue\001 +4 2 0 50 -1 0 8 0.0000 0 105 675 5940 4770 write_unit_in\001 +4 1 0 50 -1 0 8 0.0000 0 120 495 7695 5850 gpr_write\001 +4 1 0 50 -1 0 8 0.0000 0 120 480 7695 6030 spr_write\001 +4 0 0 50 -1 0 8 0.0000 0 105 750 10575 4770 write_unit_out\001 +4 2 0 50 -1 0 8 0.0000 0 120 645 5940 4320 bypass_write\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-execute_loop.fig (revision 91) @@ -0,0 +1,123 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10080 6615 10260 6615 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 11070 6300 10170 6300 10170 6930 11070 6930 11070 6300 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 10170 6300 11070 6300 11070 5670 10170 5670 10170 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10980 5985 11160 5985 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10980 6615 11160 6615 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11520 5580 11520 7020 11160 7020 11160 5580 11520 5580 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11520 6300 11880 6300 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 13860 6705 11700 6705 11700 5895 13860 5895 13860 6705 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 13680 6300 14040 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 12600 6300 12960 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 13680 6525 12960 6525 12960 6075 13680 6075 13680 6525 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 12600 6525 11880 6525 11880 6075 12600 6075 12600 6525 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 12780 6300 12780 7380 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 12780 7110 9000 7110 9000 6525 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 12240 6075 12240 5400 8820 5400 8820 6075 +2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 10440 5760 10440 5490 9180 5490 9180 6075 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10620 5760 10620 5130 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 13680 7740 13680 7380 7560 7380 7560 7740 13680 7740 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 13680 8280 13680 7920 7560 7920 7560 8280 13680 8280 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 7380 7200 13860 7200 13860 8460 7380 8460 7380 7200 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 12780 7335 12780 7920 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7560 8100 7200 8100 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8460 7380 8460 6300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8460 7380 8460 7920 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10080 5985 10260 5985 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 9540 6705 7380 6705 7380 5895 9540 5895 9540 6705 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10980 6840 10260 6840 10260 6390 10980 6390 10980 6840 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10980 6210 10260 6210 10260 5760 10980 5760 10980 6210 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 10080 5895 10080 6705 9720 6705 9720 5895 10080 5895 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9360 6300 9720 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8280 6300 8640 6300 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7200 6300 7560 6300 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 1 + 7200 6300 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 8280 6525 7560 6525 7560 6075 8280 6075 8280 6525 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9360 6525 8640 6525 8640 6075 9360 6075 9360 6525 +4 1 0 50 -1 -1 10 1.5708 4 105 360 11385 6300 select\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 12240 6435 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 13320 6435 queue\001 +4 0 0 50 -1 -1 10 0.0000 4 150 405 8820 5355 bypass\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 10620 5085 Dcache\001 +4 2 0 50 -1 -1 10 0.0000 4 90 465 13995 6660 execute\001 +4 0 0 50 -1 -1 10 0.0000 4 150 855 7290 8415 register_state\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 10620 6750 unit\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 10620 6120 unit\001 +4 1 0 50 -1 -1 10 0.0000 4 135 810 10620 7605 Register File\001 +4 1 0 50 -1 -1 10 0.0000 4 105 675 10620 8145 Status List\001 +4 1 0 50 -1 -1 10 0.0000 4 105 750 10620 6570 Functionnal\001 +4 1 0 50 -1 -1 10 0.0000 4 105 660 10620 5940 Load Store\001 +4 1 0 50 -1 -1 10 0.0000 4 105 375 12240 6255 Write\001 +4 1 0 50 -1 -1 10 0.0000 4 105 495 13320 6255 Execute\001 +4 1 0 50 -1 -1 10 1.5708 4 105 360 9945 6300 select\001 +4 0 0 50 -1 -1 10 0.0000 4 75 435 7245 6030 rename\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 7920 6435 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 105 435 9000 6435 station\001 +4 1 0 50 -1 -1 10 0.0000 4 105 300 7920 6255 Read\001 +4 1 0 50 -1 -1 10 0.0000 4 105 735 9000 6255 Reservation\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-context_state.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-context_state.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-context_state.fig (revision 91) @@ -0,0 +1,132 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3870 5670 4590 6120 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6120 3870 6120 3870 5670 4590 5670 4590 6120 +4 1 0 50 -1 -1 10 0.0000 4 105 525 4230 5850 Context\001 +4 1 0 50 -1 -1 10 0.0000 4 105 315 4230 6090 State\001 +-6 +6 3510 3510 6390 4455 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4455 4950 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4230 4095 4230 3510 3510 3510 3510 4095 4230 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 4095 5310 3510 4590 3510 4590 4095 5310 4095 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6390 4095 5670 4095 5670 3510 6390 3510 6390 4095 +4 1 0 50 -1 -1 10 0.0000 4 105 405 3870 4050 Buffer\001 +4 1 0 50 -1 -1 10 0.0000 4 135 405 3870 3870 Target\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 3870 3690 Branch\001 +4 1 0 50 -1 -1 10 0.0000 4 105 585 4950 3870 Direction\001 +4 1 0 50 -1 -1 10 0.0000 4 105 330 6030 4050 Stack\001 +4 1 0 50 -1 -1 10 0.0000 4 105 510 6075 3870 Address\001 +4 1 0 50 -1 -1 10 0.0000 4 105 435 6030 3690 Return\001 +-6 +6 2610 6480 3330 6930 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 3330 6930 2610 6930 2610 6480 3330 6480 3330 6930 +4 1 0 50 -1 -1 10 0.0000 4 105 315 2970 6660 fetch\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 2970 6840 queue\001 +-6 +6 2610 5670 3330 6120 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 3330 6120 2610 6120 2610 5670 3330 5670 3330 6120 +4 1 0 50 -1 -1 10 0.0000 4 105 450 2970 5850 address\001 +4 1 0 50 -1 -1 10 0.0000 4 120 585 2970 6030 generator\001 +-6 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5221 24 24 5040 5221 5064 5217 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5895 24 24 5040 5895 5064 5891 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 4860 5760 24 24 4860 5760 4884 5756 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 5220 3870 5220 3870 4095 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 5220 6030 5220 6030 4095 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4860 5760 4860 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5040 6480 5040 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3330 6705 4590 6705 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3870 5895 3330 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5310 6705 5670 6705 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 5040 5310 4455 4590 4455 4590 5040 5310 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 5670 2970 3330 3870 3330 3870 3510 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3870 3330 4950 3330 4950 3510 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 3330 6030 3330 6030 3510 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 6570 5400 2790 5400 2790 3150 6570 3150 6570 5400 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5040 5895 4590 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4860 6480 4860 6030 4590 6030 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 5760 4590 5760 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2970 6480 2970 6120 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2610 5895 2250 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 1 + 2250 5895 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 3690 5490 4770 5490 4770 6300 3690 6300 3690 5490 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 6705 2610 6705 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6390 6705 6750 6705 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 4410 6300 6570 6300 6570 7110 4410 7110 4410 6300 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 6390 6930 5670 6930 5670 6480 6390 6480 6390 6930 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 6930 4590 6930 4590 6480 5310 6480 5310 6930 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 3510 5490 2430 5490 2430 7110 3510 7110 3510 5490 +4 2 0 50 -1 -1 10 0.0000 4 150 435 2880 4320 predict\001 +4 1 0 50 -1 -1 10 0.0000 4 105 315 4005 6660 fetch\001 +4 0 0 50 -1 -1 10 0.0000 4 150 825 5085 6435 decod_branch\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 4995 Table\001 +4 1 0 50 -1 -1 10 0.0000 4 150 450 4950 4815 Update\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 4950 4635 Branch\001 +4 2 0 50 -1 -1 10 0.0000 4 150 405 6705 5715 update\001 +4 0 0 50 -1 -1 10 0.0000 4 105 315 3060 6345 alloc\001 +4 2 0 50 -1 -1 10 0.0000 4 105 345 6750 7065 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 6750 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6660 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 6030 6840 queue\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 6885 Icache_rsp\001 +4 2 0 50 -1 -1 10 0.0000 4 150 750 4815 6435 decod_event\001 +4 1 0 50 -1 -1 10 0.0000 4 90 330 3600 5805 event\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 5805 Icache_req\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-decod_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-decod_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-decod_unit.fig (revision 91) @@ -0,0 +1,82 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +1 1 0 1 0 14 50 -1 -1 0.000 1 0.0000 3285 3465 315 135 3285 3465 3600 3330 +1 1 0 1 0 14 50 -1 -1 0.000 1 0.0000 6795 4140 135 360 6795 4140 6930 3780 +2 2 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 5 + 3150 3780 3420 3780 3420 4500 3150 4500 3150 3780 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 3 + 3150 3780 3420 4140 3150 4500 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2610 3780 3150 3960 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2610 4500 3150 4320 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3420 4140 3780 4140 +2 4 0 1 0 14 50 -1 -1 0.000 0 0 7 0 0 5 + 4500 3780 4500 4500 3780 4500 3780 3780 4500 3780 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4500 4140 5220 4140 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3285 3600 3285 3780 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 4 + 5220 4500 6300 4500 6300 3780 5220 3780 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 2 + 6030 3780 6030 4500 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 2 + 5760 3780 5760 4500 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 0 0 2 + 5490 3780 5490 4500 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6300 4140 6660 4140 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5760 3780 5760 2970 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3285 2970 3285 3330 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 4140 7290 4140 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3960 3780 3960 2970 +2 1 0 1 0 14 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4320 3780 4320 2970 +2 4 0 1 0 14 60 -1 20 0.000 0 0 7 0 0 5 + 2790 3150 2790 4680 4680 4680 4680 3150 2790 3150 +2 4 0 1 0 14 61 -1 10 0.000 0 0 7 0 0 5 + 2835 3195 2835 4725 4725 4725 4725 3195 2835 3195 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 7155 4725 7155 3195 5085 3195 5085 4725 7155 4725 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 5040 3150 5040 4680 7110 4680 7110 3150 5040 3150 +2 1 0 1 0 17 60 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6795 2970 6795 3780 +4 1 0 50 -1 0 8 0.0000 0 120 375 3285 3465 priority\001 +4 2 0 50 -1 0 8 0.0000 0 90 300 2520 3780 ifetch\001 +4 2 0 50 -1 0 8 0.0000 0 90 300 2520 4500 ifetch\001 +4 0 0 50 -1 0 8 0.0000 0 75 300 7380 4140 decod\001 +4 1 0 50 -1 0 8 0.0000 0 90 240 6795 4140 valid\001 +4 2 0 50 -1 0 8 0.0000 0 120 360 3960 2880 predict\001 +4 1 0 50 -1 0 8 0.0000 0 105 360 5760 2880 nb_inst\001 +4 1 0 50 -1 0 8 0.0000 0 105 285 6795 2880 depth\001 +4 0 0 50 -1 0 8 0.0000 0 90 750 4320 2880 context_event\001 +4 1 0 50 -1 0 8 0.0000 0 90 1155 3285 2790 context_decod_enable\001 +4 1 0 50 -1 2 10 0.0000 0 105 420 3735 4860 decod\001 +4 1 0 50 -1 2 10 0.0000 0 150 870 6075 4860 decod_queue\001 +4 1 0 60 -1 0 8 0.0000 0 75 300 4140 4185 decod\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-fetch_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-fetch_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-fetch_unit.fig (revision 91) @@ -0,0 +1,100 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3420 2700 3780 3240 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 3420 2700 3780 2700 3780 3240 3420 3240 3420 2700 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 3510 3240 3600 3150 3690 3240 +-6 +6 4230 2700 4590 3240 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 4230 2700 4590 2700 4590 3240 4230 3240 4230 2700 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 4320 3240 4410 3150 4500 3240 +-6 +6 3420 3420 3780 3960 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 3420 3420 3780 3420 3780 3960 3420 3960 3420 3420 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 3510 3960 3600 3870 3690 3960 +-6 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 2340 4950 2880 4770 2880 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 4590 2700 4770 2700 4770 3240 4590 3240 4590 2700 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 4770 2700 4590 2970 4770 3240 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5310 3060 4770 3060 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4050 4500 4050 3690 3780 3690 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 4 + 3420 4500 4590 4500 4590 4860 3420 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 4410 4500 4410 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 4230 4500 4230 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 4050 4500 4050 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 3870 4500 3870 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 3690 4500 3690 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4590 4680 5310 4680 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2880 4680 3420 4680 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3240 3330 2880 3330 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 3420 2970 3240 3330 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 3420 3690 3240 3330 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3420 2970 3240 2970 3240 2340 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4230 2970 3780 2970 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 5130 4140 5130 2520 3060 2520 3060 4140 5130 4140 +2 4 0 1 0 14 61 -1 10 0.000 0 0 7 0 0 5 + 4815 5085 4815 4365 3285 4365 3285 5085 4815 5085 +2 4 0 1 0 14 60 -1 20 0.000 0 0 7 0 0 5 + 3240 4365 3240 5040 4770 5040 4770 4365 3240 4365 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4680 4275 4680 3240 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4500 4275 4500 4500 +2 1 0 1 0 14 50 -1 20 0.000 0 0 -1 0 0 2 + 5310 4275 4500 4275 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 5175 4185 5175 2565 3105 2565 3105 4185 5175 4185 +4 0 0 50 -1 0 8 0.0000 0 120 480 4140 3960 ptr_write\001 +4 2 0 50 -1 0 8 0.0000 0 105 555 2790 3330 Icache_req\001 +4 2 0 50 -1 0 8 0.0000 0 105 540 2790 4680 Icache_rsp\001 +4 2 0 50 -1 0 8 0.0000 0 75 255 4455 4320 flush\001 +4 0 0 50 -1 0 8 0.0000 0 90 495 5400 4320 event_val\001 +4 0 0 50 -1 0 8 0.0000 0 90 705 5445 3060 event_address\001 +4 0 0 50 -1 0 8 0.0000 0 75 300 5400 4680 decod\001 +4 1 0 50 -1 0 8 0.0000 0 90 465 4410 2655 PC_next\001 +4 1 0 50 -1 0 8 0.0000 0 75 165 3600 2655 PC\001 +4 1 0 50 -1 0 8 0.0000 0 120 900 4950 2250 predict (pc_next)\001 +4 1 0 50 -1 0 8 0.0000 0 120 360 3240 2250 predict\001 +4 1 0 50 -1 2 10 0.0000 0 165 825 4050 5220 ifetch_queue\001 +4 1 0 50 -1 2 10 0.0000 0 150 1440 4050 2430 address_management\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-prediction_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-prediction_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end-prediction_unit.fig (revision 91) @@ -0,0 +1,192 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3510 7110 4140 7290 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 3 + 3510 7110 3825 7290 4140 7110 +2 2 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 5 + 3510 7110 4140 7110 4140 7290 3510 7290 3510 7110 +-6 +2 4 0 1 0 17 60 -1 20 4.000 0 0 7 0 0 5 + 4050 6840 4050 4680 2340 4680 2340 6840 4050 6840 +2 4 0 1 0 14 60 -1 20 4.000 0 0 7 0 0 5 + 5670 6390 5670 4950 4230 4950 4230 6390 5670 6390 +2 4 0 1 0 30 60 -1 20 4.000 0 0 7 0 0 5 + 7290 6390 7290 4905 5850 4905 5850 6390 7290 6390 +2 4 0 1 0 4 60 -1 20 4.000 0 0 7 0 0 5 + 2070 6390 2070 4950 630 4950 630 6390 2070 6390 +2 4 0 1 0 4 61 -1 10 4.000 0 0 7 0 0 5 + 2115 6435 2115 4995 675 4995 675 6435 2115 6435 +2 4 0 1 0 17 61 -1 10 4.000 0 0 7 0 0 5 + 4095 6885 4095 4725 2385 4725 2385 6885 4095 6885 +2 4 0 1 0 14 61 -1 10 4.000 0 0 7 0 0 5 + 5715 6435 5715 4995 4275 4995 4275 6435 5715 6435 +2 4 0 1 0 30 61 -1 10 4.000 0 0 7 0 0 5 + 7335 6435 7335 4950 5895 4950 5895 6435 7335 6435 +2 1 1 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 3150 6210 3150 5130 +2 1 1 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 3510 6210 3510 5130 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 2790 5130 3870 5130 3870 6210 2790 6210 2790 5130 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 3780 5130 3780 5040 2700 5040 2700 6120 2790 6120 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 3690 5040 3690 4950 2610 4950 2610 6030 2700 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 3600 4950 3600 4860 2520 4860 2520 5940 2610 5940 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 2430 5670 2160 5400 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2160 5400 2565 5400 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2340 5580 2745 5580 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2430 5670 2835 5670 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 5490 2655 5490 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2970 5670 2970 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2880 6210 2880 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2790 6120 2790 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2700 6030 2700 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3330 5670 3330 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 5670 3690 6480 +2 4 0 1 0 17 50 -1 -1 4.000 0 0 4 0 0 5 + 2700 6660 2700 6480 2970 6480 2970 6660 2700 6660 +2 2 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 5 + 3150 6480 3510 6480 3510 6660 3150 6660 3150 6480 +2 2 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 5 + 3510 6660 3870 6660 3870 6480 3510 6480 3510 6660 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2970 6570 3150 6570 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 3 + 3150 6480 3330 6660 3510 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 3 + 3510 6480 3690 6660 3870 6480 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 6030 5490 6030 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 5850 5490 5850 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 5670 5490 5670 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 5490 5490 5490 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 4410 5310 5490 5310 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2160 5535 1530 5535 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 3 + 2295 5535 2160 5535 2160 7470 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 810 5130 1890 5130 1890 6210 810 6210 810 5130 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 1350 6030 1350 7245 3510 7245 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3330 6660 3330 7155 3510 7155 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 6660 3690 7110 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 5085 6120 5085 6390 3960 6750 3960 7110 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3690 6750 4815 6390 4815 6120 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2070 7920 2070 7650 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 7920 2250 7650 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 1800 7875 1800 7560 1980 7560 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3825 7290 3825 7920 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 4 + 6030 6210 6030 5130 7110 5130 7110 6210 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 4410 5130 5490 5130 5490 6210 4410 6210 4410 5130 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 5310 7110 5310 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 5490 7110 5490 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 5670 7110 5670 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 5850 7110 5850 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 2 + 6030 6030 7110 6030 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3825 7470 6210 7470 6210 6120 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 5760 6930 5760 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 5580 6930 5580 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 6570 5220 6570 4500 4950 4500 4950 5220 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 4500 3330 4500 3330 5220 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3330 4500 1350 4500 1350 5310 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 6120 6930 7920 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 7920 6570 6120 +2 2 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 5 + 2340 7470 1980 7470 1980 7650 2340 7650 2340 7470 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 3 + 1980 7650 2160 7470 2340 7650 +4 1 0 50 -1 0 8 0.0000 0 90 180 2835 6570 hit?\001 +4 0 0 50 -1 0 8 0.0000 0 120 975 2340 8010 predict_pc_current\001 +4 2 0 50 -1 0 8 0.0000 0 120 1020 1980 8010 predict_pc_previous\001 +4 2 0 50 -1 0 8 0.0000 0 120 1545 1755 7875 predict_pc_current_is_ds_take\001 +4 1 0 50 -1 0 8 0.0000 0 120 840 3825 8010 predict_pc_next\001 +4 2 0 50 -1 0 8 0.0000 0 90 450 1260 7065 direction\001 +4 0 0 50 -1 0 8 0.0000 0 105 870 7740 5580 branch_complete\001 +4 0 0 50 -1 0 8 0.0000 0 90 675 7740 5760 branch_event\001 +4 1 0 50 -1 3 6 0.0000 0 120 345 2970 5355 @_src\001 +4 1 0 50 -1 3 6 0.0000 0 105 210 3330 5355 type\001 +4 1 0 50 -1 3 6 0.0000 0 120 375 3690 5355 @_dest\001 +4 1 0 50 -1 0 8 0.0000 0 105 285 6930 8100 depth\001 +4 1 0 50 -1 0 8 0.0000 0 75 300 6570 8100 decod\001 +4 2 0 50 -1 0 8 0.0000 0 120 900 6525 4635 prediction_update\001 +4 1 0 50 -1 2 10 0.0000 0 150 1485 3330 4410 Branch_Target_Buffer\001 +4 1 0 50 -1 2 10 0.0000 0 150 1560 4950 4410 Return _Address_Stack\001 +4 1 0 50 -1 2 10 0.0000 0 165 1725 6570 4410 Update_Prediction_Table\001 +4 1 0 50 -1 2 10 0.0000 0 120 660 1350 4410 Direction\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-front_end.fig (revision 91) @@ -0,0 +1,132 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3870 5670 4590 6120 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 4590 6120 3870 6120 3870 5670 4590 5670 4590 6120 +4 1 0 50 -1 -1 10 0.0000 4 105 525 4230 5850 Context\001 +4 1 0 50 -1 -1 10 0.0000 4 105 315 4230 6090 State\001 +-6 +6 3510 3510 6390 4455 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4950 4455 4950 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4230 4095 4230 3510 3510 3510 3510 4095 4230 4095 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 4095 5310 3510 4590 3510 4590 4095 5310 4095 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 6390 4095 5670 4095 5670 3510 6390 3510 6390 4095 +4 1 0 50 -1 -1 10 0.0000 4 105 405 3870 4050 Buffer\001 +4 1 0 50 -1 -1 10 0.0000 4 135 405 3870 3870 Target\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 3870 3690 Branch\001 +4 1 0 50 -1 -1 10 0.0000 4 105 585 4950 3870 Direction\001 +4 1 0 50 -1 -1 10 0.0000 4 105 330 6030 4050 Stack\001 +4 1 0 50 -1 -1 10 0.0000 4 105 510 6075 3870 Address\001 +4 1 0 50 -1 -1 10 0.0000 4 105 435 6030 3690 Return\001 +-6 +6 2610 6480 3330 6930 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 3330 6930 2610 6930 2610 6480 3330 6480 3330 6930 +4 1 0 50 -1 -1 10 0.0000 4 105 315 2970 6660 fetch\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 2970 6840 queue\001 +-6 +6 2610 5670 3330 6120 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 3330 6120 2610 6120 2610 5670 3330 5670 3330 6120 +4 1 0 50 -1 -1 10 0.0000 4 105 450 2970 5850 address\001 +4 1 0 50 -1 -1 10 0.0000 4 120 585 2970 6030 generator\001 +-6 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5221 24 24 5040 5221 5064 5217 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 5040 5895 24 24 5040 5895 5064 5891 +1 3 0 1 0 0 50 -1 20 0.000 1 0.0000 4860 5760 24 24 4860 5760 4884 5756 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 5220 3870 5220 3870 4095 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 5220 6030 5220 6030 4095 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4860 5760 4860 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5040 6480 5040 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3330 6705 4590 6705 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3870 5895 3330 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5310 6705 5670 6705 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 5040 5310 4455 4590 4455 4590 5040 5310 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 5670 2970 3330 3870 3330 3870 3510 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 3870 3330 4950 3330 4950 3510 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4950 3330 6030 3330 6030 3510 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 6570 5400 2790 5400 2790 3150 6570 3150 6570 5400 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5040 5895 4590 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 4860 6480 4860 6030 4590 6030 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 5760 4590 5760 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2970 6480 2970 6120 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2610 5895 2250 5895 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 1 + 2250 5895 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 3690 5490 4770 5490 4770 6300 3690 6300 3690 5490 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2250 6705 2610 6705 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6390 6705 6750 6705 +2 2 2 1 0 0 50 -1 -1 3.000 0 0 -1 0 0 5 + 4410 6300 6570 6300 6570 7110 4410 7110 4410 6300 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 6390 6930 5670 6930 5670 6480 6390 6480 6390 6930 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5310 6930 4590 6930 4590 6480 5310 6480 5310 6930 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 3510 5490 2430 5490 2430 7110 3510 7110 3510 5490 +4 2 0 50 -1 -1 10 0.0000 4 150 435 2880 4320 predict\001 +4 1 0 50 -1 -1 10 0.0000 4 105 315 4005 6660 fetch\001 +4 0 0 50 -1 -1 10 0.0000 4 150 825 5085 6435 decod_branch\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 4995 Table\001 +4 1 0 50 -1 -1 10 0.0000 4 150 450 4950 4815 Update\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 4950 4635 Branch\001 +4 2 0 50 -1 -1 10 0.0000 4 150 405 6705 5715 update\001 +4 0 0 50 -1 -1 10 0.0000 4 105 315 3060 6345 alloc\001 +4 2 0 50 -1 -1 10 0.0000 4 105 345 6750 7065 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 4950 6750 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 105 345 6030 6660 decod\001 +4 1 0 50 -1 -1 10 0.0000 4 120 345 6030 6840 queue\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 6885 Icache_rsp\001 +4 2 0 50 -1 -1 10 0.0000 4 150 750 4815 6435 decod_event\001 +4 1 0 50 -1 -1 10 0.0000 4 90 330 3600 5805 event\001 +4 2 0 50 -1 -1 10 0.0000 4 150 645 2340 5805 Icache_req\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-commit_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-commit_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-commit_unit.fig (revision 91) @@ -0,0 +1,166 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 8370 4680 8730 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 4 + 8730 5400 8730 4680 8370 4680 8370 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8370 4860 8730 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8370 5040 8730 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8370 5220 8730 5220 +-6 +6 7830 4680 8190 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 4 + 8190 5400 8190 4680 7830 4680 7830 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7830 4860 8190 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7830 5040 8190 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7830 5220 8190 5220 +-6 +6 7290 4680 7650 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 4 + 7650 5400 7650 4680 7290 4680 7290 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7290 4860 7650 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7290 5040 7650 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 7290 5220 7650 5220 +-6 +6 6750 4680 7110 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 4 + 7110 5400 7110 4680 6750 4680 6750 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 4860 7110 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5040 7110 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 6750 5220 7110 5220 +-6 +6 6120 5670 6390 6030 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 6390 6030 6120 6030 6120 5670 6390 5670 6390 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 6210 6030 6255 5940 6300 6030 +-6 +6 6120 3960 6390 4320 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 6390 4320 6120 4320 6120 3960 6390 3960 6390 4320 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 6210 4320 6255 4230 6300 4320 +-6 +6 6120 4860 6390 5220 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 6390 5220 6120 5220 6120 4860 6390 4860 6390 5220 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 6210 5220 6255 5130 6300 5220 +-6 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 5940 6210 5940 3780 8910 3780 8910 6210 5940 6210 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 5670 6930 5310 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 5670 8550 5310 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 5670 8010 5310 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7470 5670 7470 5310 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 4680 6930 4320 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7470 4680 7470 4320 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 4680 8010 4320 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 4680 8550 4320 +2 4 0 1 0 17 50 -1 -1 0.000 0 0 7 0 0 5 + 8730 4320 8730 3960 6750 3960 6750 4320 8730 4320 +2 4 0 1 0 17 50 -1 -1 0.000 0 0 7 0 0 5 + 8730 6030 8730 5670 6750 5670 6750 6030 8730 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6390 5850 6750 5850 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6390 4140 6750 4140 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 5670 6390 5220 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 4320 6390 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6120 5040 5580 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 6570 6930 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7470 6570 7470 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6570 8010 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 6570 8550 6030 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9270 4950 8550 4950 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 4950 8010 4950 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 4950 7470 4950 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7470 4950 6930 4950 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8730 4050 9270 4050 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8730 4230 9270 4230 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8370 3960 8370 3420 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7110 3960 7110 3420 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7740 3420 7740 3960 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 8955 6255 8955 3825 5985 3825 5985 6255 8955 6255 +4 2 0 50 -1 0 8 0.0000 0 105 360 5490 5040 nb_inst\001 +4 1 0 50 -1 0 8 0.0000 0 90 285 7740 6750 insert\001 +4 0 0 50 -1 0 8 0.0000 0 90 375 9360 4950 commit\001 +4 0 0 50 -1 0 8 0.0000 0 120 480 9360 4230 spr_write\001 +4 0 0 50 -1 0 8 0.0000 0 75 525 9360 4050 reexecute\001 +4 1 0 50 -1 0 8 0.0000 0 90 285 7110 3330 retire\001 +4 1 0 50 -1 0 8 0.0000 0 105 330 8370 3330 update\001 +4 1 0 50 -1 0 8 0.0000 0 75 285 8370 3150 event\001 +4 1 0 50 -1 0 8 0.0000 0 105 870 8370 2970 branch_complete\001 +4 1 0 50 -1 0 8 0.0000 0 105 285 7740 3330 depth\001 +4 1 0 50 -1 0 8 0.0000 0 120 450 7740 3150 interrupt\001 +4 1 0 50 -1 0 8 0.0000 0 120 480 6255 5625 ptr_write\001 +4 1 0 50 -1 0 8 0.0000 0 105 420 6255 3915 ptr_read\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-1.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-1.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-1.fig (revision 91) @@ -0,0 +1,129 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 7110 4500 8010 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 4500 8010 4500 8010 4860 7110 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 4500 7830 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 4500 7650 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 4500 7470 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 4500 7290 4860 +-6 +6 7110 5040 8010 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 5040 8010 5040 8010 5400 7110 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 5040 7830 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 5040 7650 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 5040 7470 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 5040 7290 5400 +-6 +6 7110 5580 8010 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 5580 8010 5580 8010 5940 7110 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 5580 7830 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 5580 7650 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 5580 7470 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 5580 7290 5940 +-6 +6 7110 6120 8010 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 6120 8010 6120 8010 6480 7110 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 6120 7830 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 6120 7650 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 6120 7470 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 6120 7290 6480 +-6 +6 8370 4770 8550 5130 +2 2 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 5 + 8370 4770 8550 4770 8550 5130 8370 5130 8370 4770 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 3 + 8370 4770 8550 4950 8370 5130 +-6 +6 8370 5850 8550 6210 +2 2 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 5 + 8370 5850 8550 5850 8550 6210 8370 6210 8370 5850 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 3 + 8370 5850 8550 6030 8370 6210 +-6 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 4635 8370 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 5220 8370 5040 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 5760 8370 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6300 8370 6120 +2 2 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 5 + 6750 4500 6570 4500 6570 6480 6750 6480 6750 4500 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 6570 4500 6750 5490 6570 6480 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 6300 7110 6300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 5760 7110 5760 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 5220 7110 5220 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 4680 7110 4680 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 6030 9090 6030 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 4950 9090 4950 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6210 4230 6210 4590 6570 4590 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 5040 6570 5040 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 5490 6570 5490 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 5940 6570 5940 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 6390 6570 6390 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 8730 6660 8730 4320 6390 4320 6390 6660 8730 6660 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 8775 6705 8775 4365 6435 4365 6435 6705 8775 6705 +4 1 0 50 -1 0 8 0.0000 0 75 525 6210 4140 reexecute\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 5040 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 5490 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 5940 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 6390 issue_in\001 +4 0 0 50 -1 0 8 0.0000 0 105 465 9180 4950 issue_out\001 +4 0 0 50 -1 0 8 0.0000 0 105 465 9180 6030 issue_out\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-2.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-2.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-issue_queue-2.fig (revision 91) @@ -0,0 +1,114 @@ +#FIG 3.2 Produced by xfig version 3.2.5 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 7110 4500 8010 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 4500 8010 4500 8010 4860 7110 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 4500 7830 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 4500 7650 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 4500 7470 4860 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 4500 7290 4860 +-6 +6 7110 5040 8010 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 5040 8010 5040 8010 5400 7110 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 5040 7830 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 5040 7650 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 5040 7470 5400 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 5040 7290 5400 +-6 +6 7110 5580 8010 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 5580 8010 5580 8010 5940 7110 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 5580 7830 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 5580 7650 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 5580 7470 5940 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 5580 7290 5940 +-6 +6 7110 6120 8010 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 4 + 7110 6120 8010 6120 8010 6480 7110 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 6120 7830 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7650 6120 7650 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7470 6120 7470 6480 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 6120 7290 6480 +-6 +6 8370 4500 8550 6480 +2 2 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 5 + 8370 4500 8550 4500 8550 6480 8370 6480 8370 4500 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 3 + 8370 4500 8550 5490 8370 6480 +-6 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 4635 8370 4635 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 5220 8370 5220 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 5760 8370 5760 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 6300 8370 6300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 3 + 6570 4500 6750 4680 6570 4860 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 6300 7110 6300 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 5760 7110 5760 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 5220 7110 5220 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6750 4680 7110 4680 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 6030 9090 6030 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8550 4950 9090 4950 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6210 4230 6210 4590 6570 4590 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 8730 6660 8730 4320 6390 4320 6390 6660 8730 6660 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 8775 6705 8775 4365 6435 4365 6435 6705 8775 6705 +2 2 0 1 0 14 50 -1 -1 4.000 0 0 -1 0 0 5 + 6750 4500 6570 4500 6570 4860 6750 4860 6750 4500 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 4770 6570 4770 +4 1 0 50 -1 0 8 0.0000 0 75 525 6210 4140 reexecute\001 +4 0 0 50 -1 0 8 0.0000 0 105 465 9180 4950 issue_out\001 +4 0 0 50 -1 0 8 0.0000 0 105 465 9180 6030 issue_out\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 6300 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 5760 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 5220 issue_in\001 +4 2 0 50 -1 0 8 0.0000 0 105 390 5940 4770 issue_in\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-reexecute_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-reexecute_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-reexecute_unit.fig (revision 91) @@ -0,0 +1,100 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 7290 3870 7830 4050 +2 2 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 5 + 7290 4050 7830 4050 7830 3870 7290 3870 7290 4050 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 3 + 7290 3870 7560 4050 7830 3870 +-6 +6 7290 5310 7830 5490 +2 2 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 5 + 7290 5490 7830 5490 7830 5310 7290 5310 7290 5490 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 3 + 7290 5310 7560 5490 7830 5310 +-6 +1 1 0 1 0 17 50 -1 -1 4.000 1 3.1416 9180 4860 135 270 9180 4860 9045 5130 +2 4 0 1 0 17 60 -1 20 4.000 0 0 7 0 0 5 + 7110 5670 7110 3060 8550 3060 8550 5670 7110 5670 +2 4 0 1 0 17 61 -1 10 4.000 0 0 7 0 0 5 + 8595 5715 8595 3105 7155 3105 7155 5715 8595 5715 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 4 + 7290 4230 7290 4950 7830 4950 7830 4230 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 2 + 7290 4770 7830 4770 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 4590 7290 4590 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 2 + 7830 4410 7290 4410 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8190 3510 6840 3510 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7560 3510 7560 3870 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7560 4050 7560 4320 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 7650 4860 9045 4860 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7560 4860 7560 5310 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6840 5130 7380 5130 7380 5310 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7560 5490 7560 5940 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 3 + 8370 3240 8190 3510 8370 3780 +2 2 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 5 + 8190 3780 8370 3780 8370 3240 8190 3240 8190 3780 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8820 3240 8370 3420 +2 1 0 1 0 30 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8820 3780 8370 3600 +2 2 0 1 0 30 50 -1 -1 4.000 0 0 -1 0 0 5 + 9540 4590 10170 4590 10170 5130 9540 5130 9540 4590 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 0 0 5 + 9540 5040 9450 5040 9450 4500 10080 4500 10080 4590 +2 1 0 1 0 17 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9315 4860 9720 4860 +2 4 0 1 0 14 60 -1 20 4.000 0 0 7 0 0 5 + 10350 5310 10350 4320 8820 4320 8820 5310 10350 5310 +2 4 0 1 0 14 61 -1 10 4.000 0 0 7 0 0 5 + 10395 5355 10395 4365 8865 4365 8865 5355 10395 5355 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 5760 9630 5040 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10080 5040 10080 5760 +2 1 0 1 0 14 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9855 5760 9855 5040 +4 1 0 50 -1 0 8 0.0000 0 75 525 7560 6120 reexecute\001 +4 2 0 50 -1 0 8 0.0000 0 90 375 6795 3510 commit\001 +4 2 0 50 -1 0 8 0.0000 0 105 600 6750 5265 (store head)\001 +4 2 0 50 -1 0 8 0.0000 0 90 750 6750 5085 reexecute_rob\001 +4 0 0 50 -1 0 8 0.0000 0 105 705 8910 3780 execute_loop\001 +4 0 0 50 -1 0 8 0.0000 0 105 705 8910 3240 execute_loop\001 +4 1 0 50 -1 2 10 0.0000 0 165 990 7830 2970 reexecute_unit\001 +4 1 0 50 -1 2 10 0.0000 0 165 1380 9540 4230 special_register_unit\001 +4 2 0 50 -1 0 8 0.0000 0 120 735 9855 6120 spr_sr_commit\001 +4 2 0 50 -1 0 8 0.0000 0 105 495 9585 5940 spr_event\001 +4 2 0 50 -1 0 8 0.0000 0 105 330 9855 6210 (flags)\001 +4 0 0 50 -1 0 8 0.0000 0 105 420 10080 5940 spr_read\001 +4 1 0 50 -1 0 8 1.5708 0 75 240 9225 4860 mask\001 +4 0 0 50 -1 0 8 0.0000 0 90 525 7875 4815 spr_access\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-rename_unit.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-rename_unit.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine-rename_unit.fig (revision 91) @@ -0,0 +1,163 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 7155 4500 10260 6750 +6 8415 6120 9135 6300 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 8415 6300 9135 6300 9135 6120 8415 6120 8415 6300 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8595 6120 8595 6300 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8775 6120 8775 6300 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8955 6120 8955 6300 +-6 +6 8685 5580 8865 5940 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 8685 5940 8775 5850 8865 5940 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 8685 5940 8865 5940 8865 5580 8685 5580 8685 5940 +-6 +6 8415 5220 9135 5400 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 8415 5400 9135 5400 9135 5220 8415 5220 8415 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8595 5220 8595 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8775 5220 8775 5400 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 2 + 8955 5220 8955 5400 +-6 +6 8685 4680 8865 5040 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 8685 5040 8775 4950 8865 5040 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 8685 5040 8865 5040 8865 4680 8685 4680 8685 5040 +-6 +2 4 0 1 0 17 50 -1 -1 0.000 0 0 7 0 0 5 + 9675 6300 9675 4680 9315 4680 9315 6300 9675 6300 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8775 4860 9405 4860 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8775 5310 9405 5310 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8775 5760 9405 5760 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 8775 6210 9405 6210 +2 4 0 1 0 17 60 -1 20 0.000 0 0 7 0 0 5 + 7425 6480 7425 4500 10215 4500 10215 6480 7425 6480 +2 4 0 1 0 17 61 -1 10 0.000 0 0 7 0 0 5 + 10260 6525 10260 4545 7470 4545 7470 6525 10260 6525 +4 2 0 50 -1 0 6 0.0000 0 120 1155 8325 4860 store_queue_ptr_write\001 +4 2 0 50 -1 0 6 0.0000 0 120 1110 8325 5760 load_queue_ptr_write\001 +4 2 0 50 -1 0 6 0.0000 0 105 840 8325 5310 store_queue_use\001 +4 2 0 50 -1 0 6 0.0000 0 105 795 8325 6210 load_queue_use\001 +4 1 0 50 -1 0 8 0.0000 0 90 285 9765 4635 insert\001 +4 1 0 50 -1 2 10 0.0000 0 165 1695 8775 6705 Load_store_pointer_unit\001 +-6 +6 5580 3105 6705 4905 +6 5580 3960 6300 4680 +2 2 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 5 + 6300 3960 6120 3960 6120 4680 6300 4680 6300 3960 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5580 4500 6120 4500 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5580 4140 6120 4140 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 0 0 3 + 6120 4680 6300 4320 6120 3960 +-6 +1 1 0 1 0 17 50 -1 -1 0.000 1 0.0000 6210 3645 270 135 6210 3645 6480 3510 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6210 3780 6210 3960 +2 4 0 1 0 6 60 -1 20 0.000 0 0 7 0 0 5 + 6660 4860 6660 3330 5760 3330 5760 4860 6660 4860 +2 4 0 1 0 6 61 -1 10 0.000 0 0 7 0 0 5 + 6705 4905 6705 3375 5805 3375 5805 4905 6705 4905 +4 1 0 50 -1 0 8 0.0000 0 120 375 6210 3690 priority\001 +4 1 0 50 -1 2 10 0.0000 0 150 960 6210 3240 rename_select\001 +-6 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6300 4320 11160 4320 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9495 4320 9495 4680 +2 1 0 1 0 17 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9675 5580 10035 5580 10035 4320 +2 2 0 1 0 6 50 -1 -1 0.000 0 0 -1 0 0 5 + 7020 3780 7560 3780 7560 3240 7020 3240 7020 3780 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7290 4320 7290 3780 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 8190 3240 8190 3420 8820 3420 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7560 3600 8820 3600 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 0 0 4 + 7920 2700 7920 3240 8460 3240 8460 2700 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 0 0 2 + 7920 3060 8460 3060 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 0 0 2 + 7920 2880 8460 2880 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3780 9090 4320 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 10800 4320 10800 2520 10125 2520 10125 2700 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 10125 2520 8190 2520 8190 2700 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 8190 2520 7380 2520 7380 3240 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7200 1980 7200 3240 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 7200 2340 9855 2340 9855 2700 +2 1 0 1 0 6 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9720 2970 8190 2970 +2 2 0 1 0 6 50 -1 -1 0.000 0 0 -1 0 0 5 + 9720 3240 10260 3240 10260 2700 9720 2700 9720 3240 +2 4 0 1 0 6 50 -1 -1 0.000 0 0 7 0 0 5 + 9360 3780 9360 3240 8820 3240 8820 3780 9360 3780 +2 4 0 1 0 30 60 -1 20 0.000 0 0 7 0 0 5 + 10980 4140 10980 2160 6840 2160 6840 4140 10980 4140 +2 4 0 1 0 30 61 -1 10 0.000 0 0 7 0 0 5 + 11025 4185 11025 2205 6885 2205 6885 4185 11025 4185 +4 2 0 50 -1 0 8 0.0000 0 105 675 9000 3960 num_reg_phy\001 +4 0 0 50 -1 0 8 0.0000 0 90 660 7380 3960 num_reg_log\001 +4 1 0 50 -1 3 8 0.0000 0 75 240 7290 3510 RAT\001 +4 1 0 50 -1 3 8 0.0000 0 75 180 9990 2925 Stat\001 +4 1 0 50 -1 3 8 0.0000 0 90 180 9990 3105 List\001 +4 1 0 50 -1 3 8 0.0000 0 120 630 9090 3465 Dependency\001 +4 1 0 50 -1 3 8 0.0000 0 120 465 9090 3600 Checking\001 +4 1 0 50 -1 3 8 0.0000 0 90 465 8190 2835 Free List\001 +4 1 0 50 -1 2 10 0.0000 0 165 1725 8910 2070 Register_translation_unit\001 +4 1 0 50 -1 0 8 0.0000 0 90 285 7200 1890 retire\001 +4 0 0 50 -1 0 8 0.0000 0 90 285 11250 4320 insert\001 +4 2 0 61 -1 0 8 0.0000 0 75 300 5490 4140 decod\001 +4 2 0 61 -1 0 8 0.0000 0 75 300 5490 4500 decod\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-out_of_order_engine.fig (revision 91) @@ -0,0 +1,124 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 5130 5985 5850 6435 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 5850 6435 5130 6435 5130 5985 5850 5985 5850 6435 +4 1 0 50 -1 -1 10 0.0000 4 75 435 5490 6165 rename\001 +4 1 0 50 -1 -1 10 0.0000 4 105 360 5490 6345 select\001 +-6 +6 5850 6570 6570 7020 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 6570 7020 5850 7020 5850 6570 6570 6570 6570 7020 +4 1 0 50 -1 -1 10 0.0000 4 150 660 6210 6705 load_store\001 +4 1 0 50 -1 -1 10 0.0000 4 135 450 6210 6840 pointer\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 6210 6975 unit\001 +-6 +6 5850 5400 6570 5850 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 6570 5850 5850 5850 5850 5400 6570 5400 6570 5850 +4 1 0 50 -1 -1 10 0.0000 4 135 525 6210 5535 Register\001 +4 1 0 50 -1 -1 10 0.0000 4 105 510 6210 5670 Address\001 +4 1 0 50 -1 -1 10 0.0000 4 105 720 6210 5805 Translation\001 +-6 +6 6660 4320 7380 4770 +6 6660 4320 7380 4770 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7380 4770 6660 4770 6660 4320 7380 4320 7380 4770 +-6 +4 1 0 50 -1 -1 10 0.0000 4 105 300 7020 4590 ROB\001 +-6 +6 7830 4320 8550 4770 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 8550 4770 7830 4770 7830 4320 8550 4320 8550 4770 +4 1 0 50 -1 -1 10 0.0000 4 105 630 8190 4500 Reexecute\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 8190 4680 unit\001 +-6 +6 8910 4320 9630 4770 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 9630 4770 8910 4770 8910 4320 9630 4320 9630 4770 +4 1 0 50 -1 -1 10 0.0000 4 135 435 9270 4455 Special\001 +4 1 0 50 -1 -1 10 0.0000 4 135 525 9270 4590 Register\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 9270 4725 unit\001 +-6 +6 7200 5805 8280 6615 +6 7380 5985 8100 6435 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 8100 6435 7380 6435 7380 5985 8100 5985 8100 6435 +4 1 0 50 -1 -1 10 0.0000 4 105 345 7740 6345 queue\001 +4 1 0 50 -1 -1 10 0.0000 4 105 315 7740 6165 Issue\001 +-6 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 7200 6615 8280 6615 8280 5805 7200 5805 7200 6615 +-6 +1 3 0 1 0 7 50 -1 0 3.000 1 0.0000 7110 5760 30 30 7110 5760 7140 5756 +1 3 0 1 0 7 50 -1 0 3.000 1 0.0000 7110 6210 30 30 7110 6210 7140 6206 +1 3 0 1 0 7 50 -1 0 3.000 1 0.0000 6930 5625 30 30 6930 5625 6960 5621 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8100 6210 9990 6210 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4770 6210 5130 6210 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6660 4545 4770 4545 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5850 6210 7380 6210 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6210 6210 6210 6570 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6210 6210 6210 5850 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6930 5625 6930 6705 6570 6705 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7110 6840 7110 4770 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7110 5760 6570 5760 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7110 6840 6570 6840 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 6750 7200 4950 7200 4950 5220 6750 5220 6750 7200 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 5490 9990 5490 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6930 4770 6930 5625 6570 5625 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 6480 4950 7560 4950 7560 4140 6480 4140 6480 4950 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.03 120.05 + 3 0 1.00 60.03 120.05 + 8550 4545 8910 4545 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 9990 3960 8190 3960 8190 4320 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 7650 4950 9810 4950 9810 4140 7650 4140 7650 4950 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 7830 4635 7605 4635 7605 5985 +2 1 0 1 0 30 61 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7830 4455 7380 4455 +4 0 0 50 -1 -1 10 0.0000 4 105 345 4815 6165 decod\001 +4 0 0 50 -1 -1 10 0.0000 4 105 360 7155 5130 insert\001 +4 2 0 50 -1 -1 10 0.0000 4 105 345 6840 5130 retire\001 +4 2 0 50 -1 -1 10 0.0000 4 135 405 4680 4545 update\001 +4 0 0 50 -1 -1 10 0.0000 4 75 435 10080 6210 rename\001 +4 0 0 50 -1 -1 10 0.0000 4 150 855 10080 5490 register_state\001 +4 0 0 50 -1 -1 10 0.0000 4 90 465 10080 3960 execute\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-overview.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-overview.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-overview.fig (revision 91) @@ -0,0 +1,312 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +0 32 #9c0000 +0 33 #8c8c8c +0 34 #8c8c8c +0 35 #424242 +0 36 #8c8c8c +0 37 #424242 +0 38 #8c8c8c +0 39 #424242 +0 40 #8c8c8c +0 41 #424242 +0 42 #8c8c8c +0 43 #424242 +0 44 #c2c2c2 +0 45 #6e6e6e +0 46 #444444 +0 47 #8e8f8e +0 48 #717171 +0 49 #aeaeae +0 50 #333333 +0 51 #949395 +0 52 #747075 +0 53 #555555 +0 54 #b3b3b3 +0 55 #c3c3c3 +0 56 #6d6d6d +0 57 #454545 +0 58 #8e8e8e +0 59 #e2e2ee +0 60 #94949a +0 61 #dbdbdb +0 62 #a1a1b7 +0 63 #ededed +0 64 #e0e0e0 +0 65 #86acff +0 66 #7070ff +0 67 #7c7c7c +0 68 #c9aaa1 +0 69 #808080 +0 70 #b6b6b6 +0 71 #ac9478 +0 72 #404040 +0 73 #c0c0c0 +0 74 #c0c0c0 +0 75 #dd9d93 +0 76 #f1ece0 +0 77 #e2c8a8 +0 78 #e1e1e1 +0 79 #d2d2d2 +0 80 #da7a1a +0 81 #f1e41a +0 82 #887dc2 +0 83 #b0a193 +0 84 #837cdd +0 85 #d6d6d6 +0 86 #8c8ca5 +0 87 #4a4a4a +0 88 #8c6b6b +0 89 #5a5a5a +0 90 #636363 +0 91 #b79b73 +0 92 #4193ff +0 93 #bf703b +0 94 #db7700 +0 95 #dab800 +0 96 #006400 +0 97 #5a6b3b +0 98 #d3d3d3 +0 99 #aaaaaa +0 100 #8e8ea4 +0 101 #f3b95d +0 102 #89996b +0 103 #646464 +0 104 #b7e6ff +0 105 #86c0ec +0 106 #bdbdbd +0 107 #d39552 +0 108 #98d2fe +0 109 #8c9c6b +0 110 #f76b00 +0 111 #5a6b39 +0 112 #8c9c6b +0 113 #8c9c7b +0 114 #184a18 +0 115 #adadad +0 116 #f7bd5a +0 117 #636b9c +0 118 #f7f7f7 +0 119 #de0000 +0 120 #adadad +0 121 #f7bd5a +0 122 #adadad +0 123 #f7bd5a +0 124 #636b9c +0 125 #526b29 +0 126 #949494 +0 127 #006300 +0 128 #00634a +0 129 #7b844a +0 130 #e7bd7b +0 131 #a5b5c6 +0 132 #6b6b94 +0 133 #846b6b +0 134 #529c4a +0 135 #d6e7e7 +0 136 #526363 +0 137 #186b4a +0 138 #9ca5b5 +0 139 #ff9400 +0 140 #ff9400 +0 141 #00634a +0 142 #7b844a +0 143 #63737b +0 144 #e7bd7b +0 145 #184a18 +0 146 #f7bd5a +0 147 #000000 +0 148 #f73829 +0 149 #000000 +0 150 #ffff52 +0 151 #52794a +0 152 #639a5a +0 153 #c66142 +0 154 #e76942 +0 155 #ff7952 +0 156 #dedede +0 157 #f3eed3 +0 158 #f5ae5d +0 159 #95ce99 +0 160 #b5157d +0 161 #eeeeee +0 162 #848484 +0 163 #7b7b7b +0 164 #005a00 +0 165 #e77373 +0 166 #ffcb31 +0 167 #29794a +0 168 #de2821 +0 169 #2159c6 +0 170 #f8f8f8 +0 171 #e6e6e6 +0 172 #21845a +6 8370 3690 9090 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 9090 4140 8370 4140 8370 3690 9090 3690 9090 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 330 8730 3960 read\001 +-6 +6 11250 3690 11970 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 11970 4140 11250 4140 11250 3690 11970 3690 11970 4140 +4 1 0 50 -1 -1 12 0.0000 4 135 390 11610 3960 write\001 +-6 +6 9810 2475 10530 2925 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 2925 9810 2925 9810 2475 10530 2475 10530 2925 +4 1 0 50 -1 -1 12 0.0000 4 150 300 10170 2835 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 540 10170 2655 dcache\001 +-6 +6 1890 3690 2610 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2610 4140 1890 4140 1890 3690 2610 3690 2610 4140 +4 1 0 50 -1 -1 12 0.0000 4 150 300 2250 4050 port\001 +4 1 0 50 -1 -1 12 0.0000 4 135 495 2250 3870 icache\001 +-6 +6 6570 3015 7290 3465 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 7290 3465 6570 3465 6570 3015 7290 3015 7290 3465 +4 1 0 50 -1 -1 12 0.0000 4 135 555 6930 3285 commit\001 +-6 +6 1800 4590 4365 5355 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1800 4770 2160 4770 2160 4590 1800 4590 1800 4770 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 2160 5040 1800 5040 1800 4860 2160 4860 2160 5040 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 2160 5310 1800 5310 1800 5130 2160 5130 2160 5310 +4 0 0 50 -1 -1 12 0.0000 4 180 1635 2340 4770 Composant structurel\001 +4 0 0 50 -1 -1 12 0.0000 4 180 1935 2340 5040 Composant pluri-instance\001 +4 0 0 50 -1 -1 12 0.0000 4 180 2010 2340 5310 Composant mono-instance\001 +-6 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 6930 3015 6930 2790 5130 2790 5130 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 5130 2790 4230 2790 4230 3060 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6030 2790 6030 3690 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5490 3915 5850 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 0 3 + 3 0 1.00 60.00 120.00 + 6390 3690 6390 3240 6570 3240 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6570 3915 7650 3915 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 0 0 1 + 7650 3780 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8010 3915 8370 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11970 3915 12150 3915 12150 3240 8010 3240 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 4 + 3 0 1.00 60.00 120.00 + 11430 4140 11430 4500 8820 4500 8820 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 8640 4680 8640 4140 +2 1 0 1 0 7 50 -1 20 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11790 4140 11790 4680 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 11970 5040 11970 4680 8370 4680 8370 5040 11970 5040 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 8190 3105 12330 3105 12330 5220 8190 5220 8190 3105 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 11070 3510 11070 4320 10710 4320 10710 3510 11070 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 11070 3915 11250 3915 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9090 3915 9270 3915 +2 4 0 1 0 7 50 -1 20 3.000 0 0 7 0 0 5 + 9630 3510 9630 4320 9270 4320 9270 3510 9630 3510 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 4185 9810 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 4185 10710 4185 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 10530 3645 10710 3645 +2 1 0 1 0 7 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 9630 3645 9810 3645 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 10170 2925 10170 3420 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7650 3240 7290 3240 +2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6930 3465 6930 3915 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4410 3510 4410 3780 4770 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 1 2 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 2970 3915 2610 3915 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 1710 5400 12510 5400 12510 2295 1710 2295 1710 5400 +2 1 0 1 0 31 50 -1 -1 4.000 0 0 -1 1 1 3 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 4050 3510 4050 3780 3690 3780 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3690 4050 4770 4050 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 5 + 5580 2880 2790 2880 2790 4320 5580 4320 5580 2880 +2 2 2 1 0 7 50 -1 -1 3.000 0 0 7 0 0 5 + 7470 4320 5760 4320 5760 2610 7470 2610 7470 4320 +2 4 0 1 0 7 50 -1 20 3.000 0 0 8 0 0 5 + 8010 2880 8010 4320 7650 4320 7650 2880 8010 2880 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 4410 9810 4410 9810 3960 10530 3960 10530 4410 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 10530 3870 9810 3870 9810 3420 10530 3420 10530 3870 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 3690 4140 2970 4140 2970 3690 3690 3690 3690 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 4140 4770 4140 4770 3690 5490 3690 5490 4140 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 6570 4140 5850 4140 5850 3690 6570 3690 6570 4140 +2 4 0 1 0 31 50 -1 20 4.000 0 0 7 0 0 5 + 4590 3510 3870 3510 3870 3060 4590 3060 4590 3510 +2 4 0 1 0 11 50 -1 20 4.000 0 0 7 0 0 5 + 5490 3690 4770 3690 4770 3240 5490 3240 5490 3690 +4 1 0 50 -1 -1 12 0.0000 4 180 585 10170 4905 register\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 10935 3915 select\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 9495 3915 select\001 +4 0 1 50 -1 -1 12 0.0000 4 135 360 1710 2205 Core\001 +4 0 1 50 -1 -1 12 0.0000 4 135 750 2790 2790 Front End\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1185 8190 3015 Execution Loop\001 +4 0 1 50 -1 -1 12 0.0000 4 180 1575 5760 2520 Out Of Order Engine\001 +4 1 0 50 -1 -1 12 1.5708 4 135 465 7875 3600 select\001 +4 1 0 50 -1 -1 12 0.0000 4 105 600 10170 4230 execute\001 +4 1 0 50 -1 -1 12 0.0000 4 135 600 10170 3690 memory\001 +4 1 0 50 -1 0 12 0.0000 4 90 555 6210 3960 rename\001 +4 1 0 50 -1 -1 12 0.0000 4 135 390 3330 3960 fetch\001 +4 1 0 50 -1 0 12 0.0000 4 135 450 5130 3960 decod\001 +4 1 0 50 -1 -1 12 0.0000 4 105 570 5130 3420 context\001 +4 1 0 50 -1 -1 12 0.0000 4 105 390 5130 3600 state\001 +4 1 0 50 -1 -1 12 0.0000 4 180 675 4230 3330 predictor\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-part.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-part.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-part.fig (revision 91) @@ -0,0 +1,97 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 2610 4095 3420 4410 +4 1 0 0 -1 3 9 0.0000 0 150 780 3015 4365 Out of Order\001 +4 1 0 0 -1 0 9 0.0000 0 150 645 3015 4230 Icache_rsp\001 +-6 +6 5670 4095 6480 4455 +4 1 0 0 -1 3 9 0.0000 0 150 780 6075 4410 Out of Order\001 +4 1 0 0 -1 0 9 0.0000 0 105 315 6075 4230 Issue\001 +-6 +6 6975 3915 8235 4635 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7290 3960 7920 3960 +4 1 0 0 -1 3 9 0.0000 0 150 1200 7605 4590 Load : Out of Order\001 +4 1 0 0 -1 0 9 0.0000 0 150 690 7605 4230 Dcache_req\001 +4 1 0 0 -1 3 9 0.0000 0 105 960 7605 4410 Store : In Order\001 +-6 +6 7200 2745 8010 3105 +4 1 0 0 -1 0 9 0.0000 0 150 690 7605 3060 Dcache_rsp\001 +4 1 0 0 -1 3 9 0.0000 0 150 780 7605 2880 Out of Order\001 +-6 +6 5670 2745 6480 3060 +4 1 0 0 -1 0 9 0.0000 0 105 495 6075 3060 Execute\001 +4 1 0 0 -1 3 9 0.0000 0 150 780 6075 2880 Out of Order\001 +-6 +6 4275 2745 4815 3060 +4 1 0 0 -1 0 9 0.0000 0 105 525 4545 3060 Commit\001 +4 1 0 0 -1 3 9 0.0000 0 105 525 4545 2880 In Order\001 +-6 +6 2655 2745 3375 3105 +4 1 0 0 -1 0 9 0.0000 0 150 645 3015 3060 Icache_req\001 +4 1 0 0 -1 3 9 0.0000 0 105 600 3015 2880 In Order*\001 +-6 +6 4275 4095 4815 4410 +4 1 0 0 -1 3 9 0.0000 0 105 525 4545 4410 In Order\001 +4 1 0 0 -1 0 9 0.0000 0 105 435 4545 4230 Decode\001 +-6 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 3330 3330 2700 3330 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 2700 3870 3330 3870 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4230 3870 4860 3870 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 4860 3330 4230 3330 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 6390 3330 5760 3330 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5760 3870 6390 3870 +2 1 0 1 0 11 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 7920 3330 7290 3330 +2 4 0 1 0 6 52 -1 20 0.000 0 0 7 0 0 5 + 3015 2610 7605 2610 7605 4590 3015 4590 3015 2610 +2 4 0 1 0 31 53 -1 10 0.000 0 0 7 0 0 5 + 7650 2655 7650 4635 3060 4635 3060 2655 7650 2655 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 1800 4050 1800 3150 2700 3150 2700 4050 1800 4050 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 4230 4050 4230 3150 3330 3150 3330 4050 4230 4050 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5760 4050 5760 3150 4860 3150 4860 4050 5760 4050 +2 4 0 1 0 13 50 -1 20 0.000 0 0 7 0 0 5 + 7920 4050 7920 3150 8820 3150 8820 4050 7920 4050 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 7290 4050 7290 3150 6390 3150 6390 4050 7290 4050 +2 4 0 1 0 13 51 -1 10 0.000 0 0 7 0 0 5 + 8865 3195 7965 3195 7965 4095 8865 4095 8865 3195 +2 4 0 1 0 13 52 -1 10 0.000 0 0 7 0 0 5 + 2745 3195 1845 3195 1845 4095 2745 4095 2745 3195 +2 4 0 1 0 11 51 -1 10 0.000 0 0 7 0 0 5 + 4275 3195 3375 3195 3375 4095 4275 4095 4275 3195 +2 4 0 1 0 11 51 -1 10 0.000 0 0 7 0 0 5 + 5805 3195 4905 3195 4905 4095 5805 4095 5805 3195 +2 4 0 1 0 11 51 -1 10 0.000 0 0 7 0 0 5 + 7335 3195 6435 3195 6435 4095 7335 4095 7335 3195 +4 1 0 0 -1 2 10 0.0000 0 105 330 5310 2520 Core\001 +4 1 0 0 -1 2 10 0.0000 0 105 480 2250 3600 ICache\001 +4 1 0 0 -1 2 10 0.0000 0 105 690 3780 3600 Front end\001 +4 1 0 0 -1 2 10 0.0000 0 165 810 5310 3600 OoO Engine\001 +4 1 0 0 -1 2 10 0.0000 0 105 525 8370 3600 DCache\001 +4 1 0 0 -1 2 10 0.0000 0 105 540 6840 3510 Execute\001 +4 1 0 0 -1 2 10 0.0000 0 135 360 6840 3735 Loop\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-pipeline.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-pipeline.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_micro_architecture-pipeline.fig (revision 91) @@ -0,0 +1,126 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 11475 2550 13200 4200 +6 11550 3750 12750 4200 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 11550 3750 12150 3750 12150 4200 11550 4200 11550 3750 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 12150 3750 12750 3750 12750 4200 12150 4200 12150 3750 +4 1 0 50 -1 0 8 0.0000 0 105 375 11850 4125 request\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 12450 4125 respons\001 +4 1 0 50 -1 0 8 0.0000 0 75 375 11850 3900 Dcache\001 +4 1 0 50 -1 0 8 0.0000 0 75 375 12450 3900 Dcache\001 +-6 +4 0 0 50 -1 0 8 0.7854 0 75 375 12150 3600 Dcache\001 +4 0 0 50 -1 0 8 0.7854 0 120 1305 11550 3600 speculative_access_queue\001 +4 0 0 50 -1 0 8 0.7854 0 105 570 12750 3600 load_queue\001 +-6 +6 6450 3375 8025 4200 +2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 + 6450 3975 6750 3975 6750 4125 6450 4125 6450 3975 +2 2 0 0 0 13 55 -1 20 1.500 0 0 -1 0 0 5 + 6450 3375 6750 3375 6750 3525 6450 3525 6450 3375 +2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 + 6450 3675 6750 3675 6750 3825 6450 3825 6450 3675 +4 0 0 55 -1 0 8 0.0000 0 75 510 6900 3525 Front End\001 +4 0 0 55 -1 0 8 0.0000 0 105 1065 6900 3825 Out Of Order Engine\001 +4 0 0 55 -1 0 8 0.0000 0 105 720 6900 4125 Execute Loop\001 +-6 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 7050 4800 7650 4800 7650 5250 7050 5250 7050 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 6450 4800 7050 4800 7050 5250 6450 5250 6450 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 7650 4800 8250 4800 8250 5250 7650 5250 7650 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 8250 4800 8850 4800 8850 5250 8250 5250 8250 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 8850 4800 9450 4800 9450 5250 8850 5250 8850 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 9450 4800 10050 4800 10050 5250 9450 5250 9450 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 10050 4800 10650 4800 10650 5250 10050 5250 10050 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 10650 4800 11250 4800 11250 5250 10650 5250 10650 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 11250 4800 11850 4800 11850 5250 11250 5250 11250 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 11850 4800 12450 4800 12450 5250 11850 5250 11850 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 12450 4800 13050 4800 13050 5250 12450 5250 12450 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 13050 4800 13650 4800 13650 5250 13050 5250 13050 4800 +2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5 + 13650 4800 14250 4800 14250 5250 13650 5250 13650 4800 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 11850 4800 11550 4200 +2 1 2 1 0 7 50 -1 -1 3.000 0 0 -1 0 0 2 + 12450 4800 12750 4200 +2 2 0 1 0 13 55 -1 20 3.000 0 0 -1 0 0 5 + 6450 4800 9450 4800 9450 5250 6450 5250 6450 4800 +2 2 0 1 0 17 55 -1 20 3.000 0 0 -1 0 0 5 + 9450 4800 10650 4800 10650 5250 9450 5250 9450 4800 +2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 + 12750 4200 11550 4200 11550 3750 12750 3750 12750 4200 +2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 + 13050 4800 13650 4800 13650 5250 13050 5250 13050 4800 +2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 + 12750 4200 11550 4200 11550 3750 12750 3750 12750 4200 +2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 + 10650 5250 13050 5250 13050 4800 10650 4800 10650 5250 +2 2 0 0 0 13 55 -1 20 1.500 0 0 -1 0 0 5 + 13650 4950 14250 4950 14250 4800 13650 4800 13650 4950 +2 2 0 0 0 17 55 -1 20 1.500 0 0 -1 0 0 5 + 13650 4950 14250 4950 14250 5100 13650 5100 13650 4950 +2 2 0 0 0 4 55 -1 20 1.500 0 0 -1 0 0 5 + 13650 5250 14250 5250 14250 5100 13650 5100 13650 5250 +4 0 0 50 -1 0 8 5.4978 0 75 330 8250 5400 Icache\001 +4 0 0 50 -1 0 8 5.4978 0 90 765 6450 5400 PC_next_next\001 +4 0 0 50 -1 0 8 5.4978 0 75 165 7650 5400 PC\001 +4 0 0 50 -1 0 8 5.4978 0 90 465 7050 5400 PC_next\001 +4 0 0 50 -1 0 8 5.4978 0 105 675 8850 5400 Ifetch_queue\001 +4 0 0 50 -1 0 8 5.4978 0 105 690 9450 5400 Decod_queue\001 +4 0 0 50 -1 0 8 5.4978 0 105 675 10050 5400 Issue_queuec\001 +4 0 0 50 -1 0 8 5.4978 0 105 615 10650 5400 Read_queue\001 +4 0 0 50 -1 0 8 5.4978 0 105 990 11250 5400 Reservation_station\001 +4 0 0 50 -1 0 8 5.4978 0 105 555 12450 5400 Write_unit\001 +4 0 0 50 -1 0 8 5.4978 0 105 690 13050 5400 Execute_unit\001 +4 0 0 50 -1 0 8 5.4978 0 90 900 13650 5400 Re_Order_Buffer\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 6750 4650 1\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 7350 4650 2\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 7950 4650 3\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 8550 4650 4\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 9150 4650 5\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 9750 4650 6\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 10350 4650 7\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 10950 4650 8\001 +4 1 0 50 -1 0 8 0.0000 0 75 60 11550 4650 9\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 12150 4650 10\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 12750 4650 11\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 13350 4650 12\001 +4 1 0 50 -1 0 8 0.0000 0 75 120 13950 4650 13\001 +4 1 0 50 -1 0 8 0.0000 0 75 330 7950 4950 Icache\001 +4 1 0 50 -1 0 8 0.0000 0 75 330 8550 4950 Icache\001 +4 1 0 50 -1 0 8 0.0000 0 75 330 9150 5025 Decod\001 +4 1 0 50 -1 0 8 0.0000 0 75 405 9750 5025 Rename\001 +4 1 0 50 -1 0 8 0.0000 0 75 255 10350 5025 Issue\001 +4 1 0 50 -1 0 8 0.0000 0 75 255 10950 4950 Read\001 +4 1 0 50 -1 0 8 0.0000 0 120 435 11550 5025 Dispatch\001 +4 1 0 50 -1 0 8 0.0000 0 75 435 12150 5025 Execute\001 +4 1 0 50 -1 0 8 0.0000 0 90 300 12750 4950 Write\001 +4 1 0 50 -1 0 8 0.0000 0 90 405 13350 5025 Commit\001 +4 1 0 50 -1 0 8 0.0000 0 105 360 13950 5025 Update\001 +4 1 0 50 -1 0 8 0.0000 0 105 375 7950 5175 request\001 +4 1 0 50 -1 0 8 0.0000 0 90 375 8550 5175 respons\001 +4 1 0 50 -1 0 8 0.0000 0 105 435 10950 5175 Register\001 +4 1 0 50 -1 0 8 0.0000 0 105 435 12750 5175 Register\001 +4 2 0 50 -1 0 8 0.0000 0 90 780 11250 4050 instruction load\001 +4 1 0 50 -1 0 8 0.0000 0 90 525 7350 5025 Prediction\001 +4 1 0 50 -1 0 8 0.0000 0 90 240 6750 5025 Wait\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_service.fig =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_service.fig (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/fig/MORPHEO_service.fig (revision 91) @@ -0,0 +1,121 @@ +#FIG 3.2 +Landscape +Center +Inches +Letter +100.00 +Single +-2 +1200 2 +6 4950 3000 5850 3450 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 5850 3450 5850 3000 4950 3000 4950 3450 5850 3450 +4 1 0 50 -1 -1 10 0.0000 4 105 615 5400 3225 Generator\001 +-6 +6 7350 3000 8250 3450 +2 4 0 1 0 11 50 -1 20 0.000 0 0 7 0 0 5 + 8250 3450 8250 3000 7350 3000 7350 3450 8250 3450 +4 1 0 50 -1 -1 10 0.0000 4 105 465 7800 3225 Viewer\001 +-6 +6 4875 1950 5925 2550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 5175.000 2100.000 4950 2400 5175 2475 5400 2400 +5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 5625.000 2700.000 5400 2400 5625 2325 5850 2400 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 4950 2400 4950 1950 5850 1950 5850 2400 +4 1 0 50 -1 -1 10 0.0000 4 105 630 5400 2100 Simulator\001 +4 1 0 50 -1 -1 10 0.0000 4 105 270 5400 2325 .sim\001 +-6 +6 7275 1950 8325 2550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 7575.000 2100.000 7350 2400 7575 2475 7800 2400 +5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 8025.000 2700.000 7800 2400 8025 2325 8250 2400 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 7350 2400 7350 1950 8250 1950 8250 2400 +4 1 0 50 -1 -1 10 0.0000 4 135 240 7800 2325 .cfg\001 +4 1 0 50 -1 -1 10 0.0000 4 135 885 7800 2100 Configuration\001 +-6 +6 6075 1950 7125 2550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 6375.000 2100.000 6150 2400 6375 2475 6600 2400 +5 1 0 1 0 2 48 -1 40 0.000 0 0 0 0 6825.000 2700.000 6600 2400 6825 2325 7050 2400 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 6150 2400 6150 1950 7050 1950 7050 2400 +4 1 0 50 -1 -1 10 0.0000 4 105 255 6600 2325 .gen\001 +4 1 0 50 -1 -1 10 0.0000 4 105 420 6600 2100 Limits\001 +-6 +6 4275 5100 5325 5700 +6 4275 5100 5325 5700 +5 1 0 1 0 2 50 -1 20 0.000 0 1 0 0 4575.000 5250.000 4350 5550 4575 5625 4800 5550 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 5025.000 5850.000 4800 5550 5025 5475 5250 5550 +2 1 0 1 0 2 50 -1 20 0.000 0 0 7 0 0 4 + 4350 5550 4350 5100 5250 5100 5250 5550 +-6 +4 1 0 50 -1 -1 10 0.0000 4 105 630 4800 5250 TestBench\001 +4 1 0 50 -1 -1 10 0.0000 4 105 435 4800 5475 VHDL\001 +-6 +6 5475 5100 6525 5700 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6225.000 5850.000 6000 5550 6225 5475 6450 5550 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 5775.000 5250.000 5550 5550 5775 5625 6000 5550 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 5550 5550 5550 5100 6450 5100 6450 5550 +4 1 0 50 -1 -1 10 0.0000 4 105 585 6000 5325 Statistics\001 +-6 +6 6075 4050 7125 4650 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 6825.000 4800.000 6600 4500 6825 4425 7050 4500 +5 1 0 1 0 29 50 -1 20 0.000 0 1 0 0 6375.000 4200.000 6150 4500 6375 4575 6600 4500 +2 1 0 1 0 29 50 -1 20 0.000 0 0 7 0 0 4 + 6150 4500 6150 4050 7050 4050 7050 4500 +4 1 0 50 -1 -1 10 0.0000 4 105 585 6600 4200 Positions\001 +4 1 0 50 -1 -1 10 0.0000 4 105 255 6600 4425 .pos\001 +-6 +6 4950 4050 5850 4500 +2 4 0 1 0 4 50 -1 20 0.000 0 0 7 0 0 5 + 5850 4050 4950 4050 4950 4500 5850 4500 5850 4050 +4 1 0 50 -1 -1 10 0.0000 4 135 555 5400 4275 SystemC\001 +-6 +6 3675 4050 4725 4650 +6 3675 4050 4725 4650 +5 1 0 1 0 2 50 -1 20 0.000 0 1 0 0 3975.000 4200.000 3750 4500 3975 4575 4200 4500 +5 1 0 1 0 2 49 -1 40 0.000 0 0 0 0 4425.000 4800.000 4200 4500 4425 4425 4650 4500 +2 1 0 1 0 2 50 -1 20 0.000 0 0 7 0 0 4 + 3750 4500 3750 4050 4650 4050 4650 4500 +-6 +4 1 0 50 -1 -1 10 0.0000 4 105 435 4200 4275 VHDL\001 +-6 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 3450 5400 4050 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5700 3450 6600 4050 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5100 3450 4200 4050 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 4500 6000 5100 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 4500 4800 5100 +2 1 0 1 0 26 50 -1 -1 0.000 0 0 -1 0 1 2 + 3 0 1.00 60.00 120.00 + 7500 3450 6600 4050 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 5550 3000 5550 2850 7650 2850 7650 3000 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 1 4 + 3 0 1.00 60.00 120.00 + 3 0 1.00 60.00 120.00 + 5250 3000 5250 2775 7950 2775 7950 3000 +2 4 2 1 0 6 51 -1 20 3.000 0 0 7 0 0 5 + 8550 2700 4650 2700 4650 3750 8550 3750 8550 2700 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 5 + 3 0 1.00 60.00 120.00 + 8250 3225 8850 3225 8850 1650 7800 1650 7800 1950 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 0 0 2 + 7800 2400 7800 2775 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 0 0 2 + 6600 2400 6600 2850 +2 1 0 1 0 11 50 -1 -1 3.000 0 0 -1 1 0 2 + 3 0 1.00 60.00 120.00 + 5400 2400 5400 3000 +4 1 0 50 -1 2 12 0.0000 0 180 735 6600 3300 Morpheo\001 Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0poster.cls =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0poster.cls (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0poster.cls (revision 91) @@ -0,0 +1,200 @@ +%% +%% This is file `a0poster.cls' +%% +%% Copyright (C) 07.05.97 Gerlinde Kettl and Matthias Weiser +%% +%% Problems, bugs and comments to +%% gerlinde.kettl@physik.uni-regensburg.de +%% +\ProvidesClass{a0poster}[1997/05/07 v1.21b a0poster class (GK, MW)] +\NeedsTeXFormat{LaTeX2e}[1995/06/01] +\LoadClass{article} + +\newif\ifportrait +\newif\ifanullb +\newif\ifanull +\newif\ifaeins +\newif\ifazwei +\newif\ifadrei +\newif\ifdraft + +\newcount\xkoord +\newcount\ykoord +\newcount\xscale +\newcount\yscale + +\DeclareOption{a0b}{ +\anullbtrue +\xkoord=2594 % big points (1 bp=1/72 inch) +\ykoord=3370 % big points (1 bp=1/72 inch) +\xscale=2 +\yscale=2 +} +\DeclareOption{a0}{ +\anulltrue\anullbfalse +\xkoord=2380 % big points (1 bp=1/72 inch) +\ykoord=3368 % big points (1 bp=1/72 inch) +\xscale=2 +\yscale=2 +} +\DeclareOption{a1}{ +\aeinstrue\anullbfalse +\xkoord=1684 % big points (1 bp=1/72 inch) +\ykoord=2380 % big points (1 bp=1/72 inch) +\xscale=3 +\yscale=3 +} +\DeclareOption{a2}{ +\azweitrue\anullbfalse +\xkoord=1190 % big points (1 bp=1/72 inch) +\ykoord=1684 % big points (1 bp=1/72 inch) +\xscale=4 +\yscale=4 + +} +\DeclareOption{a3}{ +\adreitrue\anullbfalse +\xkoord=842 % big points (1 bp=1/72 inch) +\ykoord=1190 % big points (1 bp=1/72 inch) +\xscale=6 +\yscale=6 +} +\DeclareOption{landscape}{ +\portraitfalse +} +\DeclareOption{portrait}{ +\portraittrue +} +\DeclareOption{draft}{ +\drafttrue +} +\DeclareOption{final}{ +\draftfalse +} +\DeclareOption*{\PackageWarning{a0poster}{Unknown Option \CurrentOption}} +\ExecuteOptions{landscape,a0b,final} +\ProcessOptions\relax + +\ifanullb + \setlength{\paperwidth}{119cm} + \setlength{\paperheight}{87cm} + \setlength{\textwidth}{114cm} + \setlength{\textheight}{87cm} +\else\ifanull + \setlength{\paperwidth}{118.82cm} + \setlength{\paperheight}{83.96cm} + \setlength{\textwidth}{114.82cm} + \setlength{\textheight}{79.96cm} + \else\ifaeins + \setlength{\paperwidth}{83.96cm} + \setlength{\paperheight}{59.4cm} + \setlength{\textwidth}{79.96cm} + \setlength{\textheight}{55.4cm} + \else\ifazwei + \setlength{\paperwidth}{59.4cm} + \setlength{\paperheight}{41.98cm} + \setlength{\textwidth}{55.4cm} + \setlength{\textheight}{37.98cm} + \else\ifadrei + \setlength{\paperwidth}{41.98cm} + \setlength{\paperheight}{29.7cm} + \setlength{\textwidth}{37.98cm} + \setlength{\textheight}{25.7cm} + \else\relax + \fi + \fi + \fi + \fi +\fi + + +\ifportrait + \newdimen\tausch + \setlength{\tausch}{\paperwidth} + \setlength{\paperwidth}{\paperheight} + \setlength{\paperheight}{\tausch} + \setlength{\tausch}{\textwidth} + \setlength{\textwidth}{\textheight} + \setlength{\textheight}{\tausch} +\else\relax +\fi + +%% Setting proper dimensions for a DIN A0 printer + +\setlength{\headheight}{0 cm} +\setlength{\headsep}{0 cm} +\setlength{\topmargin}{0 cm} +\setlength{\oddsidemargin}{0 cm} + +\catcode`\%=11 +\newwrite\Ausgabe +\immediate\openout\Ausgabe=a0header.ps +\write\Ausgabe{%%BeginFeature *PageSize ISOA0/ISO A0} +\ifdraft\write\Ausgabe{2 dict dup /PageSize [595 842] put dup /ImagingBBox null put} +\else\write\Ausgabe{2 dict dup /PageSize [\number\xkoord\space \number\ykoord] put dup /ImagingBBox null put}\fi +\write\Ausgabe{setpagedevice} +\ifdraft\write\Ausgabe{38 84 translate} +\write\Ausgabe{0.\number\xscale\space 0.\number\yscale\space scale}\else\relax\fi +\write\Ausgabe{%%EndFeature} +\closeout\Ausgabe +\catcode`\%=14 + +\special{header=./a0header.ps} + +\input{a0size.sty} + +\renewcommand{\tiny}{\fontsize{12}{14}\selectfont} +\renewcommand{\scriptsize}{\fontsize{14.4}{18}\selectfont} +\renewcommand{\footnotesize}{\fontsize{17.28}{22}\selectfont} +\renewcommand{\small}{\fontsize{20.74}{25}\selectfont} +%\renewcommand{\normalsize}{\fontsize{24.88}{30}\selectfont} +\renewcommand{\normalsize}{\fontsize{29.86}{37}\selectfont} + +\renewcommand{\large}{\fontsize{29.86}{37}\selectfont} +\renewcommand{\Large}{\fontsize{35.83}{45}\selectfont} +\renewcommand{\LARGE}{\fontsize{43}{54}\selectfont} +\renewcommand{\huge}{\fontsize{51.6}{64}\selectfont} +\renewcommand{\Huge}{\fontsize{61.92}{77}\selectfont} +\newcommand{\veryHuge}{\fontsize{74.3}{93}\selectfont} +\newcommand{\VeryHuge}{\fontsize{89.16}{112}\selectfont} +\newcommand{\VERYHuge}{\fontsize{107}{134}\selectfont} + +\setlength\smallskipamount{6pt plus 2pt minus 2pt} +\setlength\medskipamount{12pt plus 4pt minus 4pt} +\setlength\bigskipamount{24pt plus 8pt minus 8pt} + +\setlength\abovecaptionskip{25pt} +\setlength\belowcaptionskip{0pt} +\setlength\abovedisplayskip{25pt plus 6pt minus 15 pt} +\setlength\abovedisplayshortskip{0pt plus 6pt} +\setlength\belowdisplayshortskip{13pt plus 7pt minus 6pt} +\setlength\belowdisplayskip\abovedisplayskip + +\normalsize + +\AtBeginDocument{ +\ifanullb + \ifportrait\special{papersize=91.51cm,120cm}\else\special{papersize=120cm,91.51cm}\fi +\else\ifanull + \ifportrait\special{papersize=83.96cm,118.82cm}\else\special{papersize=118.82cm,83.96cm}\fi + \else\ifaeins + \ifportrait\special{papersize=59.4cm,83.96cm}\else\special{papersize=83.96cm,59.4cm}\fi + \else\ifazwei + \ifportrait\special{papersize=41.98cm,59.4cm}\else\special{papersize=59.4cm,41.98cm}\fi + \else\ifadrei + \ifdraft + \ifportrait\special{papersize=29.7cm,41.35cm}\else\special{papersize=41.98cm,29.0cm}\fi + \else + \ifportrait\special{papersize=29.7cm,41.98cm}\else\special{papersize=41.98cm,29.7cm}\fi + \fi + \else\relax + \fi + \fi + \fi + \fi +\fi +\pagestyle{empty}} + +\endinput +%% +%% End of file `a0poster.cls'. Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0size.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0size.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/a0size.sty (revision 91) @@ -0,0 +1,241 @@ +%% +%% This is file `a0size.sty' (v1.21b) included in the a0poster package +%% +%% Copyright (C) 07.05.97 Gerlinde Kettl and Matthias Weiser +%% + +\ProvidesFile{a0size.sty}[1997/05/06 v1.21b a0poster class (GK, MW)] + +\DeclareFontShape{OT1}{cmr}{m}{n} + { <5> <6> <7> <8> <9> <10> <12> gen * cmr + <10.95> cmr10 + <14.4> cmr12 + <17.28><20.74><24.88>cmr17 + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmr17}{} + +\DeclareFontShape{OT1}{cmr}{m}{sl} + { + <5><6><7>cmsl8% + <8> <9> gen * cmsl + <10><10.95>cmsl10% + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmsl12}{} + +\DeclareFontShape{OT1}{cmr}{m}{it} + { + <5><6><7>cmti7% + <8>cmti8% + <9>cmti9% + <10><10.95>cmti10% + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmti12}{} + +\DeclareFontShape{OT1}{cmr}{m}{sc} + { + <5><6><7><8><9><10><10.95><12> + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmcsc10}{} + +\DeclareFontShape{OT1}{cmr}{m}{ui} + { + <5><6><7><8><9><10><10.95><12> + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmu10}{} + +\DeclareFontShape{OT1}{cmr}{b}{n} + { + <5><6><7><8><9><10><10.95><12> + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmb10}{} + +\DeclareFontShape{OT1}{cmr}{bx}{n} + { + <5> <6> <7> <8> <9> gen * cmbx + <10><10.95> cmbx10 + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbx12}{} + +\DeclareFontShape{OT1}{cmr}{bx}{sl} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbxsl10}{} + +\DeclareFontShape{OT1}{cmr}{bx}{it} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbxti10}{} + +\DeclareFontShape{OT1}{cmss}{m}{n} + { + <5><6><7><8>cmss8 + <9>cmss9 + <10><10.95>cmss10 + <12><14.4>cmss12 + <17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmss17}{} + +\DeclareFontShape{OT1}{cmss}{m}{sl} + { + <5><6><7><8>cmssi8 <9> cmssi9 + <10><10.95>cmssi10 + <12><14.4>cmssi12 + <17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmssi17}{} + +\DeclareFontShape{OT1}{cmss}{sbc}{n} + { + <5> <6> <7> <8> <9> cmssdc10 + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmssdc10}{} + +\DeclareFontShape{OT1}{cmss}{bx}{n} + { + <5> <6> <7> <8> <9> cmssbx10 + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmssbx10}{} + +\DeclareFontShape{OT1}{cmtt}{m}{n} + { + <5><6><7><8>cmtt8 <9> cmtt9 + <10><10.95>cmtt10 + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmtt12}{} + +\DeclareFontShape{OT1}{cmtt}{m}{it} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmitt10}{} + +\DeclareFontShape{OT1}{cmtt}{m}{sl} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmsltt10}{} + +\DeclareFontShape{OT1}{cmtt}{m}{sc} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmtcsc10}{} + +\DeclareFontShape{OML}{cmm}{m}{it} + { <5> <6> <7> <8> <9> gen * cmmi + <10><10.95>cmmi10 + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmmi12}{} + +\DeclareFontShape{OML}{cmm}{b}{it}{% + <5> <6> <7> <8> <9> gen * cmmib + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmmib10}{} + + +\DeclareFontShape{OMS}{cmsy}{m}{n}{% + <5> <6> <7> <8> <9> <10> gen * cmsy + <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmsy10}{} + +\DeclareFontShape{OMS}{cmsy}{b}{n}{% + <5> <6> <7> <8> <9> gen * cmbsy + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbsy10}{} + +\DeclareFontShape{OMX}{cmex}{m}{n}{% + <-8>sfixed * cmex7 + <8> cmex8 + <9> cmex9 + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmex10}{} + +\DeclareFontShape{U}{cmr}{m}{n} + { <5> <6> <7> <8> <9> <10> <12> gen * cmr + <10.95> cmr10 + <14.4> cmr12 + <17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmr17}{} + +\DeclareFontShape{U}{cmr}{m}{sl} + { + <5><6><7>cmsl8% + <8> <9> gen * cmsl + <10><10.95>cmsl10% + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmsl12}{} + +\DeclareFontShape{U}{cmr}{m}{it} + { + <5><6><7>cmti7% + <8>cmti8% + <9>cmti9% + <10><10.95>cmti10% + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmti12}{} + +\DeclareFontShape{U}{cmr}{m}{sc} + { + <5><6><7><8><9><10><10.95><12> + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmcsc10}{} + +\DeclareFontShape{U}{cmr}{m}{ui} + { + <5><6><7><8><9><10><10.95><12>% + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmu10}{} + +\DeclareFontShape{U}{cmr}{b}{n} + { + <5><6><7><8><9><10><10.95><12> + <14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmb10}{} + +\DeclareFontShape{U}{cmr}{bx}{n} + { + <5> <6> <7> <8> <9> gen * cmbx + <10><10.95> cmbx10 + <12><14.4><17.28><20.74><24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbx12}{} + +\DeclareFontShape{U}{cmr}{bx}{sl} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbxsl10}{} + +\DeclareFontShape{U}{cmr}{bx}{it} + { + <5> <6> <7> <8> <9> + <10> <10.95> <12> <14.4> <17.28> <20.74> <24.88> + <29.86> <35.83> <43.00> <51.6> <61.92> <74.3> <89.16> <107.0> cmbxti10}{} + +%% Copied from exscale.sty +%% Copyright (C) 1992-1995 Frank Mittelbach and Rainer Sch\"opf, +%% all rights reserved. + +\DeclareSymbolFont{largesymbols}{OMX}{cmex}{m}{n} +\newdimen\big@size +\addto@hook\every@math@size{\setbox\z@\vbox{\hbox{$($}\kern\z@}% + \global\big@size 1.2\ht\z@} +\def\bBigg@#1#2{% + {\hbox{$\left#2\vcenter to#1\big@size{}\right.\n@space$}}} +\def\big{\bBigg@\@ne} +\def\Big{\bBigg@{1.5}} +\def\bigg{\bBigg@\tw@} +\def\Bigg{\bBigg@{2.5}} + +%% End of copy + +\DeclareMathSizes{24.88}{24.88}{20.74}{14.4} +\DeclareMathSizes{29.86}{29.86}{20.74}{14.4} +\DeclareMathSizes{35.83}{35.83}{24.88}{17.28} +\DeclareMathSizes{43.00}{43.00}{35.83}{24.88} +\DeclareMathSizes{51.6}{51.6}{35.83}{24.88} +\DeclareMathSizes{61.92}{61.92}{43}{29.86} +\DeclareMathSizes{74.3}{74.3}{51.6}{35.83} +\DeclareMathSizes{89.16}{89.16}{61.92}{43} +\DeclareMathSizes{107}{107}{74.3}{51.6} + +%% End of a0size.sty Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty (revision 91) @@ -0,0 +1,206 @@ +\typeout{Fichier de style `doc-style.sty'.} + +\usepackage{makeidx} +\usepackage{palatino} +%\usepackage{fancyheadings} +\usepackage{float} +\usepackage{verbatim} +\usepackage{subfigure} +\usepackage{wrapfig} +\usepackage[dvips]{graphics} +\usepackage{graphicx} +\usepackage[french]{babel} +\usepackage[french]{minitoc} +%\usepackage[T1]{fontenc} +\usepackage[T1]{fontenc} % Pour afficher en DVI ou PDF les accents +\usepackage[latin1]{inputenc} % Car j’écris selon le jeu de caractÚres ISO-8859-1 +%\usepackage[utf8]{inputenc} % Car j’écris selon le jeu de caractÚres UTF-8 + +\usepackage{openbib} +\usepackage{fancyhdr} + +\bibliographystyle{abbrv} + +%\newif\iflangXX % change XX, by the language code (in upper case) +\newif\iflangEN +\newif\iflangFR + +% Titres de figures en 9 points helvetica gras +% choisissez selon votre installation LaTeX +\font\tenhv = phvb at 8pt +\font\tenhv = phvb7t at 8pt + +% Fontes en 11 points gras pour les titres de deuxiÚme niveau +% \font\elvbf = cmbx10 scaled 1100 +\font\elvbf = ptmb scaled 1100 + +% Dimensions des colonnes, espace entre colonnes, et indentation des +% paragraphes + +\setlength{\hoffset}{-18pt} +\setlength{\oddsidemargin}{0pt} % Marge gauche sur pages impaires +\setlength{\evensidemargin}{9pt} % Marge gauche sur pages paires +\setlength{\topmargin}{0pt} % Pas de marge en haut +\setlength{\marginparwidth}{54pt} % Largeur de note dans la marge +\setlength{\textwidth}{481pt} % Largeur de la zone de texte (17cm) +\setlength{\voffset}{-18pt} % Bon pour DOS +\setlength{\marginparsep}{7pt} % Séparation de la marge +\setlength{\headheight}{13pt} % Haut de page +\setlength{\headsep}{10pt} % Entre le haut de page et le texte +\setlength{\footskip}{27pt} % Bas de page + séparation +\setlength{\textheight}{708pt} % Hauteur de la zone de texte (25cm) + +%%\setlength{\topsep}{0pt}% +%%\setlength{\parsep}{0pt plus 1pt}% +%\setlength{\columnsep}{10mm} +% +%\setlength{\parindent}{1pc} +%\setlength{\listparindent}{\parindent}% +%\setlength{\itemindent}{\parindent}% + +% Rappel: size10.clo + +% \normalsize{\@setfontsize\normalsize\@xpt\@xiipt} +% \small{\@setfontsize\small\@ixpt{11}} +% \footnotesize{\@setfontsize\footnotesize\@viiipt{9.5}} +% \scriptsize{\@setfontsize\scriptsize\@viipt\@viiipt} +% \tiny{\@setfontsize\tiny\@vpt\@vipt} +% \large{\@setfontsize\large\@xiipt{14}} +% \Large{\@setfontsize\Large\@xivpt{18}} +% \LARGE{\@setfontsize\LARGE\@xviipt{22}} +% \huge{\@setfontsize\huge\@xxpt{25}} +% \Huge{\@setfontsize\Huge\@xxvpt{30}} + + +%% % file, Dimension, légende +\newcommand{\printgraph}[3] + {\begin{figure}[htbp] + \centering + \includegraphics#2{\dirschema/#1.eps} + \caption{#3} + \label{#1} + \end{figure} + } + +\newcommand{\TODO}[1] + { + {\bf + {\it + \begin{center} + !!!!! TODO !!!!!\\ + #1\\ + \end{center} + } + } + } + + +\def\@maketitle + { + \newpage +% \null + \vskip 1cm + \begin{center} + {\Large \bf \@title \par} + % Deux lignes vides aprÚs le titre + \vspace*{24pt} + { + \large + \lineskip .5em + \begin{tabular}[t]{c} + \@author + \end{tabular} + \par + } + % Un peu d'espace aprÚs le nom des auteurs + \vskip .5em + { + \large + \begin{tabular}[t]{c} + \@affiliation + \end{tabular} + \par + \ifx \@empty \@email + \else + \begin{tabular}{r@{~}l} + E-mail: & {\tt \@email} + \end{tabular} + \par + \fi + \begin{tabular}{r@{~}l} + {\tt \@date} + \end{tabular} + \par + } + % Une ligne vide aprÚs le bloc de titre + \vspace*{12pt} + \end{center} + } + +\def\abstract + {% + \centerline{\large\bf R\'esum\'e}% + \vspace*{12pt}% + \it% + } + +\def\endabstract + { + % Une ligne vide aprÚs le résumé + \vspace*{12pt} + } + +% On traduit 'Référence' +%\renewcommand\refname{R\'ef\'erences} + +\def\affiliation#1{\gdef\@affiliation{#1}} +\gdef\@affiliation{} + +\def\email#1{\gdef\@email{#1}} +\gdef\@email{} + +\newlength{\@ctmp} +\newlength{\@figindent} +\setlength{\@figindent}{1pc} + +\long\def\@makecaption#1#2{ + \vskip 10pt + + \setbox\@tempboxa\hbox{\tenhv\noindent #1.~#2} + \setlength{\@ctmp}{\hsize} + \addtolength{\@ctmp}{-\@figindent}\addtolength{\@ctmp}{-\@figindent} + % SI c'est plus long qu'une ligne indentée + \ifdim \wd\@tempboxa >\@ctmp + % ALORS on définit un paragraphe indenté + \begin{list}{}{\leftmargin\@figindent \rightmargin\leftmargin} + \item[]\tenhv #1.~#2\par + \end{list} + \else + % SINON centrer + \hbox to\hsize{\hfil\box\@tempboxa\hfil} + \fi} + +% Type et espacement des en-têtes + +\def\section{\@startsection {section}{1}{\z@} + {14pt plus 2pt minus 2pt}{14pt plus 2pt minus 2pt} {\large\bf}} +\def\subsection{\@startsection {subsection}{2}{\z@} + {13pt plus 2pt minus 2pt}{13pt plus 2pt minus 2pt} {\elvbf}} + +\renewcommand\subsubsection{\@startsection {subsubsection}{1}{\z@}% + {12pt \@plus -1ex \@minus -.2ex}{-2mm} + {\reset@font\normalsize\bfseries}} +% On ajoute un point aprÚs le numéro de section + +\newcommand{\Chapter}[1]{\chapter{#1}} +\newcommand{\CHapter}[1]{\chapter*{#1}} +\newcommand{\Section}[1]{\section{#1}} +\newcommand{\SEction}[1]{\section*{#1}} +\newcommand{\subSection}[1]{\subsection{#1}} +\newcommand{\subSEction}[1]{\subsection*{#1}} +\newcommand{\subsubSection}[1]{\subsubsection{#1}} +\newcommand{\subsubSEction}[1]{\subsubsection*{#1}} +\newcommand{\subsubsubSection}[1]{\subsubSEction{#1}} + +\def\registered{{\ooalign {\hfil\raise .05ex\hbox{\scriptsize +R}\hfil\crcr\mathhexbox20D}}} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/poster-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/poster-style.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/poster-style.sty (revision 91) @@ -0,0 +1,196 @@ +\usepackage{epsfig} +\usepackage{multicol} +\usepackage{pstricks,pst-grad} +\usepackage[french]{babel} +\usepackage[latin1]{inputenc} % Pour utiliser les caractères accentués dans votre texte +\usepackage{openbib} + +\bibliographystyle{abbrv} + +%\newif\iflangXX % change XX, by the language code (in upper case) +\newif\iflangEN +\newif\iflangFR + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Definition of some variables and colors +%\renewcommand{\rho}{\varrho} +%\renewcommand{\phi}{\varphi} +\setlength{\columnsep}{3cm} +\setlength{\columnseprule}{2mm} +\setlength{\parindent}{0.0cm} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% Background %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newrgbcolor{cellLineColor}{.7. .7 .9} % lightblue +\newrgbcolor{cellGradBegin}{1. 1. 1.} % white +\newrgbcolor{cellGradEnd}{.5 .5 1.} % whiteblue +\newrgbcolor{backgroundGradBegin}{1. 1. 1.} % grabbegin +\newrgbcolor{backgroundGradEnd}{1. 1. 1.} % cellGradEnd + +\newcommand{\background}[1] + { + \psframe[fillstyle=gradient,gradbegin=backgroundGradBegin,gradend=backgroundGradEnd,gradmidpoint=#1](0.,0.)(1.\textwidth,-1.\textheight) + } + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% Poster %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{poster}{\begin{center} \begin{minipage}[c]{0.98\textwidth}}{\end{minipage} \end{center}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% pcolumn %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newenvironment{pcolumn}[1]{\begin{minipage}{#1\textwidth}\begin{center}}{\end{center}\end{minipage}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% pbox %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newcommand{\pbox}[4]{\psshadowbox[#3]{\begin{minipage}[t][#2][t]{#1}#4\end{minipage}}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%% myfig %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% \myfig - replacement for \figure +%% necessary, since in multicol-environment +%% \figure won't work +% +%\newcommand{\myfig}[3][0] +% { +% \begin{center} +% \vspace{1.5cm} +% \includegraphics[width=#3\hsize,angle=#1]{#2} +% \nobreak\medskip +% \end{center} +% } + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%% mycaption %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%% \mycaption - replacement for \caption +%% necessary, since in multicol-environment \figure and +%% therefore \caption won't work +% +%%\newcounter{figure} +%\setcounter{figure}{1} +%\newcommand{\mycaption}[1] +% { +% \vspace{1.5cm} +% \begin{quote} +% { +% {\sc Figure} +% \arabic{figure}: #1 +% } +% \end{quote} +% \vspace{1.5cm} +% \stepcounter{figure} +% } + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% printgraph %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +%% % file, Dimension, légende +\newcommand{\printgraph}[3] + { + %\vspace*{1cm} + \begin{center} + \includegraphics[width=\columnwidth]{\dirschema/#1.eps} + \label{#1} + \nobreak\medskip + \end{center} + %\vspace*{1cm} + +% \begin{figure}[htbp] +% \centering +% \includegraphics[scale=#2]{\dirschema/#1.eps} +% \caption{#3} +% \label{#1} +% \end{figure} + } + +\newcommand{\printgraphonly}[2] + {\begin{figure}[htbp] + \centering + \includegraphics[scale=#2]{\dirschema/#1.eps} + \label{#1} + \end{figure} + } + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% Section %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\newcommand{\BoxSection}[2] + { + \vspace*{1cm} + \begin{center} + \pbox{#2} + {} + {linewidth=2mm,framearc=0.1,linecolor=cellLineColor,fillstyle=gradient,gradangle=0,gradbegin=cellGradBegin,gradend=cellGradEnd,gradmidpoint=1.0,framesep=1em} + { + \begin{center} + #1 + \end{center} + } + \end{center} + \vspace*{1cm} + } + +%\newcommand{\Title}[1]{\BoxSection{#1}{0.8\textwidth}} +\newcommand{\Section}[1]{\BoxSection{#1}{0.8\columnwidth}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% cell %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand{\Cell}[1]{\pbox{0.9\textwidth}{}{linewidth=2mm,framearc=0.1,linecolor=cellLineColor,fillstyle=gradient,gradangle=0,gradbegin=cellGradBegin,gradend=cellGradEnd,gradmidpoint=1.0,framesep=1em}{#1}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%% maketitle %%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\def\affiliation#1{\gdef\@affiliation{#1}} +\gdef\@affiliation{} + +\def\email#1{\gdef\@email{#1}} +\gdef\@email{} + +\def\@maketitle + { + \vspace*{1cm} + \begin{center} + \begin{pcolumn}{0.98} + \pbox{0.95\textwidth}{}{linewidth=2mm,framearc=0.3,linecolor=cellLineColor,fillstyle=gradient,gradangle=0,gradbegin=cellGradBegin,gradend=cellGradEnd,gradmidpoint=1.0,framesep=1em} + { + %%% Logo gauche + \begin{minipage}[c][9cm][c]{0.1\textwidth} + \begin{center} + % \includegraphics[width=7cm,angle=0]{gklogo.eps} + \end{center} + \end{minipage} + %%% Titel + \begin{minipage}[c][9cm][c]{0.78\textwidth} + \begin{center} + {\sc \Huge \@title}\\[10mm] + {\Large \@author\\[7.5mm] + \@email\\[7.5mm] + \@affiliation} + \end{center} + \end{minipage} + %%% Logo droit + \begin{minipage}[c][9cm][c]{0.1\textwidth} + \begin{center} + % \includegraphics[width=7cm,angle=0]{gklogo.eps} + \end{center} + \end{minipage} + } + \end{pcolumn} + \end{center} + \vspace*{1cm} + } + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/ppt-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/ppt-style.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/ppt-style.sty (revision 91) @@ -0,0 +1,68 @@ +\typeout{Fichier de style `ppt-style.sty'.} + +\usepackage{beamerarticle} +\usepackage{graphicx} +\usepackage{tabularx} +\usepackage{verbatim} +\usepackage{picinpar} +\usepackage[latin1]{inputenc} +\usepackage[french]{babel} +\usepackage{pgf,pgfarrows,pgfheaps,pgfnodes,pgfpages,pgfshade} +\usepackage{openbib} +\usepackage{ulem} + +\bibliographystyle{abbrv} + +%\newif\iflangXX % change XX, by the language code (in upper case) +\newif\iflangEN +\newif\iflangFR + +\addtobeamertemplate{footline}{\insertframenumber/\inserttotalframenumber} + +%\setbeameroption{show notes on second screen} + +%\useoutertheme{splitbarsbackground} +%\usetheme{Darmstadt} +%\usetheme{Malmoe} +%\usetheme{Copenhagen} + +%\usebackgroundtemplate{\includegraphics[height=\paperheight] {Include/background}} + +\setlength{\parindent}{0pt} +\setlength{\parskip}{0pt} + +%% % file, Dimension +\newcommand{\printgraph}[2] + {\begin{figure}[htbp] + \centering + \includegraphics[scale=#2]{\dirschema/#1.eps} + \label{#1} + \end{figure} + } + +\newcommand{\slide}[2] + { + \frame{#1} + \note{#2} + } + +\newcommand{\slidetitle}[3] + { + \slide{\frametitle{#1}#2}{#3} + } + +\newcommand{\Contents} + { + \frame + { + \tableofcontents + } + } + +\newcommand{\ContentsCurrent} + { + \frame + { + \tableofcontents[currentsection] + } + } Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/Makefile (revision 91) @@ -0,0 +1,22 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = ../.. + +#-----[ include ]------------------------------------------ + +all : + @\ + $(MAKE) all_documentation + +view : view_local + +local_clean : + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/document.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/document.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/document.tex (revision 91) @@ -0,0 +1,49 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass[10pt,a4paper,twocolumn]{article} + +\def\lang{fr} +\def\dirroot{tex} +\def\dirschema{eps} +\def\dircommon{../../common} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../sty/doc-style} + +%document-style list language (Change this file to add language) +\langFRtrue + +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{fancy} % default style + +\begin{document} + +% Créez une page de titre +\maketitle +%\thispagestyle{empty} + +%Table des matières et des figures +%\tableofcontents +%\newpage +%\listoffigures + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{\dirroot/root} +%\bibliography{\dircommon/bibliography} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/sty/header.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/sty/header.sty (revision 91) @@ -0,0 +1,19 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} +\date{\review} + +\iflangFR + \title{} + \author{} + \affiliation{} + \email{} +\else % Others language + \title{} + \author{} + \affiliation{} + \email{} +\fi Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/tex/root.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/document/tex/root.tex (revision 91) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +%\input{\dirdoc/01_introduction} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/Makefile (revision 91) @@ -0,0 +1,23 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = ../.. + +#-----[ include ]------------------------------------------ + +all : + @\ + $(MAKE) all_documentation + +view : view_local + +local_clean : + $(RM) a0header.ps + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/poster.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/poster.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/poster.tex (revision 91) @@ -0,0 +1,54 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +%\documentclass[landscape,a0b,final,a4resizeable]{a0poster} +\documentclass[landscape,a0b,final]{a0poster} +%\documentclass[portrait,a0b,final,a4resizeable]{a0poster} +%\documentclass[portrait,a0b,final]{a0poster} +%%% Option "a4resizeable" makes it possible ot resize the +% poster by the command: psresize -pa4 poster.ps poster-a4.ps +% For final printing, please remove option "a4resizeable" !! + +\def\dirroot{tex} +\def\dirschema{eps} +\def\dircommon{../../common} + +% Package de variables d'environnement : Titre, command etc ... +\pagestyle{empty} +\usepackage{../../sty/poster-style} + +%poster-style list language (Change this file to add language) +\langFRtrue + +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\pagestyle{empty} + +\begin{document} + +%\background{1.} + +\begin{poster} + +\maketitle + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{\dirroot/root} +%\bibliography{\dircommon/bibliography} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{poster} +\end{document} + Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/sty/header.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/sty/header.sty (revision 91) @@ -0,0 +1,19 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} +\date{\review} + +\iflangFR + \title{~} + \author{~} + \affiliation{~} + \email{~} +\else % Others language + \title{~} + \author{~} + \affiliation{~} + \email{~} +\fi Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/tex/root.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/poster/tex/root.tex (revision 91) @@ -0,0 +1,9 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +%\setlength{\columnseprule}{0pt} +%\renewcommand{\labelitemi}{$\star$} +%\renewcommand{\labelitemii}{$\star$} + +%\input{\dirdoc/01_introduction} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/Makefile (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/Makefile (revision 91) @@ -0,0 +1,22 @@ +# +# $Id$ +# +# [ Description ] +# +# Makefile +# + +#-----[ directory ]---------------------------------------- +DIR_DOCUMENTATION = ../.. + +#-----[ include ]------------------------------------------ + +all : + @\ + $(MAKE) all_documentation + +view : view_local + +local_clean : + +include $(DIR_DOCUMENTATION)/Makefile.Documentation Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/presentation.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/presentation.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/presentation.tex (revision 91) @@ -0,0 +1,46 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\documentclass{beamer} + +\usepackage{beamerthemetree} + +%\setbeameroption{show notes on second screen} + +\def\dirroot{tex} +\def\dirschema{eps} +\def\dircommon{../../common} + +% Package de variables d'environnement : Titre, command etc ... +\usepackage{../../sty/ppt-style} + +%presentation-style list language (Change this file to add language) +\langFRtrue + +\usepackage{sty/header} + + +%------------------------------------------------------------------------------ +% Début document +%------------------------------------------------------------------------------ + +\begin{document} + +%Slide de Titre +\frame{\titlepage} + +\Contents + +%------------------------------------------------------------------------------ +% Ajout du corps du documents +%------------------------------------------------------------------------------ + +\input{\dirroot/root} +%\bibliography{\dircommon/bibliography} + +%------------------------------------------------------------------------------ +% Fin d'ajout du corps du document +%------------------------------------------------------------------------------ + +\end{document} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/sty/header.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/sty/header.sty (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/sty/header.sty (revision 91) @@ -0,0 +1,17 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +\def\review{YYYY/MM/DD} +%\def\review{\number\day/\number\month/\number\year\xspace} +\date{\review} + +\iflangFR + \title{~} + \author{} + \institute{} +\else % Others language + \title{~} + \author{} + \institute{} +\fi Index: trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/tex/root.tex =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/tex/root.tex (revision 91) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/template/presentation/tex/root.tex (revision 91) @@ -0,0 +1,5 @@ +%------------------------------------------------------------------------------ +% $Id$ +%------------------------------------------------------------------------------ + +%\input{\dirdoc/01_introduction} Index: trunk/IPs/systemC/processor/Morpheo/Makefile =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Makefile (revision 90) +++ trunk/IPs/systemC/processor/Morpheo/Makefile (revision 91) @@ -14,5 +14,5 @@ #-----[ Directory ]---------------------------------------------------- -DIR_DOC = ./Documentation/Source +DIR_DOC = ./Documentation/ DIR_LOCALE = ./locale