Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Dcache_Access/src/Dcache_Access_genMealy_rsp.cpp	(revision 94)
@@ -56,5 +56,5 @@
 	      throw ERRORMORPHEO(FUNCTION,_("invalid load_store_unit_id.\n"));
 
-	    if (context_id > _param->_nb_context[execute_loop_id][load_store_unit_id])
+	    if (context_id > _param->_nb_context[execute_loop_id])
 	      throw ERRORMORPHEO(FUNCTION,_("invalid context_id.\n"));
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg	(revision 94)
@@ -2,5 +2,5 @@
 1	1	+1	# nb_context             
 4	8	*2	# size_upt_queue         [0] [nb_context]
-1	4	*2	# size_ufpt_queue        [0] [nb_context]
+1	4	+1	# size_ufpt_queue        [0] [nb_context]
 32	32	*2	# size_address           
 4	4	*4	# nb_inst_predict        
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg	(revision 94)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg	(revision 94)
@@ -0,0 +1,11 @@
+Update_Prediction_Table
+1	1	+1	# nb_context             
+4	4	*2	# size_upt_queue         [0] [nb_context]
+1	1	+1	# size_ufpt_queue        [0] [nb_context]
+32	32	*2	# size_address           
+4	4	*4	# nb_inst_predict        
+4	4	*4	# nb_inst_decod          
+4	4	*4	# nb_inst_branch_complete
+4	4	*4	# nb_inst_update         
+0	0	+1	# size_history           
+3	3	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp	(revision 94)
@@ -116,4 +116,5 @@
 //   ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t         ,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC    ,"out_BRANCH_EVENT_ADDRESS_SRC    ",Taddress_t         ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t         ,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST   ,"out_BRANCH_EVENT_ADDRESS_DEST   ",Taddress_t         ,_param->_nb_context);
 
@@ -130,4 +131,5 @@
   ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY             ,"out_UPDATE_DIR_HISTORY             ",Thistory_t         ,_param->_nb_inst_update);
   ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL                 ,"out_UPDATE_RAS_VAL                 ",Tcontrol_t         ,_param->_nb_inst_update);
+  ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH               ,"out_UPDATE_RAS_FLUSH               ",Tcontrol_t         ,_param->_nb_inst_update);
   ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH                ,"out_UPDATE_RAS_PUSH                ",Tcontrol_t         ,_param->_nb_inst_update);
   ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS             ,"out_UPDATE_RAS_ADDRESS             ",Taddress_t         ,_param->_nb_inst_update);
@@ -201,4 +203,5 @@
 //   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC    ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST   ,_param->_nb_context);
 
@@ -217,4 +220,5 @@
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY             ,_param->_nb_inst_update);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL                 ,_param->_nb_inst_update);
+  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH               ,_param->_nb_inst_update);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH                ,_param->_nb_inst_update);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS             ,_param->_nb_inst_update);
@@ -247,9 +251,14 @@
   const  int32_t percent_transaction_branch_complete = 75;
   const  int32_t percent_transaction_update          = 75;
-
-
+  const  int32_t percent_transaction_branch_event    = 75;
+
+  const bool     test1 = false;
+  const bool     test2 = false;
+  const bool     test3 = false;
+  const bool     test4 = true;
 
   std::list<request_t> ufpt;
   std::list<request_t> upt;
+  request_t            event;
 
   SC_START(0);
@@ -302,6 +311,6 @@
       //---------------------------------------------------------------------
       //---------------------------------------------------------------------
-      if (1)
-      {
+      if (test1)
+        {
 	uint32_t context = rand() % _param->_nb_context;
 
@@ -508,12 +517,8 @@
 	  for (uint32_t i=0; i<upt.size(); i++)
 	    {
-              LABEL("Address_src (-1): %.8x (%d)",out_UPDATE_BTB_ADDRESS_SRC [i]->read(),upt.size());
-
 	      bool have_transaction = false;
 
 	      do
 		{
-                  LABEL("Address_src (0) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
-
 		  in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
 
@@ -522,8 +527,6 @@
 //                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
 		  
-                  LABEL("Address_src (1) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
 		  SC_START(0);
-                  LABEL("Address_src (2) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
-		  
+
 		  LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
 		  
@@ -534,25 +537,26 @@
 		  
                       if (_param->_have_port_context_id)
-                      TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [i]->read(),it_upt->context);
-                      TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [i]->read(),it_upt->miss_commit);
-                      TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [i]->read(),it_upt->flag);
-                      TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [i]->read(),update_btb(it_upt->condition));
+                      TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_upt->context);
+                      TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),it_upt->miss_commit);
+                      TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_upt->take_good);
+                      TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),update_btb(it_upt->condition));
                       if (update_btb(it_upt->condition))
                         {
-                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [i]->read(),it_upt->address_src);
-                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [i]->read(),it_upt->address_dest);
-                      TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [i]->read(),it_upt->condition);
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_upt->address_src);
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_upt->address_dest);
+                      TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_upt->condition);
                         }
-                      TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [i]->read(),update_dir(it_upt->condition));
+                      TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
                       if (update_dir(it_upt->condition))
                       if (_param->_have_port_history)
-                      TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [i]->read(),it_upt->history);
-                      TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [i]->read(),update_ras(it_upt->condition));
+                      TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_upt->history);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_upt->condition));
                       if (update_ras(it_upt->condition))
                         {
-                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [i]->read(),push_ras  (it_upt->condition));
-                      TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [i]->read(),it_upt->ras_address);
-                      TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [i]->read(),it_upt->ras_index);
-                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [i]->read(),not it_upt->miss_ifetch);
+//                    TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_upt->condition));
+                      TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_upt->ras_address);
+                      TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_upt->ras_index);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
                         }
                       ++ it_upt;
@@ -560,11 +564,7 @@
 
 		  SC_START(1);
-                  LABEL("Address_src (3) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
-                  
 		} while (not have_transaction);
 
-              LABEL("Address_src (4) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
 	      in_UPDATE_ACK [port]->write(0);
-              LABEL("Address_src (5) : %.8x",out_UPDATE_BTB_ADDRESS_SRC [i]->read());
 //               if (_param->_have_port_depth)
 //               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
@@ -586,4 +586,1352 @@
       }
 
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      // DECOD MISS : no RAS in ifetch
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      if (test2)
+        {
+	uint32_t context = rand() % _param->_nb_context;
+
+	{
+          LABEL("PREDICT - fill the queue");
+	  uint32_t port = rand() % _param->_nb_inst_predict;
+
+          LABEL("  * context : %d",context);
+          LABEL("  * port    : %d",port);
+	  
+	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+	    {
+              request_t request;
+              request.context          = context;
+              request.address_src      = 0xdeadbeef+i;
+              request.address_dest     = 0x21071981+i;                                   
+              request.address_good     = request.address_dest;
+              request.condition        = BRANCH_CONDITION_FLAG_SET;                      
+              request.take             = 1;                                              
+              request.take_good        = 1;                                              
+              request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+              request.is_accurate      = true;
+              request.miss_ifetch      = false;
+              request.miss_decod       = false;
+              request.miss_commit      = false;
+              request.history          = i;                                              
+              request.ras_address      = 0xdeaddead+i;                                   
+              request.ras_index        = (0x12345678+i)%_param->_size_ras_index[context];
+              request.ufpt_ptr         = ufpt_top [context];
+//            request.upt_ptr;
+
+	      bool have_transaction = false;
+	      do
+		{
+		  in_PREDICT_VAL              [port]->write((rand()%100)<percent_transaction_predict);
+		  in_PREDICT_CONTEXT_ID       [port]->write(request.context     );
+		  in_PREDICT_BTB_ADDRESS_SRC  [port]->write(request.address_src );
+		  in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
+		  in_PREDICT_BTB_CONDITION    [port]->write(request.condition   );
+		  in_PREDICT_BTB_LAST_TAKE    [port]->write(request.take        );
+		  in_PREDICT_BTB_IS_ACCURATE  [port]->write(request.is_accurate );
+		  in_PREDICT_DIR_HISTORY      [port]->write(request.history     );
+		  in_PREDICT_RAS_ADDRESS      [port]->write(request.ras_address );
+		  in_PREDICT_RAS_INDEX        [port]->write(request.ras_index   );
+		  
+		  if (_param->_have_port_depth)
+		  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                  TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		      
+		  SC_START(0); // fct melay
+		  
+		  LABEL("PREDICT         [%d] %d - %d (accurate : %d).",
+                        port,
+                         in_PREDICT_VAL [port]->read(),
+                        out_PREDICT_ACK [port]->read(),
+                         in_PREDICT_BTB_IS_ACCURATE [port]->read());
+		  
+		  if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
+		    {
+		      LABEL("PREDICT         [%d] - Transaction accepted",port);
+		      have_transaction = true;
+
+                      if (_param->_have_port_depth)
+                      TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
+                      
+                      ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
+		    }
+		  
+		  SC_START(1); // transition
+		  
+		} while (not have_transaction);
+
+//            ufpt.push_back(request);
+
+	      in_PREDICT_VAL [port]->write(0);
+	    
+              if (_param->_have_port_depth)
+	      TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+	}
+	
+        {
+          LABEL("DECOD - Miss");
+	  uint32_t port = rand() % _param->_nb_inst_decod;
+
+          LABEL("  * context : %d",context);
+          LABEL("  * port    : %d",port);
+          
+          request_t request;
+          request.context          = context;
+          request.address_src      = 0x14011959;
+          request.address_dest     = 0x25071959; // after = not take               
+          request.address_good     = request.address_dest;
+          request.condition        = BRANCH_CONDITION_FLAG_SET;
+          request.take             = 0;                                              
+          request.take_good        = 0;                                              
+          request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+          request.is_accurate      = true;
+          request.miss_ifetch      = false;
+          request.miss_decod       = true ;
+          request.miss_commit      = false;
+          request.history          = 1; 
+          request.ras_address      = 0xbabababa;                                   
+          request.ras_index        = (0x87654321)%_param->_size_ras_index[context];
+          request.ufpt_ptr         = ufpt_top [context];
+        
+          event = request;
+
+//           for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+            {
+	      bool have_transaction = false;
+	      do
+		{
+		  in_DECOD_VAL                  [port]->write((rand()%100)<percent_transaction_decod);
+		  in_DECOD_CONTEXT_ID           [port]->write(request.context     );
+		  in_DECOD_BTB_ADDRESS_SRC      [port]->write(request.address_src );
+		  in_DECOD_BTB_ADDRESS_DEST     [port]->write(request.address_dest);
+		  in_DECOD_BTB_CONDITION        [port]->write(request.condition   );
+		  in_DECOD_BTB_LAST_TAKE        [port]->write(request.take        );
+		  in_DECOD_RAS_ADDRESS          [port]->write(request.ras_address );
+		  in_DECOD_RAS_INDEX            [port]->write(request.ras_index   );
+		  in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr    );
+		  in_DECOD_MISS_IFETCH          [port]->write(request.miss_ifetch );
+		  in_DECOD_MISS_DECOD           [port]->write(request.miss_decod  );
+		  in_DECOD_IS_ACCURATE          [port]->write(request.is_accurate );
+
+		  SC_START(0); // fct melay
+		  
+		  LABEL("DECOD           [%d] %d - %d",
+                        port,
+                         in_PREDICT_VAL [port]->read(),
+                        out_PREDICT_ACK [port]->read());
+		  
+		  if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
+		    {
+		      LABEL("DECOD          [%d] - Transaction accepted",port);
+		      have_transaction = true;
+
+                      request.upt_ptr = upt_top [context];
+                      upt.push_back(request);
+//                    ufpt.pop_front();
+
+                      upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
+		    }
+
+		  SC_START(1); // transition
+
+                } while (not have_transaction);
+
+	      in_DECOD_VAL              [port]->write(0);
+	      
+              if (_param->_have_port_depth)
+	      TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+            }
+        }
+
+	{
+          LABEL("BRANCH_COMPLETE - hit ifetch");
+	
+	  uint32_t port = rand() % _param->_nb_inst_branch_complete;
+	
+          LABEL("  * port    : %d",port);
+  
+          std::list<request_t>::iterator it_upt = upt.begin();
+
+// 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+// 	  for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+          {
+	      bool have_transaction = false;
+
+	      do
+		{
+		  in_BRANCH_COMPLETE_VAL        [port]->write((rand()%100)<percent_transaction_branch_complete);
+		  in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context     );
+		  in_BRANCH_COMPLETE_DEPTH      [port]->write(it_upt->upt_ptr     );
+		  in_BRANCH_COMPLETE_ADDRESS    [port]->write(it_upt->address_good);
+		  in_BRANCH_COMPLETE_FLAG       [port]->write(it_upt->flag        );
+
+                  if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                  TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+		  SC_START(0);
+		  
+		  LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
+		  
+		  if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
+		    {
+		      LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
+		      have_transaction = true;
+		      
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
+
+                      it_upt ++;
+		    }
+		  
+		  SC_START(1);
+		} while (not have_transaction);
+
+	      in_BRANCH_COMPLETE_VAL [port]->write(0);
+	      
+              if (_param->_have_port_depth)
+              TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+	}
+
+	{
+          LABEL("UPDATE - hit ifetch");
+	
+	  uint32_t port = 0;
+	
+          LABEL("  * port    : %d",port);
+          std::list<request_t>::iterator it_upt = upt.begin();
+  
+// 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+// 	  for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+	    {
+	      bool have_transaction = false;
+
+	      do
+		{
+		  in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+
+//                   if (_param->_have_port_depth)
+//                   TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+		  SC_START(0);
+
+		  LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+		  
+		  if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+		    {
+		      LABEL("UPDATE [%d] - Transaction accepted",port);
+		      have_transaction = true;
+		  
+                      if (_param->_have_port_context_id)
+                      TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_upt->context);
+                      TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),it_upt->miss_commit);
+                      TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_upt->take_good);
+                      TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),update_btb(it_upt->condition));
+                      if (update_btb(it_upt->condition))
+                        {
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_upt->address_src);
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_upt->address_dest);
+                      TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_upt->condition);
+                        }
+                      TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
+
+                      if (update_dir(it_upt->condition))
+                      if (_param->_have_port_history)
+                      TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_upt->history);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_upt->condition));
+                      if (update_ras(it_upt->condition))
+                        {
+//                    TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_upt->condition));
+                      TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_upt->ras_address);
+                      TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_upt->ras_index);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
+                        }
+                      ++ it_upt;
+		    }
+
+		  SC_START(1);
+		} while (not have_transaction);
+
+	      in_UPDATE_ACK [port]->write(0);
+//               if (_param->_have_port_depth)
+//               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//               TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+          upt.clear();
+	}
+
+        {
+          LABEL("BRANCH_EVENT - have miss decod");
+          
+	  uint32_t port = context;
+
+          {
+            bool have_transaction = false;
+            
+            do
+              {
+                in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
+                
+                SC_START(0);
+                
+                LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
+		
+                if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
+                  {
+                    LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
+                    have_transaction = true;
+              
+                    TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC      [port]->read(),event.address_src);
+                    TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
+                    if (event.take)
+                    TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST     [port]->read(),event.address_good);
+
+                    event.address_src  = 0;
+                    event.take         = 0;
+                    event.address_dest = 0;
+                  }
+                
+                SC_START(1);
+              } while (not have_transaction);
+
+	      in_BRANCH_EVENT_ACK [port]->write(0);
+          }
+        }
+
+
+        // Wait Garbage Collector
+        {
+          upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
+//        upt_top    [context] = (upt_top    [context]);
+
+          while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
+                 (upt_top    [context] != out_DEPTH_MAX [context]->read()))
+            SC_START(1);
+
+        }
+        }
+
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      // DECOD MISS : with RAS in ifetch
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      if (test3)
+        {
+	uint32_t context = rand() % _param->_nb_context;
+        uint32_t have_ras = false;
+	{
+          LABEL("PREDICT - fill the queue");
+	  uint32_t port = rand() % _param->_nb_inst_predict;
+
+          LABEL("  * context : %d",context);
+          LABEL("  * port    : %d",port);
+	  
+	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+	    {
+              request_t request;
+              request.context          = context;
+              request.address_src      = 0xdeadbeef+i;
+              request.address_dest     = 0x21071981+i;                                   
+              request.address_good     = request.address_dest;
+              request.condition        = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
+
+              have_ras |= (update_ras(request.condition));
+
+              request.take             = 1;                                              
+              request.take_good        = 1;                                              
+              request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+              request.is_accurate      = true;
+              request.miss_ifetch      = false;
+              request.miss_decod       = true ;
+              request.miss_commit      = false;
+              request.history          = i;                                              
+              request.ras_address      = 0x12344321+i;                                   
+              request.ras_index        = (043211234+i)%_param->_size_ras_index[context];
+              request.ufpt_ptr         = ufpt_top [context];
+//            request.upt_ptr;
+              
+	      bool have_transaction = false;
+	      do
+		{
+		  in_PREDICT_VAL              [port]->write((rand()%100)<percent_transaction_predict);
+		  in_PREDICT_CONTEXT_ID       [port]->write(request.context     );
+		  in_PREDICT_BTB_ADDRESS_SRC  [port]->write(request.address_src );
+		  in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
+		  in_PREDICT_BTB_CONDITION    [port]->write(request.condition   );
+		  in_PREDICT_BTB_LAST_TAKE    [port]->write(request.take        );
+		  in_PREDICT_BTB_IS_ACCURATE  [port]->write(request.is_accurate );
+		  in_PREDICT_DIR_HISTORY      [port]->write(request.history     );
+		  in_PREDICT_RAS_ADDRESS      [port]->write(request.ras_address );
+		  in_PREDICT_RAS_INDEX        [port]->write(request.ras_index   );
+		  
+		  if (_param->_have_port_depth)
+		  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                  TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		      
+		  SC_START(0); // fct melay
+		  
+		  LABEL("PREDICT         [%d] %d - %d (accurate : %d).",
+                        port,
+                         in_PREDICT_VAL [port]->read(),
+                        out_PREDICT_ACK [port]->read(),
+                         in_PREDICT_BTB_IS_ACCURATE [port]->read());
+		  
+		  if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
+		    {
+		      LABEL("PREDICT         [%d] - Transaction accepted",port);
+		      have_transaction = true;
+
+                      if (_param->_have_port_depth)
+                      TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
+                      
+                      ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
+		    }
+		  
+		  SC_START(1); // transition
+		  
+		} while (not have_transaction);
+
+              ufpt.push_back(request); // to update
+
+	      in_PREDICT_VAL [port]->write(0);
+	    
+              if (_param->_have_port_depth)
+	      TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+	}
+	
+        {
+          LABEL("DECOD - Miss");
+	  uint32_t port = rand() % _param->_nb_inst_decod;
+
+          LABEL("  * context : %d",context);
+          LABEL("  * port    : %d",port);
+          
+          request_t request;
+          request.context          = context;
+          request.address_src      = 0x14011959;
+          request.address_dest     = 0x25071959; // after = not take               
+          request.address_good     = request.address_dest;
+          request.condition        = BRANCH_CONDITION_FLAG_SET;
+          request.take             = 0;                                              
+          request.take_good        = 0;                                              
+          request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+          request.is_accurate      = true;
+          request.miss_ifetch      = false;
+          request.miss_decod       = true ;
+          request.miss_commit      = false;
+          request.history          = 1; 
+          request.ras_address      = 0xbabababa;                                   
+          request.ras_index        = (0x87654321)%_param->_size_ras_index[context];
+          request.ufpt_ptr         = ufpt_top [context];
+
+          event = request;
+          
+//           for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+            {
+	      bool have_transaction = false;
+	      do
+		{
+		  in_DECOD_VAL                  [port]->write((rand()%100)<percent_transaction_decod);
+		  in_DECOD_CONTEXT_ID           [port]->write(request.context     );
+		  in_DECOD_BTB_ADDRESS_SRC      [port]->write(request.address_src );
+		  in_DECOD_BTB_ADDRESS_DEST     [port]->write(request.address_dest);
+		  in_DECOD_BTB_CONDITION        [port]->write(request.condition   );
+		  in_DECOD_BTB_LAST_TAKE        [port]->write(request.take        );
+		  in_DECOD_RAS_ADDRESS          [port]->write(request.ras_address );
+		  in_DECOD_RAS_INDEX            [port]->write(request.ras_index   );
+		  in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr    );
+		  in_DECOD_MISS_IFETCH          [port]->write(request.miss_ifetch );
+		  in_DECOD_MISS_DECOD           [port]->write(request.miss_decod  );
+		  in_DECOD_IS_ACCURATE          [port]->write(request.is_accurate );
+
+		  SC_START(0); // fct melay
+		  
+		  LABEL("DECOD           [%d] %d - %d",
+                        port,
+                         in_PREDICT_VAL [port]->read(),
+                        out_PREDICT_ACK [port]->read());
+		  
+		  if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
+		    {
+		      LABEL("DECOD          [%d] - Transaction accepted",port);
+		      have_transaction = true;
+
+                      request.upt_ptr = upt_top [context];
+                      upt.push_back(request);
+//                    ufpt.pop_front();
+
+                      upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
+		    }
+
+		  SC_START(1); // transition
+
+                } while (not have_transaction);
+
+	      in_DECOD_VAL              [port]->write(0);
+	      
+              if (_param->_have_port_depth)
+	      TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+            }
+        }
+
+	{
+          LABEL("BRANCH_COMPLETE - hit ifetch");
+	
+	  uint32_t port = rand() % _param->_nb_inst_branch_complete;
+	
+          LABEL("  * port    : %d",port);
+  
+          std::list<request_t>::iterator it_upt = upt.begin();
+
+// 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+// 	  for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+          {
+	      bool have_transaction = false;
+
+	      do
+		{
+		  in_BRANCH_COMPLETE_VAL        [port]->write((rand()%100)<percent_transaction_branch_complete);
+		  in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context     );
+		  in_BRANCH_COMPLETE_DEPTH      [port]->write(it_upt->upt_ptr     );
+		  in_BRANCH_COMPLETE_ADDRESS    [port]->write(it_upt->address_good);
+		  in_BRANCH_COMPLETE_FLAG       [port]->write(it_upt->flag        );
+
+                  if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                  TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+		  SC_START(0);
+		  
+		  LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
+		  
+		  if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
+		    {
+		      LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
+		      have_transaction = true;
+		      
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_upt->take_good   );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_upt->address_src );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_upt->address_good);
+
+                      it_upt ++;
+		    }
+		  
+		  SC_START(1);
+		} while (not have_transaction);
+
+	      in_BRANCH_COMPLETE_VAL [port]->write(0);
+	      
+              if (_param->_have_port_depth)
+              TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+	}
+
+        if (have_ras)
+	{
+          LABEL("UPDATE - Update UPFT");
+	
+	  uint32_t port = 0;
+	
+          LABEL("  * port    : %d",port);
+          std::list<request_t>::iterator it_ufpt = ufpt.end();
+          -- it_ufpt;
+  
+ 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+	    {
+	      bool have_transaction = false;
+
+	      do
+		{
+		  in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+
+//                   if (_param->_have_port_depth)
+//                   TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
+//                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
+		  
+		  SC_START(0);
+
+		  LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+		  
+		  if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+		    {
+		      LABEL("UPDATE [%d] - Transaction accepted",port);
+		      have_transaction = true;
+		  
+                      if (_param->_have_port_context_id)
+                      TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_ufpt->context);
+                      TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),(it_ufpt->miss_ifetch or
+                                                                                                it_ufpt->miss_decod  or
+                                                                                                it_ufpt->miss_commit ));
+//                       if (update_btb(it_ufpt->condition) or
+//                           update_dir(it_ufpt->condition))
+//                       TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_ufpt->take_good);
+                      TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),0);
+//                       if (update_btb(it_ufpt->condition))
+//                         {
+//                       TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_ufpt->address_src);
+//                       TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_ufpt->address_dest);
+//                       TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_ufpt->condition);
+//                         }
+                      TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),0);
+
+//                       if (update_dir(it_ufpt->condition))
+//                       if (_param->_have_port_history)
+//                       TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_ufpt->history);
+//                       TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_ufpt->condition));
+                      if (update_ras(it_ufpt->condition))
+                        {
+//                    TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_ufpt->condition));
+                      LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
+                      LABEL("KANE : it_ufpt->ras_address                  : %.8x",it_ufpt->ras_address);
+
+                      TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_ufpt->ras_address);
+                      TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_ufpt->ras_index);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
+                        }
+		    }
+
+		  SC_START(1);
+		} while (not have_transaction);
+
+              -- it_ufpt;
+                
+
+	      in_UPDATE_ACK [port]->write(0);
+//               if (_param->_have_port_depth)
+//               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
+//               TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
+	    }
+	}
+        ufpt.clear();
+
+	{
+          LABEL("UPDATE - hit ifetch");
+	
+	  uint32_t port = 0;
+	
+          LABEL("  * port    : %d",port);
+          std::list<request_t>::iterator it_upt = upt.begin();
+  
+// 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+// 	  for (uint32_t i=0; i<upt.size(); i++)
+          // just one
+	    {
+	      bool have_transaction = false;
+
+	      do
+		{
+		  in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+
+//                   if (_param->_have_port_depth)
+//                   TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+		  SC_START(0);
+
+		  LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+		  
+		  if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+		    {
+		      LABEL("UPDATE [%d] - Transaction accepted",port);
+		      have_transaction = true;
+		  
+                      if (_param->_have_port_context_id)
+                      TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_upt->context);
+                      TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),it_upt->miss_commit);
+                      TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_upt->take_good);
+                      TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),update_btb(it_upt->condition));
+                      if (update_btb(it_upt->condition))
+                        {
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_upt->address_src);
+                      TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_upt->address_dest);
+                      TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_upt->condition);
+                        }
+                      TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
+
+                      if (update_dir(it_upt->condition))
+                      if (_param->_have_port_history)
+                      TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_upt->history);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_upt->condition));
+                      if (update_ras(it_upt->condition))
+                        {
+//                    TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_upt->condition));
+                      TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_upt->ras_address);
+                      TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_upt->ras_index);
+                      TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
+                        }
+                      ++ it_upt;
+		    }
+
+		  SC_START(1);
+		} while (not have_transaction);
+
+	      in_UPDATE_ACK [port]->write(0);
+//               if (_param->_have_port_depth)
+//               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//               TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+	}
+        upt.clear();
+
+        {
+          LABEL("BRANCH_EVENT - have miss decod");
+          
+	  uint32_t port = context;
+
+          {
+            bool have_transaction = false;
+            
+            do
+              {
+                in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
+                
+                SC_START(0);
+                
+                LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
+		
+                if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
+                  {
+                    LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
+                    have_transaction = true;
+              
+                    TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC      [port]->read(),event.address_src);
+                    TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
+                    if (event.take)
+                    TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST     [port]->read(),event.address_good);
+
+                    event.address_src  = 0;
+                    event.take         = 0;
+                    event.address_dest = 0;
+                  }
+                
+                SC_START(1);
+              } while (not have_transaction);
+
+	      in_BRANCH_EVENT_ACK [port]->write(0);
+          }
+        }
+
+        // Wait Garbage Collector
+        {
+          upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
+//        upt_top    [context] = (upt_top    [context]);
+
+          while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
+                 (upt_top    [context] != out_DEPTH_MAX [context]->read()))
+            SC_START(1);
+
+        }
+      }
+     
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      // COMMIT MISS : with RAS in UPFT and UPT
+      //---------------------------------------------------------------------
+      //---------------------------------------------------------------------
+      if (test4)
+        {
+          uint32_t context = rand() % _param->_nb_context;
+          uint32_t have_ufpt_ras = false;
+          uint32_t have_upt_ras  = false;
+          {
+            LABEL("PREDICT - fill the queue");
+            uint32_t port = rand() % _param->_nb_inst_predict;
+            
+            LABEL("  * context : %d",context);
+            LABEL("  * port    : %d",port);
+            
+            for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+              {
+                request_t request;
+                request.context          = context;
+                request.address_src      = rand();
+                request.address_dest     = rand();                                   
+                
+                request.condition        = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
+
+                request.take             = 1;                                              
+                request.take_good        = 1;                                              
+                request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+                request.is_accurate      = false;
+                request.miss_ifetch      = false;
+                request.miss_decod       = false;
+                request.miss_commit      = false;
+                request.history          = i;                                              
+                request.ras_address      = rand();                                   
+                request.ras_index        = rand()%_param->_size_ras_index[context];
+                request.ufpt_ptr         = ufpt_top [context];
+//              request.upt_ptr;
+                
+                bool have_transaction = false;
+                do
+                  {
+                    in_PREDICT_VAL              [port]->write((rand()%100)<percent_transaction_predict);
+                    in_PREDICT_CONTEXT_ID       [port]->write(request.context     );
+                    in_PREDICT_BTB_ADDRESS_SRC  [port]->write(request.address_src );
+                    in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
+                    in_PREDICT_BTB_CONDITION    [port]->write(request.condition   );
+                    in_PREDICT_BTB_LAST_TAKE    [port]->write(request.take        );
+                    in_PREDICT_BTB_IS_ACCURATE  [port]->write(request.is_accurate );
+                    in_PREDICT_DIR_HISTORY      [port]->write(request.history     );
+                    in_PREDICT_RAS_ADDRESS      [port]->write(request.ras_address );
+                    in_PREDICT_RAS_INDEX        [port]->write(request.ras_index   );
+                    
+                    if (_param->_have_port_depth)
+                    TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                    TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+                    
+                    SC_START(0); // fct melay
+                    
+                    LABEL("PREDICT         [%d] %d - %d (accurate : %d).",
+                          port,
+                          in_PREDICT_VAL [port]->read(),
+                          out_PREDICT_ACK [port]->read(),
+                          in_PREDICT_BTB_IS_ACCURATE [port]->read());
+                    
+                    if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
+                      {
+                        LABEL("PREDICT         [%d] - Transaction accepted",port);
+                        have_transaction = true;
+                        
+                        if (_param->_have_port_depth)
+                          TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
+                        
+                        ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
+                      }
+                    
+                    SC_START(1); // transition
+                    
+                  } while (not have_transaction);
+                
+                ufpt.push_back(request); // to update
+                
+                in_PREDICT_VAL [port]->write(0);
+                
+                if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+              }
+          }
+	
+          {
+            LABEL("DECOD");
+            uint32_t port = rand() % _param->_nb_inst_decod;
+            
+            LABEL("  * context : %d",context);
+            LABEL("  * port    : %d",port);
+            
+            for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+              {
+                request_t request = ufpt.front();
+                
+                bool have_transaction = false;
+                do
+                  {
+                    in_DECOD_VAL                  [port]->write((rand()%100)<percent_transaction_decod);
+                    in_DECOD_CONTEXT_ID           [port]->write(request.context     );
+                    in_DECOD_BTB_ADDRESS_SRC      [port]->write(request.address_src );
+                    in_DECOD_BTB_ADDRESS_DEST     [port]->write(request.address_dest);
+                    in_DECOD_BTB_CONDITION        [port]->write(request.condition   );
+                    in_DECOD_BTB_LAST_TAKE        [port]->write(request.take        );
+                    in_DECOD_RAS_ADDRESS          [port]->write(request.ras_address );
+                    in_DECOD_RAS_INDEX            [port]->write(request.ras_index   );
+                    in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr    );
+                    in_DECOD_MISS_IFETCH          [port]->write(request.miss_ifetch );
+                    in_DECOD_MISS_DECOD           [port]->write(request.miss_decod  );
+                    in_DECOD_IS_ACCURATE          [port]->write(request.is_accurate );
+          
+                    have_upt_ras |= (update_ras(request.condition));
+          
+                    SC_START(0); // fct melay
+                    
+                    LABEL("DECOD           [%d] %d - %d",
+                          port,
+                          in_PREDICT_VAL [port]->read(),
+                          out_PREDICT_ACK [port]->read());
+                    
+                    if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
+                      {
+                        LABEL("DECOD          [%d] - Transaction accepted",port);
+                        have_transaction = true;
+                        
+                        request.upt_ptr = upt_top [context];
+                        upt.push_back(request);
+                        ufpt.pop_front();
+                        
+                        upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
+                      }
+                    
+                    SC_START(1); // transition
+                    
+                  } while (not have_transaction);
+                
+                in_DECOD_VAL              [port]->write(0);
+                
+                if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+              }
+          }
+
+          {
+            LABEL("PREDICT - fill the queue");
+            uint32_t port = rand() % _param->_nb_inst_predict;
+            
+            LABEL("  * context : %d",context);
+            LABEL("  * port    : %d",port);
+            
+            for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+              {
+                request_t request;
+                request.context          = context;
+                request.address_src      = rand();
+                request.address_dest     = rand();                                   
+                request.address_good     = request.address_dest;
+                request.condition        = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
+                
+                have_ufpt_ras |= (update_ras(request.condition));
+                
+                request.take             = 1;                                              
+                request.take_good        = 1;                                              
+                request.flag             = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
+                request.is_accurate      = false;
+                request.miss_ifetch      = false;
+                request.miss_decod       = false;
+                request.miss_commit      = true;
+                request.history          = i;                                              
+                request.ras_address      = rand();                                   
+                request.ras_index        = rand()%_param->_size_ras_index[context];
+                request.ufpt_ptr         = ufpt_top [context];
+//              request.upt_ptr;
+                
+                bool have_transaction = false;
+                do
+                  {
+                    in_PREDICT_VAL              [port]->write((rand()%100)<percent_transaction_predict);
+                    in_PREDICT_CONTEXT_ID       [port]->write(request.context     );
+                    in_PREDICT_BTB_ADDRESS_SRC  [port]->write(request.address_src );
+                    in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
+                    in_PREDICT_BTB_CONDITION    [port]->write(request.condition   );
+                    in_PREDICT_BTB_LAST_TAKE    [port]->write(request.take        );
+                    in_PREDICT_BTB_IS_ACCURATE  [port]->write(request.is_accurate );
+                    in_PREDICT_DIR_HISTORY      [port]->write(request.history     );
+                    in_PREDICT_RAS_ADDRESS      [port]->write(request.ras_address );
+                    in_PREDICT_RAS_INDEX        [port]->write(request.ras_index   );
+                    
+                    if (_param->_have_port_depth)
+                    TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                    TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+                    
+                    SC_START(0); // fct melay
+                    
+                    LABEL("PREDICT         [%d] %d - %d (accurate : %d).",
+                          port,
+                          in_PREDICT_VAL [port]->read(),
+                          out_PREDICT_ACK [port]->read(),
+                          in_PREDICT_BTB_IS_ACCURATE [port]->read());
+                    
+                    if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
+                      {
+                        LABEL("PREDICT         [%d] - Transaction accepted",port);
+                        have_transaction = true;
+                        
+                        if (_param->_have_port_depth)
+                          TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
+                        
+                        ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
+                      }
+                    
+                    SC_START(1); // transition
+                    
+                  } while (not have_transaction);
+                
+                ufpt.push_back(request); // to update
+                
+                in_PREDICT_VAL [port]->write(0);
+                
+                if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+              }
+          }
+
+          std::list<request_t>::iterator it_event;
+          {
+            LABEL("BRANCH_COMPLETE - hit ifetch");
+            
+            uint32_t port = rand() % _param->_nb_inst_branch_complete;
+            
+            LABEL("  * port    : %d",port);
+            
+            // middle
+            it_event = upt.begin();
+            for (uint32_t i=0; i < (upt.size()>>1); ++i)
+              it_event ++;
+
+            for (std::list<request_t>::iterator it_upt = it_event;
+                 it_upt != upt.end();
+                 ++it_upt)
+              it_upt->miss_commit = true;
+
+            if (update_ras(it_event->condition))
+              it_event->address_good = ~(it_event->address_dest);
+            else
+              {
+                it_event->address_good = it_event->address_dest;
+                it_event->flag         = not it_event->flag;
+                it_event->take_good    = not it_event->take_good;
+              }
+
+            event = *it_event;
+
+            
+// 	  for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+// 	  for (uint32_t i=0; i<upt.size(); i++)
+            // just one
+            {
+	      bool have_transaction = false;
+              
+	      do
+		{
+		  in_BRANCH_COMPLETE_VAL        [port]->write((rand()%100)<percent_transaction_branch_complete);
+		  in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context     );
+		  in_BRANCH_COMPLETE_DEPTH      [port]->write(it_event->upt_ptr     );
+		  in_BRANCH_COMPLETE_ADDRESS    [port]->write(it_event->address_good);
+		  in_BRANCH_COMPLETE_FLAG       [port]->write(it_event->flag        );
+
+                  if (_param->_have_port_depth)
+                  TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+                  TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+		  SC_START(0);
+		  
+		  LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
+		  
+		  if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
+		    {
+		      LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
+                      LABEL("  * CONTEXT_ID %d"  ,it_event->context     );
+                      LABEL("  * DEPTH      %d"  ,it_event->upt_ptr     );
+                      LABEL("  * CONDITION  %d"  ,it_event->condition   );
+                      LABEL("  * ADDRESS    %.8x",it_event->address_good);
+                      LABEL("  * FLAG       %d"  ,it_event->flag        );
+
+		      have_transaction = true;
+		      
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
+		      TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE           [port]->read(),it_event->take_good   );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC    [port]->read(),it_event->address_src );
+		      TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST   [port]->read(),it_event->address_good);
+
+                      upt_top [it_event->context] = it_event->upt_ptr;
+		    }
+		  
+		  SC_START(1);
+		} while (not have_transaction);
+              
+	      in_BRANCH_COMPLETE_VAL [port]->write(0);
+	      
+              if (_param->_have_port_depth)
+              TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+              TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+	    }
+          }
+          
+          if (have_ufpt_ras)
+            {
+              LABEL("UPDATE - Update UPFT");
+              
+              uint32_t port = 0;
+              
+              LABEL("  * port    : %d",port);
+              std::list<request_t>::iterator it_ufpt = ufpt.end();
+              -- it_ufpt;
+              
+              for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
+                {
+                  bool have_transaction = false;
+                  
+                  do
+                    {
+                      in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+                      
+//                    if (_param->_have_port_depth)
+//                    TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
+//                    TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
+		  
+                      SC_START(0);
+                      
+                      LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+                      
+                      if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+                        {
+                          LABEL("UPDATE [%d] - Transaction accepted",port);
+                          have_transaction = true;
+                          
+                          if (_param->_have_port_context_id)
+                          TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_ufpt->context);
+                          TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),(it_ufpt->miss_ifetch or
+                                                                                                    it_ufpt->miss_decod  or
+                                                                                                    it_ufpt->miss_commit ));
+//                        if (update_btb(it_ufpt->condition) or
+//                            update_dir(it_ufpt->condition))
+//                        TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_ufpt->take_good);
+                          TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),0);
+//                        if (update_btb(it_ufpt->condition))
+//                          {
+//                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_ufpt->address_src);
+//                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_ufpt->address_dest);
+//                        TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_ufpt->condition);
+//                          }
+                          TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),0);
+
+//                        if (update_dir(it_ufpt->condition))
+//                        if (_param->_have_port_history)
+//                        TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_ufpt->history);
+//                        TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_ufpt->condition));
+                          if (update_ras(it_ufpt->condition))
+                            {
+//                            TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                              TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_ufpt->condition));
+                              TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_ufpt->ras_address);
+                              TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_ufpt->ras_index);
+                              TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
+                            }
+                        }
+                      
+                      SC_START(1);
+                    } while (not have_transaction);
+                  
+                  -- it_ufpt;
+                  
+                  
+                  in_UPDATE_ACK [port]->write(0);
+//                if (_param->_have_port_depth)
+//                TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
+//                TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
+                }
+            }
+          ufpt.clear();
+
+          {
+            LABEL("UPDATE - upt");
+            
+            uint32_t port = 0;
+            
+            LABEL("  * port    : %d",port);
+            std::list<request_t>::iterator it_upt = upt.end();
+            --it_upt;
+
+//             for (uint32_t i=0; i<upt.size(); i++)
+            while (it_upt != it_event)
+              {
+                bool have_transaction = false;
+                
+                do
+                  {
+                    in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+
+//                   if (_param->_have_port_depth)
+//                   TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+                    SC_START(0);
+                    
+                    LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+                    
+                    if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+                      {
+                        LABEL("UPDATE [%d] - Transaction accepted",port);
+                        have_transaction = true;
+                        
+                        if (_param->_have_port_context_id)
+                        TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_upt->context);
+                        TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),it_upt->miss_commit);
+                        TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_upt->take_good);
+                        TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),update_btb(it_upt->condition));
+                        if (update_btb(it_upt->condition))
+                          {
+                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_upt->address_src);
+                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_upt->address_dest);
+                        TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_upt->condition);
+                          }
+                        TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
+                        
+                        if (update_dir(it_upt->condition))
+                        if (_param->_have_port_history)
+                        TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_upt->history);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_upt->condition));
+                        if (update_ras(it_upt->condition))
+                          {
+//                      TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_upt->condition));
+                        TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_upt->ras_address);
+                        TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_upt->ras_index);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
+                          }
+
+                        -- it_upt;
+                      }
+                    
+                    SC_START(1);
+                  } while (not have_transaction);
+              
+                upt.pop_back();
+                in_UPDATE_ACK [port]->write(0);
+//               if (_param->_have_port_depth)
+//               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//               TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+              }
+          }
+//           upt.clear(); // Not yet
+
+          {
+            LABEL("BRANCH_EVENT - have miss decod");
+            
+            uint32_t port = context;
+            
+            {
+              bool have_transaction = false;
+              
+              do
+                {
+                  in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
+                  
+                  SC_START(0);
+                  
+                  LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
+                  
+                  if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
+                    {
+                      LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
+                      have_transaction = true;
+                      
+                      LABEL("  * event.address_src  : %.8x,",event.address_src );
+                      LABEL("  * event.address_good : %.8x,",event.address_good);
+                      LABEL("  * event.take         : %.8x,",event.take        );
+                      
+                      TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC      [port]->read(),event.address_src);
+                      TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
+                      if (event.take_good)
+                      TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST     [port]->read(),event.address_good);
+                      
+                      event.address_src  = 0;
+                      event.take         = 0;
+                      event.address_dest = 0;
+                    }
+                  
+                  SC_START(1);
+                } while (not have_transaction);
+              
+	      in_BRANCH_EVENT_ACK [port]->write(0);
+            }
+          }
+          
+          {
+            LABEL("UPDATE - upt");
+            
+            uint32_t port = 0;
+            
+            LABEL("  * port    : %d",port);
+            std::list<request_t>::iterator it_upt = upt.begin();
+
+            for (uint32_t i=0; i<upt.size(); i++)
+              {
+                bool have_transaction = false;
+                
+                do
+                  {
+                    in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
+
+//                   if (_param->_have_port_depth)
+//                   TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//                   TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+		  
+                    SC_START(0);
+                    
+                    LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
+                    
+                    if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
+                      {
+                        LABEL("UPDATE [%d] - Transaction accepted",port);
+                        have_transaction = true;
+                        
+                        if (_param->_have_port_context_id)
+                        TEST(Tcontext_t         ,out_UPDATE_CONTEXT_ID            [port]->read(),it_upt->context);
+                        TEST(Tcontrol_t         ,out_UPDATE_MISS_PREDICTION       [port]->read(),it_upt->miss_commit);
+                        TEST(Tcontrol_t         ,out_UPDATE_DIRECTION_GOOD        [port]->read(),it_upt->take_good);
+                        TEST(Tcontrol_t         ,out_UPDATE_BTB_VAL               [port]->read(),update_btb(it_upt->condition));
+                        if (update_btb(it_upt->condition))
+                          {
+                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_SRC       [port]->read(),it_upt->address_src);
+                        TEST(Taddress_t         ,out_UPDATE_BTB_ADDRESS_DEST      [port]->read(),it_upt->address_dest);
+                        TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION         [port]->read(),it_upt->condition);
+                          }
+                        TEST(Tcontrol_t         ,out_UPDATE_DIR_VAL               [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
+                        
+                        if (update_dir(it_upt->condition))
+                        if (_param->_have_port_history)
+                        TEST(Thistory_t         ,out_UPDATE_DIR_HISTORY           [port]->read(),it_upt->history);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_VAL               [port]->read(),update_ras(it_upt->condition));
+                        if (update_ras(it_upt->condition))
+                          {
+//                      TEST(Tcontrol_t         ,out_UPDATE_RAS_FLUSH             [port]->read(),0);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_PUSH              [port]->read(),push_ras  (it_upt->condition));
+                        TEST(Taddress_t         ,out_UPDATE_RAS_ADDRESS           [port]->read(),it_upt->ras_address);
+                        TEST(Tptr_t             ,out_UPDATE_RAS_INDEX             [port]->read(),it_upt->ras_index);
+                        TEST(Tcontrol_t         ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
+                          }
+
+                        -- it_upt;
+                      }
+                    
+                    SC_START(1);
+                  } while (not have_transaction);
+                
+                in_UPDATE_ACK [port]->write(0);
+//               if (_param->_have_port_depth)
+//               TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
+//               TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
+              }
+          }
+          upt.clear(); // Not yet
+
+          // Wait Garbage Collector
+          {
+            upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
+//        upt_top    [context] = (upt_top    [context]);
+
+            while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
+                   (upt_top    [context] != out_DEPTH_MAX [context]->read()))
+              SC_START(1);
+            
+          }
+        }
+     
     }// ITERATION
 
@@ -649,4 +1997,5 @@
 //   delete [] out_BRANCH_EVENT_MISS_PREDICTION;
   delete [] out_BRANCH_EVENT_ADDRESS_SRC    ;
+  delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
   delete [] out_BRANCH_EVENT_ADDRESS_DEST   ;
   
@@ -664,4 +2013,5 @@
   delete [] out_UPDATE_DIR_HISTORY          ;
   delete [] out_UPDATE_RAS_VAL              ;
+  delete [] out_UPDATE_RAS_FLUSH            ;
   delete [] out_UPDATE_RAS_PUSH             ;
   delete [] out_UPDATE_RAS_ADDRESS          ;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 94)
@@ -120,4 +120,5 @@
 //public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_EVENT_MISS_PREDICTION   ; //[nb_context] is always miss prediction
   public    : SC_OUT(Taddress_t         )  ** out_BRANCH_EVENT_ADDRESS_SRC       ; //[nb_context]
+  public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_EVENT_ADDRESS_DEST_VAL  ; //[nb_context]
   public    : SC_OUT(Taddress_t         )  ** out_BRANCH_EVENT_ADDRESS_DEST      ; //[nb_context]
 
@@ -135,8 +136,14 @@
   public    : SC_OUT(Thistory_t         )  ** out_UPDATE_DIR_HISTORY             ; //[nb_inst_update]
   public    : SC_OUT(Tcontrol_t         )  ** out_UPDATE_RAS_VAL                 ; //[nb_inst_update]
+  public    : SC_OUT(Tcontrol_t         )  ** out_UPDATE_RAS_FLUSH               ; //[nb_inst_update]
   public    : SC_OUT(Tcontrol_t         )  ** out_UPDATE_RAS_PUSH                ; //[nb_inst_update]
   public    : SC_OUT(Taddress_t         )  ** out_UPDATE_RAS_ADDRESS             ; //[nb_inst_update]
   public    : SC_OUT(Tptr_t             )  ** out_UPDATE_RAS_INDEX               ; //[nb_inst_update]
   public    : SC_OUT(Tcontrol_t         )  ** out_UPDATE_RAS_PREDICTION_IFETCH   ; //[nb_inst_update]
+
+    // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  public    : SC_IN (Tevent_state_t     )  **  in_EVENT_STATE                    ; //[nb_context]
+  public    : SC_IN (Tevent_type_t      )  **  in_EVENT_TYPE                     ; //[nb_context]
+  public    : SC_IN (Tdepth_t           )  **  in_EVENT_DEPTH                    ; //[nb_context]
 
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -164,12 +171,10 @@
   private   : uint32_t                      * reg_UPT_TOP                        ; //[nb_context]
   private   : uint32_t                      * reg_UPT_UPDATE                     ; //[nb_context]
-  private   : uint32_t                      * reg_UPT_NB_NEED_UPDATE             ; //[nb_context]
                                                                                               
   private   : bool                          * reg_IS_ACCURATE                    ; //[nb_context]
 
   private   : event_state_t                 * reg_EVENT_STATE                    ; //[nb_context]
-  private   : Tcontrol_t                    * reg_EVENT_RAS_CORRUPTED            ; //[nb_context] // RAS must be flush
   private   : Taddress_t                    * reg_EVENT_ADDRESS_SRC              ; //[nb_context] // Address branch
-  private   : Tcontrol_t                    * reg_EVENT_ADDRESS_SRC_VAL          ; //[nb_context] // if miss ifetch, decod issue branch, dest must be reload
+  private   : Tcontrol_t                    * reg_EVENT_ADDRESS_DEST_VAL         ; //[nb_context] // if miss ifetch, decod issue branch, dest must be reload
   private   : Taddress_t                    * reg_EVENT_ADDRESS_DEST             ; //[nb_context] // Address dest
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 94)
@@ -114,11 +114,12 @@
       ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context);
       
-      ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL            ,VAL);
-      ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK            ,ACK);
-//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID     ,"context_id"     ,Tcontext_t,_param->_size_context_id);
-//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH          ,"depth"          ,Tdepth_t  ,_param->_size_depth);
-//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC    ,"address_src"    ,Taddress_t,_param->_size_instruction_address);
-      ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST   ,"address_dest"   ,Taddress_t,_param->_size_instruction_address);
+      ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL              ,VAL);
+      ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK              ,ACK);
+//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID       ,"context_id"      ,Tcontext_t,_param->_size_context_id);
+//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH            ,"depth"           ,Tdepth_t  ,_param->_size_depth);
+//    ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION  ,"miss_prediction" ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC      ,"address_src"     ,Taddress_t,_param->_size_instruction_address);
+      ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST     ,"address_dest"    ,Taddress_t,_param->_size_instruction_address);
     }
 
@@ -139,8 +140,18 @@
       ALLOC1_SIGNAL_OUT(out_UPDATE_DIR_HISTORY          ,"dir_history"          ,Thistory_t         ,_param->_size_history);
       ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_VAL              ,"ras_val"              ,Tcontrol_t         ,1);
+      ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_FLUSH            ,"ras_flush"            ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PUSH             ,"ras_push"             ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_ADDRESS          ,"ras_address"          ,Taddress_t         ,_param->_size_instruction_address);
       ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_INDEX            ,"ras_index"            ,Tptr_t             ,_param->_max_size_ras_index);
       ALLOC1_SIGNAL_OUT(out_UPDATE_RAS_PREDICTION_IFETCH,"ras_prediction_ifetch",Tcontrol_t         ,1);
+    }
+
+    // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    {
+      ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context);
+
+      ALLOC1_SIGNAL_IN ( in_EVENT_STATE  ,"state",Tevent_state_t,_param->_size_event_state);
+      ALLOC1_SIGNAL_IN ( in_EVENT_TYPE   ,"type" ,Tevent_type_t ,_param->_size_event_type );
+      ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH  ,"depth",Tdepth_t      ,_param->_size_depth      );
     }
 
@@ -187,10 +198,8 @@
     ALLOC1(reg_UPT_TOP                      ,uint32_t     ,_param->_nb_context);
     ALLOC1(reg_UPT_UPDATE                   ,uint32_t     ,_param->_nb_context);
-    ALLOC1(reg_UPT_NB_NEED_UPDATE           ,uint32_t     ,_param->_nb_context);
 
     ALLOC1(reg_EVENT_STATE                  ,event_state_t,_param->_nb_context);
-    ALLOC1(reg_EVENT_RAS_CORRUPTED          ,Tcontrol_t   ,_param->_nb_context);
     ALLOC1(reg_EVENT_ADDRESS_SRC            ,Taddress_t   ,_param->_nb_context);
-    ALLOC1(reg_EVENT_ADDRESS_SRC_VAL        ,Tcontrol_t   ,_param->_nb_context);
+    ALLOC1(reg_EVENT_ADDRESS_DEST_VAL       ,Tcontrol_t   ,_param->_nb_context);
     ALLOC1(reg_EVENT_ADDRESS_DEST           ,Taddress_t   ,_param->_nb_context);
       }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 94)
@@ -88,4 +88,5 @@
 // 	delete [] out_BRANCH_EVENT_MISS_PREDICTION;
 	delete [] out_BRANCH_EVENT_ADDRESS_SRC    ;
+	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
 	delete [] out_BRANCH_EVENT_ADDRESS_DEST   ;
 	
@@ -105,8 +106,14 @@
 	delete [] out_UPDATE_DIR_HISTORY          ;
 	delete [] out_UPDATE_RAS_VAL              ;
+	delete [] out_UPDATE_RAS_FLUSH            ;
 	delete [] out_UPDATE_RAS_PUSH             ;
 	delete [] out_UPDATE_RAS_ADDRESS          ;
 	delete [] out_UPDATE_RAS_INDEX            ;
 	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
+
+        // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+        DELETE1_SIGNAL( in_EVENT_STATE  ,_param->_nb_context,_param->_size_event_state);
+        DELETE1_SIGNAL( in_EVENT_TYPE   ,_param->_nb_context,_param->_size_event_type );
+        DELETE1_SIGNAL( in_EVENT_DEPTH  ,_param->_nb_context,_param->_size_depth      );
 
 	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -149,10 +156,8 @@
         DELETE1(reg_UPT_TOP                      ,_param->_nb_context);
         DELETE1(reg_UPT_UPDATE                   ,_param->_nb_context);
-        DELETE1(reg_UPT_NB_NEED_UPDATE           ,_param->_nb_context);
         
         DELETE1(reg_EVENT_STATE                  ,_param->_nb_context);
-        DELETE1(reg_EVENT_RAS_CORRUPTED          ,_param->_nb_context);
         DELETE1(reg_EVENT_ADDRESS_SRC            ,_param->_nb_context);
-        DELETE1(reg_EVENT_ADDRESS_SRC_VAL        ,_param->_nb_context);
+        DELETE1(reg_EVENT_ADDRESS_DEST_VAL       ,_param->_nb_context);
         DELETE1(reg_EVENT_ADDRESS_DEST           ,_param->_nb_context);
        }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 94)
@@ -61,4 +61,6 @@
 	      //miss      : always hit
 	      //addr_dest : compute in decod stage
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK");
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_NONE_WITH_WRITE_STACK   ");
 
 #ifdef DEBUG_TEST
@@ -75,4 +77,6 @@
 	      //addr_dest : compute in decod stage
               //miss if the direction is bad
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_FLAG_UNSET");
+
               Tcontrol_t take_good = not flag; // flag set = not take
 
@@ -91,4 +95,6 @@
 	      //addr_dest : compute in decod stage
               //miss if the direction is bad
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_FLAG_SET");
+
               Tcontrol_t take_good = flag; // flag set = take
 
@@ -107,4 +113,8 @@
 	  case BRANCH_CONDITION_READ_STACK                        : // l.jr (rb==r9)
 	    {
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK");
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK   ");
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * BRANCH_CONDITION_READ_STACK                       ");
+
               // miss if destination address is bad
 	      miss      = (addr_dest != addr_good);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp	(revision 94)
@@ -24,5 +24,4 @@
     log_begin(Update_Prediction_Table,FUNCTION);
     log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
-    log_printf(NONE,Update_Prediction_Table,FUNCTION,FUNCTION);
 
     if (PORT_READ(in_NRESET) == 1)
@@ -87,4 +86,5 @@
         Thistory_t          dir_history          ;
         Tcontrol_t          ras_val              ;
+        Tcontrol_t          ras_flush            ;
         Tcontrol_t          ras_push             ;
         Taddress_t          ras_address          ;
@@ -110,4 +110,6 @@
                 
                 val                   = (state == UPDATE_FETCH_PREDICTION_STATE_EVENT);
+//              val_without_ack       = not update_ras(condition);
+
                 miss_prediction       = 1;
 //              direction_good        = ;
@@ -119,4 +121,5 @@
 //              dir_history           = ;
                 ras_val               = update_ras(condition); // repop/ repush data -> don't corrupt ras
+                ras_flush             = 0;
                 ras_push              = push_ras(condition);
                 ras_address           = reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._address_ras;
@@ -132,5 +135,5 @@
                   ufpt_update [context] = false;
                 
-                tab_ufpt_depth[context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1);
+                tab_ufpt_depth[context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
               }
           }
@@ -177,4 +180,5 @@
                 dir_history           = reg_UPDATE_PREDICTION_TABLE [context][depth]._history     ;
                 ras_val               = update_ras(condition); // repop/ repush data -> don't corrupt ras
+                ras_flush             = (state == UPDATE_PREDICTION_STATE_KO); // miss prediction, RAS is corrupted
                 ras_push              = push_ras(condition);
                 ras_address           = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_ras;
@@ -224,7 +228,4 @@
         PORT_WRITE(out_UPDATE_BTB_VAL               [i],btb_val              );
         PORT_WRITE(out_UPDATE_BTB_ADDRESS_SRC       [i],btb_address_src      );
-
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * address_src     : %.8x",btb_address_src);
-
         PORT_WRITE(out_UPDATE_BTB_ADDRESS_DEST      [i],btb_address_dest     );
         PORT_WRITE(out_UPDATE_BTB_CONDITION         [i],btb_condition        );
@@ -233,4 +234,5 @@
         PORT_WRITE(out_UPDATE_DIR_HISTORY           [i],dir_history          );
         PORT_WRITE(out_UPDATE_RAS_VAL               [i],ras_val              );
+        PORT_WRITE(out_UPDATE_RAS_FLUSH             [i],ras_flush            );
         PORT_WRITE(out_UPDATE_RAS_PUSH              [i],ras_push             );
         PORT_WRITE(out_UPDATE_RAS_ADDRESS           [i],ras_address          );
@@ -239,29 +241,21 @@
           }
       }
-
-//     // ===================================================================
-//     // =====[ BRANCH_EVENT ]==============================================
-//     // ===================================================================
-//     for (uint32_t i=0; i<_param->_nb_context; i++)
-//       {
-// 	Tdepth_t   depth   = (reg_BOTTOM [i] + reg_NB_ELT_UPDATE [i])%_param->_size_queue [i];
-// 	state_t    state   = reg_UPDATE_PREDICTION_TABLE [i][depth]._state;
-	
-// 	Tcontrol_t val     = ((state == UPDATE_PREDICTION_STATE_EVENT) or
-//                               (state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT));
-
-// 	if (val)
-// 	  {
-// //          breakpoint ("UPT : have an branch_event (depth %d)",depth);
-// 	    PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC  [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_src );
-// 	    PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST [i], reg_UPDATE_PREDICTION_TABLE [i][depth]._address_dest);
-// 	    internal_BRANCH_EVENT_DEPTH [i] = depth;
-// 	  }
-
-// 	internal_BRANCH_EVENT_VAL   [i] = val;
-// 	PORT_WRITE(out_BRANCH_EVENT_VAL [i], internal_BRANCH_EVENT_VAL [i]);
-//       }
-
-      }
+    
+    // ===================================================================
+    // =====[ BRANCH_EVENT ]==============================================
+    // ===================================================================
+    for (uint32_t i=0; i<_param->_nb_context; i++)
+      {
+	Tcontrol_t val = (reg_EVENT_STATE [i] == EVENT_STATE_UPDATE_CONTEXT);
+
+        PORT_WRITE(out_BRANCH_EVENT_VAL              [i],val);
+        PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC      [i],reg_EVENT_ADDRESS_SRC      [i]);
+        PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST_VAL [i],reg_EVENT_ADDRESS_DEST_VAL [i]);
+        PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST     [i],reg_EVENT_ADDRESS_DEST     [i]);
+
+	internal_BRANCH_EVENT_VAL [i] = val;
+      }
+      }
+
     log_end(Update_Prediction_Table,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 88)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 94)
@@ -45,8 +45,7 @@
             reg_UPT_TOP              [i] = 0;
             reg_UPT_UPDATE           [i] = 0;
-            reg_UPT_NB_NEED_UPDATE   [i] = 0;
                                                                                     
             reg_IS_ACCURATE          [i] = true;
-
+            
             reg_EVENT_STATE          [i] = EVENT_STATE_OK;
           }
@@ -54,4 +53,8 @@
     else
       {
+        bool flush_UFPT [_param->_nb_context];
+	for (uint32_t i=0; i<_param->_nb_context; i++)
+          flush_UFPT [i] = false;
+
 	// ===================================================================
 	// =====[ GARBAGE COLLECTOR ]=========================================
@@ -166,4 +169,7 @@
               Tbranch_condition_t condition  ;
               Tcontrol_t          is_accurate;
+              Taddress_t          address_src   = PORT_READ(in_DECOD_BTB_ADDRESS_SRC  [i]);
+              Taddress_t          address_dest  = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
+              Tcontrol_t          last_take     = PORT_READ(in_DECOD_BTB_LAST_TAKE    [i]);
 
               log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * DECOD[%d] - Accepted",i);
@@ -176,31 +182,27 @@
 		{
                   // Have a miss !!!
+#ifdef DEBUG_TEST
+                  if (reg_EVENT_STATE [context] != EVENT_STATE_OK)
+                    throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
+#endif
+                  
+                  if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
+                    {
+                      // Change state
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
+                      reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
+                    }
+                  else
+                    {
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss - flush ufpt)",context);
+                      reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT;
+                    }
 
                   // Flush UPFT
-
-                  // It's to accelerate miss speculation
-                  if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
-                    {
-                      // No entry need prediction, flush all entry -> Reset
-                      for (uint32_t j=0; j<_param->_size_ufpt_queue[context]; ++j)
-                        reg_UPDATE_FETCH_PREDICTION_TABLE [context][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
-                      reg_UFPT_BOTTOM [context] = 0;
-                      reg_UFPT_TOP    [context] = 0;
-//                    reg_UFPT_UPDATE [context] = 0;
-                    }
-                  else
-                    {
-                      reg_UFPT_UPDATE [context] = reg_UFPT_TOP [context];
-
-#ifdef DEBUG_TEST
-                      if (reg_EVENT_STATE [context] == EVENT_STATE_OK)
-                        throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
-#endif
-                      
-                      // Change state
-                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT (decod - miss)",context);
-                      
-                      reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT;
-                    }
+                  flush_UFPT [context] = true;
+
+                  reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
+                  reg_EVENT_ADDRESS_DEST_VAL[context] = last_take;
+                  reg_EVENT_ADDRESS_DEST    [context] = address_dest;
 
                   // Push upt (from decod interface)
@@ -209,7 +211,7 @@
 
                   reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition         = condition;
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src       = PORT_READ(in_DECOD_BTB_ADDRESS_SRC  [i]);
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest      = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
-                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take         = PORT_READ(in_DECOD_BTB_LAST_TAKE    [i]);
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src       = address_src ;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest      = address_dest;
+                  reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take         = last_take   ;
 //                reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
                   reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate       = is_accurate;
@@ -277,8 +279,4 @@
               reg_UPT_TOP     [context] = (upt_ptr_write+1)%_param->_size_upt_queue [context];
 //            reg_UPT_UPDATE  [context] = reg_UPT_TOP [context];
-              if (need_update(condition))
-                {
-                  reg_UPT_NB_NEED_UPDATE  [context] ++;
-                }
 	    }
 
@@ -296,56 +294,59 @@
 	      Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
 	      Tdepth_t   depth   = (_param->_have_port_depth     )?PORT_READ(in_BRANCH_COMPLETE_DEPTH      [i]):0;
+              Tcontrol_t miss      = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
+              Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE            [i];
+              Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST    [i];
 
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * BRANCH_COMPLETE[%d] - Accepted",i);
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context : %d",context);
 	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * depth   : %d",depth);
-	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss    : %d",internal_BRANCH_COMPLETE_MISS_PREDICTION [i]);
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * miss    : %d",miss);
 	      
-	      if (internal_BRANCH_COMPLETE_MISS_PREDICTION [i])
+              if (miss)
 		{
-		  // Miss case
-// //                breakpoint("Branch_complete and miss ...");
-
-//                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state [%d][%d] <- UPDATE_PREDICTION_STATE_EVENT (branch_complete)",context,depth);
-// 		  reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_EVENT;
-
-// 		  // Another prediction (prediction with depth higer)
-// 		  Tdepth_t top                = reg_TOP [context];
-// 		  uint32_t nb_elt_miss        = ((top> depth)?top:(top+_param->_size_queue[context]))-depth;
-// 		  uint32_t nb_elt_need_update = 1;
-// 		  for (uint32_t j=1; j<nb_elt_miss; j++)
-// 		    {
-// 		      uint32_t k=(depth+j)%_param->_size_queue[context];
-		      
-// 		      // Ifetch have make a prediction and it's a miss
-// 		      // When ifetch predict :
-// 		      //   * btb is not change       -> needn't update
-// 		      //   * direction is not change -> needn't update
-// 		      //   * ras have change         -> need    update
-
-// 		      Tbranch_condition_t cond = reg_UPDATE_PREDICTION_TABLE [context][k]._condition;
-// 		      if ((cond == BRANCH_CONDITION_NONE_WITH_WRITE_STACK) or
-// 			  (cond == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK) or
-// 			  (cond == BRANCH_CONDITION_READ_STACK))
-// 			{
-//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch miss, update ras)",context,k);
-
-// 			  nb_elt_need_update ++;
-// 			  reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_KO;
-// 			}
-// 		      else
-// 			{
-//                           log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state [%d][%d] <- UPDATE_PREDICTION_STATE_END (branch_complete, ifetch miss, don't update ras)",context,k);
-
-// 			  reg_UPDATE_PREDICTION_TABLE [context][k]._state = UPDATE_PREDICTION_STATE_END;
-// 			}
-// 		    }
-// 		  reg_NB_ELT_NEED_UPDATE [context] += nb_elt_need_update;
-
-// 		  // Update pointer :
-// 		  reg_TOP                [context]  = depth;
-// 		  reg_NB_ELT             [context] -= nb_elt_miss;
-// 	      reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
-
+                  // Have a miss !!!
+                  // Flush UPFT
+                  flush_UFPT [context] = true;
+                  
+                  // Flush UPT
+                  uint32_t top        = reg_UPT_TOP [context];
+                  uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; 
+                  for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
+                                j!=top; 
+                                j=(j+1)%_param->_size_upt_queue[context])
+                    reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
+                  
+                  // TOP is next write slot : last slot is TOP-1
+                  reg_UPT_UPDATE [context] = new_update;
+                  
+//                reg_UPT_BOTTOM [context];
+                  reg_UPT_TOP    [context] = depth;
+
+#ifdef DEBUG_TEST
+                  if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
+                    throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
+#endif
+                  
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * UPT  [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
+                  reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
+                  
+
+                  Taddress_t          address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
+
+                  if (reg_UFPT_NB_NEED_UPDATE [context] > 0)
+                    {
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
+                      reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UFPT_AND_UPT;
+                    }
+                  else
+                    {
+                      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_RAS (branch_complete - miss)",context);
+                      // have ras prediction ?
+                      reg_EVENT_STATE [context] = (new_update!=depth)?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT;
+                    }
+
+                  reg_EVENT_ADDRESS_SRC     [context] = address_src; // delay_slot is compute in Context_State
+                  reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
+                  reg_EVENT_ADDRESS_DEST    [context] = good_addr;
 		}
 	      else
@@ -363,5 +364,5 @@
 
 	      // In all case : update good_take
-	      reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = internal_BRANCH_COMPLETE_TAKE [i];
+	      reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
             }
 
@@ -381,4 +382,14 @@
               if (internal_UPDATE_FROM_UFPT [i])
                 {
+                // if free a slot, also all queue is updated
+                // Last slot ?
+                if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context])
+                  switch (reg_EVENT_STATE [context])
+                    {
+                    case EVENT_STATE_FLUSH_UFPT         : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break;
+                    case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = (reg_UPT_UPDATE[context]!=reg_UPT_TOP[context])?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT;  break;
+                    default : break;
+                    }
+                
                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * Update Fetch Prediction Table");
                   
@@ -393,7 +404,9 @@
                   reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
 
+
                   // Update pointer
-                  reg_UFPT_UPDATE [context] = (depth==0)?(_param->_size_ufpt_queue[context]-1):(depth-1);
-
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
+                  reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
                   // Free a register that need update ?
                   if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition))
@@ -405,9 +418,16 @@
                   
                   // Change state
-#ifdef DEBUG_TEST
-                  if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK   ) and
-                      (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO   ) and
-                      (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT))
-                    throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
+#ifdef DEBUG_TEST 
+                  if (internal_UPDATE_RAS [i])
+                    {
+                      if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT)
+                        throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
+                    }
+                  else
+                    {
+                      if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK   ) and
+                          (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO   ))
+                        throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
+                    }
 #endif
 
@@ -417,15 +437,25 @@
 
                   // Update pointer
+                  bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
+
                   if (internal_UPDATE_RAS [i])
-                    reg_UPT_UPDATE [context] = (depth==0)?(_param->_size_upt_queue[context]-1):(depth-1);
+                    {
+                      reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
+                    }
                   else
-                    reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
-
-                  // Free a register that need update ?
-                  if (need_update(reg_UPDATE_PREDICTION_TABLE [context][depth]._condition))
-                    reg_UPT_NB_NEED_UPDATE [context] --;
+                    {
+                      reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
+                    }
+                  
+                  // End and event ?
+                  if (end_event and
+                      (reg_EVENT_STATE [context] != EVENT_STATE_OK))
+                    {
+                      reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT;
+                    }
+
                   // Free the branch with no accurate ?
                   if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false)
-                    reg_IS_ACCURATE [i] = true;
+                    reg_IS_ACCURATE [context] = true;
                 }
 	    }
@@ -434,30 +464,67 @@
 	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
 
-// 	// ===================================================================
-// 	// =====[ BRANCH_EVENT ]==============================================
-// 	// ===================================================================
-// 	for (uint32_t i=0; i<_param->_nb_context; i++)
-// 	  if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
-//             {
-//               Tdepth_t depth = internal_BRANCH_EVENT_DEPTH [i];
-
-//               if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_EVENT)
-//                 {
-//                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state [%d][%d] <- UPDATE_PREDICTION_STATE_KO (branch_event)",i,depth);
-                  
-//                   reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_KO;
-//                 }
-//               else
-//                 {
-// #ifdef DEBUG_TEST
-//                   if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_WAITEND_AND_EVENT)
-//                     throw ERRORMORPHEO(FUNCTION,_("Branche event : invalid state"));
-// #endif
-              
-//                   log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state [%d][%d] <- UPDATE_PREDICTION_STATE_WAITEND (branch_event)",i,depth);
-                  
-//                   reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_WAITEND;
-//                 }
-//             }
+ 	// ===================================================================
+	// =====[ BRANCH_EVENT ]==============================================
+	// ===================================================================
+	for (uint32_t i=0; i<_param->_nb_context; i++)
+	  if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
+            {
+	      log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * UPDATE[%d] - Accepted",i);
+
+#ifdef DEBUG_TEST
+              if (reg_EVENT_STATE [i] != EVENT_STATE_UPDATE_CONTEXT)
+                throw ERRORMORPHEO(FUNCTION,_("Decod : invalid event state."));
+#endif
+              
+              // Change state
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_OK (branch_event)",i);
+              
+              reg_EVENT_STATE [i] = EVENT_STATE_OK;
+            }
+
+ 	// ===================================================================
+	// =====[ FLUSH ]=====================================================
+	// ===================================================================
+
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+          {
+            if (flush_UFPT [i])
+              {
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * Flush Update Fetch Prediction Table");
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * context                          : %d",i);
+                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_NB_NEED_UPDATE          : %d",reg_UFPT_NB_NEED_UPDATE [i]);
+
+              // It's to accelerate miss speculation
+              if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
+                {
+
+                  // No entry need prediction, flush all entry -> Reset
+                  for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
+                    reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
+                  reg_UFPT_BOTTOM [i] = 0;
+                  reg_UFPT_TOP    [i] = 0;
+//                reg_UFPT_UPDATE [i];
+                }
+              else
+                {
+                  for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
+                    reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
+                  
+                  // TOP is next write slot : last slot is TOP-1
+                  uint32_t top = reg_UFPT_TOP [i];
+                  reg_UFPT_UPDATE [i] = ((top==0)?_param->_size_ufpt_queue[i]:top)-1;
+                  
+//                reg_UFPT_BOTTOM [i];
+//                reg_UFPT_TOP    [i];
+                }
+
+              log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_UFPT_UPDATE         (after ) : %d",reg_UFPT_UPDATE [i]);
+
+              }
+          }
+
+ 	// ===================================================================
+	// =====[ PRINT ]=====================================================
+	// ===================================================================
 
 #if (DEBUG >= DEBUG_TRACE)
@@ -468,7 +535,6 @@
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_IS_ACCURATE           : %d",reg_IS_ACCURATE        [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_STATE           : %s"  ,toString(reg_EVENT_STATE [i]).c_str());
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_RAS_CORRUPTED   : %d"  ,reg_EVENT_RAS_CORRUPTED   [i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC     : %.8x",reg_EVENT_ADDRESS_SRC     [i]);
-        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_SRC_VAL : %d"  ,reg_EVENT_ADDRESS_SRC_VAL [i]);
+        log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_DEST_VAL: %d"  ,reg_EVENT_ADDRESS_DEST_VAL[i]);
         log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * reg_EVENT_ADDRESS_DEST    : %.8x",reg_EVENT_ADDRESS_DEST    [i]);
 
@@ -476,4 +542,5 @@
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_BOTTOM         : %d",reg_UFPT_BOTTOM         [i]);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_TOP            : %d",reg_UFPT_TOP            [i]);
+	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_UPDATE         : %d",reg_UFPT_UPDATE         [i]);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
 	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
@@ -495,5 +562,4 @@
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_TOP             : %d",reg_UPT_TOP            [i]);
 	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_UPDATE          : %d",reg_UPT_UPDATE         [i]);
-	log_printf(TRACE,Update_Prediction_Table,FUNCTION,"      * reg_UPT_NB_NEED_UPDATE  : %d",reg_UPT_NB_NEED_UPDATE [i]);
 	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
 	  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"        [%d] %.4d, %.8x %.8x, %.1d %.1d %.1d, %.8d %.8x %.4d - %s",
