Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 95) @@ -54,4 +54,5 @@ //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); @@ -129,4 +130,5 @@ //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); @@ -1234,4 +1236,5 @@ //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 95) @@ -70,4 +70,5 @@ //public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context] public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context] public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_DEST ;//[nb_context] @@ -116,4 +117,6 @@ public : SC_OUT(Tcontrol_t ) ** out_EVENT_ADDRESS_NEXT_VAL ;//[nb_context] public : SC_OUT(Tcontrol_t ) ** out_EVENT_IS_DS_TAKE ;//[nb_context] + public : SC_OUT(Tevent_type_t ) ** out_EVENT_TYPE ;//[nb_context] + public : SC_OUT(Tdepth_t ) ** out_EVENT_DEPTH ;//[nb_context] // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 95) @@ -66,4 +66,5 @@ // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t ,_param->_size_instruction_address); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 95) @@ -34,4 +34,5 @@ // DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 95) @@ -69,12 +69,13 @@ if (is_valid) { + Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]); reg_STATE [i] = CONTEXT_STATE_KO_MISS; - reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot - reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST[i]); // address_next - reg_EVENT_ADDRESS_EPCR_VAL [i] = 1; // address_dest is valid + reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot + reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next + reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val; //reg_EVENT_ADDRESS_EEAR [i] = 0; reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; - reg_EVENT_IS_DELAY_SLOT [i] = 1; - reg_EVENT_IS_DS_TAKE [i] = 0;// ?? + reg_EVENT_IS_DELAY_SLOT [i] = dest_val; + reg_EVENT_IS_DS_TAKE [i] = dest_val; reg_EVENT_DEPTH [i] = depth; } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h (revision 95) @@ -234,5 +234,5 @@ // ===== l.bf 11 - w = y+(11<<2); + w = y+(11); request.push_back (entry_t( 0x1000000b,x,y,z, @@ -262,5 +262,5 @@ // ===== l.bf -9 - w = y+(-9<<2); + w = y+(-9); request.push_back (entry_t( 0x13fffff7,x,y,z, @@ -290,5 +290,5 @@ // ===== l.bnf 11 - w = y+(11<<2); + w = y+(11); request.push_back (entry_t( 0x0c00000b,x,y,z, @@ -318,5 +318,5 @@ // ===== l.bnf -9 - w = y+(-9<<2); + w = y+(-9); request.push_back (entry_t( 0x0ffffff7,x,y,z, @@ -382,5 +382,5 @@ // ===== l.j 1018 - w = y+(1018<<2); + w = y+(1018); request.push_back (entry_t( 0x000003fa,x,y,z, @@ -410,5 +410,5 @@ // ===== l.j -1018 - w = y+(-1018<<2); + w = y+(-1018); request.push_back (entry_t( 0x03fffc06,x,y,z, @@ -438,5 +438,5 @@ // ===== l.jal 1018 - w = y+(1018<<2); + w = y+(1018); request.push_back (entry_t( 0x040003fa,x,y,z, @@ -466,5 +466,5 @@ // ===== l.jal -1018 - w = y+(-1018<<2); + w = y+(-1018); request.push_back (entry_t( 0x07fffc06,x,y,z, Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp (revision 95) @@ -89,5 +89,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); + ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_allocation.cpp (revision 95) @@ -67,5 +67,5 @@ ALLOC1_SIGNAL_IN ( in_DECOD_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_IN ( in_DECOD_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_DECOD_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -96,5 +96,5 @@ ALLOC1_SIGNAL_OUT(out_DECOD_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_DECOD_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_DECOD_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Parameters.cpp (revision 95) @@ -42,11 +42,12 @@ if (is_toplevel) { - _size_context_id = log2(nb_context); - _size_nb_inst_decod = log2(_size_queue)+1; - _size_depth = log2(max(_nb_branch_speculated,_nb_context)); - _size_general_data = size_general_data; + _size_context_id = log2(nb_context); + _size_nb_inst_decod = log2(_size_queue)+1; + _size_depth = log2(max(_nb_branch_speculated,_nb_context)); + _size_general_data = size_general_data; + _size_instruction_address = size_general_data-2; - _have_port_context_id = _size_context_id > 0; - _have_port_depth = _size_depth > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; copy (); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/SelfTest/src/test.cpp (revision 95) @@ -71,4 +71,5 @@ ALLOC1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ," in_UPDATE_CONTEXT_ID ",Tcontext_t,_param->_nb_inst_update ); ALLOC1_SC_SIGNAL( in_UPDATE_PUSH ," in_UPDATE_PUSH ",Tcontrol_t,_param->_nb_inst_update ); + ALLOC1_SC_SIGNAL( in_UPDATE_FLUSH ," in_UPDATE_FLUSH ",Tcontrol_t,_param->_nb_inst_update ); ALLOC1_SC_SIGNAL( in_UPDATE_INDEX ," in_UPDATE_INDEX ",Tptr_t ,_param->_nb_inst_update ); ALLOC1_SC_SIGNAL( in_UPDATE_ADDRESS ," in_UPDATE_ADDRESS ",Taddress_t,_param->_nb_inst_update ); @@ -109,4 +110,5 @@ INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update ); INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_PUSH ,_param->_nb_inst_update ); + INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_FLUSH ,_param->_nb_inst_update ); INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_INDEX ,_param->_nb_inst_update ); INSTANCE1_SC_SIGNAL(_Return_Address_Stack, in_UPDATE_ADDRESS ,_param->_nb_inst_update ); @@ -451,4 +453,5 @@ DELETE1_SC_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update); + DELETE1_SC_SIGNAL( in_UPDATE_FLUSH ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update); DELETE1_SC_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/include/Return_Address_Stack.h (revision 95) @@ -88,4 +88,5 @@ public : SC_IN (Tcontext_t) ** in_UPDATE_CONTEXT_ID ; //[nb_inst_update] public : SC_IN (Tcontrol_t) ** in_UPDATE_PUSH ; //[nb_inst_update] 1 = push, else pop + public : SC_IN (Tcontrol_t) ** in_UPDATE_FLUSH ; //[nb_inst_update] 1 = push, else pop public : SC_IN (Taddress_t) ** in_UPDATE_ADDRESS ; //[nb_inst_update] public : SC_IN (Tptr_t ) ** in_UPDATE_INDEX ; //[nb_inst_update] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Parameters.cpp (revision 95) @@ -37,5 +37,5 @@ _nb_inst_update = nb_inst_update ; - _size_index = max(size_queue,nb_context); + _size_index = log2(max(size_queue,nb_context)); test(); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_allocation.cpp (revision 95) @@ -91,4 +91,5 @@ ALLOC1_SIGNAL_IN ( in_UPDATE_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); ALLOC1_SIGNAL_IN ( in_UPDATE_PUSH ,"push" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_UPDATE_FLUSH ,"flush" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_UPDATE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_UPDATE_INDEX ,"index" ,Tptr_t ,_param->_size_index); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_deallocation.cpp (revision 95) @@ -52,4 +52,5 @@ DELETE1_SIGNAL( in_UPDATE_CONTEXT_ID ,_param->_nb_inst_update,_param->_size_context_id); DELETE1_SIGNAL( in_UPDATE_PUSH ,_param->_nb_inst_update,1); + DELETE1_SIGNAL( in_UPDATE_FLUSH ,_param->_nb_inst_update,1); DELETE1_SIGNAL( in_UPDATE_ADDRESS ,_param->_nb_inst_update,_param->_size_instruction_address); DELETE1_SIGNAL( in_UPDATE_INDEX ,_param->_nb_inst_update,_param->_size_index); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Return_Address_Stack/src/Return_Address_Stack_transition.cpp (revision 95) @@ -207,5 +207,5 @@ if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i]) { - ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); + throw ERRORMORPHEO(FUNCTION,"Fonction à implémenter !!!!!!!!!!!!"); @@ -217,4 +217,5 @@ // Tcontrol_t ifetch = PORT_READ(in_UPDATE_PREDICTION_IFETCH [i]); // Tcontrol_t push = PORT_READ(in_UPDATE_PUSH [i]); +// Tcontrol_t flush = PORT_READ(in_UPDATE_FLUSH [i]); // Tptr_t index = PORT_READ(in_UPDATE_INDEX [i]); // Taddress_t address = PORT_READ(in_UPDATE_ADDRESS [i]); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_min.cfg (revision 95) @@ -36,3 +36,4 @@ 1 1 +1 # dir_pht_size_address_share [2] [3] 2 2 +1 # ras_size_queue [0] [nb_context] -2 2 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [0] [nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context.cfg (revision 95) @@ -6,8 +6,8 @@ 1 4 *4 # nb_inst_decod [0] [nb_decod_unit] 1 1 +1 # nb_inst_branch_predict -1 2 +1 # nb_inst_branch_decod -1 2 +1 # nb_inst_branch_update -1 2 +1 # nb_inst_branch_complete -2 8 *4 # btb_size_queue +2 2 +1 # nb_inst_branch_decod +2 2 +1 # nb_inst_branch_update +2 2 +1 # nb_inst_branch_complete +2 8 *8 # btb_size_queue 2 2 +1 # btb_associativity 2 2 +1 # btb_size_counter @@ -35,4 +35,5 @@ 1 1 +1 # dir_pht_size_address_share [1] [3] 1 1 +1 # dir_pht_size_address_share [2] [3] -2 4 *2 # ras_size_queue [0] [nb_context] -2 4 *2 # upt_size_queue [0] [nb_context] +4 4 *2 # ras_size_queue [0] [nb_context] +4 4 *2 # upt_size_queue [0] [nb_context] +2 2 +1 # ufpt_size_queue [0] [nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_mono_context_multi_decod.cfg (revision 95) @@ -40,2 +40,3 @@ 4 4 *2 # ras_size_queue [0] [nb_context] 4 4 *4 # upt_size_queue [0] [nb_context] +2 2 *4 # ufpt_size_queue [0] [nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/config_multi_context.cfg (revision 95) @@ -46,2 +46,6 @@ 4 4 *4 # upt_size_queue [2] [nb_context] 8 8 *4 # upt_size_queue [3] [nb_context] +1 1 *4 # ufpt_size_queue [0] [nb_context] +4 4 *4 # ufpt_size_queue [1] [nb_context] +2 2 *4 # ufpt_size_queue [2] [nb_context] +4 4 *4 # ufpt_size_queue [3] [nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/main.cpp (revision 95) @@ -37,4 +37,5 @@ err (_(" * ras_size_queue [nb_context] (uint32_t )\n")); err (_(" * upt_size_queue [nb_context] (uint32_t )\n")); + err (_(" * ufpt_size_queue [nb_context] (uint32_t )\n")); exit (1); @@ -57,5 +58,5 @@ uint32_t _size_address = fromString(argv[x++]); - if (argc != static_cast(2+NB_PARAMS+3*_nb_context+_nb_decod_unit)) + if (argc != static_cast(2+NB_PARAMS+4*_nb_context+_nb_decod_unit)) usage (argc, argv); @@ -102,4 +103,7 @@ for (uint32_t i=0; i<_nb_context; i++) _upt_size_queue [i] = fromString(argv[x++]); + uint32_t * _ufpt_size_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; i++) + _ufpt_size_queue [i] = fromString(argv[x++]); int _return = EXIT_SUCCESS; @@ -130,4 +134,5 @@ _ras_size_queue , _upt_size_queue , + _ufpt_size_queue , true // is_toplevel ); @@ -152,4 +157,5 @@ delete [] _ras_size_queue ; delete [] _upt_size_queue ; + delete [] _ufpt_size_queue ; return (_return); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 95) @@ -91,6 +91,11 @@ //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"out_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); @@ -152,8 +157,12 @@ //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); if (_param->_have_port_depth) { + INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_DEPTH ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_CURRENT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_DEPTH_MIN ,_param->_nb_context); @@ -211,5 +220,5 @@ for (uint32_t i=0; i<_param->_nb_context; ++i) { - TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request +// TEST(Tcontrol_t,out_PREDICT_ACK [i]->read(),1); // Accept new request TEST(Tcontrol_t,out_BRANCH_EVENT_VAL [i]->read(),0); TEST(Tdepth_t ,out_DEPTH_CURRENT [i]->read(),0); @@ -346,11 +355,16 @@ DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete); - DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context); - DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); -//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); -//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); - DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); - DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); +//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); +//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); +//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); + + DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/config_mono_context.cfg (revision 95) @@ -1,5 +1,5 @@ Update_Prediction_Table 1 1 +1 # nb_context -4 8 *2 # size_upt_queue [0] [nb_context] +4 8 +1 # size_upt_queue [0] [nb_context] 1 4 +1 # size_ufpt_queue [0] [nb_context] 32 32 *2 # size_address Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 95) @@ -7,6 +7,6 @@ */ -#define NB_ITERATION 8 -#define CYCLE_MAX (128*NB_ITERATION) +#define NB_ITERATION 16 +#define CYCLE_MAX (1024*NB_ITERATION) #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h" @@ -136,4 +136,9 @@ ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update); ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); + + ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context); @@ -225,6 +230,9 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context); if (_param->_have_port_depth) { + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context); @@ -253,7 +261,7 @@ const int32_t percent_transaction_branch_event = 75; - const bool test1 = false; - const bool test2 = false; - const bool test3 = false; + const bool test1 = true; + const bool test2 = true; + const bool test3 = true; const bool test4 = true; @@ -270,16 +278,18 @@ in_NRESET->write(1); - Tdepth_t ufpt_bottom [_param->_nb_context]; - Tdepth_t ufpt_top [_param->_nb_context]; - - Tdepth_t upt_bottom [_param->_nb_context]; - Tdepth_t upt_top [_param->_nb_context]; + Tdepth_t ufpt_bottom [_param->_nb_context]; + Tdepth_t ufpt_top [_param->_nb_context]; + + Tdepth_t upt_bottom [_param->_nb_context]; + Tdepth_t upt_top [_param->_nb_context]; + Tdepth_t upt_top_event[_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; ++i) { - ufpt_bottom [i] = 0; - ufpt_top [i] = 0; - upt_bottom [i] = 0; - upt_top [i] = 0; + ufpt_bottom [i] = 0; + ufpt_top [i] = 0; + upt_bottom [i] = 0; + upt_top [i] = 0; + upt_top_event[i] = 0; } @@ -305,5 +315,9 @@ for (uint32_t i=0; i<_param->_nb_inst_update; ++i) in_UPDATE_ACK [i]->write(0); - + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); + in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE ); + } //--------------------------------------------------------------------- //--------------------------------------------------------------------- @@ -913,5 +927,16 @@ } } - + + { + LABEL("EVENT_STATE"); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); + } // Wait Garbage Collector @@ -1337,4 +1362,16 @@ } + { + LABEL("EVENT_STATE"); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); + } + // Wait Garbage Collector { @@ -1378,5 +1415,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); - request.is_accurate = false; + request.is_accurate = true ; request.miss_ifetch = false; request.miss_decod = false; @@ -1472,6 +1509,6 @@ LABEL("DECOD [%d] %d - %d", port, - in_PREDICT_VAL [port]->read(), - out_PREDICT_ACK [port]->read()); + in_DECOD_VAL [port]->read(), + out_DECOD_ACK [port]->read()); if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read()) @@ -1520,5 +1557,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); - request.is_accurate = false; + request.is_accurate = true ; request.miss_ifetch = false; request.miss_decod = false; @@ -1583,5 +1620,5 @@ std::list::iterator it_event; { - LABEL("BRANCH_COMPLETE - hit ifetch"); + LABEL("BRANCH_COMPLETE - Miss ifetch"); uint32_t port = rand() % _param->_nb_inst_branch_complete; @@ -1600,5 +1637,7 @@ if (update_ras(it_event->condition)) - it_event->address_good = ~(it_event->address_dest); + { + it_event->address_good = ~(it_event->address_dest); + } else { @@ -1649,5 +1688,66 @@ TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good); - upt_top [it_event->context] = it_event->upt_ptr; + upt_top_event [it_event->context] = upt_top [it_event->context]; + upt_top [it_event->context] = it_event->upt_ptr; + } + + SC_START(1); + } while (not have_transaction); + + in_BRANCH_COMPLETE_VAL [port]->write(0); + + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + } + } + + { + LABEL("BRANCH_COMPLETE - Hit ifetch"); + + uint32_t port = rand() % _param->_nb_inst_branch_complete; + + LABEL(" * port : %d",port); + + std::list::iterator it_upt = upt.begin(); + + while (it_upt != it_event) + { + bool have_transaction = false; + + do + { + in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)write(it_upt->context ); + in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); + in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); + in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + + if (_param->_have_port_depth) + TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]); + TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); + + SC_START(0); + + LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read()); + + if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read()) + { + LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); + LABEL(" * CONTEXT_ID %d" ,it_upt->context ); + LABEL(" * DEPTH %d" ,it_upt->upt_ptr ); + LABEL(" * CONDITION %d" ,it_upt->condition ); + LABEL(" * ADDRESS %.8x",it_upt->address_dest); + LABEL(" * FLAG %d" ,it_upt->flag ); + + have_transaction = true; + + TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit ); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take ); + it_upt->take_good = it_upt->take; + TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src ); + TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest); + + it_upt++; } @@ -1740,5 +1840,5 @@ { - LABEL("UPDATE - upt"); + LABEL("UPDATE - upt (after event)"); uint32_t port = 0; @@ -1746,11 +1846,13 @@ LABEL(" * port : %d",port); std::list::iterator it_upt = upt.end(); - --it_upt; // for (uint32_t i=0; icondition)) do { @@ -1768,12 +1870,22 @@ { LABEL("UPDATE [%d] - Transaction accepted",port); + LABEL(" * address_src : %.8x",it_upt->address_src); + LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read()); + have_transaction = true; + bool btb_val = ((it_upt == it_event) and + (update_btb(it_upt->condition))); + bool dir_val = ((it_upt == it_event) and + update_dir(it_upt->condition) and + not (it_upt->miss_ifetch or it_upt->miss_decod)); + bool ras_val = update_ras(it_upt->condition); + if (_param->_have_port_context_id) TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context); TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit); - TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); - TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition)); - if (update_btb(it_upt->condition)) + TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val); + + if (btb_val) { TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src); @@ -1781,11 +1893,15 @@ TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition); } - TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod)); + TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val); - if (update_dir(it_upt->condition)) + if (dir_val) + { + TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good); if (_param->_have_port_history) TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history); - TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition)); - if (update_ras(it_upt->condition)) + } + TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val); + + if (ras_val) { // TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0); @@ -1796,5 +1912,5 @@ } - -- it_upt; +// -- it_upt; } @@ -1808,7 +1924,8 @@ // TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]); } + while (it_upt != it_event); + } -// upt.clear(); // Not yet - + { LABEL("BRANCH_EVENT - have miss decod"); @@ -1852,11 +1969,24 @@ } } - + { - LABEL("UPDATE - upt"); + LABEL("EVENT_STATE"); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); + + SC_START(1); + in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); + } + + { + LABEL("UPDATE - upt (before event)"); uint32_t port = 0; LABEL(" * port : %d",port); + LABEL(" * size : %d",upt.size()); std::list::iterator it_upt = upt.begin(); @@ -1908,5 +2038,5 @@ } - -- it_upt; + ++ it_upt; } @@ -1920,14 +2050,20 @@ } } - upt.clear(); // Not yet + upt.clear(); // Wait Garbage Collector { - upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context]; -// upt_top [context] = (upt_top [context]); + LABEL("GARBAGE COLLECTOR"); + LABEL(" * upt bottom : %d",upt_bottom [context]); + LABEL(" * upt top : %d",upt_top [context]); + + upt_top [context] = (upt_top_event [context]); + upt_bottom [context] = (upt_top [context]); while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or (upt_top [context] != out_DEPTH_MAX [context]->read())) - SC_START(1); + { + SC_START(1); + } } @@ -1993,7 +2129,7 @@ delete [] out_BRANCH_EVENT_VAL ; delete [] in_BRANCH_EVENT_ACK ; -// delete [] in_BRANCH_EVENT_CONTEXT_ID ; -// delete [] in_BRANCH_EVENT_DEPTH ; -// delete [] out_BRANCH_EVENT_MISS_PREDICTION; +//delete [] in_BRANCH_EVENT_CONTEXT_ID ; +//delete [] in_BRANCH_EVENT_DEPTH ; +//delete [] out_BRANCH_EVENT_MISS_PREDICTION; delete [] out_BRANCH_EVENT_ADDRESS_SRC ; delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL; @@ -2019,4 +2155,8 @@ delete [] out_UPDATE_RAS_PREDICTION_IFETCH; + DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); + // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] out_DEPTH_CURRENT; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Types.h (revision 95) @@ -21,10 +21,10 @@ typedef enum { - EVENT_STATE_OK , // Can predict - EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt - EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt - EVENT_STATE_FLUSH_UPT_RAS , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS - EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush - EVENT_STATE_UPDATE_CONTEXT // prediction unit is update, send signal to context manager + EVENT_STATE_OK , // Can predict + EVENT_STATE_FLUSH_UFPT , // in decod stage, detect a miss, continue to execute but flush ufpt + EVENT_STATE_FLUSH_UFPT_AND_UPT , // in commit stage, detect a miss, stop context and flush ufpt and upt + EVENT_STATE_FLUSH_UPT , // in commit stage, detect a miss, context is stop and ufpt is flush, update RAS + EVENT_STATE_UPDATE_CONTEXT , // prediction unit is update, send signal to context manager + EVENT_STATE_WAIT_END_EVENT // prediction unit is ok, wait the end of envent (send by Context State) } event_state_t; @@ -44,5 +44,6 @@ UPDATE_PREDICTION_STATE_KO , // this branch is a miss prediction UPDATE_PREDICTION_STATE_EVENT , // previous branch is a miss prediction - UPDATE_PREDICTION_STATE_END // branch is updated + UPDATE_PREDICTION_STATE_END_OK , // branch is updated, update pointer + UPDATE_PREDICTION_STATE_END_KO // branch is updated, don't update pointer } upt_state_t; @@ -114,10 +115,10 @@ switch (x) { - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT_RAS : return "flush_upt_ras" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT : return "flush_upt" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_OK : return "ok" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT : return "flush_ufpt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UFPT_AND_UPT : return "flush_ufpt_and_upt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_FLUSH_UPT : return "flush_upt" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_UPDATE_CONTEXT : return "update_context" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::EVENT_STATE_WAIT_END_EVENT : return "wait_and_event" ; break; default : return "" ; break; } @@ -145,5 +146,6 @@ case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_KO : return "ko" ; break; case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_EVENT : return "event" ; break; - case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END : return "end" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_OK : return "end_ok" ; break; + case morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::UPDATE_PREDICTION_STATE_END_KO : return "end_ko" ; break; default : return "" ; break; } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 95) @@ -170,4 +170,5 @@ private : uint32_t * reg_UPT_BOTTOM ; //[nb_context] private : uint32_t * reg_UPT_TOP ; //[nb_context] + private : uint32_t * reg_UPT_TOP_EVENT ; //[nb_context] private : uint32_t * reg_UPT_UPDATE ; //[nb_context] Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 95) @@ -197,4 +197,5 @@ ALLOC1(reg_UPT_BOTTOM ,uint32_t ,_param->_nb_context); ALLOC1(reg_UPT_TOP ,uint32_t ,_param->_nb_context); + ALLOC1(reg_UPT_TOP_EVENT ,uint32_t ,_param->_nb_context); ALLOC1(reg_UPT_UPDATE ,uint32_t ,_param->_nb_context); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 95) @@ -80,15 +80,13 @@ // ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - delete [] out_BRANCH_EVENT_VAL ; - delete [] in_BRANCH_EVENT_ACK ; -// if (_param->_have_port_context_id) -// delete [] in_BRANCH_EVENT_CONTEXT_ID ; -// if (_param->_have_port_depth) -// delete [] in_BRANCH_EVENT_DEPTH ; -// delete [] out_BRANCH_EVENT_MISS_PREDICTION; - delete [] out_BRANCH_EVENT_ADDRESS_SRC ; - delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL; - delete [] out_BRANCH_EVENT_ADDRESS_DEST ; - + DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); +// DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); +// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); +// DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); + // ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ delete [] out_UPDATE_VAL ; @@ -118,11 +116,8 @@ // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - if (_param->_have_port_depth) - { - delete [] out_DEPTH_CURRENT; - delete [] out_DEPTH_MIN; - } - delete [] out_DEPTH_MAX; - + DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_DEPTH_MAX ,_param->_nb_context,_param->_size_depth+1); + // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ DELETE1(internal_PREDICT_ACK ,_param->_nb_inst_predict); @@ -155,4 +150,5 @@ DELETE1(reg_UPT_BOTTOM ,_param->_nb_context); DELETE1(reg_UPT_TOP ,_param->_nb_context); + DELETE1(reg_UPT_TOP_EVENT ,_param->_nb_context); DELETE1(reg_UPT_UPDATE ,_param->_nb_context); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_decod.cpp (revision 95) @@ -26,4 +26,6 @@ // WARNING : One branch per context per cycle + if (PORT_READ(in_NRESET) != 0) + { for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { @@ -58,5 +60,5 @@ PORT_WRITE(out_DECOD_ACK [i], internal_DECOD_ACK [i]); } - + } log_end(Update_Prediction_Table,FUNCTION); }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 95) @@ -57,7 +57,7 @@ event_state_t event_state = reg_EVENT_STATE [i]; - retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or + retire_ras_from_ufpt [i] = ((event_state == EVENT_STATE_FLUSH_UFPT ) or (event_state == EVENT_STATE_FLUSH_UFPT_AND_UPT)); - retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT_RAS); + retire_ras_from_upt [i] = (event_state == EVENT_STATE_FLUSH_UPT); ufpt_update [i] = true; @@ -154,7 +154,8 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); - Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK) or - (state == UPDATE_PREDICTION_STATE_KO)); - Tcontrol_t state_is_event = (state == UPDATE_PREDICTION_STATE_EVENT); + Tcontrol_t state_is_ok_ko = ((state == UPDATE_PREDICTION_STATE_OK ) or + (state == UPDATE_PREDICTION_STATE_KO )); + Tcontrol_t state_is_event = ((state == UPDATE_PREDICTION_STATE_KO ) or + (state == UPDATE_PREDICTION_STATE_EVENT)); Tcontrol_t state_is_event_update = state_is_event and need_update(condition); Tcontrol_t state_is_event_no_update = state_is_event and not need_update(condition); @@ -167,5 +168,5 @@ else { - val = state_is_ok_ko; + val = (state == UPDATE_PREDICTION_STATE_OK); val_without_ack = false; } @@ -173,9 +174,9 @@ miss_prediction = (state != UPDATE_PREDICTION_STATE_OK); direction_good = reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take ; - btb_val = update_btb(condition); + btb_val = state_is_ok_ko and update_btb(condition); btb_address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src ; btb_address_dest = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest; btb_condition = condition; - dir_val = update_dir(condition) and ifetch; // if not ifetch, then static prediction + dir_val = state_is_ok_ko and update_dir(condition) and ifetch; // if not ifetch, then static prediction dir_history = reg_UPDATE_PREDICTION_TABLE [context][depth]._history ; ras_val = update_ras(condition); // repop/ repush data -> don't corrupt ras @@ -208,7 +209,9 @@ } } - + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val : %d",val ); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * val_without_ack : %d",val_without_ack); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_prediction : %d",miss_prediction); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction_good : %d",direction_good ); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * btb_val : %d",btb_val); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * dir_val : %d",dir_val); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 95) @@ -44,4 +44,5 @@ reg_UPT_BOTTOM [i] = 0; reg_UPT_TOP [i] = 0; + reg_UPT_TOP_EVENT [i] = 0; reg_UPT_UPDATE [i] = 0; @@ -87,7 +88,9 @@ { uint32_t bottom = reg_UPT_BOTTOM [i]; - + bool end_ok = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_OK); + bool end_ko = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END_KO); + // Test if state is end - if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END) + if (end_ok or end_ko) { log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom); @@ -96,6 +99,14 @@ // Free slot reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY; + // Update pointer reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i]; +// if (bottom = reg_UPT_UPDATE [i]) +// reg_UPT_UPDATE [i] = reg_UPT_BOTTOM [i]; + if (end_ko) // free + { + reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i]; + reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i]; + } } } @@ -299,7 +310,7 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss); if (miss) @@ -312,4 +323,8 @@ uint32_t top = reg_UPT_TOP [context]; uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update); + for (uint32_t j=(depth+1)%_param->_size_upt_queue[context]; j!=top; @@ -317,9 +332,8 @@ reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT; - // TOP is next write slot : last slot is TOP-1 - reg_UPT_UPDATE [context] = new_update; - -// reg_UPT_BOTTOM [context]; - reg_UPT_TOP [context] = depth; + +// reg_UPT_BOTTOM [context]; + reg_UPT_TOP [context] = depth; + reg_UPT_TOP_EVENT [context] = top; #ifdef DEBUG_TEST @@ -331,6 +345,10 @@ reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO; - - Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; + Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src; + event_state_t event_state = reg_EVENT_STATE [context]; + bool previous_update_ras = (event_state == EVENT_STATE_FLUSH_UPT); + bool update_ras = (new_update != depth); + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update_ras : %d",update_ras); if (reg_UFPT_NB_NEED_UPDATE [context] > 0) @@ -341,8 +359,19 @@ else { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UFPT_RAS (branch_complete - miss)",context); - // have ras prediction ? - reg_EVENT_STATE [context] = (new_update!=depth)?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; - } + if (not previous_update_ras) + { + // have ras prediction ? + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_FLUSH_UPT (branch_complete - miss)",context); + + reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT; + + } + } + + if (not previous_update_ras) + { + reg_UPT_UPDATE [context] = new_update; + } + // else no update reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State @@ -370,97 +399,129 @@ // =====[ UPDATE ]==================================================== // =================================================================== - for (uint32_t i=0; i<_param->_nb_inst_update; i++) - if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or - (internal_UPDATE_VAL_WITHOUT_ACK [i])) - { - Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; - Tdepth_t depth = internal_UPDATE_DEPTH [i]; - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); - - if (internal_UPDATE_FROM_UFPT [i]) + { + bool can_continue [_param->_nb_context]; + for (uint32_t i=0; i<_param->_nb_context; ++i) + can_continue [i] = true; + + for (uint32_t i=0; i<_param->_nb_inst_update; i++) + { + Tcontext_t context = internal_UPDATE_CONTEXT_ID [i]; + + if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or + (internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context])) { - // if free a slot, also all queue is updated - // Last slot ? - if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) - switch (reg_EVENT_STATE [context]) - { - case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; - case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = (reg_UPT_UPDATE[context]!=reg_UPT_TOP[context])?EVENT_STATE_FLUSH_UPT_RAS:EVENT_STATE_UPDATE_CONTEXT; break; - default : break; - } - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); - - // Change state -#ifdef DEBUG_TEST - if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) - throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); -#endif - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); - - reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; - - - // Update pointer - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); - reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); - // Free a register that need update ? - if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) - reg_UFPT_NB_NEED_UPDATE [context] --; + Tdepth_t depth = internal_UPDATE_DEPTH [i]; + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth); + + if (internal_UPDATE_FROM_UFPT [i]) + { + // if free a slot, also all queue is updated + // Last slot ? + if (reg_UFPT_UPDATE [context] == reg_UFPT_BOTTOM [context]) + switch (reg_EVENT_STATE [context]) + { + case EVENT_STATE_FLUSH_UFPT : reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; break; + // impossible to have an update on ufpt and reg_upt_update>reg_upt_top + case EVENT_STATE_FLUSH_UFPT_AND_UPT : reg_EVENT_STATE [context] = EVENT_STATE_FLUSH_UPT ; break; + default : break; + } + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table"); + + // Change state +#ifdef DEBUG_TEST + if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT) + throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state.")); +#endif + + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth); + + reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END; + + + // Update pointer + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]); + reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1; + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]); + // Free a register that need update ? + if (need_update(reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._condition)) + reg_UFPT_NB_NEED_UPDATE [context] --; + } + else + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); + + // Change state +#ifdef DEBUG_TEST + if (internal_UPDATE_RAS [i]) + { + if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and + (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) + throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); + } + else + { + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) + throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); + } +#endif + +// bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or +// (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); + bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); + + // Have an update, test the state to transiste to the good state + if (ko) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth); + + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; + } + else + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_OK (update)",context,depth); + + reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; + } + + // Update pointer + // * if update RAS : update pointer is decreaste until it equal at top pointer + if (internal_UPDATE_RAS [i]) + { + // if end_event, restart too bottom, else decrease pointer + bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); + + reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); + if (end_event) + { + reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context]; + reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; + } + else + { + reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1); + } + } + else + { + // increase pointer + reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; + } + + // Free the branch with no accurate ? + if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) + reg_IS_ACCURATE [context] = true; + } } else - { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table"); - - // Change state -#ifdef DEBUG_TEST - if (internal_UPDATE_RAS [i]) - { - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) - throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); - } - else - { - if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK ) and - (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO )) - throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state.")); - } -#endif - - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth); - - reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END; - - // Update pointer - bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]); - - if (internal_UPDATE_RAS [i]) - { - reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1); - } - else - { - reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context]; - } - - // End and event ? - if (end_event and - (reg_EVENT_STATE [context] != EVENT_STATE_OK)) - { - reg_EVENT_STATE [context] = EVENT_STATE_UPDATE_CONTEXT; - } - - // Free the branch with no accurate ? - if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) - reg_IS_ACCURATE [context] = true; - } - } + can_continue [context] = false; + } - // Round robin - reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; + // Round robin + reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context; + } // =================================================================== @@ -470,5 +531,5 @@ if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i])) { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i); #ifdef DEBUG_TEST @@ -478,8 +539,57 @@ // Change state - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (branch_event)",i); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_WAIT_END_EVENT (branch_event)",i); - reg_EVENT_STATE [i] = EVENT_STATE_OK; + reg_EVENT_STATE [i] = EVENT_STATE_WAIT_END_EVENT; } + + // =================================================================== + // =====[ EVENT ]===================================================== + // =================================================================== + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + //---------------------------------------------------------------- + // Cases + //---------------------------------------------------------------- + // * EVENT_TYPE_NONE - nothing + // * EVENT_TYPE_MISS_SPECULATION + // * EVENT_STATE_END - Change state, reset pointer + // * EVENT_TYPE_EXCEPTION - + // * EVENT_STATE_EVENT - Flush upft and upt + // * EVENT_STATE_END - Change state, reset pointer + // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update + // * EVENT_TYPE_SPR_ACCESS - nothing + // * EVENT_TYPE_MSYNC - nothing + // * EVENT_TYPE_PSYNC - nothing + // * EVENT_TYPE_CSYNC - nothing + + Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]); + Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); +// Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); + + // Test if end of miss + if ((event_state == EVENT_STATE_END) and + (event_type == EVENT_TYPE_MISS_SPECULATION)) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); + +#ifdef DEBUG_TEST + if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) + throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); +#endif + + // Change state + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); + + reg_EVENT_STATE [i] = EVENT_STATE_OK; + +// uint32_t bottom = reg_UPT_BOTTOM [i]; + +// reg_UPT_TOP [i] = bottom; +// reg_UPT_UPDATE [i] = bottom; + } + } // =================================================================== @@ -561,4 +671,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]); for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Parameters.h (revision 95) @@ -51,4 +51,5 @@ public : uint32_t * _ras_size_queue ;//[nb_context] public : uint32_t * _upt_size_queue ;//[nb_context] + public : uint32_t * _ufpt_size_queue ;//[nb_context] //public : uint32_t _size_context_id ; @@ -96,4 +97,5 @@ uint32_t * ras_size_queue ,//[nb_context] uint32_t * upt_size_queue ,//[nb_context] + uint32_t * ufpt_size_queue ,//[nb_context] bool is_toplevel=false ); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 95) @@ -111,5 +111,11 @@ //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_ADDRESS_DEST_VAL ; //[nb_context] public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_DEST ; //[nb_context] + + // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] + public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] + public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters.cpp (revision 95) @@ -42,4 +42,5 @@ uint32_t * ras_size_queue ,//[nb_context] uint32_t * upt_size_queue ,//[nb_context] + uint32_t * ufpt_size_queue ,//[nb_context] bool is_toplevel ) @@ -73,4 +74,5 @@ _ras_size_queue = ras_size_queue ; _upt_size_queue = upt_size_queue ; + _ufpt_size_queue = ufpt_size_queue ; _array_size_depth = new uint32_t [_nb_context]; @@ -133,4 +135,5 @@ (_nb_context , _upt_size_queue , + _ufpt_size_queue , _size_address , _nb_inst_branch_predict , Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters_print.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters_print.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Parameters_print.cpp (revision 95) @@ -68,4 +68,5 @@ xml. singleton_begin("ras_size_queue "); xml.attribut("value",toString(_ras_size_queue [i])); xml.singleton_end(); xml. singleton_begin("upt_size_queue "); xml.attribut("value",toString(_upt_size_queue [i])); xml.singleton_end(); + xml. singleton_begin("ufpt_size_queue "); xml.attribut("value",toString(_ufpt_size_queue [i])); xml.singleton_end(); xml. balise_close(); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 95) @@ -113,11 +113,12 @@ ALLOC1_INTERFACE("branch_event", IN,SOUTH, "branch_event", _param->_nb_context); - ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); - ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); + ALLOC1_VALACK_OUT(out_BRANCH_EVENT_VAL ,VAL); + ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); +// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); +// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); +// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,"address_dest_val",Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_DEST ,"address_dest" ,Taddress_t,_param->_size_address); } @@ -129,4 +130,13 @@ ALLOC1_SIGNAL_OUT(out_DEPTH_MIN ,"min" ,Tdepth_t,_param->_size_depth); ALLOC1_SIGNAL_OUT(out_DEPTH_MAX ,"max" ,Tdepth_t,_param->_size_depth+1); + } + + // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + { + ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); + + ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); + ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); + ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); } @@ -509,4 +519,6 @@ COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_PUSH" , dest,"out_UPDATE_"+toString(i)+"_RAS_PUSH" ); + COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_FLUSH" , + dest,"out_UPDATE_"+toString(i)+"_RAS_FLUSH" ); COMPONENT_MAP(_component,src , "in_UPDATE_"+toString(i)+ "_ADDRESS" , dest,"out_UPDATE_"+toString(i)+"_RAS_ADDRESS" ); @@ -636,4 +648,5 @@ //in_UPDATE_UPT_RAS_ADDRESS - component_map return_address_stack //in_UPDATE_UPT_RAS_PUSH - component_map return_address_stack + //in_UPDATE_UPT_RAS_FLUSH - component_map return_address_stack //in_UPDATE_UPT_RAS_INDEX - component_map return_address_stack //in_UPDATE_UPT_RAS_PREDICTION_IFETCH - component_map return_address_stack @@ -682,9 +695,25 @@ #endif - PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); - PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); - PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); - PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST"); - } + PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); + PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); + PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); + PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); + } + + for (uint32_t i=0; i<_param->_nb_context; i++) + { + dest = _name; + +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(i), + dest,"event_"+toString(i)); +#endif + + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE"); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_DEPTH",dest, "in_EVENT_"+toString(i)+"_DEPTH"); + } for (uint32_t i=0; i<_param->_nb_context; i++) Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 95) @@ -62,11 +62,16 @@ DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); - DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); - DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); -// DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); -// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); -// DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context,1); - DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); - DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_BRANCH_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); +// DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); +// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); +// DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); + + DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); + DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); + DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); DELETE1_SIGNAL(out_DEPTH_CURRENT ,_param->_nb_context,_param->_size_depth); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_1-decod_unit_1-a.cfg (revision 95) @@ -43,3 +43,4 @@ 8 8 +1 # ras_size_queue [0] [nb_context] 1 1 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [0] [nb_context] 1 1 +1 # size_inst_commit Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_1-a.cfg (revision 95) @@ -58,3 +58,7 @@ 2 2 +1 # upt_size_queue [2] [nb_context] 8 8 +1 # upt_size_queue [3] [nb_context] +6 6 +1 # ufpt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [1] [nb_context] +1 1 +1 # ufpt_size_queue [2] [nb_context] +4 4 +1 # ufpt_size_queue [3] [nb_context] 1 1 +1 # size_inst_commit Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-a.cfg (revision 95) @@ -63,3 +63,7 @@ 2 2 +1 # upt_size_queue [2] [nb_context] 8 8 +1 # upt_size_queue [3] [nb_context] +6 6 +1 # ufpt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [1] [nb_context] +1 1 +1 # ufpt_size_queue [2] [nb_context] +4 4 +1 # ufpt_size_queue [3] [nb_context] 1 1 +1 # size_inst_commit Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-context_4-decod_unit_2-b.cfg (revision 95) @@ -63,3 +63,7 @@ 2 2 +1 # upt_size_queue [2] [nb_context] 8 8 +1 # upt_size_queue [3] [nb_context] +6 6 +1 # ufpt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [1] [nb_context] +1 1 +1 # ufpt_size_queue [2] [nb_context] +4 4 +1 # ufpt_size_queue [3] [nb_context] 1 1 +1 # size_inst_commit Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/config-min.cfg (revision 95) @@ -43,3 +43,4 @@ 2 2 +1 # ras_size_queue [0] [nb_context] 1 1 +1 # upt_size_queue [0] [nb_context] +1 1 +1 # ufpt_size_queue [0] [nb_context] 1 1 +1 # size_inst_commit Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/main.cpp (revision 95) @@ -44,4 +44,5 @@ err (_(" * ras_size_queue [nb_context] (uint32_t )\n")); err (_(" * upt_size_queue [nb_context] (uint32_t )\n")); + err (_(" * ufpt_size_queue [nb_context] (uint32_t )\n")); err (_(" * size_inst_commit (uint32_t )\n")); @@ -69,5 +70,5 @@ uint32_t _nb_decod_unit = fromString(argv[x++]); - if (argc != static_cast(2+NB_PARAMS+5*_nb_context+5*_nb_decod_unit)) + if (argc != static_cast(2+NB_PARAMS+6*_nb_context+5*_nb_decod_unit)) { msg("argc : %d\n",argc); @@ -158,4 +159,8 @@ for (uint32_t i=0; i<_nb_context; ++i) _upt_size_queue [i] = fromString(argv[x++]); + + uint32_t * _ufpt_size_queue = new uint32_t [_nb_context]; + for (uint32_t i=0; i<_nb_context; ++i) + _ufpt_size_queue [i] = fromString(argv[x++]); uint32_t _size_inst_commit = fromString(argv[x++]); @@ -197,4 +202,5 @@ _ras_size_queue , _upt_size_queue , + _ufpt_size_queue , _size_inst_commit , true // is_toplevel @@ -231,4 +237,5 @@ delete [] _dir_pht_nb_counter ; delete [] _dir_pht_size_address_share ; + delete [] _ufpt_size_queue ; delete [] _upt_size_queue ; delete [] _ras_size_queue ; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Parameters.h (revision 95) @@ -65,4 +65,6 @@ public : uint32_t * _ras_size_queue ;//[nb_context] public : uint32_t * _upt_size_queue ;//[nb_context] + public : uint32_t * _ufpt_size_queue ;//[nb_context] + // context_state //public : uint32_t _size_nb_inst_commit ; @@ -132,4 +134,5 @@ uint32_t * ras_size_queue , uint32_t * upt_size_queue , + uint32_t * ufpt_size_queue , // context_state uint32_t size_nb_inst_commit , Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 95) @@ -564,18 +564,20 @@ #endif - COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" , - dest, "in_BRANCH_EVENT_"+toString(i)+"_VAL" ); - COMPONENT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" , - dest,"out_BRANCH_EVENT_"+toString(i)+"_ACK" ); -// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , -// dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); -// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , -// dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); -// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION", -// dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION"); - COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" , - dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); - COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , - dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_VAL" ); + COMPONENT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" , + dest,"out_BRANCH_EVENT_"+toString(i)+"_ACK" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , +// dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , +// dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); +// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" , +// dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL", + dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Parameters.cpp (revision 95) @@ -52,4 +52,5 @@ uint32_t * ras_size_queue , uint32_t * upt_size_queue , + uint32_t * ufpt_size_queue , // context_state uint32_t size_nb_inst_commit , @@ -93,4 +94,5 @@ _ras_size_queue = ras_size_queue ; _upt_size_queue = upt_size_queue ; + _ufpt_size_queue = ufpt_size_queue ; test(); @@ -114,5 +116,5 @@ _nb_inst_fetch [i] , log2(_upt_size_queue[i]) , - size_instruction_address ); + size_instruction_address ); } @@ -140,5 +142,6 @@ _dir_pht_size_address_share , _ras_size_queue , - _upt_size_queue ); + _upt_size_queue , + _ufpt_size_queue ); _translate_context_id_from_decod_unit= new std::vector [_nb_decod_unit]; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/include/test.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/include/test.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/include/test.h (revision 95) @@ -14,4 +14,5 @@ #include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h" +#include "Common/include/Time.h" using namespace std; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/SelfTest/src/test.cpp (revision 95) @@ -89,4 +89,6 @@ (*(_Victim_Pseudo_LRU->out_ACCESS_VICTIM [i])) (ACCESS_VICTIM [i]); } + + Time * _time = new Time(); /******************************************************** @@ -210,4 +212,5 @@ cout << "<" << name << "> ............ Stop Simulation" << endl; + delete _time; #endif Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp (revision 95) @@ -36,6 +36,6 @@ ); - in_CLOCK = interface->set_signal_clk ("clock" ,1); - in_NRESET = interface->set_signal_in ("nreset",1); + in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); + in_NRESET = interface->set_signal_in ("nreset",1, RESET_VHDL_YES); } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_body.cpp (revision 95) @@ -116,45 +116,45 @@ } - vhdl->set_body (""); - vhdl->set_body ("-- port update"); - for (uint32_t i=0; i<_param->_nb_update; i++) - for (int32_t j=static_cast(log2(_param->_nb_entity)-1); j>=0; j--) - { - uint32_t cpt=0; +// vhdl->set_body (""); +// vhdl->set_body ("-- port update"); +// for (uint32_t i=0; i<_param->_nb_update; i++) +// for (int32_t j=static_cast(log2(_param->_nb_entity)-1); j>=0; j--) +// { +// uint32_t cpt=0; - for (int32_t k=(1<(_param->_nb_entity-1); k+=(1<<(j+1))) - { - bool have_cond = false; - std::string cond = ""; - - // condition to change the bit - for (uint32_t l=j+1; l(log2(_param->_nb_entity));l++) - { - have_cond = true; - - if (l==static_cast(j+1)) - cond += "when"; - else - cond += " and"; - cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; - } - - vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); - vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); - if (have_cond == true) - { - std::string update_address; - - if (_param->_size_table>1) - update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; - else - update_address = "0"; +// for (int32_t k=(1<(_param->_nb_entity-1); k+=(1<<(j+1))) +// { +// bool have_cond = false; +// std::string cond = ""; + +// // condition to change the bit +// for (uint32_t l=j+1; l(log2(_param->_nb_entity));l++) +// { +// have_cond = true; + +// if (l==static_cast(j+1)) +// cond += "when"; +// else +// cond += " and"; +// cond += " in_UPDATE_"+toString(i)+"_ENTITY("+toString(l)+")='"+toString((cpt>>(l-(j+1)))&1)+"'"; +// } + +// vhdl->set_body ("update_next_entry_"+toString(i)+"("+toString(k)+") <="); +// vhdl->set_body ("\tnot in_UPDATE_"+toString(i)+"_ENTITY("+toString(j)+") "+cond); +// if (have_cond == true) +// { +// std::string update_address; + +// if (_param->_size_table>1) +// update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; +// else +// update_address = "0"; - vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); - } - vhdl->set_body ("\t;"); - cpt ++; - } - } +// vhdl->set_body ("\telse reg_TABLE ("+update_address+")("+toString(k)+")"); +// } +// vhdl->set_body ("\t;"); +// cpt ++; +// } +// } vhdl->set_body (""); @@ -182,18 +182,18 @@ } - vhdl->set_body ("\t\t-- Update port"); - for (uint32_t i=0; i<_param->_nb_update; i++) - { - std::string update_address; - - if (_param->_size_table>1) - update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; - else - update_address = "0"; +// vhdl->set_body ("\t\t-- Update port"); +// for (uint32_t i=0; i<_param->_nb_update; i++) +// { +// std::string update_address; + +// if (_param->_size_table>1) +// update_address = "conv_integer(in_UPDATE_"+toString(i)+"_ADDRESS)"; +// else +// update_address = "0"; - vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); - vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); - vhdl->set_body ("\t\tend if;"); - } +// vhdl->set_body ("\t\tif (in_UPDATE_"+toString(i)+"_VAL = '1') then"); +// vhdl->set_body ("\t\t\treg_TABLE ("+update_address+") <= update_next_entry_"+toString(i)+";"); +// vhdl->set_body ("\t\tend if;"); +// } vhdl->set_body ("\tend if;"); @@ -210,11 +210,11 @@ { vhdl->set_body ("out_ACCESS_"+toString(i)+"_ACK <= '1';"); - vhdl->set_body ("out_ACCESS_"+toString(i)+"_ENTITY <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); + vhdl->set_body ("out_ACCESS_"+toString(i)+"_VICTIM <= access_entity_"+toString(i)+" when in_ACCESS_"+toString(i)+"_VAL = '1' else (others => '0');"); } vhdl->set_body (""); - for (uint32_t i=0; i<_param->_nb_update; i++) - { - vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); - } +// for (uint32_t i=0; i<_param->_nb_update; i++) +// { +// vhdl->set_body ("out_UPDATE_"+toString(i)+"_ACK <= '1';"); +// } }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_vhdl_declaration.cpp (revision 95) @@ -29,8 +29,8 @@ } - for (uint32_t i=0; i<_param->_nb_update; i++) - { - vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param->_nb_entity-1)); - } +// for (uint32_t i=0; i<_param->_nb_update; i++) +// { +// vhdl->set_signal ("update_next_entry_"+toString(i)+"",std_logic(_param->_nb_entity-1)); +// } }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 95) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "94" +#define MORPHEO_REVISION "95" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "15" +#define MORPHEO_DATE_DAY "16" #define MORPHEO_DATE_MONTH "12" #define MORPHEO_DATE_YEAR "2008" Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 95) @@ -26,4 +26,5 @@ std::string std_logic_conv (uint32_t size, std::string value); std::string std_logic_conv (uint32_t size, uint32_t value); + std::string std_logic_cst (uint32_t size, uint32_t value); std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min , bool force=false); std::string std_logic_range ( uint32_t max , uint32_t min , bool force=false); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_vhdl_instance.cpp (revision 95) @@ -27,10 +27,7 @@ std::list * list_interface = (_entity)->get_interfaces_list()->get_interface_list(); std::list::iterator j = list_interface->begin(); + bool print_comment = false; if (not list_interface->empty()) { - vhdl->set_body ("------------------------------------------------------"); - vhdl->set_body ("-- Output's Buffer"); - vhdl->set_body ("------------------------------------------------------"); - while (j != list_interface->end()) { @@ -48,4 +45,13 @@ (signal->get_connect_from_signal () != NULL) ) { + if (not print_comment) + { + vhdl->set_body ("------------------------------------------------------"); + vhdl->set_body ("-- Output's Buffer"); + vhdl->set_body ("------------------------------------------------------"); + + print_comment = true; + } + // Create name std::string signal_name = "signal_"+toString(cpt++); @@ -67,7 +73,11 @@ ++j; } - vhdl->set_body (""); - vhdl->set_body ("------------------------------------------------------"); - vhdl->set_body (""); + + if (print_comment) + { + vhdl->set_body (""); + vhdl->set_body ("------------------------------------------------------"); + vhdl->set_body (""); + } } } Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test.cpp (revision 95) @@ -24,5 +24,5 @@ std::string test_name = testbench_test_name(vhdl); - std::string test_name_ok = testbench_test_ok (vhdl); + std::string test_name_ok = testbench_test_ok (vhdl); vhdl->set_body(test_name + " <= '1' when ("+reset_name+" = '0') else "+test_name_ok+";"); Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_ok.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_ok.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interface_testbench_test_ok.cpp (revision 95) @@ -24,5 +24,5 @@ if (_list_signal->empty()== false) { - std::list::iterator i = _list_signal->begin(); + std::list::iterator i = _list_signal->begin(); while (i != _list_signal->end()) Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_test_ok.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_test_ok.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal_testbench_test_ok.cpp (revision 95) @@ -19,5 +19,5 @@ if (_direction == OUT) vhdl->set_body ("\tand "+_name+" = "+_name+"_test"); - + log_printf(FUNC,Behavioural,"testbench_test_ok","End"); }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_constant.cpp (revision 95) @@ -27,5 +27,5 @@ void Vhdl::set_constant (std::string name , - uint32_t size , + uint32_t size , std::string init) { @@ -35,10 +35,10 @@ }; - void Vhdl::set_constant (std::string name , + void Vhdl::set_constant (std::string name , uint32_t size , uint32_t init) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - set_constant(name,std_logic(size),std_logic_conv(size,init)); + set_constant(name,std_logic(size),std_logic_cst(size,init)); log_printf(FUNC,Behavioural,FUNCTION,"End"); }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_signal.cpp (revision 95) @@ -9,5 +9,5 @@ #include "Behavioural/include/Vhdl.h" - +#include "Common/include/ToBase2.h" #include @@ -56,5 +56,5 @@ { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - set_signal(name,std_logic(size),std_logic_conv(size,init)); + set_signal(name,std_logic(size),std_logic_cst(size,init)); log_printf(FUNC,Behavioural,FUNCTION,"End"); }; Index: /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 95) @@ -10,4 +10,5 @@ #include #include "Behavioural/include/Vhdl.h" +#include "Common/include/ToBase2.h" namespace morpheo { @@ -57,4 +58,22 @@ return _return; + }; + +#undef FUNCTION +#define FUNCTION "Vhdl::std_logic_cst" + std::string std_logic_cst (uint32_t size, uint32_t value) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + + std::string conv; + + if (size == 1) + conv = "'"+toString(value&1)+"'"; + else + conv = "\""+toBase2(value,size)+"\""; + + log_printf(FUNC,Behavioural,FUNCTION,"End"); + + return conv; }; Index: /trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Documentation/doc/document-morpheo-vhdl_generation/tex/document-morpheo-vhdl_generation-fr.tex (revision 95) @@ -6,5 +6,5 @@ Ce document est une aide pour les développeur des générateurs de modèles VHDL de \cpu. -Il est décomposé en 5 sections : +Il est décomposé en 6 sections : \begin{itemize} \item Dans la section \ref{tree}, nous présentons l'arborescence des répertoires. @@ -13,4 +13,5 @@ \item Dans la section \ref{vhdl_structural}, nous expliquerons la manière de créer des sous composants. \item Dans la section \ref{example}, nous montrerons quelques exemples. +\item Dans la section \ref{testbench}, nous présenterons la méthodologie de test. \end{itemize} @@ -363,2 +364,26 @@ \end{verbatim} + +\Section {Test du VHDL}\label{testbench} + +Lors d'une simulation systemC, \cpu va générer des fichiers de tests pour le modèle VHDL de chaque composant interne. +Ces tests sont tous écrit de la même façon. Soit l'interface X et le signal Y : +\begin{itemize} +\item Une variable {\it counter} indique le numéro de cycle courant. Elle est initialisé à 0. Elle est incrémenté à chaque cycle. +\item Le composant est instancé avec des signaux internes de même nom. +\item Pour chaque cycle, on affecte à chaque entrée la valeur obtenu lors de la simulation systemC. +\item Pour chaque sortie, on définit un signal dont le nom est {\it out\_X\_Y\_test}. Ces signaux sont affecté au valeur obtenu des sorties lors la simulation systemC. +\item Le signal {\it interface\_X\_test\_ok} est égal à 1 si chaque sortie calculé par la simulation VHDL est égal au sortie attendu (calculé par la simulation systemC). +\item Le signal {\it interface\_X\_test\_transaction} est à 1 si tous les signaux de validité et d'aquittement sont à 1. +\item Le signal {\it interface\_X\_test\_tmp} est à 1 si la simulation systemC indique qu'il y a une transaction et que la simulation vhdl indique également une transaction et que toute les sortie sont bien les sorties obtenu. Si la simulation systemC n'indique pas de transaction, on vérifie que c'est également le cas pour la simulation VHDL. +\item Le signal {\it interface\_X\_test} est égal au signal {\it interface\_X\_test\_tmp} quand il n'y a pas de reset. sinon il est positionné à 1. +\item Le signal {\it test} est un et logique entre tout tous les signaux {\it interface\_X\_test}. +\item La simulation VHDL ce termine si le signal {\it test} vaut 0 (dans ce cas, le test est un échec), ou que le registre {\it counter} vaut le nombre de cycle requis par la simulation systemC (dans ce cas, le test est un succès). +\end{itemize} + +Nous pouvons remarquer que : +\begin{itemize} +\item Nous vérifions la compatibilité au cycle des transactions entre le modèle systemC et le modèle VHDL. +\item Nous vérifions la compatibilité au bit près des données échangé lors qu'il y a une transaction sur une interface. +\item Nous ne vérifions pas la compatibilité au bit près des données présente sur une interface qui ne fait pas de transaction lors d'un cycle. +\end{itemize} Index: /trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Instance_min.cfg (revision 95) @@ -7,5 +7,6 @@ - + + Index: /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_1.cfg (revision 95) @@ -8,4 +8,5 @@ + Index: /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Instance_scalar_2.cfg (revision 95) @@ -8,4 +8,5 @@ + Index: /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 94) +++ /trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 95) @@ -23,3 +23,5 @@ + +