Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction
- Timestamp:
- Dec 19, 2008, 4:34:00 PM (16 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
r88 r97 255 255 inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; 256 256 inst->_has_immediat = 0; 257 // inst->_immediat = ; 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 // inst->_num_reg_rc = ; 257 inst->_immediat = 0; // unnecessary 258 inst->_read_ra = 1; 259 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 260 inst->_read_rb = 1; 261 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 262 inst->_read_rc = 0; 263 inst->_num_reg_rc = 0; //unnecessary 264 264 inst->_write_rd = 1; 265 265 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 271 271 // inst->_branch_stack_write = ; 272 272 // inst->_branch_direction = ; 273 // inst->_address_next = ; 273 // inst->_address_next = ; // already define : PC+4 274 274 inst->_no_execute = 0; 275 275 inst->_event_type = EVENT_TYPE_NONE; … … 283 283 inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; 284 284 inst->_has_immediat = 0; 285 // inst->_immediat = ; 285 inst->_immediat = 0; // unnecessary 286 286 inst->_read_ra = 1; 287 287 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 299 299 // inst->_branch_stack_write = ; 300 300 // inst->_branch_direction = ; 301 // inst->_address_next = ; 301 // inst->_address_next = ; // already define : PC+4 302 302 inst->_no_execute = 0; 303 303 inst->_event_type = EVENT_TYPE_NONE; … … 315 315 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 316 316 inst->_read_rb = 0; 317 // inst->_num_reg_rb = ; 318 inst->_read_rc = 0; 319 // inst->_num_reg_rc = ; 317 inst->_num_reg_rb = 0; //unnecessary 318 inst->_read_rc = 0; 319 inst->_num_reg_rc = 0; //unnecessary 320 320 inst->_write_rd = 1; 321 321 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 327 327 // inst->_branch_stack_write = ; 328 328 // inst->_branch_direction = ; 329 // inst->_address_next = ; 329 // inst->_address_next = ; // already define : PC+4 330 330 inst->_no_execute = 0; 331 331 inst->_event_type = EVENT_TYPE_NONE; … … 343 343 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 344 344 inst->_read_rb = 0; 345 // inst->_num_reg_rb = ; 345 inst->_num_reg_rb = 0; //unnecessary 346 346 inst->_read_rc = 1; 347 347 inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; … … 355 355 // inst->_branch_stack_write = ; 356 356 // inst->_branch_direction = ; 357 // inst->_address_next = ; 357 // inst->_address_next = ; // already define : PC+4 358 358 inst->_no_execute = 0; 359 359 inst->_event_type = EVENT_TYPE_NONE; … … 367 367 inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; 368 368 inst->_has_immediat = 0; 369 // inst->_immediat = ; 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 // inst->_num_reg_rc = ; 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 // inst->_num_reg_re = ; 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; 369 inst->_immediat = 0; // unnecessary 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 inst->_num_reg_rc = 0; //unnecessary 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 inst->_num_reg_re = 0; //unnecessary 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; // already define : PC+4 386 386 inst->_no_execute = 0; 387 387 inst->_event_type = EVENT_TYPE_NONE; … … 399 399 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 400 400 inst->_read_rb = 0; 401 // inst->_num_reg_rb = ; 402 inst->_read_rc = 0; 403 // inst->_num_reg_rc = ; 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 // inst->_num_reg_re = ; 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; 401 inst->_num_reg_rb = 0; //unnecessary 402 inst->_read_rc = 0; 403 inst->_num_reg_rc = 0; //unnecessary 404 inst->_write_rd = 1; 405 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 406 inst->_write_re = 0; 407 inst->_num_reg_re = 0; //unnecessary 408 inst->_exception_use = EXCEPTION_USE_NONE; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; // already define : PC+4 414 414 inst->_no_execute = 0; 415 415 inst->_event_type = EVENT_TYPE_NONE; … … 428 428 inst->_immediat = address_next; 429 429 inst->_read_ra = 0; 430 // inst->_num_reg_ra = ; 431 inst->_read_rb = 0; 432 // inst->_num_reg_rb = ; 430 inst->_num_reg_ra = 0; //unnecessary 431 inst->_read_rb = 0; 432 inst->_num_reg_rb = 0; //unnecessary 433 433 inst->_read_rc = 1; 434 434 inst->_num_reg_rc = SPR_LOGIC_SR_F; 435 435 inst->_write_rd = 0; 436 // inst->_num_reg_rd = ; 437 inst->_write_re = 0; 438 // inst->_num_reg_re = ; 436 inst->_num_reg_rd = 0; //unnecessary 437 inst->_write_re = 0; 438 inst->_num_reg_re = 0; //unnecessary 439 439 inst->_exception_use = EXCEPTION_USE_NONE; 440 440 inst->_exception = EXCEPTION_DECOD_NONE; … … 460 460 inst->_immediat = address_next; 461 461 inst->_read_ra = 0; 462 // inst->_num_reg_ra = ; 463 inst->_read_rb = 0; 464 // inst->_num_reg_rb = ; 462 inst->_num_reg_ra = 0; //unnecessary 463 inst->_read_rb = 0; 464 inst->_num_reg_rb = 0; //unnecessary 465 465 inst->_read_rc = 1; 466 466 inst->_num_reg_rc = SPR_LOGIC_SR_F; … … 468 468 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 469 469 inst->_write_re = 0; 470 // inst->_num_reg_re = ; 470 inst->_num_reg_re = 0; //unnecessary 471 471 inst->_exception_use = EXCEPTION_USE_NONE; 472 472 inst->_exception = EXCEPTION_DECOD_NONE; … … 486 486 inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; 487 487 inst->_has_immediat = 0; 488 // inst->_immediat = ; 488 inst->_immediat = 0; // unnecessary 489 489 inst->_read_ra = 1; 490 490 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); … … 496 496 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 497 497 inst->_write_re = 0; 498 // inst->_num_reg_re = ; 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; 498 inst->_num_reg_re = 0; //unnecessary 499 inst->_exception_use = EXCEPTION_USE_NONE; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; // already define : PC+4 505 505 inst->_no_execute = 0; 506 506 inst->_event_type = EVENT_TYPE_NONE; … … 520 520 inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; 521 521 inst->_has_immediat = 0; 522 // inst->_immediat = ; 522 inst->_immediat = 0; // unnecessary 523 523 inst->_read_ra = 0; 524 // inst->_num_reg_ra = ; 525 inst->_read_rb = 0; 526 // inst->_num_reg_rb = ; 527 inst->_read_rc = 0; 528 // inst->_num_reg_rc = ; 529 inst->_write_rd = 0; 530 // inst->_num_reg_rd = ; 531 inst->_write_re = 0; 532 // inst->_num_reg_re = ; 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // don't change524 inst->_num_reg_ra = 0; //unnecessary 525 inst->_read_rb = 0; 526 inst->_num_reg_rb = 0; //unnecessary 527 inst->_read_rc = 0; 528 inst->_num_reg_rc = 0; //unnecessary 529 inst->_write_rd = 0; 530 inst->_num_reg_rd = 0; //unnecessary 531 inst->_write_re = 0; 532 inst->_num_reg_re = 0; //unnecessary 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 535 // inst->_branch_condition = ; 536 // inst->_branch_stack_write = ; 537 // inst->_branch_direction = ; 538 // inst->_address_next = ; // already define : PC+4 // don't change 539 539 inst->_no_execute = 0; 540 540 inst->_event_type = EVENT_TYPE_CSYNC; … … 558 558 inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; 559 559 inst->_has_immediat = 0; 560 // inst->_immediat = ; 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 // inst->_num_reg_rc = ; 560 inst->_immediat = 0; // unnecessary 561 inst->_read_ra = 1; 562 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 563 inst->_read_rb = 1; 564 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 565 inst->_read_rc = 0; 566 inst->_num_reg_rc = 0; //unnecessary 567 567 inst->_write_rd = 1; 568 568 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 574 574 // inst->_branch_stack_write = ; 575 575 // inst->_branch_direction = ; 576 // inst->_address_next = ; 576 // inst->_address_next = ; // already define : PC+4 577 577 inst->_no_execute = 0; 578 578 inst->_event_type = EVENT_TYPE_NONE; … … 586 586 inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; 587 587 inst->_has_immediat = 0; 588 // inst->_immediat = ; 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 // inst->_num_reg_rc = ; 588 inst->_immediat = 0; // unnecessary 589 inst->_read_ra = 1; 590 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 591 inst->_read_rb = 1; 592 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 593 inst->_read_rc = 0; 594 inst->_num_reg_rc = 0; //unnecessary 595 595 inst->_write_rd = 1; 596 596 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 602 602 // inst->_branch_stack_write = ; 603 603 // inst->_branch_direction = ; 604 // inst->_address_next = ; 604 // inst->_address_next = ; // already define : PC+4 605 605 inst->_no_execute = 0; 606 606 inst->_event_type = EVENT_TYPE_NONE; … … 618 618 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 619 619 inst->_read_rb = 0; 620 // inst->_num_reg_rb = ; 621 inst->_read_rc = 0; 622 // inst->_num_reg_rc = ; 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 // inst->_num_reg_re = ; 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; 620 inst->_num_reg_rb = 0; //unnecessary 621 inst->_read_rc = 0; 622 inst->_num_reg_rc = 0; //unnecessary 623 inst->_write_rd = 1; 624 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 625 inst->_write_re = 0; 626 inst->_num_reg_re = 0; //unnecessary 627 inst->_exception_use = EXCEPTION_USE_NONE; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; // already define : PC+4 633 633 inst->_no_execute = 0; 634 634 inst->_event_type = EVENT_TYPE_NONE; … … 646 646 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 647 647 inst->_read_rb = 0; 648 // inst->_num_reg_rb = ; 649 inst->_read_rc = 0; 650 // inst->_num_reg_rc = ; 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 // inst->_num_reg_re = ; 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; 648 inst->_num_reg_rb = 0; //unnecessary 649 inst->_read_rc = 0; 650 inst->_num_reg_rc = 0; //unnecessary 651 inst->_write_rd = 1; 652 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 653 inst->_write_re = 0; 654 inst->_num_reg_re = 0; //unnecessary 655 inst->_exception_use = EXCEPTION_USE_NONE; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; // already define : PC+4 661 661 inst->_no_execute = 0; 662 662 inst->_event_type = EVENT_TYPE_NONE; … … 674 674 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 675 675 inst->_read_rb = 0; 676 // inst->_num_reg_rb = ; 677 inst->_read_rc = 0; 678 // inst->_num_reg_rc = ; 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 // inst->_num_reg_re = ; 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; 676 inst->_num_reg_rb = 0; //unnecessary 677 inst->_read_rc = 0; 678 inst->_num_reg_rc = 0; //unnecessary 679 inst->_write_rd = 1; 680 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 681 inst->_write_re = 0; 682 inst->_num_reg_re = 0; //unnecessary 683 inst->_exception_use = EXCEPTION_USE_NONE; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; // already define : PC+4 689 689 inst->_no_execute = 0; 690 690 inst->_event_type = EVENT_TYPE_NONE; … … 702 702 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 703 703 inst->_read_rb = 0; 704 // inst->_num_reg_rb = ; 705 inst->_read_rc = 0; 706 // inst->_num_reg_rc = ; 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 // inst->_num_reg_re = ; 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; 704 inst->_num_reg_rb = 0; //unnecessary 705 inst->_read_rc = 0; 706 inst->_num_reg_rc = 0; //unnecessary 707 inst->_write_rd = 1; 708 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 709 inst->_write_re = 0; 710 inst->_num_reg_re = 0; //unnecessary 711 inst->_exception_use = EXCEPTION_USE_NONE; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; // already define : PC+4 717 717 inst->_no_execute = 0; 718 718 inst->_event_type = EVENT_TYPE_NONE; … … 730 730 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 731 731 inst->_read_rb = 0; 732 // inst->_num_reg_rb = ; 733 inst->_read_rc = 0; 734 // inst->_num_reg_rc = ; 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 // inst->_num_reg_re = ; 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; 732 inst->_num_reg_rb = 0; //unnecessary 733 inst->_read_rc = 0; 734 inst->_num_reg_rc = 0; //unnecessary 735 inst->_write_rd = 1; 736 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 737 inst->_write_re = 0; 738 inst->_num_reg_re = 0; //unnecessary 739 inst->_exception_use = EXCEPTION_USE_NONE; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; // already define : PC+4 745 745 inst->_no_execute = 0; 746 746 inst->_event_type = EVENT_TYPE_NONE; … … 758 758 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 759 759 inst->_read_rb = 0; 760 // inst->_num_reg_rb = ; 761 inst->_read_rc = 0; 762 // inst->_num_reg_rc = ; 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 // inst->_num_reg_re = ; 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; 760 inst->_num_reg_rb = 0; //unnecessary 761 inst->_read_rc = 0; 762 inst->_num_reg_rc = 0; //unnecessary 763 inst->_write_rd = 1; 764 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 765 inst->_write_re = 0; 766 inst->_num_reg_re = 0; //unnecessary 767 inst->_exception_use = EXCEPTION_USE_NONE; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; // already define : PC+4 773 773 inst->_no_execute = 0; 774 774 inst->_event_type = EVENT_TYPE_NONE; … … 782 782 inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; 783 783 inst->_has_immediat = 0; 784 // inst->_immediat = ; 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 // inst->_num_reg_rb = ; 789 inst->_read_rc = 0; 790 // inst->_num_reg_rc = ; 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 // inst->_num_reg_re = ; 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; 784 inst->_immediat = 0; // unnecessary 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 inst->_num_reg_rb = 0; //unnecessary 789 inst->_read_rc = 0; 790 inst->_num_reg_rc = 0; //unnecessary 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 inst->_num_reg_re = 0; //unnecessary 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; // already define : PC+4 801 801 inst->_no_execute = 0; 802 802 inst->_event_type = EVENT_TYPE_NONE; … … 810 810 inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; 811 811 inst->_has_immediat = 0; 812 // inst->_immediat = ; 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 // inst->_num_reg_rb = ; 817 inst->_read_rc = 0; 818 // inst->_num_reg_rc = ; 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 // inst->_num_reg_re = ; 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; 812 inst->_immediat = 0; // unnecessary 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 inst->_num_reg_rb = 0; //unnecessary 817 inst->_read_rc = 0; 818 inst->_num_reg_rc = 0; //unnecessary 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 inst->_num_reg_re = 0; //unnecessary 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; // already define : PC+4 829 829 inst->_no_execute = 0; 830 830 inst->_event_type = EVENT_TYPE_NONE; … … 838 838 inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; 839 839 inst->_has_immediat = 0; 840 // inst->_immediat = ; 840 inst->_immediat = 0; // unnecessary 841 841 inst->_read_ra = 0; 842 // inst->_num_reg_ra = ; 843 inst->_read_rb = 0; 844 // inst->_num_reg_rb = ; 845 inst->_read_rc = 0; 846 // inst->_num_reg_rc = ; 847 inst->_write_rd = 0; 848 // inst->_num_reg_rd = ; 849 inst->_write_re = 0; 850 // inst->_num_reg_re = ; 842 inst->_num_reg_ra = 0; //unnecessary 843 inst->_read_rb = 0; 844 inst->_num_reg_rb = 0; //unnecessary 845 inst->_read_rc = 0; 846 inst->_num_reg_rc = 0; //unnecessary 847 inst->_write_rd = 0; 848 inst->_num_reg_rd = 0; //unnecessary 849 inst->_write_re = 0; 850 inst->_num_reg_re = 0; //unnecessary 851 851 inst->_exception_use = EXCEPTION_USE_NONE; 852 852 inst->_exception = EXCEPTION_DECOD_NONE; … … 869 869 inst->_immediat = inst->_address_next+1; 870 870 inst->_read_ra = 0; 871 // inst->_num_reg_ra = ; 872 inst->_read_rb = 0; 873 // inst->_num_reg_rb = ; 874 inst->_read_rc = 0; 875 // inst->_num_reg_rc = ; 871 inst->_num_reg_ra = 0; //unnecessary 872 inst->_read_rb = 0; 873 inst->_num_reg_rb = 0; //unnecessary 874 inst->_read_rc = 0; 875 inst->_num_reg_rc = 0; //unnecessary 876 876 inst->_write_rd = 1; 877 877 inst->_num_reg_rd = 9; // Link register 878 878 inst->_write_re = 0; 879 // inst->_num_reg_re = ; 879 inst->_num_reg_re = 0; //unnecessary 880 880 inst->_exception_use = EXCEPTION_USE_NONE; 881 881 inst->_exception = EXCEPTION_DECOD_NONE; … … 904 904 inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; 905 905 inst->_has_immediat = 0; 906 // inst->_immediat = ; 906 inst->_immediat = 0; // unnecessary 907 907 inst->_read_ra = 0; 908 // inst->_num_reg_ra = ; 908 inst->_num_reg_ra = 0; //unnecessary 909 909 inst->_read_rb = 1; 910 910 // inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 911 911 inst->_read_rc = 0; 912 // inst->_num_reg_rc = ; 912 inst->_num_reg_rc = 0; //unnecessary 913 913 inst->_write_rd = 1; 914 914 inst->_num_reg_rd = 9; // Link register 915 915 inst->_write_re = 0; 916 // inst->_num_reg_re = ; 916 inst->_num_reg_re = 0; //unnecessary 917 917 inst->_exception_use = EXCEPTION_USE_NONE; 918 918 inst->_exception = EXCEPTION_DECOD_NONE; … … 921 921 // inst->_branch_stack_write = 1; 922 922 inst->_branch_direction = 1; 923 // inst->_address_next = ; 923 // inst->_address_next = ; // already define : PC+4 924 924 inst->_no_execute = 0; 925 925 inst->_event_type = EVENT_TYPE_NONE; … … 934 934 inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; 935 935 inst->_has_immediat = 0; 936 // inst->_immediat = ; 936 inst->_immediat = 0; // unnecessary 937 937 inst->_read_ra = 0; 938 // inst->_num_reg_ra = ; 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 // inst->_num_reg_rc = ; 943 inst->_write_rd = 0; 944 // inst->_num_reg_rd = ; 945 inst->_write_re = 0; 946 // inst->_num_reg_re = ; 938 inst->_num_reg_ra = 0; //unnecessary 939 inst->_read_rb = 1; 940 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 941 inst->_read_rc = 0; 942 inst->_num_reg_rc = 0; //unnecessary 943 inst->_write_rd = 0; 944 inst->_num_reg_rd = 0; //unnecessary 945 inst->_write_re = 0; 946 inst->_num_reg_re = 0; //unnecessary 947 947 inst->_exception_use = EXCEPTION_USE_NONE; 948 948 inst->_exception = EXCEPTION_DECOD_NONE; … … 950 950 // inst->_branch_stack_write = 0; 951 951 inst->_branch_direction = 1; 952 // inst->_address_next = ; 952 // inst->_address_next = ; // already define : PC+4 953 953 inst->_no_execute = 0; 954 954 inst->_event_type = EVENT_TYPE_NONE; … … 966 966 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 967 967 inst->_read_rb = 0; 968 // inst->_num_reg_rb = ; 969 inst->_read_rc = 0; 970 // inst->_num_reg_rc = ; 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 // inst->_num_reg_re = ; 968 inst->_num_reg_rb = 0; //unnecessary 969 inst->_read_rc = 0; 970 inst->_num_reg_rc = 0; //unnecessary 971 inst->_write_rd = 1; 972 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 973 inst->_write_re = 0; 974 inst->_num_reg_re = 0; //unnecessary 975 975 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 976 976 inst->_exception = EXCEPTION_DECOD_NONE; … … 978 978 // inst->_branch_stack_write = ; 979 979 // inst->_branch_direction = ; 980 // inst->_address_next = ; 980 // inst->_address_next = ; // already define : PC+4 981 981 inst->_no_execute = 0; 982 982 inst->_event_type = EVENT_TYPE_NONE; … … 994 994 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 995 995 inst->_read_rb = 0; 996 // inst->_num_reg_rb = ; 997 inst->_read_rc = 0; 998 // inst->_num_reg_rc = ; 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 // inst->_num_reg_re = ; 996 inst->_num_reg_rb = 0; //unnecessary 997 inst->_read_rc = 0; 998 inst->_num_reg_rc = 0; //unnecessary 999 inst->_write_rd = 1; 1000 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1001 inst->_write_re = 0; 1002 inst->_num_reg_re = 0; //unnecessary 1003 1003 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1004 1004 inst->_exception = EXCEPTION_DECOD_NONE; … … 1006 1006 // inst->_branch_stack_write = ; 1007 1007 // inst->_branch_direction = ; 1008 // inst->_address_next = ; 1008 // inst->_address_next = ; // already define : PC+4 1009 1009 inst->_no_execute = 0; 1010 1010 inst->_event_type = EVENT_TYPE_NONE; … … 1022 1022 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1023 1023 inst->_read_rb = 0; 1024 // inst->_num_reg_rb = ; 1025 inst->_read_rc = 0; 1026 // inst->_num_reg_rc = ; 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 // inst->_num_reg_re = ; 1024 inst->_num_reg_rb = 0; //unnecessary 1025 inst->_read_rc = 0; 1026 inst->_num_reg_rc = 0; //unnecessary 1027 inst->_write_rd = 1; 1028 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1029 inst->_write_re = 0; 1030 inst->_num_reg_re = 0; //unnecessary 1031 1031 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1032 1032 inst->_exception = EXCEPTION_DECOD_NONE; … … 1034 1034 // inst->_branch_stack_write = ; 1035 1035 // inst->_branch_direction = ; 1036 // inst->_address_next = ; 1036 // inst->_address_next = ; // already define : PC+4 1037 1037 inst->_no_execute = 0; 1038 1038 inst->_event_type = EVENT_TYPE_NONE; … … 1050 1050 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1051 1051 inst->_read_rb = 0; 1052 // inst->_num_reg_rb = ; 1053 inst->_read_rc = 0; 1054 // inst->_num_reg_rc = ; 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 // inst->_num_reg_re = ; 1052 inst->_num_reg_rb = 0; //unnecessary 1053 inst->_read_rc = 0; 1054 inst->_num_reg_rc = 0; //unnecessary 1055 inst->_write_rd = 1; 1056 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1057 inst->_write_re = 0; 1058 inst->_num_reg_re = 0; //unnecessary 1059 1059 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1060 1060 inst->_exception = EXCEPTION_DECOD_NONE; … … 1062 1062 // inst->_branch_stack_write = ; 1063 1063 // inst->_branch_direction = ; 1064 // inst->_address_next = ; 1064 // inst->_address_next = ; // already define : PC+4 1065 1065 inst->_no_execute = 0; 1066 1066 inst->_event_type = EVENT_TYPE_NONE; … … 1078 1078 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1079 1079 inst->_read_rb = 0; 1080 // inst->_num_reg_rb = ; 1081 inst->_read_rc = 0; 1082 // inst->_num_reg_rc = ; 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 // inst->_num_reg_re = ; 1080 inst->_num_reg_rb = 0; //unnecessary 1081 inst->_read_rc = 0; 1082 inst->_num_reg_rc = 0; //unnecessary 1083 inst->_write_rd = 1; 1084 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1085 inst->_write_re = 0; 1086 inst->_num_reg_re = 0; //unnecessary 1087 1087 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1088 1088 inst->_exception = EXCEPTION_DECOD_NONE; … … 1090 1090 // inst->_branch_stack_write = ; 1091 1091 // inst->_branch_direction = ; 1092 // inst->_address_next = ; 1092 // inst->_address_next = ; // already define : PC+4 1093 1093 inst->_no_execute = 0; 1094 1094 inst->_event_type = EVENT_TYPE_NONE; … … 1106 1106 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1107 1107 inst->_read_rb = 0; 1108 // inst->_num_reg_rb = ; 1109 inst->_read_rc = 0; 1110 // inst->_num_reg_rc = ; 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 // inst->_num_reg_re = ; 1108 inst->_num_reg_rb = 0; //unnecessary 1109 inst->_read_rc = 0; 1110 inst->_num_reg_rc = 0; //unnecessary 1111 inst->_write_rd = 1; 1112 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1113 inst->_write_re = 0; 1114 inst->_num_reg_re = 0; //unnecessary 1115 1115 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1116 1116 inst->_exception = EXCEPTION_DECOD_NONE; … … 1118 1118 // inst->_branch_stack_write = ; 1119 1119 // inst->_branch_direction = ; 1120 // inst->_address_next = ; 1120 // inst->_address_next = ; // already define : PC+4 1121 1121 inst->_no_execute = 0; 1122 1122 inst->_event_type = EVENT_TYPE_NONE; … … 1134 1134 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1135 1135 inst->_read_rb = 0; 1136 // inst->_num_reg_rb = ; 1137 inst->_read_rc = 0; 1138 // inst->_num_reg_rc = ; 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 // inst->_num_reg_re = ; 1136 inst->_num_reg_rb = 0; //unnecessary 1137 inst->_read_rc = 0; 1138 inst->_num_reg_rc = 0; //unnecessary 1139 inst->_write_rd = 1; 1140 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1141 inst->_write_re = 0; 1142 inst->_num_reg_re = 0; //unnecessary 1143 1143 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1144 1144 inst->_exception = EXCEPTION_DECOD_NONE; … … 1146 1146 // inst->_branch_stack_write = ; 1147 1147 // inst->_branch_direction = ; 1148 // inst->_address_next = ; 1148 // inst->_address_next = ; // already define : PC+4 1149 1149 inst->_no_execute = 0; 1150 1150 inst->_event_type = EVENT_TYPE_NONE; … … 1158 1158 inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; 1159 1159 inst->_has_immediat = 0; 1160 // inst->_immediat = ; 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 // inst->_num_reg_rc = ; 1167 inst->_write_rd = 0; 1168 // inst->_num_reg_rd = ; 1169 inst->_write_re = 0; 1170 // inst->_num_reg_re = ; 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // don't change1160 inst->_immediat = 0; // unnecessary 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 inst->_num_reg_rc = 0; //unnecessary 1167 inst->_write_rd = 0; 1168 inst->_num_reg_rd = 0; //unnecessary 1169 inst->_write_re = 0; 1170 inst->_num_reg_re = 0; //unnecessary 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1173 // inst->_branch_condition = ; 1174 // inst->_branch_stack_write = ; 1175 // inst->_branch_direction = ; 1176 // inst->_address_next = ; // already define : PC+4 // don't change 1177 1177 inst->_no_execute = 0; 1178 1178 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1191 1191 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1192 1192 inst->_read_rb = 0; 1193 // inst->_num_reg_rb = ; 1194 inst->_read_rc = 0; 1195 // inst->_num_reg_rc = ; 1196 inst->_write_rd = 0; 1197 // inst->_num_reg_rd = ; 1198 inst->_write_re = 0; 1199 // inst->_num_reg_re = ; 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // don't change1193 inst->_num_reg_rb = 0; //unnecessary 1194 inst->_read_rc = 0; 1195 inst->_num_reg_rc = 0; //unnecessary 1196 inst->_write_rd = 0; 1197 inst->_num_reg_rd = 0; //unnecessary 1198 inst->_write_re = 0; 1199 inst->_num_reg_re = 0; //unnecessary 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1202 // inst->_branch_condition = ; 1203 // inst->_branch_stack_write = ; 1204 // inst->_branch_direction = ; 1205 // inst->_address_next = ; // already define : PC+4 // don't change 1206 1206 inst->_no_execute = 0; 1207 1207 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1221 1221 inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; 1222 1222 inst->_has_immediat = 0; 1223 // inst->_immediat = ; 1223 inst->_immediat = 0; // unnecessary 1224 1224 inst->_read_ra = 0; 1225 // inst->_num_reg_ra = ; 1226 inst->_read_rb = 0; 1227 // inst->_num_reg_rb = ; 1228 inst->_read_rc = 0; 1229 // inst->_num_reg_rc = ; 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 // inst->_num_reg_re = ; 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // don't change1225 inst->_num_reg_ra = 0; //unnecessary 1226 inst->_read_rb = 0; 1227 inst->_num_reg_rb = 0; //unnecessary 1228 inst->_read_rc = 0; 1229 inst->_num_reg_rc = 0; //unnecessary 1230 inst->_write_rd = 1; 1231 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1232 inst->_write_re = 0; 1233 inst->_num_reg_re = 0; //unnecessary 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1236 // inst->_branch_condition = ; 1237 // inst->_branch_stack_write = ; 1238 // inst->_branch_direction = ; 1239 // inst->_address_next = ; // already define : PC+4 // don't change 1240 1240 inst->_no_execute = 0; 1241 1241 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1254 1254 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1255 1255 inst->_read_rb = 0; 1256 // inst->_num_reg_rb = ; 1257 inst->_read_rc = 0; 1258 // inst->_num_reg_rc = ; 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 // inst->_num_reg_re = ; 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // don't change1256 inst->_num_reg_rb = 0; //unnecessary 1257 inst->_read_rc = 0; 1258 inst->_num_reg_rc = 0; //unnecessary 1259 inst->_write_rd = 1; 1260 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1261 inst->_write_re = 0; 1262 inst->_num_reg_re = 0; //unnecessary 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1265 // inst->_branch_condition = ; 1266 // inst->_branch_stack_write = ; 1267 // inst->_branch_direction = ; 1268 // inst->_address_next = ; // already define : PC+4 // don't change 1269 1269 inst->_no_execute = 0; 1270 1270 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1280 1280 inst->_immediat = EXTENDZ(inst->_instruction,16); 1281 1281 inst->_read_ra = 0; 1282 // inst->_num_reg_ra = ; 1283 inst->_read_rb = 0; 1284 // inst->_num_reg_rb = ; 1285 inst->_read_rc = 0; 1286 // inst->_num_reg_rc = ; 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 // inst->_num_reg_re = ; 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; 1282 inst->_num_reg_ra = 0; //unnecessary 1283 inst->_read_rb = 0; 1284 inst->_num_reg_rb = 0; //unnecessary 1285 inst->_read_rc = 0; 1286 inst->_num_reg_rc = 0; //unnecessary 1287 inst->_write_rd = 1; 1288 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1289 inst->_write_re = 0; 1290 inst->_num_reg_re = 0; //unnecessary 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; // already define : PC+4 1297 1297 inst->_no_execute = 0; 1298 1298 inst->_event_type = EVENT_TYPE_NONE; … … 1306 1306 inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; 1307 1307 inst->_has_immediat = 0; 1308 // inst->_immediat = ; 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 // inst->_num_reg_rc = ; 1315 inst->_write_rd = 0; 1316 // inst->_num_reg_rd = ; 1317 inst->_write_re = 0; 1318 // inst->_num_reg_re = ; 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // don't change1308 inst->_immediat = 0; // unnecessary 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 inst->_num_reg_rc = 0; //unnecessary 1315 inst->_write_rd = 0; 1316 inst->_num_reg_rd = 0; //unnecessary 1317 inst->_write_re = 0; 1318 inst->_num_reg_re = 0; //unnecessary 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1321 // inst->_branch_condition = ; 1322 // inst->_branch_stack_write = ; 1323 // inst->_branch_direction = ; 1324 // inst->_address_next = ; // already define : PC+4 // don't change 1325 1325 inst->_no_execute = 0; 1326 1326 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1340 1340 inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; 1341 1341 inst->_has_immediat = 0; 1342 // inst->_immediat = ; 1342 inst->_immediat = 0; // unnecessary 1343 1343 inst->_read_ra = 0; 1344 // inst->_num_reg_ra = ; 1345 inst->_read_rb = 0; 1346 // inst->_num_reg_rb = ; 1347 inst->_read_rc = 0; 1348 // inst->_num_reg_rc = ; 1349 inst->_write_rd = 0; 1350 // inst->_num_reg_rd = ; 1351 inst->_write_re = 0; 1352 // inst->_num_reg_re = ; 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // don't change1344 inst->_num_reg_ra = 0; //unnecessary 1345 inst->_read_rb = 0; 1346 inst->_num_reg_rb = 0; //unnecessary 1347 inst->_read_rc = 0; 1348 inst->_num_reg_rc = 0; //unnecessary 1349 inst->_write_rd = 0; 1350 inst->_num_reg_rd = 0; //unnecessary 1351 inst->_write_re = 0; 1352 inst->_num_reg_re = 0; //unnecessary 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1355 // inst->_branch_condition = ; 1356 // inst->_branch_stack_write = ; 1357 // inst->_branch_direction = ; 1358 // inst->_address_next = ; // already define : PC+4 // don't change 1359 1359 inst->_no_execute = 0; 1360 1360 inst->_event_type = EVENT_TYPE_MSYNC; … … 1376 1376 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1377 1377 inst->_read_rc = 0; 1378 // inst->_num_reg_rc = ; 1379 inst->_write_rd = 0; 1380 // inst->_num_reg_rd = ; 1381 inst->_write_re = 0; 1382 // inst->_num_reg_re = ; 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // don't change1378 inst->_num_reg_rc = 0; //unnecessary 1379 inst->_write_rd = 0; 1380 inst->_num_reg_rd = 0; //unnecessary 1381 inst->_write_re = 0; 1382 inst->_num_reg_re = 0; //unnecessary 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1385 // inst->_branch_condition = ; 1386 // inst->_branch_stack_write = ; 1387 // inst->_branch_direction = ; 1388 // inst->_address_next = ; // already define : PC+4 // don't change 1389 1389 inst->_no_execute = 0; 1390 1390 inst->_event_type = EVENT_TYPE_SPR_ACCESS; … … 1398 1398 inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; 1399 1399 inst->_has_immediat = 0; 1400 // inst->_immediat = ; 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 // inst->_num_reg_rc = ; 1400 inst->_immediat = 0; // unnecessary 1401 inst->_read_ra = 1; 1402 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1403 inst->_read_rb = 1; 1404 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1405 inst->_read_rc = 0; 1406 inst->_num_reg_rc = 0; //unnecessary 1407 1407 inst->_write_rd = 1; 1408 1408 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1414 1414 // inst->_branch_stack_write = ; 1415 1415 // inst->_branch_direction = ; 1416 // inst->_address_next = ; 1416 // inst->_address_next = ; // already define : PC+4 1417 1417 inst->_no_execute = 0; 1418 1418 inst->_event_type = EVENT_TYPE_NONE; … … 1430 1430 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1431 1431 inst->_read_rb = 0; 1432 // inst->_num_reg_rb = ; 1433 inst->_read_rc = 0; 1434 // inst->_num_reg_rc = ; 1432 inst->_num_reg_rb = 0; //unnecessary 1433 inst->_read_rc = 0; 1434 inst->_num_reg_rc = 0; //unnecessary 1435 1435 inst->_write_rd = 1; 1436 1436 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1442 1442 // inst->_branch_stack_write = ; 1443 1443 // inst->_branch_direction = ; 1444 // inst->_address_next = ; 1444 // inst->_address_next = ; // already define : PC+4 1445 1445 inst->_no_execute = 0; 1446 1446 inst->_event_type = EVENT_TYPE_NONE; … … 1454 1454 inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; 1455 1455 inst->_has_immediat = 0; 1456 // inst->_immediat = ; 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 // inst->_num_reg_rc = ; 1456 inst->_immediat = 0; // unnecessary 1457 inst->_read_ra = 1; 1458 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1459 inst->_read_rb = 1; 1460 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1461 inst->_read_rc = 0; 1462 inst->_num_reg_rc = 0; //unnecessary 1463 1463 inst->_write_rd = 1; 1464 1464 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 1470 1470 // inst->_branch_stack_write = ; 1471 1471 // inst->_branch_direction = ; 1472 // inst->_address_next = ; 1472 // inst->_address_next = ; // already define : PC+4 1473 1473 inst->_no_execute = 0; 1474 1474 inst->_event_type = EVENT_TYPE_NONE; … … 1484 1484 // inst->_immediat = EXTENDZ(inst->_instruction,16); 1485 1485 inst->_has_immediat = 0; 1486 // inst->_immediat = ; 1486 inst->_immediat = 0; // unnecessary 1487 1487 inst->_read_ra = 0; 1488 // inst->_num_reg_ra = ; 1489 inst->_read_rb = 0; 1490 // inst->_num_reg_rb = ; 1491 inst->_read_rc = 0; 1492 // inst->_num_reg_rc = ; 1493 inst->_write_rd = 0; 1494 // inst->_num_reg_rd = ; 1495 inst->_write_re = 0; 1496 // inst->_num_reg_re = ; 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; 1488 inst->_num_reg_ra = 0; //unnecessary 1489 inst->_read_rb = 0; 1490 inst->_num_reg_rb = 0; //unnecessary 1491 inst->_read_rc = 0; 1492 inst->_num_reg_rc = 0; //unnecessary 1493 inst->_write_rd = 0; 1494 inst->_num_reg_rd = 0; //unnecessary 1495 inst->_write_re = 0; 1496 inst->_num_reg_re = 0; //unnecessary 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; // already define : PC+4 1503 1503 inst->_no_execute = 1; 1504 1504 inst->_event_type = EVENT_TYPE_NONE; … … 1512 1512 inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; 1513 1513 inst->_has_immediat = 0; 1514 // inst->_immediat = ; 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 // inst->_num_reg_rc = ; 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 // inst->_num_reg_re = ; 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; 1514 inst->_immediat = 0; // unnecessary 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 inst->_num_reg_rc = 0; //unnecessary 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 inst->_num_reg_re = 0; //unnecessary 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; // already define : PC+4 1531 1531 inst->_no_execute = 0; 1532 1532 inst->_event_type = EVENT_TYPE_NONE; … … 1544 1544 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1545 1545 inst->_read_rb = 0; 1546 // inst->_num_reg_rb = ; 1547 inst->_read_rc = 0; 1548 // inst->_num_reg_rc = ; 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 // inst->_num_reg_re = ; 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; 1546 inst->_num_reg_rb = 0; //unnecessary 1547 inst->_read_rc = 0; 1548 inst->_num_reg_rc = 0; //unnecessary 1549 inst->_write_rd = 1; 1550 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1551 inst->_write_re = 0; 1552 inst->_num_reg_re = 0; //unnecessary 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; // already define : PC+4 1559 1559 inst->_no_execute = 0; 1560 1560 inst->_event_type = EVENT_TYPE_NONE; … … 1574 1574 inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; 1575 1575 inst->_has_immediat = 0; 1576 // inst->_immediat = ; 1576 inst->_immediat = 0; // unnecessary 1577 1577 inst->_read_ra = 0; 1578 // inst->_num_reg_ra = ; 1579 inst->_read_rb = 0; 1580 // inst->_num_reg_rb = ; 1581 inst->_read_rc = 0; 1582 // inst->_num_reg_rc = ; 1583 inst->_write_rd = 0; 1584 // inst->_num_reg_rd = ; 1585 inst->_write_re = 0; 1586 // inst->_num_reg_re = ; 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // don't change1578 inst->_num_reg_ra = 0; //unnecessary 1579 inst->_read_rb = 0; 1580 inst->_num_reg_rb = 0; //unnecessary 1581 inst->_read_rc = 0; 1582 inst->_num_reg_rc = 0; //unnecessary 1583 inst->_write_rd = 0; 1584 inst->_num_reg_rd = 0; //unnecessary 1585 inst->_write_re = 0; 1586 inst->_num_reg_re = 0; //unnecessary 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1589 // inst->_branch_condition = ; 1590 // inst->_branch_stack_write = ; 1591 // inst->_branch_direction = ; 1592 // inst->_address_next = ; // already define : PC+4 // don't change 1593 1593 inst->_no_execute = 0; 1594 1594 inst->_event_type = EVENT_TYPE_PSYNC; … … 1603 1603 inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; 1604 1604 inst->_has_immediat = 0; 1605 // inst->_immediat = ; 1605 inst->_immediat = 0; // unnecessary 1606 1606 inst->_read_ra = 0; 1607 // inst->_num_reg_ra = ; 1608 inst->_read_rb = 0; 1609 // inst->_num_reg_rb = ; 1610 inst->_read_rc = 0; 1611 // inst->_num_reg_rc = ; 1612 inst->_write_rd = 0; 1613 // inst->_num_reg_rd = ; 1614 inst->_write_re = 0; 1615 // inst->_num_reg_re = ; 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // don't change1607 inst->_num_reg_ra = 0; //unnecessary 1608 inst->_read_rb = 0; 1609 inst->_num_reg_rb = 0; //unnecessary 1610 inst->_read_rc = 0; 1611 inst->_num_reg_rc = 0; //unnecessary 1612 inst->_write_rd = 0; 1613 inst->_num_reg_rd = 0; //unnecessary 1614 inst->_write_re = 0; 1615 inst->_num_reg_re = 0; //unnecessary 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1618 // inst->_branch_condition = ; 1619 // inst->_branch_stack_write = ; 1620 // inst->_branch_direction = ; 1621 // inst->_address_next = ; // already define : PC+4 // don't change 1622 1622 inst->_no_execute = 1; 1623 1623 inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage … … 1631 1631 inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; 1632 1632 inst->_has_immediat = 0; 1633 // inst->_immediat = ; 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 // inst->_num_reg_rc = ; 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 // inst->_num_reg_re = ; 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; 1633 inst->_immediat = 0; // unnecessary 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 inst->_num_reg_rc = 0; //unnecessary 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 inst->_num_reg_re = 0; //unnecessary 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; // already define : PC+4 1650 1650 inst->_no_execute = 0; 1651 1651 inst->_event_type = EVENT_TYPE_NONE; … … 1663 1663 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1664 1664 inst->_read_rb = 0; 1665 // inst->_num_reg_rb = ; 1666 inst->_read_rc = 0; 1667 // inst->_num_reg_rc = ; 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 // inst->_num_reg_re = ; 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; 1665 inst->_num_reg_rb = 0; //unnecessary 1666 inst->_read_rc = 0; 1667 inst->_num_reg_rc = 0; //unnecessary 1668 inst->_write_rd = 1; 1669 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1670 inst->_write_re = 0; 1671 inst->_num_reg_re = 0; //unnecessary 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; // already define : PC+4 1678 1678 inst->_no_execute = 0; 1679 1679 inst->_event_type = EVENT_TYPE_NONE; … … 1694 1694 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1695 1695 inst->_read_rc = 0; 1696 // inst->_num_reg_rc = ; 1697 inst->_write_rd = 0; 1698 // inst->_num_reg_rd = ; 1699 inst->_write_re = 0; 1700 // inst->_num_reg_re = ; 1696 inst->_num_reg_rc = 0; //unnecessary 1697 inst->_write_rd = 0; 1698 inst->_num_reg_rd = 0; //unnecessary 1699 inst->_write_re = 0; 1700 inst->_num_reg_re = 0; //unnecessary 1701 1701 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1702 1702 inst->_exception = EXCEPTION_DECOD_NONE; … … 1704 1704 // inst->_branch_stack_write = ; 1705 1705 // inst->_branch_direction = ; 1706 // inst->_address_next = ; 1706 // inst->_address_next = ; // already define : PC+4 1707 1707 inst->_no_execute = 0; 1708 1708 inst->_event_type = EVENT_TYPE_NONE; … … 1723 1723 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1724 1724 inst->_read_rc = 0; 1725 // inst->_num_reg_rc = ; 1726 inst->_write_rd = 0; 1727 // inst->_num_reg_rd = ; 1728 inst->_write_re = 0; 1729 // inst->_num_reg_re = ; 1725 inst->_num_reg_rc = 0; //unnecessary 1726 inst->_write_rd = 0; 1727 inst->_num_reg_rd = 0; //unnecessary 1728 inst->_write_re = 0; 1729 inst->_num_reg_re = 0; //unnecessary 1730 1730 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1731 1731 inst->_exception = EXCEPTION_DECOD_NONE; … … 1733 1733 // inst->_branch_stack_write = ; 1734 1734 // inst->_branch_direction = ; 1735 // inst->_address_next = ; 1735 // inst->_address_next = ; // already define : PC+4 1736 1736 inst->_no_execute = 0; 1737 1737 inst->_event_type = EVENT_TYPE_NONE; … … 1745 1745 inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; 1746 1746 inst->_has_immediat = 0; 1747 // inst->_immediat = ; 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 // inst->_num_reg_rc = ; 1754 inst->_write_rd = 0; 1755 // inst->_num_reg_rd = ; 1747 inst->_immediat = 0; // unnecessary 1748 inst->_read_ra = 1; 1749 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1750 inst->_read_rb = 1; 1751 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1752 inst->_read_rc = 0; 1753 inst->_num_reg_rc = 0; //unnecessary 1754 inst->_write_rd = 0; 1755 inst->_num_reg_rd = 0; //unnecessary 1756 1756 inst->_write_re = 1; 1757 1757 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1761 1761 // inst->_branch_stack_write = ; 1762 1762 // inst->_branch_direction = ; 1763 // inst->_address_next = ; 1763 // inst->_address_next = ; // already define : PC+4 1764 1764 inst->_no_execute = 0; 1765 1765 inst->_event_type = EVENT_TYPE_NONE; … … 1777 1777 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1778 1778 inst->_read_rb = 0; 1779 // inst->_num_reg_rb = ; 1780 inst->_read_rc = 0; 1781 // inst->_num_reg_rc = ; 1782 inst->_write_rd = 0; 1783 // inst->_num_reg_rd = ; 1779 inst->_num_reg_rb = 0; //unnecessary 1780 inst->_read_rc = 0; 1781 inst->_num_reg_rc = 0; //unnecessary 1782 inst->_write_rd = 0; 1783 inst->_num_reg_rd = 0; //unnecessary 1784 1784 inst->_write_re = 1; 1785 1785 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1789 1789 // inst->_branch_stack_write = ; 1790 1790 // inst->_branch_direction = ; 1791 // inst->_address_next = ; 1791 // inst->_address_next = ; // already define : PC+4 1792 1792 inst->_no_execute = 0; 1793 1793 inst->_event_type = EVENT_TYPE_NONE; … … 1801 1801 inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; 1802 1802 inst->_has_immediat = 0; 1803 // inst->_immediat = ; 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 // inst->_num_reg_rc = ; 1810 inst->_write_rd = 0; 1811 // inst->_num_reg_rd = ; 1803 inst->_immediat = 0; // unnecessary 1804 inst->_read_ra = 1; 1805 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1806 inst->_read_rb = 1; 1807 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1808 inst->_read_rc = 0; 1809 inst->_num_reg_rc = 0; //unnecessary 1810 inst->_write_rd = 0; 1811 inst->_num_reg_rd = 0; //unnecessary 1812 1812 inst->_write_re = 1; 1813 1813 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1817 1817 // inst->_branch_stack_write = ; 1818 1818 // inst->_branch_direction = ; 1819 // inst->_address_next = ; 1819 // inst->_address_next = ; // already define : PC+4 1820 1820 inst->_no_execute = 0; 1821 1821 inst->_event_type = EVENT_TYPE_NONE; … … 1833 1833 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1834 1834 inst->_read_rb = 0; 1835 // inst->_num_reg_rb = ; 1836 inst->_read_rc = 0; 1837 // inst->_num_reg_rc = ; 1838 inst->_write_rd = 0; 1839 // inst->_num_reg_rd = ; 1835 inst->_num_reg_rb = 0; //unnecessary 1836 inst->_read_rc = 0; 1837 inst->_num_reg_rc = 0; //unnecessary 1838 inst->_write_rd = 0; 1839 inst->_num_reg_rd = 0; //unnecessary 1840 1840 inst->_write_re = 1; 1841 1841 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1845 1845 // inst->_branch_stack_write = ; 1846 1846 // inst->_branch_direction = ; 1847 // inst->_address_next = ; 1847 // inst->_address_next = ; // already define : PC+4 1848 1848 inst->_no_execute = 0; 1849 1849 inst->_event_type = EVENT_TYPE_NONE; … … 1857 1857 inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; 1858 1858 inst->_has_immediat = 0; 1859 // inst->_immediat = ; 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 // inst->_num_reg_rc = ; 1866 inst->_write_rd = 0; 1867 // inst->_num_reg_rd = ; 1859 inst->_immediat = 0; // unnecessary 1860 inst->_read_ra = 1; 1861 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1862 inst->_read_rb = 1; 1863 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1864 inst->_read_rc = 0; 1865 inst->_num_reg_rc = 0; //unnecessary 1866 inst->_write_rd = 0; 1867 inst->_num_reg_rd = 0; //unnecessary 1868 1868 inst->_write_re = 1; 1869 1869 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1873 1873 // inst->_branch_stack_write = ; 1874 1874 // inst->_branch_direction = ; 1875 // inst->_address_next = ; 1875 // inst->_address_next = ; // already define : PC+4 1876 1876 inst->_no_execute = 0; 1877 1877 inst->_event_type = EVENT_TYPE_NONE; … … 1889 1889 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1890 1890 inst->_read_rb = 0; 1891 // inst->_num_reg_rb = ; 1892 inst->_read_rc = 0; 1893 // inst->_num_reg_rc = ; 1894 inst->_write_rd = 0; 1895 // inst->_num_reg_rd = ; 1891 inst->_num_reg_rb = 0; //unnecessary 1892 inst->_read_rc = 0; 1893 inst->_num_reg_rc = 0; //unnecessary 1894 inst->_write_rd = 0; 1895 inst->_num_reg_rd = 0; //unnecessary 1896 1896 inst->_write_re = 1; 1897 1897 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1901 1901 // inst->_branch_stack_write = ; 1902 1902 // inst->_branch_direction = ; 1903 // inst->_address_next = ; 1903 // inst->_address_next = ; // already define : PC+4 1904 1904 inst->_no_execute = 0; 1905 1905 inst->_event_type = EVENT_TYPE_NONE; … … 1913 1913 inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; 1914 1914 inst->_has_immediat = 0; 1915 // inst->_immediat = ; 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 // inst->_num_reg_rc = ; 1922 inst->_write_rd = 0; 1923 // inst->_num_reg_rd = ; 1915 inst->_immediat = 0; // unnecessary 1916 inst->_read_ra = 1; 1917 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1918 inst->_read_rb = 1; 1919 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1920 inst->_read_rc = 0; 1921 inst->_num_reg_rc = 0; //unnecessary 1922 inst->_write_rd = 0; 1923 inst->_num_reg_rd = 0; //unnecessary 1924 1924 inst->_write_re = 1; 1925 1925 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1929 1929 // inst->_branch_stack_write = ; 1930 1930 // inst->_branch_direction = ; 1931 // inst->_address_next = ; 1931 // inst->_address_next = ; // already define : PC+4 1932 1932 inst->_no_execute = 0; 1933 1933 inst->_event_type = EVENT_TYPE_NONE; … … 1945 1945 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1946 1946 inst->_read_rb = 0; 1947 // inst->_num_reg_rb = ; 1948 inst->_read_rc = 0; 1949 // inst->_num_reg_rc = ; 1950 inst->_write_rd = 0; 1951 // inst->_num_reg_rd = ; 1947 inst->_num_reg_rb = 0; //unnecessary 1948 inst->_read_rc = 0; 1949 inst->_num_reg_rc = 0; //unnecessary 1950 inst->_write_rd = 0; 1951 inst->_num_reg_rd = 0; //unnecessary 1952 1952 inst->_write_re = 1; 1953 1953 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1957 1957 // inst->_branch_stack_write = ; 1958 1958 // inst->_branch_direction = ; 1959 // inst->_address_next = ; 1959 // inst->_address_next = ; // already define : PC+4 1960 1960 inst->_no_execute = 0; 1961 1961 inst->_event_type = EVENT_TYPE_NONE; … … 1969 1969 inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; 1970 1970 inst->_has_immediat = 0; 1971 // inst->_immediat = ; 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 // inst->_num_reg_rc = ; 1978 inst->_write_rd = 0; 1979 // inst->_num_reg_rd = ; 1971 inst->_immediat = 0; // unnecessary 1972 inst->_read_ra = 1; 1973 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1974 inst->_read_rb = 1; 1975 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1976 inst->_read_rc = 0; 1977 inst->_num_reg_rc = 0; //unnecessary 1978 inst->_write_rd = 0; 1979 inst->_num_reg_rd = 0; //unnecessary 1980 1980 inst->_write_re = 1; 1981 1981 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 1985 1985 // inst->_branch_stack_write = ; 1986 1986 // inst->_branch_direction = ; 1987 // inst->_address_next = ; 1987 // inst->_address_next = ; // already define : PC+4 1988 1988 inst->_no_execute = 0; 1989 1989 inst->_event_type = EVENT_TYPE_NONE; … … 2001 2001 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2002 2002 inst->_read_rb = 0; 2003 // inst->_num_reg_rb = ; 2004 inst->_read_rc = 0; 2005 // inst->_num_reg_rc = ; 2006 inst->_write_rd = 0; 2007 // inst->_num_reg_rd = ; 2003 inst->_num_reg_rb = 0; //unnecessary 2004 inst->_read_rc = 0; 2005 inst->_num_reg_rc = 0; //unnecessary 2006 inst->_write_rd = 0; 2007 inst->_num_reg_rd = 0; //unnecessary 2008 2008 inst->_write_re = 1; 2009 2009 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2013 2013 // inst->_branch_stack_write = ; 2014 2014 // inst->_branch_direction = ; 2015 // inst->_address_next = ; 2015 // inst->_address_next = ; // already define : PC+4 2016 2016 inst->_no_execute = 0; 2017 2017 inst->_event_type = EVENT_TYPE_NONE; … … 2025 2025 inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; 2026 2026 inst->_has_immediat = 0; 2027 // inst->_immediat = ; 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 // inst->_num_reg_rc = ; 2034 inst->_write_rd = 0; 2035 // inst->_num_reg_rd = ; 2027 inst->_immediat = 0; // unnecessary 2028 inst->_read_ra = 1; 2029 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2030 inst->_read_rb = 1; 2031 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2032 inst->_read_rc = 0; 2033 inst->_num_reg_rc = 0; //unnecessary 2034 inst->_write_rd = 0; 2035 inst->_num_reg_rd = 0; //unnecessary 2036 2036 inst->_write_re = 1; 2037 2037 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2041 2041 // inst->_branch_stack_write = ; 2042 2042 // inst->_branch_direction = ; 2043 // inst->_address_next = ; 2043 // inst->_address_next = ; // already define : PC+4 2044 2044 inst->_no_execute = 0; 2045 2045 inst->_event_type = EVENT_TYPE_NONE; … … 2057 2057 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2058 2058 inst->_read_rb = 0; 2059 // inst->_num_reg_rb = ; 2060 inst->_read_rc = 0; 2061 // inst->_num_reg_rc = ; 2062 inst->_write_rd = 0; 2063 // inst->_num_reg_rd = ; 2059 inst->_num_reg_rb = 0; //unnecessary 2060 inst->_read_rc = 0; 2061 inst->_num_reg_rc = 0; //unnecessary 2062 inst->_write_rd = 0; 2063 inst->_num_reg_rd = 0; //unnecessary 2064 2064 inst->_write_re = 1; 2065 2065 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2069 2069 // inst->_branch_stack_write = ; 2070 2070 // inst->_branch_direction = ; 2071 // inst->_address_next = ; 2071 // inst->_address_next = ; // already define : PC+4 2072 2072 inst->_no_execute = 0; 2073 2073 inst->_event_type = EVENT_TYPE_NONE; … … 2081 2081 inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; 2082 2082 inst->_has_immediat = 0; 2083 // inst->_immediat = ; 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 // inst->_num_reg_rc = ; 2090 inst->_write_rd = 0; 2091 // inst->_num_reg_rd = ; 2083 inst->_immediat = 0; // unnecessary 2084 inst->_read_ra = 1; 2085 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2086 inst->_read_rb = 1; 2087 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2088 inst->_read_rc = 0; 2089 inst->_num_reg_rc = 0; //unnecessary 2090 inst->_write_rd = 0; 2091 inst->_num_reg_rd = 0; //unnecessary 2092 2092 inst->_write_re = 1; 2093 2093 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2097 2097 // inst->_branch_stack_write = ; 2098 2098 // inst->_branch_direction = ; 2099 // inst->_address_next = ; 2099 // inst->_address_next = ; // already define : PC+4 2100 2100 inst->_no_execute = 0; 2101 2101 inst->_event_type = EVENT_TYPE_NONE; … … 2113 2113 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2114 2114 inst->_read_rb = 0; 2115 // inst->_num_reg_rb = ; 2116 inst->_read_rc = 0; 2117 // inst->_num_reg_rc = ; 2118 inst->_write_rd = 0; 2119 // inst->_num_reg_rd = ; 2115 inst->_num_reg_rb = 0; //unnecessary 2116 inst->_read_rc = 0; 2117 inst->_num_reg_rc = 0; //unnecessary 2118 inst->_write_rd = 0; 2119 inst->_num_reg_rd = 0; //unnecessary 2120 2120 inst->_write_re = 1; 2121 2121 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2125 2125 // inst->_branch_stack_write = ; 2126 2126 // inst->_branch_direction = ; 2127 // inst->_address_next = ; 2127 // inst->_address_next = ; // already define : PC+4 2128 2128 inst->_no_execute = 0; 2129 2129 inst->_event_type = EVENT_TYPE_NONE; … … 2137 2137 inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; 2138 2138 inst->_has_immediat = 0; 2139 // inst->_immediat = ; 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 // inst->_num_reg_rc = ; 2146 inst->_write_rd = 0; 2147 // inst->_num_reg_rd = ; 2139 inst->_immediat = 0; // unnecessary 2140 inst->_read_ra = 1; 2141 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2142 inst->_read_rb = 1; 2143 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2144 inst->_read_rc = 0; 2145 inst->_num_reg_rc = 0; //unnecessary 2146 inst->_write_rd = 0; 2147 inst->_num_reg_rd = 0; //unnecessary 2148 2148 inst->_write_re = 1; 2149 2149 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2153 2153 // inst->_branch_stack_write = ; 2154 2154 // inst->_branch_direction = ; 2155 // inst->_address_next = ; 2155 // inst->_address_next = ; // already define : PC+4 2156 2156 inst->_no_execute = 0; 2157 2157 inst->_event_type = EVENT_TYPE_NONE; … … 2169 2169 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2170 2170 inst->_read_rb = 0; 2171 // inst->_num_reg_rb = ; 2172 inst->_read_rc = 0; 2173 // inst->_num_reg_rc = ; 2174 inst->_write_rd = 0; 2175 // inst->_num_reg_rd = ; 2171 inst->_num_reg_rb = 0; //unnecessary 2172 inst->_read_rc = 0; 2173 inst->_num_reg_rc = 0; //unnecessary 2174 inst->_write_rd = 0; 2175 inst->_num_reg_rd = 0; //unnecessary 2176 2176 inst->_write_re = 1; 2177 2177 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2181 2181 // inst->_branch_stack_write = ; 2182 2182 // inst->_branch_direction = ; 2183 // inst->_address_next = ; 2183 // inst->_address_next = ; // already define : PC+4 2184 2184 inst->_no_execute = 0; 2185 2185 inst->_event_type = EVENT_TYPE_NONE; … … 2193 2193 inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; 2194 2194 inst->_has_immediat = 0; 2195 // inst->_immediat = ; 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 // inst->_num_reg_rc = ; 2202 inst->_write_rd = 0; 2203 // inst->_num_reg_rd = ; 2195 inst->_immediat = 0; // unnecessary 2196 inst->_read_ra = 1; 2197 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2198 inst->_read_rb = 1; 2199 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2200 inst->_read_rc = 0; 2201 inst->_num_reg_rc = 0; //unnecessary 2202 inst->_write_rd = 0; 2203 inst->_num_reg_rd = 0; //unnecessary 2204 2204 inst->_write_re = 1; 2205 2205 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2209 2209 // inst->_branch_stack_write = ; 2210 2210 // inst->_branch_direction = ; 2211 // inst->_address_next = ; 2211 // inst->_address_next = ; // already define : PC+4 2212 2212 inst->_no_execute = 0; 2213 2213 inst->_event_type = EVENT_TYPE_NONE; … … 2225 2225 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2226 2226 inst->_read_rb = 0; 2227 // inst->_num_reg_rb = ; 2228 inst->_read_rc = 0; 2229 // inst->_num_reg_rc = ; 2230 inst->_write_rd = 0; 2231 // inst->_num_reg_rd = ; 2227 inst->_num_reg_rb = 0; //unnecessary 2228 inst->_read_rc = 0; 2229 inst->_num_reg_rc = 0; //unnecessary 2230 inst->_write_rd = 0; 2231 inst->_num_reg_rd = 0; //unnecessary 2232 2232 inst->_write_re = 1; 2233 2233 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2237 2237 // inst->_branch_stack_write = ; 2238 2238 // inst->_branch_direction = ; 2239 // inst->_address_next = ; 2239 // inst->_address_next = ; // already define : PC+4 2240 2240 inst->_no_execute = 0; 2241 2241 inst->_event_type = EVENT_TYPE_NONE; … … 2249 2249 inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; 2250 2250 inst->_has_immediat = 0; 2251 // inst->_immediat = ; 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 // inst->_num_reg_rc = ; 2258 inst->_write_rd = 0; 2259 // inst->_num_reg_rd = ; 2251 inst->_immediat = 0; // unnecessary 2252 inst->_read_ra = 1; 2253 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2254 inst->_read_rb = 1; 2255 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2256 inst->_read_rc = 0; 2257 inst->_num_reg_rc = 0; //unnecessary 2258 inst->_write_rd = 0; 2259 inst->_num_reg_rd = 0; //unnecessary 2260 2260 inst->_write_re = 1; 2261 2261 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2265 2265 // inst->_branch_stack_write = ; 2266 2266 // inst->_branch_direction = ; 2267 // inst->_address_next = ; 2267 // inst->_address_next = ; // already define : PC+4 2268 2268 inst->_no_execute = 0; 2269 2269 inst->_event_type = EVENT_TYPE_NONE; … … 2281 2281 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2282 2282 inst->_read_rb = 0; 2283 // inst->_num_reg_rb = ; 2284 inst->_read_rc = 0; 2285 // inst->_num_reg_rc = ; 2286 inst->_write_rd = 0; 2287 // inst->_num_reg_rd = ; 2283 inst->_num_reg_rb = 0; //unnecessary 2284 inst->_read_rc = 0; 2285 inst->_num_reg_rc = 0; //unnecessary 2286 inst->_write_rd = 0; 2287 inst->_num_reg_rd = 0; //unnecessary 2288 2288 inst->_write_re = 1; 2289 2289 inst->_num_reg_re = SPR_LOGIC_SR_F; … … 2293 2293 // inst->_branch_stack_write = ; 2294 2294 // inst->_branch_direction = ; 2295 // inst->_address_next = ; 2295 // inst->_address_next = ; // already define : PC+4 2296 2296 inst->_no_execute = 0; 2297 2297 inst->_event_type = EVENT_TYPE_NONE; … … 2312 2312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2313 2313 inst->_read_rc = 0; 2314 // inst->_num_reg_rc = ; 2315 inst->_write_rd = 0; 2316 // inst->_num_reg_rd = ; 2317 inst->_write_re = 0; 2318 // inst->_num_reg_re = ; 2314 inst->_num_reg_rc = 0; //unnecessary 2315 inst->_write_rd = 0; 2316 inst->_num_reg_rd = 0; //unnecessary 2317 inst->_write_re = 0; 2318 inst->_num_reg_re = 0; //unnecessary 2319 2319 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2320 2320 inst->_exception = EXCEPTION_DECOD_NONE; … … 2322 2322 // inst->_branch_stack_write = ; 2323 2323 // inst->_branch_direction = ; 2324 // inst->_address_next = ; 2324 // inst->_address_next = ; // already define : PC+4 2325 2325 inst->_no_execute = 0; 2326 2326 inst->_event_type = EVENT_TYPE_NONE; … … 2334 2334 inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; 2335 2335 inst->_has_immediat = 0; 2336 // inst->_immediat = ; 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 // inst->_num_reg_rc = ; 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 // inst->_num_reg_re = ; 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; 2336 inst->_immediat = 0; // unnecessary 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 inst->_num_reg_rc = 0; //unnecessary 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 inst->_num_reg_re = 0; //unnecessary 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; // already define : PC+4 2353 2353 inst->_no_execute = 0; 2354 2354 inst->_event_type = EVENT_TYPE_NONE; … … 2366 2366 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2367 2367 inst->_read_rb = 0; 2368 // inst->_num_reg_rb = ; 2369 inst->_read_rc = 0; 2370 // inst->_num_reg_rc = ; 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 // inst->_num_reg_re = ; 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; 2368 inst->_num_reg_rb = 0; //unnecessary 2369 inst->_read_rc = 0; 2370 inst->_num_reg_rc = 0; //unnecessary 2371 inst->_write_rd = 1; 2372 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2373 inst->_write_re = 0; 2374 inst->_num_reg_re = 0; //unnecessary 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; // already define : PC+4 2381 2381 inst->_no_execute = 0; 2382 2382 inst->_event_type = EVENT_TYPE_NONE; … … 2390 2390 inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; 2391 2391 inst->_has_immediat = 0; 2392 // inst->_immediat = ; 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 // inst->_num_reg_rc = ; 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 // inst->_num_reg_re = ; 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; 2392 inst->_immediat = 0; // unnecessary 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 inst->_num_reg_rc = 0; //unnecessary 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 inst->_num_reg_re = 0; //unnecessary 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; // already define : PC+4 2409 2409 inst->_no_execute = 0; 2410 2410 inst->_event_type = EVENT_TYPE_NONE; … … 2422 2422 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2423 2423 inst->_read_rb = 0; 2424 // inst->_num_reg_rb = ; 2425 inst->_read_rc = 0; 2426 // inst->_num_reg_rc = ; 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 // inst->_num_reg_re = ; 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; 2424 inst->_num_reg_rb = 0; //unnecessary 2425 inst->_read_rc = 0; 2426 inst->_num_reg_rc = 0; //unnecessary 2427 inst->_write_rd = 1; 2428 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2429 inst->_write_re = 0; 2430 inst->_num_reg_re = 0; //unnecessary 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; // already define : PC+4 2437 2437 inst->_no_execute = 0; 2438 2438 inst->_event_type = EVENT_TYPE_NONE; … … 2446 2446 inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; 2447 2447 inst->_has_immediat = 0; 2448 // inst->_immediat = ; 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 // inst->_num_reg_rc = ; 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 // inst->_num_reg_re = ; 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; 2448 inst->_immediat = 0; // unnecessary 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 inst->_num_reg_rc = 0; //unnecessary 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 inst->_num_reg_re = 0; //unnecessary 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; // already define : PC+4 2465 2465 inst->_no_execute = 0; 2466 2466 inst->_event_type = EVENT_TYPE_NONE; … … 2478 2478 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2479 2479 inst->_read_rb = 0; 2480 // inst->_num_reg_rb = ; 2481 inst->_read_rc = 0; 2482 // inst->_num_reg_rc = ; 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 // inst->_num_reg_re = ; 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; 2480 inst->_num_reg_rb = 0; //unnecessary 2481 inst->_read_rc = 0; 2482 inst->_num_reg_rc = 0; //unnecessary 2483 inst->_write_rd = 1; 2484 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2485 inst->_write_re = 0; 2486 inst->_num_reg_re = 0; //unnecessary 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; // already define : PC+4 2493 2493 inst->_no_execute = 0; 2494 2494 inst->_event_type = EVENT_TYPE_NONE; … … 2502 2502 inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; 2503 2503 inst->_has_immediat = 0; 2504 // inst->_immediat = ; 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 // inst->_num_reg_rc = ; 2504 inst->_immediat = 0; // unnecessary 2505 inst->_read_ra = 1; 2506 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2507 inst->_read_rb = 1; 2508 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2509 inst->_read_rc = 0; 2510 inst->_num_reg_rc = 0; //unnecessary 2511 2511 inst->_write_rd = 1; 2512 2512 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); … … 2518 2518 // inst->_branch_stack_write = ; 2519 2519 // inst->_branch_direction = ; 2520 // inst->_address_next = ; 2520 // inst->_address_next = ; // already define : PC+4 2521 2521 inst->_no_execute = 0; 2522 2522 inst->_event_type = EVENT_TYPE_NONE; … … 2537 2537 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2538 2538 inst->_read_rc = 0; 2539 // inst->_num_reg_rc = ; 2540 inst->_write_rd = 0; 2541 // inst->_num_reg_rd = ; 2542 inst->_write_re = 0; 2543 // inst->_num_reg_re = ; 2539 inst->_num_reg_rc = 0; //unnecessary 2540 inst->_write_rd = 0; 2541 inst->_num_reg_rd = 0; //unnecessary 2542 inst->_write_re = 0; 2543 inst->_num_reg_re = 0; //unnecessary 2544 2544 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2545 2545 inst->_exception = EXCEPTION_DECOD_NONE; … … 2547 2547 // inst->_branch_stack_write = ; 2548 2548 // inst->_branch_direction = ; 2549 // inst->_address_next = ; 2549 // inst->_address_next = ; // already define : PC+4 2550 2550 inst->_no_execute = 0; 2551 2551 inst->_event_type = EVENT_TYPE_NONE; … … 2567 2567 // inst->_immediat = EXTENDZ(inst->_instruction,16); 2568 2568 inst->_has_immediat = 0; 2569 // inst->_immediat = ; 2569 inst->_immediat = 0; // unnecessary 2570 2570 inst->_read_ra = 0; 2571 // inst->_num_reg_ra = ; 2572 inst->_read_rb = 0; 2573 // inst->_num_reg_rb = ; 2574 inst->_read_rc = 0; 2575 // inst->_num_reg_rc = ; 2576 inst->_write_rd = 0; 2577 // inst->_num_reg_rd = ; 2578 inst->_write_re = 0; 2579 // inst->_num_reg_re = ; 2571 inst->_num_reg_ra = 0; //unnecessary 2572 inst->_read_rb = 0; 2573 inst->_num_reg_rb = 0; //unnecessary 2574 inst->_read_rc = 0; 2575 inst->_num_reg_rc = 0; //unnecessary 2576 inst->_write_rd = 0; 2577 inst->_num_reg_rd = 0; //unnecessary 2578 inst->_write_re = 0; 2579 inst->_num_reg_re = 0; //unnecessary 2580 2580 inst->_exception_use = EXCEPTION_USE_SYSCALL; 2581 2581 inst->_exception = EXCEPTION_SYSCALL; … … 2590 2590 2591 2591 2592 // inst->_address_next = ; // don't change2592 // inst->_address_next = ; // already define : PC+4 // don't change 2593 2593 inst->_no_execute = 1; 2594 2594 inst->_event_type = EVENT_TYPE_EXCEPTION; … … 2611 2611 inst->_immediat = EXTENDZ(inst->_instruction,16); 2612 2612 inst->_read_ra = 0; 2613 // inst->_num_reg_ra = ; 2614 inst->_read_rb = 0; 2615 // inst->_num_reg_rb = ; 2613 inst->_num_reg_ra = 0; //unnecessary 2614 inst->_read_rb = 0; 2615 inst->_num_reg_rb = 0; //unnecessary 2616 2616 inst->_read_rc = 0; // read all SR 2617 // inst->_num_reg_rc = ; 2618 inst->_write_rd = 0; 2619 // inst->_num_reg_rd = ; 2620 inst->_write_re = 0; 2621 // inst->_num_reg_re = ; 2617 inst->_num_reg_rc = 0; //unnecessary 2618 inst->_write_rd = 0; 2619 inst->_num_reg_rd = 0; //unnecessary 2620 inst->_write_re = 0; 2621 inst->_num_reg_re = 0; //unnecessary 2622 2622 inst->_exception_use = EXCEPTION_USE_TRAP; 2623 2623 inst->_exception = EXCEPTION_DECOD_NONE; … … 2625 2625 // inst->_branch_stack_write = ; 2626 2626 // inst->_branch_direction = ; 2627 // inst->_address_next = ; 2627 // inst->_address_next = ; // already define : PC+4 2628 2628 inst->_no_execute = 1; 2629 2629 inst->_event_type = EVENT_TYPE_NONE; … … 2638 2638 inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; 2639 2639 inst->_has_immediat = 0; 2640 // inst->_immediat = ; 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 // inst->_num_reg_rc = ; 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 // inst->_num_reg_re = ; 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; 2640 inst->_immediat = 0; // unnecessary 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 inst->_num_reg_rc = 0; //unnecessary 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 inst->_num_reg_re = 0; //unnecessary 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; // already define : PC+4 2657 2657 inst->_no_execute = 0; 2658 2658 inst->_event_type = EVENT_TYPE_NONE; … … 2670 2670 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2671 2671 inst->_read_rb = 0; 2672 // inst->_num_reg_rb = ; 2673 inst->_read_rc = 0; 2674 // inst->_num_reg_rc = ; 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 // inst->_num_reg_re = ; 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; 2672 inst->_num_reg_rb = 0; //unnecessary 2673 inst->_read_rc = 0; 2674 inst->_num_reg_rc = 0; //unnecessary 2675 inst->_write_rd = 1; 2676 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2677 inst->_write_re = 0; 2678 inst->_num_reg_re = 0; //unnecessary 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; // already define : PC+4 2685 2685 inst->_no_execute = 0; 2686 2686 inst->_event_type = EVENT_TYPE_NONE;
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