Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 97)
@@ -255,11 +255,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -271,5 +271,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -283,5 +283,5 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 1;
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
@@ -299,5 +299,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -315,7 +315,7 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -327,5 +327,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -343,5 +343,5 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_CY_OV;
@@ -355,5 +355,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -367,21 +367,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -399,17 +399,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -428,13 +428,13 @@
     inst->_immediat           = address_next;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_F;
     inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -460,7 +460,7 @@
     inst->_immediat           = address_next;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_F;
@@ -468,5 +468,5 @@
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -486,5 +486,5 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 1;
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
@@ -496,11 +496,11 @@
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -520,21 +520,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_CSYNC;
@@ -558,11 +558,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -574,5 +574,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -586,11 +586,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -602,5 +602,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -618,17 +618,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -646,17 +646,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -674,17 +674,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -702,17 +702,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -730,17 +730,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -758,17 +758,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -782,21 +782,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -810,21 +810,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -838,15 +838,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -869,13 +869,13 @@
     inst->_immediat           = inst->_address_next+1;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = 9; // Link register
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -904,15 +904,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
     inst->_read_rb            = 1;
 //  inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = 9; // Link register
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -921,5 +921,5 @@
 //  inst->_branch_stack_write = 1;
     inst->_branch_direction   = 1;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -934,15 +934,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -950,5 +950,5 @@
 //  inst->_branch_stack_write = 0;
     inst->_branch_direction   = 1;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -966,11 +966,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -978,5 +978,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -994,11 +994,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1006,5 +1006,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1022,11 +1022,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1034,5 +1034,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1050,11 +1050,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1062,5 +1062,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1078,11 +1078,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1090,5 +1090,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1106,11 +1106,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1118,5 +1118,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1134,11 +1134,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1146,5 +1146,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1158,21 +1158,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1191,17 +1191,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1221,21 +1221,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1254,17 +1254,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1280,19 +1280,19 @@
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1306,21 +1306,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1340,21 +1340,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_MSYNC;
@@ -1376,15 +1376,15 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1398,11 +1398,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1414,5 +1414,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1430,7 +1430,7 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1442,5 +1442,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1454,11 +1454,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1470,5 +1470,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1484,21 +1484,21 @@
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1512,21 +1512,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1544,17 +1544,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1574,21 +1574,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_PSYNC;
@@ -1603,21 +1603,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
@@ -1631,21 +1631,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1663,17 +1663,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1694,9 +1694,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1704,5 +1704,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1723,9 +1723,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1733,5 +1733,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1745,13 +1745,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1761,5 +1761,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1777,9 +1777,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1789,5 +1789,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1801,13 +1801,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1817,5 +1817,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1833,9 +1833,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1845,5 +1845,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1857,13 +1857,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1873,5 +1873,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1889,9 +1889,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1901,5 +1901,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1913,13 +1913,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1929,5 +1929,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1945,9 +1945,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1957,5 +1957,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1969,13 +1969,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1985,5 +1985,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2001,9 +2001,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2013,5 +2013,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2025,13 +2025,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2041,5 +2041,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2057,9 +2057,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2069,5 +2069,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2081,13 +2081,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2097,5 +2097,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2113,9 +2113,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2125,5 +2125,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2137,13 +2137,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2153,5 +2153,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2169,9 +2169,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2181,5 +2181,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2193,13 +2193,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2209,5 +2209,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2225,9 +2225,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2237,5 +2237,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2249,13 +2249,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2265,5 +2265,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2281,9 +2281,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2293,5 +2293,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2312,9 +2312,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2322,5 +2322,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2334,21 +2334,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2366,17 +2366,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2390,21 +2390,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2422,17 +2422,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2446,21 +2446,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2478,17 +2478,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2502,11 +2502,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -2518,5 +2518,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2537,9 +2537,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2547,5 +2547,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2567,15 +2567,15 @@
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_SYSCALL;
     inst->_exception          = EXCEPTION_SYSCALL;
@@ -2590,5 +2590,5 @@
 
 
-//  inst->_address_next       = ; // don't change
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_EXCEPTION;
@@ -2611,13 +2611,13 @@
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 0; // read all SR
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_TRAP;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2625,5 +2625,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2638,21 +2638,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2670,17 +2670,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
