Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 97)
@@ -75,5 +75,5 @@
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR      ," in_COMMIT_EVENT_ADDRESS_EPCR      ",Taddress_t   );
   ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ",Tcontrol_t   );
-  ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR      ," in_COMMIT_EVENT_ADDRESS_EEAR      ",Taddress_t   );
+  ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR      ," in_COMMIT_EVENT_ADDRESS_EEAR      ",Tgeneral_data_t);
 
   ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL            ," in_BRANCH_COMPLETE_VAL            ",Tcontrol_t   ,_param->_nb_inst_branch_complete);
@@ -97,5 +97,7 @@
   ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL         ,"out_EVENT_ADDRESS_NEXT_VAL         ",Tcontrol_t   ,_param->_nb_context   );
   ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE               ,"out_EVENT_IS_DS_TAKE               ",Tcontrol_t   ,_param->_nb_context   );
-						      				           
+  ALLOC1_SC_SIGNAL(out_EVENT_TYPE                     ,"out_EVENT_TYPE                     ",Tevent_type_t,_param->_nb_context   );
+  ALLOC1_SC_SIGNAL(out_EVENT_DEPTH                    ,"out_EVENT_DEPTH                    ",Tdepth_t     ,_param->_nb_context   );
+
   ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL                  ,"out_SPR_EVENT_VAL                  ",Tcontrol_t   ,_param->_nb_context   );
   ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK                  ," in_SPR_EVENT_ACK                  ",Tcontrol_t   ,_param->_nb_context   );
@@ -177,4 +179,7 @@
   INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL         ,_param->_nb_context   );
   INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE               ,_param->_nb_context   );
+  INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE                     ,_param->_nb_context   );
+  if (_param->_have_port_depth)
+  INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH                    ,_param->_nb_context   );
 								        
   INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL                  ,_param->_nb_context   );
@@ -1273,4 +1278,6 @@
   DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL         ,_param->_nb_context   );
   DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE               ,_param->_nb_context   );
+  DELETE1_SC_SIGNAL(out_EVENT_TYPE                     ,_param->_nb_context   );
+  DELETE1_SC_SIGNAL(out_EVENT_DEPTH                    ,_param->_nb_context   );
   DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL                  ,_param->_nb_context   );
   DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK                  ,_param->_nb_context   );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h	(revision 97)
@@ -93,5 +93,5 @@
   public    : SC_IN (Taddress_t         )   *  in_COMMIT_EVENT_ADDRESS_EPCR          ;
   public    : SC_IN (Tcontrol_t         )   *  in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ;
-  public    : SC_IN (Taddress_t         )   *  in_COMMIT_EVENT_ADDRESS_EEAR          ;
+  public    : SC_IN (Tgeneral_data_t    )   *  in_COMMIT_EVENT_ADDRESS_EEAR          ;
 
     // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp	(revision 97)
@@ -97,5 +97,5 @@
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EPCR          ,"address_epcr"    ,Taddress_t         ,_param->_size_instruction_address);
       ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL      ,"address_eear_val",Tcontrol_t         ,1);
-      ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR          ,"address_eear"    ,Taddress_t         ,_param->_size_instruction_address);
+      ALLOC_SIGNAL_IN  ( in_COMMIT_EVENT_ADDRESS_EEAR          ,"address_eear"    ,Tgeneral_data_t    ,_param->_size_general_data);
     }
 
@@ -133,4 +133,7 @@
       ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL             ,"address_next_val",Tcontrol_t        ,1);
       ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE                   ,"is_ds_take"      ,Tcontrol_t        ,1);
+      ALLOC1_SIGNAL_OUT(out_EVENT_TYPE                         ,"type"            ,Tevent_type_t     ,_param->_size_event_type);
+      ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH                        ,"depth"           ,Tdepth_t          ,_param->_size_depth);
+
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp	(revision 97)
@@ -76,5 +76,7 @@
         DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL             ,_param->_nb_context,1);
         DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE                   ,_param->_nb_context,1);
-        
+        DELETE1_SIGNAL(out_EVENT_TYPE                         ,_param->_nb_context,_param->_size_event_type);
+        DELETE1_SIGNAL(out_EVENT_DEPTH                        ,_param->_nb_context,_param->_size_depth);
+
 	DELETE1_SIGNAL(out_SPR_EVENT_VAL                      ,_param->_nb_context,1);
         DELETE1_SIGNAL( in_SPR_EVENT_ACK                      ,_param->_nb_context,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp	(revision 97)
@@ -38,12 +38,27 @@
         // SR can't change in this cycle
         // Exception Prefix High
-        Taddress_t address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
-        Taddress_t address_next     = reg_EVENT_ADDRESS_EPCR [i];
-        Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
-        Tcontrol_t is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
+        Taddress_t    address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
+        Taddress_t    address_next     = reg_EVENT_ADDRESS_EPCR [i];
+        Tcontrol_t    address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
+        Tcontrol_t    is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
 	// excep : address exception
 	// miss  : address delay_slot, and address dest
 	// psync : address next
 	// csync : address next
+        Tevent_type_t type                         ;//[nb_context]
+        Tdepth_t      depth            = reg_EVENT_DEPTH [i];
+
+        switch (state)
+          {
+          case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION         ); break;
+          case CONTEXT_STATE_KO_MISS_ADDR  : (type = EVENT_TYPE_MISS_SPECULATION  ); break;
+          case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC             ); break; 
+          case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC             ); break;
+          default                          : (type = EVENT_TYPE_NONE              ); break;
+          }
+//      (type = EVENT_TYPE_SPR_ACCESS        );
+//      (type = EVENT_TYPE_MSYNC             );
+//      (type = EVENT_TYPE_BRANCH_NO_ACCURATE);
+
         internal_EVENT_VAL [i] = val;
 	PORT_WRITE(out_EVENT_VAL              [i], val);
@@ -52,4 +67,7 @@
 	PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
 	PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
+	PORT_WRITE(out_EVENT_TYPE             [i], type);
+        if (_param->_have_port_depth)
+	PORT_WRITE(out_EVENT_DEPTH            [i], depth);
 
 	log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
@@ -59,4 +77,6 @@
 	log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
 	log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
+	log_printf(TRACE,Context_State,FUNCTION,"    * TYPE             : %d", type);
+	log_printf(TRACE,Context_State,FUNCTION,"    * DEPTH            : %d", depth);
       }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp	(revision 97)
@@ -255,11 +255,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -271,5 +271,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -283,5 +283,5 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 1;
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
@@ -299,5 +299,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -315,7 +315,7 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -327,5 +327,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -343,5 +343,5 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_CY_OV;
@@ -355,5 +355,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -367,21 +367,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -399,17 +399,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -428,13 +428,13 @@
     inst->_immediat           = address_next;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_F;
     inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -460,7 +460,7 @@
     inst->_immediat           = address_next;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 1;
     inst->_num_reg_rc         = SPR_LOGIC_SR_F;
@@ -468,5 +468,5 @@
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -486,5 +486,5 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 1;
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
@@ -496,11 +496,11 @@
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -520,21 +520,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_CSYNC;
@@ -558,11 +558,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -574,5 +574,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -586,11 +586,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -602,5 +602,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -618,17 +618,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -646,17 +646,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -674,17 +674,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -702,17 +702,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -730,17 +730,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -758,17 +758,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -782,21 +782,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -810,21 +810,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -838,15 +838,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -869,13 +869,13 @@
     inst->_immediat           = inst->_address_next+1;
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = 9; // Link register
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -904,15 +904,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
     inst->_read_rb            = 1;
 //  inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = 9; // Link register
     inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -921,5 +921,5 @@
 //  inst->_branch_stack_write = 1;
     inst->_branch_direction   = 1;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -934,15 +934,15 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_NONE;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -950,5 +950,5 @@
 //  inst->_branch_stack_write = 0;
     inst->_branch_direction   = 1;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -966,11 +966,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -978,5 +978,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -994,11 +994,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1006,5 +1006,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1022,11 +1022,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1034,5 +1034,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1050,11 +1050,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1062,5 +1062,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1078,11 +1078,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1090,5 +1090,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1106,11 +1106,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1118,5 +1118,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1134,11 +1134,11 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1146,5 +1146,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1158,21 +1158,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1191,17 +1191,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1221,21 +1221,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1254,17 +1254,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1280,19 +1280,19 @@
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1306,21 +1306,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1340,21 +1340,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_MSYNC;
@@ -1376,15 +1376,15 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_SPR_ACCESS;
@@ -1398,11 +1398,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1414,5 +1414,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1430,7 +1430,7 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1442,5 +1442,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1454,11 +1454,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -1470,5 +1470,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1484,21 +1484,21 @@
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1512,21 +1512,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1544,17 +1544,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1574,21 +1574,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_PSYNC;
@@ -1603,21 +1603,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ; // don't change
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
@@ -1631,21 +1631,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1663,17 +1663,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1694,9 +1694,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1704,5 +1704,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1723,9 +1723,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -1733,5 +1733,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1745,13 +1745,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1761,5 +1761,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1777,9 +1777,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1789,5 +1789,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1801,13 +1801,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1817,5 +1817,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1833,9 +1833,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1845,5 +1845,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1857,13 +1857,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1873,5 +1873,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1889,9 +1889,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1901,5 +1901,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1913,13 +1913,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1929,5 +1929,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1945,9 +1945,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1957,5 +1957,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -1969,13 +1969,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -1985,5 +1985,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2001,9 +2001,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2013,5 +2013,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2025,13 +2025,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2041,5 +2041,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2057,9 +2057,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2069,5 +2069,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2081,13 +2081,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2097,5 +2097,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2113,9 +2113,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2125,5 +2125,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2137,13 +2137,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2153,5 +2153,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2169,9 +2169,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2181,5 +2181,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2193,13 +2193,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2209,5 +2209,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2225,9 +2225,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2237,5 +2237,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2249,13 +2249,13 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2265,5 +2265,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2281,9 +2281,9 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
     inst->_write_re           = 1;
     inst->_num_reg_re         = SPR_LOGIC_SR_F;
@@ -2293,5 +2293,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2312,9 +2312,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2322,5 +2322,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2334,21 +2334,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2366,17 +2366,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2390,21 +2390,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2422,17 +2422,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2446,21 +2446,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2478,17 +2478,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2502,11 +2502,11 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
     inst->_write_rd           = 1;
     inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
@@ -2518,5 +2518,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2537,9 +2537,9 @@
     inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
     inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2547,5 +2547,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2567,15 +2567,15 @@
 //  inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
+    inst->_immediat           = 0; // unnecessary
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_SYSCALL;
     inst->_exception          = EXCEPTION_SYSCALL;
@@ -2590,5 +2590,5 @@
 
 
-//  inst->_address_next       = ; // don't change
+//  inst->_address_next       = ; // already define : PC+4 // don't change
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_EXCEPTION;
@@ -2611,13 +2611,13 @@
     inst->_immediat           = EXTENDZ(inst->_instruction,16);
     inst->_read_ra            = 0;
-//  inst->_num_reg_ra         = ;
-    inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
+    inst->_num_reg_ra         = 0; //unnecessary
+    inst->_read_rb            = 0;
+    inst->_num_reg_rb         = 0; //unnecessary
     inst->_read_rc            = 0; // read all SR
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 0;
-//  inst->_num_reg_rd         = ;
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 0;
+    inst->_num_reg_rd         = 0; //unnecessary
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
     inst->_exception_use      = EXCEPTION_USE_TRAP;
     inst->_exception          = EXCEPTION_DECOD_NONE;
@@ -2625,5 +2625,5 @@
 //  inst->_branch_stack_write = ;
 //  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 1;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2638,21 +2638,21 @@
     inst->_operation          = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR;
     inst->_has_immediat       = 0;
-//  inst->_immediat           = ;
-    inst->_read_ra            = 1;
-    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
-    inst->_read_rb            = 1;
-    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_immediat           = 0; // unnecessary
+    inst->_read_ra            = 1;
+    inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
+    inst->_read_rb            = 1;
+    inst->_num_reg_rb         = range<Tgeneral_address_t>(inst->_instruction,15,11);
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
@@ -2670,17 +2670,17 @@
     inst->_num_reg_ra         = range<Tgeneral_address_t>(inst->_instruction,20,16);
     inst->_read_rb            = 0;
-//  inst->_num_reg_rb         = ;
-    inst->_read_rc            = 0;
-//  inst->_num_reg_rc         = ;
-    inst->_write_rd           = 1;
-    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
-    inst->_write_re           = 0;
-//  inst->_num_reg_re         = ;
-    inst->_exception_use      = EXCEPTION_USE_NONE;
-    inst->_exception          = EXCEPTION_DECOD_NONE;
-//  inst->_branch_condition   = ;
-//  inst->_branch_stack_write = ;
-//  inst->_branch_direction   = ;
-//  inst->_address_next       = ;
+    inst->_num_reg_rb         = 0; //unnecessary
+    inst->_read_rc            = 0;
+    inst->_num_reg_rc         = 0; //unnecessary
+    inst->_write_rd           = 1;
+    inst->_num_reg_rd         = range<Tgeneral_address_t>(inst->_instruction,25,21);
+    inst->_write_re           = 0;
+    inst->_num_reg_re         = 0; //unnecessary
+    inst->_exception_use      = EXCEPTION_USE_NONE;
+    inst->_exception          = EXCEPTION_DECOD_NONE;
+//  inst->_branch_condition   = ;
+//  inst->_branch_stack_write = ;
+//  inst->_branch_direction   = ;
+//  inst->_address_next       = ; // already define : PC+4
     inst->_no_execute         = 0;
     inst->_event_type         = EVENT_TYPE_NONE;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp	(revision 97)
@@ -75,4 +75,8 @@
   ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL             ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL             ",Tcontrol_t,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE                   ,"out_EVENT_IFETCH_UNIT_IS_DS_TAKE                   ",Tcontrol_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL                      ,"out_EVENT_PREDICTION_UNIT_VAL                      ",Tcontrol_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK                      ," in_EVENT_PREDICTION_UNIT_ACK                      ",Tcontrol_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE                     ,"out_EVENT_PREDICTION_UNIT_TYPE                     ",Tevent_type_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH                    ,"out_EVENT_PREDICTION_UNIT_DEPTH                    ",Tdepth_t  ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL                        ," in_EVENT_CONTEXT_STATE_VAL                        ",Tcontrol_t,_param->_nb_context);
   ALLOC1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK                        ,"out_EVENT_CONTEXT_STATE_ACK                        ",Tcontrol_t,_param->_nb_context);
@@ -81,4 +85,6 @@
   ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL           ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL           ",Tcontrol_t,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE                 ," in_EVENT_CONTEXT_STATE_IS_DS_TAKE                 ",Tcontrol_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE                       ," in_EVENT_CONTEXT_STATE_TYPE                       ",Tevent_type_t,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH                      ," in_EVENT_CONTEXT_STATE_DEPTH                      ",Tdepth_t  ,_param->_nb_context);
 
   ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT                                  ,"out_DEPTH_CURRENT                                  ",Tdepth_t  ,_param->_nb_context);
@@ -132,4 +138,9 @@
   INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL               ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_IS_DS_TAKE                     ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_VAL                        ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_PREDICTION_UNIT_ACK                        ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_TYPE                       ,_param->_nb_context);
+  if (_param->_have_port_depth)
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_DEPTH                      ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_VAL                          ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_CONTEXT_STATE_ACK                          ,_param->_nb_context);
@@ -138,4 +149,7 @@
   INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL             ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_IS_DS_TAKE                   ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_TYPE                         ,_param->_nb_context);
+  if (_param->_have_port_depth)
+  INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_DEPTH                        ,_param->_nb_context);
 
   for (uint32_t i=0; i<_param->_nb_context; ++i)
@@ -230,4 +244,8 @@
   DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL               ,_param->_nb_context);
   DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE                     ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL                        ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK                        ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE                       ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH                      ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL                          ,_param->_nb_context);
   DELETE1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK                          ,_param->_nb_context);
@@ -236,4 +254,6 @@
   DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL             ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE                   ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE                         ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH                        ,_param->_nb_context);
 
   DELETE1_SC_SIGNAL(out_DEPTH_MIN                                        ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h	(revision 97)
@@ -97,4 +97,9 @@
   public    : SC_OUT(Tcontrol_t           )  ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL                ;//[nb_context]
   public    : SC_OUT(Tcontrol_t           )  ** out_EVENT_IFETCH_UNIT_IS_DS_TAKE                      ;//[nb_context]
+
+  public    : SC_OUT(Tcontrol_t           )  ** out_EVENT_PREDICTION_UNIT_VAL                         ;//[nb_context]
+  public    : SC_IN (Tcontrol_t           )  **  in_EVENT_PREDICTION_UNIT_ACK                         ;//[nb_context]
+  public    : SC_OUT(Tevent_type_t        )  ** out_EVENT_PREDICTION_UNIT_TYPE                        ;//[nb_context]
+  public    : SC_OUT(Tdepth_t             )  ** out_EVENT_PREDICTION_UNIT_DEPTH                       ;//[nb_context]
                                             
   public    : SC_IN (Tcontrol_t           )  **  in_EVENT_CONTEXT_STATE_VAL                           ;//[nb_context]
@@ -104,4 +109,6 @@
   public    : SC_IN (Tcontrol_t           )  **  in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL              ;//[nb_context]
   public    : SC_IN (Tcontrol_t           )  **  in_EVENT_CONTEXT_STATE_IS_DS_TAKE                    ;//[nb_context]
+  public    : SC_IN (Tevent_type_t        )  **  in_EVENT_CONTEXT_STATE_TYPE                          ;//[nb_context]
+  public    : SC_IN (Tdepth_t             )  **  in_EVENT_CONTEXT_STATE_DEPTH                         ;//[nb_context]
 
     // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	      
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp	(revision 97)
@@ -138,11 +138,17 @@
 // 	sensitive << (*(in_CLOCK)).neg(); // don't need internal register
         for (uint32_t i=0; i<_param->_nb_context; ++i)
-          sensitive << (*( in_EVENT_ACK                            [i]))
-                    << (*( in_EVENT_IFETCH_UNIT_ACK                [i]))
-                    << (*( in_EVENT_CONTEXT_STATE_VAL              [i]))
-                    << (*( in_EVENT_CONTEXT_STATE_ADDRESS          [i]))
-                    << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT     [i]))
-                    << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]))
-                    << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE       [i]));
+          {
+            sensitive << (*( in_EVENT_ACK                            [i]))
+                      << (*( in_EVENT_IFETCH_UNIT_ACK                [i]))
+                      << (*( in_EVENT_PREDICTION_UNIT_ACK            [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_VAL              [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_ADDRESS          [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT     [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE       [i]))
+                      << (*( in_EVENT_CONTEXT_STATE_TYPE             [i]));
+            if (_param->_have_port_depth)
+            sensitive << (*( in_EVENT_CONTEXT_STATE_DEPTH            [i]));
+          }
 
 # ifdef SYSTEMCASS_SPECIFIC
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp	(revision 97)
@@ -105,4 +105,9 @@
       ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL                ,"IFETCH_UNIT_ADDRESS_NEXT_VAL"  ,Tcontrol_t           ,1);
       ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_IS_DS_TAKE                      ,"IFETCH_UNIT_IS_DS_TAKE"        ,Tcontrol_t           ,1);
+
+      ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_VAL                         ,"PREDICTION_UNIT_VAL"           ,Tcontrol_t           ,1);
+      ALLOC1_SIGNAL_IN  ( in_EVENT_PREDICTION_UNIT_ACK                         ,"PREDICTION_UNIT_ACK"           ,Tcontrol_t           ,1);
+      ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_TYPE                        ,"PREDICTION_UNIT_TYPE"          ,Tevent_type_t        ,_param->_size_event_type);
+      ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_DEPTH                       ,"PREDICTION_UNIT_DEPTH"         ,Tdepth_t             ,_param->_size_depth);
                                                                                                             
       ALLOC1_SIGNAL_IN  ( in_EVENT_CONTEXT_STATE_VAL                           ,"CONTEXT_STATE_VAL"             ,Tcontrol_t           ,1);
@@ -112,4 +117,7 @@
       ALLOC1_SIGNAL_IN  ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL              ,"CONTEXT_STATE_ADDRESS_NEXT_VAL",Tcontrol_t           ,1);
       ALLOC1_SIGNAL_IN  ( in_EVENT_CONTEXT_STATE_IS_DS_TAKE                    ,"CONTEXT_STATE_IS_DS_TAKE"      ,Tcontrol_t           ,1);
+      ALLOC1_SIGNAL_IN  ( in_EVENT_CONTEXT_STATE_TYPE                          ,"CONTEXT_STATE_TYPE"            ,Tevent_type_t        ,_param->_size_event_type);
+      ALLOC1_SIGNAL_IN  ( in_EVENT_CONTEXT_STATE_DEPTH                         ,"CONTEXT_STATE_DEPTH"           ,Tdepth_t             ,_param->_size_depth);
+
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp	(revision 97)
@@ -55,4 +55,10 @@
         DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL               ,_param->_nb_context,1);
         DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE                     ,_param->_nb_context,1);
+
+        DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL                        ,_param->_nb_context,1);
+        DELETE1_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK                        ,_param->_nb_context,1);
+        DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE                       ,_param->_nb_context,_param->_size_event_type);
+        DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH                      ,_param->_nb_context,_param->_size_depth);
+
         DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_VAL                          ,_param->_nb_context,1);
         DELETE1_SIGNAL(out_EVENT_CONTEXT_STATE_ACK                          ,_param->_nb_context,1);
@@ -61,4 +67,6 @@
         DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL             ,_param->_nb_context,1);
         DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE                   ,_param->_nb_context,1);
+        DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE                         ,_param->_nb_context,_param->_size_event_type);
+        DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH                        ,_param->_nb_context,_param->_size_depth);
         
         DELETE1_SIGNAL(out_DEPTH_MIN                                        ,_param->_nb_context,_param->_size_depth  );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp	(revision 97)
@@ -25,27 +25,66 @@
     for (uint32_t i=0; i<_param->_nb_context; ++i)
       {
-        Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]);
+        Taddress_t    address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]);
         PORT_WRITE(out_EVENT_ADDRESS             [i],address);
         PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS [i],address);
 
-        Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]);
+        Taddress_t    address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]);
         PORT_WRITE(out_EVENT_ADDRESS_NEXT             [i],address_next);
         PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT [i],address_next);
 
-        Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]);
+        Tcontrol_t    address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]);
         PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL             [i],address_next_val);
         PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL [i],address_next_val);
 
-        Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]);
+        Tcontrol_t    is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]);
         PORT_WRITE(out_EVENT_IS_DS_TAKE             [i],is_ds_take);
         PORT_WRITE(out_EVENT_IFETCH_UNIT_IS_DS_TAKE [i],is_ds_take);
 
-        Tcontrol_t val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]);
-        PORT_WRITE(out_EVENT_VAL             [i],val);
-        PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i],val);
+        Tevent_type_t event_type = PORT_READ(in_EVENT_CONTEXT_STATE_TYPE [i]);
+        PORT_WRITE(out_EVENT_PREDICTION_UNIT_TYPE [i],event_type);
+        
+        if (_param->_have_port_depth)
+          {
+        Tdepth_t      depth = PORT_READ(in_EVENT_CONTEXT_STATE_DEPTH [i]);
+        PORT_WRITE(out_EVENT_PREDICTION_UNIT_DEPTH [i],depth);
+          }
+        
 
-        Tcontrol_t ack = (PORT_READ(in_EVENT_ACK             [i]) and
-                          PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i]));
-        PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i],ack);
+        Tcontrol_t ack                 = PORT_READ(in_EVENT_ACK                 [i]);
+        Tcontrol_t ifetch_unit_ack     = PORT_READ(in_EVENT_IFETCH_UNIT_ACK     [i]);
+        Tcontrol_t prediction_unit_ack = PORT_READ(in_EVENT_PREDICTION_UNIT_ACK [i]);
+        Tcontrol_t context_state_val   = PORT_READ(in_EVENT_CONTEXT_STATE_VAL   [i]);
+
+        Tcontrol_t val                 = (//ack                 and
+                                            ifetch_unit_ack     and
+                                            prediction_unit_ack and
+                                            context_state_val   
+                                          );
+        Tcontrol_t ifetch_unit_val     = (  ack                 and
+                                          //ifetch_unit_ack     and
+                                            prediction_unit_ack and
+                                            context_state_val   
+                                            );
+        Tcontrol_t prediction_unit_val = (  ack                 and
+                                            ifetch_unit_ack     and
+                                          //prediction_unit_ack and
+                                            context_state_val   
+                                            );
+        Tcontrol_t context_state_ack   = (  ack                 and
+                                            ifetch_unit_ack     and
+                                            prediction_unit_ack // and
+                                          //context_state_val   
+                                            );
+
+        log_printf(TRACE,Front_end_Glue,FUNCTION,"  * val                 %d, ack                 %d",val                ,ack                );
+        log_printf(TRACE,Front_end_Glue,FUNCTION,"  * ifetch_unit_val     %d, ifetch_unit_ack     %d",ifetch_unit_val    ,ifetch_unit_ack    );
+        log_printf(TRACE,Front_end_Glue,FUNCTION,"  * prediction_unit_val %d, prediction_unit_ack %d",prediction_unit_val,prediction_unit_ack);
+        log_printf(TRACE,Front_end_Glue,FUNCTION,"  * context_state_val   %d, context_state_ack   %d",context_state_val  ,context_state_ack  );
+
+
+        PORT_WRITE(out_EVENT_VAL                 [i], val                );
+        PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL     [i], ifetch_unit_val    );
+        PORT_WRITE(out_EVENT_PREDICTION_UNIT_VAL [i], prediction_unit_val);
+        PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK   [i], context_state_ack  );
 
 #ifdef DEBUG
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp	(revision 97)
@@ -94,7 +94,8 @@
   ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST          ,"out_BRANCH_EVENT_ADDRESS_DEST          ",Taddress_t         ,_param->_nb_context);
 												                         
-  ALLOC1_SC_SIGNAL( in_EVENT_STATE                    ," in_EVENT_STATE                    ",Tevent_state_t     ,_param->_nb_context);
-  ALLOC1_SC_SIGNAL( in_EVENT_TYPE                     ," in_EVENT_TYPE                     ",Tevent_type_t      ,_param->_nb_context);
-  ALLOC1_SC_SIGNAL( in_EVENT_DEPTH                    ," in_EVENT_DEPTH                    ",Tdepth_t           ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_VAL                          ," in_EVENT_VAL                          ",Tcontrol_t         ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_EVENT_ACK                          ,"out_EVENT_ACK                          ",Tcontrol_t         ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_TYPE                         ," in_EVENT_TYPE                         ",Tevent_type_t      ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_DEPTH                        ," in_EVENT_DEPTH                        ",Tdepth_t           ,_param->_nb_context);
 
   ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT                      ,"out_DEPTH_CURRENT                      ",Tdepth_t           ,_param->_nb_context);
@@ -160,5 +161,6 @@
   INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST          ,_param->_nb_context);
 
-  INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE                        ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL                          ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK                          ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE                         ,_param->_nb_context);
   if (_param->_have_port_depth)
@@ -364,5 +366,6 @@
   DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST     ,_param->_nb_context);
 
-  DELETE1_SC_SIGNAL( in_EVENT_STATE                    ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_EVENT_VAL                      ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_EVENT_ACK                      ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_TYPE                     ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_DEPTH                    ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps	(revision 97)
@@ -21,5 +21,5 @@
 
 Update_Prediction_Table_LIBRARY		= 	-lUpdate_Prediction_Table	\
-					$(Behavioural_LIBRARY)	
+					$(Behavioural_LIBRARY)
 
 Update_Prediction_Table_DIR_LIBRARY		=	-L$(Update_Prediction_Table_DIR)/lib	\
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg	(revision 95)
+++ 	(revision )
@@ -1,11 +1,0 @@
-Update_Prediction_Table
-1	1	+1	# nb_context             
-4	4	*2	# size_upt_queue         [0] [nb_context]
-1	1	+1	# size_ufpt_queue        [0] [nb_context]
-32	32	*2	# size_address           
-4	4	*4	# nb_inst_predict        
-4	4	*4	# nb_inst_decod          
-4	4	*4	# nb_inst_branch_complete
-4	4	*4	# nb_inst_update         
-0	0	+1	# size_history           
-3	3	*2	# size_ras_index         [0] [nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp	(revision 97)
@@ -42,5 +42,5 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
 #endif
 
@@ -137,5 +137,6 @@
   ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH   ,"out_UPDATE_RAS_PREDICTION_IFETCH   ",Tcontrol_t         ,_param->_nb_inst_update);
 
-  ALLOC1_SC_SIGNAL( in_EVENT_STATE                    ," in_EVENT_STATE                    ",Tevent_state_t     ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_EVENT_VAL                      ," in_EVENT_VAL                      ",Tcontrol_t         ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL(out_EVENT_ACK                      ,"out_EVENT_ACK                      ",Tcontrol_t         ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_EVENT_TYPE                     ," in_EVENT_TYPE                     ",Tevent_type_t      ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_EVENT_DEPTH                    ," in_EVENT_DEPTH                    ",Tdepth_t           ,_param->_nb_context);
@@ -230,5 +231,6 @@
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX               ,_param->_nb_inst_update);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH   ,_param->_nb_inst_update);
-  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE                    ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL                      ,_param->_nb_context);
+  INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK                      ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE                     ,_param->_nb_context);
   if (_param->_have_port_depth)
@@ -316,8 +318,6 @@
         in_UPDATE_ACK          [i]->write(0);
       for (uint32_t i=0; i<_param->_nb_context; ++i)
-        {
-        in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT);
-        in_EVENT_TYPE  [i]->write(EVENT_TYPE_NONE     );
-        }
+        in_EVENT_VAL   [i]->write(0);
+
       //---------------------------------------------------------------------
       //---------------------------------------------------------------------
@@ -932,9 +932,9 @@
          
           SC_START(1);
-          in_EVENT_STATE [context]->write(EVENT_STATE_END            );
+          in_EVENT_VAL   [context]->write(1);
           in_EVENT_TYPE  [context]->write(EVENT_TYPE_MISS_SPECULATION);
 
           SC_START(1);
-          in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT       );
+          in_EVENT_VAL   [context]->write(0);
           in_EVENT_TYPE  [context]->write(EVENT_TYPE_NONE            );
         }
@@ -1366,9 +1366,9 @@
          
           SC_START(1);
-          in_EVENT_STATE [context]->write(EVENT_STATE_END            );
+          in_EVENT_VAL   [context]->write(1);
           in_EVENT_TYPE  [context]->write(EVENT_TYPE_MISS_SPECULATION);
 
           SC_START(1);
-          in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT       );
+          in_EVENT_VAL   [context]->write(0);
           in_EVENT_TYPE  [context]->write(EVENT_TYPE_NONE            );
         }
@@ -1974,9 +1974,9 @@
             
             SC_START(1);
-            in_EVENT_STATE [context]->write(EVENT_STATE_END            );
+            in_EVENT_VAL   [context]->write(1);
             in_EVENT_TYPE  [context]->write(EVENT_TYPE_MISS_SPECULATION);
             
             SC_START(1);
-            in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT       );
+            in_EVENT_VAL   [context]->write(0);
             in_EVENT_TYPE  [context]->write(EVENT_TYPE_NONE            );
           }
@@ -2155,5 +2155,6 @@
   delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
 
-  DELETE1_SC_SIGNAL( in_EVENT_STATE                    ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_EVENT_VAL                      ,_param->_nb_context);
+  DELETE1_SC_SIGNAL(out_EVENT_ACK                      ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_TYPE                     ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_EVENT_DEPTH                    ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h	(revision 97)
@@ -52,10 +52,9 @@
   public    : Stat                           * _stat;
 
-  private   : counter_t                     ** _stat_nb_branch_hit       ; //[nb_context]
-  private   : counter_t                     ** _stat_nb_branch_miss      ; //[nb_context]
-  private   : counter_t                     ** _stat_nb_branch_unused    ; //[nb_context]
-  private   : counter_t                     ** _stat_queue_nb_cycle_empty; //[nb_context]
-  private   : counter_t                     ** _stat_queue_nb_cycle_full ; //[nb_context]
-  private   : counter_t                     ** _stat_queue_nb_elt        ; //[nb_context]
+  private   : counter_t                    *** _stat_nb_branch_hit            ; //[nb_context][MAX_BRANCH_CONDITION]
+  private   : counter_t                    *** _stat_nb_branch_miss           ; //[nb_context][MAX_BRANCH_CONDITION]
+  private   : counter_t                     ** _stat_nb_branch_unused         ; //[nb_context]
+  private   : counter_t                     ** _stat_ufpt_queue_nb_elt        ; //[nb_context]
+  private   : counter_t                     ** _stat_upt_queue_nb_elt         ; //[nb_context]
 
 #endif
@@ -143,5 +142,6 @@
 
     // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tevent_state_t     )  **  in_EVENT_STATE                    ; //[nb_context]
+  public    : SC_IN (Tcontrol_t         )  **  in_EVENT_VAL                      ; //[nb_context]
+  public    : SC_OUT(Tcontrol_t         )  ** out_EVENT_ACK                      ; //[nb_context]
   public    : SC_IN (Tevent_type_t      )  **  in_EVENT_TYPE                     ; //[nb_context]
   public    : SC_IN (Tdepth_t           )  **  in_EVENT_DEPTH                    ; //[nb_context]
@@ -197,4 +197,5 @@
   private   : Tdepth_t                      * internal_UPDATE_DEPTH                   ; //[nb_inst_update]
   private   : bool                          * internal_UPDATE_RAS                     ; //[nb_inst_update]
+  private   : Tcontrol_t                    * internal_EVENT_ACK                      ; //[nb_context]
 
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp	(revision 97)
@@ -76,5 +76,5 @@
     if (usage_is_set(_usage,USE_SYSTEMC))
       {
-
+        // Constant
 	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
 	  {
@@ -82,4 +82,9 @@
 	    PORT_WRITE(out_BRANCH_COMPLETE_ACK [i], internal_BRANCH_COMPLETE_ACK [i]);
 	  }
+        for (uint32_t i=0; i<_param->_nb_context; ++i)
+          {
+            internal_EVENT_ACK [i] = 1;
+            PORT_WRITE(out_EVENT_ACK [i], internal_EVENT_ACK [i]);
+          }
 
 	log_printf(INFO,Update_Prediction_Table,FUNCTION,"Method - transition");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp	(revision 97)
@@ -151,5 +151,6 @@
       ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context);
 
-      ALLOC1_SIGNAL_IN ( in_EVENT_STATE  ,"state",Tevent_state_t,_param->_size_event_state);
+      ALLOC1_VALACK_IN ( in_EVENT_VAL    ,VAL);
+      ALLOC1_VALACK_OUT(out_EVENT_ACK    ,ACK);
       ALLOC1_SIGNAL_IN ( in_EVENT_TYPE   ,"type" ,Tevent_type_t ,_param->_size_event_type );
       ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH  ,"depth",Tdepth_t      ,_param->_size_depth      );
@@ -183,4 +184,5 @@
     ALLOC1(internal_UPDATE_DEPTH                    ,Tdepth_t  ,_param->_nb_inst_update);
     ALLOC1(internal_UPDATE_RAS                      ,bool      ,_param->_nb_inst_update);
+    ALLOC1(internal_EVENT_ACK                       ,Tcontrol_t,_param->_nb_context);
 
     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp	(revision 97)
@@ -111,5 +111,6 @@
 
         // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-        DELETE1_SIGNAL( in_EVENT_STATE  ,_param->_nb_context,_param->_size_event_state);
+        DELETE1_SIGNAL( in_EVENT_VAL    ,_param->_nb_context,1);
+        DELETE1_SIGNAL(out_EVENT_ACK    ,_param->_nb_context,1);
         DELETE1_SIGNAL( in_EVENT_TYPE   ,_param->_nb_context,_param->_size_event_type );
         DELETE1_SIGNAL( in_EVENT_DEPTH  ,_param->_nb_context,_param->_size_depth      );
@@ -137,4 +138,5 @@
         DELETE1(internal_UPDATE_DEPTH                    ,_param->_nb_inst_update);
         DELETE1(internal_UPDATE_RAS                      ,_param->_nb_inst_update);
+        DELETE1(internal_EVENT_ACK                       ,_param->_nb_context);
         
         // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp	(revision 97)
@@ -67,6 +67,6 @@
               if (take != 1)
                 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str()));
-              if (addr_dest != addr_good)
-                throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
+//               if (addr_dest != addr_good)
+//                 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
 #endif
 
@@ -85,6 +85,6 @@
 
 #ifdef DEBUG_TEST
-              if (addr_dest != addr_good)
-                throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
+//               if (addr_dest != addr_good)
+//                 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
 #endif
 
@@ -103,6 +103,6 @@
 
 #ifdef DEBUG_TEST
-              if (addr_dest != addr_good)
-                throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
+//               if (addr_dest != addr_good)
+//                 throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str()));
 #endif
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp	(revision 97)
@@ -8,4 +8,6 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
+#include "Behavioural/include/Allocation.h"
+
 
 namespace morpheo {
@@ -28,21 +30,76 @@
 		      param_statistics);
 
-//     _stat_nb_branch_hit        = new counter_t * [_param->_nb_context];
-//     _stat_nb_branch_miss       = new counter_t * [_param->_nb_context];
-//     _stat_nb_branch_unused     = new counter_t * [_param->_nb_context];
-//     _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context];
-//     _stat_queue_nb_cycle_full  = new counter_t * [_param->_nb_context];
-//     _stat_queue_nb_elt         = new counter_t * [_param->_nb_context];
-  
-//     for (uint32_t i=0; i<_param->_nb_context; ++i)
-//       {
-//         _stat_nb_branch_hit        [i] = _stat->create_counter("nb_branch_hit_"       +toString(i),"",toString(_("Branch hit speculation (context %d)"),i));
-//         _stat_nb_branch_miss       [i] = _stat->create_counter("nb_branch_miss_"      +toString(i),"",toString(_("Branch miss speculation (context %d)"),i));
-//         _stat_nb_branch_unused     [i] = _stat->create_counter("nb_branch_unused_"    +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i));
-//         _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i));
-//         _stat_queue_nb_cycle_full  [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i));
-//         _stat_queue_nb_elt         [i] = _stat->create_counter("queue_nb_elt_"        +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i));
-//       }
-    
+    {
+      ALLOC2(_stat_nb_branch_hit        ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION);
+      ALLOC2(_stat_nb_branch_miss       ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION);
+      ALLOC1(_stat_nb_branch_unused     ,counter_t *,_param->_nb_context);
+      
+      for (uint32_t i=0; i<_param->_nb_context; ++i)
+        {
+          std::string sum_miss        = "0";
+          std::string sum_branchement = "0";
+
+          for (uint32_t j=0; j<MAX_BRANCH_CONDITION; ++j)
+            if (is_branch_condition_valid(j))
+              {
+                std::string nb_miss        = "nb_branch_miss_"+toString(i)+"_"+toString(j); 
+                std::string nb_branchement = "+ nb_branch_hit_"+toString(i)+"_"+toString(j)+" nb_branch_miss_"+toString(i)+"_"+toString(j);
+                _stat_nb_branch_hit  [i][j] = _stat->create_counter("nb_branch_hit_" +toString(i)+"_"+toString(j),"",toString(_("Branch hit  speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i));
+                _stat_nb_branch_miss [i][j] = _stat->create_counter(nb_miss,"",toString(_("Branch miss speculation, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i));
+
+//                 _stat->create_expr_average("average_miss_"+toString(i)+"_"+toString(j),
+//                                            "nb_branch_miss_"+toString(i)+"_"+toString(j),
+//                                            nb_branchement,
+//                                            "miss/branchement",
+//                                            toString(_("Average miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i));
+
+                _stat->create_expr_percent("percent_miss_"+toString(i)+"_"+toString(j),
+                                           nb_miss,
+                                           nb_branchement,
+                                           toString(_("Percent miss by branchement, branch condition : %s (context %d)"),toString(static_cast<branch_condition_t>(j)).c_str(),i));
+
+                sum_miss        = "+ "+nb_miss       +" "+ sum_miss;
+                sum_branchement = "+ "+nb_branchement+" "+sum_branchement;
+              }
+
+//           _stat->create_expr_average("average_miss_"+toString(i),
+//                                      sum_miss,
+//                                      sum_branchement,
+//                                      "miss/branchement",
+//                                      toString(_("Average miss by branchement (context %d)"),i));
+
+          _stat->create_expr_percent("percent_miss_"+toString(i),
+                                     sum_miss,
+                                     sum_branchement,
+                                     toString(_("Percent miss by branchement (context %d)"),i));
+          
+          _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused (previous speculation) (context %d)"),i));
+        }
+    }
+
+    {
+      ALLOC1(_stat_ufpt_queue_nb_elt        ,counter_t *,_param->_nb_context);
+     
+      for (uint32_t i=0; i<_param->_nb_context; ++i)
+        {
+          _stat_ufpt_queue_nb_elt         [i] = _stat->create_counter("ufpt_queue_nb_elt_"+toString(i),"",toString(_("Branchement in Update Fetch Prediction Table (context %d)"),i));
+          
+          _stat->create_expr_average_by_cycle("average_occupation_ufpt_queue_"+toString(i),"ufpt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Fetch Prediction Table (context %d)"),i));
+          _stat->create_expr_percent         ("percent_occupation_ufpt_queue_"+toString(i), "average_occupation_ufpt_queue_"+toString(i), toString(_param->_size_ufpt_queue[i]), toString(_("Percent occupation of Update Fetch Prediction Table (context %d)"),i));
+        }
+    }
+
+    {
+      ALLOC1(_stat_upt_queue_nb_elt        ,counter_t *,_param->_nb_context);
+     
+      for (uint32_t i=0; i<_param->_nb_context; ++i)
+        {
+          _stat_upt_queue_nb_elt         [i] = _stat->create_counter("upt_queue_nb_elt_"+toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i));
+          
+          _stat->create_expr_average_by_cycle("average_occupation_upt_queue_"+toString(i),"upt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Prediction Table (context %d)"),i));
+          _stat->create_expr_percent         ("percent_occupation_upt_queue_"+toString(i), "average_occupation_upt_queue_"+toString(i), toString(_param->_size_upt_queue[i]), toString(_("Percent occupation of Update Prediction Table (context %d)"),i));
+        }
+    }
+
     log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End");
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp	(revision 97)
@@ -8,4 +8,5 @@
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
+#include "Behavioural/include/Allocation.h"
 
 namespace morpheo {
@@ -27,10 +28,10 @@
     
     delete    _stat;
-//     delete [] _stat_nb_branch_hit       ;
-//     delete [] _stat_nb_branch_miss      ;
-//     delete [] _stat_nb_branch_unused    ;
-//     delete [] _stat_queue_nb_cycle_empty;
-//     delete [] _stat_queue_nb_cycle_full ;
-//     delete [] _stat_queue_nb_elt        ;
+
+    DELETE2(_stat_nb_branch_hit            ,_param->_nb_context,MAX_BRANCH_CONDITION);
+    DELETE2(_stat_nb_branch_miss           ,_param->_nb_context,MAX_BRANCH_CONDITION);
+    DELETE1(_stat_nb_branch_unused         ,_param->_nb_context);
+    DELETE1(_stat_ufpt_queue_nb_elt        ,_param->_nb_context);
+    DELETE1(_stat_upt_queue_nb_elt         ,_param->_nb_context);
     
     log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp	(revision 97)
@@ -472,4 +472,8 @@
 //                    bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or
 //                                       (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT));
+#ifdef STATISTICS
+                      Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
+                      bool ok     = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
+#endif
                       bool ko     = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
 
@@ -480,4 +484,9 @@
                           
                           reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
+
+#ifdef STATISTICS
+                          if (usage_is_set(_usage,USE_STATISTICS))
+                            (*_stat_nb_branch_miss [context][condition])++;
+#endif
                         }
                       else
@@ -486,4 +495,15 @@
                           
                           reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK;
+
+
+#ifdef STATISTICS
+                          if (usage_is_set(_usage,USE_STATISTICS))
+                            {
+                              if (ok)
+                                (*_stat_nb_branch_hit    [context][condition]) ++;
+                              else
+                                (*_stat_nb_branch_unused [context]) ++;
+                            }
+#endif
                         }
                       
@@ -548,48 +568,38 @@
 	// ===================================================================
         for (uint32_t i=0; i<_param->_nb_context; ++i)
-          {
-            //----------------------------------------------------------------
-            // Cases
-            //----------------------------------------------------------------
-            //   * EVENT_TYPE_NONE               - nothing
-            //   * EVENT_TYPE_MISS_SPECULATION   
-            //     * EVENT_STATE_END             - Change state, reset pointer
-            //   * EVENT_TYPE_EXCEPTION          - 
-            //     * EVENT_STATE_EVENT           - Flush upft and upt
-            //     * EVENT_STATE_END             - Change state, reset pointer
-            //   * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
-            //   * EVENT_TYPE_SPR_ACCESS         - nothing
-            //   * EVENT_TYPE_MSYNC              - nothing
-            //   * EVENT_TYPE_PSYNC              - nothing
-            //   * EVENT_TYPE_CSYNC              - nothing
-
-            Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]);
-            Tevent_type_t  event_type  = PORT_READ(in_EVENT_TYPE  [i]);
-//             Tdepth_t       depth       = PORT_READ(in_EVENT_DEPTH [i]);
+          if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
+            {
+              //----------------------------------------------------------------
+              // Cases
+              //----------------------------------------------------------------
+              //   * EVENT_TYPE_NONE               - nothing
+              //   * EVENT_TYPE_MISS_SPECULATION   - Change state, reset pointer
+              //   * EVENT_TYPE_EXCEPTION          - Flush upft and upt, Change state, reset pointer
+              //   * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
+              //   * EVENT_TYPE_SPR_ACCESS         - nothing
+              //   * EVENT_TYPE_MSYNC              - nothing
+              //   * EVENT_TYPE_PSYNC              - nothing
+              //   * EVENT_TYPE_CSYNC              - nothing
+              
+              Tevent_type_t  event_type  = PORT_READ(in_EVENT_TYPE  [i]);
+//            Tdepth_t       depth       = PORT_READ(in_EVENT_DEPTH [i]);
             
-            // Test if end of miss
-            if ((event_state == EVENT_STATE_END) and
-                (event_type  == EVENT_TYPE_MISS_SPECULATION))
-              {
-                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * EVENT");
-                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * state : EVENT_STATE_END");
-                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * type  : EVENT_TYPE_MISS_SPECULATION");
-
-#ifdef DEBUG_TEST
-                if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
-                  throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
-#endif
-                
-                // Change state
-                log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_OK (event)",i);
-                
-                reg_EVENT_STATE [i] = EVENT_STATE_OK;
-
-//                 uint32_t bottom = reg_UPT_BOTTOM [i];
-
-//                 reg_UPT_TOP    [i] = bottom;
-//                 reg_UPT_UPDATE [i] = bottom;
-              }
-          }
+              // Test if end of miss
+              if (event_type  == EVENT_TYPE_MISS_SPECULATION)
+                {
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"  * EVENT");
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * type  : EVENT_TYPE_MISS_SPECULATION");
+                  
+#ifdef DEBUG_TEST
+                  if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT)
+                    throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state."));
+#endif
+                  
+                  // Change state
+                  log_printf(TRACE,Update_Prediction_Table,FUNCTION,"    * EVENT [%d] <- EVENT_STATE_OK (event)",i);
+                  
+                  reg_EVENT_STATE [i] = EVENT_STATE_OK;
+                }
+            }
 
  	// ===================================================================
@@ -634,4 +644,17 @@
           }
 
+#ifdef STATISTICS
+        if (usage_is_set(_usage,USE_STATISTICS))
+          for (uint32_t i=0; i<_param->_nb_context; i++)
+            {
+              for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
+                if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
+                  (*_stat_ufpt_queue_nb_elt [i]) ++;
+              for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
+                if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
+                  (*_stat_upt_queue_nb_elt [i]) ++;
+            }
+#endif
+        
  	// ===================================================================
 	// =====[ PRINT ]=====================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h	(revision 97)
@@ -115,5 +115,6 @@
 
     // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-  public    : SC_IN (Tevent_state_t     )  **  in_EVENT_STATE                    ; //[nb_context]
+  public    : SC_IN (Tcontrol_t         )  **  in_EVENT_VAL                      ; //[nb_context]
+  public    : SC_OUT(Tcontrol_t         )  ** out_EVENT_ACK                      ; //[nb_context]
   public    : SC_IN (Tevent_type_t      )  **  in_EVENT_TYPE                     ; //[nb_context]
   public    : SC_IN (Tdepth_t           )  **  in_EVENT_DEPTH                    ; //[nb_context]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp	(revision 97)
@@ -136,5 +136,6 @@
       ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context);
 
-      ALLOC1_SIGNAL_IN ( in_EVENT_STATE  ,"state",Tevent_state_t,_param->_size_event_state);
+      ALLOC1_VALACK_IN ( in_EVENT_VAL    ,VAL);
+      ALLOC1_VALACK_OUT(out_EVENT_ACK    ,ACK);
       ALLOC1_SIGNAL_IN ( in_EVENT_TYPE   ,"type" ,Tevent_type_t ,_param->_size_event_type );
       ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH  ,"depth",Tdepth_t      ,_param->_size_depth      );
@@ -711,5 +712,6 @@
 #endif
 
-	  PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE");
+	  PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_VAL"  ,dest, "in_EVENT_"+toString(i)+"_VAL"  );
+	  PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ACK"  ,dest,"out_EVENT_"+toString(i)+"_ACK"  );
 	  PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" );
 	  if (_param->_have_port_depth)
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp	(revision 97)
@@ -71,5 +71,6 @@
         DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST     ,_param->_nb_context,_param->_size_instruction_address);
 
-        DELETE1_SIGNAL( in_EVENT_STATE  ,_param->_nb_context,_param->_size_event_state);
+        DELETE1_SIGNAL( in_EVENT_VAL    ,_param->_nb_context,1);
+        DELETE1_SIGNAL(out_EVENT_ACK    ,_param->_nb_context,1);
         DELETE1_SIGNAL( in_EVENT_TYPE   ,_param->_nb_context,_param->_size_event_type );
         DELETE1_SIGNAL( in_EVENT_DEPTH  ,_param->_nb_context,_param->_size_depth      );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp	(revision 97)
@@ -99,5 +99,5 @@
   ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR      ," in_COMMIT_EVENT_ADDRESS_EPCR      ",Taddress_t           );
   ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL  ",Tcontrol_t           );
-  ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR      ," in_COMMIT_EVENT_ADDRESS_EEAR      ",Taddress_t           );
+  ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR      ," in_COMMIT_EVENT_ADDRESS_EEAR      ",Tgeneral_data_t      );
   ALLOC1_SC_SIGNAL(out_EVENT_VAL                      ,"out_EVENT_VAL                      ",Tcontrol_t           ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_EVENT_ACK                      ," in_EVENT_ACK                      ",Tcontrol_t           ,_param->_nb_context);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp	(revision 95)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp	(revision 97)
@@ -140,5 +140,5 @@
       ALLOC_SIGNAL_IN   ( in_COMMIT_EVENT_ADDRESS_EPCR        ,"ADDRESS_EPCR"     ,Taddress_t           ,_param->_size_instruction_address   );
       ALLOC_SIGNAL_IN   ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL    ,"ADDRESS_EEAR_VAL" ,Tcontrol_t           ,1                       );
-      ALLOC_SIGNAL_IN   ( in_COMMIT_EVENT_ADDRESS_EEAR        ,"ADDRESS_EEAR"     ,Taddress_t           ,_param->_size_instruction_address   );
+      ALLOC_SIGNAL_IN   ( in_COMMIT_EVENT_ADDRESS_EEAR        ,"ADDRESS_EEAR"     ,Tgeneral_data_t      ,_param->_size_general_data          );
     }
 
@@ -580,4 +580,23 @@
           COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST"    ,
                                    dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST"    );
+        }
+
+      // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+      for (uint32_t i=0; i<_param->_nb_context; ++i)
+        {
+          dest = _name+"_glue";
+#ifdef POSITION
+          _component->interface_map (src ,"event_"+toString(i),
+                                     dest,"event_"+toString(i));
+#endif
+          COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+                "_VAL"  ,
+                                   dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_VAL"  );
+          COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+                "_ACK"  ,
+                                   dest, "in_EVENT_"+toString(i)+"_PREDICTION_UNIT_ACK"  );
+          COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+                "_TYPE" ,
+                                   dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_TYPE" );
+          if (_param->_have_port_depth)
+          COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+                "_DEPTH",
+                                   dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_DEPTH");
         }
 
@@ -967,4 +986,9 @@
           COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+              "_IS_DS_TAKE"      ,
                                    dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_IS_DS_TAKE"      );
+          COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+              "_TYPE"            ,
+                                   dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_TYPE"            );
+          if (_param->_have_port_depth)
+          COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+              "_DEPTH"           ,
+                                   dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_DEPTH"           );
         }
 
@@ -1129,13 +1153,19 @@
       //   in_EVENT_IFETCH_UNIT_ACK                             - component_ifetch_unit
       //  out_EVENT_IFETCH_UNIT_ADDRESS                         - component_ifetch_unit
-      //   in_EVENT_IFETCH_UNIT_ADDRESS_NEXT                    - component_ifetch_unit
+      //  out_EVENT_IFETCH_UNIT_ADDRESS_NEXT                    - component_ifetch_unit
       //  out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL                - component_ifetch_unit
       //   in_EVENT_IFETCH_UNIT_IS_DS_TAKE                      - component_ifetch_unit
+      //  out_EVENT_PREDICTION_UNIT_VAL                         - component_prediction_unit
+      //   in_EVENT_PREDICTION_UNIT_ACK                         - component_prediction_unit
+      //  out_EVENT_PREDICTION_UNIT_TYPE                        - component_prediction_unit
+      //  out_EVENT_PREDICTION_UNIT_DEPTH                       - component_prediction_unit
       //   in_EVENT_CONTEXT_STATE_VAL                           - component_context_state
       //  out_EVENT_CONTEXT_STATE_ACK                           - component_context_state
       //   in_EVENT_CONTEXT_STATE_ADDRESS                       - component_context_state
       //   in_EVENT_CONTEXT_STATE_ADDRESS_NEXT                  - component_context_state
-      //  out_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL              - component_context_state
+      //   in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL              - component_context_state
       //   in_EVENT_CONTEXT_STATE_IS_DS_TAKE                    - component_context_state
+      //   in_EVENT_CONTEXT_STATE_TYPE                          - component_context_state
+      //   in_EVENT_CONTEXT_STATE_DEPTH                         - component_context_state
 
       // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	      
