Changeset 97 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src

Timestamp:

Dec 19, 2008, 4:34:00 PM (16 years ago)

Author:

rosiere

Message:

1) Update Prediction Table : statistics
2) Size instruction address on 30 bits
3) Change Log File
4) Add debug_level in simulation configuration file

Location:

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src

Files:

• Parameters.cpp (modified) (1 diff)
• Rename_select_allocation.cpp (modified) (4 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp

@@ -50 +50 @@
     if (is_toplevel)
       {
-        _size_general_data     = size_general_data    ;
-        _size_depth            = log2(max_branch_speculated);
-        _size_front_end_id     = log2(_nb_front_end);
-        _size_context_id       = log2(max<uint32_t>(_nb_context,_nb_front_end));
-        
-        _have_port_front_end_id= _size_front_end_id > 0;
-        _have_port_context_id  = _size_context_id   > 0;
-        _have_port_depth       = _size_depth        > 0;
+        _size_instruction_address = size_general_data-2;
+        _size_general_data        = size_general_data    ;
+        _size_depth               = log2(max_branch_speculated);
+        _size_front_end_id        = log2(_nb_front_end);
+        _size_context_id          = log2(max<uint32_t>(_nb_context,_nb_front_end));
+                                  
+        _have_port_front_end_id   = _size_front_end_id > 0;
+        _have_port_context_id     = _size_context_id   > 0;
+        _have_port_depth          = _size_depth        > 0;
         
         copy();

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp

@@ -69 +69 @@
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE    ,"no_execute"   ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
-      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS       ,"address"      ,Tgeneral_data_t   ,_param->_size_general_data          , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS       ,"address"      ,Taddress_t        ,_param->_size_instruction_address   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT  ,"has_immediat" ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT      ,"immediat"     ,Tgeneral_data_t   ,_param->_size_general_data          , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
@@ -82 +82 @@
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE      ,"write_re"     ,Tcontrol_t        ,1                                   , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE    ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]);
-      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t      ,_param->_size_exception             , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
+      _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t      ,_param->_size_exception_use         , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
       _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION     ,"exception"    ,Texception_t      ,_param->_size_exception             , _param->_nb_front_end, _param->_nb_inst_decod[it1]);
     }
@@ -99 +99 @@
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE    ,"no_execute"   ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t        ,1                                   );
-      ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS       ,"address"      ,Tgeneral_data_t   ,_param->_size_general_data          );
+      ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS       ,"address"      ,Taddress_t        ,_param->_size_instruction_address   );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT  ,"has_immediat" ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IMMEDIAT      ,"immediat"     ,Tgeneral_data_t   ,_param->_size_general_data          );
@@ -112 +112 @@
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_WRITE_RE      ,"write_re"     ,Tcontrol_t        ,1                                   );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE    ,"num_reg_re"   ,Tspecial_address_t,_param->_size_special_register_logic);
-      ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t      ,_param->_size_exception             );
+      ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t      ,_param->_size_exception_use         );
       ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION     ,"exception"    ,Texception_t      ,_param->_size_exception             );
     }