Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/SelfTest/src/test.cpp (revision 97) @@ -10,7 +10,10 @@ #include "Behavioural/Custom/include/Custom_default.h" #include "Behavioural/Custom/include/Custom_example.h" +#include "Common/include/Time.h" void test (string name) { + Time * timing = new Time (false); + morpheo::behavioural::custom::custom_information_t (*_get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information); @@ -81,5 +84,4 @@ delete generator1; delete simulator1; - - + delete timing; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Configuration.h (revision 97) @@ -46,4 +46,5 @@ public : ~Configuration (); + public : std::string header (void); public : std::string getName (void); public : Tusage_t getUsage (void); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/include/Parameters.h (revision 97) @@ -30,4 +30,5 @@ public : uint32_t * _ras_size_queue ;//[nb_thread] public : uint32_t * _upt_size_queue ;//[nb_thread] + public : uint32_t * _ufpt_size_queue ;//[nb_thread] // Decod bloc Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration.cpp (revision 97) @@ -23,19 +23,25 @@ log_begin(Configuration,FUNCTION); + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Simulator configuration + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + _simulator = new Simulator (filename_simulator); - _generator = new Generator (filename_generator); - _instance = new Instance (filename_instance , - _generator, - get_custom_information); //-------------------------------------------------- - // Name + // Directory //-------------------------------------------------- - _name = _instance->getName(); + directory_init (_simulator->getParam("directory_statistics"), + _simulator->getParam("directory_vhdl" ), + _simulator->getParam("directory_position" ), + _simulator->getParam("directory_log" )); //-------------------------------------------------- - // Parameters + // Debug & Log File //-------------------------------------------------- - _param = _instance->_param; + debug_init (fromString(_simulator->getParam("debug_level"))); + + log_init(fromString(_simulator->getParam("debug_have_log_file")), + MORPHEO_LOG); //-------------------------------------------------- @@ -64,4 +70,11 @@ //-------------------------------------------------- + // Header + //-------------------------------------------------- + + if (usage_is_set(_usage,USE_HEADER)) + std::cout << header(); + + //-------------------------------------------------- // Parameters_Statistics //-------------------------------------------------- @@ -75,11 +88,24 @@ fromString(_simulator->getParam("simulation_nb_instruction"))); + + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + // Generator configuration + Instance + //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + _generator = new Generator (filename_generator); + _instance = new Instance (filename_instance , + _generator, + get_custom_information); + //-------------------------------------------------- - // Directory + // Name //-------------------------------------------------- - directory_init (_simulator->getParam("directory_statistics"), - _simulator->getParam("directory_vhdl" ), - _simulator->getParam("directory_position" ), - _simulator->getParam("directory_log" )); + _name = _instance->getName(); + + //-------------------------------------------------- + // Parameters + //-------------------------------------------------- + _param = _instance->_param; + log_end(Configuration,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 97) @@ -0,0 +1,70 @@ +/* + * $Id$ + * + * [ Description ] + * + */ + +#include "Behavioural/Configuration/include/Configuration.h" +#include "Behavioural/include/Version.h" + +namespace morpheo { +namespace behavioural { +namespace configuration { + +#undef FUNCTION +#define FUNCTION "Configuration::header" +std::string Configuration::header (void) + { + log_begin(Configuration,FUNCTION); + + std::string str = ""; + + /* + _ + | | + _ __ ___ ___ _ __ _ __ | |__ ___ ___ + | '_ ` _ \ / _ \| '__| '_ \| '_ \ / _ \/ _ \ + | | | | | | (_) | | | |_) | | | | __/ (_) | + |_| |_| |_|\___/|_| | .__/|_| |_|\___|\___/ + | | + |_| + __ + /\ \ + ___ ___ ___ _ __ _____\ \ \___ __ ___ + /' __` __`\ / __`\/\`'__\/\ '__`\ \ _ `\ /'__`\ / __`\ + /\ \/\ \/\ \/\ \L\ \ \ \/ \ \ \L\ \ \ \ \ \/\ __//\ \L\ \ + \ \_\ \_\ \_\ \____/\ \_\ \ \ ,__/\ \_\ \_\ \____\ \____/ + \/_/\/_/\/_/\/___/ \/_/ \ \ \/ \/_/\/_/\/____/\/___/ + \ \_\ + \/_/ + +*/ + + str += toString(MSG_INFORMATION)+" __ \n"; + str += toString(MSG_INFORMATION)+" /\\ \\ \n"; + str += toString(MSG_INFORMATION)+" ___ ___ ___ _ __ _____\\ \\ \\___ __ ___ \n"; + str += toString(MSG_INFORMATION)+" /' __` __`\\ / __`\\/\\`'__\\/\\ '__`\\ \\ _ `\\ /'__`\\ / __`\\ \n"; + str += toString(MSG_INFORMATION)+" /\\ \\/\\ \\/\\ \\/\\ \\L\\ \\ \\ \\/ \\ \\ \\L\\ \\ \\ \\ \\ \\/\\ __//\\ \\L\\ \\\n"; + str += toString(MSG_INFORMATION)+" \\ \\_\\ \\_\\ \\_\\ \\____/\\ \\_\\ \\ \\ ,__/\\ \\_\\ \\_\\ \\____\\ \\____/\n"; + str += toString(MSG_INFORMATION)+" \\/_/\\/_/\\/_/\\/___/ \\/_/ \\ \\ \\/ \\/_/\\/_/\\/____/\\/___/ \n"; + str += toString(MSG_INFORMATION)+" \\ \\_\\ \n"; + str += toString(MSG_INFORMATION)+" \\/_/ \n"; + str += toString(MSG_INFORMATION)+"\n"; + str += toString(MSG_INFORMATION)+_(" * Multiple ORganization of a Processor with HEterogeneous and Open architecture\n"); + str += toString(MSG_INFORMATION)+_(" * Version : ")+toString(MORPHEO_HEADER)+"\n"; + str += toString(MSG_INFORMATION)+_(" * Last change : ")+toString(MORPHEO_DATE )+"\n"; + str += toString(MSG_INFORMATION)+_(" * E-mail support : mathieu.rosiere@lip6.fr\n" ); + str += toString(MSG_INFORMATION)+_(" * Original author(s) : Mathieu Rosière\n" ); + str += toString(MSG_INFORMATION)+_(" * Contributor(s) : Stéphane Dubuisson - XMLLight\n"); + str += toString(MSG_INFORMATION)+_(" Vincent Moulu - VHDL\n" ); + str += toString(MSG_INFORMATION)+"\n"; + + log_end(Configuration,FUNCTION); + + return str; + }; + +}; // end namespace configuration +}; // end namespace behavioural +}; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance.cpp (revision 97) @@ -164,4 +164,5 @@ DELETE1(_param->_nb_inst_decod ,_param->_nb_decod_bloc); DELETE1(_param->_size_decod_queue ,_param->_nb_decod_bloc); + DELETE1(_param->_ufpt_size_queue ,_param->_nb_thread); DELETE1(_param->_upt_size_queue ,_param->_nb_thread); DELETE1(_param->_ras_size_queue ,_param->_nb_thread); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_fromInternalStructure.cpp (revision 97) @@ -21,5 +21,5 @@ // Common //----------------------------------------------------- - log_printf(INFO,Configuration,FUNCTION,_("COMMON")); + //log_printf(INFO,Configuration,FUNCTION,_("COMMON")); _param->_size_general_data = fromString(getParam("size_data" , "")); @@ -46,8 +46,9 @@ ALLOC1(_param->_ras_size_queue ,uint32_t,_param->_nb_thread); ALLOC1(_param->_upt_size_queue ,uint32_t,_param->_nb_thread); + ALLOC1(_param->_ufpt_size_queue ,uint32_t,_param->_nb_thread); for (uint32_t i=0; i<_param->_nb_thread; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("THREAD [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("THREAD [%d]"),i); _param->_size_ifetch_queue [i] = fromString(getParam("size_ifetch_queue", "thread",toString(i).c_str(),"")); @@ -55,4 +56,5 @@ _param->_ras_size_queue [i] = fromString(getParam("ras_size_queue" , "thread",toString(i).c_str(),"")); _param->_upt_size_queue [i] = fromString(getParam("upt_size_queue" , "thread",toString(i).c_str(),"")); + _param->_ufpt_size_queue [i] = fromString(getParam("ufpt_size_queue" , "thread",toString(i).c_str(),"")); // just read !!! @@ -85,5 +87,5 @@ for (uint32_t i=0; i<_param->_nb_decod_bloc; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("DECOD_BLOC [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("DECOD_BLOC [%d]"),i); _param->_size_decod_queue [i] = fromString (getParam("size_decod_queue" , "decod_bloc",toString(i).c_str(),"")); @@ -111,5 +113,5 @@ for (uint32_t i=0; i<_param->_nb_rename_bloc; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("RENAME_BLOC [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("RENAME_BLOC [%d]"),i); _param->_nb_inst_insert [i] = fromString (getParam("nb_inst_insert" , "rename_bloc",toString(i).c_str(),"")); @@ -134,5 +136,5 @@ for (uint32_t i=0; i<_param->_nb_read_bloc; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("READ_BLOC [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("READ_BLOC [%d]"),i); _param->_size_read_queue [i] = fromString (getParam("size_read_queue" ,"read_bloc",toString(i).c_str(),"")); @@ -150,5 +152,5 @@ for (uint32_t i=0; i<_param->_nb_write_bloc; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("WRITE_BLOC [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("WRITE_BLOC [%d]"),i); _param->_size_write_queue [i] = fromString (getParam("size_write_queue" ,"write_bloc",toString(i).c_str(),"")); @@ -171,5 +173,5 @@ for (uint32_t i=0; i<_param->_nb_load_store_unit; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("LOAD_STORE_UNIT [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("LOAD_STORE_UNIT [%d]"),i); _param->_size_store_queue [i] = fromString (getParam("size_store_queue" ,"load_store_unit",toString(i).c_str(),"")); @@ -192,5 +194,5 @@ for (uint32_t i=0; i<_param->_nb_functionnal_unit; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("FUNCTIONNAL_UNIT [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("FUNCTIONNAL_UNIT [%d]"),i); _param->_nb_inst_functionnal_unit [i] = fromString (getParam("nb_inst_functionnal_unit","functionnal_unit",toString(i).c_str(),"")); @@ -243,5 +245,5 @@ //----------------------------------------------------- - log_printf(INFO,Configuration,FUNCTION,_("ICACHE_PORT")); + //log_printf(INFO,Configuration,FUNCTION,_("ICACHE_PORT")); _param->_nb_icache_port = fromString(getParam("nb_icache_port" , "")); @@ -252,5 +254,5 @@ // dcache_port //----------------------------------------------------- - log_printf(INFO,Configuration,FUNCTION,_("DCACHE_PORT")); + //log_printf(INFO,Configuration,FUNCTION,_("DCACHE_PORT")); _param->_nb_dcache_port = fromString(getParam("nb_dcache_port" , "")); @@ -282,5 +284,5 @@ for (uint32_t i=0; i<_param->_nb_front_end; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("FRONT_END [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("FRONT_END [%d]"),i); _param->_nb_context [i] = fromString(getParam("nb_context" ,"front_end",toString(i).c_str(), "")); @@ -306,5 +308,5 @@ for (uint32_t j=0; j<3; ++j) { - log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j); + //log_printf(INFO,Configuration,FUNCTION,_("PREDICTOR [%d][%d]"),i,j); _param->_dir_have_bht [i][j] = fromString(getParam("dir_have_bht" ,"front_end",toString(i).c_str(),"predictor",toString(j).c_str(), "")); @@ -343,5 +345,5 @@ for (uint32_t i=0; i<_param->_nb_ooo_engine; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("OOO_ENGINE [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("OOO_ENGINE [%d]"),i); _param->_nb_rename_unit [i] = fromString(getParam("nb_rename_unit" ,"ooo_engine",toString(i).c_str(), "")); @@ -383,5 +385,5 @@ for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) { - log_printf(INFO,Configuration,FUNCTION,_("EXECUTE_LOOP [%d]"),i); + //log_printf(INFO,Configuration,FUNCTION,_("EXECUTE_LOOP [%d]"),i); _param->_nb_read_unit [i] = fromString(getParam("nb_read_unit" ,"execute_loop",toString(i).c_str(), "")); @@ -402,5 +404,5 @@ //----------------------------------------------------- - log_printf(INFO,Configuration,FUNCTION,_("LINK")); + //log_printf(INFO,Configuration,FUNCTION,_("LINK")); _param->_dispatch_priority = fromString(getParam("dispatch_priority" , "")); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getLink.cpp (revision 97) @@ -74,10 +74,10 @@ { _return = link2array(dest); - log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\"= %s."),name,src.c_str(),dest.c_str()); + //log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\"= %s."),name,src.c_str(),dest.c_str()); } else { _return.clear(); - log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\" not find."),name,src.c_str()); + //log_printf(INFO,Configuration,FUNCTION,_("Link \"%s[%s]\" not find."),name,src.c_str()); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Instance_getParam.cpp (revision 97) @@ -48,5 +48,5 @@ if (it == ((*list_components)[component]).end()) { - log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is not define, take default value for parameter \"%s\"."),component.c_str(),id.c_str(),name); + //log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is not define, take default value for parameter \"%s\"."),component.c_str(),id.c_str(),name); value = _generator->getParam(name)->_default; @@ -68,5 +68,5 @@ if (it == (*list_parameters).end()) { - log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is define, but parameter \"%s\" is not define. Take default value."),component.c_str(),id.c_str(),name); + //log_printf(INFO,Configuration,FUNCTION,_("Component \"%s[%s]\" is define, but parameter \"%s\" is not define. Take default value."),component.c_str(),id.c_str(),name); value = _generator->getParam(name)->_default; @@ -85,5 +85,5 @@ } - log_printf(INFO,Configuration,FUNCTION,_("Parameters \"%s\" = %s."),name,value.c_str()); + //log_printf(INFO,Configuration,FUNCTION,_("Parameters \"%s\" = %s."),name,value.c_str()); log_end(Configuration,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 97) @@ -74,5 +74,5 @@ ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ",Taddress_t ,_param->_nb_front_end); ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_front_end); - ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ",Taddress_t ,_param->_nb_front_end); + ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ",Tgeneral_data_t ,_param->_nb_front_end); ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_VAL ," in_COMMIT_EVENT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_OOO_ENGINE_ACK ,"out_COMMIT_EVENT_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine); @@ -85,5 +85,5 @@ ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine); ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine); - ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",Taddress_t ,_param->_nb_ooo_engine); + ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ," in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ",Tgeneral_data_t ,_param->_nb_ooo_engine); ALLOC2_SC_SIGNAL( in_ISSUE_OOO_ENGINE_VAL ," in_ISSUE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); ALLOC2_SC_SIGNAL(out_ISSUE_OOO_ENGINE_ACK ,"out_ISSUE_OOO_ENGINE_ACK ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_issue[it1]); @@ -139,5 +139,5 @@ ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"out_EXECUTE_OOO_ENGINE_EXCEPTION ",Texception_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); - ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,"out_EXECUTE_OOO_ENGINE_ADDRESS ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_ADDRESS ,"out_EXECUTE_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); ALLOC3_SC_SIGNAL(out_EXECUTE_OOO_ENGINE_DATA ,"out_EXECUTE_OOO_ENGINE_DATA ",Tgeneral_data_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_VAL ," in_EXECUTE_EXECUTE_LOOP_VAL ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); @@ -152,5 +152,5 @@ ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); - ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_EXECUTE_LOOP_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_EXECUTE_LOOP_ADDRESS ",Taddress_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_EXECUTE_LOOP_DATA ," in_EXECUTE_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); ALLOC2_SC_SIGNAL( in_INSERT_OOO_ENGINE_VAL ," in_INSERT_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_nb_inst_insert[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 97) @@ -95,5 +95,5 @@ public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ;//[nb_front_end] public : SC_OUT(Tcontrol_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ;//[nb_front_end] - public : SC_OUT(Taddress_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ;//[nb_front_end] + public : SC_OUT(Tgeneral_data_t ) ** out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ;//[nb_front_end] public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_VAL ;//[nb_ooo_engine] @@ -107,5 +107,5 @@ public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ;//[nb_ooo_engine] public : SC_IN (Tcontrol_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ;//[nb_ooo_engine] - public : SC_IN (Taddress_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ;//[nb_ooo_engine] + public : SC_IN (Tgeneral_data_t ) ** in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ;//[nb_ooo_engine] @@ -168,5 +168,5 @@ public : SC_OUT(Texception_t ) **** out_EXECUTE_OOO_ENGINE_EXCEPTION ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] public : SC_OUT(Tcontrol_t ) **** out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] - public : SC_OUT(Tgeneral_data_t ) **** out_EXECUTE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] + public : SC_OUT(Taddress_t ) **** out_EXECUTE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] public : SC_OUT(Tgeneral_data_t ) **** out_EXECUTE_OOO_ENGINE_DATA ;//[nb_ooo_engine][ooo_engine_nb_execute_loop][nb_inst_execute] @@ -182,5 +182,5 @@ public : SC_IN (Texception_t ) *** in_EXECUTE_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_write_unit] public : SC_IN (Tcontrol_t ) *** in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_write_unit] - public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_write_unit] + public : SC_IN (Taddress_t ) *** in_EXECUTE_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_write_unit] public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_write_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 97) @@ -97,7 +97,7 @@ ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); - ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_OUT(out_COMMIT_EVENT_FRONT_END_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); } @@ -113,7 +113,7 @@ ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_spr); + ALLOC1_SIGNAL_IN ( in_COMMIT_EVENT_OOO_ENGINE_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data); } @@ -186,5 +186,5 @@ _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); - _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); + _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); _ALLOC3_SIGNAL_OUT(out_EXECUTE_OOO_ENGINE_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_ooo_engine,_param->_ooo_engine_nb_execute_loop[it1],_param->_nb_inst_execute[it1][it2]); } @@ -204,5 +204,5 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); - _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_write_unit[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/include/Types.h (revision 97) @@ -67,5 +67,5 @@ Texception_t _exception ; Tcontrol_t _no_sequence ; - Tgeneral_data_t _address ; + Taddress_t _address ; } execute_operation_t; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/SelfTest/src/test.cpp (revision 97) @@ -145,5 +145,5 @@ sc_signal out_EXECUTE_OUT_PACKET_ID (rename.c_str()); //sc_signal out_EXECUTE_OUT_OPERATION (rename.c_str()); - sc_signal out_EXECUTE_OUT_TYPE (rename.c_str()); +//sc_signal out_EXECUTE_OUT_TYPE (rename.c_str()); sc_signal out_EXECUTE_OUT_WRITE_RD (rename.c_str()); sc_signal out_EXECUTE_OUT_NUM_REG_RD (rename.c_str()); @@ -200,5 +200,5 @@ (*(_Functionnal_unit->out_EXECUTE_OUT_PACKET_ID )) (out_EXECUTE_OUT_PACKET_ID ); //(*(_Functionnal_unit->out_EXECUTE_OUT_OPERATION )) (out_EXECUTE_OUT_OPERATION ); - (*(_Functionnal_unit->out_EXECUTE_OUT_TYPE )) (out_EXECUTE_OUT_TYPE ); +//(*(_Functionnal_unit->out_EXECUTE_OUT_TYPE )) (out_EXECUTE_OUT_TYPE ); (*(_Functionnal_unit->out_EXECUTE_OUT_WRITE_RD )) (out_EXECUTE_OUT_WRITE_RD ); (*(_Functionnal_unit->out_EXECUTE_OUT_NUM_REG_RD )) (out_EXECUTE_OUT_NUM_REG_RD ); @@ -632,5 +632,5 @@ TEST(Tcontext_t , out_EXECUTE_OUT_OOO_ENGINE_ID.read(), transaction_out.front()._ooo_engine_id); //TEST(Toperation_t , out_EXECUTE_OUT_OPERATION .read(), transaction_out.front()._operation ); - TEST(Ttype_t , out_EXECUTE_OUT_TYPE .read(), transaction_out.front()._type ); + //TEST(Ttype_t , out_EXECUTE_OUT_TYPE .read(), transaction_out.front()._type ); TEST(Tcontrol_t , out_EXECUTE_OUT_WRITE_RE .read(), transaction_out.front()._write_re ); TEST(Tgeneral_address_t, out_EXECUTE_OUT_NUM_REG_RD .read(), transaction_out.front()._num_reg_rd ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h (revision 97) @@ -106,5 +106,5 @@ public : SC_OUT(Tpacket_t ) * out_EXECUTE_OUT_PACKET_ID ; //public : SC_OUT(Toperation_t ) * out_EXECUTE_OUT_OPERATION ; - public : SC_OUT(Ttype_t ) * out_EXECUTE_OUT_TYPE ; +//public : SC_OUT(Ttype_t ) * out_EXECUTE_OUT_TYPE ; public : SC_OUT(Tcontrol_t ) * out_EXECUTE_OUT_WRITE_RD ; public : SC_OUT(Tgeneral_address_t) * out_EXECUTE_OUT_NUM_REG_RD ; @@ -115,5 +115,5 @@ public : SC_OUT(Texception_t ) * out_EXECUTE_OUT_EXCEPTION ; public : SC_OUT(Tcontrol_t ) * out_EXECUTE_OUT_NO_SEQUENCE ; - public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_OUT_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_EXECUTE_OUT_ADDRESS ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_allocation.cpp (revision 97) @@ -105,5 +105,5 @@ out_EXECUTE_OUT_PACKET_ID = interface->set_signal_out ("packet_id" ,_param->_size_rob_ptr ); //out_EXECUTE_OUT_OPERATION = interface->set_signal_out ("operation" ,_param->_size_operation ); - out_EXECUTE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); + //out_EXECUTE_OUT_TYPE = interface->set_signal_out ("type" ,_param->_size_type ); out_EXECUTE_OUT_WRITE_RD = interface->set_signal_out ("write_rd" ,1); out_EXECUTE_OUT_NUM_REG_RD = interface->set_signal_out ("num_reg_rd" ,_param->_size_general_register); @@ -114,5 +114,5 @@ out_EXECUTE_OUT_EXCEPTION = interface->set_signal_out ("exception" ,_param->_size_exception); out_EXECUTE_OUT_NO_SEQUENCE = interface->set_signal_out ("no_sequence" ,1); - out_EXECUTE_OUT_ADDRESS = interface->set_signal_out ("address" ,_param->_size_general_data); + out_EXECUTE_OUT_ADDRESS = interface->set_signal_out ("address" ,_param->_size_instruction_address); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_deallocation.cpp (revision 97) @@ -64,6 +64,6 @@ if (_param->_have_port_rob_ptr) delete out_EXECUTE_OUT_PACKET_ID ; - //delete out_EXECUTE_OUT_OPERATION ; - delete out_EXECUTE_OUT_TYPE ; +// delete out_EXECUTE_OUT_OPERATION ; +// delete out_EXECUTE_OUT_TYPE ; delete out_EXECUTE_OUT_WRITE_RD ; delete out_EXECUTE_OUT_NUM_REG_RD ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_genMoore.cpp (revision 97) @@ -45,5 +45,5 @@ PORT_WRITE(out_EXECUTE_OUT_PACKET_ID ,_execute_operation_out->_packet_id ); // PORT_WRITE(out_EXECUTE_OUT_OPERATION ,_execute_operation_out->_operation ); - PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation_out->_type ); + // PORT_WRITE(out_EXECUTE_OUT_TYPE ,_execute_operation_out->_type ); PORT_WRITE(out_EXECUTE_OUT_WRITE_RD ,_execute_operation_out->_write_rd ); PORT_WRITE(out_EXECUTE_OUT_NUM_REG_RD ,_execute_operation_out->_num_reg_rd ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 97) @@ -95,5 +95,5 @@ log_printf(TRACE,Functionnal_unit,FUNCTION," * packet_id : %d",_execute_operation_in->_packet_id ); log_printf(TRACE,Functionnal_unit,FUNCTION," * operation : %d",_execute_operation_in->_operation ); - log_printf(TRACE,Functionnal_unit,FUNCTION," * type : %s",toString_type(_execute_operation_in->_type).c_str()); + log_printf(TRACE,Functionnal_unit,FUNCTION," * type : %s",toString(_execute_operation_in->_type).c_str()); log_printf(TRACE,Functionnal_unit,FUNCTION," * has_immediat : %d",_execute_operation_in->_has_immediat ); log_printf(TRACE,Functionnal_unit,FUNCTION," * immediat : %.8x",_execute_operation_in->_immediat ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Parameters.cpp (revision 97) @@ -75,4 +75,5 @@ if (is_toplevel) { + _size_instruction_address= size_general_data-2; _size_context_id = log2(nb_context ); _size_front_end_id = log2(nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp (revision 97) @@ -97,5 +97,5 @@ ALLOC1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,"out_MEMORY_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_memory); //ALLOC1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,"out_MEMORY_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_memory); - ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); +//ALLOC1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,"out_MEMORY_OUT_TYPE ",Ttype_t ,_param->_nb_inst_memory); ALLOC1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,"out_MEMORY_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_memory); // = (operation==load) ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,"out_MEMORY_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_memory); // destination (load) @@ -106,5 +106,5 @@ ALLOC1_SC_SIGNAL(out_MEMORY_OUT_EXCEPTION ,"out_MEMORY_OUT_EXCEPTION ",Texception_t ,_param->_nb_inst_memory); ALLOC1_SC_SIGNAL(out_MEMORY_OUT_NO_SEQUENCE ,"out_MEMORY_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_memory); - ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_memory); + ALLOC1_SC_SIGNAL(out_MEMORY_OUT_ADDRESS ,"out_MEMORY_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_memory); ALLOC1_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_cache_port); ALLOC1_SC_SIGNAL( in_DCACHE_REQ_ACK ," in_DCACHE_REQ_ACK ",Tcontrol_t ,_param->_nb_cache_port); @@ -169,5 +169,5 @@ INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); //INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); - INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); +//INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); INSTANCE1_SC_SIGNAL(_Load_store_unit,out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); @@ -520,5 +520,5 @@ TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID[0]->read(), tab_request[packet_id]._ooo_engine_id); // TEST(Toperation_t , out_MEMORY_OUT_OPERATION [0]->read(), tab_request[packet_id]._operation ); - TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); +// TEST(Ttype_t , out_MEMORY_OUT_TYPE [0]->read(), TYPE_MEMORY ); if (is_operation_memory_load (tab_request[packet_id]._operation)) @@ -730,5 +730,5 @@ DELETE1_SC_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory); //DELETE1_SC_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory); - DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); +//DELETE1_SC_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory); DELETE1_SC_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory); DELETE1_SC_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h (revision 97) @@ -118,5 +118,5 @@ public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] //public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] - public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] +//public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) @@ -127,5 +127,5 @@ public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] - public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] + public : SC_OUT(Taddress_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Types.h (revision 97) @@ -235,4 +235,43 @@ }; + + template<> inline std::string toString(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tstore_queue_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_EMPTY : return "empty" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_NO_VALID_NO_SPECULATIVE : return "no_valid_no_speculative"; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_SPECULATIVE : return "valid_speculative" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_VALID_NO_SPECULATIVE : return "valid_no_speculative" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::STORE_QUEUE_COMMIT : return "commit" ; break; + default : return "" ; break; + } + }; + + template<> inline std::string toString(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tspeculative_access_queue_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_EMPTY : return "empty" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE : return "wait_cache" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE : return "wait_load_queue"; break; + default : return "" ; break; + } + }; + + template<> inline std::string toString(const morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Tload_queue_state_t& x) + { + switch (x) + { + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_EMPTY : return "empty" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT_CHECK : return "wait_check" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_WAIT : return "wait" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT_CHECK : return "commit_check"; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_CHECK : return "check" ; break; + case morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::LOAD_QUEUE_COMMIT : return "commit" ; break; + default : return "" ; break; + } + }; + }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp (revision 97) @@ -72,7 +72,7 @@ ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,1 ); + ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); } @@ -88,14 +88,14 @@ ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); +// ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_general_register ); - ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_deallocation.cpp (revision 97) @@ -63,5 +63,5 @@ DELETE1_SIGNAL(out_MEMORY_OUT_PACKET_ID ,_param->_nb_inst_memory,_param->_size_rob_ptr ); // DELETE1_SIGNAL(out_MEMORY_OUT_OPERATION ,_param->_nb_inst_memory,_param->_size_operation ); - DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); +// DELETE1_SIGNAL(out_MEMORY_OUT_TYPE ,_param->_nb_inst_memory,_param->_size_type ); DELETE1_SIGNAL(out_MEMORY_OUT_WRITE_RD ,_param->_nb_inst_memory,1 ); DELETE1_SIGNAL(out_MEMORY_OUT_NUM_REG_RD ,_param->_nb_inst_memory,_param->_size_general_register ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (revision 97) @@ -121,5 +121,5 @@ PORT_WRITE(out_MEMORY_OUT_PACKET_ID [0], memory_out_packet_id ); // PORT_WRITE(out_MEMORY_OUT_OPERATION [0], memory_out_operation ); - PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); +// PORT_WRITE(out_MEMORY_OUT_TYPE [0], TYPE_MEMORY ); PORT_WRITE(out_MEMORY_OUT_WRITE_RD [0], memory_out_write_rd ); PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD [0], memory_out_num_reg_rd ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp (revision 97) @@ -23,5 +23,6 @@ void Load_store_unit::function_speculative_load_commit_transition (void) { - log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); + log_begin(Load_store_unit,FUNCTION); + log_function(Load_store_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -53,5 +54,5 @@ // solution 1) - log_printf(TRACE,Load_store_unit,FUNCTION,"CHECK"); + log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK"); for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) { @@ -63,5 +64,5 @@ is_operation_memory_load(_load_queue[index_load]._operation)) { - log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); + log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); nb_check++; // use one port @@ -283,10 +284,10 @@ // - second is the information of re order buffer : the store become not speculative and can access at the data cache - log_printf(TRACE,Load_store_unit,FUNCTION,"store_queue"); - log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue"); + log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); // Write pointer is define in rename stage : Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); - log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); + log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); // Need read : state and exception. @@ -373,5 +374,5 @@ if (update_info == true) { - log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); + log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); @@ -395,11 +396,11 @@ // In speculative access queue, they are many type's request - log_printf(TRACE,Load_store_unit,FUNCTION,"speculative_access_queue"); - log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); + log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); + log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); // Write in reservation station uint32_t index = _speculative_access_queue_control->push(); - log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); + log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); Texception_t exception; @@ -428,5 +429,5 @@ _speculative_access_queue [index]._exception = exception; - log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); + log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); } } @@ -439,5 +440,5 @@ (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); + log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT transaction"); switch (internal_MEMORY_OUT_SELECT_QUEUE) @@ -449,5 +450,5 @@ // ======================= - log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); + log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); // Entry flush and increase the read pointer @@ -464,5 +465,5 @@ // ====================== - log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); + log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); // Entry flush and increase the read pointer @@ -476,5 +477,5 @@ case SELECT_LOAD_QUEUE_SPECULATIVE : { - log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); + log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; @@ -497,5 +498,5 @@ (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); + log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ"); switch (internal_DCACHE_REQ_SELECT_QUEUE) @@ -587,6 +588,6 @@ _load_queue [ptr_write]._rdata = address; // to the exception - log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); - log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); + log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); + log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; @@ -601,5 +602,5 @@ ( internal_DCACHE_RSP_ACK == 1)) { - log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_RSP"); + log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP"); // don't use context_id : because there are one queue for all thread @@ -609,5 +610,5 @@ Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); - log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); if (DCACHE_RSP_IS_LOAD(packet_id) == 1) @@ -615,5 +616,5 @@ packet_id >>= 1; - log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); + log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); @@ -626,5 +627,5 @@ if (error != DCACHE_ERROR_NONE) { - log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); + log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; @@ -633,6 +634,6 @@ else { - log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); - log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); + log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); + log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); // FIXME : convention : if bus error, the cache return the fautive address ! @@ -650,5 +651,5 @@ else { - log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); + log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! @@ -664,33 +665,77 @@ #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) // ***** dump store queue - std::cout << "Dump STORE_QUEUE :" << std::endl - << "ptr_read : " << toString(static_cast(reg_STORE_QUEUE_PTR_READ)) << std::endl; + log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE"); + log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); for (uint32_t i=0; i<_param->_size_store_queue; i++) { uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; - std::cout << "{" << j << "}" << std::endl - << _store_queue[j] << std::endl; + + log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %s", + j, + _store_queue[j]._context_id , + _store_queue[j]._front_end_id , + _store_queue[j]._ooo_engine_id , + _store_queue[j]._packet_id , + _store_queue[j]._operation , + _store_queue[j]._load_queue_ptr_write, + _store_queue[j]._address , + _store_queue[j]._wdata , + //_store_queue[j]._write_rd , + //_store_queue[j]._num_reg_rd , + _store_queue[j]._exception , + toString(_store_queue[j]._state).c_str()); } // ***** dump speculative_access queue - std::cout << "Dump SPECULATIVE_ACCESS_QUEUE :" << std::endl; + log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE"); for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) { uint32_t j = (*_speculative_access_queue_control)[i]; - std::cout << "{" << j << "}" << std::endl - << _speculative_access_queue[j] << std::endl; + + log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.6d, %.2d, %s", + j, + _speculative_access_queue[j]._context_id , + _speculative_access_queue[j]._front_end_id , + _speculative_access_queue[j]._ooo_engine_id , + _speculative_access_queue[j]._packet_id , + _speculative_access_queue[j]._operation , + _speculative_access_queue[j]._load_queue_ptr_write, + _speculative_access_queue[j]._store_queue_ptr_write, + _speculative_access_queue[j]._address , + _speculative_access_queue[j]._write_rd , + _speculative_access_queue[j]._num_reg_rd , + _speculative_access_queue[j]._exception , + toString(_speculative_access_queue[j]._state).c_str()); } // ***** dump load queue - std::cout << "Dump LOAD_QUEUE :" << std::endl - << "ptr_read_check_priority : " << toString(static_cast(reg_LOAD_QUEUE_CHECK_PRIORITY)) << std::endl; + log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE"); + log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY); for (uint32_t i=0; i<_param->_size_load_queue; i++) { uint32_t j = i; - std::cout << "{" << j << "}" << std::endl - << _load_queue[j] << std::endl; + + log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.6d, %.2d, %s", + j, + _load_queue[j]._context_id , + _load_queue[j]._front_end_id , + _load_queue[j]._ooo_engine_id , + _load_queue[j]._packet_id , + _load_queue[j]._operation , + _load_queue[j]._store_queue_ptr_write, + _load_queue[j]._address , + _load_queue[j]._check_hit_byte , + _load_queue[j]._check_hit , + _load_queue[j]._shift , + _load_queue[j]._is_load_signed , + _load_queue[j]._access_size , + _load_queue[j]._rdata , + _load_queue[j]._write_rd , + _load_queue[j]._num_reg_rd , + _load_queue[j]._exception , + toString(_load_queue[j]._state).c_str()); } #endif @@ -712,5 +757,5 @@ } - log_printf(FUNC,Load_store_unit,FUNCTION,"End"); + log_end(Load_store_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Parameters.cpp (revision 97) @@ -69,4 +69,5 @@ if (is_toplevel) { + _size_instruction_address = size_general_data-2; _size_context_id = log2(nb_context ); _size_front_end_id = log2(nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 97) @@ -190,5 +190,5 @@ _queue_head->_num_reg_re , - toString_type(_queue_head->_type).c_str()); + toString(_queue_head->_type).c_str()); @@ -240,5 +240,5 @@ (*it)->_num_reg_re , - toString_type((*it)->_type).c_str()); + toString((*it)->_type).c_str()); ++i; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp (revision 97) @@ -22,28 +22,28 @@ { log_printf(FUNC,Read_queue,"vhdl_body","Begin"); - vhdl->set_body (""); - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- Instance queue "); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); - - vhdl->set_body("instance_"+_name+"_queue : "+_name+"_queue"); - vhdl->set_body("port map ("); - vhdl->set_body("\t in_CLOCK \t=>\t in_CLOCK "); - vhdl->set_body("\t, in_NRESET \t=>\t in_NRESET"); - vhdl->set_body("\t, in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); - vhdl->set_body("\t,out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); - vhdl->set_body("\t, in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); - vhdl->set_body("\t,out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); - vhdl->set_body("\t, in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); - vhdl->set_body("\t,out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); - vhdl->set_body(");"); - - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- Queue_data "); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); + vhdl->set_body(0,""); + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- Instance queue "); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); + + vhdl->set_body(0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body(0,"port map ("); + vhdl->set_body(1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body(1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body(1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body(1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body(1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body(1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body(1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body(1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body(0,");"); + + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- Queue_data "); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); uint32_t min = 0; @@ -53,5 +53,5 @@ { max = min-1+_param->_size_context_id; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_CONTEXT_ID;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_CONTEXT_ID;"); min = max+1; } @@ -59,5 +59,5 @@ { max = min-1+_param->_size_front_end_id; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_FRONT_END_ID;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_FRONT_END_ID;"); min = max+1; } @@ -65,185 +65,185 @@ { max = min-1+_param->_size_ooo_engine_id; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OOO_ENGINE_ID;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OOO_ENGINE_ID;"); min = max+1; } - if(_param->_have_port_rob_id ) - { - max = min-1+_param->_size_rob_id; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_ROB_ID;"); + if(_param->_have_port_rob_ptr ) + { + max = min-1+_param->_size_rob_ptr ; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_ROB_ID;"); min = max+1; } max = min-1+_param->_size_operation; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OPERATION;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_OPERATION;"); min = max+1; max = min-1+_param->_size_type; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_TYPE;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_HAS_IMMEDIAT;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_TYPE;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_HAS_IMMEDIAT;"); min = max+1; max = min-1+_param->_size_general_data; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_IMMEDIAT;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RA;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_IMMEDIAT;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RA;"); min = max+1; max = min-1+_param->_size_general_register; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RA;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RB;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RA;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RB;"); min = max+1; max = min-1+_param->_size_general_register; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RB;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RC;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RB;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_READ_RC;"); min = max+1; max = min-1+_param->_size_special_register; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RC;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RD;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RC;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RD;"); min = max+1; max = min-1+_param->_size_general_register; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RD;"); - min = max+1; - - max = min; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RE;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RD;"); + min = max+1; + + max = min; + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_WRITE_RE;"); min = max+1; max = min-1+_param->_size_special_register; - vhdl->set_body ("internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RE;"); - min = max+1; - - vhdl->set_body ("internal_QUEUE_RETIRE_ACK <= internal_READ_QUEUE_OUT_VAL and in_READ_QUEUE_OUT_ACK;"); - - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- Interface read"); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); - vhdl->set_body("-- GPR"); - vhdl->set_body ("out_GPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RA_VAL;"); - vhdl->set_body ("out_GPR_READ_1_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RB_VAL;"); + vhdl->set_body(0,"internal_QUEUE_INSERT_DATA"+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_READ_QUEUE_IN_NUM_REG_RE;"); + min = max+1; + + vhdl->set_body(0,"internal_QUEUE_RETIRE_ACK <= internal_READ_QUEUE_OUT_VAL and in_READ_QUEUE_OUT_ACK;"); + + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- Interface read"); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); + vhdl->set_body(0,"-- GPR"); + vhdl->set_body(0,"out_GPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RA_VAL;"); + vhdl->set_body(0,"out_GPR_READ_1_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RB_VAL;"); if(_param->_have_port_ooo_engine_id) { - vhdl->set_body ("out_GPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); - vhdl->set_body ("out_GPR_READ_1_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); - } - vhdl->set_body ("out_GPR_READ_0_NUM_REG <= internal_NUM_REG_RA;"); - vhdl->set_body ("out_GPR_READ_1_NUM_REG <= internal_NUM_REG_RB;"); - vhdl->set_body(""); - - vhdl->set_body("-- SPR"); - vhdl->set_body ("out_SPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RC_VAL;"); + vhdl->set_body(0,"out_GPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); + vhdl->set_body(0,"out_GPR_READ_1_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); + } + vhdl->set_body(0,"out_GPR_READ_0_NUM_REG <= internal_NUM_REG_RA;"); + vhdl->set_body(0,"out_GPR_READ_1_NUM_REG <= internal_NUM_REG_RB;"); + vhdl->set_body(0,""); + + vhdl->set_body(0,"-- SPR"); + vhdl->set_body(0,"out_SPR_READ_0_VAL <= internal_QUEUE_RETIRE_VAL and internal_READ_RC_VAL;"); if(_param->_have_port_ooo_engine_id) { - vhdl->set_body ("out_SPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); - } - vhdl->set_body ("out_SPR_READ_0_NUM_REG <= internal_NUM_REG_RC;"); - - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- Interface read_queue_out"); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); + vhdl->set_body(0,"out_SPR_READ_0_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); + } + vhdl->set_body(0,"out_SPR_READ_0_NUM_REG <= internal_NUM_REG_RC;"); + + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- Interface read_queue_out"); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); if(_param->_have_port_context_id ) - vhdl->set_body ("out_READ_QUEUE_OUT_CONTEXT_ID <= internal_CONTEXT_ID ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_CONTEXT_ID <= internal_CONTEXT_ID ;"); if(_param->_have_port_front_end_id ) - vhdl->set_body ("out_READ_QUEUE_OUT_FRONT_END_ID <= internal_FRONT_END_ID ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_FRONT_END_ID <= internal_FRONT_END_ID ;"); if(_param->_have_port_ooo_engine_id ) - vhdl->set_body ("out_READ_QUEUE_OUT_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); - if(_param->_have_port_rob_id ) - vhdl->set_body ("out_READ_QUEUE_OUT_ROB_ID <= internal_ROB_ID ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_OPERATION <= internal_OPERATION ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_TYPE <= internal_TYPE ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_HAS_IMMEDIAT <= internal_HAS_IMMEDIAT ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_IMMEDIAT <= internal_IMMEDIAT ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RA <= internal_NUM_REG_RA ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RA <= internal_NEXT_DATA_RA ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RB <= internal_NUM_REG_RB ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RB <= internal_NEXT_DATA_RB ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RC <= internal_NUM_REG_RC ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); - vhdl->set_body ("out_READ_QUEUE_OUT_DATA_RC <= internal_NEXT_DATA_RC ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_WRITE_RD <= internal_WRITE_RD ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RD <= internal_NUM_REG_RD ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_WRITE_RE <= internal_WRITE_RE ;"); - vhdl->set_body ("out_READ_QUEUE_OUT_NUM_REG_RE <= internal_NUM_REG_RE ;"); - - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- next reg update"); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); - vhdl->set_body("-- read_rx_val - 1 : must access at the registerFile (after access, is set at 0)"); - - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_READ_RA_VAL <="); - vhdl->set_body("\t'0' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); - for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) - { - std::string cmp; - - if (_param->_have_port_ooo_engine_id) - cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; - else - cmp = ""; - - vhdl->set_body("\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_READ_RA_VAL and not in_GPR_READ_0_ACK;"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_READ_RB_VAL <="); - vhdl->set_body("\t'0' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); - for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) - { - std::string cmp; - - if (_param->_have_port_ooo_engine_id) - cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; - else - cmp = ""; - - vhdl->set_body("\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_READ_RB_VAL and not in_GPR_READ_1_ACK;"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_READ_RC_VAL <="); - vhdl->set_body("\t'0' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_OOO_ENGINE_ID <= internal_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr ) + vhdl->set_body(0,"out_READ_QUEUE_OUT_ROB_ID <= internal_ROB_ID ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_OPERATION <= internal_OPERATION ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_TYPE <= internal_TYPE ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_HAS_IMMEDIAT <= internal_HAS_IMMEDIAT ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_IMMEDIAT <= internal_IMMEDIAT ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RA <= internal_NUM_REG_RA ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA <= internal_NEXT_DATA_RA ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RB <= internal_NUM_REG_RB ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB <= internal_NEXT_DATA_RB ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RC <= internal_NUM_REG_RC ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RC <= internal_NEXT_DATA_RC ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_WRITE_RD <= internal_WRITE_RD ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RD <= internal_NUM_REG_RD ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_WRITE_RE <= internal_WRITE_RE ;"); + vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RE <= internal_NUM_REG_RE ;"); + + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- next reg update"); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); + vhdl->set_body(0,"-- read_rx_val - 1 : must access at the registerFile (after access, is set at 0)"); + + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_READ_RA_VAL <="); + vhdl->set_body(1,"'0' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); + for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) + { + std::string cmp; + + if (_param->_have_port_ooo_engine_id) + cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; + else + cmp = ""; + + vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_READ_RA_VAL and not in_GPR_READ_0_ACK;"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_READ_RB_VAL <="); + vhdl->set_body(1,"'0' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); + for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) + { + std::string cmp; + + if (_param->_have_port_ooo_engine_id) + cmp = "and (in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID=internal_OOO_ENGINE_ID) "; + else + cmp = ""; + + vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_READ_RB_VAL and not in_GPR_READ_1_ACK;"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_READ_RC_VAL <="); + vhdl->set_body(1,"'0' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) { @@ -255,25 +255,25 @@ cmp = ""; - vhdl->set_body("\t\t((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_READ_RC_VAL and not in_SPR_READ_0_ACK;"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_READ_QUEUE_OUT_VAL <= not internal_NEXT_READ_RA_VAL and not internal_NEXT_READ_RB_VAL and not internal_NEXT_READ_RC_VAL;"); - vhdl->set_body(" out_READ_QUEUE_OUT_VAL <= internal_READ_QUEUE_OUT_VAL and internal_QUEUE_RETIRE_VAL;"); + vhdl->set_body(2,"((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_READ_RC_VAL and not in_SPR_READ_0_ACK;"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_READ_QUEUE_OUT_VAL <= not internal_NEXT_READ_RA_VAL and not internal_NEXT_READ_RB_VAL and not internal_NEXT_READ_RC_VAL;"); + vhdl->set_body(0," out_READ_QUEUE_OUT_VAL <= internal_READ_QUEUE_OUT_VAL and internal_QUEUE_RETIRE_VAL;"); } - vhdl->set_body(""); - vhdl->set_body("-- data_rx_val - 1 : the read of registerFile is valid"); - - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RA_VAL <="); - vhdl->set_body("\t'1' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(0,""); + vhdl->set_body(0,"-- data_rx_val - 1 : the read of registerFile is valid"); + + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RA_VAL <="); + vhdl->set_body(1,"'1' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) { @@ -285,15 +285,15 @@ cmp = ""; - vhdl->set_body("\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_DATA_RA_VAL or (internal_READ_RA_VAL and in_GPR_READ_0_ACK and in_GPR_READ_0_DATA_VAL);"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RB_VAL <="); - vhdl->set_body("\t'1' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_DATA_RA_VAL or (internal_READ_RA_VAL and in_GPR_READ_0_ACK and in_GPR_READ_0_DATA_VAL);"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RB_VAL <="); + vhdl->set_body(1,"'1' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) { @@ -305,15 +305,15 @@ cmp = ""; - vhdl->set_body("\t\t((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_DATA_RB_VAL or (internal_READ_RB_VAL and in_GPR_READ_1_ACK and in_GPR_READ_1_DATA_VAL);"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RC_VAL <="); - vhdl->set_body("\t'1' when"); - // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(2,"((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_DATA_RB_VAL or (internal_READ_RB_VAL and in_GPR_READ_1_ACK and in_GPR_READ_1_DATA_VAL);"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RC_VAL <="); + vhdl->set_body(1,"'1' when"); + // bypass + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) { @@ -325,20 +325,20 @@ cmp = ""; - vhdl->set_body("\t\t((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); - } - vhdl->set_body("\t\tfalse else"); - vhdl->set_body("\tinternal_DATA_RC_VAL or (internal_READ_RC_VAL and in_SPR_READ_0_ACK and in_SPR_READ_0_DATA_VAL);"); - } - - vhdl->set_body(""); - vhdl->set_body("-- data_rx - data read"); - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RA <="); + vhdl->set_body(2,"((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RC=in_SPR_WRITE_"+toString(i)+"_NUM_REG)) or"); + } + vhdl->set_body(2,"false else"); + vhdl->set_body(1,"internal_DATA_RC_VAL or (internal_READ_RC_VAL and in_SPR_READ_0_ACK and in_SPR_READ_0_DATA_VAL);"); + } + + vhdl->set_body(0,""); + vhdl->set_body(0,"-- data_rx - data read"); + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RA <="); #ifdef SYSTEMC_VHDL_COMPATIBILITY - vhdl->set_body("\t"+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RA='0' else"); + vhdl->set_body(1,""+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RA='0' else"); #endif // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) { @@ -350,17 +350,17 @@ cmp = ""; - vhdl->set_body("\tin_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); - } - vhdl->set_body("\treg_DATA_RA when (internal_DATA_RA_VAL='1') else"); - vhdl->set_body("\tin_GPR_READ_0_DATA;"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RB <="); + vhdl->set_body(1,"in_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RA=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); + } + vhdl->set_body(1,"reg_DATA_RA when (internal_DATA_RA_VAL='1') else"); + vhdl->set_body(1,"in_GPR_READ_0_DATA;"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RB <="); #ifdef SYSTEMC_VHDL_COMPATIBILITY - vhdl->set_body("\t"+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RB='0' else"); + vhdl->set_body(1,""+std_logic_others(_param->_size_general_data,0)+" when internal_READ_RB='0' else"); #endif // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_gpr_write-1; i>=0 ; i--) { @@ -372,17 +372,17 @@ cmp = ""; - vhdl->set_body("\tin_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); - } - vhdl->set_body("\treg_DATA_RB when (internal_DATA_RB_VAL='1') else"); - vhdl->set_body("\tin_GPR_READ_1_DATA;"); - } - { - vhdl->set_body(""); - vhdl->set_body("internal_NEXT_DATA_RC <="); + vhdl->set_body(1,"in_GPR_WRITE_"+toString(i)+"_DATA when ((in_GPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (internal_NUM_REG_RB=in_GPR_WRITE_"+toString(i)+"_NUM_REG)) else"); + } + vhdl->set_body(1,"reg_DATA_RB when (internal_DATA_RB_VAL='1') else"); + vhdl->set_body(1,"in_GPR_READ_1_DATA;"); + } + { + vhdl->set_body(0,""); + vhdl->set_body(0,"internal_NEXT_DATA_RC <="); #ifdef SYSTEMC_VHDL_COMPATIBILITY - vhdl->set_body("\t"+std_logic_others(_param->_size_special_data,0)+" when internal_READ_RC='0' else"); + vhdl->set_body(1,""+std_logic_others(_param->_size_special_data,0)+" when internal_READ_RC='0' else"); #endif // bypass - vhdl->set_body("\t\t-- check bypass"); + vhdl->set_body(2,"-- check bypass"); for (int32_t i=_param->_nb_spr_write-1; i>=0 ; i--) { @@ -394,50 +394,50 @@ cmp = ""; - vhdl->set_body("\tin_SPR_WRITE_"+toString(i)+"_DATA when ((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (in_SPR_WRITE_"+toString(i)+"_NUM_REG=internal_NUM_REG_RC)) else"); - } - vhdl->set_body("\treg_DATA_RC when (internal_DATA_RC_VAL='1') else"); - vhdl->set_body("\tin_SPR_READ_0_DATA;"); - - vhdl->set_body(""); - vhdl->set_body("-----------------------------------"); - vhdl->set_body("-- transition"); - vhdl->set_body("-----------------------------------"); - vhdl->set_body(""); - vhdl->set_body("-- need a new head if :"); - vhdl->set_body("-- * queue is empty"); - vhdl->set_body("-- * pop with queue"); - vhdl->set_body ("internal_NEXT_NEED_NEW_HEAD <= not internal_QUEUE_RETIRE_VAL or (internal_QUEUE_RETIRE_VAL and internal_QUEUE_RETIRE_ACK);"); - - vhdl->set_body ("internal_READ_RA_VAL <= internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_READ_RA_VAL;"); - vhdl->set_body ("internal_READ_RB_VAL <= internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_READ_RB_VAL;"); - vhdl->set_body ("internal_READ_RC_VAL <= internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_READ_RC_VAL;"); - vhdl->set_body ("internal_DATA_RA_VAL <= not internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_DATA_RA_VAL;"); - vhdl->set_body ("internal_DATA_RB_VAL <= not internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_DATA_RB_VAL;"); - vhdl->set_body ("internal_DATA_RC_VAL <= not internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_DATA_RC_VAL;"); - - - vhdl->set_body (""); - vhdl->set_body ("transition: process (in_CLOCK)"); - vhdl->set_body ("begin -- process transition"); - vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then"); - vhdl->set_body (""); - vhdl->set_body ("\t\tif (in_NRESET = '0') then"); - vhdl->set_body ("\t\t\treg_NEED_NEW_HEAD <= '1';"); - vhdl->set_body ("\t\telse"); - vhdl->set_body ("\t\t\treg_NEED_NEW_HEAD <= internal_NEXT_NEED_NEW_HEAD;"); - vhdl->set_body ("\t\t\treg_READ_RA_VAL <= internal_NEXT_READ_RA_VAL;"); - vhdl->set_body ("\t\t\treg_READ_RB_VAL <= internal_NEXT_READ_RB_VAL;"); - vhdl->set_body ("\t\t\treg_READ_RC_VAL <= internal_NEXT_READ_RC_VAL;"); - vhdl->set_body ("\t\t\treg_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); - vhdl->set_body ("\t\t\treg_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); - vhdl->set_body ("\t\t\treg_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); - vhdl->set_body ("\t\t\treg_DATA_RA <= internal_NEXT_DATA_RA ;"); - vhdl->set_body ("\t\t\treg_DATA_RB <= internal_NEXT_DATA_RB ;"); - vhdl->set_body ("\t\t\treg_DATA_RC <= internal_NEXT_DATA_RC ;"); - - vhdl->set_body ("\t\tend if;"); - vhdl->set_body (""); - vhdl->set_body ("\tend if;"); - vhdl->set_body ("end process transition;"); + vhdl->set_body(1,"in_SPR_WRITE_"+toString(i)+"_DATA when ((in_SPR_WRITE_"+toString(i)+"_VAL='1') "+cmp+"and (in_SPR_WRITE_"+toString(i)+"_NUM_REG=internal_NUM_REG_RC)) else"); + } + vhdl->set_body(1,"reg_DATA_RC when (internal_DATA_RC_VAL='1') else"); + vhdl->set_body(1,"in_SPR_READ_0_DATA;"); + + vhdl->set_body(0,""); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,"-- transition"); + vhdl->set_body(0,"-----------------------------------"); + vhdl->set_body(0,""); + vhdl->set_body(0,"-- need a new head if :"); + vhdl->set_body(0,"-- * queue is empty"); + vhdl->set_body(0,"-- * pop with queue"); + vhdl->set_body(0,"internal_NEXT_NEED_NEW_HEAD <= not internal_QUEUE_RETIRE_VAL or (internal_QUEUE_RETIRE_VAL and internal_QUEUE_RETIRE_ACK);"); + + vhdl->set_body(0,"internal_READ_RA_VAL <= internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_READ_RA_VAL;"); + vhdl->set_body(0,"internal_READ_RB_VAL <= internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_READ_RB_VAL;"); + vhdl->set_body(0,"internal_READ_RC_VAL <= internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_READ_RC_VAL;"); + vhdl->set_body(0,"internal_DATA_RA_VAL <= not internal_READ_RA when reg_NEED_NEW_HEAD='1' else reg_DATA_RA_VAL;"); + vhdl->set_body(0,"internal_DATA_RB_VAL <= not internal_READ_RB when reg_NEED_NEW_HEAD='1' else reg_DATA_RB_VAL;"); + vhdl->set_body(0,"internal_DATA_RC_VAL <= not internal_READ_RC when reg_NEED_NEW_HEAD='1' else reg_DATA_RC_VAL;"); + + + vhdl->set_body(0,""); + vhdl->set_body(0,"transition: process (in_CLOCK)"); + vhdl->set_body(0,"begin -- process transition"); + vhdl->set_body(1,"if in_CLOCK'event and in_CLOCK = '1' then"); + vhdl->set_body(0,""); + vhdl->set_body(2,"if (in_NRESET = '0') then"); + vhdl->set_body(3,"reg_NEED_NEW_HEAD <= '1';"); + vhdl->set_body(2,"else"); + vhdl->set_body(3,"reg_NEED_NEW_HEAD <= internal_NEXT_NEED_NEW_HEAD;"); + vhdl->set_body(3,"reg_READ_RA_VAL <= internal_NEXT_READ_RA_VAL;"); + vhdl->set_body(3,"reg_READ_RB_VAL <= internal_NEXT_READ_RB_VAL;"); + vhdl->set_body(3,"reg_READ_RC_VAL <= internal_NEXT_READ_RC_VAL;"); + vhdl->set_body(3,"reg_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); + vhdl->set_body(3,"reg_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); + vhdl->set_body(3,"reg_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); + vhdl->set_body(3,"reg_DATA_RA <= internal_NEXT_DATA_RA ;"); + vhdl->set_body(3,"reg_DATA_RB <= internal_NEXT_DATA_RB ;"); + vhdl->set_body(3,"reg_DATA_RC <= internal_NEXT_DATA_RC ;"); + + vhdl->set_body(2,"end if;"); + vhdl->set_body(0,""); + vhdl->set_body(1,"end if;"); + vhdl->set_body(0,"end process transition;"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_declaration.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_declaration.cpp (revision 97) @@ -87,9 +87,9 @@ min = max+1; } - if(_param->_have_port_rob_id ) + if(_param->_have_port_rob_ptr) { - size = _param->_size_rob_id; + size = _param->_size_rob_ptr; max = min-1+size; - vhdl->set_alias ("internal_ROB_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + vhdl->set_alias ("internal_ROB_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); min = max+1; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/src/test.cpp (revision 97) @@ -6,5 +6,5 @@ * Test */ -#define NB_ITERATION 2 +#define NB_ITERATION 1 #define CYCLE_MAX (2048*NB_ITERATION) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_allocation.cpp (revision 97) @@ -231,6 +231,6 @@ in_BYPASS_WRITE_GPR_DATA [i] = interface->set_signal_in ("gpr_data" ,_param->_size_general_data); in_BYPASS_WRITE_SPR_VAL [i] = interface->set_signal_valack_in ("spr_val",VAL); - in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in ("spr_num_reg" ,_param->_size_general_register); - in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in ("spr_data" ,_param->_size_general_data); + in_BYPASS_WRITE_SPR_NUM_REG [i] = interface->set_signal_in ("spr_num_reg" ,_param->_size_special_register); + in_BYPASS_WRITE_SPR_DATA [i] = interface->set_signal_in ("spr_data" ,_param->_size_special_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 97) @@ -50,5 +50,5 @@ _queue[it_dump]._write_re , \ _queue[it_dump]._num_reg_re , \ - toString_type(_queue[it_dump]._type).c_str()); \ + toString(_queue[it_dump]._type).c_str()); \ } while (0) #else @@ -84,5 +84,5 @@ _queue[(*_queue_control)[it_dump]]._write_re , \ _queue[(*_queue_control)[it_dump]]._num_reg_re , \ - toString_type(_queue[(*_queue_control)[it_dump]]._type).c_str()); \ + toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \ } while (0) #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_body.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_body.cpp (revision 97) @@ -88,5 +88,5 @@ if (_param->_have_port_ooo_engine_id) vhdl->set_body ("out_RETIRE_"+toString(i)+"_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID"+range_retire+";"); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) vhdl->set_body ("out_RETIRE_"+toString(i)+"_ROB_ID <= reg_ROB_ID "+range_retire+";"); vhdl->set_body ("out_RETIRE_"+toString(i)+"_OPERATION <= reg_OPERATION "+range_retire+";"); @@ -268,5 +268,5 @@ if (_param->_have_port_ooo_engine_id) vhdl->set_body ("\t\t\t\treg_OOO_ENGINE_ID "+range_insert+" <= in_INSERT_OOO_ENGINE_ID;"); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) vhdl->set_body ("\t\t\t\treg_ROB_ID "+range_insert+" <= in_INSERT_ROB_ID ;"); vhdl->set_body ("\t\t\t\treg_OPERATION "+range_insert+" <= in_INSERT_OPERATION ;"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_declaration.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_vhdl_declaration.cpp (revision 97) @@ -32,6 +32,6 @@ if (_param->_have_port_ooo_engine_id) vhdl->set_type ("Tooo_engine_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_ooo_engine_id)); - if (_param->_have_port_rob_id) - vhdl->set_type ("Trob_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_rob_id)); + if (_param->_have_port_rob_ptr) + vhdl->set_type ("Trob_id ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_rob_ptr)); vhdl->set_type ("Toperation ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_operation)); vhdl->set_type ("Ttype ","array (" + toString(_param->_size_queue-1) + " downto 0) of " + std_logic(_param->_size_type)); @@ -48,5 +48,5 @@ if (_param->_have_port_ooo_engine_id) vhdl->set_signal("reg_OOO_ENGINE_ID ","Tooo_engine_id"); - if (_param->_have_port_rob_id) + if (_param->_have_port_rob_ptr) vhdl->set_signal("reg_ROB_ID ","Trob_id"); vhdl->set_signal("reg_OPERATION ","Toperation"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp (revision 97) @@ -1,4 +1,4 @@ /* - * $Id$ + * $id: Read_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ * * [ Description ] @@ -115,6 +115,6 @@ ALLOC1_VALACK_IN ( in_GPR_READ_ACK,ACK); ALLOC1_SIGNAL_OUT(out_GPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data ); - ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register); + ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); } @@ -127,6 +127,6 @@ ALLOC1_VALACK_IN ( in_SPR_READ_ACK,ACK); ALLOC1_SIGNAL_OUT(out_SPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_data ); - ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_register); + ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1); } @@ -138,6 +138,6 @@ ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL,VAL); ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data ); - ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data); } @@ -148,6 +148,6 @@ ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL,VAL); ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_data ); - ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data); } @@ -158,9 +158,9 @@ ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_data ); - ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data ); ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_data ); - ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); } @@ -171,6 +171,6 @@ ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_VAL ,"val" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); - ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data ); - ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); + ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 97) @@ -123,5 +123,5 @@ ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_EXCEPTION ," in_EXECUTE_QUEUE_IN_EXCEPTION" , Texception_t ); ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ," in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_ADDRESS ," in_EXECUTE_QUEUE_IN_ADDRESS" , Taddress_t ); ALLOC_SC_SIGNAL ( in_EXECUTE_QUEUE_IN_DATA ," in_EXECUTE_QUEUE_IN_DATA" , Tgeneral_data_t ); ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_VAL ,"out_EXECUTE_QUEUE_OUT_VAL" , Tcontrol_t ); @@ -136,5 +136,5 @@ ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_EXCEPTION ,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , Texception_t ); ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_ADDRESS ,"out_EXECUTE_QUEUE_OUT_ADDRESS" , Taddress_t ); ALLOC_SC_SIGNAL (out_EXECUTE_QUEUE_OUT_DATA ,"out_EXECUTE_QUEUE_OUT_DATA" , Tgeneral_data_t ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h (revision 97) @@ -78,5 +78,5 @@ public : SC_IN (Texception_t ) * in_EXECUTE_QUEUE_IN_EXCEPTION ; public : SC_IN (Tcontrol_t ) * in_EXECUTE_QUEUE_IN_NO_SEQUENCE ; - public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_QUEUE_IN_ADDRESS ; + public : SC_IN (Taddress_t ) * in_EXECUTE_QUEUE_IN_ADDRESS ; public : SC_IN (Tgeneral_data_t ) * in_EXECUTE_QUEUE_IN_DATA ; @@ -93,5 +93,5 @@ public : SC_OUT(Texception_t ) * out_EXECUTE_QUEUE_OUT_EXCEPTION ; public : SC_OUT(Tcontrol_t ) * out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ; - public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_QUEUE_OUT_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_EXECUTE_QUEUE_OUT_ADDRESS ; public : SC_OUT(Tgeneral_data_t ) * out_EXECUTE_QUEUE_OUT_DATA ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_allocation.cpp (revision 97) @@ -67,5 +67,5 @@ ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_IN ( in_EXECUTE_QUEUE_IN_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); } @@ -90,5 +90,5 @@ ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_OUT(out_EXECUTE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Parameters.cpp (revision 97) @@ -41,4 +41,5 @@ if (is_toplevel) { + _size_instruction_address= size_general_data-2; _size_context_id = log2(_nb_context ); _size_front_end_id = log2(_nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/test.cpp (revision 97) @@ -22,5 +22,5 @@ public : Tpacket_t _packet_id ; //public : Toperation_t _operation ; - public : Ttype_t _type ; +//public : Ttype_t _type ; public : Tcontrol_t _write_rd ; public : Tgeneral_address_t _num_reg_rd ; @@ -37,6 +37,6 @@ Tcontext_t ooo_engine_id, Tpacket_t packet_id , - //Toperation_t operation , - Ttype_t type , +// Toperation_t operation , +// Ttype_t type , Tcontrol_t write_rd , Tgeneral_address_t num_reg_rd , @@ -53,6 +53,6 @@ _ooo_engine_id = ooo_engine_id; _packet_id = packet_id ; - //_operation = operation ; - _type = type ; +// _operation = operation ; +// _type = type ; _write_rd = write_rd ; _num_reg_rd = num_reg_rd ; @@ -74,5 +74,5 @@ << " * _packet_id : " << toString(x._packet_id ) << std::endl //<< " * _operation : " << toString(x._operation ) << std::endl - << " * _type : " << toString(x._type ) << std::endl + //<< " * _type : " << toString(x._type ) << std::endl << " * _write_rd : " << toString(x._write_rd ) << std::endl << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl @@ -133,5 +133,5 @@ ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t ); //ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t ); +//ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t ); ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t); @@ -142,5 +142,5 @@ ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t ); ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL ( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Taddress_t ); ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t ); @@ -154,5 +154,5 @@ ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t ); ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Taddress_t ); ALLOC_SC_SIGNAL (out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); @@ -195,5 +195,5 @@ INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_OPERATION ); - INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE ); +//INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_TYPE ); INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_WRITE_RD ); INSTANCE_SC_SIGNAL (_Write_unit, in_WRITE_UNIT_IN_NUM_REG_RD ); @@ -309,5 +309,5 @@ i, //range(rand(),_param->_size_operation ), - range(rand(),_param->_size_type ), + //range(rand(),_param->_size_type ), range(rand(),1 ), range(rand(),_param->_size_general_register), @@ -316,5 +316,5 @@ range(rand(),_param->_size_special_register), range(rand(),_param->_size_special_data ), - range(rand(),_param->_size_exception ), + range(rand(),0 ), range(rand(),1 ), range(rand(),_param->_size_general_data )); @@ -341,5 +341,5 @@ in_WRITE_UNIT_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); //in_WRITE_UNIT_IN_OPERATION ->write(request [nb_request_in]->_operation ); - in_WRITE_UNIT_IN_TYPE ->write(request [nb_request_in]->_type ); + //in_WRITE_UNIT_IN_TYPE ->write(request [nb_request_in]->_type ); in_WRITE_UNIT_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); in_WRITE_UNIT_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/test.cpp (revision 97) @@ -22,5 +22,5 @@ public : Tpacket_t _packet_id ; //public : Toperation_t _operation ; - public : Ttype_t _type ; +//public : Ttype_t _type ; public : Tcontrol_t _write_rd ; public : Tgeneral_address_t _num_reg_rd ; @@ -37,6 +37,6 @@ Tcontext_t ooo_engine_id, Tpacket_t packet_id , - //Toperation_t operation , - Ttype_t type , +// Toperation_t operation , +// Ttype_t type , Tcontrol_t write_rd , Tgeneral_address_t num_reg_rd , @@ -54,5 +54,5 @@ _packet_id = packet_id ; //_operation = operation ; - _type = type ; + //_type = type ; _write_rd = write_rd ; _num_reg_rd = num_reg_rd ; @@ -74,5 +74,5 @@ << " * _packet_id : " << toString(x._packet_id ) << std::endl //<< " * _operation : " << toString(x._operation ) << std::endl - << " * _type : " << toString(x._type ) << std::endl + //<< " * _type : " << toString(x._type ) << std::endl << " * _write_rd : " << toString(x._write_rd ) << std::endl << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl @@ -132,5 +132,5 @@ ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); +//ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); @@ -141,5 +141,5 @@ ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); @@ -154,5 +154,5 @@ ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); - ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Tgeneral_data_t ); + ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); @@ -193,5 +193,5 @@ INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); - INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); +//INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); @@ -307,5 +307,5 @@ i, //range(rand(),_param->_size_operation ), - range(rand(),_param->_size_type ), + //range(rand(),_param->_size_type ), range(rand(),1 ), range(rand(),_param->_size_general_register), @@ -314,5 +314,5 @@ range(rand(),_param->_size_special_register), range(rand(),_param->_size_special_data ), - range(rand(),_param->_size_exception ), + range(rand(),0 ), range(rand(),1 ), range(rand(),_param->_size_general_data )); @@ -339,5 +339,5 @@ in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); //in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation ); - in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); + //in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Types.h (revision 97) @@ -27,5 +27,5 @@ public : Tpacket_t _packet_id ; //public : Toperation_t _operation ; - public : Ttype_t _type ; +//public : Ttype_t _type ; public : Tcontrol_t _write_rd ; public : Tgeneral_address_t _num_reg_rd ; @@ -42,6 +42,6 @@ Tcontext_t ooo_engine_id, Tpacket_t packet_id , - //Toperation_t operation , - Ttype_t type , +// Toperation_t operation , +// Ttype_t type , Tcontrol_t write_rd , Tgeneral_address_t num_reg_rd , @@ -59,5 +59,5 @@ _packet_id = packet_id ; //_operation = operation ; - _type = type ; + //_type = type ; _write_rd = write_rd ; _num_reg_rd = num_reg_rd ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h (revision 97) @@ -76,5 +76,5 @@ public : SC_IN (Tpacket_t ) * in_WRITE_QUEUE_IN_PACKET_ID ; //public : SC_IN (Toperation_t ) * in_WRITE_QUEUE_IN_OPERATION ; - public : SC_IN (Ttype_t ) * in_WRITE_QUEUE_IN_TYPE ; +//public : SC_IN (Ttype_t ) * in_WRITE_QUEUE_IN_TYPE ; public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_WRITE_RD ; public : SC_IN (Tgeneral_address_t) * in_WRITE_QUEUE_IN_NUM_REG_RD ; @@ -85,5 +85,5 @@ public : SC_IN (Texception_t ) * in_WRITE_QUEUE_IN_EXCEPTION ; public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_NO_SEQUENCE ; - public : SC_IN (Tgeneral_data_t ) * in_WRITE_QUEUE_IN_ADDRESS ; + public : SC_IN (Taddress_t ) * in_WRITE_QUEUE_IN_ADDRESS ; // -----[ Interface "Write_queue_out" ]------------------------------- @@ -99,5 +99,5 @@ public : SC_OUT(Texception_t ) * out_WRITE_QUEUE_OUT_EXCEPTION ; public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_NO_SEQUENCE ; - public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_DATA ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Parameters.cpp (revision 97) @@ -50,4 +50,5 @@ if (is_toplevel) { + _size_instruction_address= size_general_data-2; _size_context_id = log2(_nb_context ); _size_front_end_id = log2(_nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_allocation.cpp (revision 97) @@ -60,5 +60,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); +// ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); @@ -69,5 +69,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); } @@ -87,5 +87,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_deallocation.cpp (revision 97) @@ -41,5 +41,5 @@ delete in_WRITE_QUEUE_IN_PACKET_ID ; // delete in_WRITE_QUEUE_IN_OPERATION ; - delete in_WRITE_QUEUE_IN_TYPE ; +// delete in_WRITE_QUEUE_IN_TYPE ; delete in_WRITE_QUEUE_IN_WRITE_RD ; delete in_WRITE_QUEUE_IN_NUM_REG_RD ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_transition.cpp (revision 97) @@ -53,5 +53,5 @@ (_param->_have_port_rob_ptr )?PORT_READ(in_WRITE_QUEUE_IN_PACKET_ID ):0, //PORT_READ(in_WRITE_QUEUE_IN_OPERATION ), - PORT_READ(in_WRITE_QUEUE_IN_TYPE ), + //PORT_READ(in_WRITE_QUEUE_IN_TYPE ), PORT_READ(in_WRITE_QUEUE_IN_WRITE_RD ), PORT_READ(in_WRITE_QUEUE_IN_NUM_REG_RD ), @@ -72,6 +72,6 @@ if ( (internal_WRITE_QUEUE_OUT_VAL and PORT_READ(in_WRITE_QUEUE_OUT_ACK)) or ((_queue->empty() == false) and - (_queue->front()->_type == TYPE_MEMORY) and - (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and +// (_queue->front()->_type == TYPE_MEMORY) and + (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE) and // this exception code must be uniq (_queue->front()->_write_rd == 0) and (_queue->front()->_write_re == 0))) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h (revision 97) @@ -71,5 +71,5 @@ public : SC_IN (Tpacket_t ) * in_WRITE_UNIT_IN_PACKET_ID ; //public : SC_IN (Toperation_t ) * in_WRITE_UNIT_IN_OPERATION ; - public : SC_IN (Ttype_t ) * in_WRITE_UNIT_IN_TYPE ; +//public : SC_IN (Ttype_t ) * in_WRITE_UNIT_IN_TYPE ; public : SC_IN (Tcontrol_t ) * in_WRITE_UNIT_IN_WRITE_RD ; public : SC_IN (Tgeneral_address_t) * in_WRITE_UNIT_IN_NUM_REG_RD ; @@ -80,5 +80,5 @@ public : SC_IN (Texception_t ) * in_WRITE_UNIT_IN_EXCEPTION ; public : SC_IN (Tcontrol_t ) * in_WRITE_UNIT_IN_NO_SEQUENCE ; - public : SC_IN (Tgeneral_data_t ) * in_WRITE_UNIT_IN_ADDRESS ; + public : SC_IN (Taddress_t ) * in_WRITE_UNIT_IN_ADDRESS ; // -----[ Interface "write_unit_out" ]-------------------------------- @@ -94,5 +94,5 @@ public : SC_OUT(Texception_t ) * out_WRITE_UNIT_OUT_EXCEPTION ; public : SC_OUT(Tcontrol_t ) * out_WRITE_UNIT_OUT_NO_SEQUENCE ; - public : SC_OUT(Tgeneral_data_t ) * out_WRITE_UNIT_OUT_ADDRESS ; + public : SC_OUT(Taddress_t ) * out_WRITE_UNIT_OUT_ADDRESS ; public : SC_OUT(Tgeneral_data_t ) * out_WRITE_UNIT_OUT_DATA ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Parameters.cpp (revision 97) @@ -73,4 +73,5 @@ if (is_toplevel) { + _size_instruction_address = size_general_data-2; _size_context_id = log2(_nb_context ); _size_front_end_id = log2(_nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp (revision 97) @@ -66,5 +66,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); // ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); +// ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); @@ -75,5 +75,5 @@ ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); } @@ -93,5 +93,5 @@ ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data ); + ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); } @@ -206,5 +206,5 @@ _component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" ); //_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" ); - _component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" ); + //_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" ); _component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD" , _name, "in_WRITE_UNIT_IN_WRITE_RD" ); _component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD" , _name, "in_WRITE_UNIT_IN_NUM_REG_RD" ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_deallocation.cpp (revision 97) @@ -40,5 +40,5 @@ delete in_WRITE_UNIT_IN_PACKET_ID ; // delete in_WRITE_UNIT_IN_OPERATION ; - delete in_WRITE_UNIT_IN_TYPE ; +// delete in_WRITE_UNIT_IN_TYPE ; delete in_WRITE_UNIT_IN_WRITE_RD ; delete in_WRITE_UNIT_IN_NUM_REG_RD ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/SelfTest/src/test.cpp (revision 97) @@ -20,5 +20,5 @@ public : Tpacket_t _packet_id ; //public : Toperation_t _operation ; - public : Ttype_t _type ; +//public : Ttype_t _type ; public : Tcontrol_t _write_rd ; public : Tgeneral_address_t _num_reg_rd ; @@ -36,5 +36,5 @@ Tpacket_t packet_id , // Toperation_t operation , - Ttype_t type , +// Ttype_t type , Tcontrol_t write_rd , Tgeneral_address_t num_reg_rd , @@ -52,5 +52,5 @@ _packet_id = packet_id ; // _operation = operation ; - _type = type ; +// _type = type ; _write_rd = write_rd ; _num_reg_rd = num_reg_rd ; @@ -108,5 +108,5 @@ ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ," in_EXECUTE_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); //ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ," in_EXECUTE_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); - ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ," in_EXECUTE_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ," in_EXECUTE_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ," in_EXECUTE_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ," in_EXECUTE_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); @@ -117,5 +117,5 @@ ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_EXCEPTION ," in_EXECUTE_UNIT_OUT_EXCEPTION ",Texception_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ," in_EXECUTE_UNIT_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); - ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_ADDRESS ," in_EXECUTE_UNIT_OUT_ADDRESS ",Taddress_t ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_VAL ,"out_WRITE_UNIT_IN_VAL ",Tcontrol_t ,_param->_nb_write_unit ); @@ -126,5 +126,5 @@ ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID ,"out_WRITE_UNIT_IN_PACKET_ID ",Tpacket_t ,_param->_nb_write_unit ); //ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_OPERATION ,"out_WRITE_UNIT_IN_OPERATION ",Toperation_t ,_param->_nb_write_unit ); - ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,"out_WRITE_UNIT_IN_TYPE ",Ttype_t ,_param->_nb_write_unit ); +//ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,"out_WRITE_UNIT_IN_TYPE ",Ttype_t ,_param->_nb_write_unit ); ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD ,"out_WRITE_UNIT_IN_WRITE_RD ",Tcontrol_t ,_param->_nb_write_unit ); ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD ,"out_WRITE_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_write_unit ); @@ -135,5 +135,5 @@ ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_EXCEPTION ,"out_WRITE_UNIT_IN_EXCEPTION ",Texception_t ,_param->_nb_write_unit ); ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_NO_SEQUENCE ,"out_WRITE_UNIT_IN_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_write_unit ); - ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_ADDRESS ,"out_WRITE_UNIT_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_write_unit ); + ALLOC1_SC_SIGNAL(out_WRITE_UNIT_IN_ADDRESS ,"out_WRITE_UNIT_IN_ADDRESS ",Taddress_t ,_param->_nb_write_unit ); /******************************************************** @@ -157,5 +157,5 @@ INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); //INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); - INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); INSTANCE2_SC_SIGNAL(_Execution_unit_to_Write_unit, in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); @@ -179,5 +179,5 @@ INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); //INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); - INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); +//INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_WRITE_RD ,_param->_nb_write_unit ); INSTANCE1_SC_SIGNAL(_Execution_unit_to_Write_unit,out_WRITE_UNIT_IN_NUM_REG_RD ,_param->_nb_write_unit ); @@ -265,6 +265,6 @@ ooo_engine_id, nb_request_in, - //range (rand(), _param->_size_operation ), - range (rand(), _param->_size_type ), +// range (rand(), _param->_size_operation ), +// range (rand(), _param->_size_type ), range (rand(), 2 ), range (rand(), _param->_size_general_register), @@ -299,5 +299,5 @@ in_EXECUTE_UNIT_OUT_PACKET_ID [i][j] ->write(request[i][j].front()._packet_id ); // in_EXECUTE_UNIT_OUT_OPERATION [i][j] ->write(request[i][j].front()._operation ); - in_EXECUTE_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type ); +// in_EXECUTE_UNIT_OUT_TYPE [i][j] ->write(request[i][j].front()._type ); in_EXECUTE_UNIT_OUT_WRITE_RD [i][j] ->write(request[i][j].front()._write_rd ); in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j] ->write(request[i][j].front()._num_reg_rd ); @@ -367,5 +367,5 @@ TEST(Tcontext_t ,out_WRITE_UNIT_IN_OOO_ENGINE_ID [i]->read(), request[x][y].front()._ooo_engine_id ); // TEST(Toperation_t ,out_WRITE_UNIT_IN_OPERATION [i]->read(), request[x][y].front()._operation ); - TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[x][y].front()._type ); +// TEST(Ttype_t ,out_WRITE_UNIT_IN_TYPE [i]->read(), request[x][y].front()._type ); TEST(Tcontrol_t ,out_WRITE_UNIT_IN_WRITE_RD [i]->read(), request[x][y].front()._write_rd ); TEST(Tgeneral_address_t,out_WRITE_UNIT_IN_NUM_REG_RD [i]->read(), request[x][y].front()._num_reg_rd ); @@ -404,5 +404,5 @@ DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); //DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); - DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); +//DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); DELETE2_SC_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,_param->_nb_execute_unit,_param->_nb_execute_unit_port[it1]); @@ -422,5 +422,5 @@ DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID ,_param->_nb_write_unit ); //DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_OPERATION ,_param->_nb_write_unit ); - DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); +//DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_TYPE ,_param->_nb_write_unit ); DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD ,_param->_nb_write_unit ); DELETE1_SC_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD ,_param->_nb_write_unit ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/include/Execution_unit_to_Write_unit.h (revision 97) @@ -72,5 +72,5 @@ public : SC_IN (Tpacket_t ) *** in_EXECUTE_UNIT_OUT_PACKET_ID ; //public : SC_IN (Toperation_t ) *** in_EXECUTE_UNIT_OUT_OPERATION ; - public : SC_IN (Ttype_t ) *** in_EXECUTE_UNIT_OUT_TYPE ; +//public : SC_IN (Ttype_t ) *** in_EXECUTE_UNIT_OUT_TYPE ; public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_WRITE_RD ; public : SC_IN (Tgeneral_address_t) *** in_EXECUTE_UNIT_OUT_NUM_REG_RD ; @@ -81,5 +81,5 @@ public : SC_IN (Texception_t ) *** in_EXECUTE_UNIT_OUT_EXCEPTION ; public : SC_IN (Tcontrol_t ) *** in_EXECUTE_UNIT_OUT_NO_SEQUENCE ; - public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_UNIT_OUT_ADDRESS ; + public : SC_IN (Taddress_t ) *** in_EXECUTE_UNIT_OUT_ADDRESS ; // ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -91,5 +91,5 @@ public : SC_OUT(Tpacket_t ) ** out_WRITE_UNIT_IN_PACKET_ID ; //public : SC_OUT(Toperation_t ) ** out_WRITE_UNIT_IN_OPERATION ; - public : SC_OUT(Ttype_t ) ** out_WRITE_UNIT_IN_TYPE ; +//public : SC_OUT(Ttype_t ) ** out_WRITE_UNIT_IN_TYPE ; public : SC_OUT(Tcontrol_t ) ** out_WRITE_UNIT_IN_WRITE_RD ; public : SC_OUT(Tgeneral_address_t) ** out_WRITE_UNIT_IN_NUM_REG_RD ; @@ -100,5 +100,5 @@ public : SC_OUT(Texception_t ) ** out_WRITE_UNIT_IN_EXCEPTION ; public : SC_OUT(Tcontrol_t ) ** out_WRITE_UNIT_IN_NO_SEQUENCE ; - public : SC_OUT(Tgeneral_data_t ) ** out_WRITE_UNIT_IN_ADDRESS ; + public : SC_OUT(Taddress_t ) ** out_WRITE_UNIT_IN_ADDRESS ; // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_allocation.cpp (revision 97) @@ -67,5 +67,5 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); //_ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); - _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + //_ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); @@ -76,5 +76,5 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); - _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address, _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1]); } @@ -90,5 +90,5 @@ ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); //ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); - ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); + //ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); @@ -99,5 +99,5 @@ ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); } // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_deallocation.cpp (revision 97) @@ -36,5 +36,5 @@ DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_PACKET_ID , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_rob_ptr ); // DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_OPERATION , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_operation ); - DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_type ); + // DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_TYPE , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_type ); DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_WRITE_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],1 ); DELETE2_SIGNAL( in_EXECUTE_UNIT_OUT_NUM_REG_RD , _param->_nb_execute_unit, _param->_nb_execute_unit_port[it1],_param->_size_general_register); @@ -54,5 +54,5 @@ DELETE1_SIGNAL(out_WRITE_UNIT_IN_PACKET_ID , _param->_nb_write_unit,_param->_size_rob_ptr ); // DELETE1_SIGNAL(out_WRITE_UNIT_IN_OPERATION , _param->_nb_write_unit,_param->_size_operation ); - DELETE1_SIGNAL(out_WRITE_UNIT_IN_TYPE , _param->_nb_write_unit,_param->_size_type ); + // DELETE1_SIGNAL(out_WRITE_UNIT_IN_TYPE , _param->_nb_write_unit,_param->_size_type ); DELETE1_SIGNAL(out_WRITE_UNIT_IN_WRITE_RD , _param->_nb_write_unit,1 ); DELETE1_SIGNAL(out_WRITE_UNIT_IN_NUM_REG_RD , _param->_nb_write_unit,_param->_size_general_register); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Execution_unit_to_Write_unit_genMealy.cpp (revision 97) @@ -75,6 +75,6 @@ if (_param->_have_port_rob_ptr ) PORT_WRITE(out_WRITE_UNIT_IN_PACKET_ID [dest], PORT_READ(in_EXECUTE_UNIT_OUT_PACKET_ID [i][j])); - // PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i][j])); - PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i][j])); +// PORT_WRITE(out_WRITE_UNIT_IN_OPERATION [dest], PORT_READ(in_EXECUTE_UNIT_OUT_OPERATION [i][j])); +// PORT_WRITE(out_WRITE_UNIT_IN_TYPE [dest], PORT_READ(in_EXECUTE_UNIT_OUT_TYPE [i][j])); PORT_WRITE(out_WRITE_UNIT_IN_WRITE_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_WRITE_RD [i][j])); PORT_WRITE(out_WRITE_UNIT_IN_NUM_REG_RD [dest], PORT_READ(in_EXECUTE_UNIT_OUT_NUM_REG_RD [i][j])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Execution_unit_to_Write_unit/src/Parameters.cpp (revision 97) @@ -58,4 +58,5 @@ if (is_toplevel) { + _size_instruction_address= size_general_data-2; _size_context_id = log2(nb_context ); _size_front_end_id = log2(nb_front_end ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Parameters_msg_error.cpp (revision 97) @@ -95,5 +95,5 @@ // Test uniq type if (type_present [j][k] and type_uniq[k]) - test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString_type(k).c_str(),j)); + test.error(toString(_("The execute_unit '%d' can execute operation of type '%s' at the thread '%d'. But an another execute_unit can be execute the same type for the same thread. And the type must be single !.\n"),i,toString(k).c_str(),j)); type_present [j][k] = true; @@ -104,5 +104,5 @@ for (uint32_t i=0; i<_nb_thread; i++) if (type_present [i][j]) - test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString_type(j).c_str())); + test.error(toString(_("The thread '%d' can execute the type's operation '%s' but this type is invalid.\n"),i,toString(j).c_str())); for (Ttype_t j=0; j<_nb_type; j++) @@ -110,5 +110,5 @@ for (uint32_t i=0; i<_nb_thread; i++) if (not type_present [i][j]) - test.error(toString(_("The thread '%d' can't access at the execute_unit to execute the type's operation '%s' (and this type is not optional !).\n"),i,toString_type(j).c_str())); + test.error(toString(_("The thread '%d' can't access at the execute_unit to execute the type's operation '%s' (and this type is not optional !).\n"),i,toString(j).c_str())); // Test all excluve type @@ -119,5 +119,5 @@ if ((j != k) and (_table_execute_type[i][k] == true)) { - test.error(toString(_("The execute_unit [%d] implement the type '%s', and this type is exclusive with all others type.\n"),i,toString_type(j).c_str())); + test.error(toString(_("The execute_unit [%d] implement the type '%s', and this type is exclusive with all others type.\n"),i,toString(j).c_str())); break; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Network/Read_unit_to_Execution_unit/src/Read_unit_to_Execution_unit_genMealy.cpp (revision 97) @@ -51,5 +51,5 @@ #ifdef DEBUG_TEST if (_destination[i][num_thread][type].empty()) - throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString_type(type)+"]."); + throw ERRORMORPHEO(FUNCTION,"Invalid Operation : They have no execute_unit to receive a operation from the read_unit ["+toString(i)+"], thread ["+toString(num_thread)+"] and a operation's type ["+toString(type)+"]."); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/src/test.cpp (revision 97) @@ -84,5 +84,5 @@ ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_EXCEPTION ,"out_EXECUTE_LOOP_OUT_EXCEPTION ",Texception_t ,_param->_nb_write_unit); ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"out_EXECUTE_LOOP_OUT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_write_unit); - ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,"out_EXECUTE_LOOP_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_write_unit); + ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_ADDRESS ,"out_EXECUTE_LOOP_OUT_ADDRESS ",Taddress_t ,_param->_nb_write_unit); ALLOC1_SC_SIGNAL(out_EXECUTE_LOOP_OUT_DATA ,"out_EXECUTE_LOOP_OUT_DATA ",Tgeneral_data_t ,_param->_nb_write_unit); ALLOC2_SC_SIGNAL(out_DCACHE_REQ_VAL ,"out_DCACHE_REQ_VAL ",Tcontrol_t ,_param->_nb_load_store_unit,_param->_nb_cache_port[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h (revision 97) @@ -107,5 +107,5 @@ public : SC_OUT(Texception_t ) ** out_EXECUTE_LOOP_OUT_EXCEPTION ;//[nb_write_unit] public : SC_OUT(Tcontrol_t ) ** out_EXECUTE_LOOP_OUT_NO_SEQUENCE ;//[nb_write_unit] - public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_LOOP_OUT_ADDRESS ;//[nb_write_unit] + public : SC_OUT(Taddress_t ) ** out_EXECUTE_LOOP_OUT_ADDRESS ;//[nb_write_unit] public : SC_OUT(Tgeneral_data_t ) ** out_EXECUTE_LOOP_OUT_DATA ;//[nb_write_unit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp (revision 97) @@ -96,5 +96,5 @@ ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception); ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); - ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data); } @@ -850,6 +850,6 @@ // COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_OPERATION" , // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_OPERATION" ); - COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_TYPE" ); +// COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" , +// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_TYPE" ); COMPONENT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RD" , dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_0_WRITE_RD" ); @@ -975,6 +975,6 @@ // COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_OPERATION" , // dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_OPERATION" ); - COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_TYPE" , - dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_TYPE" ); +// COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_TYPE" , +// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_TYPE" ); COMPONENT_MAP(_component ,src ,"out_MEMORY_OUT_"+toString(j)+"_WRITE_RD" , dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_"+toString(j)+"_WRITE_RD" ); @@ -1085,6 +1085,6 @@ // COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_OPERATION" , // dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" ); - COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" , - dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ); +// COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" , +// dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ); COMPONENT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RD" , dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" ); @@ -1597,6 +1597,6 @@ // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , // // dest,"out_EXECUTE_OUT_OPERATION" ); -// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , -// dest,"out_EXECUTE_OUT_TYPE" ); +// // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , +// // dest,"out_EXECUTE_OUT_TYPE" ); // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , // dest,"out_EXECUTE_OUT_WRITE_RD" ); @@ -1644,6 +1644,6 @@ // // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" , // // dest,"out_MEMORY_OUT_OPERATION" ); -// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , -// dest,"out_MEMORY_OUT_TYPE" ); +// // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" , +// // dest,"out_MEMORY_OUT_TYPE" ); // PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" , // dest,"out_MEMORY_OUT_WRITE_RD" ); @@ -1695,6 +1695,6 @@ // // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" , // // dest, "in_WRITE_UNIT_IN_OPERATION" ); -// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" , -// dest, "in_WRITE_UNIT_IN_TYPE" ); +// // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" , +// // dest, "in_WRITE_UNIT_IN_TYPE" ); // PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" , // dest, "in_WRITE_UNIT_IN_WRITE_RD" ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Parameters.cpp (revision 97) @@ -156,5 +156,5 @@ if (timing[x][j][k]._latence > 0) { - log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString_type(j).c_str()); + log_printf(TRACE,Execute_loop,FUNCTION,"Execute unit '%d' (functional unit '%d') can execute type '%s'.",i,x,toString(j).c_str()); _read_unit_to_execution_unit_table_execute_type [i][j] = true; break; // find an operation @@ -524,4 +524,5 @@ if (is_toplevel) { + _size_instruction_address= size_general_data-2; _size_context_id = log2(nb_context); _size_front_end_id = log2(nb_front_end); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 97) @@ -75,5 +75,5 @@ ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); + ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -97,5 +97,7 @@ ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context ); ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context ); - + ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context ); + ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context ); ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context ); @@ -177,4 +179,7 @@ INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context ); + INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context ); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context ); INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context ); @@ -1273,4 +1278,6 @@ DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context ); DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context ); + DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context ); DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context ); DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 97) @@ -93,5 +93,5 @@ public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EPCR ; public : SC_IN (Tcontrol_t ) * in_COMMIT_EVENT_ADDRESS_EEAR_VAL ; - public : SC_IN (Taddress_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; + public : SC_IN (Tgeneral_data_t ) * in_COMMIT_EVENT_ADDRESS_EEAR ; // ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 97) @@ -97,5 +97,5 @@ ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); } @@ -133,4 +133,7 @@ ALLOC1_SIGNAL_OUT(out_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t ,1); ALLOC1_SIGNAL_OUT(out_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type); + ALLOC1_SIGNAL_OUT(out_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 97) @@ -76,5 +76,7 @@ DELETE1_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context,1); - + DELETE1_SIGNAL(out_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type); + DELETE1_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context,1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp (revision 97) @@ -38,12 +38,27 @@ // SR can't change in this cycle // Exception Prefix High - Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); - Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; - Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); - Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); + Taddress_t address = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0); + Taddress_t address_next = reg_EVENT_ADDRESS_EPCR [i]; + Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]); + Tcontrol_t is_ds_take = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE [i]); // excep : address exception // miss : address delay_slot, and address dest // psync : address next // csync : address next + Tevent_type_t type ;//[nb_context] + Tdepth_t depth = reg_EVENT_DEPTH [i]; + + switch (state) + { + case CONTEXT_STATE_KO_EXCEP_ADDR : (type = EVENT_TYPE_EXCEPTION ); break; + case CONTEXT_STATE_KO_MISS_ADDR : (type = EVENT_TYPE_MISS_SPECULATION ); break; + case CONTEXT_STATE_KO_PSYNC_ADDR : (type = EVENT_TYPE_PSYNC ); break; + case CONTEXT_STATE_KO_CSYNC_ADDR : (type = EVENT_TYPE_CSYNC ); break; + default : (type = EVENT_TYPE_NONE ); break; + } +// (type = EVENT_TYPE_SPR_ACCESS ); +// (type = EVENT_TYPE_MSYNC ); +// (type = EVENT_TYPE_BRANCH_NO_ACCURATE); + internal_EVENT_VAL [i] = val; PORT_WRITE(out_EVENT_VAL [i], val); @@ -52,4 +67,7 @@ PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val); PORT_WRITE(out_EVENT_IS_DS_TAKE [i], is_ds_take); + PORT_WRITE(out_EVENT_TYPE [i], type); + if (_param->_have_port_depth) + PORT_WRITE(out_EVENT_DEPTH [i], depth); log_printf(TRACE,Context_State,FUNCTION," * EVENT Context : %d", i); @@ -59,4 +77,6 @@ log_printf(TRACE,Context_State,FUNCTION," * ADDRESS_NEXT_VAL : %d", address_next_val); log_printf(TRACE,Context_State,FUNCTION," * IS_DS_TAKE : %d", is_ds_take); + log_printf(TRACE,Context_State,FUNCTION," * TYPE : %d", type); + log_printf(TRACE,Context_State,FUNCTION," * DEPTH : %d", depth); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp (revision 97) @@ -255,11 +255,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -271,5 +271,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -283,5 +283,5 @@ inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 1; inst->_num_reg_ra = range(inst->_instruction,20,16); @@ -299,5 +299,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -315,7 +315,7 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -327,5 +327,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -343,5 +343,5 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; + inst->_num_reg_rb = 0; //unnecessary inst->_read_rc = 1; inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV; @@ -355,5 +355,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -367,21 +367,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -399,17 +399,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -428,13 +428,13 @@ inst->_immediat = address_next; inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary inst->_read_rc = 1; inst->_num_reg_rc = SPR_LOGIC_SR_F; inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -460,7 +460,7 @@ inst->_immediat = address_next; inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary inst->_read_rc = 1; inst->_num_reg_rc = SPR_LOGIC_SR_F; @@ -468,5 +468,5 @@ inst->_num_reg_rd = range(inst->_instruction,25,21); inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -486,5 +486,5 @@ inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 1; inst->_num_reg_ra = range(inst->_instruction,20,16); @@ -496,11 +496,11 @@ inst->_num_reg_rd = range(inst->_instruction,25,21); inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -520,21 +520,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_CSYNC; @@ -558,11 +558,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -574,5 +574,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -586,11 +586,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -602,5 +602,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -618,17 +618,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -646,17 +646,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -674,17 +674,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -702,17 +702,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -730,17 +730,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -758,17 +758,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -782,21 +782,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -810,21 +810,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -838,15 +838,15 @@ inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -869,13 +869,13 @@ inst->_immediat = inst->_address_next+1; inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = 9; // Link register inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -904,15 +904,15 @@ inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; + inst->_num_reg_ra = 0; //unnecessary inst->_read_rb = 1; // inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = 9; // Link register inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -921,5 +921,5 @@ // inst->_branch_stack_write = 1; inst->_branch_direction = 1; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -934,15 +934,15 @@ inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_NONE; inst->_exception = EXCEPTION_DECOD_NONE; @@ -950,5 +950,5 @@ // inst->_branch_stack_write = 0; inst->_branch_direction = 1; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -966,11 +966,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -978,5 +978,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -994,11 +994,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1006,5 +1006,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1022,11 +1022,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1034,5 +1034,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1050,11 +1050,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1062,5 +1062,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1078,11 +1078,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1090,5 +1090,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1106,11 +1106,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1118,5 +1118,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1134,11 +1134,11 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1146,5 +1146,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1158,21 +1158,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1191,17 +1191,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1221,21 +1221,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1254,17 +1254,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1280,19 +1280,19 @@ inst->_immediat = EXTENDZ(inst->_instruction,16); inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1306,21 +1306,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1340,21 +1340,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_MSYNC; @@ -1376,15 +1376,15 @@ inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_SPR_ACCESS; @@ -1398,11 +1398,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -1414,5 +1414,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1430,7 +1430,7 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -1442,5 +1442,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1454,11 +1454,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -1470,5 +1470,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1484,21 +1484,21 @@ // inst->_immediat = EXTENDZ(inst->_instruction,16); inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; @@ -1512,21 +1512,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1544,17 +1544,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1574,21 +1574,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_PSYNC; @@ -1603,21 +1603,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; // don't change + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage @@ -1631,21 +1631,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1663,17 +1663,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1694,9 +1694,9 @@ inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1704,5 +1704,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1723,9 +1723,9 @@ inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -1733,5 +1733,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1745,13 +1745,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1761,5 +1761,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1777,9 +1777,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1789,5 +1789,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1801,13 +1801,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1817,5 +1817,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1833,9 +1833,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1845,5 +1845,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1857,13 +1857,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1873,5 +1873,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1889,9 +1889,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1901,5 +1901,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1913,13 +1913,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1929,5 +1929,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1945,9 +1945,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1957,5 +1957,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -1969,13 +1969,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -1985,5 +1985,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2001,9 +2001,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2013,5 +2013,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2025,13 +2025,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2041,5 +2041,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2057,9 +2057,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2069,5 +2069,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2081,13 +2081,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2097,5 +2097,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2113,9 +2113,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2125,5 +2125,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2137,13 +2137,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2153,5 +2153,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2169,9 +2169,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2181,5 +2181,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2193,13 +2193,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2209,5 +2209,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2225,9 +2225,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2237,5 +2237,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2249,13 +2249,13 @@ inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2265,5 +2265,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2281,9 +2281,9 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary inst->_write_re = 1; inst->_num_reg_re = SPR_LOGIC_SR_F; @@ -2293,5 +2293,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2312,9 +2312,9 @@ inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -2322,5 +2322,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2334,21 +2334,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2366,17 +2366,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2390,21 +2390,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2422,17 +2422,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2446,21 +2446,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2478,17 +2478,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2502,11 +2502,11 @@ inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary inst->_write_rd = 1; inst->_num_reg_rd = range(inst->_instruction,25,21); @@ -2518,5 +2518,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2537,9 +2537,9 @@ inst->_num_reg_rb = range(inst->_instruction,15,11); inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; inst->_exception = EXCEPTION_DECOD_NONE; @@ -2547,5 +2547,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2567,15 +2567,15 @@ // inst->_immediat = EXTENDZ(inst->_instruction,16); inst->_has_immediat = 0; -// inst->_immediat = ; + inst->_immediat = 0; // unnecessary inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_SYSCALL; inst->_exception = EXCEPTION_SYSCALL; @@ -2590,5 +2590,5 @@ -// inst->_address_next = ; // don't change +// inst->_address_next = ; // already define : PC+4 // don't change inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_EXCEPTION; @@ -2611,13 +2611,13 @@ inst->_immediat = EXTENDZ(inst->_instruction,16); inst->_read_ra = 0; -// inst->_num_reg_ra = ; - inst->_read_rb = 0; -// inst->_num_reg_rb = ; + inst->_num_reg_ra = 0; //unnecessary + inst->_read_rb = 0; + inst->_num_reg_rb = 0; //unnecessary inst->_read_rc = 0; // read all SR -// inst->_num_reg_rc = ; - inst->_write_rd = 0; -// inst->_num_reg_rd = ; - inst->_write_re = 0; -// inst->_num_reg_re = ; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 0; + inst->_num_reg_rd = 0; //unnecessary + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary inst->_exception_use = EXCEPTION_USE_TRAP; inst->_exception = EXCEPTION_DECOD_NONE; @@ -2625,5 +2625,5 @@ // inst->_branch_stack_write = ; // inst->_branch_direction = ; -// inst->_address_next = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 1; inst->_event_type = EVENT_TYPE_NONE; @@ -2638,21 +2638,21 @@ inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; inst->_has_immediat = 0; -// inst->_immediat = ; - inst->_read_ra = 1; - inst->_num_reg_ra = range(inst->_instruction,20,16); - inst->_read_rb = 1; - inst->_num_reg_rb = range(inst->_instruction,15,11); - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_immediat = 0; // unnecessary + inst->_read_ra = 1; + inst->_num_reg_ra = range(inst->_instruction,20,16); + inst->_read_rb = 1; + inst->_num_reg_rb = range(inst->_instruction,15,11); + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; @@ -2670,17 +2670,17 @@ inst->_num_reg_ra = range(inst->_instruction,20,16); inst->_read_rb = 0; -// inst->_num_reg_rb = ; - inst->_read_rc = 0; -// inst->_num_reg_rc = ; - inst->_write_rd = 1; - inst->_num_reg_rd = range(inst->_instruction,25,21); - inst->_write_re = 0; -// inst->_num_reg_re = ; - inst->_exception_use = EXCEPTION_USE_NONE; - inst->_exception = EXCEPTION_DECOD_NONE; -// inst->_branch_condition = ; -// inst->_branch_stack_write = ; -// inst->_branch_direction = ; -// inst->_address_next = ; + inst->_num_reg_rb = 0; //unnecessary + inst->_read_rc = 0; + inst->_num_reg_rc = 0; //unnecessary + inst->_write_rd = 1; + inst->_num_reg_rd = range(inst->_instruction,25,21); + inst->_write_re = 0; + inst->_num_reg_re = 0; //unnecessary + inst->_exception_use = EXCEPTION_USE_NONE; + inst->_exception = EXCEPTION_DECOD_NONE; +// inst->_branch_condition = ; +// inst->_branch_stack_write = ; +// inst->_branch_direction = ; +// inst->_address_next = ; // already define : PC+4 inst->_no_execute = 0; inst->_event_type = EVENT_TYPE_NONE; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/SelfTest/src/test.cpp (revision 97) @@ -75,4 +75,8 @@ ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); ALLOC1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"out_EVENT_IFETCH_UNIT_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,"out_EVENT_PREDICTION_UNIT_VAL ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ," in_EVENT_PREDICTION_UNIT_ACK ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,"out_EVENT_PREDICTION_UNIT_TYPE ",Tevent_type_t,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,"out_EVENT_PREDICTION_UNIT_DEPTH ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ," in_EVENT_CONTEXT_STATE_VAL ",Tcontrol_t,_param->_nb_context); ALLOC1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,"out_EVENT_CONTEXT_STATE_ACK ",Tcontrol_t,_param->_nb_context); @@ -81,4 +85,6 @@ ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ," in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ",Tcontrol_t,_param->_nb_context); ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ," in_EVENT_CONTEXT_STATE_IS_DS_TAKE ",Tcontrol_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ," in_EVENT_CONTEXT_STATE_TYPE ",Tevent_type_t,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ," in_EVENT_CONTEXT_STATE_DEPTH ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); @@ -132,4 +138,9 @@ INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue,out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); @@ -138,4 +149,7 @@ INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Front_end_Glue, in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); for (uint32_t i=0; i<_param->_nb_context; ++i) @@ -230,4 +244,8 @@ DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context); @@ -236,4 +254,6 @@ DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context); DELETE1_SC_SIGNAL(out_DEPTH_MIN ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/include/Front_end_Glue.h (revision 97) @@ -97,4 +97,9 @@ public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ;//[nb_context] public : SC_OUT(Tcontrol_t ) ** out_EVENT_IFETCH_UNIT_IS_DS_TAKE ;//[nb_context] + + public : SC_OUT(Tcontrol_t ) ** out_EVENT_PREDICTION_UNIT_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_PREDICTION_UNIT_ACK ;//[nb_context] + public : SC_OUT(Tevent_type_t ) ** out_EVENT_PREDICTION_UNIT_TYPE ;//[nb_context] + public : SC_OUT(Tdepth_t ) ** out_EVENT_PREDICTION_UNIT_DEPTH ;//[nb_context] public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_VAL ;//[nb_context] @@ -104,4 +109,6 @@ public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ;//[nb_context] public : SC_IN (Tcontrol_t ) ** in_EVENT_CONTEXT_STATE_IS_DS_TAKE ;//[nb_context] + public : SC_IN (Tevent_type_t ) ** in_EVENT_CONTEXT_STATE_TYPE ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_EVENT_CONTEXT_STATE_DEPTH ;//[nb_context] // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue.cpp (revision 97) @@ -138,11 +138,17 @@ // sensitive << (*(in_CLOCK)).neg(); // don't need internal register for (uint32_t i=0; i<_param->_nb_context; ++i) - sensitive << (*( in_EVENT_ACK [i])) - << (*( in_EVENT_IFETCH_UNIT_ACK [i])) - << (*( in_EVENT_CONTEXT_STATE_VAL [i])) - << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) - << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) - << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) - << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])); + { + sensitive << (*( in_EVENT_ACK [i])) + << (*( in_EVENT_IFETCH_UNIT_ACK [i])) + << (*( in_EVENT_PREDICTION_UNIT_ACK [i])) + << (*( in_EVENT_CONTEXT_STATE_VAL [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i])) + << (*( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i])) + << (*( in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i])) + << (*( in_EVENT_CONTEXT_STATE_TYPE [i])); + if (_param->_have_port_depth) + sensitive << (*( in_EVENT_CONTEXT_STATE_DEPTH [i])); + } # ifdef SYSTEMCASS_SPECIFIC Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_allocation.cpp (revision 97) @@ -105,4 +105,9 @@ ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,"IFETCH_UNIT_ADDRESS_NEXT_VAL" ,Tcontrol_t ,1); ALLOC1_SIGNAL_OUT (out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,"IFETCH_UNIT_IS_DS_TAKE" ,Tcontrol_t ,1); + + ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_VAL ,"PREDICTION_UNIT_VAL" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_PREDICTION_UNIT_ACK ,"PREDICTION_UNIT_ACK" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_TYPE ,"PREDICTION_UNIT_TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC1_SIGNAL_OUT (out_EVENT_PREDICTION_UNIT_DEPTH ,"PREDICTION_UNIT_DEPTH" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_VAL ,"CONTEXT_STATE_VAL" ,Tcontrol_t ,1); @@ -112,4 +117,7 @@ ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,"CONTEXT_STATE_ADDRESS_NEXT_VAL",Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,"CONTEXT_STATE_IS_DS_TAKE" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_TYPE ,"CONTEXT_STATE_TYPE" ,Tevent_type_t ,_param->_size_event_type); + ALLOC1_SIGNAL_IN ( in_EVENT_CONTEXT_STATE_DEPTH ,"CONTEXT_STATE_DEPTH" ,Tdepth_t ,_param->_size_depth); + } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_deallocation.cpp (revision 97) @@ -55,4 +55,10 @@ DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_EVENT_IFETCH_UNIT_IS_DS_TAKE ,_param->_nb_context,1); + + DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_PREDICTION_UNIT_ACK ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_TYPE ,_param->_nb_context,_param->_size_event_type); + DELETE1_SIGNAL(out_EVENT_PREDICTION_UNIT_DEPTH ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_VAL ,_param->_nb_context,1); DELETE1_SIGNAL(out_EVENT_CONTEXT_STATE_ACK ,_param->_nb_context,1); @@ -61,4 +67,6 @@ DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL ,_param->_nb_context,1); DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_IS_DS_TAKE ,_param->_nb_context,1); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_TYPE ,_param->_nb_context,_param->_size_event_type); + DELETE1_SIGNAL( in_EVENT_CONTEXT_STATE_DEPTH ,_param->_nb_context,_param->_size_depth); DELETE1_SIGNAL(out_DEPTH_MIN ,_param->_nb_context,_param->_size_depth ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Front_end_Glue/src/Front_end_Glue_genMealy_event.cpp (revision 97) @@ -25,27 +25,66 @@ for (uint32_t i=0; i<_param->_nb_context; ++i) { - Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]); + Taddress_t address = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS [i]); PORT_WRITE(out_EVENT_ADDRESS [i],address); PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS [i],address); - Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]); + Taddress_t address_next = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT [i]); PORT_WRITE(out_EVENT_ADDRESS_NEXT [i],address_next); PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT [i],address_next); - Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]); + Tcontrol_t address_next_val = PORT_READ(in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL [i]); PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i],address_next_val); PORT_WRITE(out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL [i],address_next_val); - Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]); + Tcontrol_t is_ds_take = PORT_READ(in_EVENT_CONTEXT_STATE_IS_DS_TAKE [i]); PORT_WRITE(out_EVENT_IS_DS_TAKE [i],is_ds_take); PORT_WRITE(out_EVENT_IFETCH_UNIT_IS_DS_TAKE [i],is_ds_take); - Tcontrol_t val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); - PORT_WRITE(out_EVENT_VAL [i],val); - PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i],val); + Tevent_type_t event_type = PORT_READ(in_EVENT_CONTEXT_STATE_TYPE [i]); + PORT_WRITE(out_EVENT_PREDICTION_UNIT_TYPE [i],event_type); + + if (_param->_have_port_depth) + { + Tdepth_t depth = PORT_READ(in_EVENT_CONTEXT_STATE_DEPTH [i]); + PORT_WRITE(out_EVENT_PREDICTION_UNIT_DEPTH [i],depth); + } + - Tcontrol_t ack = (PORT_READ(in_EVENT_ACK [i]) and - PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i])); - PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i],ack); + Tcontrol_t ack = PORT_READ(in_EVENT_ACK [i]); + Tcontrol_t ifetch_unit_ack = PORT_READ(in_EVENT_IFETCH_UNIT_ACK [i]); + Tcontrol_t prediction_unit_ack = PORT_READ(in_EVENT_PREDICTION_UNIT_ACK [i]); + Tcontrol_t context_state_val = PORT_READ(in_EVENT_CONTEXT_STATE_VAL [i]); + + Tcontrol_t val = (//ack and + ifetch_unit_ack and + prediction_unit_ack and + context_state_val + ); + Tcontrol_t ifetch_unit_val = ( ack and + //ifetch_unit_ack and + prediction_unit_ack and + context_state_val + ); + Tcontrol_t prediction_unit_val = ( ack and + ifetch_unit_ack and + //prediction_unit_ack and + context_state_val + ); + Tcontrol_t context_state_ack = ( ack and + ifetch_unit_ack and + prediction_unit_ack // and + //context_state_val + ); + + log_printf(TRACE,Front_end_Glue,FUNCTION," * val %d, ack %d",val ,ack ); + log_printf(TRACE,Front_end_Glue,FUNCTION," * ifetch_unit_val %d, ifetch_unit_ack %d",ifetch_unit_val ,ifetch_unit_ack ); + log_printf(TRACE,Front_end_Glue,FUNCTION," * prediction_unit_val %d, prediction_unit_ack %d",prediction_unit_val,prediction_unit_ack); + log_printf(TRACE,Front_end_Glue,FUNCTION," * context_state_val %d, context_state_ack %d",context_state_val ,context_state_ack ); + + + PORT_WRITE(out_EVENT_VAL [i], val ); + PORT_WRITE(out_EVENT_IFETCH_UNIT_VAL [i], ifetch_unit_val ); + PORT_WRITE(out_EVENT_PREDICTION_UNIT_VAL [i], prediction_unit_val); + PORT_WRITE(out_EVENT_CONTEXT_STATE_ACK [i], context_state_ack ); #ifdef DEBUG Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 97) @@ -94,7 +94,8 @@ ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); - ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context); @@ -160,5 +161,6 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); - INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_STATE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_EVENT_ACK ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit, in_EVENT_TYPE ,_param->_nb_context); if (_param->_have_port_depth) @@ -364,5 +366,6 @@ DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context); - DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/Makefile.deps (revision 97) @@ -21,5 +21,5 @@ Update_Prediction_Table_LIBRARY = -lUpdate_Prediction_Table \ - $(Behavioural_LIBRARY) + $(Behavioural_LIBRARY) Update_Prediction_Table_DIR_LIBRARY = -L$(Update_Prediction_Table_DIR)/lib \ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/debug.cfg (revision 96) +++ (revision ) @@ -1,11 +1,0 @@ -Update_Prediction_Table -1 1 +1 # nb_context -4 4 *2 # size_upt_queue [0] [nb_context] -1 1 +1 # size_ufpt_queue [0] [nb_context] -32 32 *2 # size_address -4 4 *4 # nb_inst_predict -4 4 *4 # nb_inst_decod -4 4 *4 # nb_inst_branch_complete -4 4 *4 # nb_inst_update -0 0 +1 # size_history -3 3 *2 # size_ras_index [0] [nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 97) @@ -42,5 +42,5 @@ #ifdef STATISTICS - morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); + morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); #endif @@ -137,5 +137,6 @@ ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update); - ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); @@ -230,5 +231,6 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update); - INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context); if (_param->_have_port_depth) @@ -316,8 +318,6 @@ in_UPDATE_ACK [i]->write(0); for (uint32_t i=0; i<_param->_nb_context; ++i) - { - in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT); - in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE ); - } + in_EVENT_VAL [i]->write(0); + //--------------------------------------------------------------------- //--------------------------------------------------------------------- @@ -932,9 +932,9 @@ SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_VAL [context]->write(1); in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_VAL [context]->write(0); in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); } @@ -1366,9 +1366,9 @@ SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_VAL [context]->write(1); in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_VAL [context]->write(0); in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); } @@ -1974,9 +1974,9 @@ SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_END ); + in_EVENT_VAL [context]->write(1); in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION); SC_START(1); - in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT ); + in_EVENT_VAL [context]->write(0); in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE ); } @@ -2155,5 +2155,6 @@ delete [] out_UPDATE_RAS_PREDICTION_IFETCH; - DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context); DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 97) @@ -52,10 +52,9 @@ public : Stat * _stat; - private : counter_t ** _stat_nb_branch_hit ; //[nb_context] - private : counter_t ** _stat_nb_branch_miss ; //[nb_context] - private : counter_t ** _stat_nb_branch_unused ; //[nb_context] - private : counter_t ** _stat_queue_nb_cycle_empty; //[nb_context] - private : counter_t ** _stat_queue_nb_cycle_full ; //[nb_context] - private : counter_t ** _stat_queue_nb_elt ; //[nb_context] + private : counter_t *** _stat_nb_branch_hit ; //[nb_context][MAX_BRANCH_CONDITION] + private : counter_t *** _stat_nb_branch_miss ; //[nb_context][MAX_BRANCH_CONDITION] + private : counter_t ** _stat_nb_branch_unused ; //[nb_context] + private : counter_t ** _stat_ufpt_queue_nb_elt ; //[nb_context] + private : counter_t ** _stat_upt_queue_nb_elt ; //[nb_context] #endif @@ -143,5 +142,6 @@ // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] @@ -197,4 +197,5 @@ private : Tdepth_t * internal_UPDATE_DEPTH ; //[nb_inst_update] private : bool * internal_UPDATE_RAS ; //[nb_inst_update] + private : Tcontrol_t * internal_EVENT_ACK ; //[nb_context] #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 97) @@ -76,5 +76,5 @@ if (usage_is_set(_usage,USE_SYSTEMC)) { - + // Constant for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) { @@ -82,4 +82,9 @@ PORT_WRITE(out_BRANCH_COMPLETE_ACK [i], internal_BRANCH_COMPLETE_ACK [i]); } + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + internal_EVENT_ACK [i] = 1; + PORT_WRITE(out_EVENT_ACK [i], internal_EVENT_ACK [i]); + } log_printf(INFO,Update_Prediction_Table,FUNCTION,"Method - transition"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 97) @@ -151,5 +151,6 @@ ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); + ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); @@ -183,4 +184,5 @@ ALLOC1(internal_UPDATE_DEPTH ,Tdepth_t ,_param->_nb_inst_update); ALLOC1(internal_UPDATE_RAS ,bool ,_param->_nb_inst_update); + ALLOC1(internal_EVENT_ACK ,Tcontrol_t,_param->_nb_context); // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 97) @@ -111,5 +111,6 @@ // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); + DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); @@ -137,4 +138,5 @@ DELETE1(internal_UPDATE_DEPTH ,_param->_nb_inst_update); DELETE1(internal_UPDATE_RAS ,_param->_nb_inst_update); + DELETE1(internal_EVENT_ACK ,_param->_nb_context); // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 97) @@ -67,6 +67,6 @@ if (take != 1) throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad direction.",i,toString(condition).c_str())); - if (addr_dest != addr_good) - throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +// if (addr_dest != addr_good) +// throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); #endif @@ -85,6 +85,6 @@ #ifdef DEBUG_TEST - if (addr_dest != addr_good) - throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +// if (addr_dest != addr_good) +// throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); #endif @@ -103,6 +103,6 @@ #ifdef DEBUG_TEST - if (addr_dest != addr_good) - throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); +// if (addr_dest != addr_good) +// throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_allocation.cpp (revision 97) @@ -8,4 +8,6 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" +#include "Behavioural/include/Allocation.h" + namespace morpheo { @@ -28,21 +30,76 @@ param_statistics); -// _stat_nb_branch_hit = new counter_t * [_param->_nb_context]; -// _stat_nb_branch_miss = new counter_t * [_param->_nb_context]; -// _stat_nb_branch_unused = new counter_t * [_param->_nb_context]; -// _stat_queue_nb_cycle_empty = new counter_t * [_param->_nb_context]; -// _stat_queue_nb_cycle_full = new counter_t * [_param->_nb_context]; -// _stat_queue_nb_elt = new counter_t * [_param->_nb_context]; - -// for (uint32_t i=0; i<_param->_nb_context; ++i) -// { -// _stat_nb_branch_hit [i] = _stat->create_counter("nb_branch_hit_" +toString(i),"",toString(_("Branch hit speculation (context %d)"),i)); -// _stat_nb_branch_miss [i] = _stat->create_counter("nb_branch_miss_" +toString(i),"",toString(_("Branch miss speculation (context %d)"),i)); -// _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused, because an previous branch have miss speculation (context %d)"),i)); -// _stat_queue_nb_cycle_empty [i] = _stat->create_counter("queue_nb_cycle_empty_"+toString(i),"",toString(_("Cycle number where the Update Prediction Table is empty (context %d)"),i)); -// _stat_queue_nb_cycle_full [i] = _stat->create_counter("queue_nb_cycle_full_" +toString(i),"",toString(_("Cycle number where the Update Prediction Table is full (%d elements) (context %d)"),_param->_size_queue[i],i)); -// _stat_queue_nb_elt [i] = _stat->create_counter("queue_nb_elt_" +toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); -// } - + { + ALLOC2(_stat_nb_branch_hit ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); + ALLOC2(_stat_nb_branch_miss ,counter_t *,_param->_nb_context,MAX_BRANCH_CONDITION); + ALLOC1(_stat_nb_branch_unused ,counter_t *,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + std::string sum_miss = "0"; + std::string sum_branchement = "0"; + + for (uint32_t j=0; jcreate_counter("nb_branch_hit_" +toString(i)+"_"+toString(j),"",toString(_("Branch hit speculation, branch condition : %s (context %d)"),toString(static_cast(j)).c_str(),i)); + _stat_nb_branch_miss [i][j] = _stat->create_counter(nb_miss,"",toString(_("Branch miss speculation, branch condition : %s (context %d)"),toString(static_cast(j)).c_str(),i)); + +// _stat->create_expr_average("average_miss_"+toString(i)+"_"+toString(j), +// "nb_branch_miss_"+toString(i)+"_"+toString(j), +// nb_branchement, +// "miss/branchement", +// toString(_("Average miss by branchement, branch condition : %s (context %d)"),toString(static_cast(j)).c_str(),i)); + + _stat->create_expr_percent("percent_miss_"+toString(i)+"_"+toString(j), + nb_miss, + nb_branchement, + toString(_("Percent miss by branchement, branch condition : %s (context %d)"),toString(static_cast(j)).c_str(),i)); + + sum_miss = "+ "+nb_miss +" "+ sum_miss; + sum_branchement = "+ "+nb_branchement+" "+sum_branchement; + } + +// _stat->create_expr_average("average_miss_"+toString(i), +// sum_miss, +// sum_branchement, +// "miss/branchement", +// toString(_("Average miss by branchement (context %d)"),i)); + + _stat->create_expr_percent("percent_miss_"+toString(i), + sum_miss, + sum_branchement, + toString(_("Percent miss by branchement (context %d)"),i)); + + _stat_nb_branch_unused [i] = _stat->create_counter("nb_branch_unused_" +toString(i),"",toString(_("Branch unused (previous speculation) (context %d)"),i)); + } + } + + { + ALLOC1(_stat_ufpt_queue_nb_elt ,counter_t *,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + _stat_ufpt_queue_nb_elt [i] = _stat->create_counter("ufpt_queue_nb_elt_"+toString(i),"",toString(_("Branchement in Update Fetch Prediction Table (context %d)"),i)); + + _stat->create_expr_average_by_cycle("average_occupation_ufpt_queue_"+toString(i),"ufpt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Fetch Prediction Table (context %d)"),i)); + _stat->create_expr_percent ("percent_occupation_ufpt_queue_"+toString(i), "average_occupation_ufpt_queue_"+toString(i), toString(_param->_size_ufpt_queue[i]), toString(_("Percent occupation of Update Fetch Prediction Table (context %d)"),i)); + } + } + + { + ALLOC1(_stat_upt_queue_nb_elt ,counter_t *,_param->_nb_context); + + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + _stat_upt_queue_nb_elt [i] = _stat->create_counter("upt_queue_nb_elt_"+toString(i),"",toString(_("Average branchement by cycle in Update Prediction Table (context %d)"),i)); + + _stat->create_expr_average_by_cycle("average_occupation_upt_queue_"+toString(i),"upt_queue_nb_elt_"+toString(i), "", toString(_("Average instruction by cycle in Update Prediction Table (context %d)"),i)); + _stat->create_expr_percent ("percent_occupation_upt_queue_"+toString(i), "average_occupation_upt_queue_"+toString(i), toString(_param->_size_upt_queue[i]), toString(_("Percent occupation of Update Prediction Table (context %d)"),i)); + } + } + log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_statistics_deallocation.cpp (revision 97) @@ -8,4 +8,5 @@ #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h" +#include "Behavioural/include/Allocation.h" namespace morpheo { @@ -27,10 +28,10 @@ delete _stat; -// delete [] _stat_nb_branch_hit ; -// delete [] _stat_nb_branch_miss ; -// delete [] _stat_nb_branch_unused ; -// delete [] _stat_queue_nb_cycle_empty; -// delete [] _stat_queue_nb_cycle_full ; -// delete [] _stat_queue_nb_elt ; + + DELETE2(_stat_nb_branch_hit ,_param->_nb_context,MAX_BRANCH_CONDITION); + DELETE2(_stat_nb_branch_miss ,_param->_nb_context,MAX_BRANCH_CONDITION); + DELETE1(_stat_nb_branch_unused ,_param->_nb_context); + DELETE1(_stat_ufpt_queue_nb_elt ,_param->_nb_context); + DELETE1(_stat_upt_queue_nb_elt ,_param->_nb_context); log_printf(FUNC,Update_Prediction_Table,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 97) @@ -472,4 +472,8 @@ // bool have_event = ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO) or // (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_EVENT)); +#ifdef STATISTICS + Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition; + bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK); +#endif bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO); @@ -480,4 +484,9 @@ reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO; + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + (*_stat_nb_branch_miss [context][condition])++; +#endif } else @@ -486,4 +495,15 @@ reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_OK; + + +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + if (ok) + (*_stat_nb_branch_hit [context][condition]) ++; + else + (*_stat_nb_branch_unused [context]) ++; + } +#endif } @@ -548,48 +568,38 @@ // =================================================================== for (uint32_t i=0; i<_param->_nb_context; ++i) - { - //---------------------------------------------------------------- - // Cases - //---------------------------------------------------------------- - // * EVENT_TYPE_NONE - nothing - // * EVENT_TYPE_MISS_SPECULATION - // * EVENT_STATE_END - Change state, reset pointer - // * EVENT_TYPE_EXCEPTION - - // * EVENT_STATE_EVENT - Flush upft and upt - // * EVENT_STATE_END - Change state, reset pointer - // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update - // * EVENT_TYPE_SPR_ACCESS - nothing - // * EVENT_TYPE_MSYNC - nothing - // * EVENT_TYPE_PSYNC - nothing - // * EVENT_TYPE_CSYNC - nothing - - Tevent_state_t event_state = PORT_READ(in_EVENT_STATE [i]); - Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); -// Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); + if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i]) + { + //---------------------------------------------------------------- + // Cases + //---------------------------------------------------------------- + // * EVENT_TYPE_NONE - nothing + // * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer + // * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer + // * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update + // * EVENT_TYPE_SPR_ACCESS - nothing + // * EVENT_TYPE_MSYNC - nothing + // * EVENT_TYPE_PSYNC - nothing + // * EVENT_TYPE_CSYNC - nothing + + Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]); +// Tdepth_t depth = PORT_READ(in_EVENT_DEPTH [i]); - // Test if end of miss - if ((event_state == EVENT_STATE_END) and - (event_type == EVENT_TYPE_MISS_SPECULATION)) - { - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state : EVENT_STATE_END"); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); - -#ifdef DEBUG_TEST - if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) - throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); -#endif - - // Change state - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); - - reg_EVENT_STATE [i] = EVENT_STATE_OK; - -// uint32_t bottom = reg_UPT_BOTTOM [i]; - -// reg_UPT_TOP [i] = bottom; -// reg_UPT_UPDATE [i] = bottom; - } - } + // Test if end of miss + if (event_type == EVENT_TYPE_MISS_SPECULATION) + { + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_MISS_SPECULATION"); + +#ifdef DEBUG_TEST + if (reg_EVENT_STATE [i] != EVENT_STATE_WAIT_END_EVENT) + throw ERRORMORPHEO(FUNCTION,_("Event : invalid event state.")); +#endif + + // Change state + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i); + + reg_EVENT_STATE [i] = EVENT_STATE_OK; + } + } // =================================================================== @@ -634,4 +644,17 @@ } +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + for (uint32_t i=0; i<_param->_nb_context; i++) + { + for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++) + if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY) + (*_stat_ufpt_queue_nb_elt [i]) ++; + for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++) + if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY) + (*_stat_upt_queue_nb_elt [i]) ++; + } +#endif + // =================================================================== // =====[ PRINT ]===================================================== Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 97) @@ -115,5 +115,6 @@ // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - public : SC_IN (Tevent_state_t ) ** in_EVENT_STATE ; //[nb_context] + public : SC_IN (Tcontrol_t ) ** in_EVENT_VAL ; //[nb_context] + public : SC_OUT(Tcontrol_t ) ** out_EVENT_ACK ; //[nb_context] public : SC_IN (Tevent_type_t ) ** in_EVENT_TYPE ; //[nb_context] public : SC_IN (Tdepth_t ) ** in_EVENT_DEPTH ; //[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 97) @@ -136,5 +136,6 @@ ALLOC1_INTERFACE("event", IN,SOUTH,"event", _param->_nb_context); - ALLOC1_SIGNAL_IN ( in_EVENT_STATE ,"state",Tevent_state_t,_param->_size_event_state); + ALLOC1_VALACK_IN ( in_EVENT_VAL ,VAL); + ALLOC1_VALACK_OUT(out_EVENT_ACK ,ACK); ALLOC1_SIGNAL_IN ( in_EVENT_TYPE ,"type" ,Tevent_type_t ,_param->_size_event_type ); ALLOC1_SIGNAL_IN ( in_EVENT_DEPTH ,"depth",Tdepth_t ,_param->_size_depth ); @@ -711,5 +712,6 @@ #endif - PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_STATE",dest, "in_EVENT_"+toString(i)+"_STATE"); + PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_VAL" ,dest, "in_EVENT_"+toString(i)+"_VAL" ); + PORT_MAP(_component,src ,"out_EVENT_"+toString(i)+"_ACK" ,dest,"out_EVENT_"+toString(i)+"_ACK" ); PORT_MAP(_component,src , "in_EVENT_"+toString(i)+"_TYPE" ,dest, "in_EVENT_"+toString(i)+"_TYPE" ); if (_param->_have_port_depth) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 97) @@ -71,5 +71,6 @@ DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context,_param->_size_instruction_address); - DELETE1_SIGNAL( in_EVENT_STATE ,_param->_nb_context,_param->_size_event_state); + DELETE1_SIGNAL( in_EVENT_VAL ,_param->_nb_context,1); + DELETE1_SIGNAL(out_EVENT_ACK ,_param->_nb_context,1); DELETE1_SIGNAL( in_EVENT_TYPE ,_param->_nb_context,_param->_size_event_type ); DELETE1_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 97) @@ -99,5 +99,5 @@ ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); + ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 97) @@ -140,5 +140,5 @@ ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_instruction_address ); + ALLOC_SIGNAL_IN ( in_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); } @@ -580,4 +580,23 @@ COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" , dest, "in_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST" ); + } + + // ~~~~~[ Interface : "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + for (uint32_t i=0; i<_param->_nb_context; ++i) + { + dest = _name+"_glue"; +#ifdef POSITION + _component->interface_map (src ,"event_"+toString(i), + dest,"event_"+toString(i)); +#endif + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_VAL" , + dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_VAL" ); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_ACK" , + dest, "in_EVENT_"+toString(i)+"_PREDICTION_UNIT_ACK" ); + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_TYPE" , + dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_TYPE" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src , "in_EVENT_"+toString(i)+ "_DEPTH", + dest,"out_EVENT_"+toString(i)+"_PREDICTION_UNIT_DEPTH"); } @@ -967,4 +986,9 @@ COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_IS_DS_TAKE" , dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_IS_DS_TAKE" ); + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_TYPE" , + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_TYPE" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_EVENT_"+toString(i)+ "_DEPTH" , + dest, "in_EVENT_"+toString(i)+"_CONTEXT_STATE_DEPTH" ); } @@ -1129,13 +1153,19 @@ // in_EVENT_IFETCH_UNIT_ACK - component_ifetch_unit // out_EVENT_IFETCH_UNIT_ADDRESS - component_ifetch_unit - // in_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit + // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT - component_ifetch_unit // out_EVENT_IFETCH_UNIT_ADDRESS_NEXT_VAL - component_ifetch_unit // in_EVENT_IFETCH_UNIT_IS_DS_TAKE - component_ifetch_unit + // out_EVENT_PREDICTION_UNIT_VAL - component_prediction_unit + // in_EVENT_PREDICTION_UNIT_ACK - component_prediction_unit + // out_EVENT_PREDICTION_UNIT_TYPE - component_prediction_unit + // out_EVENT_PREDICTION_UNIT_DEPTH - component_prediction_unit // in_EVENT_CONTEXT_STATE_VAL - component_context_state // out_EVENT_CONTEXT_STATE_ACK - component_context_state // in_EVENT_CONTEXT_STATE_ADDRESS - component_context_state // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT - component_context_state - // out_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state + // in_EVENT_CONTEXT_STATE_ADDRESS_NEXT_VAL - component_context_state // in_EVENT_CONTEXT_STATE_IS_DS_TAKE - component_context_state + // in_EVENT_CONTEXT_STATE_TYPE - component_context_state + // in_EVENT_CONTEXT_STATE_DEPTH - component_context_state // ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 97) @@ -68,5 +68,5 @@ ALLOC2_SC_SIGNAL( in_INSERT_NO_EXECUTE ," in_INSERT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); ALLOC2_SC_SIGNAL( in_INSERT_IS_DELAY_SLOT ," in_INSERT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); - ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Tgeneral_data_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + ALLOC2_SC_SIGNAL( in_INSERT_ADDRESS ," in_INSERT_ADDRESS ",Taddress_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION ," in_INSERT_EXCEPTION ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); ALLOC2_SC_SIGNAL( in_INSERT_EXCEPTION_USE ," in_INSERT_EXCEPTION_USE ",Texception_t ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -123,5 +123,5 @@ ALLOC1_SC_SIGNAL( in_COMMIT_EXCEPTION ," in_COMMIT_EXCEPTION ",Texception_t ,_param->_nb_inst_commit); ALLOC1_SC_SIGNAL( in_COMMIT_NO_SEQUENCE ," in_COMMIT_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_commit); - ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_commit); + ALLOC1_SC_SIGNAL( in_COMMIT_ADDRESS ," in_COMMIT_ADDRESS ",Taddress_t ,_param->_nb_inst_commit); ALLOC1_SC_SIGNAL(out_COMMIT_NUM_REG_RD ,"out_COMMIT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_commit); ALLOC1_SC_SIGNAL(out_REEXECUTE_VAL ,"out_REEXECUTE_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute); @@ -151,5 +151,5 @@ ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EPCR ,"out_UPDATE_ADDRESS_EPCR ",Taddress_t ); ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR_VAL ,"out_UPDATE_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Taddress_t ); + ALLOC_SC_SIGNAL (out_UPDATE_ADDRESS_EEAR ,"out_UPDATE_ADDRESS_EEAR ",Tgeneral_data_t ); ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 97) @@ -82,5 +82,5 @@ public : SC_IN (Tcontrol_t ) *** in_INSERT_NO_EXECUTE ;//[nb_rename_unit][nb_inst_insert] public : SC_IN (Tcontrol_t ) *** in_INSERT_IS_DELAY_SLOT ;//[nb_rename_unit][nb_inst_insert] - public : SC_IN (Tgeneral_data_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] + public : SC_IN (Taddress_t ) *** in_INSERT_ADDRESS ;//[nb_rename_unit][nb_inst_insert] public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION ;//[nb_rename_unit][nb_inst_insert] public : SC_IN (Texception_t ) *** in_INSERT_EXCEPTION_USE ;//[nb_rename_unit][nb_inst_insert] @@ -141,5 +141,5 @@ public : SC_IN (Texception_t ) ** in_COMMIT_EXCEPTION ;//[nb_inst_commit] public : SC_IN (Tcontrol_t ) ** in_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] - public : SC_IN (Tgeneral_data_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit] + public : SC_IN (Taddress_t ) ** in_COMMIT_ADDRESS ;//[nb_inst_commit] public : SC_OUT(Tgeneral_address_t ) ** out_COMMIT_NUM_REG_RD ;//[nb_inst_commit] @@ -175,5 +175,5 @@ public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EPCR ; public : SC_OUT(Tcontrol_t ) * out_UPDATE_ADDRESS_EEAR_VAL ; - public : SC_OUT(Taddress_t ) * out_UPDATE_ADDRESS_EEAR ; + public : SC_OUT(Tgeneral_data_t ) * out_UPDATE_ADDRESS_EEAR ; // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 97) @@ -71,5 +71,5 @@ _ALLOC2_SIGNAL_IN ( in_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); - _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); + _ALLOC2_SIGNAL_IN ( in_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); _ALLOC2_SIGNAL_IN ( in_INSERT_EXCEPTION_USE ,"exception_use" ,Texception_t ,_param->_size_exception ,_param->_nb_rename_unit,_param->_nb_inst_insert[it1]); @@ -138,5 +138,5 @@ ALLOC1_SIGNAL_IN ( in_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC1_SIGNAL_IN ( in_COMMIT_NO_SEQUENCE ,"no_sequence",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_IN ( in_COMMIT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_instruction_address); + ALLOC1_SIGNAL_IN ( in_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); // ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register+_param->_size_rename_unit_id); ALLOC1_SIGNAL_OUT(out_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register); @@ -185,5 +185,5 @@ ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EPCR ,"address_epcr" ,Taddress_t ,_param->_size_instruction_address); ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR_VAL ,"address_eear_val",Tcontrol_t ,1); - ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Taddress_t ,_param->_size_instruction_address); + ALLOC_SIGNAL_OUT(out_UPDATE_ADDRESS_EEAR ,"address_eear" ,Tgeneral_data_t ,_param->_size_general_data); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 97) @@ -75,5 +75,5 @@ log_printf(TRACE,Commit_unit,FUNCTION," * front_end_id : %d",front_end_id); log_printf(TRACE,Commit_unit,FUNCTION," * context_id : %d",context_id); - log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString_type(type).c_str()); + log_printf(TRACE,Commit_unit,FUNCTION," * type : %s",toString(type).c_str()); log_printf(TRACE,Commit_unit,FUNCTION," * operation : %d",operation ); log_printf(TRACE,Commit_unit,FUNCTION," * exception : %d",exception ); @@ -478,10 +478,48 @@ it++) { - log_printf(TRACE,Commit_unit,FUNCTION," [%d] %.8x (%.8x) %s - ptr : %d", + log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d", x, - (*it)->address, - (*it)->address<<2, - toString((*it)->state).c_str(), - (*it)->ptr); + (*it)->front_end_id , + (*it)->context_id , + (*it)->rename_unit_id , + (*it)->depth , + (*it)->type , + (*it)->operation , + (*it)->address , + (*it)->is_delay_slot , + (*it)->use_store_queue , + (*it)->store_queue_ptr_write , + (*it)->use_load_queue , + (*it)->load_queue_ptr_write , + toString((*it)->state).c_str() , + (*it)->ptr ); + log_printf(TRACE,Commit_unit,FUNCTION," %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.5d %.6d, %.1d %.1d %.6d %.6d, %.1d %.1d %.6d %.6d ", + (*it)->read_ra , + (*it)->num_reg_ra_log , + (*it)->num_reg_ra_phy , + (*it)->read_rb , + (*it)->num_reg_rb_log , + (*it)->num_reg_rb_phy , + (*it)->read_rc , + (*it)->num_reg_rc_log , + (*it)->num_reg_rc_phy , + (*it)->write_rd , + (*it)->num_reg_rd_log , + (*it)->num_reg_rd_phy_old , + (*it)->num_reg_rd_phy_new , + (*it)->write_re , + (*it)->num_reg_re_log , + (*it)->num_reg_re_phy_old , + (*it)->num_reg_re_phy_new ); + + log_printf(TRACE,Commit_unit,FUNCTION," %.2d %.2d %.1d %.1d %.8x %s", + (*it)->exception , + (*it)->exception_use , + (*it)->flags , + (*it)->no_sequence , + (*it)->data_commit , + toString((*it)->event_state).c_str() + ); + x++; } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Issue_queue/src/Parameters_msg_error.cpp (revision 97) @@ -78,5 +78,5 @@ for (uint32_t j=0; j<_nb_type; j++) if (not type_present [j]) - test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString_type(j).c_str())); + test.error(toString(_("Rename_unit [%d] can't issue instruction's type \"%s\".\n"),i,toString(j).c_str())); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/OOO_Engine_Glue/src/OOO_Engine_Glue_allocation.cpp (revision 97) @@ -73,5 +73,5 @@ ALLOC1_SIGNAL_OUT (out_INSERT_RD_NUM_REG ,"RD_NUM_REG" ,Tgeneral_address_t ,_param->_size_general_register); ALLOC1_SIGNAL_OUT (out_INSERT_RE_USE ,"RE_USE" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_general_register); + ALLOC1_SIGNAL_OUT (out_INSERT_RE_NUM_REG ,"RE_NUM_REG" ,Tspecial_address_t ,_param->_size_special_register); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/include/Reexecute_unit.h (revision 97) @@ -80,5 +80,5 @@ public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] - public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Taddress_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] @@ -95,5 +95,5 @@ public : SC_OUT(Texception_t ) ** out_COMMIT_EXCEPTION ;//[nb_inst_commit] public : SC_OUT(Tcontrol_t ) ** out_COMMIT_NO_SEQUENCE ;//[nb_inst_commit] - public : SC_OUT(Tgeneral_data_t ) ** out_COMMIT_ADDRESS ;//[nb_inst_commit] + public : SC_OUT(Taddress_t ) ** out_COMMIT_ADDRESS ;//[nb_inst_commit] public : SC_IN (Tgeneral_address_t ) ** in_COMMIT_NUM_REG_RD ;//[nb_inst_commit] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Parameters.cpp (revision 97) @@ -71,4 +71,5 @@ if (is_toplevel) { + _size_instruction_address = size_general_data-2 ; _size_context_id = size_context_id ; _size_front_end_id = size_front_end_id ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_allocation.cpp (revision 97) @@ -70,5 +70,5 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); - _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); } @@ -89,5 +89,5 @@ ALLOC1_SIGNAL_OUT(out_COMMIT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); ALLOC1_SIGNAL_OUT(out_COMMIT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data); + ALLOC1_SIGNAL_OUT(out_COMMIT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); ALLOC1_SIGNAL_IN ( in_COMMIT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t ,_param->_size_general_register); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 97) @@ -58,5 +58,5 @@ // Need spr_acces / reexecute ? Texception_t exception = PORT_READ(in_EXECUTE_LOOP_EXCEPTION [x][y]); - Tgeneral_data_t address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); + Taddress_t address = PORT_READ(in_EXECUTE_LOOP_ADDRESS [x][y]); Tcontrol_t spr_access = ((exception == EXCEPTION_ALU_SPR_ACCESS_MUST_READ ) or (exception == EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE)); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Load_Store_pointer_unit/src/Load_Store_pointer_unit_allocation.cpp (revision 97) @@ -80,6 +80,6 @@ // ALLOC1_SIGNAL_IN ( in_RETIRE_TYPE ,"type" ,Ttype_t ,_param->_size_type ); // ALLOC1_SIGNAL_IN ( in_RETIRE_OPERATION ,"operation" ,Toperation_t,_param->_size_operation ); - ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,_param->_size_operation ); - ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,_param->_size_operation ); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_STORE_QUEUE ,"use_store_queue" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_IN ( in_RETIRE_USE_LOAD_QUEUE ,"use_load_queue" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_RETIRE_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr); ALLOC1_SIGNAL_IN ( in_RETIRE_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_genMealy_rename.cpp (revision 97) @@ -27,13 +27,21 @@ for (uint32_t i=0; i<_param->_nb_inst_insert; i++) + if (PORT_READ(in_RENAME_VAL [i])) // not in sensitive list : it's to have valide value to array access { Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; - PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RA_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RB_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RC_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RD_LOG [i])]); - PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][PORT_READ(in_RENAME_NUM_REG_RE_LOG [i])]); + Tgeneral_address_t num_reg_ra_log = PORT_READ(in_RENAME_NUM_REG_RA_LOG [i]); //%_param->_nb_general_register; + Tgeneral_address_t num_reg_rb_log = PORT_READ(in_RENAME_NUM_REG_RB_LOG [i]); //%_param->_nb_general_register; + Tspecial_address_t num_reg_rc_log = PORT_READ(in_RENAME_NUM_REG_RC_LOG [i]); //%_param->_nb_special_register; + Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RENAME_NUM_REG_RD_LOG [i]); //%_param->_nb_general_register; + Tspecial_address_t num_reg_re_log = PORT_READ(in_RENAME_NUM_REG_RE_LOG [i]); //%_param->_nb_special_register; + + PORT_WRITE(out_RENAME_NUM_REG_RA_PHY [i], rat_gpr[front_end_id][context_id][num_reg_ra_log]); + PORT_WRITE(out_RENAME_NUM_REG_RB_PHY [i], rat_gpr[front_end_id][context_id][num_reg_rb_log]); + PORT_WRITE(out_RENAME_NUM_REG_RC_PHY [i], rat_spr[front_end_id][context_id][num_reg_rc_log]); + PORT_WRITE(out_RENAME_NUM_REG_RD_PHY_OLD [i], rat_gpr[front_end_id][context_id][num_reg_rd_log]); + PORT_WRITE(out_RENAME_NUM_REG_RE_PHY_OLD [i], rat_spr[front_end_id][context_id][num_reg_re_log]); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"yo6"); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/SelfTest/src/test.cpp (revision 97) @@ -59,5 +59,5 @@ ALLOC2_SC_SIGNAL( in_RENAME_IN_NO_EXECUTE ," in_RENAME_IN_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_IS_DELAY_SLOT ," in_RENAME_IN_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); - ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_IN_ADDRESS ," in_RENAME_IN_ADDRESS ",Taddress_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_HAS_IMMEDIAT ," in_RENAME_IN_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IN_IMMEDIAT ," in_RENAME_IN_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -84,5 +84,5 @@ ALLOC1_SC_SIGNAL(out_RENAME_OUT_NO_EXECUTE ,"out_RENAME_OUT_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_IS_DELAY_SLOT,"out_RENAME_OUT_IS_DELAY_SLOT",Tcontrol_t ,_param->_nb_inst_rename); - ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_rename); + ALLOC1_SC_SIGNAL(out_RENAME_OUT_ADDRESS ,"out_RENAME_OUT_ADDRESS ",Taddress_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_HAS_IMMEDIAT ,"out_RENAME_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_rename); ALLOC1_SC_SIGNAL(out_RENAME_OUT_IMMEDIAT ,"out_RENAME_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_rename); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/include/Rename_select.h (revision 97) @@ -76,5 +76,5 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] - public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -102,5 +102,5 @@ public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_NO_EXECUTE ;//[nb_inst_rename] public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_IS_DELAY_SLOT;//[nb_inst_rename] - public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] + public : SC_OUT(Taddress_t ) ** out_RENAME_OUT_ADDRESS ;//[nb_inst_rename] public : SC_OUT(Tcontrol_t ) ** out_RENAME_OUT_HAS_IMMEDIAT ;//[nb_inst_rename] public : SC_OUT(Tgeneral_data_t ) ** out_RENAME_OUT_IMMEDIAT ;//[nb_inst_rename] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Parameters.cpp (revision 97) @@ -50,12 +50,13 @@ if (is_toplevel) { - _size_general_data = size_general_data ; - _size_depth = log2(max_branch_speculated); - _size_front_end_id = log2(_nb_front_end); - _size_context_id = log2(max(_nb_context,_nb_front_end)); - - _have_port_front_end_id= _size_front_end_id > 0; - _have_port_context_id = _size_context_id > 0; - _have_port_depth = _size_depth > 0; + _size_instruction_address = size_general_data-2; + _size_general_data = size_general_data ; + _size_depth = log2(max_branch_speculated); + _size_front_end_id = log2(_nb_front_end); + _size_context_id = log2(max(_nb_context,_nb_front_end)); + + _have_port_front_end_id = _size_front_end_id > 0; + _have_port_context_id = _size_context_id > 0; + _have_port_depth = _size_depth > 0; copy(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Rename_select/src/Rename_select_allocation.cpp (revision 97) @@ -69,5 +69,5 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -82,5 +82,5 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic, _param->_nb_front_end, _param->_nb_inst_decod[it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception , _param->_nb_front_end, _param->_nb_inst_decod[it1]); } @@ -99,5 +99,5 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); @@ -112,5 +112,5 @@ ALLOC1_SIGNAL_OUT(out_RENAME_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register_logic); - ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception ); + ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION_USE ,"exception_use",Texception_t ,_param->_size_exception_use ); ALLOC1_SIGNAL_OUT(out_RENAME_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/include/Rename_unit.h (revision 97) @@ -78,5 +78,5 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] - public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Taddress_t ) *** in_RENAME_IN_ADDRESS ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IN_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IN_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -104,5 +104,5 @@ public : SC_OUT(Tcontrol_t ) ** out_INSERT_NO_EXECUTE ;//[nb_inst_insert] public : SC_OUT(Tcontrol_t ) ** out_INSERT_IS_DELAY_SLOT ;//[nb_inst_insert] - public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] + public : SC_OUT(Taddress_t ) ** out_INSERT_ADDRESS ;//[nb_inst_insert] public : SC_OUT(Tcontrol_t ) ** out_INSERT_HAS_IMMEDIAT ;//[nb_inst_insert] public : SC_OUT(Tgeneral_data_t ) ** out_INSERT_IMMEDIAT ;//[nb_inst_insert] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Parameters.cpp (revision 97) @@ -119,4 +119,5 @@ if (is_toplevel) { + _size_instruction_address = size_general_data-2; _size_front_end_id = log2(_nb_front_end); _size_context_id = log2(max(_nb_context,_nb_front_end)); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/src/Rename_unit_allocation.cpp (revision 97) @@ -69,5 +69,5 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_IN_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IS_DELAY_SLOT ,"is_delay_slot",Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 , _param->_nb_front_end, _param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data , _param->_nb_front_end, _param->_nb_inst_decod[it1]); @@ -99,5 +99,5 @@ ALLOC1_SIGNAL_OUT(out_INSERT_NO_EXECUTE ,"no_execute" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_INSERT_IS_DELAY_SLOT ,"is_delay_slot" ,Tcontrol_t ,1 ); - ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); + ALLOC1_SIGNAL_OUT(out_INSERT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address ); ALLOC1_SIGNAL_OUT(out_INSERT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT(out_INSERT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 97) @@ -57,5 +57,5 @@ ALLOC2_SC_SIGNAL( in_RENAME_NO_EXECUTE ," in_RENAME_NO_EXECUTE ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IS_DELAY_SLOT ," in_RENAME_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); - ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + ALLOC2_SC_SIGNAL( in_RENAME_ADDRESS ," in_RENAME_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_HAS_IMMEDIAT ," in_RENAME_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); ALLOC2_SC_SIGNAL( in_RENAME_IMMEDIAT ," in_RENAME_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -105,5 +105,5 @@ ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_EXCEPTION ," in_EXECUTE_LOOP_EXCEPTION ",Texception_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_NO_SEQUENCE ," in_EXECUTE_LOOP_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); - ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_ADDRESS ," in_EXECUTE_LOOP_ADDRESS ",Taddress_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); ALLOC2_SC_SIGNAL( in_EXECUTE_LOOP_DATA ," in_EXECUTE_LOOP_DATA ",Tgeneral_data_t ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); @@ -145,5 +145,5 @@ ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EPCR ,"out_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ); ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"out_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ); - ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ); + ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ADDRESS_EEAR ,"out_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t ); ALLOC2_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 97) @@ -38,5 +38,5 @@ throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l)); #endif -// log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l); + log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l); _spr [i][j][k][l]->reset(); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 97) @@ -77,5 +77,5 @@ public : SC_IN (Tcontrol_t ) *** in_RENAME_NO_EXECUTE ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_IS_DELAY_SLOT ;//[nb_front_end][nb_inst_decod] - public : SC_IN (Tgeneral_data_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] + public : SC_IN (Taddress_t ) *** in_RENAME_ADDRESS ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tcontrol_t ) *** in_RENAME_HAS_IMMEDIAT ;//[nb_front_end][nb_inst_decod] public : SC_IN (Tgeneral_data_t ) *** in_RENAME_IMMEDIAT ;//[nb_front_end][nb_inst_decod] @@ -127,5 +127,5 @@ public : SC_IN (Texception_t ) *** in_EXECUTE_LOOP_EXCEPTION ;//[nb_execute_loop][nb_inst_execute] public : SC_IN (Tcontrol_t ) *** in_EXECUTE_LOOP_NO_SEQUENCE ;//[nb_execute_loop][nb_inst_execute] - public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] + public : SC_IN (Taddress_t ) *** in_EXECUTE_LOOP_ADDRESS ;//[nb_execute_loop][nb_inst_execute] public : SC_IN (Tgeneral_data_t ) *** in_EXECUTE_LOOP_DATA ;//[nb_execute_loop][nb_inst_execute] @@ -171,5 +171,5 @@ public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EPCR ; public : SC_OUT(Tcontrol_t ) * out_COMMIT_EVENT_ADDRESS_EEAR_VAL ; - public : SC_OUT(Taddress_t ) * out_COMMIT_EVENT_ADDRESS_EEAR ; + public : SC_OUT(Tgeneral_data_t ) * out_COMMIT_EVENT_ADDRESS_EEAR ; // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 97) @@ -66,5 +66,5 @@ _ALLOC2_SIGNAL_IN ( in_RENAME_NO_EXECUTE ,"NO_EXECUTE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IS_DELAY_SLOT ,"IS_DELAY_SLOT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); - _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); + _ALLOC2_SIGNAL_IN ( in_RENAME_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_HAS_IMMEDIAT ,"HAS_IMMEDIAT" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); _ALLOC2_SIGNAL_IN ( in_RENAME_IMMEDIAT ,"IMMEDIAT" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_front_end,_param->_nb_inst_decod[it1]); @@ -124,5 +124,5 @@ _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_EXCEPTION ,"EXCEPTION" ,Texception_t ,_param->_size_exception ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); - _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); + _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); _ALLOC2_SIGNAL_IN ( in_EXECUTE_LOOP_DATA ,"DATA" ,Tgeneral_data_t ,_param->_size_general_data ,_param->_nb_execute_loop,_param->_nb_inst_execute[it1]); } @@ -184,5 +184,5 @@ ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EPCR ,"ADDRESS_EPCR" ,Taddress_t ,_param->_size_instruction_address ); ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR_VAL ,"ADDRESS_EEAR_VAL" ,Tcontrol_t ,1 ); - ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Taddress_t ,_param->_size_general_data ); + ALLOC_SIGNAL_OUT (out_COMMIT_EVENT_ADDRESS_EEAR ,"ADDRESS_EEAR" ,Tgeneral_data_t ,_param->_size_general_data ); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/Parameters_print.cpp (revision 97) @@ -63,5 +63,5 @@ for (uint32_t i=0; i<_nb_inst_issue ; ++i) for (uint32_t j=0; j<_nb_type; ++j) - str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString_type(j)+"] : "+toString(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type] + str+= toString(MSG_INFORMATION)+" * table_issue_type ["+toString(i)+"]["+toString(j)+"] : "+toString(_table_issue_type [i][j] )+"\n";//[nb_inst_issue][nb_type] str+= toString(MSG_INFORMATION)+" * size_reexecute_queue : "+toString(_size_reexecute_queue )+"\n"; str+= toString(MSG_INFORMATION)+" * reexecute_priority : "+toString(_reexecute_priority )+"\n"; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-min.cfg (revision 97) @@ -7,4 +7,5 @@ 2 2 +1 # ras_size_queue [0] [nb_thread] 1 1 +1 # upt_size_queue [0] [nb_thread] +1 1 +1 # ufpt_size_queue [0] [nb_thread] 1 1 +1 # nb_decod_bloc 1 1 +1 # size_decod_queue [0] [nb_decod_bloc] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/config-w1a.cfg (revision 97) @@ -7,4 +7,5 @@ 4 4 +1 # ras_size_queue [0] [nb_thread] 4 4 +1 # upt_size_queue [0] [nb_thread] +2 2 +1 # ufpt_size_queue [0] [nb_thread] 1 1 +1 # nb_decod_bloc 4 4 +1 # size_decod_queue [0] [nb_decod_bloc] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/SelfTest/src/main.cpp (revision 97) @@ -25,4 +25,5 @@ err (_(" * ras_size_queue [nb_thread] (uint32_t )\n")); err (_(" * upt_size_queue [nb_thread] (uint32_t )\n")); + err (_(" * ufpt_size_queue [nb_thread] (uint32_t )\n")); err (_(" * nb_decod_bloc (uint32_t )\n")); @@ -183,4 +184,5 @@ uint32_t * _ras_size_queue ;//[nb_thread] uint32_t * _upt_size_queue ;//[nb_thread] + uint32_t * _ufpt_size_queue ;//[nb_thread] // Decod_bloc @@ -335,5 +337,5 @@ SELFTEST0(_nb_thread ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread)) usage (argc, argv); @@ -346,4 +348,5 @@ SELFTEST1(_ras_size_queue ,uint32_t ,argv,x,_nb_thread); SELFTEST1(_upt_size_queue ,uint32_t ,argv,x,_nb_thread); + SELFTEST1(_ufpt_size_queue ,uint32_t ,argv,x,_nb_thread); // Decod bloc @@ -351,5 +354,5 @@ SELFTEST0(_nb_decod_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc)) usage (argc, argv); @@ -364,5 +367,5 @@ SELFTEST0(_nb_rename_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc)) usage (argc, argv); @@ -382,5 +385,5 @@ SELFTEST0(_nb_read_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc)) usage (argc, argv); @@ -393,5 +396,5 @@ SELFTEST0(_nb_write_bloc ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc)) usage (argc, argv); @@ -404,5 +407,5 @@ SELFTEST0(_nb_load_store_unit ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit)) usage (argc, argv); @@ -421,5 +424,5 @@ SELFTEST0(_nb_functionnal_unit ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit)) usage (argc, argv); @@ -464,5 +467,5 @@ SELFTEST0(_nb_front_end ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end)) usage (argc, argv); @@ -491,5 +494,5 @@ SELFTEST0(_nb_ooo_engine ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine)) usage (argc, argv); @@ -518,5 +521,5 @@ SELFTEST0(_nb_execute_loop ,uint32_t ,argv,x); - if (argc < static_cast(2+NB_PARAMS+4*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) + if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+5*_nb_decod_bloc+10*_nb_rename_bloc+3*_nb_read_bloc+3*_nb_write_bloc+8*_nb_load_store_unit+1*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) usage (argc, argv); @@ -536,5 +539,5 @@ printf(" * Link\n"); - if (argc < static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) + if (argc < static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop)) usage (argc, argv); @@ -590,5 +593,5 @@ _sum_cache_port += _nb_cache_port[i]; - if (argc != static_cast(2+NB_PARAMS+5*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop+ + if (argc != static_cast(2+NB_PARAMS+6*_nb_thread+6*_nb_decod_bloc+11*_nb_rename_bloc+4*_nb_read_bloc+4*_nb_write_bloc+9*_nb_load_store_unit+2*_nb_functionnal_unit+31*_nb_front_end+18*_nb_ooo_engine+11*_nb_execute_loop+ 3*_nb_thread+_nb_front_end+_sum_inst_issue*_nb_read_bloc+_nb_load_store_unit*(_nb_read_bloc+_nb_write_bloc+_nb_thread)+_nb_functionnal_unit*(_nb_read_bloc+_nb_write_bloc)+_sum_cache_port)) usage (argc, argv); @@ -626,4 +629,5 @@ _ras_size_queue , _upt_size_queue , + _ufpt_size_queue , _nb_decod_bloc , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/include/Parameters.h (revision 97) @@ -46,4 +46,5 @@ public : uint32_t * _ras_size_queue ;//[nb_thread] public : uint32_t * _upt_size_queue ;//[nb_thread] + public : uint32_t * _ufpt_size_queue ;//[nb_thread] // Decod bloc @@ -221,4 +222,5 @@ public : uint32_t ** _front_end_ras_size_queue ;//[nb_front_end][nb_context] public : uint32_t ** _front_end_upt_size_queue ;//[nb_front_end][nb_context] + public : uint32_t ** _front_end_ufpt_size_queue ;//[nb_front_end][nb_context] // translate for ooo_engine @@ -346,4 +348,5 @@ uint32_t * ras_size_queue ,//[nb_thread] uint32_t * upt_size_queue ,//[nb_thread] + uint32_t * ufpt_size_queue ,//[nb_thread] // Decod bloc Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters.cpp (revision 97) @@ -84,4 +84,5 @@ uint32_t * ras_size_queue ,//[nb_thread] uint32_t * upt_size_queue ,//[nb_thread] + uint32_t * ufpt_size_queue ,//[nb_thread] // Decod bloc @@ -237,4 +238,5 @@ _ras_size_queue = ras_size_queue ; _upt_size_queue = upt_size_queue ; + _ufpt_size_queue = ufpt_size_queue ; _nb_decod_bloc = nb_decod_bloc ; @@ -441,4 +443,5 @@ ALLOC2(_front_end_ras_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); ALLOC2(_front_end_upt_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); + ALLOC2(_front_end_ufpt_size_queue ,uint32_t ,_nb_front_end,_nb_context[it1]); for (uint32_t i=0; i<_nb_front_end; ++i) @@ -451,4 +454,5 @@ _front_end_ras_size_queue [i][j] = _ras_size_queue [num_thread]; _front_end_upt_size_queue [i][j] = _upt_size_queue [num_thread]; + _front_end_ufpt_size_queue [i][j] = _ufpt_size_queue [num_thread]; uint32_t num_decod_bloc = _link_decod_bloc_with_thread [num_thread]; @@ -1733,4 +1737,5 @@ _front_end_ras_size_queue [i], _front_end_upt_size_queue [i], + _front_end_ufpt_size_queue [i], _size_nb_inst_commit ); @@ -2027,4 +2032,5 @@ DELETE1(_front_end_nb_inst_branch_complete ,_nb_front_end); DELETE3(_front_end_instruction_implemeted ,_nb_front_end,_nb_context[it1],NB_INSTRUCTION); + DELETE2(_front_end_ufpt_size_queue ,_nb_front_end,_nb_context[it1]); DELETE2(_front_end_upt_size_queue ,_nb_front_end,_nb_context[it1]); DELETE2(_front_end_ras_size_queue ,_nb_front_end,_nb_context[it1]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Parameters_print.cpp (revision 97) @@ -43,4 +43,5 @@ str+= toString(MSG_INFORMATION)+" * ras_size_queue : "+toString(_ras_size_queue [i])+"\n"; str+= toString(MSG_INFORMATION)+" * upt_size_queue : "+toString(_upt_size_queue [i])+"\n"; + str+= toString(MSG_INFORMATION)+" * ufpt_size_queue : "+toString(_ufpt_size_queue [i])+"\n"; for (uint32_t j=0; jset_type ("Tregfile", "array " + std_logic_range(_param->_nb_word,true) + " of " + std_logic(_param->_size_word)); + vhdl->set_type ("Tregfile", "array " + _std_logic_range(_param->_nb_word) + " of " + std_logic(_param->_size_word)); vhdl->set_signal ("reg_DATA", "Tregfile"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h (revision 97) @@ -16,4 +16,5 @@ #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" +#include "Common/include/Time.h" using namespace std; @@ -28,34 +29,2 @@ morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * param); - -class Time -{ -private : timeval time_begin; -// private : timeval time_end; - -public : Time () - { - gettimeofday(&time_begin ,NULL); - }; - -public : ~Time () - { - cout << *this; - }; - -public : friend ostream& operator<< (ostream& output_stream, - const Time & x) - { - timeval time_end; - - gettimeofday(&time_end ,NULL); - - uint32_t nb_cycles = static_cast(sc_simulation_time()); - - double average = static_cast(nb_cycles) / static_cast(time_end.tv_sec-x.time_begin.tv_sec); - - output_stream << nb_cycles << "\t(" << average << " cycles / seconds )" << endl; - - return output_stream; - } -}; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/include/test.h (revision 97) @@ -15,4 +15,5 @@ #include "Behavioural/Generic/Select/Select_Priority_Fixed/include/Select_Priority_Fixed.h" +#include "Common/include/Time.h" using namespace std; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/SelfTest/src/test.cpp (revision 97) @@ -94,4 +94,5 @@ cout << "<" << name << "> Start Simulation ............" << endl; + Time * _time = new Time(); if (_param->_nb_entity > (8*sizeof (Tentity_t))) @@ -148,4 +149,5 @@ ********************************************************/ + delete _time; cout << "<" << name << "> ............ Stop Simulation" << endl; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Select/Select_Priority_Fixed/src/Select_Priority_Fixed.cpp (revision 97) @@ -52,5 +52,5 @@ #ifdef VHDL - if (usage_is_set(_usage,USE_VHDL) + if (usage_is_set(_usage,USE_VHDL)) { // generate the vhdl Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Common (revision 97) @@ -27,5 +27,4 @@ DIR_SRC = src DIR_OBJ = obj -#DIR_LIB = $(DIR_TMP)/lib DIR_SCRIPT = $(MORPHEO_SCRIPT) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.deps (revision 97) @@ -20,6 +20,7 @@ #-----[ Library ]------------------------------------------ -Behavioural_LIBRARY = -lBehavioural \ - -lCommon +Behavioural_LIBRARY = -lBehavioural \ + -lCommon + Behavioural_DIR_LIBRARY = -L$(Behavioural_DIR)/lib \ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h (revision 97) @@ -16,4 +16,6 @@ [0][19] - SPR_CID */ + +#include "Common/include/ToString.h" namespace morpheo { @@ -33,16 +35,19 @@ //=========================================================[ Type ]===== -# define TYPE_ALU 0x0 // 00000 - unit multiple -# define TYPE_SHIFT 0x1 // 00000 - unit multiple -# define TYPE_MOVE 0x2 // 00000 - unit multiple -# define TYPE_TEST 0x3 // 00000 - unit multiple -# define TYPE_MUL 0x4 // 00000 - unit multiple -# define TYPE_DIV 0x5 // 00000 - unit multiple, type optionnal -# define TYPE_EXTEND 0x6 // 00000 - unit multiple, type optionnal -# define TYPE_FIND 0x7 // 00000 - unit multiple, type optionnal -# define TYPE_SPECIAL 0x8 // 00000 - unit uniq -# define TYPE_CUSTOM 0x9 // 00000 - unit uniq , type optionnal -# define TYPE_BRANCH 0xa // 00000 - unit multiple -# define TYPE_MEMORY 0xb // 00000 - unit uniq +typedef enum + { + TYPE_ALU = 0x0, // 00000 - unit multiple + TYPE_SHIFT = 0x1, // 00000 - unit multiple + TYPE_MOVE = 0x2, // 00000 - unit multiple + TYPE_TEST = 0x3, // 00000 - unit multiple + TYPE_MUL = 0x4, // 00000 - unit multiple + TYPE_DIV = 0x5, // 00000 - unit multiple, type optionnal + TYPE_EXTEND = 0x6, // 00000 - unit multiple, type optionnal + TYPE_FIND = 0x7, // 00000 - unit multiple, type optionnal + TYPE_SPECIAL = 0x8, // 00000 - unit uniq + TYPE_CUSTOM = 0x9, // 00000 - unit uniq , type optionnal + TYPE_BRANCH = 0xa, // 00000 - unit multiple + TYPE_MEMORY = 0xb // 00000 - unit uniq + } type_t; //#define NB_TYPE 11 @@ -610,13 +615,48 @@ # define SIZE_BRANCH_CONDITION 4 - -# define BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK 0x0 // None condition (jump) -# define BRANCH_CONDITION_NONE_WITH_WRITE_STACK 0x8 // None condition (jump) -# define BRANCH_CONDITION_FLAG_UNSET 0x2 // Branch if Flag is clear -# define BRANCH_CONDITION_FLAG_SET 0x3 // Branch if Flag is set -# define BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK 0x4 // Branch if a register is read -# define BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK 0xc // Branch if a register is read -# define BRANCH_CONDITION_READ_STACK 0xf // Branch with pop in stack pointer - +# define MAX_BRANCH_CONDITION (1< inline std::string toString(const morpheo::behavioural::type_t& x) + { + switch (x) + { + case morpheo::behavioural::TYPE_ALU : return "ALU" ; + case morpheo::behavioural::TYPE_SHIFT : return "SHIFT" ; + case morpheo::behavioural::TYPE_MOVE : return "MOVE" ; + case morpheo::behavioural::TYPE_TEST : return "TEST" ; + case morpheo::behavioural::TYPE_MUL : return "MUL" ; + case morpheo::behavioural::TYPE_DIV : return "DIV" ; + case morpheo::behavioural::TYPE_EXTEND : return "EXTEND" ; + case morpheo::behavioural::TYPE_FIND : return "FIND" ; + case morpheo::behavioural::TYPE_SPECIAL : return "SPECIAL" ; + case morpheo::behavioural::TYPE_CUSTOM : return "CUSTOM" ; + case morpheo::behavioural::TYPE_BRANCH : return "BRANCH" ; + case morpheo::behavioural::TYPE_MEMORY : return "MEMORY" ; + default : return ""; + } + }; + + template<> inline std::string toString(const morpheo::behavioural::branch_condition_t& x) + { + switch (x) + { + case morpheo::behavioural::BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : return "none_without_write_stack" ; + case morpheo::behavioural::BRANCH_CONDITION_NONE_WITH_WRITE_STACK : return "none_with_write_stack" ; + case morpheo::behavioural::BRANCH_CONDITION_FLAG_UNSET : return "flag_unset" ; + case morpheo::behavioural::BRANCH_CONDITION_FLAG_SET : return "flag_set" ; + case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : return "read_register_without_write_stack"; + case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : return "read_register_with_write_stack" ; + case morpheo::behavioural::BRANCH_CONDITION_READ_STACK : return "read_stack" ; + default : return ""; + } + }; + }; // end namespace morpheo Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Types.h (revision 97) @@ -152,24 +152,4 @@ }; // end namespace behavioural - - inline std::string toString_type(const morpheo::behavioural::Ttype_t& x) - { - switch (x) - { - case TYPE_ALU : return "ALU" ; break; - case TYPE_SHIFT : return "SHIFT" ; break; - case TYPE_MOVE : return "MOVE" ; break; - case TYPE_TEST : return "TEST" ; break; - case TYPE_MUL : return "MUL" ; break; - case TYPE_DIV : return "DIV" ; break; - case TYPE_EXTEND : return "EXTEND" ; break; - case TYPE_FIND : return "FIND" ; break; - case TYPE_SPECIAL : return "SPECIAL" ; break; - case TYPE_CUSTOM : return "CUSTOM" ; break; - case TYPE_BRANCH : return "BRANCH" ; break; - case TYPE_MEMORY : return "MEMORY" ; break; - default : return "Unknow type"; break; - } - }; template<> inline std::string toString(const morpheo::behavioural::Tpriority_t& x) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 97) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "96" +#define MORPHEO_REVISION "97" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "16" +#define MORPHEO_DATE_DAY "19" #define MORPHEO_DATE_MONTH "12" #define MORPHEO_DATE_YEAR "2008" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 97) @@ -23,12 +23,15 @@ namespace behavioural { - std::string std_logic (uint32_t size); - std::string std_logic_conv (uint32_t size, std::string value); - std::string std_logic_conv (uint32_t size, uint32_t value); - std::string std_logic_cst (uint32_t size, uint32_t value); - std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min , bool force=false); - std::string std_logic_range ( uint32_t max , uint32_t min , bool force=false); - std::string std_logic_range (uint32_t size, bool force=false); - std::string std_logic_others (uint32_t size, bool cst); + std::string std_logic (uint32_t size); + std::string std_logic_conv (uint32_t size, std::string value); + std::string std_logic_conv (uint32_t size, uint32_t value); + std::string std_logic_cst (uint32_t size, uint32_t value); + std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min ); + std::string std_logic_range ( uint32_t max , uint32_t min ); + std::string std_logic_range (uint32_t size ); + std::string _std_logic_range (uint32_t size, uint32_t max , uint32_t min ); + std::string _std_logic_range ( uint32_t max , uint32_t min ); + std::string _std_logic_range (uint32_t size ); + std::string std_logic_others (uint32_t size, bool cst); class Vhdl Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Component_test_map.cpp (revision 97) @@ -48,16 +48,17 @@ i != _list_component->end(); ++i) - { - test_ok &= (*i)->_entity->test_map(depth+1,false,is_behavioural); - if (recursive) - try - { - test_ok &= (*i)->_component->test_map(depth+1,recursive); - } - catch (morpheo::ErrorMorpheo & error) - { - // no error propagation, only top level - } - } + if (((*i)->_instance & INSTANCE_COMPONENT) != 0) + { + test_ok &= (*i)->_entity->test_map(depth+1,false,is_behavioural); + if (recursive) + try + { + test_ok &= (*i)->_component->test_map(depth+1,recursive); + } + catch (morpheo::ErrorMorpheo & error) + { + // no error propagation, only top level + } + } log_printf(FUNC,Behavioural,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_exist.cpp (revision 97) @@ -1,3 +1,4 @@ #include "Behavioural/include/SPR_access_mode.h" +// #include "Common/include/Debug.h" namespace morpheo { @@ -15,4 +16,9 @@ spr_access_mode_t mode = _spr_generic [num_group][num_reg]; +// log_printf(TRACE,true,"exist"," * exist"); +// log_printf(TRACE,true,"exist"," * num_group : %d",num_group); +// log_printf(TRACE,true,"exist"," * num_register : %d",num_reg); +// log_printf(TRACE,true,"exist"," * supervisor_access_mode : %d",mode._supervisor_access_mode); +// log_printf(TRACE,true,"exist"," * user_access_mode : %d",mode._user_access_mode ); return ((mode._supervisor_access_mode != SPR_ACCESS_MODE_NONE) or Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode_implement_group.cpp (revision 97) @@ -33,14 +33,14 @@ _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ 20]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - const uint32_t nb_shadow = 1; + const uint32_t nb_shadow = 1; // max 16 - for (uint32_t i=32; i<=32+nb_shadow; i++) - _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - for (uint32_t i=48; i<=48+nb_shadow; i++) - _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - for (uint32_t i=64; i<=64+nb_shadow; i++) - _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; - for (uint32_t i=1024; i<=1024+32*nb_shadow; i++) - _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; + for (uint32_t i=32; i<32+nb_shadow; i++) + _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; + for (uint32_t i=48; i<48+nb_shadow; i++) + _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; + for (uint32_t i=64; i<64+nb_shadow; i++) + _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; +// for (uint32_t i=1024; i<1024+32*nb_shadow; i++) +// _spr_generic [GROUP_SYSTEM_AND_CONTROL ][ i]._supervisor_access_mode = SPR_ACCESS_MODE_READ_WRITE; break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_set_body_component_port_map.cpp (revision 97) @@ -18,8 +18,8 @@ #define FUNCTION "Vhdl::set_body_component_port_map" void Vhdl::set_body_component_port_map (std::list & list_port_map , - std::string name_port , - uint32_t size_port , - std::string name_signal , - uint32_t size_signal ) + std::string name_port , + uint32_t size_port , + std::string name_signal , + uint32_t size_signal ) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Vhdl_std_logic.cpp (revision 97) @@ -80,25 +80,22 @@ #undef FUNCTION #define FUNCTION "Vhdl::std_logic_range" - std::string std_logic_range (uint32_t size, uint32_t max, uint32_t min, bool force) + std::string std_logic_range (uint32_t size, uint32_t max, uint32_t min) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); std::string type; - if (force) { - type = "("+toString(max)+" downto "+toString(min)+")"; - } - else - { - if (max == min) - { - type = "("+toString(max)+")"; - } + if (size < 2) + type = ""; else { - if (size < 2) - type = ""; + if (max == min) + { + type = "("+toString(max)+")"; + } else - type = "("+toString(max)+" downto "+toString(min)+")"; + { + type = "("+toString(max)+" downto "+toString(min)+")"; + } } } @@ -109,14 +106,9 @@ }; - std::string std_logic_range (uint32_t max, uint32_t min, bool force) + std::string std_logic_range (uint32_t max, uint32_t min) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); std::string type; - if (force) - { - type = "("+toString(max)+" downto "+toString(min)+")"; - } - else { if (max == min) @@ -138,8 +130,37 @@ }; - std::string std_logic_range (uint32_t size, bool force) + std::string std_logic_range (uint32_t size) { log_printf(FUNC,Behavioural,FUNCTION,"Begin"); - std::string _return = std_logic_range(size-1,0,force); + std::string _return = std_logic_range(size,size-1,0); + log_printf(FUNC,Behavioural,FUNCTION,"End"); + + return _return; + } + +#undef FUNCTION +#define FUNCTION "Vhdl::_std_logic_range" + std::string _std_logic_range (uint32_t size, uint32_t max, uint32_t min) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + std::string type=_std_logic_range(max,min); + log_printf(FUNC,Behavioural,FUNCTION,"End"); + + return type; + }; + + std::string _std_logic_range (uint32_t max, uint32_t min) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + std::string type = "("+toString(max)+" downto "+toString(min)+")"; + log_printf(FUNC,Behavioural,FUNCTION,"End"); + + return type; + }; + + std::string _std_logic_range (uint32_t size) + { + log_printf(FUNC,Behavioural,FUNCTION,"Begin"); + std::string _return = _std_logic_range(size,size-1,0); log_printf(FUNC,Behavioural,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Debug.h (revision 97) @@ -9,5 +9,4 @@ * function to help the debugging : * - * - debug_tab * - log_printf * - log_begin @@ -26,4 +25,6 @@ #include "Common/include/Message.h" +#include "Common/include/FromString.h" +#include "Common/include/ChangeCase.h" #include "Behavioural/include/Debug_component.h" #include @@ -36,5 +37,5 @@ namespace morpheo { -enum _debug_verbosity +typedef enum { DEBUG_NONE , @@ -43,17 +44,20 @@ DEBUG_FUNC , DEBUG_ALL - }; - -std::string debug_tab (void); -void debug_tab_inc (void); -void debug_tab_dec (void); - + } debug_verbosity_t; + + extern debug_verbosity_t debug; + +void debug_init (void); +void debug_init (debug_verbosity_t level); #ifdef DEBUG + # define log_printf(level, component, func, str... ) \ do \ { \ - if ((DEBUG == DEBUG_ALL ) or \ + debug_init(); \ + \ + if ((debug == DEBUG_ALL ) or \ (DEBUG_ ## level == DEBUG_NONE) or \ - (( DEBUG_ ## level <= DEBUG) and \ + (( DEBUG_ ## level <= debug) and \ ( DEBUG_ ## component == true )) ) \ { \ @@ -67,9 +71,5 @@ } \ \ - if (DEBUG >= DEBUG_FUNC) \ - { \ - msg("%s",debug_tab().c_str()); \ - } \ - if (DEBUG >= DEBUG_ALL ) \ + if (debug >= DEBUG_ALL ) \ { \ switch (DEBUG_ ## level) \ @@ -83,5 +83,5 @@ } \ } \ - if (DEBUG >= DEBUG_FUNC) \ + if (debug >= DEBUG_FUNC) \ { \ msg( "<%s> " ,func); \ @@ -98,5 +98,4 @@ do \ { \ - debug_tab_inc (); \ log_printf(FUNC,component,func,_("Begin")); \ } while(0) @@ -106,5 +105,4 @@ { \ log_printf(FUNC,component,func,_("End")); \ - debug_tab_dec (); \ } while(0) @@ -172,4 +170,33 @@ #endif + + template<> inline debug_verbosity_t fromString (const std::string& x) + { + std::string y=x; + LowerCase(y); + + if ( (y.compare("0") == 0) or + (y.compare("none") == 0)) + return DEBUG_NONE ; + if ( (y.compare("1") == 0) or + (y.compare("info") == 0)) + return DEBUG_INFO ; + if ( (y.compare("2") == 0) or + (y.compare("trace") == 0)) + return DEBUG_TRACE; + if ( (y.compare("3") == 0) or + (y.compare("func") == 0)) + return DEBUG_FUNC ; + if ( (y.compare("4") == 0) or + (y.compare("all") == 0)) + return DEBUG_ALL ; + +#ifdef DEBUG + return DEBUG; +#else + return DEBUG_NONE ; +#endif + } + }; // end namespace morpheo #endif // !DEBUG_H Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Message.h (revision 97) @@ -41,26 +41,17 @@ #endif -#ifdef LOG_FILE extern FILE * log_stream; -void log_init (void); +FILE * log (FILE * stream); +void log_init (bool have_file, + std::string directory, + std::string file=""); #define fmsg(stream,arg...) \ do \ { \ - log_init(); \ - fprintf(log_stream,arg); \ - fflush(log_stream); \ + FILE * _stream = log(stream); \ + fprintf(_stream,arg); \ + fflush(_stream); \ } while (0) - -#else - -#define fmsg(stream,arg...) \ - do \ - { \ - fprintf(stream,arg); \ - fflush(stream); \ - } while (0) - -#endif #define fmsgDebug(stream,arg...) \ Index: trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/include/Time.h (revision 97) @@ -15,10 +15,15 @@ { #ifdef SYSTEMC -private : double nb_cycles_begin; +private : const bool systemc; +private : double nb_cycles_begin; #endif -private : timeval time_begin; +private : timeval time_begin; // private : timeval time_end; -public : Time () +public : Time (bool systemc=true) +#ifdef SYSTEMC + : + systemc (systemc) +#endif { #ifdef SYSTEMC @@ -41,14 +46,19 @@ #ifdef SYSTEMC - double nb_cycles_end = sc_simulation_time(); - double average = static_cast(nb_cycles_end-x.nb_cycles_begin+1) / static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); - - output << "Timing : " << nb_cycles_end << " cycles \t(" << average << " cycles/s)" << std::endl; -#else - double average = static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); - - output << "Timing : " average << " s" << std::endl; + if (x.systemc) + { + double nb_cycles_end = sc_simulation_time(); + double average = static_cast(nb_cycles_end-x.nb_cycles_begin+1) / static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); + + output << "Timing : " << nb_cycles_end << " cycles \t(" << average << " cycles/s)" << std::endl; + } + else #endif - + { + double average = static_cast(time_end.tv_sec-x.time_begin.tv_sec+1); + + output << "Timing : " << average << " s" << std::endl; + } + return output; } Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Debug.cpp (revision 97) @@ -11,25 +11,36 @@ namespace morpheo { -static uint32_t _debug_depth = 0; +#ifdef DEBUG +static bool debug_initialized; +#endif +debug_verbosity_t debug; #undef FUNCTION -#define FUNCTION "debug_tab" -std::string debug_tab (void) +#define FUNCTION "debug_init" +void debug_init (void) { - return std::string(_debug_depth,'\t'); +#ifdef DEBUG + if (not debug_initialized) + { + debug = DEBUG; + +// debug_initialized = true; + } +#endif } #undef FUNCTION -#define FUNCTION "debug_tab_inc" -void debug_tab_inc (void) +#define FUNCTION "debug_init" +void debug_init (debug_verbosity_t level) { -// _debug_depth ++; -} - -#undef FUNCTION -#define FUNCTION "debug_tab_dec" -void debug_tab_dec (void) -{ -// _debug_depth --; +#ifdef DEBUG + if (not debug_initialized) + { + // Take min + debug = (level < DEBUG)?level:DEBUG; + + debug_initialized = true; + } +#endif } Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Environment.cpp (revision 97) @@ -9,4 +9,5 @@ #include "Common/include/ErrorMorpheo.h" #include "Common/include/Debug.h" +#include "Common/include/Message.h" #include Index: trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Common/src/Message.cpp (revision 97) @@ -1,3 +1,2 @@ -#ifdef LOG_FILE /* * $Id$ @@ -16,33 +15,48 @@ namespace morpheo { -static bool log_initialized; -FILE * log_stream; - + static bool log_initialized; + FILE * log_stream; + +#undef FUNCTION +#define FUNCTION "log" + FILE * log (FILE * stream) + { + // if log stream is initialized, take this, else return the default stream. + return (log_initialized and (log_stream!=NULL))?log_stream:stream; + }; + #undef FUNCTION #define FUNCTION "log_init" -void log_init (void) -{ - if (not log_initialized) - { - log_initialized = true; - - directory(); - - std::string filename = MORPHEO_LOG+"/Morpheo_"+toString(getpid())+".log"; - - log_stream = fopen (filename.c_str(), "w"); - - if (log_stream==NULL) - { - fprintf(stderr,_("%s Error create log file \"%s\", take the standard output.\n"),MSG_ERROR,filename.c_str()); - log_stream = stdout; - } - else - { - fprintf(stdout,_("%s Create log file \"%s\".\n"),MSG_INFORMATION,filename.c_str()); - } - } -} - + void log_init (bool have_file, + std::string directory, + std::string file) + { + if (not log_initialized) + { + log_initialized = true; + + if (have_file) + { + // if the file is not define, take pid. + std::string filename = directory+"/Morpheo_"+((file!="")?file:toString(getpid()))+".log"; + + log_stream = fopen (filename.c_str(), "w"); + + if (log_stream==NULL) + { + fprintf(stderr,_("%s Error create log file \"%s\", take the standard output.\n"),MSG_ERROR,filename.c_str()); + log_stream = stdout; + } + else + { + fprintf(stdout,_("%s Create log file \"%s\".\n"),MSG_INFORMATION,filename.c_str()); + } + } + else + { + log_stream = NULL; + } + } + } + }; // end namespace morpheo -#endif Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.gen (revision 97) @@ -20,4 +20,5 @@ + Index: trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/Files/Morpheo.sim (revision 97) @@ -10,5 +10,5 @@ - + @@ -18,10 +18,11 @@ - - - - + + + + - + + Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/toto =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/SelfTest/toto (revision 96) +++ (revision ) @@ -1,1754 +1,0 @@ --------------------| SelfTest -Create directory : obj -Create directory : /tmp/Morpheo/bin -Create directory : log -Create directory : obj -Compilation : Translation -Compilation : Environm-------------------| Common -Archive : libCommon -ar: creating lib/libCommon.a -a - obj/Debug.o -a - obj/Environment.o -a - obj/Message.o -a - obj/ToString.o -a - obj/Translation.o -Create directory : obj -Create directory : lib -Compilation : Vhdl_get_architecture -testbencComCompCompilation : Stat_create_counter -Archive : libBehavioural -ar: creating lib/libBehavioural.a -a - obj/Component.o -a - obj/Component_find_entity.o -a - obj/Component_generate_file.o -a - obj/Component_get_component.o -a - obj/Component_get_entity.o -a - obj/Component_get_name.o -a - obj/Component_interface_map.o -a - obj/Component_port_map.o -a - obj/Component_print.o -a - obj/Component_set_component.o -a - obj/Component_set_entity.o -a - obj/Component_signal_internal.o -a - obj/Component_test_map.o -a - obj/Component_toXML.o -a - obj/Component_vhdl_instance.o -a - obj/Entity.o -a - obj/Entity_find_interface.o -a - obj/Entity_find_signal.o -a - obj/Entity_get_comment.o -a - obj/Entity_get_interfaces.o -a - obj/Entity_get_name.o -a - obj/Entity_get_type.o -a - obj/Entity_mapping.o -a - obj/Entity_print.o -a - obj/Entity_set_comment.o -a - obj/Entity_set_interfaces.o -a - obj/Entity_test_map.o -a - obj/Entity_toXML.o -a - obj/Identification.o -a - obj/Interface.o -a - obj/Interface_fifo.o -a - obj/Interface_fifo_get_cycle.o -a - obj/Interface_fifo_save_ptr.o -a - obj/Interface_fifo_set_signal.o -a - obj/Interface_fifo_testbench.o -a - obj/Interface_fifo_testbench_cycle.o -a - obj/Interface_fifo_testbench_test.o -a - obj/Interface_fifo_testbench_test_transaction.o -a - obj/Interface_fifo_testbench_transaction.o -a - obj/Interface_find_signal.o -a - obj/Interface_get_clock.o -a - obj/Interface_get_comment.o -a - obj/Interface_get_cycle.o -a - obj/Interface_get_name.o -a - obj/Interface_get_reset.o -a - obj/Interface_get_signal.o -a - obj/Interface_interface_map.o -a - obj/Interface_print.o -a - obj/Interfaces.o -a - obj/Interface_set_comment.o -a - obj/Interface_set_port.o -a - obj/Interface_set_signal.o -a - obj/Interfaces_find_interface.o -a - obj/Interfaces_find_signal.o -a - obj/Interfaces_get_clock.o -a - obj/Interfaces_get_cycle.o -a - obj/Interfaces_get_interface.o -a - obj/Interfaces_get_reset.o -a - obj/Interfaces_get_signal.o -a - obj/Interface_signal_name.o -a - obj/Interfaces_print.o -a - obj/Interfaces_set_interface.o -a - obj/Interfaces_set_port.o -a - obj/Interfaces_set_signal.o -a - obj/Interfaces_testbench_body.o -a - obj/Interfaces_testbench.o -a - obj/Interfaces_testbench_generate_file.o -a - obj/Interfaces_test_map.o -a - obj/Interfaces_toXML.o -a - obj/Interface_testbench_body.o -a - obj/Interface_testbench.o -a - obj/Interface_testbench_cycle.o -a - obj/Interface_testbench_test.o -a - obj/Interface_testbench_test_name.o -a - obj/Interface_testbench_test_ok.o -a - obj/Interface_test_map.o -a - obj/Interface_toXML.o -a - obj/Parameters_copy.o -a - obj/Parameters.o -a - obj/Parameters_Statistics.o -a - obj/Parameters_test.o -a - obj/Signal_connect.o -a - obj/Signal.o -a - obj/Signal_get_clock.o -a - obj/Signal_get_connect_from_signal.o -a - obj/Signal_get_connect_to_signal.o -a - obj/Signal_get_direction.o -a - obj/Signal_get_name.o -a - obj/Signal_get_name_vhdl.o -a - obj/Signal_get_reset.o -a - obj/Signal_get_reset_cycle.o -a - obj/Signal_get_size.o -a - obj/Signal_get_type_info.o -a - obj/Signal_link.o -a - obj/Signal_presence_testbench.o -a - obj/Signal_presence_vhdl.o -a - obj/Signal_print.o -a - obj/Signal_set_port.o -a - obj/Signal_set_size.o -a - obj/Signal_testbench_body.o -a - obj/Signal_testbench.o -a - obj/Signal_testbench_test_ok.o -a - obj/Signal_test_map.o -a - obj/Signal_toXML.o -a - obj/Simulation.o -a - obj/Simulation_end_cycle.o -a - obj/Simulation_test_end.o -a - obj/SPR_access_mode_change_mode.o -a - obj/SPR_access_mode.o -a - obj/SPR_access_mode_exist.o -a - obj/SPR_access_mode_implement_group.o -a - obj/SPR_access_mode_invalid_register.o -a - obj/SPR_access_mode_read_write.o -a - obj/SPR_access_mode_translate_address.o -a - obj/SPR_access_mode_valid.o -a - obj/Stat_add_stat.o -a - obj/Stat_alloc_operand.o -a - obj/Stat_binary_tree_change_type.o -a - obj/Stat_binary_tree.o -a - obj/Stat_binary_tree_eval.o -a - obj/Stat_binary_tree_goto_next_root.o -a - obj/Stat_binary_tree_goto_top_level.o -a - obj/Stat_binary_tree_import.o -a - obj/Stat_binary_tree_insert_tree.o -a - obj/Stat_binary_tree_is_leaf.o -a - obj/Stat_binary_tree_valid.o -a - obj/Stat_binary_tree_val_leaf.o -a - obj/Stat_binary_tree_val_tree.o -a - obj/Stat.o -a - obj/Stat_create_counter.o -a - obj/Stat_create_expr.o -a - obj/Stat_create_variable.o -a - obj/Stat_end_cycle.o -a - obj/Stat_end_simulation.o -a - obj/Stat_eval_expr.o -a - obj/Stat_eval_exprs.o -a - obj/Stat_generate_file.o -a - obj/Stat_have_counter.o -a - obj/Stat_is_valid_var.o -a - obj/Stat_print.o -a - obj/Stat_string2tree.o -a - obj/Stat_test_and_save.o -a - obj/Test.o -a - obj/Types.o -a - obj/Usage.o -a - obj/Vhdl.o -a - obj/Vhdl_direction_toString.o -a - obj/Vhdl_generate_file.o -a - obj/Vhdl_generate_file_model.o -a - obj/Vhdl_generate_file_package.o -a - obj/Vhdl_get_alias.o -a - obj/Vhdl_get_architecture.o -a - obj/Vhdl_get_body.o -a - obj/Vhdl_get_component.o -a - obj/Vhdl_get_entity.o -a - obj/Vhdl_get_header.o -a - obj/Vhdl_get_library_ieee.o -a - obj/Vhdl_get_library_work.o -a - obj/Vhdl_get_list.o -a - obj/Vhdl_get_model.o -a - obj/Vhdl_get_package.o -a - obj/Vhdl_get_port.o -a - obj/Vhdl_get_signal.o -a - obj/Vhdl_get_type.o -a - obj/Vhdl_set_alias.o -a - obj/Vhdl_set_body_component.o -a - obj/Vhdl_set_body_component_port_map.o -a - obj/Vhdl_set_body.o -a - obj/Vhdl_set_constant.o -a - obj/Vhdl_set_library_work.o -a - obj/Vhdl_set_list.o -a - obj/Vhdl_set_port.o -a - obj/Vhdl_set_signal.o -a - obj/Vhdl_set_type.o -a - obj/Vhdl_std_logic.o -a - obj/XML_attribut.o -a - obj/XML_balise_close.o -a - obj/XML_balise_open_begin.o -a - obj/XML_balise_open.o -a - obj/XML_balise_open_end.o -a - obj/XML_comment.o -a - obj/XML.o -a - obj/XML_depth.o -a - obj/XML_filename_extension.o -a - obj/XML_generate_file.o -a - obj/XML_get_body.o -a - obj/XML_header.o -a - obj/XML_indent.o -a - obj/XML_insert_XML.o -a - obj/XMLLightFunctors.o -a - obj/XML_singleton_begin.o -a - obj/XML_singleton.o -a - obj/XML_singleton_end.o -a - obj/XML_text.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Instruction --------------------| Instruction -Archive : libInstruction -ar: creating lib/libInstruction.a -a - obj/Instruction.o -Create directory : obj -Compilation : Operation --------------------| Operation -Archive : libOperation -ar: creating lib/libOperation.a -a - obj/Operation.o -Create directory : obj -Compilation : Custom_default --------------------| Custom -Archive : libCustom -ar: creating lib/libCustom.a -a - obj/Custom_default.o -a - obj/Custom_example.o -a - obj/Encryption.o -a - obj/Random.o -Create directory : obj -Compilation : Generator_getLinkCompilation : Instance_gCompilation : Link_affectation_print --------------------| Configuration -File -Compilation : Parameter_affectation_toXML -src/Instance_link2array.cpp: In member function 'std::vector, std::allocator >, std::allocator, std::allocator > > > morpheo::behavioural::configuration::Instance::link2array(std::string)': -src/Instance_link2array.cpp:33: attention : comparaison est toujours vraie en raison d'une gamme limitée de type de données -Archive : libConfiguration -ar: creating lib/libConfiguration.a -a - obj/Configuration.o -a - obj/Configuration_getName.o -a - obj/Configuration_getParam.o -a - obj/Configuration_getParamStatistics.o -a - obj/Configuration_getUsage.o -a - obj/Configuration_print.o -a - obj/Configuration_toFile.o -a - obj/Generator.o -a - obj/Generator_fromFile.o -a - obj/Generator_getLink.o -a - obj/Generator_getParam.o -a - obj/Generator_insert.o -a - obj/Generator_print.o -a - obj/Generator_test.o -a - obj/Generator_toFile.o -a - obj/Generator_toXML.o -a - obj/Instance.o -a - obj/Instance_fromFile.o -a - obj/Instance_fromInternalStructure.o -a - obj/Instance_fromXMLLight.o -a - obj/Instance_getLink.o -a - obj/Instance_getName.o -a - obj/Instance_getParam.o -a - obj/Instance_link2array.o -a - obj/Instance_print.o -a - obj/Instance_test.o -a - obj/Instance_test_use.o -a - obj/Instance_toFile.o -a - obj/Instance_toXML.o -a - obj/Link_affectation.o -a - obj/Link_affectation_print.o -a - obj/Link_affectation_toXML.o -a - obj/Link_definition.o -a - obj/Link_definition_print.o -a - obj/Link_definition_toXML.o -a - obj/Parameter_affectation.o -a - obj/Parameter_affectation_print.o -a - obj/Parameter_affectation_toXML.o -a - obj/Parameter_definition.o -a - obj/Parameter_definition_print.o -a - obj/Parameter_definition_test.o -a - obj/Parameter_definition_toXML.o -a - obj/Simulator.o -a - obj/Simulator_fromFile.o -a - obj/Simulator_getParam.o -a - obj/Simulator_insert.o -a - obj/Simulator_print.o -a - obj/Simulator_toFile.o -a - obj/Simulator_toXML.o -a - obj/XMLUtils_getAttribute.o -a - obj/XMLUtils_testAttributesEmpty.o -a - obj/XMLUtils_testNoAttribute.o -a - obj/XMLUtils_testNodeName.o -a - obj/XMLUtils_testSingleton.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Priority_reset_load_balancing_noneCompilation : Priority_allocation -Archive : libPriority -ar: creating lib/libPriority.a -a - obj/Priority_allocation.o -a - obj/Priority.o -a - obj/Priority_deallocation.o -a - obj/Priority_reset.o -a - obj/Priority_reset_load_balancing_balance.o -a - obj/Priority_reset_load_balancing_maximum_for_priority.o -a - obj/Priority_reset_load_balancing_none.o -a - obj/Priority_reset_load_balancing_priority_only.o -a - obj/Priority_reset_priority_none.o -a - obj/Priority_reset_priority_round_robin.o -a - obj/Priority_reset_priority_static.o -a - obj/Priority_select.o -a - obj/Priority_transition.o -a - obj/Priority_transition_load_balancing_balance.o -a - obj/Priority_transition_load_balancing_maximum_for_priority.o -a - obj/Priority_transition_load_balancing_none.o -a - obj/Priority_transition_load_balancing_priority_only.o -a - obj/Priority_transition_priority_none.o -a - obj/Priority_transition_priority_round_robin.o -a - obj/Priority_transition_priority_static.o --------------------| Common -Create directory : obj -Compilation : Icache_Access_deallocCompCompilCompilation Compilation : Icache_Access_end_cycle -Archive : libIcache_Access -ar: creating lib/libIcache_Access.a -a - obj/Icache_Access_allocation.o -a - obj/Icache_Access.o -a - obj/Icache_Access_deallocation.o -a - obj/Icache_Access_end_cycle.o -a - obj/Icache_Access_genMealy_req.o -a - obj/Icache_Access_genMealy_rsp.o -a - obj/Icache_Access_statistics_allocation.o -a - obj/Icache_Access_statistics_deallocation.o -a - obj/Icache_Access_transition.o -a - obj/Icache_Access_vhdl_body.o -a - obj/Icache_Access_vhdl.o -a - obj/Icache_Access_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Compilation : Dcache_AcceCompilation : Dcache_Access_genMealy_rCompilation : Dcache_Access_deallocation -Archive : libDcache_Access -ar: creating lib/libDcache_Access.a -a - obj/Dcache_Access_allocation.o -a - obj/Dcache_Access.o -a - obj/Dcache_Access_deallocation.o -a - obj/Dcache_Access_end_cycle.o -a - obj/Dcache_Access_genMealy_req.o -a - obj/Dcache_Access_genMealy_rsp.o -a - obj/Dcache_Access_statistics_allocation.o -a - obj/Dcache_Access_statistics_deallocation.o -a - obj/Dcache_Access_transition.o -a - obj/Dcache_Access_vhdl_body.o -a - obj/Dcache_Access_vhdl.o -a - obj/Dcache_Access_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Address_management -Compilation : Parameters -agement_statistics_deallocatioCompilation : Address_management_vhdl --------------------| Address_management -Compilation : Address_management_allocation -Compilation : Address_management_end_cycle -Compilation : Address_management_transition -Archive : libAddress_management -ar: creating lib/libAddress_management.a -a - obj/Address_management_allocation.o -a - obj/Address_management.o -a - obj/Address_management_deallocation.o -a - obj/Address_management_end_cycle.o -a - obj/Address_management_genMoore.o -a - obj/Address_management_statistics_allocation.o -a - obj/Address_management_statistics_deallocation.o -a - obj/Address_management_transition.o -a - obj/Address_management_vhdl_body.o -a - obj/Address_management_vhdl.o -a - obj/Address_management_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Ifetch_queue_statCompilation : Ifetch_queue_allocation -e --------------------| Ifetch_queue -Archive : libIfetch_queue -ar: creating lib/libIfetch_queue.a -a - obj/Ifetch_queue_allocation.o -a - obj/Ifetch_queue.o -a - obj/Ifetch_queue_deallocation.o -a - obj/Ifetch_queue_end_cycle.o -a - obj/Ifetch_queue_genMoore.o -a - obj/Ifetch_queue_statistics_allocation.o -a - obj/Ifetch_queue_statistics_deallocation.o -a - obj/Ifetch_queue_transition.o -a - obj/Ifetch_queue_vhdl_body.o -a - obj/Ifetch_queue_vhdl.o -a - obj/Ifetch_queue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Ifetch_unit_Glue_vhdlCompilation : Ifetch_unitCompilation : Ifetch_unit_Glue_allocation -Compilation : Ifetch_unit_Glue_statistics_deallocation --------------------| Ifetch_unit_Glue -Archive : libIfetch_unit_Glue -ar: creating lib/libIfetch_unit_Glue.a -a - obj/Ifetch_unit_Glue_allocation.o -a - obj/Ifetch_unit_Glue.o -a - obj/Ifetch_unit_Glue_deallocation.o -a - obj/Ifetch_unit_Glue_end_cycle.o -a - obj/Ifetch_unit_Glue_genMealy_event.o -a - obj/Ifetch_unit_Glue_genMealy_icache_req.o -a - obj/Ifetch_unit_Glue_statistics_allocation.o -a - obj/Ifetch_unit_Glue_statistics_deallocation.o -a - obj/Ifetch_unit_Glue_transition.o -a - obj/Ifetch_unit_Glue_vhdl_body.o -a - obj/Ifetch_unit_Glue_vhdl.o -a - obj/Ifetch_unit_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Ifetch_unit_transCompi-------------------| Ifetch_unit -Archive : libIfetch_unit -ar: creating lib/libIfetch_unit.a -a - obj/Ifetch_unit_allocation.o -a - obj/Ifetch_unit.o -a - obj/Ifetch_unit_deallocation.o -a - obj/Ifetch_unit_end_cycle.o -a - obj/Ifetch_unit_statistics_allocation.o -a - obj/Ifetch_unit_statistics_deallocation.o -a - obj/Ifetch_unit_transition.o -a - obj/Ifetch_unit_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Branch_Targ-------------------| Branch_TargCompilation : Branch_Target_Buffer_Glue_statistics_deallocation -_Buffer_Glue_vhdl_declaration -Compilation : Branch_Target_Buffer_Glue_end_cycle -Archive : libBranch_Target_Buffer_Glue -ar: creating lib/libBranch_Target_Buffer_Glue.a -a - obj/Branch_Target_Buffer_Glue_allocation.o -a - obj/Branch_Target_Buffer_Glue.o -a - obj/Branch_Target_Buffer_Glue_deallocation.o -a - obj/Branch_Target_Buffer_Glue_end_cycle.o -a - obj/Branch_Target_Buffer_Glue_genMealy_decod.o -a - obj/Branch_Target_Buffer_Glue_genMealy_predict.o -a - obj/Branch_Target_Buffer_Glue_genMealy_update.o -a - obj/Branch_Target_Buffer_Glue_statistics_allocation.o -a - obj/Branch_Target_Buffer_Glue_statistics_deallocation.o -a - obj/Branch_Target_Buffer_Glue_transition.o -a - obj/Branch_Target_Buffer_Glue_vhdl_body.o -a - obj/Branch_Target_Buffer_Glue_vhdl.o -a - obj/Branch_Target_Buffer_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Branch_Target_Buffer_Register_genMeCompilation Compilation : Branch-------------------| Branch_Target_Buffer_Register -Archive : libBranch_Target_Buffer_Register -ar: creating lib/libBranch_Target_Buffer_Register.a -a - obj/Branch_Target_Buffer_Register_allocation.o -a - obj/Branch_Target_Buffer_Register.o -a - obj/Branch_Target_Buffer_Register_deallocation.o -a - obj/Branch_Target_Buffer_Register_end_cycle.o -a - obj/Branch_Target_Buffer_Register_genMealy_decod.o -a - obj/Branch_Target_Buffer_Register_genMealy_predict.o -a - obj/Branch_Target_Buffer_Register_genMealy_update.o -a - obj/Branch_Target_Buffer_Register_statistics_allocation.o -a - obj/Branch_Target_Buffer_Register_statistics_deallocation.o -a - obj/Branch_Target_Buffer_Register_transition.o -a - obj/Branch_Target_Buffer_Register_vhdl_body.o -a - obj/Branch_Target_Buffer_Register_vhdl.o -a - obj/Branch_Target_Buffer_Register_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : ParamCompilatio-------------------| Sort -on -arameters_printCompilation : Parameters -Compilation : Sort_allocation -Archive : libSort -ar: creating lib/libSort.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Sort_allocation.o -a - obj/Sort.o -a - obj/Sort_deallocation.o -a - obj/Sort_end_cycle.o -a - obj/Sort_genMealy.o -a - obj/Sort_statistics_allocation.o -a - obj/Sort_statistics_deallocation.o -a - obj/Sort_transition.o -a - obj/Sort_vhdl_body.o -a - obj/Sort_vhdl.o -a - obj/Sort_vhdl_declaration.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Victim_Pseudo_LRU_vhdCompilation : Parameters - : Victim_Pseudo_LRCompilation : Victim_Pseudo_LRU_deallocation -Archive : libVictim_Pseudo_LRU -ar: creating lib/libVictim_Pseudo_LRU.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Victim_Pseudo_LRU_allocation.o -a - obj/Victim_Pseudo_LRU.o -a - obj/Victim_Pseudo_LRU_deallocation.o -a - obj/Victim_Pseudo_LRU_end_cycle.o -a - obj/Victim_Pseudo_LRU_genMealy.o -a - obj/Victim_Pseudo_LRU_statistics_declaration.o -a - obj/Victim_Pseudo_LRU_transition.o -a - obj/Victim_Pseudo_LRU_vhdl_body.o -a - obj/Victim_Pseudo_LRU_vhdl.o -a - obj/Victim_Pseudo_LRU_vhdl_declaration.o -Create directory : obj -Compilation : Victim_deallocatio-------------------| Victim -Compilation : Parameters_print -Archive : libVictim -ar: creating lib/libVictim.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Victim_allocation.o -a - obj/Victim.o -a - obj/Victim_deallocation.o -Create directory : obj -Compilation : Branch_TargCompilation -------------------| Branch_Target_Buffer -Archive : libBranch_Target_Buffer -ar: creating lib/libBranch_Target_Buffer.a -a - obj/Branch_Target_Buffer_allocation.o -a - obj/Branch_Target_Buffer.o -a - obj/Branch_Target_Buffer_deallocation.o -a - obj/Branch_Target_Buffer_end_cycle.o -a - obj/Branch_Target_Buffer_statistics_allocation.o -a - obj/Branch_Target_Buffer_statistics_deallocation.o -a - obj/Branch_Target_Buffer_transition.o -a - obj/Branch_Target_Buffer_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Direction_Glue_vhdl -yCompilationCompiCompilation : Direction_Glue_genMealy_update -Archive : libDirection_Glue -ar: creating lib/libDirection_Glue.a -a - obj/Direction_Glue_allocation.o -a - obj/Direction_Glue.o -a - obj/Direction_Glue_deallocation.o -a - obj/Direction_Glue_end_cycle.o -a - obj/Direction_Glue_genMealy_predict.o -a - obj/Direction_Glue_genMealy_update.o -a - obj/Direction_Glue_statistics_allocation.o -a - obj/Direction_Glue_statistics_deallocation.o -a - obj/Direction_Glue_transition.o -a - obj/Direction_Glue_vhdl_body.o -a - obj/Direction_Glue_vhdl.o -a - obj/Direction_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Direction_statistics_CoCompilation : Parameters_print -Archive : libDirection -ar: creating lib/libDirection.a -a - obj/Direction_allocation.o -a - obj/Direction.o -a - obj/Direction_deallocation.o -a - obj/Direction_end_cycle.o -a - obj/Direction_statistics_allocation.o -a - obj/Direction_statistics_deallocation.o -a - obj/Direction_transition.o -a - obj/Direction_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Return_Address_Stack_statistics_dealloCompilation : Parameters --------------------| Return_Address_Stack -Archive : libReturn_Address_Stack -ar: creating lib/libReturn_Address_Stack.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Return_Address_Stack_allocation.o -a - obj/Return_Address_Stack.o -a - obj/Return_Address_Stack_deallocation.o -a - obj/Return_Address_Stack_end_cycle.o -a - obj/Return_Address_Stack_genMealy_decod.o -a - obj/Return_Address_Stack_genMealy_predict.o -a - obj/Return_Address_Stack_statistics_allocation.o -a - obj/Return_Address_Stack_statistics_deallocation.o -a - obj/Return_Address_Stack_transition.o -a - obj/Return_Address_Stack_vhdl_body.o -a - obj/Return_Address_Stack_vhdl.o -a - obj/Return_Address_Stack_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Update_Prediction_Table_end_cCompilation : Update_Prediction_Table_genMealy_predict -Archive : libUpdate_Prediction_Table -ar: creating lib/libUpdate_Prediction_Table.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Update_Prediction_Table_allocation.o -a - obj/Update_Prediction_Table.o -a - obj/Update_Prediction_Table_deallocation.o -a - obj/Update_Prediction_Table_end_cycle.o -a - obj/Update_Prediction_Table_genMealy_branch_complete.o -a - obj/Update_Prediction_Table_genMealy_decod.o -a - obj/Update_Prediction_Table_genMealy_predict.o -a - obj/Update_Prediction_Table_genMoore.o -a - obj/Update_Prediction_Table_statistics_allocation.o -a - obj/Update_Prediction_Table_statistics_deallocation.o -a - obj/Update_Prediction_Table_transition.o -a - obj/Update_Prediction_Table_vhdl_body.o -a - obj/Update_Prediction_Table_vhdl.o -a - obj/Update_Prediction_Table_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Prediction_unit_Glue_statisticsCompilation : Prediction_unit_Glue_genMealy_decod -t -_deCompilation : Parameters_msg_error - --------------------| Prediction_unit_Glue -Archive : libPrediction_unit_Glue -ar: creating lib/libPrediction_unit_Glue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Prediction_unit_Glue_allocation.o -a - obj/Prediction_unit_Glue.o -a - obj/Prediction_unit_Glue_deallocation.o -a - obj/Prediction_unit_Glue_end_cycle.o -a - obj/Prediction_unit_Glue_genMealy_decod.o -a - obj/Prediction_unit_Glue_genMealy_predict.o -a - obj/Prediction_unit_Glue_genMealy_update.o -a - obj/Prediction_unit_Glue_statistics_allocation.o -a - obj/Prediction_unit_Glue_statistics_deallocation.o -a - obj/Prediction_unit_Glue_transition.o -a - obj/Prediction_unit_Glue_vhdl_body.o -a - obj/Prediction_unit_Glue_vhdl.o -a - obj/Prediction_unit_Glue_vhdl_declaration.o -Create directory : obj -Compilation : Prediction_unit_-------------------| Prediction_unit -Archive : libPrediction_unit -ar: creating lib/libPrediction_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Prediction_unit_allocation.o -a - obj/Prediction_unit.o -a - obj/Prediction_unit_deallocation.o -a - obj/Prediction_unit_end_cycle.o -a - obj/Prediction_unit_statistics_allocation.o -a - obj/Prediction_unit_statistics_deallocation.o -a - obj/Prediction_unit_transition.o -a - obj/Prediction_unit_vhdl.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common --------------------| Common --------------------| Behavioural --------------------| Instruction --------------------| Operation --------------------| Custom -Create directory : obj -Compilation : Decod_transition-------------------| Decod -Archive : libDecod -ar: creating lib/libDecod.a -a - obj/Decod_allocation.o -a - obj/Decod.o -a - obj/Decod_deallocation.o -a - obj/Decod_end_cycle.o -a - obj/Decod_genMealy.o -a - obj/Decod_statistics_allocation.o -a - obj/Decod_statistics_deallocation.o -a - obj/Decod_transition.o -a - obj/Decod_vhdl_body.o -a - obj/Decod_vhdl.o -a - obj/Decod_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Decod_queueCompilation : Decod_queu-------------------| Decod_queue -Archive : libDecod_queue -ar: creating lib/libDecod_queue.a -a - obj/Decod_queue_allocation.o -a - obj/Decod_queue.o -a - obj/Decod_queue_deallocation.o -a - obj/Decod_queue_end_cycle.o -a - obj/Decod_queue_genMealy_decod_out.o -a - obj/Decod_queue_genMoore.o -a - obj/Decod_queue_statistics_allocation.o -a - obj/Decod_queue_statistics_deallocation.o -a - obj/Decod_queue_transition.o -a - obj/Decod_queue_vhdl_body.o -a - obj/Decod_queue_vhdl.o -a - obj/Decod_queue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Decod_unit_statiCompilation : Decod_unit_end_cycle -n -n --------------------| Decod_unit -Compilation : Decod_unit_statistics_allocation -Archive : libDecod_unit -ar: creating lib/libDecod_unit.a -a - obj/Decod_unit_allocation.o -a - obj/Decod_unit.o -a - obj/Decod_unit_deallocation.o -a - obj/Decod_unit_end_cycle.o -a - obj/Decod_unit_statistics_allocation.o -a - obj/Decod_unit_statistics_deallocation.o -a - obj/Decod_unit_transition.o -a - obj/Decod_unit_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Context_State_endCoCompilation : Context_State -vhdl_declaratio-------------------| Context_State -Archive : libContext_State -ar: creating lib/libContext_State.a -a - obj/Context_State_allocation.o -a - obj/Context_State.o -a - obj/Context_State_deallocation.o -a - obj/Context_State_end_cycle.o -a - obj/Context_State_genMoore.o -a - obj/Context_State_statistics_allocation.o -a - obj/Context_State_statistics_deallocation.o -a - obj/Context_State_transition.o -a - obj/Context_State_vhdl_body.o -a - obj/Context_State_vhdl.o -a - obj/Context_State_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Parameters_Compilation : Parameters_prin-------------------| Front_end_Glue -Archive : libFront_end_Glue -ar: creating lib/libFront_end_Glue.a -a - obj/Front_end_Glue_allocation.o -a - obj/Front_end_Glue.o -a - obj/Front_end_Glue_deallocation.o -a - obj/Front_end_Glue_end_cycle.o -a - obj/Front_end_Glue_genMealy_branch_complete.o -a - obj/Front_end_Glue_genMealy_decod.o -a - obj/Front_end_Glue_genMealy_depth.o -a - obj/Front_end_Glue_genMealy_event.o -a - obj/Front_end_Glue_statistics_allocation.o -a - obj/Front_end_Glue_statistics_deallocation.o -a - obj/Front_end_Glue_transition.o -a - obj/Front_end_Glue_vhdl_body.o -a - obj/Front_end_Glue_vhdl.o -a - obj/Front_end_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Front_end_statistCompilation : Front_end_end_cycle - -CoCreate directory : lib -Archive : libFront_end -ar: creating lib/libFront_end.a -a - obj/Front_end_allocation.o -a - obj/Front_end.o -a - obj/Front_end_deallocation.o -a - obj/Front_end_end_cycle.o -a - obj/Front_end_statistics_allocation.o -a - obj/Front_end_statistics_deallocation.o -a - obj/Front_end_transition.o -a - obj/Front_end_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Create directory : lib --------------------| Commit_unit -src/Commit_unit_transition.cpp: In member function 'void morpheo::behavioural::core::multi_ooo_engine::ooo_engine::commit_unit::Commit_unit::transition()': -src/Commit_unit_transition.cpp:460: attention : format '%d' expects type 'int', but argument 4 has type 'size_t' -Archive : libCommit_unit -ar: creating lib/libCommit_unit.a -a - obj/Commit_unit_allocation.o -a - obj/Commit_unit.o -a - obj/Commit_unit_deallocation.o -a - obj/Commit_unit_end_cycle.o -a - obj/Commit_unit_genMealy_commit.o -a - obj/Commit_unit_genMealy_insert.o -a - obj/Commit_unit_genMealy_retire.o -a - obj/Commit_unit_genMoore.o -a - obj/Commit_unit_statistics_allocation.o -a - obj/Commit_unit_statistics_deallocation.o -a - obj/Commit_unit_transition.o -a - obj/Commit_unit_vhdl_body.o -a - obj/Commit_unit_vhdl.o -a - obj/Commit_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Compilation : Issue_queueCCompilation : Issue_queue_statistics_allocation -src/Issue_queue_transition.cpp: In member function 'void morpheo::behavioural::core::multi_ooo_engine::ooo_engine::issue_queue::Issue_queue::transition()': -src/Issue_queue_transition.cpp:157: attention : format '%d' expects type 'int', but argument 4 has type 'size_t' -Archive : libIssue_queue -ar: creating lib/libIssue_queue.a -a - obj/Issue_queue_allocation.o -a - obj/Issue_queue.o -a - obj/Issue_queue_deallocation.o -a - obj/Issue_queue_end_cycle.o -a - obj/Issue_queue_genMealy.o -a - obj/Issue_queue_genMoore.o -a - obj/Issue_queue_statistics_allocation.o -a - obj/Issue_queue_statistics_deallocation.o -a - obj/Issue_queue_transition.o -a - obj/Issue_queue_vhdl_body.o -a - obj/Issue_queue_vhdl.o -a - obj/Issue_queue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Compilation : Reexecute_unit_vhdl_body - -allocaCreate -------------------| Reexecute_unit -Archive : libReexecute_unit -ar: creating lib/libReexecute_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Reexecute_unit_allocation.o -a - obj/Reexecute_unit.o -a - obj/Reexecute_unit_deallocation.o -a - obj/Reexecute_unit_end_cycle.o -a - obj/Reexecute_unit_genMealy_commit.o -a - obj/Reexecute_unit_genMealy_reexecute.o -a - obj/Reexecute_unit_genMoore.o -a - obj/Reexecute_unit_must_reexecute.o -a - obj/Reexecute_unit_statistics_allocation.o -a - obj/Reexecute_unit_statistics_deallocation.o -a - obj/Reexecute_unit_transition.o -a - obj/Reexecute_unit_vhdl_body.o -a - obj/Reexecute_unit_vhdl.o -a - obj/Reexecute_unit_vhdl_declaration.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Load_Store_pointeCompilation : Load_Store_pointer_unit_genMealy_retire -Compilation : Load_Store_pointer_unit_statistics_declaration -Compilation : LoadCompilation : Load_Store_pointer_unit_vhdl_body -Compilation : Load_Store_pointer_unit_genMealy_insert --------------------| Load_Store_pointer_unit -Archive : libLoad_Store_pointer_unit -ar: creating lib/libLoad_Store_pointer_unit.a -a - obj/Load_Store_pointer_unit_allocation.o -a - obj/Load_Store_pointer_unit.o -a - obj/Load_Store_pointer_unit_deallocation.o -a - obj/Load_Store_pointer_unit_end_cycle.o -a - obj/Load_Store_pointer_unit_genMealy_insert.o -a - obj/Load_Store_pointer_unit_genMealy_retire.o -a - obj/Load_Store_pointer_unit_statistics_declaration.o -a - obj/Load_Store_pointer_unit_transition.o -a - obj/Load_Store_pointer_unit_vhdl_body.o -a - obj/Load_Store_pointer_unit_vhdl.o -a - obj/Load_Store_pointer_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Register_Address_Translation_unit_-------------------| Register_Address_Translation_unit -Archive : libRegister_Address_Translation_unit -ar: creating lib/libRegister_Address_Translation_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Register_Address_Translation_unit_allocation.o -a - obj/Register_Address_Translation_unit.o -a - obj/Register_Address_Translation_unit_deallocation.o -a - obj/Register_Address_Translation_unit_end_cycle.o -a - obj/Register_Address_Translation_unit_genMealy_rename.o -a - obj/Register_Address_Translation_unit_genMealy_retire.o -a - obj/Register_Address_Translation_unit_statistics_declaration.o -a - obj/Register_Address_Translation_unit_transition.o -a - obj/Register_Address_Translation_unit_vhdl_body.o -a - obj/Register_Address_Translation_unit_vhdl.o -a - obj/Register_Address_Translation_unit_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Free_List_uCompilation -------------------| Free_List_unit -Archive : libFree_List_unit -ar: creating lib/libFree_List_unit.a -a - obj/Free_List_unit_allocation.o -a - obj/Free_List_unit.o -a - obj/Free_List_unit_deallocation.o -a - obj/Free_List_unit_end_cycle.o -a - obj/Free_List_unit_genMealy_pop.o -a - obj/Free_List_unit_genMealy_push_gpr.o -a - obj/Free_List_unit_genMealy_push_spr.o -a - obj/Free_List_unit_statistics_declaration.o -a - obj/Free_List_unit_transition.o -a - obj/Free_List_unit_vhdl_body.o -a - obj/Free_List_unit_vhdl.o -a - obj/Free_List_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Para-----------------Compilation : Stat_List_unit -Archive : libStat_List_unit -ar: creating lib/libStat_List_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Stat_List_unit_allocation.o -a - obj/Stat_List_unit.o -a - obj/Stat_List_unit_deallocation.o -a - obj/Stat_List_unit_end_cycle.o -a - obj/Stat_List_unit_genMealy.o -a - obj/Stat_List_unit_genMoore.o -a - obj/Stat_List_unit_statistics_declaration.o -a - obj/Stat_List_unit_transition.o -a - obj/Stat_List_unit_vhdl_body.o -a - obj/Stat_List_unit_vhdl.o -a - obj/Stat_List_unit_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Create directory : lib -ndency_checking_unit_allocation -Compilation : Dependency_checking_unit_deallocation -Archive : libDependency_checking_unit -ar: creating lib/libDependency_checking_unit.a -a - obj/Dependency_checking_unit_allocation.o -a - obj/Dependency_checking_unit.o -a - obj/Dependency_checking_unit_deallocation.o -a - obj/Dependency_checking_unit_end_cycle.o -a - obj/Dependency_checking_unit_genMealy.o -a - obj/Dependency_checking_unit_statistics_declaration.o -a - obj/Dependency_checking_unit_transition.o -a - obj/Dependency_checking_unit_vhdl_body.o -a - obj/Dependency_checking_unit_vhdl.o -a - obj/Dependency_checking_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Register_translation_unit_Glue_vhdl_CompiCompilation : Parameters -rror -unit_Glue -deallocatiCre-------------------| Register_translation_unit_Glue -Archive : libRegister_translation_unit_Glue -ar: creating lib/libRegister_translation_unit_Glue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Register_translation_unit_Glue_allocation.o -a - obj/Register_translation_unit_Glue.o -a - obj/Register_translation_unit_Glue_deallocation.o -a - obj/Register_translation_unit_Glue_end_cycle.o -a - obj/Register_translation_unit_Glue_genMealy_insert.o -a - obj/Register_translation_unit_Glue_genMealy_insert_valack.o -a - obj/Register_translation_unit_Glue_genMealy_retire.o -a - obj/Register_translation_unit_Glue_statistics_declaration.o -a - obj/Register_translation_unit_Glue_transition.o -a - obj/Register_translation_unit_Glue_vhdl_body.o -a - obj/Register_translation_unit_Glue_vhdl.o -a - obj/Register_translation_unit_Glue_vhdl_declaration.o -Create directory : obj -Compilation : Register_translation_unit_deallocatiCompilation : Parameters -print -ion_-------------------| Register_translation_unit -Archive : libRegister_translation_unit -ar: creating lib/libRegister_translation_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Register_translation_unit_allocation.o -a - obj/Register_translation_unit.o -a - obj/Register_translation_unit_deallocation.o -a - obj/Register_translation_unit_end_cycle.o -a - obj/Register_translation_unit_statistics_declaration.o -a - obj/Register_translation_unit_transition.o -a - obj/Register_translation_unit_vhdl.o --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Compilation : Rename_select_deallCompilation : Rename_select_genMealy --------------------| Rename_select -Archive : libRename_select -ar: creating lib/libRename_select.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Rename_select_allocation.o -a - obj/Rename_select.o -a - obj/Rename_select_deallocation.o -a - obj/Rename_select_end_cycle.o -a - obj/Rename_select_genMealy.o -a - obj/Rename_select_statistics_declaration.o -a - obj/Rename_select_transition.o -a - obj/Rename_select_vhdl_body.o -a - obj/Rename_select_vhdl.o -a - obj/Rename_select_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Rename_unit_Glue_statisticsCompilation : Rename_unit_Glue_allocation -Archive : libRename_unit_Glue -ar: creating lib/libRename_unit_Glue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Rename_unit_Glue_allocation.o -a - obj/Rename_unit_Glue.o -a - obj/Rename_unit_Glue_deallocation.o -a - obj/Rename_unit_Glue_end_cycle.o -a - obj/Rename_unit_Glue_genMealy_insert.o -a - obj/Rename_unit_Glue_genMealy_insert_valack.o -a - obj/Rename_unit_Glue_genMealy_retire_valack.o -a - obj/Rename_unit_Glue_statistics_allocation.o -a - obj/Rename_unit_Glue_statistics_deallocation.o -a - obj/Rename_unit_Glue_transition.o -a - obj/Rename_unit_Glue_vhdl_body.o -a - obj/Rename_unit_Glue_vhdl.o -a - obj/Rename_unit_Glue_vhdl_declaration.o -Create directory : obj -Compilation : Parameters_msg_erCreat-------------------| Rename_unit -Archive : libRename_unit -ar: creating lib/libRename_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Rename_unit_allocation.o -a - obj/Rename_unit.o -a - obj/Rename_unit_deallocation.o -a - obj/Rename_unit_end_cycle.o -a - obj/Rename_unit_statistics_allocation.o -a - obj/Rename_unit_statistics_deallocation.o -a - obj/Rename_unit_transition.o -a - obj/Rename_unit_vhdl.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Special_Register_unit_Compilation -------------------| Special_Register_unit -Archive : libSpecial_Register_unit -ar: creating lib/libSpecial_Register_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Special_Register_unit_allocation.o -a - obj/Special_Register_unit.o -a - obj/Special_Register_unit_deallocation.o -a - obj/Special_Register_unit_end_cycle.o -a - obj/Special_Register_unit_genMealy_spr_access.o -a - obj/Special_Register_unit_genMoore.o -a - obj/Special_Register_unit_statistics_allocation.o -a - obj/Special_Register_unit_statistics_deallocation.o -a - obj/Special_Register_unit_transition.o -a - obj/Special_Register_unit_vhdl_body.o -a - obj/Special_Register_unit_vhdl.o -a - obj/Special_Register_unit_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : OOO_Engine_Glue_gCompilati-------------------| OOO_Engine_Glue -Archive : libOOO_Engine_Glue -ar: creating lib/libOOO_Engine_Glue.a -a - obj/OOO_Engine_Glue_allocation.o -a - obj/OOO_Engine_Glue.o -a - obj/OOO_Engine_Glue_deallocation.o -a - obj/OOO_Engine_Glue_end_cycle.o -a - obj/OOO_Engine_Glue_genMealy_insert.o -a - obj/OOO_Engine_Glue_genMealy_insert_valack.o -a - obj/OOO_Engine_Glue_genMealy_rename.o -a - obj/OOO_Engine_Glue_genMealy_retire.o -a - obj/OOO_Engine_Glue_genMealy_retire_valack.o -a - obj/OOO_Engine_Glue_genMealy_spr.o -a - obj/OOO_Engine_Glue_statistics_allocation.o -a - obj/OOO_Engine_Glue_statistics_deallocation.o -a - obj/OOO_Engine_Glue_transition.o -a - obj/OOO_Engine_Glue_vhdl_body.o -a - obj/OOO_Engine_Glue_vhdl.o -a - obj/OOO_Engine_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : OOO_Engine -Compilation : OOO_Engine_allocation -Archive : libOOO_Engine -ar: creating lib/libOOO_Engine.a -a - obj/OOO_Engine_allocation.o -a - obj/OOO_Engine.o -a - obj/OOO_Engine_deallocation.o -a - obj/OOO_Engine_end_cycle.o -a - obj/OOO_Engine_statistics_allocation.o -a - obj/OOO_Engine_statistics_deallocation.o -a - obj/OOO_Engine_transition.o -a - obj/OOO_Engine_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Parameters_msg_erCreate directory : lib -ute_loop_Glue_vhdl_body --------------------| Execute_loop_Glue -oop_Glue_genMealy_spr_Compilation : Execute_loop_Glue_statistics_allocation -Archive : libExecute_loop_Glue -ar: creating lib/libExecute_loop_Glue.a -a - obj/Execute_loop_Glue_allocation.o -a - obj/Execute_loop_Glue.o -a - obj/Execute_loop_Glue_deallocation.o -a - obj/Execute_loop_Glue_end_cycle.o -a - obj/Execute_loop_Glue_genMealy_gpr_write.o -a - obj/Execute_loop_Glue_genMealy_spr_write.o -a - obj/Execute_loop_Glue_statistics_allocation.o -a - obj/Execute_loop_Glue_statistics_deallocation.o -a - obj/Execute_loop_Glue_transition.o -a - obj/Execute_loop_Glue_vhdl_body.o -a - obj/Execute_loop_Glue_vhdl.o -a - obj/Execute_loop_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Queue_Control -nb_eCreate directory : lib --------------------| Queue_Control -Archive : libQueue_Control -ar: creating lib/libQueue_Control.a -a - obj/Queue_Control_clear.o -a - obj/Queue_Control.o -a - obj/Queue_Control_flags.o -a - obj/Queue_Control_nb_elt.o -a - obj/Queue_Control_operator.o -a - obj/Queue_Control_pop.o -a - obj/Queue_Control_push.o -Create directory : obj -Compilation : Queue_genMoore - - -declarCompilation : Queu-------------------| Queue -Archive : libQueue -ar: creating lib/libQueue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Queue_allocation.o -a - obj/Queue.o -a - obj/Queue_deallocation.o -a - obj/Queue_end_cycle.o -a - obj/Queue_genMoore.o -a - obj/Queue_statistics_declaration.o -a - obj/Queue_transition.o -a - obj/Queue_vhdl_body.o -a - obj/Queue_vhdl.o -a - obj/Queue_vhdl_declaration.o -Create directory : obj -Compilation : Read_queue_transCompiC-------------------| Read_queue -src/Read_queue_transition.cpp: In member function 'void morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Read_queue::transition()': -src/Read_queue_transition.cpp:49: attention : format '%d' expects type 'int', but argument 3 has type 'size_t' -src/Read_queue_transition.cpp:144: attention : format '%d' expects type 'int', but argument 3 has type 'size_t' -Archive : libRead_queue -ar: creating lib/libRead_queue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Read_queue_allocation.o -a - obj/Read_queue.o -a - obj/Read_queue_deallocation.o -a - obj/Read_queue_end_cycle.o -a - obj/Read_queue_genMealy_read_queue_out_gpr.o -a - obj/Read_queue_genMealy_read_queue_out_spr.o -a - obj/Read_queue_genMealy_read_queue_out_val.o -a - obj/Read_queue_genMoore.o -a - obj/Read_queue_statistics_declaration.o -a - obj/Read_queue_transition.o -a - obj/Read_queue_vhdl_body.o -a - obj/Read_queue_vhdl.o -a - obj/Read_queue_vhdl_declaration.o --------------------| Queue_Control --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Parameters_msg_error -nd_cCompiCompilation : Parameters_print -Archive : libReservation_station -ar: creating lib/libReservation_station.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Reservation_station_allocation.o -a - obj/Reservation_station.o -a - obj/Reservation_station_deallocation.o -a - obj/Reservation_station_end_cycle.o -a - obj/Reservation_station_genMoore.o -a - obj/Reservation_station_statistics_declaration.o -a - obj/Reservation_station_transition.o -a - obj/Reservation_station_vhdl_body.o -a - obj/Reservation_station_vhdl.o -a - obj/Reservation_station_vhdl_declaration.o -Create directory : obj -Compilation : Read_unit_deallCompiCompilation : Read_unit_allocation -Archive : libRead_unit -ar: creating lib/libRead_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Read_unit_allocation.o -a - obj/Read_unit.o -a - obj/Read_unit_deallocation.o -a - obj/Read_unit_end_cycle.o -a - obj/Read_unit_statistics_declaration.o -a - obj/Read_unit_transition.o -a - obj/Read_unit_vhdl.o --------------------| Common --------------------| Behavioural --------------------| Instruction --------------------| Operation --------------------| Custom --------------------| Common --------------------| Behavioural -Create directory : obj -Create directory : lib -Compilation : Functionnal_unit_Compi-------------------| Functionnal_unit -Archive : libFunctionnal_unit -ar: creating lib/libFunctionnal_unit.a -a - obj/Functionnal_unit_allocation.o -a - obj/Functionnal_unit.o -a - obj/Functionnal_unit_deallocation.o -a - obj/Functionnal_unit_end_cycle.o -a - obj/Functionnal_unit_genMoore.o -a - obj/Functionnal_unit_statistics_declaration.o -a - obj/Functionnal_unit_transition.o -a - obj/Functionnal_unit_vhdl_body.o -a - obj/Functionnal_unit_vhdl.o -a - obj/Functionnal_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Queue_Control --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Load_store_unit_genMealy_Compilation : Load_store_unit_genMealCompilation : Load_store_unit_function_speculative_load_commit_genMealy_dcache -Archive : libLoad_store_unit -ar: creating lib/libLoad_store_unit.a -a - obj/Load_store_unit_allocation.o -a - obj/Load_store_unit.o -a - obj/Load_store_unit_deallocation.o -a - obj/Load_store_unit_end_cycle.o -a - obj/Load_store_unit_function_speculative_load_commit_genMealy_dcache.o -a - obj/Load_store_unit_function_speculative_load_commit_genMealy_insert.o -a - obj/Load_store_unit_function_speculative_load_commit_genMealy_retire.o -a - obj/Load_store_unit_function_speculative_load_commit_genMoore.o -a - obj/Load_store_unit_function_speculative_load_commit_transition.o -a - obj/Load_store_unit_genMealy_dcache.o -a - obj/Load_store_unit_genMealy_insert.o -a - obj/Load_store_unit_genMealy_retire.o -a - obj/Load_store_unit_genMoore.o -a - obj/Load_store_unit_statistics_declaration.o -a - obj/Load_store_unit_transition.o -a - obj/Load_store_unit_vhdl_body.o -a - obj/Load_store_unit_vhdl.o -a - obj/Load_store_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Write_queue_genMoCreate directory Compilation : Parameters_print -Archive : libWrite_queue -ar: creating lib/libWrite_queue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Write_queue_allocation.o -a - obj/Write_queue.o -a - obj/Write_queue_deallocation.o -a - obj/Write_queue_end_cycle.o -a - obj/Write_queue_genMoore.o -a - obj/Write_queue_statistics_declaration.o -a - obj/Write_queue_transition.o -a - obj/Write_queue_vhdl_body.o -a - obj/Write_queue_vhdl.o -a - obj/Write_queue_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Execute_queue_allocation -Compilation : Execute_queue_vhdCompila-------------------| Execute_queue -CompilCompilation : Parameters -Archive : libExecute_queue -ar: creating lib/libExecute_queue.a -a - obj/Execute_queue_allocation.o -a - obj/Execute_queue.o -a - obj/Execute_queue_deallocation.o -a - obj/Execute_queue_end_cycle.o -a - obj/Execute_queue_genMoore.o -a - obj/Execute_queue_statistics_declaration.o -a - obj/Execute_queue_transition.o -a - obj/Execute_queue_vhdl_body.o -a - obj/Execute_queue_vhdl.o -a - obj/Execute_queue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Write_unit_deallC-------------------| Write_unit -Archive : libWrite_unit -ar: creating lib/libWrite_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Write_unit_allocation.o -a - obj/Write_unit.o -a - obj/Write_unit_deallocation.o -a - obj/Write_unit_end_cycle.o -a - obj/Write_unit_statistics_declaration.o -a - obj/Write_unit_transition.o -a - obj/Write_unit_vhdl.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : RegisterFile_Monolithic_statiCompilation Compilation : RegisterFile_Monolithic_vhdl_body -Archive : libRegisterFile_Monolithic -ar: creating lib/libRegisterFile_Monolithic.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/RegisterFile_Monolithic_allocation.o -a - obj/RegisterFile_Monolithic.o -a - obj/RegisterFile_Monolithic_deallocation.o -a - obj/RegisterFile_Monolithic_end_cycle.o -a - obj/RegisterFile_Monolithic_genMealy_read.o -a - obj/RegisterFile_Monolithic_statistics_declaration.o -a - obj/RegisterFile_Monolithic_transition.o -a - obj/RegisterFile_Monolithic_vhdl_body.o -a - obj/RegisterFile_Monolithic_vhdl.o -a - obj/RegisterFile_Monolithic_vhdl_declaration.o --------------------| Common --------------------| Behavioural --------------------| Common --------------------| Behavioural --------------------| RegisterFile_Monolithic --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Select_Priority_Fixed_transCompiCompilation : Select_Priority_Fixed_genMeaCompilation : Select_Priority_Fixed_end_cycle -Compilation : Select_Priority_Fixed_deallocation -Compilation : Parameters -Archive : libSelect_Priority_Fixed -ar: creating lib/libSelect_Priority_Fixed.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Select_Priority_Fixed_allocation.o -a - obj/Select_Priority_Fixed.o -a - obj/Select_Priority_Fixed_deallocation.o -a - obj/Select_Priority_Fixed_end_cycle.o -a - obj/Select_Priority_Fixed_genMealy_entity.o -a - obj/Select_Priority_Fixed_statistics_declaration.o -a - obj/Select_Priority_Fixed_transition.o -a - obj/Select_Priority_Fixed_vhdl_body.o -a - obj/Select_Priority_Fixed_vhdl.o -a - obj/Select_Priority_Fixed_vhdl_declaration.o -Create directory : obj -Compilation : Para-------------------| RegisterFile_Multi_Banked -Archive : libRegisterFile_Multi_Banked -ar: creating lib/libRegisterFile_Multi_Banked.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/RegisterFile_Multi_Banked_address_xxx.o -a - obj/RegisterFile_Multi_Banked_allocation.o -a - obj/RegisterFile_Multi_Banked.o -a - obj/RegisterFile_Multi_Banked_deallocation.o -a - obj/RegisterFile_Multi_Banked_end_cycle.o -a - obj/RegisterFile_Multi_Banked_full_crossbar_genMealy_read.o -a - obj/RegisterFile_Multi_Banked_full_crossbar_genMealy_write.o -a - obj/RegisterFile_Multi_Banked_full_crossbar_transition.o -a - obj/RegisterFile_Multi_Banked_genMealy_read.o -a - obj/RegisterFile_Multi_Banked_genMealy_write.o -a - obj/RegisterFile_Multi_Banked_partial_crossbar_genMealy_read.o -a - obj/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.o -a - obj/RegisterFile_Multi_Banked_partial_crossbar_transition.o -a - obj/RegisterFile_Multi_Banked_statistics_declaration.o -a - obj/RegisterFile_Multi_Banked_transition.o -a - obj/RegisterFile_Multi_Banked_vhdl_body.o -a - obj/RegisterFile_Multi_Banked_vhdl.o -a - obj/RegisterFile_Multi_Banked_vhdl_declaration.o -Create directory : obj -Compilation : RegisterFile -g_error -tion -Create directory : lib -Compilation : Parameters --------------------| RegisterFile -Archive : libRegisterFile -ar: creating lib/libRegisterFile.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/RegisterFile_allocation.o -a - obj/RegisterFile.o -a - obj/RegisterFile_deallocation.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Register_unit_Glue_genMealy_sCompilation -------------------| Register_unit_Glue -Archive : libRegister_unit_Glue -ar: creating lib/libRegister_unit_Glue.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Register_unit_Glue_allocation.o -a - obj/Register_unit_Glue.o -a - obj/Register_unit_Glue_deallocation.o -a - obj/Register_unit_Glue_end_cycle.o -a - obj/Register_unit_Glue_genMealy_gpr_read.o -a - obj/Register_unit_Glue_genMealy_gpr_read_registerfile.o -a - obj/Register_unit_Glue_genMealy_gpr_read_status.o -a - obj/Register_unit_Glue_genMealy_gpr_registerfile.o -a - obj/Register_unit_Glue_genMealy_gpr_write.o -a - obj/Register_unit_Glue_genMealy_gpr_write_status.o -a - obj/Register_unit_Glue_genMealy_insert.o -a - obj/Register_unit_Glue_genMealy_retire.o -a - obj/Register_unit_Glue_genMealy_spr_read.o -a - obj/Register_unit_Glue_genMealy_spr_read_registerfile.o -a - obj/Register_unit_Glue_genMealy_spr_read_status.o -a - obj/Register_unit_Glue_genMealy_spr_registerfile.o -a - obj/Register_unit_Glue_genMealy_spr_write.o -a - obj/Register_unit_Glue_genMealy_spr_write_status.o -a - obj/Register_unit_Glue_statistics_declaration.o -a - obj/Register_unit_Glue_transition.o -a - obj/Register_unit_Glue_vhdl_body.o -a - obj/Register_unit_Glue_vhdl.o -a - obj/Register_unit_Glue_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Parameters_msg_error -ion -Compilation : Parameters -Archive : libRegister_unit -ar: creating lib/libRegister_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Register_unit_allocation.o -a - obj/Register_unit.o -a - obj/Register_unit_deallocation.o -a - obj/Register_unit_end_cycle.o -a - obj/Register_unit_statistics_declaration.o -a - obj/Register_unit_transition.o -a - obj/Register_unit_vhdl_body.o -a - obj/Register_unit_vhdl.o -a - obj/Register_unit_vhdl_declaration.o --------------------| Common --------------------| Behavioural -Create directory : obj -Compilation : Read_unit_to_ExecCompilation : Read_unit_to_Execution_unit_vhdl_declaration --------------------| Read_unit_to_Execution_unit -Archive : libRead_unit_to_Execution_unit -ar: creating lib/libRead_unit_to_Execution_unit.a -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -a - obj/Read_unit_to_Execution_unit_allocation.o -a - obj/Read_unit_to_Execution_unit.o -a - obj/Read_unit_to_Execution_unit_deallocation.o -a - obj/Read_unit_to_Execution_unit_end_cycle.o -a - obj/Read_unit_to_Execution_unit_genMealy.o -a - obj/Read_unit_to_Execution_unit_statistics_declaration.o -a - obj/Read_unit_to_Execution_unit_transition.o -a - obj/Read_unit_to_Execution_unit_vhdl_body.o -a - obj/Read_unit_to_Execution_unit_vhdl.o -a - obj/Read_unit_to_Execution_unit_vhdl_declaration.o --------------------| Behavioural -Create directory : obj -Compilation : Execution_uCompilation : ParametersCompilation : Executio-------------------| Execution_unit_to_Write_unit -Archive : libExecution_unit_to_Write_unit -ar: creating lib/libExecution_unit_to_Write_unit.a -a - obj/Execution_unit_to_Write_unit_allocation.o -a - obj/Execution_unit_to_Write_unit.o -a - obj/Execution_unit_to_Write_unit_deallocation.o -a - obj/Execution_unit_to_Write_unit_end_cycle.o -a - obj/Execution_unit_to_Write_unit_genMealy.o -a - obj/Execution_unit_to_Write_unit_statistics_declaration.o -a - obj/Execution_unit_to_Write_unit_transition.o -a - obj/Execution_unit_to_Write_unit_vhdl_body.o -a - obj/Execution_unit_to_Write_unit_vhdl.o -a - obj/Execution_unit_to_Write_unit_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Create directory : lib -Compilation : Execute_loop_end_CCompilation : Execute_loop_allocation -Archive : libExecute_loop -ar: creating lib/libExecute_loop.a -a - obj/Execute_loop_allocation.o -a - obj/Execute_loop.o -a - obj/Execute_loop_deallocation.o -a - obj/Execute_loop_end_cycle.o -a - obj/Execute_loop_statistics_declaration.o -a - obj/Execute_loop_transition.o -a - obj/Execute_loop_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o --------------------| Common --------------------| Behavioural --------------------| Priority --------------------| Common -Create directory : obj -Compilation : Core_Glue --------------------| Core_Glue -Archive : libCore_Glue -ar: creating lib/libCore_Glue.a -a - obj/Core_Glue_allocation.o -a - obj/Core_Glue.o -a - obj/Core_Glue_deallocation.o -a - obj/Core_Glue_end_cycle.o -a - obj/Core_Glue_genMealy_branch_complete.o -a - obj/Core_Glue_genMealy_commit_event.o -a - obj/Core_Glue_genMealy_execute.o -a - obj/Core_Glue_genMealy_insert.o -a - obj/Core_Glue_genMealy_issue.o -a - obj/Core_Glue_statistics_allocation.o -a - obj/Core_Glue_statistics_deallocation.o -a - obj/Core_Glue_transition.o -a - obj/Core_Glue_vhdl_body.o -a - obj/Core_Glue_vhdl.o -a - obj/Core_Glue_vhdl_declaration.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Create directory : lib -Compilation : Core_deallocation ----Compilation : Core_transition -Compilation : Core_end_cycle -Archive : libCore -ar: creating lib/libCore.a -a - obj/Core_allocation.o -a - obj/Core.o -a - obj/Core_deallocation.o -a - obj/Core_end_cycle.o -a - obj/Core_statistics_allocation.o -a - obj/Core_statistics_deallocation.o -a - obj/Core_transition.o -a - obj/Core_vhdl.o -a - obj/Parameters.o -a - obj/Parameters_msg_error.o -a - obj/Parameters_print.o -Create directory : obj -Compilation : Morpheo_statistics_deallocation -Create directory : lib --------------------| TopLevel -Archive : libMorpheo -ar: creating lib/libMorpheo.a -a - obj/Morpheo_allocation.o -a - obj/Morpheo_configuration.o -a - obj/Morpheo.o -a - obj/Morpheo_deallocation.o -a - obj/Morpheo_end_cycle.o -a - obj/Morpheo_header.o -a - obj/Morpheo_simulation_end.o -a - obj/Morpheo_statistics_allocation.o -a - obj/Morpheo_statistics_deallocation.o -a - obj/Morpheo_transition.o -a - obj/Morpheo_vhdl.o -Compilation : main -Compilation : test -src/test.cpp: In function 'void test(std::string, std::string, std::string, std::string, morpheo::behavioural::custom::custom_information_t (*)())': -src/test.cpp:45: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:46: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:47: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:48: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:49: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:50: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:52: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:53: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:54: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:55: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:56: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:57: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:59: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:60: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:61: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:62: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:63: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:64: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:65: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:67: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:68: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:69: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:70: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:71: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:72: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:74: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:85: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:85: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:86: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:86: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:88: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:88: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:90: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:90: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:91: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:91: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:92: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:92: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:94: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:94: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:95: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:95: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:97: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:97: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:99: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:99: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:100: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:100: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:101: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:101: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:103: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:103: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:104: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:104: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:106: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:106: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:108: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:108: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:109: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:109: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:110: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:110: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:111: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:111: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:113: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:113: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:114: erreur: cast from 'sc_core::sc_out*' to 'uint32_t' loses precision -src/test.cpp:114: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:116: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:116: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:118: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:118: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:119: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:119: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:120: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:120: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -src/test.cpp:122: erreur: cast from 'sc_core::sc_in*' to 'uint32_t' loses precision -src/test.cpp:122: erreur: cast from 'sc_core::sc_signal*' to 'uint32_t' loses precision -distcc[16160] ERROR: compile src/test.cpp on fox/8,lzo failed -make[2]: *** [obj/test.o] Erreur 1 -make[1]: *** [all_selftest] Erreur 2 -make: *** [all] Erreur 2 -Command exited with non-zero status 2 -94.15user 117.94system 6:41.60elapsed 52%CPU (0avgtext+0avgdata 0maxresident)k -0inputs+0outputs (0major+3715681minor)pagefaults 0swaps Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/include/Morpheo.h (revision 97) @@ -150,6 +150,4 @@ public : ~Morpheo (void); - private : std::string header (void); - private : void configuration (std::string filename_simulator, std::string filename_generator, Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo.cpp (revision 97) @@ -37,7 +37,4 @@ filename_instance, get_custom_information); - - if (usage_is_set(_usage,USE_HEADER)) - std::cout << header(); log_printf(INFO,Morpheo,FUNCTION,_("<%s> : Allocation"),_name.c_str()); Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 96) +++ trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_configuration.cpp (revision 97) @@ -52,4 +52,5 @@ param->_ras_size_queue , param->_upt_size_queue , + param->_ufpt_size_queue , param->_nb_decod_bloc , Index: trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/TopLevel/src/Morpheo_header.cpp (revision 96) +++ (revision ) @@ -1,66 +1,0 @@ -/* - * $Id$ - * - * [ Description ] - * - */ - -#include "TopLevel/include/Morpheo.h" -#include "Behavioural/include/Version.h" - -namespace morpheo { - -#undef FUNCTION -#define FUNCTION "Morpheo::header" - std::string Morpheo::header (void) - { - log_begin(Morpheo,FUNCTION); - - std::string str = ""; - - /* - _ - | | - _ __ ___ ___ _ __ _ __ | |__ ___ ___ - | '_ ` _ \ / _ \| '__| '_ \| '_ \ / _ \/ _ \ - | | | | | | (_) | | | |_) | | | | __/ (_) | - |_| |_| |_|\___/|_| | .__/|_| |_|\___|\___/ - | | - |_| - __ - /\ \ - ___ ___ ___ _ __ _____\ \ \___ __ ___ - /' __` __`\ / __`\/\`'__\/\ '__`\ \ _ `\ /'__`\ / __`\ - /\ \/\ \/\ \/\ \L\ \ \ \/ \ \ \L\ \ \ \ \ \/\ __//\ \L\ \ - \ \_\ \_\ \_\ \____/\ \_\ \ \ ,__/\ \_\ \_\ \____\ \____/ - \/_/\/_/\/_/\/___/ \/_/ \ \ \/ \/_/\/_/\/____/\/___/ - \ \_\ - \/_/ - -*/ - - str += toString(MSG_INFORMATION)+" __ \n"; - str += toString(MSG_INFORMATION)+" /\\ \\ \n"; - str += toString(MSG_INFORMATION)+" ___ ___ ___ _ __ _____\\ \\ \\___ __ ___ \n"; - str += toString(MSG_INFORMATION)+" /' __` __`\\ / __`\\/\\`'__\\/\\ '__`\\ \\ _ `\\ /'__`\\ / __`\\ \n"; - str += toString(MSG_INFORMATION)+" /\\ \\/\\ \\/\\ \\/\\ \\L\\ \\ \\ \\/ \\ \\ \\L\\ \\ \\ \\ \\ \\/\\ __//\\ \\L\\ \\\n"; - str += toString(MSG_INFORMATION)+" \\ \\_\\ \\_\\ \\_\\ \\____/\\ \\_\\ \\ \\ ,__/\\ \\_\\ \\_\\ \\____\\ \\____/\n"; - str += toString(MSG_INFORMATION)+" \\/_/\\/_/\\/_/\\/___/ \\/_/ \\ \\ \\/ \\/_/\\/_/\\/____/\\/___/ \n"; - str += toString(MSG_INFORMATION)+" \\ \\_\\ \n"; - str += toString(MSG_INFORMATION)+" \\/_/ \n"; - str += toString(MSG_INFORMATION)+"\n"; - str += toString(MSG_INFORMATION)+_(" * Multiple ORganization of a Processor with HEterogeneous and Open architecture\n"); - str += toString(MSG_INFORMATION)+_(" * Version : ")+toString(MORPHEO_HEADER)+"\n"; - str += toString(MSG_INFORMATION)+_(" * Last change : ")+toString(MORPHEO_DATE )+"\n"; - str += toString(MSG_INFORMATION)+_(" * E-mail support : mathieu.rosiere@lip6.fr\n" ); - str += toString(MSG_INFORMATION)+_(" * Original author(s) : Mathieu Rosière\n" ); - str += toString(MSG_INFORMATION)+_(" * Contributor(s) : Stéphane Dubuisson - XMLLight\n"); - str += toString(MSG_INFORMATION)+_(" Vincent Moulu - VHDL\n" ); - str += toString(MSG_INFORMATION)+"\n"; - - log_end(Morpheo,FUNCTION); - - return str; - }; - -}; // end namespace morpheo Index: trunk/Makefile.flags =================================================================== --- trunk/Makefile.flags (revision 96) +++ trunk/Makefile.flags (revision 97) @@ -23,5 +23,4 @@ # -DPRINT_COLOR \ -# -DLOG_FILE \ # -DPOSITION \ # -DREGISTER_INIT \ @@ -29,5 +28,4 @@ # Flags : # DEBUG={level} - Print Debug Message -# LOG_FILE - Print Message in a log file # SYSTEMC - To generate a systemc's model # VHDL - To generate a vhdl's models Index: trunk/Platforms/Test/Makefile =================================================================== --- trunk/Platforms/Test/Makefile (revision 96) +++ trunk/Platforms/Test/Makefile (revision 97) @@ -58,4 +58,6 @@ OBJECTS = $(patsubst $(DIR_SRC)/%.cpp,$(DIR_OBJ)/%.o,$(wildcard $(DIR_SRC)/*.cpp)) LOGS = $(patsubst $(DIR_DATA)/%.cfg,$(DIR_LOG)/%.log,$(wildcard $(DIR_DATA)/*.cfg)) +DEBUG_CFG = $(DIR_DATA)/debug.cfg +DEBUG_LOG = $(DIR_LOG)/debug.log EXEC = $(DIR_BIN)/soft.x @@ -106,7 +108,13 @@ run : $(DIR_LOG) all @\ - $(MAKE) $(LOGS); \ + declare logs; \ + if $(TEST) -f "$(DEBUG_CFG)"; then \ + logs="$(DEBUG_LOG)"; \ + else \ + logs="$(LOGS)"; \ + fi; \ + $(MAKE) $$logs; \ declare -i have_test_ko=0; \ - for log in $(LOGS); do \ + for log in $$logs; do \ $(GREP) -q "Test OK" $$log; \ declare -i test_ok=$$?; \