Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/main.cpp	(revision 98)
@@ -18,5 +18,5 @@
   err (_(" * nb_inst_branch_complete                       (uint32_t)\n"));
   err (_(" * size_depth                    [nb_context]	   (uint32_t)\n"));
-  err (_(" * size_address                                  (uint32_t)\n"));
+  err (_(" * size_general_data                             (uint32_t)\n"));
   err (_(" * size_inst_decod               [nb_decod_unit] (uint32_t)\n"));
   err (_(" * size_inst_commit                              (uint32_t)\n"));
@@ -52,5 +52,5 @@
     _size_depth [i] = fromString<uint32_t>(argv[x++]);
 
-  uint32_t   _size_address  = fromString<uint32_t>(argv[x++]);
+  uint32_t   _size_general_data = fromString<uint32_t>(argv[x++]);
 
   uint32_t * _size_inst_decod               = new uint32_t [_nb_decod_unit];
@@ -70,5 +70,5 @@
 	 _nb_inst_branch_complete      ,
 	 _size_depth                   ,
-	 _size_address                 ,
+	 _size_general_data            ,
 	 _size_inst_decod              ,
 	 _size_inst_commit             ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp	(revision 98)
@@ -51,5 +51,5 @@
   ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK               ,"out_BRANCH_EVENT_ACK               ",Tcontrol_t   ,_param->_nb_context);
 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID        ," in_BRANCH_EVENT_CONTEXT_ID        ",Tcontext_t   ,_param->_nb_context);
-//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH             ," in_BRANCH_EVENT_DEPTH             ",Tdepth_t     ,_param->_nb_context);
+  ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH             ," in_BRANCH_EVENT_DEPTH             ",Tdepth_t     ,_param->_nb_context);
 //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION   ," in_BRANCH_EVENT_MISS_PREDICTION   ",Tcontrol_t   ,_param->_nb_context);
   ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC       ," in_BRANCH_EVENT_ADDRESS_SRC       ",Taddress_t   ,_param->_nb_context);
@@ -129,5 +129,6 @@
   INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK               ,_param->_nb_context);
 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID        ,_param->_nb_context);
-//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH             ,_param->_nb_context);
+  if (_param->_have_port_depth)				        
+  INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH             ,_param->_nb_context);
 //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION   ,_param->_nb_context);
   INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC       ,_param->_nb_context);
@@ -217,7 +218,8 @@
   srand(seed);
 
+  const  int32_t percent_transaction_branch_event    = 75;
   const  int32_t percent_transaction_decod_event     = 75;
   const  int32_t percent_transaction_commit_event    = 75;
-  const  int32_t percent_transaction_branch_complete = 75;
+//const  int32_t percent_transaction_branch_complete = 75;
   const  int32_t percent_transaction_event           = 75;
   const  int32_t percent_transaction_spr             = 75;
@@ -239,6 +241,8 @@
 	in_DECOD_EVENT_VAL [i]->write(0);
       in_COMMIT_EVENT_VAL ->write(0);
-      for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
-	in_BRANCH_COMPLETE_VAL [i]->write(0);
+//       for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
+// 	in_BRANCH_COMPLETE_VAL [i]->write(0);
+      for (uint32_t i=0; i<_param->_nb_context; i++)
+	in_BRANCH_EVENT_VAL [i]->write(0);
 
       for (uint32_t i=0; i<_param->_nb_context; i++)
@@ -525,25 +529,45 @@
 	  in_NB_INST_COMMIT_MEM [context]->write(1);
 	  
-	  uint32_t port = rand()%_param->_nb_inst_branch_complete;
-	  
-	  in_BRANCH_COMPLETE_CONTEXT_ID       [port]->write(context);
+// 	  uint32_t port = rand()%_param->_nb_inst_branch_complete;
+	  
+// 	  in_BRANCH_COMPLETE_CONTEXT_ID       [port]->write(context);
+// 	  if (_param->_have_port_depth)
+// 	  in_BRANCH_COMPLETE_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
+// 	  in_BRANCH_COMPLETE_ADDRESS_SRC      [port]->write(0x400);
+// 	  in_BRANCH_COMPLETE_ADDRESS_DEST     [port]->write(0x500);
+// 	  in_BRANCH_COMPLETE_MISS_PREDICTION  [port]->write(1);
+// 	  in_BRANCH_COMPLETE_TAKE             [port]->write(0);
+
+// 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+// 	  do
+// 	    {
+// 	      in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
+	      
+// 	      SC_START(1);
+// 	    }
+// 	  while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
+// 		       out_BRANCH_COMPLETE_ACK [port]->read()));
+// 	  in_BRANCH_COMPLETE_VAL [port]->write(0);
+
+	  uint32_t port = context;
+	  
 	  if (_param->_have_port_depth)
-	  in_BRANCH_COMPLETE_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
-	  in_BRANCH_COMPLETE_ADDRESS_SRC      [port]->write(0x400);
-	  in_BRANCH_COMPLETE_ADDRESS_DEST     [port]->write(0x500);
-	  in_BRANCH_COMPLETE_MISS_PREDICTION  [port]->write(1);
-	  in_BRANCH_COMPLETE_TAKE             [port]->write(0);
-
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  do
-	    {
-	      in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
-	      
-	      SC_START(1);
-	    }
-	  while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
-		       out_BRANCH_COMPLETE_ACK [port]->read()));
-	  in_BRANCH_COMPLETE_VAL [port]->write(0);
+	  in_BRANCH_EVENT_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
+	  in_BRANCH_EVENT_ADDRESS_SRC      [port]->write(0x400);
+	  in_BRANCH_EVENT_ADDRESS_DEST     [port]->write(0x500);
+	  in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0);
+
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+	  do
+	    {
+	      in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
+	      
+	      SC_START(1);
+	    }
+	  while (not ( in_BRANCH_EVENT_VAL [port]->read() and
+		       out_BRANCH_EVENT_ACK [port]->read()));
+	  in_BRANCH_EVENT_VAL [port]->write(0);
 	  
 	  LABEL("miss (wait end)");
@@ -595,25 +619,44 @@
 	  in_NB_INST_COMMIT_MEM [context]->write(1);
 	  
-	  uint32_t port = rand()%_param->_nb_inst_branch_complete;
-	  
-	  in_BRANCH_COMPLETE_CONTEXT_ID       [port]->write(context);
-	  if (_param->_have_port_depth)
-	  in_BRANCH_COMPLETE_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
-	  in_BRANCH_COMPLETE_ADDRESS_SRC      [port]->write(0x600);
-	  in_BRANCH_COMPLETE_ADDRESS_DEST     [port]->write(0x700);
-	  in_BRANCH_COMPLETE_MISS_PREDICTION  [port]->write(1);
-	  in_BRANCH_COMPLETE_TAKE             [port]->write(1);
-
-	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
-	  
-	  do
-	    {
-	      in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
-	      
-	      SC_START(1);
-	    }
-	  while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
-		       out_BRANCH_COMPLETE_ACK [port]->read()));
-	  in_BRANCH_COMPLETE_VAL [port]->write(0);
+// 	  uint32_t port = rand()%_param->_nb_inst_branch_complete;
+	  
+// 	  in_BRANCH_COMPLETE_CONTEXT_ID       [port]->write(context);
+// 	  if (_param->_have_port_depth)
+// 	  in_BRANCH_COMPLETE_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
+// 	  in_BRANCH_COMPLETE_ADDRESS_SRC      [port]->write(0x600);
+// 	  in_BRANCH_COMPLETE_ADDRESS_DEST     [port]->write(0x700);
+// 	  in_BRANCH_COMPLETE_MISS_PREDICTION  [port]->write(1);
+// 	  in_BRANCH_COMPLETE_TAKE             [port]->write(1);
+
+// 	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+// 	  do
+// 	    {
+// 	      in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
+	      
+// 	      SC_START(1);
+// 	    }
+// 	  while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
+// 		       out_BRANCH_COMPLETE_ACK [port]->read()));
+// 	  in_BRANCH_COMPLETE_VAL [port]->write(0);
+
+	  uint32_t port = context;
+	  
+	  in_BRANCH_EVENT_DEPTH            [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
+	  in_BRANCH_EVENT_ADDRESS_SRC      [port]->write(0x600);
+	  in_BRANCH_EVENT_ADDRESS_DEST     [port]->write(0x700);
+	  in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1);
+
+	  TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
+	  
+	  do
+	    {
+	      in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
+	      
+	      SC_START(1);
+	    }
+	  while (not ( in_BRANCH_EVENT_VAL [port]->read() and
+		       out_BRANCH_EVENT_ACK [port]->read()));
+	  in_BRANCH_EVENT_VAL [port]->write(0);
 	  
 	  LABEL("miss (wait end)");
@@ -1238,5 +1281,5 @@
   DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK               ,_param->_nb_context);
 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID        ,_param->_nb_context);
-//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH             ,_param->_nb_context);
+  DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH             ,_param->_nb_context);
 //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION   ,_param->_nb_context);
   DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC       ,_param->_nb_context);
