Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp	(revision 98)
@@ -35,5 +35,5 @@
 //   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
 //   _usage = usage_unset(_usage,USE_POSITION             );
-   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
 //   _usage = usage_unset(_usage,USE_INFORMATION          );
 
@@ -139,5 +139,5 @@
   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH          ,"out_BRANCH_COMPLETE_DEPTH          ",Tdepth_t          ,_param->_nb_inst_branch_complete);
   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS        ,"out_BRANCH_COMPLETE_ADDRESS        ",Taddress_t        ,_param->_nb_inst_branch_complete);
-  ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG           ,"out_BRANCH_COMPLETE_FLAG           ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
+  ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE    ,"out_BRANCH_COMPLETE_NO_SEQUENCE    ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
   ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t        ,_param->_nb_inst_branch_complete);
   ALLOC_SC_SIGNAL (out_UPDATE_VAL                      ,"out_UPDATE_VAL                      ",Tcontrol_t        );
@@ -282,5 +282,5 @@
   INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_DEPTH          ,_param->_nb_inst_branch_complete);
   INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_ADDRESS        ,_param->_nb_inst_branch_complete);
-  INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_FLAG           ,_param->_nb_inst_branch_complete);
+  INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete);
   INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
   INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL                      );
@@ -678,5 +678,5 @@
   DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH          ,_param->_nb_inst_branch_complete);
   DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS        ,_param->_nb_inst_branch_complete);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG           ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete);
   DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
   DELETE_SC_SIGNAL (out_UPDATE_VAL                      );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h	(revision 98)
@@ -57,5 +57,6 @@
   public    : counter_t                      * _stat_nb_inst_commit;
   public    : counter_t                      * _stat_nb_inst_commit_conflit_access;
-  public    : counter_t                     ** _stat_nb_inst_retire;
+  public    : counter_t                     ** _stat_nb_inst_retire_ok;
+  public    : counter_t                     ** _stat_nb_inst_retire_ko;
   public    : counter_t                     ** _stat_bank_nb_inst;// [nb_bank]
 #endif
@@ -161,5 +162,6 @@
   public    : SC_OUT(Tdepth_t           )  ** out_BRANCH_COMPLETE_DEPTH            ;//[nb_inst_branch_complete]
   public    : SC_OUT(Taddress_t         )  ** out_BRANCH_COMPLETE_ADDRESS          ;//[nb_inst_branch_complete]
-  public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_FLAG             ;//[nb_inst_branch_complete]
+//public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_FLAG             ;//[nb_inst_branch_complete]
+  public    : SC_OUT(Tcontrol_t         )  ** out_BRANCH_COMPLETE_NO_SEQUENCE      ;//[nb_inst_branch_complete]
   public    : SC_IN (Tcontrol_t         )  **  in_BRANCH_COMPLETE_MISS_PREDICTION  ;//[nb_inst_branch_complete]
 										   
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp	(revision 98)
@@ -167,5 +167,6 @@
       ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_DEPTH          ,"depth"          ,Tdepth_t           ,_param->_size_depth    );
       ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS        ,"address"        ,Taddress_t         ,_param->_size_instruction_address);
-      ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG           ,"flag"           ,Tcontrol_t         ,1);
+//    ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG           ,"flag"           ,Tcontrol_t         ,1);
+      ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE    ,"no_sequence"    ,Tcontrol_t         ,1);
       ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t         ,1);
     }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp	(revision 98)
@@ -108,12 +108,13 @@
         DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr);
 
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL            ,_param->_nb_inst_branch_complete,1                         );
-        DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK            ,_param->_nb_inst_branch_complete,1                         );
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL            ,_param->_nb_inst_branch_complete,1);
+        DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK            ,_param->_nb_inst_branch_complete,1);
         DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID     ,_param->_nb_inst_branch_complete,_param->_size_context_id  );
         DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID   ,_param->_nb_inst_branch_complete,_param->_size_front_end_id);
         DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH          ,_param->_nb_inst_branch_complete,_param->_size_depth       );
         DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS        ,_param->_nb_inst_branch_complete,_param->_size_instruction_address     );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG           ,_param->_nb_inst_branch_complete,1                         );
-        DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1                         );
+//      DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG           ,_param->_nb_inst_branch_complete,1);
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE    ,_param->_nb_inst_branch_complete,1);
+        DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1);
 
         DELETE_SIGNAL (out_UPDATE_VAL                      ,1                         );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp	(revision 98)
@@ -86,11 +86,12 @@
 		      
 		      if (_param->_have_port_context_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i], entry->context_id           );
+		      PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID   [i], entry->context_id      );
 		      if (_param->_have_port_front_end_id)
-		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id         );
+		      PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id    );
 		      if (_param->_have_port_depth)
-		      PORT_WRITE(out_BRANCH_COMPLETE_DEPTH        [i], entry->depth                );
-		      PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS      [i], entry->data_commit          );
-		      PORT_WRITE(out_BRANCH_COMPLETE_FLAG         [i], (entry->flags&FLAG_F)!=0    );
+		      PORT_WRITE(out_BRANCH_COMPLETE_DEPTH        [i], entry->depth           );
+		      PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS      [i], entry->data_commit     );
+// 		      PORT_WRITE(out_BRANCH_COMPLETE_FLAG         [i],(entry->flags&FLAG_F)!=0);
+		      PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE  [i], entry->no_sequence     );
 		      
 		      break;
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp	(revision 98)
@@ -28,35 +28,33 @@
 
     _stat_nb_inst_insert                = new counter_t * [_param->_nb_rename_unit];
-    _stat_nb_inst_retire                = new counter_t * [_param->_nb_rename_unit];
+    _stat_nb_inst_retire_ok             = new counter_t * [_param->_nb_rename_unit];
+    _stat_nb_inst_retire_ko             = new counter_t * [_param->_nb_rename_unit];
     _stat_bank_nb_inst                  = new counter_t * [_param->_nb_bank];
     
     {
-      std::string sum_nb_inst_insert = "";
-      std::string sum_nb_inst_retire = "";
+      std::string sum_nb_inst_insert    = "0";
+      std::string sum_nb_inst_retire_ok = "0";
+      std::string sum_nb_inst_retire_ko = "0";
 
       for (uint32_t i=0; i<_param->_nb_rename_unit; i++)
 	{
-	  _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_"+toString(i));
-	  _stat_nb_inst_retire [i] = _stat->create_variable("nb_inst_retire_"+toString(i));
+	  _stat_nb_inst_insert    [i] = _stat->create_variable("nb_inst_insert_"   +toString(i));
+	  _stat_nb_inst_retire_ok [i] = _stat->create_variable("nb_inst_retire_ok_"+toString(i));
+	  _stat_nb_inst_retire_ko [i] = _stat->create_variable("nb_inst_retire_ko_"+toString(i));
 	  
 	  _stat->create_expr_average_by_cycle("average_use_interface_insert_"+toString(i), "nb_inst_insert_"+toString(i), "", toString(_("Average instruction by cycle on insert interface (rename_unit %d)"),i));
-	  _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "nb_inst_retire_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i));
+	  _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "+ nb_inst_retire_ok_"+toString(i)+" nb_inst_retire_ko_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i));
 	  _stat->create_expr_percent         ("percent_use_interface_insert_"+toString(i) , "average_use_interface_insert_"+toString(i), toString(_param->_nb_inst_insert [i]), toString(_("Percent usage of insert interface (rename_unit %d)"),i));
 	  _stat->create_expr_percent         ("percent_use_interface_retire_"+toString(i) , "average_use_interface_retire_"+toString(i), toString(_param->_nb_inst_retire [i]), toString(_("Percent usage of retire interface (rename_unit %d)"),i));
 
-	  if (i == 0)
-            {
-              sum_nb_inst_insert = "nb_inst_insert_"+toString(i);
-              sum_nb_inst_retire = "nb_inst_retire_"+toString(i);
-            }
-          else
-            {
-              sum_nb_inst_insert = "+ nb_inst_insert_"+toString(i) + " " +sum_nb_inst_insert;
-              sum_nb_inst_retire = "+ nb_inst_retire_"+toString(i) + " " +sum_nb_inst_retire;
-            }
+          sum_nb_inst_insert    = "+ nb_inst_insert_"+   toString(i) + " " +sum_nb_inst_insert;
+          sum_nb_inst_retire_ok = "+ nb_inst_retire_ok_"+toString(i) + " " +sum_nb_inst_retire_ok;
+          sum_nb_inst_retire_ko = "+ nb_inst_retire_ko_"+toString(i) + " " +sum_nb_inst_retire_ko;
 	}
 
-      _stat->create_expr_average_by_cycle("average_inst_insert", sum_nb_inst_insert, "", _("Average instruction insert by cycle"));
-      _stat->create_expr_average_by_cycle("average_inst_retire", sum_nb_inst_retire, "", _("Average instruction retire by cycle"));
+      _stat->create_expr_average_by_cycle("average_inst_insert"   , sum_nb_inst_insert   , "", _("Average instruction insert by cycle"));
+      _stat->create_expr_average_by_cycle("average_inst_retire_ok", sum_nb_inst_retire_ok, "", _("Average instruction retire ok by cycle (IPC)"));
+      _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle"));
+      _stat->create_expr_average_by_cycle("average_inst_retire"   , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle"));
     }
 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp	(revision 98)
@@ -28,5 +28,6 @@
 
     delete [] _stat_nb_inst_insert;
-    delete [] _stat_nb_inst_retire;
+    delete [] _stat_nb_inst_retire_ok;
+    delete [] _stat_nb_inst_retire_ko;
     delete [] _stat_bank_nb_inst;
     
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp	(revision 98)
@@ -281,9 +281,4 @@
 	      log_printf(TRACE,Commit_unit,FUNCTION,"  * RETIRE            [%d][%d]",x,y);
 
-#ifdef STATISTICS
-              if (usage_is_set(_usage,USE_STATISTICS))
-                (*_stat_nb_inst_retire [x]) ++;
-#endif
-
 #ifdef DEBUG_TEST
 	      if (not PORT_READ(in_RETIRE_ACK [x][y]))
@@ -291,7 +286,17 @@
 #endif
 
-
 	      entry_t *  entry        =  _rob [i].front();
-	      
+#ifdef STATISTICS
+              if (usage_is_set(_usage,USE_STATISTICS))
+                {
+                  rob_state_t state = entry->state;
+                  
+                  if (state == ROB_END_OK)
+                    (*_stat_nb_inst_retire_ok [x]) ++;
+                  else
+                    (*_stat_nb_inst_retire_ko [x]) ++;
+                }
+#endif
+
 	      Tcontext_t front_end_id = entry->front_end_id;
 	      Tcontext_t context_id   = entry->context_id  ;
@@ -478,5 +483,5 @@
 	     it++)
 	  {
-            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
+            log_printf(TRACE,Commit_unit,FUNCTION,"      [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d",
                        x,
                        (*it)->front_end_id            ,
@@ -487,4 +492,5 @@
                        (*it)->operation               ,
                        (*it)->address                 ,
+                       (*it)->address << 2            ,
                        (*it)->is_delay_slot           ,
                        (*it)->use_store_queue         ,
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp	(revision 98)
@@ -21,4 +21,5 @@
   {
     log_begin(Reexecute_unit,FUNCTION);
+    log_function(Reexecute_unit,FUNCTION,_name.c_str());
 
     // Initialisation
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp	(revision 98)
@@ -22,4 +22,5 @@
   {
     log_begin(Reexecute_unit,FUNCTION);
+    log_function(Reexecute_unit,FUNCTION,_name.c_str());
 
     // ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp	(revision 98)
@@ -22,4 +22,5 @@
   {
     log_begin(Reexecute_unit,FUNCTION);
+    log_function(Reexecute_unit,FUNCTION,_name.c_str());
 
     // ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp	(revision 98)
@@ -22,4 +22,5 @@
   {
     log_begin(Reexecute_unit,FUNCTION);
+    log_function(Reexecute_unit,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -135,4 +136,43 @@
       }
 
+#if ((DEBUG >= DEBUG_TRACE) and DEBUG_Reexecute_unit)
+    log_printf(TRACE,Reexecute_unit,FUNCTION,"  * Dump Reexecute_queue");
+
+    for (uint32_t i=0; i<_param->_nb_bank; ++i)
+      {
+        uint32_t j=0;
+        for (std::list<entry_t *>::iterator it=_reexecute_queue[i].begin();
+             it!=_reexecute_queue[i].end();
+             ++it)
+          {
+            log_printf(TRACE,Reexecute_unit,FUNCTION,"  [%.4d][%.4d] %.4d %.4d %.4d, %.1d %.1d, %.4d %.4d, %.8x (%.2d %.4d) %.8x, %.1d %.5d, %s",
+                       i,
+                       j,
+                       (*it)->context_id    ,
+                       (*it)->front_end_id  ,
+                       (*it)->packet_id     ,
+                       (*it)->spr_wen       ,
+                       (*it)->reexecute     ,
+                       (*it)->type          ,
+                       (*it)->operation     ,
+                       (*it)->address       ,
+                      ((*it)->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group,
+                      ((*it)->address                                ) & _param->_mask_spr_num_reg  ,
+                       (*it)->data          ,
+                       (*it)->write_rd      ,
+                       (*it)->num_reg_rd    ,
+                       toString((*it)->state).c_str());
+
+            ++j;
+          }
+      }
+//     // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~    
+//   private   : std::list<entry_t *>          * _reexecute_queue                         ;//[nb_bank]
+  typedef struct 
+  {
+  } entry_t;
+
+#endif
+
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     end_cycle ();
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp	(revision 98)
@@ -132,8 +132,8 @@
 
           for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k)
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * GPR[%.2d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]);
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]);
 
           for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k)
-            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * SPR[%.2d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]);
+            log_printf(TRACE,Register_Address_Translation_unit,FUNCTION,"      * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]);
         }
 #endif
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp	(revision 98)
@@ -50,15 +50,17 @@
   sc_signal<Tcontrol_t> *  in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
 
-  ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL    ," in_INSERT_RENAME_VAL    ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK    ,"out_INSERT_RENAME_ACK    ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL    ,"out_INSERT_INSERT_VAL    ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK    ," in_INSERT_INSERT_ACK    ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,"out_INSERT_RAT_INSERT_VAL",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK," in_INSERT_RAT_RENAME_ACK",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK," in_INSERT_RAT_INSERT_ACK",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert);
-  ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL        ," in_INSERT_RENAME_VAL        ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK        ,"out_INSERT_RENAME_ACK        ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL        ,"out_INSERT_INSERT_VAL        ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK        ," in_INSERT_INSERT_ACK        ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL    ,"out_INSERT_RAT_INSERT_VAL    ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK    ," in_INSERT_RAT_RENAME_ACK    ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK    ," in_INSERT_RAT_INSERT_ACK    ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL     ,"out_INSERT_FREE_LIST_VAL     ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK     ," in_INSERT_FREE_LIST_ACK     ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,"out_INSERT_FREE_LIST_GPR_VAL ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,"out_INSERT_FREE_LIST_SPR_VAL ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL     ,"out_INSERT_STAT_LIST_VAL     ",Tcontrol_t,_param->_nb_inst_insert);
+  ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK     ," in_INSERT_STAT_LIST_ACK     ",Tcontrol_t,_param->_nb_inst_insert);
 
   ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA           ," in_INSERT_DEPENDENCY_CHECKING_READ_RA           ",Tcontrol_t        ,_param->_nb_inst_insert);
@@ -126,15 +128,17 @@
   (*(_Register_translation_unit_Glue->in_NRESET))       (*(in_NRESET));
 
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL    ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK    ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL    ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK    ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert);
-  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL        ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK        ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL        ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK        ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL    ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK    ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK    ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL     ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK     ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL     ,_param->_nb_inst_insert);
+  INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK     ,_param->_nb_inst_insert);
   
   INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RA           ,_param->_nb_inst_insert);
@@ -243,29 +247,32 @@
       for (uint32_t i=0; i<_param->_nb_inst_insert;i++)
 	{
-	  TEST(Tcontrol_t,out_INSERT_RENAME_ACK     [i]->read(),(in_INSERT_INSERT_ACK     [i]->read() and
-								 in_INSERT_RAT_RENAME_ACK [i]->read() and
-								 in_INSERT_RAT_INSERT_ACK [i]->read() and
-								 in_INSERT_FREE_LIST_ACK  [i]->read() and
-								 in_INSERT_STAT_LIST_ACK  [i]->read() ));
-	  TEST(Tcontrol_t,out_INSERT_INSERT_VAL     [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
-								 in_INSERT_RAT_RENAME_ACK [i]->read() and
-								 in_INSERT_RAT_INSERT_ACK [i]->read() and
-								 in_INSERT_FREE_LIST_ACK  [i]->read() and
-								 in_INSERT_STAT_LIST_ACK  [i]->read() ));
-	  TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
-								 in_INSERT_INSERT_ACK     [i]->read() and
-								 in_INSERT_RAT_RENAME_ACK [i]->read() and
-								 in_INSERT_FREE_LIST_ACK  [i]->read() and
-								 in_INSERT_STAT_LIST_ACK  [i]->read() ));
-	  TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL  [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
-								 in_INSERT_INSERT_ACK     [i]->read() and
-								 in_INSERT_RAT_RENAME_ACK [i]->read() and
-								 in_INSERT_RAT_INSERT_ACK [i]->read() and
-								 in_INSERT_STAT_LIST_ACK  [i]->read() ));
-	  TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL  [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
-								 in_INSERT_INSERT_ACK     [i]->read() and
-								 in_INSERT_RAT_RENAME_ACK [i]->read() and
-								 in_INSERT_RAT_INSERT_ACK [i]->read() and
-								 in_INSERT_FREE_LIST_ACK  [i]->read() ));
+	  TEST(Tcontrol_t,out_INSERT_RENAME_ACK         [i]->read(),(in_INSERT_INSERT_ACK     [i]->read() and
+                                                                     in_INSERT_RAT_RENAME_ACK [i]->read() and
+                                                                     in_INSERT_RAT_INSERT_ACK [i]->read() and
+                                                                     in_INSERT_FREE_LIST_ACK  [i]->read() and
+                                                                     in_INSERT_STAT_LIST_ACK  [i]->read() ));
+	  TEST(Tcontrol_t,out_INSERT_INSERT_VAL         [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
+                                                                     in_INSERT_RAT_RENAME_ACK [i]->read() and
+                                                                     in_INSERT_RAT_INSERT_ACK [i]->read() and
+                                                                     in_INSERT_FREE_LIST_ACK  [i]->read() and
+                                                                     in_INSERT_STAT_LIST_ACK  [i]->read() ));
+	  TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL     [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
+                                                                     in_INSERT_INSERT_ACK     [i]->read() and
+                                                                     in_INSERT_RAT_RENAME_ACK [i]->read() and
+                                                                     in_INSERT_FREE_LIST_ACK  [i]->read() and
+                                                                     in_INSERT_STAT_LIST_ACK  [i]->read() ));
+	  TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL      [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
+                                                                     in_INSERT_INSERT_ACK     [i]->read() and
+                                                                     in_INSERT_RAT_RENAME_ACK [i]->read() and
+                                                                     in_INSERT_RAT_INSERT_ACK [i]->read() and
+                                                                     in_INSERT_STAT_LIST_ACK  [i]->read() ));
+	  TEST(Tcontrol_t,out_INSERT_FREE_LIST_GPR_VAL  [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD[i]->read() and
+                                                                     (in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG[i]->read()!=0)));
+	  TEST(Tcontrol_t,out_INSERT_FREE_LIST_SPR_VAL  [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE[i]->read()));
+	  TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL      [i]->read(),(in_INSERT_RENAME_VAL     [i]->read() and
+                                                                     in_INSERT_INSERT_ACK     [i]->read() and
+                                                                     in_INSERT_RAT_RENAME_ACK [i]->read() and
+                                                                     in_INSERT_RAT_INSERT_ACK [i]->read() and
+                                                                     in_INSERT_FREE_LIST_ACK  [i]->read() ));
 	}
       
@@ -295,15 +302,17 @@
   delete in_NRESET;
 
-  DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL    ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK    ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL    ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK    ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert);
-  DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK        ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK    ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL     ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK     ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL     ,_param->_nb_inst_insert);
+  DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK     ,_param->_nb_inst_insert);
   
   DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA           ,_param->_nb_inst_insert);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h	(revision 98)
@@ -73,4 +73,6 @@
   public    : SC_OUT(Tcontrol_t)           ** out_INSERT_FREE_LIST_VAL                         ;//[nb_inst_insert]
   public    : SC_IN (Tcontrol_t)           **  in_INSERT_FREE_LIST_ACK                         ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t)           ** out_INSERT_FREE_LIST_GPR_VAL                     ;//[nb_inst_insert]
+  public    : SC_OUT(Tcontrol_t)           ** out_INSERT_FREE_LIST_SPR_VAL                     ;//[nb_inst_insert]
   public    : SC_OUT(Tcontrol_t)           ** out_INSERT_STAT_LIST_VAL                         ;//[nb_inst_insert]
   public    : SC_IN (Tcontrol_t)           **  in_INSERT_STAT_LIST_ACK                         ;//[nb_inst_insert]
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp	(revision 98)
@@ -61,15 +61,17 @@
       ALLOC1_INTERFACE("insert",OUT, EAST, "insert's interface", _param->_nb_inst_insert);
       
-      ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL    ,"rename_val"    ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK    ,"rename_ack"    ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL    ,"insert_val"    ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK    ,"insert_ack"    ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL,"rat_insert_val",Tcontrol_t,1);
-      ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK,"rat_rename_ack",Tcontrol_t,1);
-      ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK,"rat_insert_ack",Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL ,"free_list_val" ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK ,"free_list_ack" ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1);
-      ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL        ,"rename_val"        ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK        ,"rename_ack"        ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL        ,"insert_val"        ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK        ,"insert_ack"        ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL    ,"rat_insert_val"    ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK    ,"rat_rename_ack"    ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK    ,"rat_insert_ack"    ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL     ,"free_list_val"     ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK     ,"free_list_ack"     ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_GPR_VAL ,"free_list_gpr_val" ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_SPR_VAL ,"free_list_spr_val" ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL     ,"stat_list_val"     ,Tcontrol_t,1);
+      ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK     ,"stat_list_ack"     ,Tcontrol_t,1);
 
       ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RA           ,"DEPENDENCY_CHECKING_READ_RA"           ,Tcontrol_t        ,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp	(revision 98)
@@ -30,15 +30,17 @@
 	delete     in_NRESET;
 
-	DELETE1_SIGNAL( in_INSERT_RENAME_VAL    ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL(out_INSERT_RENAME_ACK    ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL(out_INSERT_INSERT_VAL    ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL( in_INSERT_INSERT_ACK    ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1);
-	DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_RENAME_VAL        ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_RENAME_ACK        ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_INSERT_VAL        ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_INSERT_ACK        ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL    ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK    ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK    ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL     ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK     ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL     ,_param->_nb_inst_insert,1);
+	DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK     ,_param->_nb_inst_insert,1);
 	
 	DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA           ,_param->_nb_inst_insert,1);
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp	(revision 98)
@@ -36,10 +36,13 @@
 	Tcontrol_t         WRITE_RD           = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD           [i]);
 	Tgeneral_address_t NUM_REG_RD_LOG     = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG     [i]);
-	Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]);
-	Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]);
+	Tgeneral_address_t NUM_REG_RD_PHY_OLD = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]):0;
+	Tgeneral_address_t NUM_REG_RD_PHY_NEW = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]):0;
 	Tcontrol_t         WRITE_RE           = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE           [i]);
 	Tspecial_address_t NUM_REG_RE_LOG     = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG     [i]);
 	Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD [i]);
 	Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i]);
+
+	PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL            [i], WRITE_RD and (NUM_REG_RD_LOG!=0));
+	PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL            [i], WRITE_RE          );
 
 	PORT_WRITE(out_INSERT_STAT_LIST_READ_RA            [i], READ_RA           );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp	(revision 98)
@@ -384,9 +384,4 @@
 #endif
 	  
-	  PORT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL"    ,
-		              dest,"in_RENAME_"+toString(i)+"_WRITE_RD");
-	  PORT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL"    ,
-		              dest,"in_RENAME_"+toString(i)+"_WRITE_RE");
-
 	  dest = _name+"_register_translation_unit_glue";
 	  COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_VAL" ,
@@ -394,4 +389,8 @@
 	  COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_ACK" ,
 		                   dest, "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" );
+	  COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL"    ,
+			           dest,"out_INSERT_"+toString(i)+"_FREE_LIST_GPR_VAL");
+	  COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL"    ,
+			           dest,"out_INSERT_"+toString(i)+"_FREE_LIST_SPR_VAL");
 
 	  dest = _name+"_dependency_checking_unit";
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp	(revision 98)
@@ -132,5 +132,5 @@
   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH            ,"out_BRANCH_COMPLETE_DEPTH            ",Tdepth_t          ,_param->_nb_inst_branch_complete);
   ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS          ,"out_BRANCH_COMPLETE_ADDRESS          ",Taddress_t        ,_param->_nb_inst_branch_complete);
-  ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG             ,"out_BRANCH_COMPLETE_FLAG             ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
+  ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE      ,"out_BRANCH_COMPLETE_NO_SEQUENCE      ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
   ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION  ," in_BRANCH_COMPLETE_MISS_PREDICTION  ",Tcontrol_t        ,_param->_nb_inst_branch_complete);
 
@@ -268,15 +268,15 @@
 //   INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_NEW_NUM_REG            ,_param->_sum_inst_retire);
 
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_issue);
-  INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_branch_complete);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_branch_complete);
   if (_param->_have_port_front_end_id)
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_branch_complete);
   if (_param->_have_port_context_id)
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_branch_complete);
   if (_param->_have_port_depth)
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_issue);
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_issue);
-  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FLAG             ,_param->_nb_inst_issue);
-  INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_issue);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_branch_complete);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_branch_complete);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_NO_SEQUENCE      ,_param->_nb_inst_branch_complete);
+  INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_branch_complete);
 
   INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_VAL                 );
@@ -433,23 +433,23 @@
   DELETE1_SC_SIGNAL(out_INSERT_RE_NUM_REG                ,_param->_sum_inst_insert);
   
-//   DELETE1_SC_SIGNAL(out_RETIRE_VAL                       ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL( in_RETIRE_ACK                       ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE                ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG            ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE                ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG            ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE                ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG            ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE                ,_param->_sum_inst_retire);
-//   DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG            ,_param->_sum_inst_retire);
-  
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG             ,_param->_nb_inst_issue);
-  DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_issue);
+//DELETE1_SC_SIGNAL(out_RETIRE_VAL                       ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL( in_RETIRE_ACK                       ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE                ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG            ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE                ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG            ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE                ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG            ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE                ,_param->_sum_inst_retire);
+//DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG            ,_param->_sum_inst_retire);
+  
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE      ,_param->_nb_inst_branch_complete);
+  DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_branch_complete);
   
   DELETE_SC_SIGNAL  (out_COMMIT_EVENT_VAL                 );
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h	(revision 98)
@@ -34,5 +34,5 @@
   public : Tspr_t read  (void  )
     {
-      return x=0;
+      return x;
     };
   public : void   write (Tspr_t x) 
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp	(revision 98)
@@ -148,5 +148,8 @@
 		{
 		  _spr [i][j][k] = new SPR * [NB_REG_GROUP[k]];
-
+                  
+                  for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
+                    _spr [i][j][k][l] = NULL;
+                  
 		  switch (k)
 		    {
@@ -218,6 +221,4 @@
 		    default :
 		      {
-			for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
-			  _spr [i][j][k][l] = NULL;
 		      }
 		    }
@@ -232,7 +233,14 @@
 	for (uint32_t k=0; k<NB_GROUP; k++)
 	  if (_param->_implement_group [i][j][k])
-	    for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
-	      if (_spr [i][j][k][l] == NULL)
-		_spr_access_mode [i][j]->invalid_register (k,l);
+            {
+              for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
+                if (_spr [i][j][k][l] == NULL)
+                  _spr_access_mode [i][j]->invalid_register (k,l);
+            }
+          else
+            {
+              for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
+                _spr_access_mode [i][j]->invalid_register (k,l);
+            }
 
 #ifdef POSITION
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp	(revision 98)
@@ -77,8 +77,8 @@
 	    for (uint32_t k=0; k<NB_GROUP; k++)
 	      {
-		if (_param->_implement_group [i][j][k])
+                if (_spr [i][j][k] != NULL)
 		  {
 		    for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
-		      if (_spr [i][j][k] != NULL)
+		      if (_spr [i][j][k][l] != NULL)
 			delete _spr [i][j][k][l];
 		    delete [] _spr [i][j][k];
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMealy_spr_access.cpp	(revision 98)
@@ -22,5 +22,5 @@
   {
     log_begin(Special_Register_unit,FUNCTION);
-
+    log_function(Special_Register_unit,FUNCTION,_name.c_str());
 
     // ===================================================================
@@ -28,6 +28,9 @@
     // ===================================================================
     for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
-//       if (PORT_READ(in_SPR_ACCESS_VAL [i]) and not PORT_READ(in_SPR_ACCESS_WEN [i]))
+      // not necessery if have not read enable
+      if (PORT_READ(in_SPR_ACCESS_VAL [i]))
 	{
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"  * SPR_ACCESS [%d]",i);
+
 	  Tcontext_t     front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0;
 	  Tcontext_t     context_id   = (_param->_have_port_context_id  )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID   [i]):0;
@@ -35,4 +38,14 @@
 	  Tspr_address_t num_reg      = PORT_READ(in_SPR_ACCESS_NUM_REG   [i]);
 	  
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * front_end_id : %d",front_end_id);
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * context_id   : %d",context_id  );
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * num_group    : %d",num_group   );
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * num_reg      : %d",num_reg     );
+          
+#ifdef DEBUG_TEST
+          if (not _spr_access_mode [front_end_id][context_id]->exist(num_group,num_reg))
+            msgWarning("Access at an invalid special register (group %d, register %d)\n",num_group,num_reg);
+#endif
+
 	  SR * sr = static_cast<SR*>(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
 	  
@@ -43,13 +56,21 @@
 									       sm,
 									       sumra);
-	  
-	  PORT_WRITE(out_SPR_ACCESS_RDATA   [i], (valid)?_spr[front_end_id][context_id][num_group][num_reg]->read():0);
-	  PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid);
+
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SM           : %d",sm);
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SUMRA        : %d",sumra);
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * valid        : %d",valid);
+
+          // ISA OpenRISC : no action/exception if unauthorised spr access. Also, read 0.
+//           if (not PORT_READ(in_SPR_ACCESS_WEN [i]))
+//             {
+          Tspr_t rdata = (valid)?(_spr[front_end_id][context_id][num_group][num_reg]->read()):0;
+
+          log_printf(TRACE,Special_Register_unit,FUNCTION,"    * rdata        : %.8x",rdata);
+
+          PORT_WRITE(out_SPR_ACCESS_RDATA   [i], rdata);
+//             }
+          PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid);
 	}
     
-#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
-    end_cycle ();
-#endif
-
     log_end(Special_Register_unit,FUNCTION);
   };
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp	(revision 98)
@@ -22,4 +22,5 @@
   {
     log_begin(Special_Register_unit,FUNCTION);
+    log_function(Special_Register_unit,FUNCTION,_name.c_str());
 
     // ===================================================================
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp	(revision 98)
@@ -22,4 +22,5 @@
   {
     log_begin(Special_Register_unit,FUNCTION);
+    log_function(Special_Register_unit,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -38,5 +39,5 @@
 			throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l));
 #endif
- 		      log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l);
+ 		      log_printf(TRACE,Special_Register_unit,FUNCTION,"  * Reset SPR [%d][%d][%d][%d]",i,j,k,l);
 		      _spr [i][j][k][l]->reset();
 		    }
@@ -52,4 +53,6 @@
 	    if (PORT_READ(in_SPR_ACCESS_WEN [i]))
 	      {
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"  * SPR_ACCESS [%d]",i);
+
 		Tcontext_t     front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0;
 		Tcontext_t     context_id   = (_param->_have_port_context_id  )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID   [i]):0;
@@ -57,13 +60,28 @@
 		Tspr_address_t num_reg      = PORT_READ(in_SPR_ACCESS_NUM_REG   [i]);
 
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * front_end_id : %d",front_end_id);
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * context_id   : %d",context_id  );
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * num_group    : %d",num_group   );
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * num_reg      : %d",num_reg     );
+
  		SR * sr = static_cast<SR*>(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
 
 		Tcontrol_t sm    = sr->sm   ;
 		Tcontrol_t sumra = sr->sumra;
+                Tcontrol_t valid = _spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg),
+                                                                                      sm,
+                                                                                      sumra);	
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SM           : %d",sm);
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * SUMRA        : %d",sumra);
+                log_printf(TRACE,Special_Register_unit,FUNCTION,"    * valid        : %d",valid);
 
-		if (_spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg),
-								       sm,
-								       sumra))
-		  _spr[front_end_id][context_id][num_group][num_reg]->write(PORT_READ(in_SPR_ACCESS_WDATA [i]));
+                if (valid)
+                  {
+                    Tspr_t wdata = PORT_READ(in_SPR_ACCESS_WDATA [i]);
+
+                    log_printf(TRACE,Special_Register_unit,FUNCTION,"    * wdata        : %.8x",wdata);
+
+                    _spr[front_end_id][context_id][num_group][num_reg]->write(wdata);
+                  }
 		
 	      }
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h	(revision 98)
@@ -157,5 +157,5 @@
   public    : SC_OUT(Tdepth_t          )   ** out_BRANCH_COMPLETE_DEPTH            ;//[nb_inst_branch_complete]
   public    : SC_OUT(Taddress_t        )   ** out_BRANCH_COMPLETE_ADDRESS          ;//[nb_inst_branch_complete]
-  public    : SC_OUT(Tcontrol_t        )   ** out_BRANCH_COMPLETE_FLAG             ;//[nb_inst_branch_complete]
+  public    : SC_OUT(Tcontrol_t        )   ** out_BRANCH_COMPLETE_NO_SEQUENCE      ;//[nb_inst_branch_complete]
   public    : SC_IN (Tcontrol_t        )   **  in_BRANCH_COMPLETE_MISS_PREDICTION  ;//[nb_inst_branch_complete]
                                                                                    
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp	(revision 98)
@@ -166,5 +166,5 @@
       ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_DEPTH            ,"DEPTH"                     ,Tdepth_t          ,_param->_size_depth                  );
       ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ADDRESS          ,"ADDRESS"                   ,Taddress_t        ,_param->_size_instruction_address    );
-      ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_FLAG             ,"FLAG"                      ,Tcontrol_t        ,1                                    );
+      ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_NO_SEQUENCE      ,"NO_SEQUENCE"               ,Tcontrol_t        ,1                                    );
       ALLOC1_SIGNAL_IN  ( in_BRANCH_COMPLETE_MISS_PREDICTION  ,"MISS_PREDICTION"           ,Tcontrol_t        ,1                                    );
     }
@@ -909,6 +909,6 @@
           PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"        ,
                               dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS"        );
-          PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG"           ,
-                              dest,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG"           );
+          PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE"    ,
+                              dest,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE"    );
           PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION",
                               dest, "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION");
Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp
===================================================================
--- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 97)
+++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp	(revision 98)
@@ -105,12 +105,12 @@
 //         DELETE1_SIGNAL(out_RETIRE_RE_NEW_NUM_REG            ,_param->_sum_inst_retire,_param->_size_special_register       );
         
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_issue,1                                    );
-        DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_issue,1                                    );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_issue,_param->_size_front_end_id           );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_issue,_param->_size_context_id             );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_issue,_param->_size_depth                  );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_issue,_param->_size_general_data           );
-        DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG             ,_param->_nb_inst_issue,1                                    );
-        DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_issue,1                                    );
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL              ,_param->_nb_inst_branch_complete,1                         );
+        DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK              ,_param->_nb_inst_branch_complete,1                         );
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID     ,_param->_nb_inst_branch_complete,_param->_size_front_end_id);
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID       ,_param->_nb_inst_branch_complete,_param->_size_context_id  );
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH            ,_param->_nb_inst_branch_complete,_param->_size_depth       );
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS          ,_param->_nb_inst_branch_complete,_param->_size_general_data);
+        DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE      ,_param->_nb_inst_branch_complete,1                         );
+        DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION  ,_param->_nb_inst_branch_complete,1                         );
         
         DELETE_SIGNAL (out_COMMIT_EVENT_VAL                 , 1);
