Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Configuration/src/Configuration_header.cpp (revision 98) @@ -39,6 +39,5 @@ \ \_\ \/_/ - -*/ + */ str += toString(MSG_INFORMATION)+" __ \n"; @@ -57,5 +56,7 @@ str += toString(MSG_INFORMATION)+_(" * E-mail support : mathieu.rosiere@lip6.fr\n" ); str += toString(MSG_INFORMATION)+_(" * Original author(s) : Mathieu Rosière\n" ); - str += toString(MSG_INFORMATION)+_(" * Contributor(s) : Stéphane Dubuisson - XMLLight\n"); + str += toString(MSG_INFORMATION)+_(" * Contributor(s) : Clément Berleux - VHDL\n" ); + str += toString(MSG_INFORMATION)+_(" Kamel Chekkal - VHDL\n" ); + str += toString(MSG_INFORMATION)+_(" Stéphane Dubuisson - XMLLight\n"); str += toString(MSG_INFORMATION)+_(" Vincent Moulu - VHDL\n" ); str += toString(MSG_INFORMATION)+"\n"; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/SelfTest/src/test.cpp (revision 98) @@ -55,5 +55,5 @@ ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,"out_BRANCH_COMPLETE_FRONT_END_DEPTH ",Tdepth_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,"out_BRANCH_COMPLETE_FRONT_END_ADDRESS ",Taddress_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); - ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,"out_BRANCH_COMPLETE_FRONT_END_FLAG ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,"out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ," in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ," in_BRANCH_COMPLETE_OOO_ENGINE_VAL ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); @@ -63,5 +63,5 @@ ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ," in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ," in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); - ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ," in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + ALLOC2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ," in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); ALLOC2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL ,"out_COMMIT_EVENT_FRONT_END_VAL ",Tcontrol_t ,_param->_nb_front_end); @@ -186,5 +186,5 @@ INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); - INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); @@ -197,5 +197,5 @@ INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); - INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + INSTANCE2_SC_SIGNAL(_Core_Glue, in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); INSTANCE2_SC_SIGNAL(_Core_Glue,out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); INSTANCE1_SC_SIGNAL(_Core_Glue,out_COMMIT_EVENT_FRONT_END_VAL ,_param->_nb_front_end); @@ -393,5 +393,5 @@ in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j]->write(range(rand(),_param->_size_depth )); in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j]->write(range(rand(),_param->_size_instruction_address)); - in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j]->write(rand()%2); + in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE [i][j]->write(rand()%2); } @@ -520,6 +520,6 @@ TEST(Taddress_t,out_BRANCH_COMPLETE_FRONT_END_ADDRESS [x][j]->read(), in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j]->read()); - TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_FLAG [x][j]->read(), - in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j]->read()); + TEST(Tcontrol_t,out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE [x][j]->read(), + in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE [i][j]->read()); TEST(Tcontrol_t,out_BRANCH_COMPLETE_OOO_ENGINE_ACK [i][j]->read(), in_BRANCH_COMPLETE_FRONT_END_ACK [x][j]->read()); @@ -674,5 +674,5 @@ DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); - DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_VAL ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); @@ -682,5 +682,5 @@ DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); - DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + DELETE2_SC_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); DELETE2_SC_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); DELETE1_SC_SIGNAL(out_COMMIT_EVENT_FRONT_END_VAL ,_param->_nb_front_end); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/include/Core_Glue.h (revision 98) @@ -73,5 +73,5 @@ public : SC_OUT(Tdepth_t ) *** out_BRANCH_COMPLETE_FRONT_END_DEPTH ;//[nb_front_end][nb_inst_branch_complete] public : SC_OUT(Taddress_t ) *** out_BRANCH_COMPLETE_FRONT_END_ADDRESS ;//[nb_front_end][nb_inst_branch_complete] - public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_FRONT_END_FLAG ;//[nb_front_end][nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ;//[nb_front_end][nb_inst_branch_complete] public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ;//[nb_front_end][nb_inst_branch_complete] @@ -82,5 +82,5 @@ public : SC_IN (Tdepth_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ;//[nb_ooo_engine][nb_inst_branch_complete] public : SC_IN (Taddress_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ;//[nb_ooo_engine][nb_inst_branch_complete] - public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ;//[nb_ooo_engine][nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) *** in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ;//[nb_ooo_engine][nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) *** out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION;//[nb_ooo_engine][nb_inst_branch_complete] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue.cpp (revision 98) @@ -112,5 +112,5 @@ sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_VAL [i][j])) << (*(in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j])) - << (*(in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j])); + << (*(in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE [i][j])); if (_param->_have_port_front_end_id) sensitive << (*(in_BRANCH_COMPLETE_OOO_ENGINE_FRONT_END_ID [i][j])); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_allocation.cpp (revision 98) @@ -70,5 +70,5 @@ _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); - _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_FLAG ,"FLAG" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1]); } @@ -82,5 +82,5 @@ _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); - _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,"FLAG" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); + _ALLOC2_SIGNAL_IN ( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); _ALLOC2_SIGNAL_OUT(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,"MISS_PREDICTION" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1]); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_deallocation.cpp (revision 98) @@ -33,5 +33,5 @@ DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_DEPTH ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],_param->_size_depth); DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ADDRESS ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],_param->_size_instruction_address); - DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_FLAG ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); DELETE2_SIGNAL( in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION ,_param->_nb_front_end,_param->_front_end_nb_inst_branch_complete[it1],1); @@ -42,5 +42,5 @@ DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_depth); DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],_param->_size_instruction_address); - DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_FLAG ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); + DELETE2_SIGNAL( in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE ,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); DELETE2_SIGNAL(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION,_param->_nb_ooo_engine,_param->_ooo_engine_nb_inst_branch_complete[it1],1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Core_Glue/src/Core_Glue_genMealy_branch_complete.cpp (revision 98) @@ -51,5 +51,5 @@ PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_DEPTH [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH [i][j])); PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ADDRESS [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS [i][j])); - PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_FLAG [num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_FLAG [i][j])); + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_NO_SEQUENCE[num_front_end][j],PORT_READ(in_BRANCH_COMPLETE_OOO_ENGINE_NO_SEQUENCE[i][j])); PORT_WRITE(out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION [i][j], PORT_READ(in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION [num_front_end][j])); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/Operation/src/Operation.cpp (revision 98) @@ -226,4 +226,7 @@ Tgeneral_data_t imm = unsigned(param->_size_data,op->_immediat); + log_printf(TRACE,Functionnal_unit,FUNCTION," * data_rc : %d",op->_data_rc); + log_printf(TRACE,Functionnal_unit,FUNCTION," * f_in : %d",f_in); + // Result op->_timing = param->_timing[op->_type][op->_operation]; @@ -233,4 +236,6 @@ op->_no_sequence = f_in == 0; op->_address = imm; + + log_printf(TRACE,Functionnal_unit,FUNCTION," * no_sequence : %d",op->_no_sequence); }; @@ -664,5 +669,5 @@ spr_address_t spr_addr = reg->_spr_access_mode->translate_address(addr); - + // Test if this group is implemented in this functionnal_unit if (reg->_spr_access_mode->valid(spr_addr)) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/src/Functionnal_unit_transition.cpp (revision 98) @@ -87,6 +87,8 @@ _execute_operation_in->_write_rd = PORT_READ(in_EXECUTE_IN_WRITE_RD ); _execute_operation_in->_num_reg_rd = PORT_READ(in_EXECUTE_IN_NUM_REG_RD ); + _execute_operation_in->_data_rd = 0; // no necessaray _execute_operation_in->_write_re = PORT_READ(in_EXECUTE_IN_WRITE_RE ); _execute_operation_in->_num_reg_re = PORT_READ(in_EXECUTE_IN_NUM_REG_RE ); + _execute_operation_in->_data_re = 0; // no necessaray log_printf(TRACE,Functionnal_unit,FUNCTION," * context_id : %d",_execute_operation_in->_context_id ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/SelfTest/src/test.cpp (revision 98) @@ -370,10 +370,15 @@ for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) { - for (uint32_t i=0; i<_param->_nb_general_register; i++) + _gpr_val [0][j] = 0; + _gpr [0][j] = 0; + _spr_val [0][j] = 0; + _spr [0][j] = 0; + + for (uint32_t i=1; i<_param->_nb_general_register; i++) { _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); _gpr [i][j] = rand()%(1<<_param->_size_general_data); } - for (uint32_t i=0; i<_param->_nb_special_register; i++) + for (uint32_t i=1; i<_param->_nb_special_register; i++) { _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); @@ -381,4 +386,6 @@ } } + + // End initialisation ....... @@ -466,5 +473,5 @@ Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; - Tgeneral_data_t data = rand()%(1<<_param->_size_general_data); + Tgeneral_data_t data = (num_reg!=0)?(rand()%(1<<_param->_size_general_data)):0; GPR_WRITE_VAL [i]->write(val); @@ -534,5 +541,5 @@ // TEST(Tcontrol_t ,READ_QUEUE_OUT_READ_RA ->read(),_read_ra [rob_id]); TEST(Tgeneral_address_t,READ_QUEUE_OUT_NUM_REG_RA ->read(),_num_reg_ra [rob_id]); - TEST(Tcontrol_t ,READ_QUEUE_OUT_DATA_RA_VAL->read(),not _read_ra [rob_id] or _gpr_val [_num_reg_ra[rob_id]][ctxt]); + TEST(Tcontrol_t ,READ_QUEUE_OUT_DATA_RA_VAL->read(),not _read_ra [rob_id] or _gpr_val [_num_reg_ra[rob_id]][ctxt] or (_num_reg_ra[rob_id] == 0)); if (_read_ra [rob_id] and READ_QUEUE_OUT_DATA_RA_VAL->read()) @@ -540,5 +547,5 @@ // TEST(Tcontrol_t ,READ_QUEUE_OUT_READ_RB ->read(),_read_rb [rob_id]); TEST(Tgeneral_address_t,READ_QUEUE_OUT_NUM_REG_RB ->read(),_num_reg_rb [rob_id]); - TEST(Tcontrol_t ,READ_QUEUE_OUT_DATA_RB_VAL->read(),not _read_rb [rob_id] or _gpr_val [_num_reg_rb[rob_id]][ctxt]); + TEST(Tcontrol_t ,READ_QUEUE_OUT_DATA_RB_VAL->read(),not _read_rb [rob_id] or _gpr_val [_num_reg_rb[rob_id]][ctxt] or (_num_reg_rb[rob_id] == 0)); if (_read_rb [rob_id] and READ_QUEUE_OUT_DATA_RB_VAL->read()) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/include/Types.h (revision 98) @@ -110,33 +110,33 @@ log_printf(FUNC,Read_queue,FUNCTION,"Begin"); - _context_id = x._context_id ; - _front_end_id = x._front_end_id ; - _ooo_engine_id= x._ooo_engine_id; - _rob_id = x._rob_id ; - _operation = x._operation ; - _type = x._type ; + _context_id = x._context_id ; + _front_end_id = x._front_end_id ; + _ooo_engine_id = x._ooo_engine_id; + _rob_id = x._rob_id ; + _operation = x._operation ; + _type = x._type ; _store_queue_ptr_write = x._store_queue_ptr_write; _load_queue_ptr_write = x._load_queue_ptr_write ; - _has_immediat = x._has_immediat ; - _immediat = x._immediat ; - _read_ra = x._read_ra ; - _read_ra_val = x._read_ra == 1 ; //if not must read, the registerFile is already access - _num_reg_ra = x._num_reg_ra ; - _data_ra_val = x._read_ra == 0 ; //if not must read, the data is already valid - _data_ra = 0 ; - _read_rb = x._read_rb ; - _read_rb_val = x._read_rb == 1 ; - _num_reg_rb = x._num_reg_rb ; - _data_rb_val = x._read_rb == 0 ; - _data_rb = 0 ; - _read_rc = x._read_rc ; - _read_rc_val = x._read_rc == 1 ; - _num_reg_rc = x._num_reg_rc ; - _data_rc_val = x._read_rc == 0 ; - _data_rc = 0 ; - _write_rd = x._write_rd ; - _num_reg_rd = x._num_reg_rd ; - _write_re = x._write_re ; - _num_reg_re = x._num_reg_re ; + _has_immediat = x._has_immediat ; + _immediat = x._immediat ; + _read_ra = x._read_ra ; + _read_ra_val = x._read_ra == 1 ; //if not must read, the registerFile is already access + _num_reg_ra = x._num_reg_ra ; + _data_ra_val = ((x._read_ra == 0) or (x._num_reg_ra == 0)); //if not must read, the data is already valid + _data_ra = 0 ; + _read_rb = x._read_rb ; + _read_rb_val = x._read_rb == 1 ; + _num_reg_rb = x._num_reg_rb ; + _data_rb_val = ((x._read_rb == 0) or (x._num_reg_rb == 0)); + _data_rb = 0 ; + _read_rc = x._read_rc ; + _read_rc_val = x._read_rc == 1 ; + _num_reg_rc = x._num_reg_rc ; + _data_rc_val = x._read_rc == 0 ; + _data_rc = 0 ; + _write_rd = x._write_rd ; + _num_reg_rd = x._num_reg_rd ; + _write_re = x._write_re ; + _num_reg_re = x._num_reg_re ; log_printf(FUNC,Read_queue,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_transition.cpp (revision 98) @@ -146,7 +146,4 @@ if (_queue->size()>0) { -// protected : Tread_queue_head_entry_t * _queue_head; -// protected : std::queue * _queue; - log_printf(TRACE,Read_queue,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.8x, %.1d %.1d %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", 0, @@ -246,6 +243,4 @@ } #endif - - } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl.cpp (revision 98) @@ -26,5 +26,5 @@ //----- Queue ----- - + morpheo::behavioural::generic::queue::Parameters * param_queue; morpheo::behavioural::generic::queue::Queue * queue; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Read_queue/src/Read_queue_vhdl_body.cpp (revision 98) @@ -176,13 +176,13 @@ vhdl->set_body(0,"out_READ_QUEUE_OUT_HAS_IMMEDIAT <= internal_HAS_IMMEDIAT ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_IMMEDIAT <= internal_IMMEDIAT ;"); -// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RA <= internal_READ_RA ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RA <= internal_NUM_REG_RA ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA_VAL <= internal_NEXT_DATA_RA_VAL;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RA <= internal_NEXT_DATA_RA ;"); -// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RB <= internal_READ_RB ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RB <= internal_NUM_REG_RB ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB_VAL <= internal_NEXT_DATA_RB_VAL;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RB <= internal_NEXT_DATA_RB ;"); -// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;"); +// vhdl->set_body(0,"out_READ_QUEUE_OUT_READ_RC <= internal_READ_RC ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_NUM_REG_RC <= internal_NUM_REG_RC ;"); vhdl->set_body(0,"out_READ_QUEUE_OUT_DATA_RC_VAL <= internal_NEXT_DATA_RC_VAL;"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/src/Reservation_station_transition.cpp (revision 98) @@ -25,30 +25,31 @@ log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \ for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \ - log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ - it_dump, \ - _queue[it_dump]._context_id , \ - _queue[it_dump]._front_end_id , \ - _queue[it_dump]._ooo_engine_id , \ - _queue[it_dump]._rob_id , \ - _queue[it_dump]._type , \ - _queue[it_dump]._operation , \ - _queue[it_dump]._store_queue_ptr_write, \ - _queue[it_dump]._load_queue_ptr_write , \ - _queue[it_dump]._has_immediat , \ - _queue[it_dump]._immediat , \ - _queue[it_dump]._num_reg_ra , \ - _queue[it_dump]._data_ra_val , \ - _queue[it_dump]._data_ra , \ - _queue[it_dump]._num_reg_rb , \ - _queue[it_dump]._data_rb_val , \ - _queue[it_dump]._data_rb , \ - _queue[it_dump]._num_reg_rc , \ - _queue[it_dump]._data_rc_val , \ - _queue[it_dump]._data_rc , \ - _queue[it_dump]._write_rd , \ - _queue[it_dump]._num_reg_rd , \ - _queue[it_dump]._write_re , \ - _queue[it_dump]._num_reg_re , \ - toString(_queue[it_dump]._type).c_str()); \ + if (_queue_valid [it_dump]) \ + log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d, %.2d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ + it_dump, \ + _queue[it_dump]._context_id , \ + _queue[it_dump]._front_end_id , \ + _queue[it_dump]._ooo_engine_id , \ + _queue[it_dump]._rob_id , \ + _queue[it_dump]._type , \ + _queue[it_dump]._operation , \ + _queue[it_dump]._store_queue_ptr_write, \ + _queue[it_dump]._load_queue_ptr_write , \ + _queue[it_dump]._has_immediat , \ + _queue[it_dump]._immediat , \ + _queue[it_dump]._num_reg_ra , \ + _queue[it_dump]._data_ra_val , \ + _queue[it_dump]._data_ra , \ + _queue[it_dump]._num_reg_rb , \ + _queue[it_dump]._data_rb_val , \ + _queue[it_dump]._data_rb , \ + _queue[it_dump]._num_reg_rc , \ + _queue[it_dump]._data_rc_val , \ + _queue[it_dump]._data_rc , \ + _queue[it_dump]._write_rd , \ + _queue[it_dump]._num_reg_rd , \ + _queue[it_dump]._write_re , \ + _queue[it_dump]._num_reg_re , \ + toString(_queue[it_dump]._type).c_str()); \ } while (0) #else Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/Makefile.deps =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/Makefile.deps (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/Makefile.deps (revision 98) @@ -13,4 +13,7 @@ include $(DIR_MORPHEO)/Behavioural/Makefile.deps endif +ifndef Queue +include $(DIR_MORPHEO)/Behavioural/Generic/Queue/Makefile.deps +endif #-----[ Directory ]---------------------------------------- @@ -20,7 +23,9 @@ #-----[ Library ]------------------------------------------ Execute_queue_LIBRARY = -lExecute_queue \ + $(Queue_LIBRARY) \ $(Behavioural_LIBRARY) Execute_queue_DIR_LIBRARY = -L$(Execute_queue_DIR)/lib \ + $(Queue_DIR_LIBRARY) \ $(Behavioural_DIR_LIBRARY) @@ -30,4 +35,5 @@ @\ $(MAKE) Behavioural_library; \ + $(MAKE) Queue_library; \ $(MAKE) --directory=$(Execute_queue_DIR) --makefile=Makefile; @@ -35,3 +41,4 @@ @\ $(MAKE) Behavioural_library_clean; \ + $(MAKE) Queue_library_clean; \ $(MAKE) --directory=$(Execute_queue_DIR) --makefile=Makefile clean; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/SelfTest/src/test.cpp (revision 98) @@ -7,5 +7,5 @@ */ -#define NB_ITERATION 1 +#define NB_ITERATION 16 #define CYCLE_MAX (128*NB_ITERATION) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Parameters.h (revision 98) @@ -38,4 +38,5 @@ //public : uint32_t _size_ooo_engine_id ; //public : uint32_t _size_packet_id ; + public : uint32_t _size_internal_queue ; //public : bool _have_port_context_id ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl.cpp (revision 98) @@ -9,4 +9,5 @@ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/include/Execute_queue.h" #include "Behavioural/include/Vhdl.h" +#include "Behavioural/Generic/Queue/include/Queue.h" namespace morpheo { @@ -25,4 +26,30 @@ { log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); + + //----- Queue ----- + + morpheo::behavioural::generic::queue::Parameters * param_queue; + morpheo::behavioural::generic::queue::Queue * queue; + + param_queue = new morpheo::behavioural::generic::queue::Parameters + (_param->_size_queue, + _param->_size_internal_queue + ); + + std::string queue_name = _name + "_queue"; + queue = new morpheo::behavioural::generic::queue::Queue + (queue_name.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_queue + ,USE_VHDL); + + _component->set_component(queue->_component +#ifdef POSITION + , 0, 0, 0, 0 +#endif + , INSTANCE_LIBRARY + ); Vhdl * vhdl = new Vhdl (_name); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_body.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_body.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_body.cpp (revision 98) @@ -24,356 +24,325 @@ { log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); - vhdl->set_body (0,""); - vhdl->set_body (0,"process (in_CLOCK)"); - vhdl->set_body (0,"begin"); - vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); -// vhdl->set_body (2,"if in_NRESET = '0' then"); -// vhdl->set_body (3,"reg_CURRENT_STATE <= STATE_0;"); -// vhdl->set_body (2,"else"); - vhdl->set_body (3,"reg_CURRENT_STATE <= sig_NEXT_STATE;"); + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Instance queue "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body (0,");"); + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Input Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + { + uint32_t min = 0; + uint32_t max, size; + + if(_param->_have_port_context_id ) + { + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); + min = max+1; + } + +// size = _param->_size_operation; +// max = min-1+size; +// vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_OPERATION;"); +// min = max+1; +// +// size = _param->_size_type; +// max = min-1+size; +// vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_TYPE;"); +// min = max+1; + + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_FLAGS;"); + min = max+1; + + size = _param->_size_exception; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); + min = max+1; + + size = 1; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); + min = max+1; + + size = _param->_size_instruction_address; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_ADDRESS;"); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_EXECUTE_QUEUE_IN_DATA;"); + min = max+1; + } + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Output Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + if(_param->_have_port_context_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID <= internal_EXECUTE_QUEUE_OUT_PACKET_ID ;"); +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OPERATION <= internal_EXECUTE_QUEUE_OUT_OPERATION ;"); +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_TYPE <= internal_EXECUTE_QUEUE_OUT_TYPE ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FLAGS <= internal_EXECUTE_QUEUE_OUT_FLAGS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_EXCEPTION <= internal_EXECUTE_QUEUE_OUT_EXCEPTION ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_ADDRESS <= internal_EXECUTE_QUEUE_OUT_ADDRESS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_DATA <= internal_EXECUTE_QUEUE_OUT_DATA ;"); + + +// vhdl->set_body (0,""); +// vhdl->set_body (0,"process (in_CLOCK)"); +// vhdl->set_body (0,"begin"); +// vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); +// // vhdl->set_body (2,"if in_NRESET = '0' then"); +// // vhdl->set_body (3,"reg_CURRENT_STATE <= STATE_0;"); +// // vhdl->set_body (2,"else"); +// vhdl->set_body (3,"reg_CURRENT_STATE <= sig_NEXT_STATE;"); +// // vhdl->set_body (2,"end if;"); + +// for (uint32_t i = 0; i <_param->_size_queue - 1; i++) +// { +// vhdl->set_body (2,"if sig_WEN_"+toString(i)+" = '1' then"); +// vhdl->set_body (3,"if sig_SEL_"+toString(i)+" = '0' then"); +// if (_param->_have_port_context_id) +// vhdl->set_body (4,"reg_CONTEXT_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); +// if (_param->_have_port_front_end_id) +// vhdl->set_body (4,"reg_FRONT_END_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); +// if (_param->_have_port_ooo_engine_id) +// vhdl->set_body (4,"reg_OOO_ENGINE_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); +// if (_param->_have_port_rob_ptr) +// vhdl->set_body (4,"reg_PACKET_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); +// vhdl->set_body (4, "reg_FLAGS_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_FLAGS;"); +// vhdl->set_body (4, "reg_EXCEPTION_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); +// vhdl->set_body (4, "reg_NO_SEQUENCE_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); +// vhdl->set_body (4, "reg_ADDRESS_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_ADDRESS;"); +// vhdl->set_body (4, "reg_DATA_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_DATA;"); + +// vhdl->set_body (3, "else"); +// if (_param->_have_port_context_id) +// vhdl->set_body (4,"reg_CONTEXT_ID_"+toString(i)+" <= reg_CONTEXT_ID_"+toString(i+1)+";"); +// if (_param->_have_port_front_end_id) +// vhdl->set_body (4,"reg_FRONT_END_ID_"+toString(i)+" <= reg_FRONT_END_ID_"+toString(i+1)+";"); +// if (_param->_have_port_ooo_engine_id) +// vhdl->set_body (4,"reg_OOO_ENGINE_ID_"+toString(i)+" <= reg_OOO_ENGINE_ID_"+toString(i+1)+";"); +// if (_param->_have_port_rob_ptr) +// vhdl->set_body (4,"reg_PACKET_ID_"+toString(i)+" <= reg_PACKET_ID_"+toString(i+1)+";"); +// vhdl->set_body (4, "reg_FLAGS_"+toString(i)+" <= reg_FLAGS_"+toString(i+1)+";"); +// vhdl->set_body (4, "reg_EXCEPTION_"+toString(i)+" <= reg_EXCEPTION_"+toString(i+1)+";"); +// vhdl->set_body (4, "reg_NO_SEQUENCE_"+toString(i)+" <= reg_NO_SEQUENCE_"+toString(i+1)+";"); +// vhdl->set_body (4, "reg_ADDRESS_"+toString(i)+" <= reg_ADDRESS_"+toString(i+1)+";"); +// vhdl->set_body (4, "reg_DATA_"+toString(i)+" <= reg_DATA_"+toString(i+1)+";"); + +// vhdl->set_body (3,"end if;"); + +// vhdl->set_body (2,"end if;"); +// } + +// vhdl->set_body (2,"if sig_WEN_"+toString(_param->_size_queue-1)+" = '1' then"); +// if (_param->_have_port_context_id) +// vhdl->set_body (3,"reg_CONTEXT_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); +// if (_param->_have_port_front_end_id) +// vhdl->set_body (3,"reg_FRONT_END_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); +// if (_param->_have_port_ooo_engine_id) +// vhdl->set_body (3,"reg_OOO_ENGINE_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); +// if (_param->_have_port_rob_ptr) +// vhdl->set_body (3,"reg_PACKET_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); +// vhdl->set_body (3, "reg_FLAGS_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_FLAGS;"); +// vhdl->set_body (3, "reg_EXCEPTION_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); +// vhdl->set_body (3, "reg_NO_SEQUENCE_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); +// vhdl->set_body (3, "reg_ADDRESS_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_ADDRESS;"); +// vhdl->set_body (3, "reg_DATA_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_DATA;"); // vhdl->set_body (2,"end if;"); - for (uint32_t i = 0; i <_param->_size_queue - 1; i++) - { - vhdl->set_body (2,"if sig_WEN_"+toString(i)+" = '1' then"); - vhdl->set_body (3,"if sig_SEL_"+toString(i)+" = '0' then"); - if (_param->_have_port_context_id) - vhdl->set_body (4,"reg_CONTEXT_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); - if (_param->_have_port_front_end_id) - vhdl->set_body (4,"reg_FRONT_END_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); - if (_param->_have_port_ooo_engine_id) - vhdl->set_body (4,"reg_OOO_ENGINE_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); - if (_param->_have_port_rob_ptr) - vhdl->set_body (4,"reg_PACKET_ID_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); - vhdl->set_body (4, "reg_FLAGS_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_FLAGS;"); - vhdl->set_body (4, "reg_EXCEPTION_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); - vhdl->set_body (4, "reg_NO_SEQUENCE_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); - vhdl->set_body (4, "reg_ADDRESS_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_ADDRESS;"); - vhdl->set_body (4, "reg_DATA_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_DATA;"); - - vhdl->set_body (3, "else"); - if (_param->_have_port_context_id) - vhdl->set_body (4,"reg_CONTEXT_ID_"+toString(i)+" <= reg_CONTEXT_ID_"+toString(i+1)+";"); - if (_param->_have_port_front_end_id) - vhdl->set_body (4,"reg_FRONT_END_ID_"+toString(i)+" <= reg_FRONT_END_ID_"+toString(i+1)+";"); - if (_param->_have_port_ooo_engine_id) - vhdl->set_body (4,"reg_OOO_ENGINE_ID_"+toString(i)+" <= reg_OOO_ENGINE_ID_"+toString(i+1)+";"); - if (_param->_have_port_rob_ptr) - vhdl->set_body (4,"reg_PACKET_ID_"+toString(i)+" <= reg_PACKET_ID_"+toString(i+1)+";"); - vhdl->set_body (4, "reg_FLAGS_"+toString(i)+" <= reg_FLAGS_"+toString(i+1)+";"); - vhdl->set_body (4, "reg_EXCEPTION_"+toString(i)+" <= reg_EXCEPTION_"+toString(i+1)+";"); - vhdl->set_body (4, "reg_NO_SEQUENCE_"+toString(i)+" <= reg_NO_SEQUENCE_"+toString(i+1)+";"); - vhdl->set_body (4, "reg_ADDRESS_"+toString(i)+" <= reg_ADDRESS_"+toString(i+1)+";"); - vhdl->set_body (4, "reg_DATA_"+toString(i)+" <= reg_DATA_"+toString(i+1)+";"); - - vhdl->set_body (3,"end if;"); - - vhdl->set_body (2,"end if;"); - } - - vhdl->set_body (2,"if sig_WEN_"+toString(_param->_size_queue-1)+" = '1' then"); - if (_param->_have_port_context_id) - vhdl->set_body (3,"reg_CONTEXT_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); - if (_param->_have_port_front_end_id) - vhdl->set_body (3,"reg_FRONT_END_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); - if (_param->_have_port_ooo_engine_id) - vhdl->set_body (3,"reg_OOO_ENGINE_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); - if (_param->_have_port_rob_ptr) - vhdl->set_body (3,"reg_PACKET_ID_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); - vhdl->set_body (3, "reg_FLAGS_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_FLAGS;"); - vhdl->set_body (3, "reg_EXCEPTION_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); - vhdl->set_body (3, "reg_NO_SEQUENCE_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); - vhdl->set_body (3, "reg_ADDRESS_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_ADDRESS;"); - vhdl->set_body (3, "reg_DATA_"+toString(_param->_size_queue-1)+" <= in_EXECUTE_QUEUE_IN_DATA;"); - vhdl->set_body (2,"end if;"); - - - vhdl->set_body (1,"end if;"); - vhdl->set_body (0,"end process;"); - - - vhdl->set_body (0,""); - vhdl->set_body (0,""); - vhdl->set_body (0,""); - - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_VAL <= sig_OUT_VAL;"); - vhdl->set_body (0,"out_EXECUTE_QUEUE_IN_ACK <= sig_IN_ACK;"); - if (_param->_have_port_context_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= reg_CONTEXT_ID_0;"); - if (_param->_have_port_front_end_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= reg_FRONT_END_ID_0;"); - if (_param->_have_port_ooo_engine_id) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0;"); - if (_param->_have_port_rob_ptr) - vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID <= reg_PACKET_ID_0;"); - vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_FLAGS <= reg_FLAGS_0;"); - vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_EXCEPTION <= reg_EXCEPTION_0;"); - vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= reg_NO_SEQUENCE_0;"); - vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_ADDRESS <= reg_ADDRESS_0;"); - vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_DATA <= reg_DATA_0;"); - - - vhdl->set_body (0,""); - - vhdl->set_body (0,"process (reg_CURRENT_STATE, in_EXECUTE_QUEUE_OUT_ACK, in_EXECUTE_QUEUE_IN_VAL, in_NRESET)"); - vhdl->set_body (0,"begin"); - vhdl->set_body (1,"if in_NRESET = '0' then"); - vhdl->set_body (2,"sig_NEXT_STATE <= STATE_0;"); - vhdl->set_body (1,"else"); - vhdl->set_body (2,"case reg_CURRENT_STATE is"); - for (uint32_t i = 0; i <_param->_size_queue + 1; i++) - { - vhdl->set_body (3,"when STATE_"+toString(i)+" =>"); - if (i == 0) - { - vhdl->set_body (4,"if in_EXECUTE_QUEUE_IN_VAL = '1' then"); - vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE ("+toString(_param->_size_queue-1)+" downto 0) & '0';"); - vhdl->set_body (4,"else"); - vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); - vhdl->set_body (4,"end if;"); - continue; - } - if (i == (_param->_size_queue)) - { - vhdl->set_body (4,"if in_EXECUTE_QUEUE_OUT_ACK = '1' then"); - vhdl->set_body (5,"sig_NEXT_STATE <= '0' & reg_CURRENT_STATE ("+toString(_param->_size_queue)+" downto 1);"); - vhdl->set_body (4,"else"); - vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); - vhdl->set_body (4,"end if;"); - continue; - } - vhdl->set_body (4,"if in_EXECUTE_QUEUE_IN_VAL = '1' and in_EXECUTE_QUEUE_OUT_ACK = '0' then"); - vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE ("+toString(_param->_size_queue-1)+" downto 0) & '0';"); - vhdl->set_body (4,"elsif in_EXECUTE_QUEUE_IN_VAL = '0' and in_EXECUTE_QUEUE_OUT_ACK = '1' then"); - vhdl->set_body (5,"sig_NEXT_STATE <= '0' & reg_CURRENT_STATE ("+toString(_param->_size_queue)+" downto 1);"); - vhdl->set_body (4,"else"); - vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); - vhdl->set_body (4,"end if;"); - } - vhdl->set_body (3,"when others => assert false report \"wrong state\" severity failure;"); - vhdl->set_body (2,"end case;"); - vhdl->set_body (1,"end if;"); - - vhdl->set_body (2,"case reg_CURRENT_STATE is"); - for (uint32_t i = 0; i <_param->_size_queue + 1; i++) - { - vhdl->set_body (3,"when STATE_"+toString(i)+" =>"); - if (i == 0) - { - vhdl->set_body (4,"sig_OUT_VAL <= '0';"); - vhdl->set_body (4,"sig_IN_ACK <= '1';"); - for (uint32_t j = 0; j <_param->_size_queue; j++) - { - if (i == j) - { - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_IN_VAL;"); - } - else - { - if (j < (_param->_size_queue - 1)) - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); - } - } - continue; - } - if (i == (_param->_size_queue)) - { - vhdl->set_body (4,"sig_OUT_VAL <= '1';"); - vhdl->set_body (4,"sig_IN_ACK <= '0';"); - for (uint32_t j = 0; j <_param->_size_queue; j++) - { - if (j == (i - 1)) - { - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); - } - else - { - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); - } - } - continue; - } - vhdl->set_body (4,"sig_OUT_VAL <= '1';"); - vhdl->set_body (4,"sig_IN_ACK <= '1';"); - for (uint32_t j = 0; j <_param->_size_queue; j++) - { - if (j < (i - 1)) - { - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); - } - if (j == (i - 1)) - { - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK and in_EXECUTE_QUEUE_IN_VAL;"); - } - if (j == i) - { - if (j < (_param->_size_queue - 1)) - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_IN_VAL and not in_EXECUTE_QUEUE_OUT_ACK;"); - } - if (j > i) - { - if (j < (_param->_size_queue - 1)) - vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); - vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); - } - } - } - vhdl->set_body (3,"when others =>"); - vhdl->set_body (2,"end case;"); - - vhdl->set_body (0,"end process;"); - - - + +// vhdl->set_body (1,"end if;"); +// vhdl->set_body (0,"end process;"); + + +// vhdl->set_body (0,""); +// vhdl->set_body (0,""); +// vhdl->set_body (0,""); + +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_VAL <= sig_OUT_VAL;"); +// vhdl->set_body (0,"out_EXECUTE_QUEUE_IN_ACK <= sig_IN_ACK;"); +// if (_param->_have_port_context_id) +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= reg_CONTEXT_ID_0;"); +// if (_param->_have_port_front_end_id) +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= reg_FRONT_END_ID_0;"); +// if (_param->_have_port_ooo_engine_id) +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0;"); +// if (_param->_have_port_rob_ptr) +// vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID <= reg_PACKET_ID_0;"); +// vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_FLAGS <= reg_FLAGS_0;"); +// vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_EXCEPTION <= reg_EXCEPTION_0;"); +// vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= reg_NO_SEQUENCE_0;"); +// vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_ADDRESS <= reg_ADDRESS_0;"); +// vhdl->set_body (0, "out_EXECUTE_QUEUE_OUT_DATA <= reg_DATA_0;"); + + +// vhdl->set_body (0,""); + +// vhdl->set_body (0,"process (reg_CURRENT_STATE, in_EXECUTE_QUEUE_OUT_ACK, in_EXECUTE_QUEUE_IN_VAL, in_NRESET)"); +// vhdl->set_body (0,"begin"); +// vhdl->set_body (1,"if in_NRESET = '0' then"); +// vhdl->set_body (2,"sig_NEXT_STATE <= STATE_0;"); +// vhdl->set_body (1,"else"); +// vhdl->set_body (2,"case reg_CURRENT_STATE is"); +// for (uint32_t i = 0; i <_param->_size_queue + 1; i++) +// { +// vhdl->set_body (3,"when STATE_"+toString(i)+" =>"); +// if (i == 0) +// { +// vhdl->set_body (4,"if in_EXECUTE_QUEUE_IN_VAL = '1' then"); +// vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE ("+toString(_param->_size_queue-1)+" downto 0) & '0';"); +// vhdl->set_body (4,"else"); +// vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); +// vhdl->set_body (4,"end if;"); +// continue; +// } +// if (i == (_param->_size_queue)) +// { +// vhdl->set_body (4,"if in_EXECUTE_QUEUE_OUT_ACK = '1' then"); +// vhdl->set_body (5,"sig_NEXT_STATE <= '0' & reg_CURRENT_STATE ("+toString(_param->_size_queue)+" downto 1);"); +// vhdl->set_body (4,"else"); +// vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); +// vhdl->set_body (4,"end if;"); +// continue; +// } +// vhdl->set_body (4,"if in_EXECUTE_QUEUE_IN_VAL = '1' and in_EXECUTE_QUEUE_OUT_ACK = '0' then"); +// vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE ("+toString(_param->_size_queue-1)+" downto 0) & '0';"); +// vhdl->set_body (4,"elsif in_EXECUTE_QUEUE_IN_VAL = '0' and in_EXECUTE_QUEUE_OUT_ACK = '1' then"); +// vhdl->set_body (5,"sig_NEXT_STATE <= '0' & reg_CURRENT_STATE ("+toString(_param->_size_queue)+" downto 1);"); +// vhdl->set_body (4,"else"); +// vhdl->set_body (5,"sig_NEXT_STATE <= reg_CURRENT_STATE;"); +// vhdl->set_body (4,"end if;"); +// } +// vhdl->set_body (3,"when others => assert false report \"wrong state\" severity failure;"); // vhdl->set_body (2,"end case;"); -// for (uint32_t i = 0; i <_param->_size_queue; i++) +// vhdl->set_body (1,"end if;"); + +// vhdl->set_body (2,"case reg_CURRENT_STATE is"); +// for (uint32_t i = 0; i <_param->_size_queue + 1; i++) // { -// if (i == 0) -// vhdl->set_body (4,"sig_WEN_"+toString(i)+" <= in_EXECUTE_QUEUE_IN_VAL;"); -// else -// vhdl->set_body (4,"sig_WEN_"+toString(i)+" <= '0';"); -// if (i < _param->_size_queue - 1) -// vhdl->set_body (4,"sig_SEL_"+toString(i)+" <= '0';"); +// vhdl->set_body (3,"when STATE_"+toString(i)+" =>"); +// if (i == 0) +// { +// vhdl->set_body (4,"sig_OUT_VAL <= '0';"); +// vhdl->set_body (4,"sig_IN_ACK <= '1';"); +// for (uint32_t j = 0; j <_param->_size_queue; j++) +// { +// if (i == j) +// { +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_IN_VAL;"); +// } +// else +// { +// if (j < (_param->_size_queue - 1)) +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); +// } +// } +// continue; +// } +// if (i == (_param->_size_queue)) +// { +// vhdl->set_body (4,"sig_OUT_VAL <= '1';"); +// vhdl->set_body (4,"sig_IN_ACK <= '0';"); +// for (uint32_t j = 0; j <_param->_size_queue; j++) +// { +// if (j == (i - 1)) +// { +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); +// } +// else +// { +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); +// } +// } +// continue; +// } +// vhdl->set_body (4,"sig_OUT_VAL <= '1';"); +// vhdl->set_body (4,"sig_IN_ACK <= '1';"); +// for (uint32_t j = 0; j <_param->_size_queue; j++) +// { +// if (j < (i - 1)) +// { +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK;"); +// } +// if (j == (i - 1)) +// { +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_OUT_ACK and in_EXECUTE_QUEUE_IN_VAL;"); +// } +// if (j == i) +// { +// if (j < (_param->_size_queue - 1)) +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= in_EXECUTE_QUEUE_IN_VAL and not in_EXECUTE_QUEUE_OUT_ACK;"); +// } +// if (j > i) +// { +// if (j < (_param->_size_queue - 1)) +// vhdl->set_body (4,"sig_SEL_"+toString(j)+" <= '0';"); +// vhdl->set_body (4,"sig_WEN_"+toString(j)+" <= '0';"); +// } +// } // } -// vhdl->set_body (2,"end process;"); - -// vhdl->set_body (0,"sig_TRANS_OUT <="); -// vhdl->set_body (1,"'0' when reg_CURRENT_STATE = STATE_0 else"); -// vhdl->set_body (1,"'1';"); - -// vhdl->set_body (0,"sig_TRANS_IN <="); -// vhdl->set_body (1,"'0' when reg_CURRENT_STATE = STATE_"+toString(_param->_size_queue)+" else"); -// vhdl->set_body (1,"'1';"); - - - -// vhdl->set_body (0,"sig_NEXT_STATE <="); -// vhdl->set_body (1,"reg_CURRENT_STATE("+toString(_param->_size_queue-1)+" downto 0) & '0' when in_EXECUTE_QUEUE_IN_VAL = '1' and ((reg_CURRENT_STATE = STATE_0) xor (in_EXECUTE_QUEUE_OUT_ACK = '0')) and sig_TRANS_IN = '1' else"); -// vhdl->set_body (1,"'0' & reg_CURRENT_STATE("+toString(_param->_size_queue)+" downto 1) when in_EXECUTE_QUEUE_OUT_ACK = '1' and ((in_EXECUTE_QUEUE_IN_VAL = '0') xor (reg_CURRENT_STATE = STATE_"+toString(_param->_size_queue)+")) and sig_TRANS_OUT = '1' else"); -// vhdl->set_body (1,"reg_CURRENT_STATE;"); - -// vhdl->set_body (0,"sig_WEN_0 <="); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_IN_VAL when reg_CURRENT_STATE = STATE_0 else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_OUT_ACK and in_EXECUTE_QUEUE_IN_VAL when reg_CURRENT_STATE = STATE_1 else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_OUT_ACK;"); -// for (uint32_t i = 1; i <_param->_size_queue-1; i++) -// { -// vhdl->set_body (0,"sig_WEN_"+toString(i)+" <="); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_IN_VAL and not in_EXECUTE_QUEUE_OUT_ACK when reg_CURRENT_STATE = STATE_"+toString(i)+" else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_IN_VAL and in_EXECUTE_QUEUE_OUT_ACK when reg_CURRENT_STATE = STATE_"+toString(i+1)+" else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_OUT_ACK;"); -// } -// vhdl->set_body (0,"sig_WEN_"+toString(_param->_size_queue-1)+" <="); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_IN_VAL and not in_EXECUTE_QUEUE_OUT_ACK when reg_CURRENT_STATE = STATE_"+toString(_param->_size_queue-1)+" else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_OUT_ACK;"); - -// vhdl->set_body (0,""); -// for (uint32_t i = 0; i <_param->_size_queue-1; i++) -// { -// vhdl->set_body (0,"sig_SEL_"+toString(i)+" <="); -// vhdl->set_body (1,"'0' when reg_CURRENT_STATE = STATE_"+toString(i+1)+" or reg_CURRENT_STATE = STATE_"+toString(i)+" else"); -// vhdl->set_body (1,"in_EXECUTE_QUEUE_OUT_ACK;"); -// } - -// process (reg_CURRENT_STATE, in_PUSH_0_VAL, in_POP_0_ACK) -// begin -// case reg_CURRENT_STATE is - -// with reg_CURRENT_STATE select -// sig_WEN0 <= -// 0 when 1, -// 4 when 6; -// when "00001" => out_POP_0_VAL <= '0'; -// out_PUSH_0_ACK <= '1'; -// sig_SEL0 <= '0'; -// sig_WEN0 <= in_PUSH_0_VAL; -// sig_SEL1 <= '0'; -// sig_WEN1 <= '0'; -// sig_SEL2 <= '0'; -// sig_WEN2 <= '0'; -// sig_WEN3 <= '0'; -// if in_PUSH_0_VAL = '1' then -// sig_NEXT_STATE <= reg_CURRENT_STATE(3 downto 0) & '0'; -// else -// sig_NEXT_STATE <= reg_CURRENT_STATE; -// end if; - -// when "00010" => out_POP_0_VAL <= '1'; -// out_PUSH_0_ACK <= '1'; -// sig_SEL0 <= '0'; -// sig_WEN0 <= in_POP_0_ACK and in_PUSH_0_VAL; -// sig_SEL1 <= '0'; -// sig_WEN1 <= in_PUSH_0_VAL and not in_POP_0_ACK; -// sig_SEL2 <= '0'; -// sig_WEN2 <= '0'; -// sig_WEN3 <= '0'; -// if (in_PUSH_0_VAL = '1') and (in_POP_0_ACK = '0') then -// sig_NEXT_STATE <= reg_CURRENT_STATE(3 downto 0) & '0'; -// elsif (in_PUSH_0_VAL = '0') and (in_POP_0_ACK = '1') then -// sig_NEXT_STATE <= '0' & reg_CURRENT_STATE(4 downto 1); -// else -// sig_NEXT_STATE <= reg_CURRENT_STATE; -// end if; - -// when "00100" => out_POP_0_VAL <= '1'; -// out_PUSH_0_ACK <= '1'; -// sig_SEL0 <= in_POP_0_ACK; -// sig_WEN0 <= in_POP_0_ACK; -// sig_SEL1 <= '0'; -// sig_WEN1 <= in_POP_0_ACK and in_PUSH_0_VAL; -// sig_SEL2 <= '0'; -// sig_WEN2 <= in_PUSH_0_VAL and not in_POP_0_ACK; -// sig_WEN3 <= '0'; -// if (in_PUSH_0_VAL = '1') and (in_POP_0_ACK = '0') then -// sig_NEXT_STATE <= reg_CURRENT_STATE(3 downto 0) & '0'; -// elsif (in_PUSH_0_VAL = '0') and (in_POP_0_ACK = '1') then -// sig_NEXT_STATE <= '0' & reg_CURRENT_STATE(4 downto 1); -// else -// sig_NEXT_STATE <= reg_CURRENT_STATE; -// end if; - -// when "01000" => out_POP_0_VAL <= '1'; -// out_PUSH_0_ACK <= '1'; -// sig_SEL0 <= in_POP_0_ACK; -// sig_WEN0 <= in_POP_0_ACK; -// sig_SEL1 <= in_POP_0_ACK; -// sig_WEN1 <= in_POP_0_ACK; -// sig_SEL2 <= '0'; -// sig_WEN2 <= in_POP_0_ACK and in_PUSH_0_VAL; -// sig_WEN3 <= in_PUSH_0_VAL and not in_POP_0_ACK; -// if (in_PUSH_0_VAL = '1') and (in_POP_0_ACK = '0') then -// sig_NEXT_STATE <= reg_CURRENT_STATE(3 downto 0) & '0'; -// elsif (in_PUSH_0_VAL = '0') and (in_POP_0_ACK = '1') then -// sig_NEXT_STATE <= '0' & reg_CURRENT_STATE(4 downto 1); -// else -// sig_NEXT_STATE <= reg_CURRENT_STATE; -// end if; - -// when "10000" => out_POP_0_VAL <= '1'; -// out_PUSH_0_ACK <= '0'; -// sig_SEL0 <= in_POP_0_ACK; -// sig_WEN0 <= in_POP_0_ACK; -// sig_SEL1 <= in_POP_0_ACK; -// sig_WEN1 <= in_POP_0_ACK; -// sig_SEL2 <= in_POP_0_ACK; -// sig_WEN2 <= in_POP_0_ACK; -// sig_WEN3 <= '0'; -// if (in_PUSH_0_VAL = '0') and (in_POP_0_ACK = '1') then -// sig_NEXT_STATE <= '0' & reg_CURRENT_STATE(4 downto 1); -// else -// sig_NEXT_STATE <= reg_CURRENT_STATE; -// end if; - -// when others => -// sig_next_state <= "00001"; - -// end case; -// end process; +// vhdl->set_body (3,"when others =>"); +// vhdl->set_body (2,"end case;"); +// vhdl->set_body (0,"end process;"); log_printf(FUNC,Execute_queue,FUNCTION,"End"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_declaration.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_declaration.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Execute_queue/src/Execute_queue_vhdl_declaration.cpp (revision 98) @@ -25,37 +25,112 @@ log_printf(FUNC,Execute_queue,FUNCTION,"Begin"); - for (uint32_t i=0; i<_param->_size_queue; ++i) + vhdl->set_alias ("internal_QUEUE_INSERT_VAL ",1," in_EXECUTE_QUEUE_IN_VAL",std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_INSERT_ACK ",1,"out_EXECUTE_QUEUE_IN_ACK",std_logic_range(1)); + vhdl->set_signal ("internal_QUEUE_INSERT_DATA ",_param->_size_internal_queue); + vhdl->set_signal ("internal_QUEUE_RETIRE_DATA ",_param->_size_internal_queue); + vhdl->set_alias ("internal_QUEUE_RETIRE_VAL ",1,"out_EXECUTE_QUEUE_OUT_VAL",std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_RETIRE_ACK ",1," in_EXECUTE_QUEUE_OUT_ACK",std_logic_range(1)); + + uint32_t min = 0; + uint32_t max, size; + + if(_param->_have_port_context_id ) { - if (_param->_have_port_context_id) - vhdl->set_signal("reg_CONTEXT_ID_"+toString(i),_param->_size_context_id); - if (_param->_have_port_front_end_id) - vhdl->set_signal("reg_FRONT_END_ID_"+toString(i),_param->_size_front_end_id); - if (_param->_have_port_ooo_engine_id) - vhdl->set_signal("reg_OOO_ENGINE_ID_"+toString(i),_param->_size_ooo_engine_id); - if (_param->_have_port_rob_ptr) - vhdl->set_signal("reg_PACKET_ID_"+toString(i),_param->_size_rob_ptr); - vhdl->set_signal("reg_FLAGS_"+toString(i),_param->_size_special_data); - vhdl->set_signal("reg_EXCEPTION_"+toString(i),_param->_size_exception); - vhdl->set_signal("reg_NO_SEQUENCE_"+toString(i),1); - vhdl->set_signal("reg_ADDRESS_"+toString(i),_param->_size_instruction_address); - vhdl->set_signal("reg_DATA_"+toString(i),_param->_size_general_data); + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_PACKET_ID ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; } - vhdl->set_signal("reg_CURRENT_STATE",_param->_size_queue+1); +// size = _param->_size_operation; +// max = min-1+size; +// vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_OPERATION ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); +// min = max+1; +// +// size = _param->_size_type; +// max = min-1+size; +// vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_TYPE ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); +// min = max+1; - vhdl->set_signal("sig_NEXT_STATE",_param->_size_queue+1); + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FLAGS ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; - for (uint32_t i=0; i<_param->_size_queue-1; ++i) - { - vhdl->set_signal("sig_WEN_"+toString(i),1); - vhdl->set_signal("sig_SEL_"+toString(i),1); - } - vhdl->set_signal("sig_WEN_"+toString(_param->_size_queue - 1),1); + size = _param->_size_exception; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_EXCEPTION ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; - vhdl->set_signal("sig_IN_ACK",1); - vhdl->set_signal("sig_OUT_VAL",1); + size = 1; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; - for (uint32_t i=0; i<_param->_size_queue+1; ++i) - vhdl->set_constant("STATE_"+toString(i),_param->_size_queue+1,1<_size_instruction_address; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_ADDRESS ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_DATA ",std_logic(size),"internal_QUEUE_RETIRE_DATA",std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + +// for (uint32_t i=0; i<_param->_size_queue; ++i) +// { +// if (_param->_have_port_context_id) +// vhdl->set_signal("reg_CONTEXT_ID_"+toString(i),_param->_size_context_id); +// if (_param->_have_port_front_end_id) +// vhdl->set_signal("reg_FRONT_END_ID_"+toString(i),_param->_size_front_end_id); +// if (_param->_have_port_ooo_engine_id) +// vhdl->set_signal("reg_OOO_ENGINE_ID_"+toString(i),_param->_size_ooo_engine_id); +// if (_param->_have_port_rob_ptr) +// vhdl->set_signal("reg_PACKET_ID_"+toString(i),_param->_size_rob_ptr); +// vhdl->set_signal("reg_FLAGS_"+toString(i),_param->_size_special_data); +// vhdl->set_signal("reg_EXCEPTION_"+toString(i),_param->_size_exception); +// vhdl->set_signal("reg_NO_SEQUENCE_"+toString(i),1); +// vhdl->set_signal("reg_ADDRESS_"+toString(i),_param->_size_instruction_address); +// vhdl->set_signal("reg_DATA_"+toString(i),_param->_size_general_data); +// } + +// vhdl->set_signal("reg_CURRENT_STATE",_param->_size_queue+1); + +// vhdl->set_signal("sig_NEXT_STATE",_param->_size_queue+1); + +// for (uint32_t i=0; i<_param->_size_queue-1; ++i) +// { +// vhdl->set_signal("sig_WEN_"+toString(i),1); +// vhdl->set_signal("sig_SEL_"+toString(i),1); +// } +// vhdl->set_signal("sig_WEN_"+toString(_param->_size_queue - 1),1); + +// vhdl->set_signal("sig_IN_ACK",1); +// vhdl->set_signal("sig_OUT_VAL",1); + +// for (uint32_t i=0; i<_param->_size_queue+1; ++i) +// vhdl->set_constant("STATE_"+toString(i),_param->_size_queue+1,1<(argv[x++]); - uint32_t _size_address = fromString(argv[x++]); + uint32_t _size_general_data = fromString(argv[x++]); uint32_t * _size_inst_decod = new uint32_t [_nb_decod_unit]; @@ -70,5 +70,5 @@ _nb_inst_branch_complete , _size_depth , - _size_address , + _size_general_data , _size_inst_decod , _size_inst_commit , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp (revision 98) @@ -51,5 +51,5 @@ ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); -//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); //ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); @@ -129,5 +129,6 @@ INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context); //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); //INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); @@ -217,7 +218,8 @@ srand(seed); + const int32_t percent_transaction_branch_event = 75; const int32_t percent_transaction_decod_event = 75; const int32_t percent_transaction_commit_event = 75; - const int32_t percent_transaction_branch_complete = 75; +//const int32_t percent_transaction_branch_complete = 75; const int32_t percent_transaction_event = 75; const int32_t percent_transaction_spr = 75; @@ -239,6 +241,8 @@ in_DECOD_EVENT_VAL [i]->write(0); in_COMMIT_EVENT_VAL ->write(0); - for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) - in_BRANCH_COMPLETE_VAL [i]->write(0); +// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) +// in_BRANCH_COMPLETE_VAL [i]->write(0); + for (uint32_t i=0; i<_param->_nb_context; i++) + in_BRANCH_EVENT_VAL [i]->write(0); for (uint32_t i=0; i<_param->_nb_context; i++) @@ -525,25 +529,45 @@ in_NB_INST_COMMIT_MEM [context]->write(1); - uint32_t port = rand()%_param->_nb_inst_branch_complete; - - in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); +// uint32_t port = rand()%_param->_nb_inst_branch_complete; + +// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); +// if (_param->_have_port_depth) +// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); +// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); +// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); +// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); +// in_BRANCH_COMPLETE_TAKE [port]->write(0); + +// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + +// do +// { +// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); + +// SC_START(1); +// } +// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and +// out_BRANCH_COMPLETE_ACK [port]->read())); +// in_BRANCH_COMPLETE_VAL [port]->write(0); + + uint32_t port = context; + if (_param->_have_port_depth) - in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); - in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400); - in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500); - in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); - in_BRANCH_COMPLETE_TAKE [port]->write(0); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); - - SC_START(1); - } - while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and - out_BRANCH_COMPLETE_ACK [port]->read())); - in_BRANCH_COMPLETE_VAL [port]->write(0); + in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400); + in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500); + in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); + + SC_START(1); + } + while (not ( in_BRANCH_EVENT_VAL [port]->read() and + out_BRANCH_EVENT_ACK [port]->read())); + in_BRANCH_EVENT_VAL [port]->write(0); LABEL("miss (wait end)"); @@ -595,25 +619,44 @@ in_NB_INST_COMMIT_MEM [context]->write(1); - uint32_t port = rand()%_param->_nb_inst_branch_complete; - - in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); - if (_param->_have_port_depth) - in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); - in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); - in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); - in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); - in_BRANCH_COMPLETE_TAKE [port]->write(1); - - TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); - - do - { - in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); - - SC_START(1); - } - while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and - out_BRANCH_COMPLETE_ACK [port]->read())); - in_BRANCH_COMPLETE_VAL [port]->write(0); +// uint32_t port = rand()%_param->_nb_inst_branch_complete; + +// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context); +// if (_param->_have_port_depth) +// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); +// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600); +// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700); +// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1); +// in_BRANCH_COMPLETE_TAKE [port]->write(1); + +// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + +// do +// { +// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete); + +// SC_START(1); +// } +// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and +// out_BRANCH_COMPLETE_ACK [port]->read())); +// in_BRANCH_COMPLETE_VAL [port]->write(0); + + uint32_t port = context; + + in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context])); + in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600); + in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700); + in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1); + + TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1); + + do + { + in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event); + + SC_START(1); + } + while (not ( in_BRANCH_EVENT_VAL [port]->read() and + out_BRANCH_EVENT_ACK [port]->read())); + in_BRANCH_EVENT_VAL [port]->write(0); LABEL("miss (wait end)"); @@ -1238,5 +1281,5 @@ DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context); //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); + DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context); //DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h (revision 98) @@ -67,8 +67,8 @@ public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_ACK ;//[nb_context] //public : SC_IN (Tcontext_t ) ** in_BRANCH_EVENT_CONTEXT_ID ;//[nb_context] -//public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context] -//public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context] + public : SC_IN (Tdepth_t ) ** in_BRANCH_EVENT_DEPTH ;//[nb_context] +//public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_MISS_PREDICTION ;//[nb_context]// always public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_SRC ;//[nb_context] - public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ADDRESS_DEST_VAL ;//[nb_context]// take or not public : SC_IN (Taddress_t ) ** in_BRANCH_EVENT_ADDRESS_DEST ;//[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Parameters.h (revision 98) @@ -29,5 +29,5 @@ public : uint32_t * _array_size_depth ; //[nb_context] //public : uint32_t * _size_depth ; //[nb_context] -//public : uint32_t _size_address ; +//public : uint32_t _size_general_data ; //public : uint32_t * _size_nb_inst_decod ; //[nb_decod_unit] //public : uint32_t _size_nb_inst_commit ; @@ -39,5 +39,5 @@ uint32_t nb_inst_branch_complete, uint32_t * size_depth, - uint32_t size_address, + uint32_t size_general_data, uint32_t * size_nb_inst_decod, uint32_t size_nb_inst_commit, Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_allocation.cpp (revision 98) @@ -63,5 +63,5 @@ ALLOC1_VALACK_OUT(out_BRANCH_EVENT_ACK ,ACK); // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); -// ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); // ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t ,_param->_size_instruction_address); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_deallocation.cpp (revision 98) @@ -31,5 +31,5 @@ DELETE1_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context,1); // DELETE1_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); -// DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); // DELETE1_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); DELETE1_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp (revision 98) @@ -40,10 +40,11 @@ if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i]) { + log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i); + // throw ERRORMORPHEO(FUNCTION,_("Not yet implemented (Comming Soon).\n")); context_state_t state = reg_STATE [i]; - Tdepth_t depth = // (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]): - 0; + Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0; Tdepth_t depth_cur = reg_EVENT_DEPTH [i]; Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0; @@ -61,9 +62,9 @@ // is_valid = can modify local information // if context_state_ok : yes - // if context_state_ko : test the depth, and the priority of envent + // if context_state_ko : test the depth, and the priority of event bool is_valid = ((state == CONTEXT_STATE_OK) or (depth1< depth0) or - ((depth1==depth0) and (priority1>priority0))); + ((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth if (is_valid) @@ -76,5 +77,5 @@ //reg_EVENT_ADDRESS_EEAR [i] = 0; reg_EVENT_ADDRESS_EEAR_VAL [i] = 0; - reg_EVENT_IS_DELAY_SLOT [i] = dest_val; + reg_EVENT_IS_DELAY_SLOT [i] = 1; reg_EVENT_IS_DS_TAKE [i] = dest_val; reg_EVENT_DEPTH [i] = depth; @@ -89,4 +90,6 @@ if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i]) { + log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i); + Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0; Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0; @@ -190,4 +193,6 @@ if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK ) { + log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT"); + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0; Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0; @@ -252,50 +257,51 @@ // ------------------------------------------------------------------- - for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) - if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) - { - if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) - { - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; - Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; - Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; - Tdepth_t depth_max = _param->_array_size_depth [context]; +// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++) +// if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]) +// { +// log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i); +// if (PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i])) +// { +// Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; +// Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; +// Tdepth_t depth_cur = reg_EVENT_DEPTH [context]; +// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0; +// Tdepth_t depth_max = _param->_array_size_depth [context]; -// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); -// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); - Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); - Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); +// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min)); +// // Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min)); +// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max)); +// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max)); - context_state_t state = reg_STATE [context]; +// context_state_t state = reg_STATE [context]; - // miss > excep > spr/sync - uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); - uint8_t priority1 = 2; // miss +// // miss > excep > spr/sync +// uint8_t priority0 = (state == CONTEXT_STATE_KO_MISS)?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0); +// uint8_t priority1 = 2; // miss - // is_valid = can modify local information - // if context_state_ok : yes - // if context_state_ko : test the depth, and the priority of envent +// // is_valid = can modify local information +// // if context_state_ok : yes +// // if context_state_ko : test the depth, and the priority of envent - bool is_valid = ((state == CONTEXT_STATE_OK) or - (depth1< depth0) or - ((depth1==depth0) and (priority1>priority0))); +// bool is_valid = ((state == CONTEXT_STATE_OK) or +// (depth1< depth0) or +// ((depth1==depth0) and (priority1>priority0))); - if (is_valid) - { - // commit - Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); - reg_STATE [context] = CONTEXT_STATE_KO_MISS; - reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT - reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); - reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence - //reg_EVENT_ADDRESS_EEAR [context]; - reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; - reg_EVENT_IS_DELAY_SLOT [context] = take; - reg_EVENT_IS_DS_TAKE [context] = take; - reg_EVENT_DEPTH [context] = depth; - } - } - } +// if (is_valid) +// { +// // commit +// Tcontrol_t take = PORT_READ(in_BRANCH_COMPLETE_TAKE [i]); +// reg_STATE [context] = CONTEXT_STATE_KO_MISS; +// reg_EVENT_ADDRESS [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_SRC [i])+1; //DELAY_SLOT +// reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_BRANCH_COMPLETE_ADDRESS_DEST [i]); +// reg_EVENT_ADDRESS_EPCR_VAL [context] = take; // if not take : in sequence +// //reg_EVENT_ADDRESS_EEAR [context]; +// reg_EVENT_ADDRESS_EEAR_VAL [context] = 0; +// reg_EVENT_IS_DELAY_SLOT [context] = take; +// reg_EVENT_IS_DS_TAKE [context] = take; +// reg_EVENT_DEPTH [context] = depth; +// } +// } +// } // ------------------------------------------------------------------- @@ -305,4 +311,5 @@ if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i])) { + log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i); // Write pc context_state_t state = reg_STATE [i]; @@ -338,4 +345,6 @@ if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i])) { + log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i); + // Write spr #ifdef DEBUG_TEST Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Parameters.cpp (revision 98) @@ -23,5 +23,5 @@ uint32_t nb_inst_branch_complete, uint32_t * size_depth, - uint32_t size_address, + uint32_t size_general_data, uint32_t * size_nb_inst_decod, uint32_t size_nb_inst_commit, @@ -35,5 +35,5 @@ _nb_inst_branch_complete = nb_inst_branch_complete ; _array_size_depth = size_depth ; -// _size_address = size_address ; +// _size_general_data = size_general_data ; // _size_nb_inst_decod = size_nb_inst_decod ; // _size_nb_inst_commit = size_nb_inst_commit ; @@ -46,5 +46,6 @@ _size_context_id = log2(_nb_context); _size_depth = log2(max(size_depth,_nb_context)); - _size_instruction_address = size_address; + _size_general_data = size_general_data; + _size_instruction_address = size_general_data-2; _size_nb_inst_decod = max(size_nb_inst_decod,_nb_decod_unit); _size_nb_inst_commit = size_nb_inst_commit; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp (revision 98) @@ -145,8 +145,8 @@ // Because, is not ds take, can continue in sequence -#ifdef DEBUG_TEST - if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) - throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); -#endif +// #ifdef DEBUG_TEST +// if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE)) +// throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take")); +// #endif #ifdef STATISTICS Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_decod.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_decod.cpp (revision 98) @@ -22,24 +22,46 @@ void Branch_Target_Buffer_Glue::genMealy_decod (void) { - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Glue,FUNCTION); + log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * DECOD [%d]",i); Tcontrol_t val = PORT_READ(in_DECOD_VAL [i]); Tcontrol_t register_ack = PORT_READ(in_DECOD_REGISTER_ACK [i]); Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_DECOD_VICTIM_ACK [i]):true; - PORT_WRITE(out_DECOD_ACK [i], register_ack and victim_ack); - PORT_WRITE(out_DECOD_REGISTER_VAL [i], val and victim_ack); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d", val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d", register_ack); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d", victim_ack ); + PORT_WRITE(out_DECOD_ACK [i], ( +// val and + register_ack and + victim_ack + )); + PORT_WRITE(out_DECOD_REGISTER_VAL [i], ( + val and +// register_ack and + victim_ack + )); if (_param->_have_port_victim) { - PORT_WRITE(out_DECOD_VICTIM_VAL [i], val and register_ack ); + PORT_WRITE(out_DECOD_VICTIM_VAL [i], ( + val and + register_ack // and +// victim_ack + )); if (not _param->_is_full_associative) - PORT_WRITE(out_DECOD_VICTIM_ADDRESS [i], (PORT_READ(in_DECOD_ADDRESS_SRC [i]) >> _param->_shift_bank)&_param->_mask_bank); + { + Tgeneral_data_t address_src = PORT_READ(in_DECOD_ADDRESS_SRC [i]); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x", address_src); + + PORT_WRITE(out_DECOD_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); + } } } - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_predict.cpp (revision 98) @@ -22,15 +22,21 @@ void Branch_Target_Buffer_Glue::genMealy_predict (void) { - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Glue,FUNCTION); + log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_predict; i++) { - Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; - Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); - Tgeneral_data_t addr = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * PREDICT [%d]",i); + Tptr_t index = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_INDEX [i]):0; + Tcontrol_t hit = PORT_READ(in_PREDICT_REGISTER_HIT [i][index]); + Tgeneral_data_t address_src = PORT_READ(in_PREDICT_REGISTER_ADDRESS_SRC [i][index]); + + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * index : %d" ,index ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * hit : %d" ,hit ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x",address_src); // Multiplexor PORT_WRITE(out_PREDICT_HIT [i],hit); - PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],addr); + PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],address_src); PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],PORT_READ(in_PREDICT_REGISTER_ADDRESS_DEST [i][index])); PORT_WRITE(out_PREDICT_CONDITION [i],PORT_READ(in_PREDICT_REGISTER_CONDITION [i][index])); @@ -42,19 +48,39 @@ Tcontrol_t sort_val = (_param->_have_port_victim)?PORT_READ(in_PREDICT_SORT_VAL [i]):true; Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_PREDICT_VICTIM_ACK [i]):true; + + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * sort_val : %d",sort_val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); - PORT_WRITE(out_PREDICT_ACK [i], register_ack and sort_val and victim_ack); - PORT_WRITE(out_PREDICT_REGISTER_VAL [i], val and sort_val and victim_ack); + PORT_WRITE(out_PREDICT_ACK [i], ( +// val and + register_ack and + sort_val and + victim_ack + )); + PORT_WRITE(out_PREDICT_REGISTER_VAL [i], ( + val and +// register_ack and + sort_val and + victim_ack + )); if (_param->_have_port_victim) { - PORT_WRITE(out_PREDICT_VICTIM_VAL [i], val and register_ack and sort_val ); + PORT_WRITE(out_PREDICT_VICTIM_VAL [i], ( + val and + register_ack and + sort_val // and +// victim_ack + )); PORT_WRITE(out_PREDICT_VICTIM_HIT [i], hit); if (not _param->_is_full_associative) - PORT_WRITE(out_PREDICT_VICTIM_ADDRESS [i], (addr >> _param->_shift_bank)&_param->_mask_bank); + PORT_WRITE(out_PREDICT_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); PORT_WRITE(out_PREDICT_VICTIM_INDEX [i], index); } } - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_update.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Branch_Target_Buffer_Glue_genMealy_update.cpp (revision 98) @@ -22,11 +22,18 @@ void Branch_Target_Buffer_Glue::genMealy_update (void) { - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"Begin"); + log_begin(Branch_Target_Buffer_Glue,FUNCTION); + log_function(Branch_Target_Buffer_Glue,FUNCTION,_name.c_str()); for (uint32_t i=0; i<_param->_nb_inst_update; i++) { - Tcontrol_t val = PORT_READ(in_UPDATE_VAL [i]); - Tcontrol_t register_ack = PORT_READ(in_UPDATE_REGISTER_ACK [i]); - Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM_ACK [i]):true; + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * UPDATE [%d]",i); + + Tcontrol_t val = PORT_READ(in_UPDATE_VAL [i]); + Tcontrol_t register_ack = PORT_READ(in_UPDATE_REGISTER_ACK [i]); + Tcontrol_t victim_ack = (_param->_have_port_victim)?PORT_READ(in_UPDATE_VICTIM_ACK [i]):true; + + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * val : %d",val ); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * register_ack : %d",register_ack); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * victim_ack : %d",victim_ack ); PORT_WRITE(out_UPDATE_ACK [i], register_ack and victim_ack); @@ -37,9 +44,14 @@ PORT_WRITE(out_UPDATE_VICTIM_VAL [i], val and register_ack ); if (not _param->_is_full_associative) - PORT_WRITE(out_UPDATE_VICTIM_ADDRESS [i], (PORT_READ(in_UPDATE_ADDRESS_SRC [i]) >> _param->_shift_bank)&_param->_mask_bank); + { + Tgeneral_data_t address_src = PORT_READ(in_UPDATE_ADDRESS_SRC [i]); + log_printf(TRACE,Branch_Target_Buffer_Glue,FUNCTION," * address_src : %.8x",address_src); + + PORT_WRITE(out_UPDATE_VICTIM_ADDRESS [i], (address_src >> _param->_shift_bank)&_param->_mask_bank); + } } } - log_printf(FUNC,Branch_Target_Buffer_Glue,FUNCTION,"End"); + log_end(Branch_Target_Buffer_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Glue/src/Parameters.cpp (revision 98) @@ -48,5 +48,5 @@ _mask_bank = gen_mask (_size_victim_address); - _shift_bank = log2(max_nb_instruction)+2; + _shift_bank = log2(max_nb_instruction); test(); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Parameters.cpp (revision 98) @@ -60,5 +60,5 @@ _mask_offset = gen_mask (size_offset); _mask_bank = gen_mask (size_bank ); - _shift_offset = 2; + _shift_offset = 0; _shift_bank = _shift_offset+size_offset; _shift_tag = _shift_bank +size_bank ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_allocation.cpp (revision 98) @@ -270,12 +270,4 @@ // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifndef REGISTER_INIT - if (usage_is_set(_usage,USE_SYSTEMC)) - { - reg_PREDICT_PRIORITY = 0; - reg_DECOD_PRIORITY = 0; - } -#endif - // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_decod.cpp (revision 98) @@ -25,4 +25,6 @@ log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); + if (PORT_READ(in_NRESET)) + { // Init uint32_t decod_unit = reg_DECOD_PRIORITY; @@ -262,5 +264,5 @@ else PORT_WRITE(out_DECOD_ACK [i][j], ack[j]); - + } log_end(Prediction_unit_Glue,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_predict.cpp (revision 98) @@ -24,16 +24,12 @@ log_begin(Prediction_unit_Glue,FUNCTION); log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); - + + if (PORT_READ(in_NRESET)) + { + + // Init Tcontrol_t ack [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) - { - ack [i] = 0; - -// if (_param->_have_port_depth) -// { -// PORT_WRITE(out_DEPTH_TAIL [i],PORT_READ(in_DEPTH_UPT_TAIL [i])); -// } -// PORT_WRITE(out_DEPTH_NB_BRANCH [i],PORT_READ(in_DEPTH_UPT_NB_BRANCH [i])); - } + ack [i] = 0; for (uint32_t i=0; i<_param->_nb_inst_branch_predict; i++) @@ -41,22 +37,27 @@ log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * PREDICT [%d]",i); - Tcontrol_t btb_val; - Tcontrol_t dir_val; - Tcontrol_t ras_val; - Tcontrol_t upt_val; - - Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; + Tcontrol_t btb_val = false; + Tcontrol_t dir_val = false; + Tcontrol_t ras_val = false; + Tcontrol_t upt_val = false; + + Tcontrol_t btb_ack = PORT_READ(in_PREDICT_BTB_ACK [i]); + Tcontrol_t dir_ack = PORT_READ(in_PREDICT_DIR_ACK [i]); + Tcontrol_t ras_ack = PORT_READ(in_PREDICT_RAS_ACK [i]); + Tcontrol_t upt_ack = PORT_READ(in_PREDICT_UPT_ACK [i]); + + Tcontext_t context = (reg_PREDICT_PRIORITY+i)%_param->_nb_context; // priority log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * context : %d",context); ack [context] = 1; - + if (PORT_READ(in_PREDICT_VAL[context]) == 0) { log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * not valid ..."); - btb_val = false; - dir_val = false; - ras_val = false; - upt_val = false; +// btb_val = false; +// dir_val = false; +// ras_val = false; +// upt_val = false; } else @@ -67,4 +68,8 @@ Taddress_t pc_current = PORT_READ(in_PREDICT_PC_CURRENT [context]); Tcontrol_t pc_current_is_ds_take = PORT_READ(in_PREDICT_PC_CURRENT_IS_DS_TAKE [context]); + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_previous : 0x%.8x",pc_previous ); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current : 0x%.8x",pc_current ); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * pc_current_is_ds_take : %d" ,pc_current_is_ds_take); Taddress_t pc_next ; @@ -75,17 +80,26 @@ // STEP (1) - Compute the address source + // if pc_current is a ds take, then pc_previous is a branchement Taddress_t address = (pc_current_is_ds_take)?pc_previous:pc_current; Taddress_t address_lsb = pc_current%_param->_nb_instruction [context]; //if pc_current_is_ds_take, then pc_current%_param->_nb_instruction [context] == 0 Taddress_t address_msb; - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%x",address); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address : 0x%.8x",address); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_lsb : %d" ,address_lsb); // STEP (2) - Test if branch (access at branch_target_buffer) btb_val = true; - ack [context] &= PORT_READ(in_PREDICT_BTB_ACK [i]); if (_param->_have_port_context_id) PORT_WRITE(out_PREDICT_BTB_CONTEXT_ID [i],context); PORT_WRITE(out_PREDICT_BTB_ADDRESS [i],address); + + ack [context] &= btb_ack; + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_ack : %d" ,btb_ack); + + // BTB_ack = 0 ? + if (not btb_ack) + continue; // special case : @@ -95,20 +109,26 @@ Tcontrol_t is_accurate = PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i]) and not (pc_current_is_ds_take and not hit); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * hit : %d" ,hit); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * is_accurate : %d" ,is_accurate); + // STEP (3) : Test if have branch in the packet if (hit == 1) { // STEP (3a) : branch - test condition - bool use_dir = false; bool use_ras = false; bool use_upt = false; - Tbranch_condition_t cond = PORT_READ(in_PREDICT_BTB_CONDITION [i]); + Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]); Taddress_t address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]); Taddress_t address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]); - Tcontrol_t push; + Tcontrol_t push ; Tcontrol_t direction; - switch (cond) + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * condition : %s" ,toString(condition).c_str()); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%.8x",address_src); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_dest : 0x%.8x",address_dest); + + switch (condition) { case BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : // l.j @@ -188,5 +208,5 @@ if (use_dir) { - ack[context] &= PORT_READ(in_PREDICT_DIR_ACK [i]); + ack[context] &= dir_ack; PORT_WRITE(out_PREDICT_DIR_ADDRESS_SRC [i], address_src); PORT_WRITE(out_PREDICT_DIR_STATIC [i], address_dest_have_port_context_id) PORT_WRITE(out_PREDICT_RAS_CONTEXT_ID [i], context); @@ -207,10 +227,11 @@ if (use_upt) { - ack[context] &= PORT_READ(in_PREDICT_UPT_ACK [i]); + ack[context] &= upt_ack; + if (_param->_have_port_context_id) PORT_WRITE(out_PREDICT_UPT_CONTEXT_ID [i],context); PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_SRC [i],address_src); PORT_WRITE(out_PREDICT_UPT_BTB_ADDRESS_DEST [i],address_dest); - PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],cond); + PORT_WRITE(out_PREDICT_UPT_BTB_CONDITION [i],condition); PORT_WRITE(out_PREDICT_UPT_BTB_LAST_TAKE [i],direction); PORT_WRITE(out_PREDICT_UPT_BTB_IS_ACCURATE [i],is_accurate); @@ -225,23 +246,33 @@ // * use_ras and ras_ack // * use_upt and upt_ack -// ack [context] = (PORT_READ(in_PREDICT_BTB_ACK [i]) and -// (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i])) and -// (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])) and -// (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i]))); - - dir_val = (use_dir and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i]))) and - (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); - - ras_val = (use_ras and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and - (not use_upt or (use_upt and PORT_READ(in_PREDICT_UPT_ACK [i])))); - - upt_val = (use_upt and - PORT_READ(in_PREDICT_BTB_ACK [i]) and - (not use_dir or (use_dir and PORT_READ(in_PREDICT_DIR_ACK [i]))) and - (not use_ras or (use_ras and PORT_READ(in_PREDICT_RAS_ACK [i])))); +// ack [context] = (btb_ack and +// (use_dir and dir_ack) and +// (use_ras and ras_ack) and +// (use_upt and upt_ack)); + + dir_val = (btb_ack and + use_dir and +// use_ras and +// use_upt and +// (not use_dir or (use_dir and dir_ack)) and + (not use_ras or (use_ras and ras_ack)) and + (not use_upt or (use_upt and upt_ack))); + + ras_val = (btb_ack and +// use_dir and + use_ras and +// use_upt and + (not use_dir or (use_dir and dir_ack)) and +// (not use_ras or (use_ras and ras_ack)) and + (not use_upt or (use_upt and upt_ack))); + + upt_val = (btb_ack and +// use_dir and +// use_ras and + use_upt and + (not use_dir or (use_dir and dir_ack)) and + (not use_ras or (use_ras and ras_ack))// and +// (not use_upt or (use_upt and upt_ack)) + ); // pc_next - is previously computed @@ -252,4 +283,5 @@ log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src : 0x%x",address_src); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * address_src_lsb : %d",address_src_lsb); + if (address_src_lsb == (_param->_nb_instruction [context]-1)) { @@ -288,15 +320,18 @@ PORT_WRITE(out_PREDICT_PC_NEXT_IS_DS_TAKE [context] , pc_next_is_ds_take ); + Taddress_t address_limit_min = address_lsb; + Taddress_t address_limit_max = ((pc_current_is_ds_take)?(address_lsb+1):address_msb); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * instruction enable :"); log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * nb_inst : %d",_param->_nb_instruction [context]); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [0:%d[ = 0",address_lsb); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 1",address_lsb,((pc_current_is_ds_take)?1:address_msb)); - log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * [%d:%d[ = 0",((pc_current_is_ds_take)?1:address_msb),_param->_nb_instruction [context]); - - for (uint32_t j=0; j_nb_instruction [context]); + + for (uint32_t j=0; j_nb_instruction [context]; j++) + for (uint32_t j=address_limit_max; j<_param->_nb_instruction [context]; j++) PORT_WRITE(out_PREDICT_INSTRUCTION_ENABLE [context][j], 0); // After last address (branch) : not valid if (_param->_have_port_inst_ifetch_ptr) @@ -316,4 +351,5 @@ for (uint32_t i=0; i<_param->_nb_context; i++) PORT_WRITE(out_PREDICT_ACK[i],ack[i]); + } log_end(Prediction_unit_Glue,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Prediction_unit_Glue/src/Prediction_unit_Glue_genMealy_update.cpp (revision 98) @@ -23,32 +23,69 @@ { log_begin(Prediction_unit_Glue,FUNCTION); + log_function(Prediction_unit_Glue,FUNCTION,_name.c_str()); -// for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) -// { -// Tcontrol_t btb_ack = PORT_READ(in_UPDATE_BTB_ACK [i]); -// Tcontrol_t dir_ack = PORT_READ(in_UPDATE_DIR_ACK [i]); -// Tcontrol_t ras_ack = PORT_READ(in_UPDATE_RAS_ACK [i]); -// Tcontrol_t upt_val = PORT_READ(in_UPDATE_UPT_VAL [i]); + for (uint32_t i=0; i<_param->_nb_inst_branch_update; i++) + { + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * UPDATE [%d]",i); + Tcontrol_t btb_ack = PORT_READ(in_UPDATE_BTB_ACK [i]); + Tcontrol_t dir_ack = PORT_READ(in_UPDATE_DIR_ACK [i]); + Tcontrol_t ras_ack = PORT_READ(in_UPDATE_RAS_ACK [i]); + Tcontrol_t upt_val = PORT_READ(in_UPDATE_UPT_VAL [i]); -// Tcontrol_t need_btb = PORT_READ(in_UPDATE_UPT_BTB_VAL [i]); -// Tcontrol_t need_dir = PORT_READ(in_UPDATE_UPT_DIR_VAL [i]); -// Tcontrol_t need_ras = PORT_READ(in_UPDATE_UPT_RAS_VAL [i]); + Tcontrol_t upt_btb_val = PORT_READ(in_UPDATE_UPT_BTB_VAL [i]); + Tcontrol_t upt_dir_val = PORT_READ(in_UPDATE_UPT_DIR_VAL [i]); + Tcontrol_t upt_ras_val = PORT_READ(in_UPDATE_UPT_RAS_VAL [i]); -// PORT_WRITE(out_UPDATE_BTB_VAL [i], (upt_val and need_btb and -// (not need_dir or (need_dir and dir_ack)) and -// (not need_ras or (need_ras and ras_ack)))); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_val : %d",upt_val); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_btb_val - btb_ack : %d - %d",upt_btb_val, btb_ack); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_dir_val - dir_ack : %d - %d",upt_dir_val, dir_ack); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * upt_ras_val - ras_ack : %d - %d",upt_ras_val, ras_ack); -// PORT_WRITE(out_UPDATE_DIR_VAL [i], (upt_val and need_dir and -// (not need_btb or (need_btb and btb_ack)) and -// (not need_ras or (need_ras and ras_ack)))); + Tcontrol_t btb_val = (upt_val and + upt_btb_val and +// upt_dir_val and +// upt_ras_val and +// (not upt_btb_val or (upt_btb_val and btb_ack)) and + (not upt_dir_val or (upt_dir_val and dir_ack)) and + (not upt_ras_val or (upt_ras_val and ras_ack)) + ); -// PORT_WRITE(out_UPDATE_RAS_VAL [i], (upt_val and need_ras and -// (not need_btb or (need_btb and btb_ack)) and -// (not need_dir or (need_dir and dir_ack)))); + Tcontrol_t dir_val = (upt_val and +// upt_btb_val and + upt_dir_val and +// upt_ras_val and + (not upt_btb_val or (upt_btb_val and btb_ack)) and +// (not upt_dir_val or (upt_dir_val and dir_ack)) and + (not upt_ras_val or (upt_ras_val and ras_ack)) + ); -// PORT_WRITE(out_UPDATE_UPT_ACK [i], ((not need_btb or (need_btb and btb_ack)) and -// (not need_dir or (need_dir and dir_ack)) and -// (not need_ras or (need_ras and ras_ack)))); -// } + Tcontrol_t ras_val = (upt_val and +// upt_btb_val and +// upt_dir_val and + upt_ras_val and + (not upt_btb_val or (upt_btb_val and btb_ack)) and + (not upt_dir_val or (upt_dir_val and dir_ack))// and +// (not upt_ras_val or (upt_ras_val and ras_ack)) + ); + + Tcontrol_t upt_ack = ( +// upt_val and +// upt_btb_val and +// upt_dir_val and +// upt_ras_val and + (not upt_btb_val or (upt_btb_val and btb_ack)) and + (not upt_dir_val or (upt_dir_val and dir_ack)) and + (not upt_ras_val or (upt_ras_val and ras_ack)) + ); + + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * btb_val : %d",btb_val); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * dir_val : %d",dir_val); + log_printf(TRACE,Prediction_unit_Glue,FUNCTION," * ras_val : %d",ras_val); + + PORT_WRITE(out_UPDATE_BTB_VAL [i], btb_val); + PORT_WRITE(out_UPDATE_DIR_VAL [i], dir_val); + PORT_WRITE(out_UPDATE_RAS_VAL [i], ras_val); + PORT_WRITE(out_UPDATE_UPT_ACK [i], upt_ack); + } log_end(Prediction_unit_Glue,FUNCTION); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/SelfTest/src/test.cpp (revision 98) @@ -79,5 +79,5 @@ ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); - ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,"out_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -88,5 +88,5 @@ ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); -//ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); //ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,"out_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); @@ -145,5 +145,5 @@ INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Prediction_unit, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); @@ -155,5 +155,6 @@ //if (_param->_have_port_context_id) //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -//INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); //INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Prediction_unit,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); @@ -351,5 +352,5 @@ DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); @@ -360,5 +361,5 @@ DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context); //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -//DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); + DELETE1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context); //DELETE1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context); DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp (revision 98) @@ -27,4 +27,5 @@ Tcontrol_t take_good ; Tcontrol_t flag ; + Tcontrol_t no_sequence ; Tcontrol_t is_accurate ; Thistory_t history ; @@ -104,5 +105,5 @@ ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); - ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -112,6 +113,6 @@ ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context); -// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); -// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); +// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); + ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context); // ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context); @@ -194,5 +195,5 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete); @@ -202,10 +203,9 @@ INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context); -// if (_param->_have_port_context_id) -// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); -// if (_param->_have_port_depth) -// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_DEPTH ,_param->_nb_context); -// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ADDRESS ,_param->_nb_context); -// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); +//if (_param->_have_port_context_id) +//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context); + if (_param->_have_port_depth) + INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context); +//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context); @@ -347,4 +347,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true; request.miss_ifetch = false; @@ -486,5 +487,5 @@ in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); - in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); if (_param->_have_port_depth) @@ -627,4 +628,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true; request.miss_ifetch = false; @@ -704,4 +706,5 @@ request.take_good = 0; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true; request.miss_ifetch = false; @@ -712,4 +715,5 @@ request.ras_index = (0x87654321)%_param->_size_ras_index[context]; request.ufpt_ptr = ufpt_top [context]; + request.upt_ptr = upt_top [context]; event = request; @@ -786,5 +790,5 @@ in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); - in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); if (_param->_have_port_depth) @@ -910,5 +914,6 @@ LABEL("BRANCH_EVENT [%d] - Transaction accepted",port); have_transaction = true; - + + TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); @@ -982,4 +987,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true; request.miss_ifetch = false; @@ -1059,4 +1065,5 @@ request.take_good = 0; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true; request.miss_ifetch = false; @@ -1067,4 +1074,5 @@ request.ras_index = (0x87654321)%_param->_size_ras_index[context]; request.ufpt_ptr = ufpt_top [context]; + request.upt_ptr = upt_top [context]; event = request; @@ -1141,5 +1149,5 @@ in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good); - in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); if (_param->_have_port_depth) @@ -1345,4 +1353,5 @@ have_transaction = true; + TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take); @@ -1415,4 +1424,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true ; request.miss_ifetch = false; @@ -1557,4 +1567,5 @@ request.take_good = 1; request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good); + request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag; request.is_accurate = true ; request.miss_ifetch = false; @@ -1644,4 +1655,5 @@ it_event->address_good = it_event->address_dest; it_event->flag = not it_event->flag; + it_event->no_sequence = not it_event->no_sequence; it_event->take_good = not it_event->take_good; } @@ -1662,5 +1674,5 @@ in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr ); in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good); - in_BRANCH_COMPLETE_FLAG [port]->write(it_event->flag ); + in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence ); if (_param->_have_port_depth) @@ -1675,9 +1687,10 @@ { LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); - LABEL(" * CONTEXT_ID %d" ,it_event->context ); - LABEL(" * DEPTH %d" ,it_event->upt_ptr ); - LABEL(" * CONDITION %d" ,it_event->condition ); - LABEL(" * ADDRESS %.8x",it_event->address_good); - LABEL(" * FLAG %d" ,it_event->flag ); + LABEL(" * CONTEXT_ID : %d" ,it_event->context ); + LABEL(" * DEPTH : %d" ,it_event->upt_ptr ); + LABEL(" * CONDITION : %d" ,it_event->condition ); + LABEL(" * ADDRESS : %.8x",it_event->address_good); + LABEL(" * FLAG : %d" ,it_event->flag ); + LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence ); have_transaction = true; @@ -1722,5 +1735,5 @@ in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr ); in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest); - in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag ); + in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence ); if (_param->_have_port_depth) @@ -1735,9 +1748,10 @@ { LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port); - LABEL(" * CONTEXT_ID %d" ,it_upt->context ); - LABEL(" * DEPTH %d" ,it_upt->upt_ptr ); - LABEL(" * CONDITION %d" ,it_upt->condition ); - LABEL(" * ADDRESS %.8x",it_upt->address_dest); - LABEL(" * FLAG %d" ,it_upt->flag ); + LABEL(" * CONTEXT_ID : %d" ,it_upt->context ); + LABEL(" * DEPTH : %d" ,it_upt->upt_ptr ); + LABEL(" * CONDITION : %d" ,it_upt->condition ); + LABEL(" * ADDRESS : %.8x",it_upt->address_dest); + LABEL(" * FLAG : %d" ,it_upt->flag ); + LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence ); have_transaction = true; @@ -1953,4 +1967,5 @@ LABEL(" * event.take : %.8x,",event.take ); + TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr); TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src); TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good); @@ -2120,5 +2135,5 @@ delete [] in_BRANCH_COMPLETE_DEPTH ; delete [] in_BRANCH_COMPLETE_ADDRESS ; - delete [] in_BRANCH_COMPLETE_FLAG ; + delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; delete [] out_BRANCH_COMPLETE_TAKE ; @@ -2129,6 +2144,6 @@ delete [] out_BRANCH_EVENT_VAL ; delete [] in_BRANCH_EVENT_ACK ; -//delete [] in_BRANCH_EVENT_CONTEXT_ID ; -//delete [] in_BRANCH_EVENT_DEPTH ; +//delete [] out_BRANCH_EVENT_CONTEXT_ID ; + delete [] out_BRANCH_EVENT_DEPTH ; //delete [] out_BRANCH_EVENT_MISS_PREDICTION; delete [] out_BRANCH_EVENT_ADDRESS_SRC ; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h (revision 98) @@ -106,5 +106,5 @@ public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ; //[nb_inst_branch_complete] public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ; //[nb_inst_branch_complete] - public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_FLAG ; //[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ; //[nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION; //[nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_TAKE ; //[nb_inst_branch_complete] @@ -116,5 +116,5 @@ public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] //public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] -//public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] is always miss prediction public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] @@ -176,4 +176,5 @@ private : event_state_t * reg_EVENT_STATE ; //[nb_context] + private : Tdepth_t * reg_EVENT_DEPTH ; //[nb_context] private : Taddress_t * reg_EVENT_ADDRESS_SRC ; //[nb_context] // Address branch private : Tcontrol_t * reg_EVENT_ADDRESS_DEST_VAL ; //[nb_context] // if miss ifetch, decod issue branch, dest must be reload Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table.cpp (revision 98) @@ -161,5 +161,5 @@ if (_param->_have_port_depth) sensitive << (*(in_BRANCH_COMPLETE_DEPTH [i])); - sensitive << (*(in_BRANCH_COMPLETE_FLAG [i])) + sensitive << (*(in_BRANCH_COMPLETE_NO_SEQUENCE [i])) << (*(in_BRANCH_COMPLETE_ADDRESS [i])); } @@ -173,5 +173,5 @@ if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); - (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); + (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_NO_SEQUENCE[i])); (*(out_BRANCH_COMPLETE_MISS_PREDICTION [i])) (*(in_BRANCH_COMPLETE_ADDRESS [i])); @@ -180,5 +180,5 @@ if (_param->_have_port_depth) (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_DEPTH [i])); - (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_FLAG [i])); + (*(out_BRANCH_COMPLETE_TAKE [i])) (*(in_BRANCH_COMPLETE_NO_SEQUENCE[i])); if (_param->_have_port_context_id) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_allocation.cpp (revision 98) @@ -103,5 +103,5 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_instruction_address); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); @@ -117,5 +117,5 @@ ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_instruction_address); @@ -203,4 +203,5 @@ ALLOC1(reg_EVENT_STATE ,event_state_t,_param->_nb_context); + ALLOC1(reg_EVENT_DEPTH ,Tdepth_t ,_param->_nb_context); ALLOC1(reg_EVENT_ADDRESS_SRC ,Taddress_t ,_param->_nb_context); ALLOC1(reg_EVENT_ADDRESS_DEST_VAL ,Tcontrol_t ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_deallocation.cpp (revision 98) @@ -73,5 +73,5 @@ delete [] in_BRANCH_COMPLETE_DEPTH ; delete [] in_BRANCH_COMPLETE_ADDRESS ; - delete [] in_BRANCH_COMPLETE_FLAG ; + delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ; delete [] out_BRANCH_COMPLETE_MISS_PREDICTION; delete [] out_BRANCH_COMPLETE_TAKE ; @@ -83,5 +83,5 @@ DELETE1_SIGNAL( in_BRANCH_EVENT_ACK ,_param->_nb_context,1); // DELETE1_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context,_param->_size_context_id); -// DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); + DELETE1_SIGNAL(out_BRANCH_EVENT_DEPTH ,_param->_nb_context,_param->_size_depth); // DELETE1_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context,1); DELETE1_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context,_param->_size_instruction_address); @@ -156,4 +156,5 @@ DELETE1(reg_EVENT_STATE ,_param->_nb_context); + DELETE1(reg_EVENT_DEPTH ,_param->_nb_context); DELETE1(reg_EVENT_ADDRESS_SRC ,_param->_nb_context); DELETE1(reg_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMealy_branch_complete.cpp (revision 98) @@ -40,5 +40,5 @@ Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition ; - Tcontrol_t flag = PORT_READ(in_BRANCH_COMPLETE_FLAG [i]); + Tcontrol_t no_sequence = PORT_READ(in_BRANCH_COMPLETE_NO_SEQUENCE [i]); Taddress_t addr_good = PORT_READ(in_BRANCH_COMPLETE_ADDRESS [i]); @@ -46,5 +46,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth ); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %s",toString(condition).c_str()); - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flag : %d",flag); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * no_sequence : %d",no_sequence); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * address_good : %.8x",addr_good); @@ -74,28 +74,13 @@ } case BRANCH_CONDITION_FLAG_UNSET : // l.bnf - { - //addr_dest : compute in decod stage - //miss if the direction is bad - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG_UNSET"); - - Tcontrol_t take_good = not flag; // flag set = not take - - miss = (take != take_good); - take = take_good; - -#ifdef DEBUG_TEST -// if (addr_dest != addr_good) -// throw ERRORMORPHEO(FUNCTION,toString("Branch_complete[%d] (condition %s) : bad destination address.",i,toString(condition).c_str())); -#endif - - break; - } case BRANCH_CONDITION_FLAG_SET : // l.bf { //addr_dest : compute in decod stage //miss if the direction is bad - log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG_SET"); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_CONDITION_FLAG"); - Tcontrol_t take_good = flag; // flag set = take +// Tcontrol_t take_good = not flag; // flag set = not take +// Tcontrol_t take_good = flag; // flag set = take + Tcontrol_t take_good = no_sequence; miss = (take != take_good); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_genMoore.cpp (revision 98) @@ -253,4 +253,6 @@ PORT_WRITE(out_BRANCH_EVENT_VAL [i],val); + if (_param->_have_port_depth) + PORT_WRITE(out_BRANCH_EVENT_DEPTH [i],reg_EVENT_DEPTH [i]); PORT_WRITE(out_BRANCH_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]); PORT_WRITE(out_BRANCH_EVENT_ADDRESS_DEST_VAL [i],reg_EVENT_ADDRESS_DEST_VAL [i]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp (revision 98) @@ -213,4 +213,5 @@ flush_UFPT [context] = true; + reg_EVENT_DEPTH [context] = upt_ptr_write; reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State reg_EVENT_ADDRESS_DEST_VAL[context] = last_take; @@ -303,6 +304,6 @@ if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i]) { - Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; - Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; + Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0; + Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0; Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i]; Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i]; @@ -375,4 +376,5 @@ // else no update + reg_EVENT_DEPTH [context] = depth; reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State reg_EVENT_ADDRESS_DEST_VAL[context] = good_take; @@ -668,4 +670,5 @@ log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_STATE : %s" ,toString(reg_EVENT_STATE [i]).c_str()); + log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x",reg_EVENT_ADDRESS_SRC [i]); log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/include/Prediction_unit.h (revision 98) @@ -98,5 +98,5 @@ public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ; //[nb_inst_branch_complete] public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ; //[nb_inst_branch_complete] - public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_FLAG ; //[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ; //[nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ; //[nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_TAKE ; //[nb_inst_branch_complete] @@ -108,5 +108,5 @@ public : SC_IN (Tcontrol_t ) ** in_BRANCH_EVENT_ACK ; //[nb_context] //public : SC_OUT(Tcontext_t ) ** out_BRANCH_EVENT_CONTEXT_ID ; //[nb_context] -//public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] + public : SC_OUT(Tdepth_t ) ** out_BRANCH_EVENT_DEPTH ; //[nb_context] //public : SC_OUT(Tcontrol_t ) ** out_BRANCH_EVENT_MISS_PREDICTION ; //[nb_context] public : SC_OUT(Taddress_t ) ** out_BRANCH_EVENT_ADDRESS_SRC ; //[nb_context] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_allocation.cpp (revision 98) @@ -102,5 +102,5 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t,_param->_size_address); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_TAKE ,"take" ,Tcontrol_t,1); @@ -116,5 +116,5 @@ ALLOC1_VALACK_IN ( in_BRANCH_EVENT_ACK ,ACK); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_CONTEXT_ID ,"context_id" ,Tcontext_t,_param->_size_context_id); -// ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); + ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth); // ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_MISS_PREDICTION ,"miss_prediction" ,Tcontrol_t,1); ALLOC1_SIGNAL_OUT(out_BRANCH_EVENT_ADDRESS_SRC ,"address_src" ,Taddress_t,_param->_size_address); @@ -675,6 +675,6 @@ PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); - PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" , - dest, "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" , + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" ); PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", dest,"out_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); @@ -698,4 +698,6 @@ PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_VAL" ); PORT_MAP(_component,src , "in_BRANCH_EVENT_"+toString(i)+"_ACK" ,dest, "in_BRANCH_EVENT_"+toString(i)+"_ACK" ); + if (_param->_have_port_depth) + PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ,dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_SRC" ); PORT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL",dest,"out_BRANCH_EVENT_"+toString(i)+"_ADDRESS_DEST_VAL"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/src/Prediction_unit_deallocation.cpp (revision 98) @@ -56,5 +56,5 @@ DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth); DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete,1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/SelfTest/src/test.cpp (revision 98) @@ -88,5 +88,5 @@ ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); - ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC0_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ); @@ -176,5 +176,5 @@ INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Front_end, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Front_end,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); INSTANCE0_SC_SIGNAL(_Front_end, in_COMMIT_EVENT_VAL ); @@ -330,5 +330,5 @@ DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); DELETE0_SC_SIGNAL( in_COMMIT_EVENT_VAL ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/include/Front_end.h (revision 98) @@ -116,5 +116,5 @@ public : SC_IN (Tdepth_t ) ** in_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] public : SC_IN (Taddress_t ) ** in_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] - public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_allocation.cpp (revision 98) @@ -123,5 +123,5 @@ ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address); - ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_FLAG ,"FLAG" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); } @@ -538,6 +538,6 @@ PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , dest, "in_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); - PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" , - dest, "in_BRANCH_COMPLETE_"+toString(i)+"_FLAG" ); + PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE", + dest, "in_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE"); dest = _name+"_context_state"; @@ -570,6 +570,7 @@ // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" , // dest, "in_BRANCH_EVENT_"+toString(i)+"_CONTEXT_ID" ); -// COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , -// dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); + if (_param->_have_port_depth) + COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_DEPTH" , + dest, "in_BRANCH_EVENT_"+toString(i)+"_DEPTH" ); // COMPONENT_MAP(_component,src ,"out_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" , // dest, "in_BRANCH_EVENT_"+toString(i)+"_MISS_PREDICTION" ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/src/Front_end_deallocation.cpp (revision 98) @@ -70,5 +70,5 @@ DELETE1_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); DELETE1_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); DELETE1_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/SelfTest/src/test.cpp (revision 98) @@ -35,5 +35,5 @@ // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); // _usage = usage_unset(_usage,USE_POSITION ); - _usage = usage_unset(_usage,USE_STATISTICS ); +// _usage = usage_unset(_usage,USE_STATISTICS ); // _usage = usage_unset(_usage,USE_INFORMATION ); @@ -139,5 +139,5 @@ ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); - ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,"out_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC_SC_SIGNAL (out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ); @@ -282,5 +282,5 @@ INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_Commit_unit,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); INSTANCE1_SC_SIGNAL(_Commit_unit, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); INSTANCE_SC_SIGNAL (_Commit_unit,out_UPDATE_VAL ); @@ -678,5 +678,5 @@ DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete); DELETE_SC_SIGNAL (out_UPDATE_VAL ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/include/Commit_unit.h (revision 98) @@ -57,5 +57,6 @@ public : counter_t * _stat_nb_inst_commit; public : counter_t * _stat_nb_inst_commit_conflit_access; - public : counter_t ** _stat_nb_inst_retire; + public : counter_t ** _stat_nb_inst_retire_ok; + public : counter_t ** _stat_nb_inst_retire_ko; public : counter_t ** _stat_bank_nb_inst;// [nb_bank] #endif @@ -161,5 +162,6 @@ public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] - public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] +//public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_allocation.cpp (revision 98) @@ -167,5 +167,6 @@ ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_DEPTH ,"depth" ,Tdepth_t ,_param->_size_depth ); ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); - ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t ,1); +// ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_FLAG ,"flag" ,Tcontrol_t ,1); + ALLOC1_SIGNAL_OUT(out_BRANCH_COMPLETE_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION,"miss_prediction",Tcontrol_t ,1); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_deallocation.cpp (revision 98) @@ -108,12 +108,13 @@ DELETE1_SIGNAL(out_REEXECUTE_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_reexecute,_param->_size_store_queue_ptr); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1 ); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1); DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete,_param->_size_front_end_id); DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_instruction_address ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1 ); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1 ); +// DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete,1); DELETE_SIGNAL (out_UPDATE_VAL ,1 ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_genMoore.cpp (revision 98) @@ -86,11 +86,12 @@ if (_param->_have_port_context_id) - PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); + PORT_WRITE(out_BRANCH_COMPLETE_CONTEXT_ID [i], entry->context_id ); if (_param->_have_port_front_end_id) - PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); + PORT_WRITE(out_BRANCH_COMPLETE_FRONT_END_ID [i], entry->front_end_id ); if (_param->_have_port_depth) - PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); - PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->data_commit ); - PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i], (entry->flags&FLAG_F)!=0 ); + PORT_WRITE(out_BRANCH_COMPLETE_DEPTH [i], entry->depth ); + PORT_WRITE(out_BRANCH_COMPLETE_ADDRESS [i], entry->data_commit ); +// PORT_WRITE(out_BRANCH_COMPLETE_FLAG [i],(entry->flags&FLAG_F)!=0); + PORT_WRITE(out_BRANCH_COMPLETE_NO_SEQUENCE [i], entry->no_sequence ); break; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_allocation.cpp (revision 98) @@ -28,35 +28,33 @@ _stat_nb_inst_insert = new counter_t * [_param->_nb_rename_unit]; - _stat_nb_inst_retire = new counter_t * [_param->_nb_rename_unit]; + _stat_nb_inst_retire_ok = new counter_t * [_param->_nb_rename_unit]; + _stat_nb_inst_retire_ko = new counter_t * [_param->_nb_rename_unit]; _stat_bank_nb_inst = new counter_t * [_param->_nb_bank]; { - std::string sum_nb_inst_insert = ""; - std::string sum_nb_inst_retire = ""; + std::string sum_nb_inst_insert = "0"; + std::string sum_nb_inst_retire_ok = "0"; + std::string sum_nb_inst_retire_ko = "0"; for (uint32_t i=0; i<_param->_nb_rename_unit; i++) { - _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_"+toString(i)); - _stat_nb_inst_retire [i] = _stat->create_variable("nb_inst_retire_"+toString(i)); + _stat_nb_inst_insert [i] = _stat->create_variable("nb_inst_insert_" +toString(i)); + _stat_nb_inst_retire_ok [i] = _stat->create_variable("nb_inst_retire_ok_"+toString(i)); + _stat_nb_inst_retire_ko [i] = _stat->create_variable("nb_inst_retire_ko_"+toString(i)); _stat->create_expr_average_by_cycle("average_use_interface_insert_"+toString(i), "nb_inst_insert_"+toString(i), "", toString(_("Average instruction by cycle on insert interface (rename_unit %d)"),i)); - _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "nb_inst_retire_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i)); + _stat->create_expr_average_by_cycle("average_use_interface_retire_"+toString(i), "+ nb_inst_retire_ok_"+toString(i)+" nb_inst_retire_ko_"+toString(i), "", toString(_("Average instruction by cycle on retire interface (rename_unit %d)"),i)); _stat->create_expr_percent ("percent_use_interface_insert_"+toString(i) , "average_use_interface_insert_"+toString(i), toString(_param->_nb_inst_insert [i]), toString(_("Percent usage of insert interface (rename_unit %d)"),i)); _stat->create_expr_percent ("percent_use_interface_retire_"+toString(i) , "average_use_interface_retire_"+toString(i), toString(_param->_nb_inst_retire [i]), toString(_("Percent usage of retire interface (rename_unit %d)"),i)); - if (i == 0) - { - sum_nb_inst_insert = "nb_inst_insert_"+toString(i); - sum_nb_inst_retire = "nb_inst_retire_"+toString(i); - } - else - { - sum_nb_inst_insert = "+ nb_inst_insert_"+toString(i) + " " +sum_nb_inst_insert; - sum_nb_inst_retire = "+ nb_inst_retire_"+toString(i) + " " +sum_nb_inst_retire; - } + sum_nb_inst_insert = "+ nb_inst_insert_"+ toString(i) + " " +sum_nb_inst_insert; + sum_nb_inst_retire_ok = "+ nb_inst_retire_ok_"+toString(i) + " " +sum_nb_inst_retire_ok; + sum_nb_inst_retire_ko = "+ nb_inst_retire_ko_"+toString(i) + " " +sum_nb_inst_retire_ko; } - _stat->create_expr_average_by_cycle("average_inst_insert", sum_nb_inst_insert, "", _("Average instruction insert by cycle")); - _stat->create_expr_average_by_cycle("average_inst_retire", sum_nb_inst_retire, "", _("Average instruction retire by cycle")); + _stat->create_expr_average_by_cycle("average_inst_insert" , sum_nb_inst_insert , "", _("Average instruction insert by cycle")); + _stat->create_expr_average_by_cycle("average_inst_retire_ok", sum_nb_inst_retire_ok, "", _("Average instruction retire ok by cycle (IPC)")); + _stat->create_expr_average_by_cycle("average_inst_retire_ko", sum_nb_inst_retire_ko, "", _("Average instruction retire ko (event, miss) by cycle")); + _stat->create_expr_average_by_cycle("average_inst_retire" , "+ "+sum_nb_inst_retire_ok+" "+sum_nb_inst_retire_ko, "", _("Average instruction retire by cycle")); } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_statistics_deallocation.cpp (revision 98) @@ -28,5 +28,6 @@ delete [] _stat_nb_inst_insert; - delete [] _stat_nb_inst_retire; + delete [] _stat_nb_inst_retire_ok; + delete [] _stat_nb_inst_retire_ko; delete [] _stat_bank_nb_inst; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Commit_unit/src/Commit_unit_transition.cpp (revision 98) @@ -281,9 +281,4 @@ log_printf(TRACE,Commit_unit,FUNCTION," * RETIRE [%d][%d]",x,y); -#ifdef STATISTICS - if (usage_is_set(_usage,USE_STATISTICS)) - (*_stat_nb_inst_retire [x]) ++; -#endif - #ifdef DEBUG_TEST if (not PORT_READ(in_RETIRE_ACK [x][y])) @@ -291,7 +286,17 @@ #endif - entry_t * entry = _rob [i].front(); - +#ifdef STATISTICS + if (usage_is_set(_usage,USE_STATISTICS)) + { + rob_state_t state = entry->state; + + if (state == ROB_END_OK) + (*_stat_nb_inst_retire_ok [x]) ++; + else + (*_stat_nb_inst_retire_ko [x]) ++; + } +#endif + Tcontext_t front_end_id = entry->front_end_id; Tcontext_t context_id = entry->context_id ; @@ -478,5 +483,5 @@ it++) { - log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x %.1d, %.1d %.4d, %.1d %.4d, %s - %d", + log_printf(TRACE,Commit_unit,FUNCTION," [%.4d] %.4d %.4d %.4d %.4d, %.3d %.3d, %.8x (%.8x) %.1d, %.1d %.4d, %.1d %.4d, %s - %d", x, (*it)->front_end_id , @@ -487,4 +492,5 @@ (*it)->operation , (*it)->address , + (*it)->address << 2 , (*it)->is_delay_slot , (*it)->use_store_queue , Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_commit.cpp (revision 98) @@ -21,4 +21,5 @@ { log_begin(Reexecute_unit,FUNCTION); + log_function(Reexecute_unit,FUNCTION,_name.c_str()); // Initialisation Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMealy_reexecute.cpp (revision 98) @@ -22,4 +22,5 @@ { log_begin(Reexecute_unit,FUNCTION); + log_function(Reexecute_unit,FUNCTION,_name.c_str()); // =================================================================== Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_genMoore.cpp (revision 98) @@ -22,4 +22,5 @@ { log_begin(Reexecute_unit,FUNCTION); + log_function(Reexecute_unit,FUNCTION,_name.c_str()); // =================================================================== Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Reexecute_unit/src/Reexecute_unit_transition.cpp (revision 98) @@ -22,4 +22,5 @@ { log_begin(Reexecute_unit,FUNCTION); + log_function(Reexecute_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -135,4 +136,43 @@ } +#if ((DEBUG >= DEBUG_TRACE) and DEBUG_Reexecute_unit) + log_printf(TRACE,Reexecute_unit,FUNCTION," * Dump Reexecute_queue"); + + for (uint32_t i=0; i<_param->_nb_bank; ++i) + { + uint32_t j=0; + for (std::list::iterator it=_reexecute_queue[i].begin(); + it!=_reexecute_queue[i].end(); + ++it) + { + log_printf(TRACE,Reexecute_unit,FUNCTION," [%.4d][%.4d] %.4d %.4d %.4d, %.1d %.1d, %.4d %.4d, %.8x (%.2d %.4d) %.8x, %.1d %.5d, %s", + i, + j, + (*it)->context_id , + (*it)->front_end_id , + (*it)->packet_id , + (*it)->spr_wen , + (*it)->reexecute , + (*it)->type , + (*it)->operation , + (*it)->address , + ((*it)->address >> _param->_shift_spr_num_group) & _param->_mask_spr_num_group, + ((*it)->address ) & _param->_mask_spr_num_reg , + (*it)->data , + (*it)->write_rd , + (*it)->num_reg_rd , + toString((*it)->state).c_str()); + + ++j; + } + } +// // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// private : std::list * _reexecute_queue ;//[nb_bank] + typedef struct + { + } entry_t; + +#endif + #if defined(STATISTICS) or defined(VHDL_TESTBENCH) end_cycle (); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp (revision 98) @@ -132,8 +132,8 @@ for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.2d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) - log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.2d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); + log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); } #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp (revision 98) @@ -50,15 +50,17 @@ sc_signal * in_NRESET = new sc_signal ("NRESET"); - ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL ," in_INSERT_RENAME_VAL ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK ,"out_INSERT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL ,"out_INSERT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK ," in_INSERT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,"out_INSERT_RAT_INSERT_VAL",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK," in_INSERT_RAT_RENAME_ACK",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK," in_INSERT_RAT_INSERT_ACK",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); - ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL ," in_INSERT_RENAME_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK ,"out_INSERT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL ,"out_INSERT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK ," in_INSERT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,"out_INSERT_RAT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ," in_INSERT_RAT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ," in_INSERT_RAT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,"out_INSERT_FREE_LIST_GPR_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,"out_INSERT_FREE_LIST_SPR_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert); + ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert); ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ," in_INSERT_DEPENDENCY_CHECKING_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); @@ -126,15 +128,17 @@ (*(_Register_translation_unit_Glue->in_NRESET)) (*(in_NRESET)); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); - INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); + INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); @@ -243,29 +247,32 @@ for (uint32_t i=0; i<_param->_nb_inst_insert;i++) { - TEST(Tcontrol_t,out_INSERT_RENAME_ACK [i]->read(),(in_INSERT_INSERT_ACK [i]->read() and - in_INSERT_RAT_RENAME_ACK [i]->read() and - in_INSERT_RAT_INSERT_ACK [i]->read() and - in_INSERT_FREE_LIST_ACK [i]->read() and - in_INSERT_STAT_LIST_ACK [i]->read() )); - TEST(Tcontrol_t,out_INSERT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and - in_INSERT_RAT_RENAME_ACK [i]->read() and - in_INSERT_RAT_INSERT_ACK [i]->read() and - in_INSERT_FREE_LIST_ACK [i]->read() and - in_INSERT_STAT_LIST_ACK [i]->read() )); - TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and - in_INSERT_INSERT_ACK [i]->read() and - in_INSERT_RAT_RENAME_ACK [i]->read() and - in_INSERT_FREE_LIST_ACK [i]->read() and - in_INSERT_STAT_LIST_ACK [i]->read() )); - TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and - in_INSERT_INSERT_ACK [i]->read() and - in_INSERT_RAT_RENAME_ACK [i]->read() and - in_INSERT_RAT_INSERT_ACK [i]->read() and - in_INSERT_STAT_LIST_ACK [i]->read() )); - TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and - in_INSERT_INSERT_ACK [i]->read() and - in_INSERT_RAT_RENAME_ACK [i]->read() and - in_INSERT_RAT_INSERT_ACK [i]->read() and - in_INSERT_FREE_LIST_ACK [i]->read() )); + TEST(Tcontrol_t,out_INSERT_RENAME_ACK [i]->read(),(in_INSERT_INSERT_ACK [i]->read() and + in_INSERT_RAT_RENAME_ACK [i]->read() and + in_INSERT_RAT_INSERT_ACK [i]->read() and + in_INSERT_FREE_LIST_ACK [i]->read() and + in_INSERT_STAT_LIST_ACK [i]->read() )); + TEST(Tcontrol_t,out_INSERT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and + in_INSERT_RAT_RENAME_ACK [i]->read() and + in_INSERT_RAT_INSERT_ACK [i]->read() and + in_INSERT_FREE_LIST_ACK [i]->read() and + in_INSERT_STAT_LIST_ACK [i]->read() )); + TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and + in_INSERT_INSERT_ACK [i]->read() and + in_INSERT_RAT_RENAME_ACK [i]->read() and + in_INSERT_FREE_LIST_ACK [i]->read() and + in_INSERT_STAT_LIST_ACK [i]->read() )); + TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and + in_INSERT_INSERT_ACK [i]->read() and + in_INSERT_RAT_RENAME_ACK [i]->read() and + in_INSERT_RAT_INSERT_ACK [i]->read() and + in_INSERT_STAT_LIST_ACK [i]->read() )); + TEST(Tcontrol_t,out_INSERT_FREE_LIST_GPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD[i]->read() and + (in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG[i]->read()!=0))); + TEST(Tcontrol_t,out_INSERT_FREE_LIST_SPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE[i]->read())); + TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and + in_INSERT_INSERT_ACK [i]->read() and + in_INSERT_RAT_RENAME_ACK [i]->read() and + in_INSERT_RAT_INSERT_ACK [i]->read() and + in_INSERT_FREE_LIST_ACK [i]->read() )); } @@ -295,15 +302,17 @@ delete in_NRESET; - DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); - DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert); + DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert); DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/include/Register_translation_unit_Glue.h (revision 98) @@ -73,4 +73,6 @@ public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_VAL ;//[nb_inst_insert] public : SC_IN (Tcontrol_t) ** in_INSERT_FREE_LIST_ACK ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_GPR_VAL ;//[nb_inst_insert] + public : SC_OUT(Tcontrol_t) ** out_INSERT_FREE_LIST_SPR_VAL ;//[nb_inst_insert] public : SC_OUT(Tcontrol_t) ** out_INSERT_STAT_LIST_VAL ;//[nb_inst_insert] public : SC_IN (Tcontrol_t) ** in_INSERT_STAT_LIST_ACK ;//[nb_inst_insert] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_allocation.cpp (revision 98) @@ -61,15 +61,17 @@ ALLOC1_INTERFACE("insert",OUT, EAST, "insert's interface", _param->_nb_inst_insert); - ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK ,"rename_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL ,"insert_val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK ,"insert_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL,"rat_insert_val",Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK,"rat_rename_ack",Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK,"rat_insert_ack",Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL ,"free_list_val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK ,"free_list_ack" ,Tcontrol_t,1); - ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1); - ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_RENAME_VAL ,"rename_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_RENAME_ACK ,"rename_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_INSERT_VAL ,"insert_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_INSERT_ACK ,"insert_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_RAT_INSERT_VAL ,"rat_insert_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_RAT_RENAME_ACK ,"rat_rename_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_RAT_INSERT_ACK ,"rat_insert_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_VAL ,"free_list_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_FREE_LIST_ACK ,"free_list_ack" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_GPR_VAL ,"free_list_gpr_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_FREE_LIST_SPR_VAL ,"free_list_spr_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_OUT(out_INSERT_STAT_LIST_VAL ,"stat_list_val" ,Tcontrol_t,1); + ALLOC1_SIGNAL_IN ( in_INSERT_STAT_LIST_ACK ,"stat_list_ack" ,Tcontrol_t,1); ALLOC1_SIGNAL_IN ( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,"DEPENDENCY_CHECKING_READ_RA" ,Tcontrol_t ,1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_deallocation.cpp (revision 98) @@ -30,15 +30,17 @@ delete in_NRESET; - DELETE1_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL,_param->_nb_inst_insert,1); - DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK,_param->_nb_inst_insert,1); - DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK,_param->_nb_inst_insert,1); - DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1); - DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert,1); + DELETE1_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert,1); DELETE1_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert,1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/src/Register_translation_unit_Glue_genMealy_insert.cpp (revision 98) @@ -36,10 +36,13 @@ Tcontrol_t WRITE_RD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD [i]); Tgeneral_address_t NUM_REG_RD_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG [i]); - Tgeneral_address_t NUM_REG_RD_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]); - Tgeneral_address_t NUM_REG_RD_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]); + Tgeneral_address_t NUM_REG_RD_PHY_OLD = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD [i]):0; + Tgeneral_address_t NUM_REG_RD_PHY_NEW = (NUM_REG_RD_LOG!=0)?PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW [i]):0; Tcontrol_t WRITE_RE = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE [i]); Tspecial_address_t NUM_REG_RE_LOG = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG [i]); Tspecial_address_t NUM_REG_RE_PHY_OLD = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD [i]); Tspecial_address_t NUM_REG_RE_PHY_NEW = PORT_READ(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW [i]); + + PORT_WRITE(out_INSERT_FREE_LIST_GPR_VAL [i], WRITE_RD and (NUM_REG_RD_LOG!=0)); + PORT_WRITE(out_INSERT_FREE_LIST_SPR_VAL [i], WRITE_RE ); PORT_WRITE(out_INSERT_STAT_LIST_READ_RA [i], READ_RA ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/src/Register_translation_unit_allocation.cpp (revision 98) @@ -384,9 +384,4 @@ #endif - PORT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" , - dest,"in_RENAME_"+toString(i)+"_WRITE_RD"); - PORT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" , - dest,"in_RENAME_"+toString(i)+"_WRITE_RE"); - dest = _name+"_register_translation_unit_glue"; COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_VAL" , @@ -394,4 +389,8 @@ COMPONENT_MAP(_component,src ,"out_POP_"+toString(i)+"_ACK" , dest, "in_INSERT_"+toString(i)+"_FREE_LIST_ACK" ); + COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_GPR_VAL" , + dest,"out_INSERT_"+toString(i)+"_FREE_LIST_GPR_VAL"); + COMPONENT_MAP(_component,src , "in_POP_"+toString(i)+"_SPR_VAL" , + dest,"out_INSERT_"+toString(i)+"_FREE_LIST_SPR_VAL"); dest = _name+"_dependency_checking_unit"; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/SelfTest/src/test.cpp (revision 98) @@ -132,5 +132,5 @@ ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,"out_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,"out_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete); - ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,"out_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete); + ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,"out_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete); ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ," in_BRANCH_COMPLETE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_branch_complete); @@ -268,15 +268,15 @@ // INSTANCE1_SC_SIGNAL(_OOO_Engine,out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue); - INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); if (_param->_have_port_front_end_id) - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); if (_param->_have_port_context_id) - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); if (_param->_have_port_depth) - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue); - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue); - INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue); - INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_OOO_Engine,out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); + INSTANCE1_SC_SIGNAL(_OOO_Engine, in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); INSTANCE_SC_SIGNAL (_OOO_Engine,out_COMMIT_EVENT_VAL ); @@ -433,23 +433,23 @@ DELETE1_SC_SIGNAL(out_INSERT_RE_NUM_REG ,_param->_sum_inst_insert); -// DELETE1_SC_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); -// DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); - - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue); - DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue); +//DELETE1_SC_SIGNAL(out_RETIRE_VAL ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL( in_RETIRE_ACK ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_USE ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RD_OLD_NUM_REG ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_USE ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RD_NEW_NUM_REG ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_USE ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RE_OLD_NUM_REG ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_USE ,_param->_sum_inst_retire); +//DELETE1_SC_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire); + + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete); + DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete); DELETE_SC_SIGNAL (out_COMMIT_EVENT_VAL ); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/SPR.h (revision 98) @@ -34,5 +34,5 @@ public : Tspr_t read (void ) { - return x=0; + return x; }; public : void write (Tspr_t x) Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_allocation.cpp (revision 98) @@ -148,5 +148,8 @@ { _spr [i][j][k] = new SPR * [NB_REG_GROUP[k]]; - + + for (uint32_t l=0; l_implement_group [i][j][k]) - for (uint32_t l=0; linvalid_register (k,l); + { + for (uint32_t l=0; linvalid_register (k,l); + } + else + { + for (uint32_t l=0; linvalid_register (k,l); + } #ifdef POSITION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_deallocation.cpp (revision 98) @@ -77,8 +77,8 @@ for (uint32_t k=0; k_implement_group [i][j][k]) + if (_spr [i][j][k] != NULL) { for (uint32_t l=0; l_nb_inst_reexecute; i++) -// if (PORT_READ(in_SPR_ACCESS_VAL [i]) and not PORT_READ(in_SPR_ACCESS_WEN [i])) + // not necessery if have not read enable + if (PORT_READ(in_SPR_ACCESS_VAL [i])) { + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_ACCESS [%d]",i); + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; @@ -35,4 +38,14 @@ Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); + log_printf(TRACE,Special_Register_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Special_Register_unit,FUNCTION," * context_id : %d",context_id ); + log_printf(TRACE,Special_Register_unit,FUNCTION," * num_group : %d",num_group ); + log_printf(TRACE,Special_Register_unit,FUNCTION," * num_reg : %d",num_reg ); + +#ifdef DEBUG_TEST + if (not _spr_access_mode [front_end_id][context_id]->exist(num_group,num_reg)) + msgWarning("Access at an invalid special register (group %d, register %d)\n",num_group,num_reg); +#endif + SR * sr = static_cast(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); @@ -43,13 +56,21 @@ sm, sumra); - - PORT_WRITE(out_SPR_ACCESS_RDATA [i], (valid)?_spr[front_end_id][context_id][num_group][num_reg]->read():0); - PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid); + + log_printf(TRACE,Special_Register_unit,FUNCTION," * SM : %d",sm); + log_printf(TRACE,Special_Register_unit,FUNCTION," * SUMRA : %d",sumra); + log_printf(TRACE,Special_Register_unit,FUNCTION," * valid : %d",valid); + + // ISA OpenRISC : no action/exception if unauthorised spr access. Also, read 0. +// if (not PORT_READ(in_SPR_ACCESS_WEN [i])) +// { + Tspr_t rdata = (valid)?(_spr[front_end_id][context_id][num_group][num_reg]->read()):0; + + log_printf(TRACE,Special_Register_unit,FUNCTION," * rdata : %.8x",rdata); + + PORT_WRITE(out_SPR_ACCESS_RDATA [i], rdata); +// } + PORT_WRITE(out_SPR_ACCESS_INVALID [i], not valid); } -#if defined(STATISTICS) or defined(VHDL_TESTBENCH) - end_cycle (); -#endif - log_end(Special_Register_unit,FUNCTION); }; Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_genMoore.cpp (revision 98) @@ -22,4 +22,5 @@ { log_begin(Special_Register_unit,FUNCTION); + log_function(Special_Register_unit,FUNCTION,_name.c_str()); // =================================================================== Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp (revision 98) @@ -22,4 +22,5 @@ { log_begin(Special_Register_unit,FUNCTION); + log_function(Special_Register_unit,FUNCTION,_name.c_str()); if (PORT_READ(in_NRESET) == 0) @@ -38,5 +39,5 @@ throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l)); #endif - log_printf(TRACE,Special_Register_unit,FUNCTION,"Reset SPR [%d][%d][%d][%d]",i,j,k,l); + log_printf(TRACE,Special_Register_unit,FUNCTION," * Reset SPR [%d][%d][%d][%d]",i,j,k,l); _spr [i][j][k][l]->reset(); } @@ -52,4 +53,6 @@ if (PORT_READ(in_SPR_ACCESS_WEN [i])) { + log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_ACCESS [%d]",i); + Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0; Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0; @@ -57,13 +60,28 @@ Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]); + log_printf(TRACE,Special_Register_unit,FUNCTION," * front_end_id : %d",front_end_id); + log_printf(TRACE,Special_Register_unit,FUNCTION," * context_id : %d",context_id ); + log_printf(TRACE,Special_Register_unit,FUNCTION," * num_group : %d",num_group ); + log_printf(TRACE,Special_Register_unit,FUNCTION," * num_reg : %d",num_reg ); + SR * sr = static_cast(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]); Tcontrol_t sm = sr->sm ; Tcontrol_t sumra = sr->sumra; + Tcontrol_t valid = _spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg), + sm, + sumra); + log_printf(TRACE,Special_Register_unit,FUNCTION," * SM : %d",sm); + log_printf(TRACE,Special_Register_unit,FUNCTION," * SUMRA : %d",sumra); + log_printf(TRACE,Special_Register_unit,FUNCTION," * valid : %d",valid); - if (_spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg), - sm, - sumra)) - _spr[front_end_id][context_id][num_group][num_reg]->write(PORT_READ(in_SPR_ACCESS_WDATA [i])); + if (valid) + { + Tspr_t wdata = PORT_READ(in_SPR_ACCESS_WDATA [i]); + + log_printf(TRACE,Special_Register_unit,FUNCTION," * wdata : %.8x",wdata); + + _spr[front_end_id][context_id][num_group][num_reg]->write(wdata); + } } Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/include/OOO_Engine.h (revision 98) @@ -157,5 +157,5 @@ public : SC_OUT(Tdepth_t ) ** out_BRANCH_COMPLETE_DEPTH ;//[nb_inst_branch_complete] public : SC_OUT(Taddress_t ) ** out_BRANCH_COMPLETE_ADDRESS ;//[nb_inst_branch_complete] - public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_FLAG ;//[nb_inst_branch_complete] + public : SC_OUT(Tcontrol_t ) ** out_BRANCH_COMPLETE_NO_SEQUENCE ;//[nb_inst_branch_complete] public : SC_IN (Tcontrol_t ) ** in_BRANCH_COMPLETE_MISS_PREDICTION ;//[nb_inst_branch_complete] Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_allocation.cpp (revision 98) @@ -166,5 +166,5 @@ ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_DEPTH ,"DEPTH" ,Tdepth_t ,_param->_size_depth ); ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_ADDRESS ,"ADDRESS" ,Taddress_t ,_param->_size_instruction_address ); - ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_FLAG ,"FLAG" ,Tcontrol_t ,1 ); + ALLOC1_SIGNAL_OUT (out_BRANCH_COMPLETE_NO_SEQUENCE ,"NO_SEQUENCE" ,Tcontrol_t ,1 ); ALLOC1_SIGNAL_IN ( in_BRANCH_COMPLETE_MISS_PREDICTION ,"MISS_PREDICTION" ,Tcontrol_t ,1 ); } @@ -909,6 +909,6 @@ PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" , dest,"out_BRANCH_COMPLETE_"+toString(i)+"_ADDRESS" ); - PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG" , - dest,"out_BRANCH_COMPLETE_"+toString(i)+"_FLAG" ); + PORT_MAP(_component,src ,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" , + dest,"out_BRANCH_COMPLETE_"+toString(i)+"_NO_SEQUENCE" ); PORT_MAP(_component,src , "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION", dest, "in_BRANCH_COMPLETE_"+toString(i)+"_MISS_PREDICTION"); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/src/OOO_Engine_deallocation.cpp (revision 98) @@ -105,12 +105,12 @@ // DELETE1_SIGNAL(out_RETIRE_RE_NEW_NUM_REG ,_param->_sum_inst_retire,_param->_size_special_register ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_issue,1 ); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_issue,1 ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_issue,_param->_size_front_end_id ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_issue,_param->_size_context_id ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_issue,_param->_size_depth ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_issue,_param->_size_general_data ); - DELETE1_SIGNAL(out_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_issue,1 ); - DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_issue,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_FRONT_END_ID ,_param->_nb_inst_branch_complete,_param->_size_front_end_id); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete,_param->_size_context_id ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete,_param->_size_depth ); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete,_param->_size_general_data); + DELETE1_SIGNAL(out_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete,1 ); + DELETE1_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION ,_param->_nb_inst_branch_complete,1 ); DELETE_SIGNAL (out_COMMIT_EVENT_VAL , 1); Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/src/Core_allocation.cpp (revision 98) @@ -323,6 +323,6 @@ COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_ADDRESS" , dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); - COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_FLAG" , - dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_FLAG" ); + COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_NO_SEQUENCE" , + dest,"out_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" ); COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_MISS_PREDICTION", dest, "in_BRANCH_COMPLETE_FRONT_END_"+toString(i)+"_"+toString(j)+"_MISS_PREDICTION"); @@ -519,6 +519,6 @@ COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_ADDRESS" , dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_ADDRESS" ); - COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_FLAG" , - dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_FLAG" ); + COMPONENT_MAP(_component,src ,"out_BRANCH_COMPLETE_" +toString(j)+"_NO_SEQUENCE" , + dest, "in_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_NO_SEQUENCE" ); COMPONENT_MAP(_component,src , "in_BRANCH_COMPLETE_" +toString(j)+"_MISS_PREDICTION", dest,"out_BRANCH_COMPLETE_OOO_ENGINE_"+toString(i)+"_"+toString(j)+"_MISS_PREDICTION"); @@ -1249,5 +1249,5 @@ // out_BRANCH_COMPLETE_FRONT_END_DEPTH - front_end. in_BRANCH_COMPLETE_DEPTH // out_BRANCH_COMPLETE_FRONT_END_ADDRESS - front_end. in_BRANCH_COMPLETE_ADDRESS - // out_BRANCH_COMPLETE_FRONT_END_FLAG - front_end. in_BRANCH_COMPLETE_FLAG + // out_BRANCH_COMPLETE_FRONT_END_FLAG - front_end. in_BRANCH_COMPLETE_NO_SEQUENCE // in_BRANCH_COMPLETE_FRONT_END_MISS_PREDICTION - front_end.out_BRANCH_COMPLETE_MISS_PREDICTION @@ -1258,5 +1258,5 @@ // in_BRANCH_COMPLETE_OOO_ENGINE_DEPTH - ooo_engine.out_BRANCH_COMPLETE_DEPTH // in_BRANCH_COMPLETE_OOO_ENGINE_ADDRESS - ooo_engine.out_BRANCH_COMPLETE_ADDRESS - // in_BRANCH_COMPLETE_OOO_ENGINE_FLAG - ooo_engine.out_BRANCH_COMPLETE_FLAG + // in_BRANCH_COMPLETE_OOO_ENGINE_FLAG - ooo_engine.out_BRANCH_COMPLETE_NO_SEQUENCE // out_BRANCH_COMPLETE_OOO_ENGINE_MISS_PREDICTION- ooo_engine. in_BRANCH_COMPLETE_MISS_PREDICTION Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic.cpp (revision 98) @@ -49,5 +49,6 @@ #ifdef VHDL // generate the vhdl - vhdl(); + if (usage_is_set(_usage,USE_VHDL)) + vhdl(); #endif Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Version.h (revision 98) @@ -10,8 +10,8 @@ #define MORPHEO_MAJOR_VERSION 0 #define MORPHEO_MINOR_VERSION 2 -#define MORPHEO_REVISION "97" +#define MORPHEO_REVISION "98" #define MORPHEO_CODENAME "Castor" -#define MORPHEO_DATE_DAY "19" +#define MORPHEO_DATE_DAY "31" #define MORPHEO_DATE_MONTH "12" #define MORPHEO_DATE_YEAR "2008" Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Vhdl.h (revision 98) @@ -23,15 +23,15 @@ namespace behavioural { - std::string std_logic (uint32_t size); - std::string std_logic_conv (uint32_t size, std::string value); - std::string std_logic_conv (uint32_t size, uint32_t value); - std::string std_logic_cst (uint32_t size, uint32_t value); - std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min ); - std::string std_logic_range ( uint32_t max , uint32_t min ); - std::string std_logic_range (uint32_t size ); - std::string _std_logic_range (uint32_t size, uint32_t max , uint32_t min ); - std::string _std_logic_range ( uint32_t max , uint32_t min ); - std::string _std_logic_range (uint32_t size ); - std::string std_logic_others (uint32_t size, bool cst); + std::string std_logic (uint32_t size); + std::string std_logic_conv (uint32_t size, std::string value); + std::string std_logic_conv (uint32_t size, uint32_t value); + std::string std_logic_cst (uint32_t size, uint32_t value); + std::string std_logic_range (uint32_t size, uint32_t max , uint32_t min ); + std::string std_logic_range ( uint32_t max , uint32_t min ); + std::string std_logic_range (uint32_t size ); + std::string _std_logic_range (uint32_t size, uint32_t max , uint32_t min ); + std::string _std_logic_range ( uint32_t max , uint32_t min ); + std::string _std_logic_range (uint32_t size ); + std::string std_logic_others (uint32_t size, bool cst); class Vhdl Index: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode.cpp =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode.cpp (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Behavioural/src/SPR_access_mode.cpp (revision 98) @@ -21,11 +21,11 @@ { for (uint32_t i=0; iset_type ("Tregfile", "array "+std_logic_range(nb_word)+" of "+std_logic(size_word)); -\end{verbatim} +\end{lstlisting} \subSection{Constantes} @@ -124,5 +133,6 @@ La déclaration de constante, ce fait avec la méthode {\it set\_constant} de la classe {\it Vhdl}. Les différentes surcharges de cette méthode est le type des arguments {\it type} et {\it init}. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_constant (std::string name, std::string type, @@ -134,27 +144,30 @@ uint32_t size, uint32_t init); -\end{verbatim} +\end{lstlisting} Par exemple pour coder les états d'un automate à 5 états en One Hot : -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} vhdl->set_constant ("State_idle",5,1); -\end{verbatim} +\end{lstlisting} Dans le cas de signaux de type {\it std\_logic}, au lieu de déclarer des constantes, il existe deux fonctions permettant d'utiliser des constantes directement dans le corps du composant. La première est {\it std\_logic\_others}. Elle permet de définir des constantes dont soit les bits sont à pleins un soit à plein zéro. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} std::string std_logic_others (uint32_t size, bool cst ); -\end{verbatim} +\end{lstlisting} Pour toute les autres constantes, la méthode {\it std\_logic\_conv} transforme un entier en {\it std\_logic\_vector}. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} std::string std_logic_conv (uint32_t size, std::string value); std::string std_logic_conv (uint32_t size, uint32_t value); -\end{verbatim} +\end{lstlisting} @@ -162,14 +175,16 @@ Les signaux internes sont définit grâce au méthode {\it set\_signal}. Le premier argument est le nom du signal. Le second est soit un type soit une taille (dans le cas où le type est un {\it std\_logic\_vector}). -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_signal (std::string name, std::string type); void set_signal (std::string name, uint32_t size); -\end{verbatim} +\end{lstlisting} La méthode est également surchargé si le signal à besoin d'une initialisation. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_signal (std::string name, std::string type, @@ -181,9 +196,10 @@ uint32_t size, uint32_t init); -\end{verbatim} +\end{lstlisting} En vhdl il est possible de renommer une champ d'un signal. Ceci ce fait à l'aide de la fonction {\it set\_alias}. Elle prend 4 arguments. Le premier étant le nom du signal après le renommage. le second est soit le type, soit la taille du {\it std\_logic\_vector} du signal rénommé. Les deux derniers conserné le signal à renommé : le nom de ce dernier ainsi que l'intervalle. Pour le dernier paramètre il est recommandé d'utilisé la fonction {\it std\_logic\_range}. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_alias (std::string name1 , std::string type1 , @@ -194,6 +210,5 @@ std::string name2 , std::string range2); -\end{verbatim} - +\end{lstlisting} \Section{VHDL : comportement}\label{vhdl_body} @@ -203,27 +218,184 @@ Il n'y a pas de fonction aidant à l'écriture du Vhdl. La méthode {\it set\_body} permet de définir une ligne de code VHDL. Un retour à la ligne est automatiquement inséré. Le premier argument est pour l'indentation. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_body (uint32_t depth, std::string text ); void set_body (std::string text ); -\end{verbatim} +\end{lstlisting} Pour les commentaires, il y a la fonction {\it set\_comment}. -\begin{verbatim} +\lstparam{C++} +\begin{lstlisting} void set_comment (uint32_t depth, std::string text ); void set_comment (std::string text ); -\end{verbatim} - - +\end{lstlisting} \Section{VHDL : structurelle}\label{vhdl_structural} +\subSection{Description du fichier {\it Component\_vhdl.cpp}} +Les modèles systemC structurelle sont des modèles qui instancie d'autre modèle. Il n'y a pas de description comportementale. Ces modèles sont générés automatiquement. +Par contre les modèles systemC comportementales peuvent être décrit par un modèle VHDL mixte (incluant une description comportementale et des instances d'autre composant). + +Les modèles génériques sont dans le répertoire {\it IPs/systemC/processor/Morpheo/Behavioural/Generic}. + +\lstparam{C++} +\begin{lstlisting}[caption={Component\_vhdl.cpp}, label=component_vhdl.cpp] + void component::vhdl (void) + { + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; + }; +\end{lstlisting} + + +La première étape est d'éditer le fichier {\it Component\_vhdl.cpp}. Le listing \ref{component_vhdl.cpp} représente le contenu de ce fichier. +\begin{itemize} +\item Ligne 3 : Déclaration et construction de la variable {\it vhdl} qui est du type {\it Vhdl}. +\item Ligne 5 : Ajout dans le modèle VHDL des interfaces présentes dans le modèle SystemC. (cf fichiers Component.h). +\item Ligne 6 : Ajout dans le modèle VHDL des composants internes dans le modèle SystemC. (cf fichiers Component.h et Component\_allocation.cpp). +\item Ligne 8 : Ajout dans le modèle VHDL des déclarations définit dans le fichiers Component\_vhdl\_declaration.cpp (cf section \ref{vhdl_declaration}). +\item Ligne 9 : Ajout dans le modèle VHDL de la description comportemental définit dans le fichiers Component\_vhdl\_body.cpp (cf section \ref{vhdl_body}). +\item Ligne 11 : Génération des fichiers VHDL. Le nom du fichier est construit à partir du nom fournit lors de la construction de la variable {\it vhdl}. +\item Ligne 13 : Destruction de l'objet. +\end{itemize} + +Pour la suite, nous allons supposer l'instanciation d'une FIFO. + +\subSection{Ajout d'une instance} + +Dans le fichier Component\_vhdl.cpp : +\begin{enumerate} +\item Inclure la définition de la classe désirée. +\lstparam{C++} +\begin{lstlisting} +#include "Behavioural/Generic/Queue/include/Queue.h" +\end{lstlisting} +\item Creer les paramètres du modèles. +\lstparam{C++} +\begin{lstlisting} + morpheo::behavioural::generic::queue::Parameters * param_queue; + param_queue = new morpheo::behavioural::generic::queue::Parameters + (16, //size_queue + 32);//size_data +\end{lstlisting} +\item Creer le modèle +\lstparam{C++} +\begin{lstlisting} + morpheo::behavioural::generic::queue::Queue * queue; + std::string queue_name = _name + "_queue"; + + queue = new morpheo::behavioural::generic::queue::Queue + (queue_name.c_str() // nom du modèle +#ifdef STATISTICS + ,NULL // Pas paramètres pour les statistiques +#endif + ,param_queue // Paramètres de la file + ,USE_VHDL); // Utilisation du modèle VHDL +\end{lstlisting} +\item Inclure le modèle dans la liste des composants internes +\lstparam{C++} +\begin{lstlisting} + _component->set_component(queue->_component +#ifdef POSITION + , 20, 20, 20, 20 + // Coordonée pour l'outil de visualisation +#endif + , INSTANCE_LIBRARY + // Instancier uniquement les libraries + ); +\end{lstlisting} +\item Indiquer dans le fichier Makefile.deps que le composant dépends de ce modèle. +\lstparam{make} +\begin{lstlisting} +# Inclure les dépendances +ifndef Queue +include $(DIR_MORPHEO)/Behavioural/Generic/Queue/Makefile.deps +endif + +# Inclure les librairies +Component_LIBRARY = -lComponent \ + $(Queue_LIBRARY) + +# Les chemins vers les libraries +Component_DIR_LIBRARY = -L$(Component_DIR)/lib \ + $(Queue_DIR_LIBRARY) + +# Construction de la librarie ``Component'' +Component_library : + @\ + $(MAKE) Queue_library; \ + $(MAKE) --directory=$(Component_DIR) --makefile=Makefile; + +# Effacement des fichiers générés +Component_library_clean : + @\ + $(MAKE) Queue_library_clean; \ + $(MAKE) --directory=$(Component_DIR) --makefile=Makefile clean; +\end{lstlisting} +\end{enumerate} + +\subSection{Instanciation} +L'instanciation ce fait comme avec des composants VHDL classique : +\lstparam{C++} +\begin{lstlisting} + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Instance queue "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body (0,");"); +\end{lstlisting} + \Section{Exemples}\label{example} \subSection{Banc de Registres Monolithique} +\subsubSection{Fichier RegisterFile\_Monolithic\_vhdl.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl.cpp}] +void RegisterFile_Monolithic::vhdl (void) +{ + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port (vhdl); + _component ->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; +}; +\end{lstlisting} + + \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_declaration.cpp} -\begin{verbatim} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_declaration.cpp}] void RegisterFile_Monolithic::vhdl_declaration (Vhdl * & vhdl) { @@ -234,12 +406,15 @@ vhdl->set_signal ("reg_DATA", "Tregfile"); }; -\end{verbatim} +\end{lstlisting} + \subsubSection{Fichier RegisterFile\_Monolithic\_vhdl\_body.cpp} -\begin{verbatim} + +\lstparam{C++} +\begin{lstlisting}[caption={RegisterFile\_Monolithic\_vhdl\_body.cpp}] void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl) { vhdl->set_body (0,""); vhdl->set_comment(0,"---------------------------------------------------"); - vhdl->set_comment(0," Ackitement"); + vhdl->set_comment(0," Ack"); vhdl->set_comment(0,"---------------------------------------------------"); vhdl->set_body (0,""); @@ -295,9 +470,11 @@ vhdl->set_body (0,"end process RegisterFile_write;"); }; -\end{verbatim} +\end{lstlisting} \subsubSection{Fichier RegisterFile\_Monolithic.vhdl} -\begin{verbatim} -library ieee; + +\lstparam{VHDL} +\begin{lstlisting}[caption={RegisterFile\_Monolithic.cpp}] + library ieee; use ieee.numeric_bit.all; use ieee.numeric_std.all; @@ -362,6 +539,424 @@ end process RegisterFile_write; end behavioural; - -\end{verbatim} +\end{lstlisting} + +\subSection{Tampon entre la boucle d'exécutione et le buffer de réordonnancement} + +\subsubSection{Fichier Execute\_queue\_vhdl.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl.cpp}] +void Execute_queue::vhdl (void) +{ + morpheo::behavioural::generic::queue::Parameters * param_queue; + + param_queue = new morpheo::behavioural::generic::queue::Parameters + (_param->_size_queue, + _param->_size_internal_queue + ); + + morpheo::behavioural::generic::queue::Queue * queue; + + std::string queue_name = _name + "_queue"; + queue = new morpheo::behavioural::generic::queue::Queue + (queue_name.c_str() +#ifdef STATISTICS + ,NULL +#endif + ,param_queue + ,USE_VHDL); + + _component->set_component(queue->_component +#ifdef POSITION + , 50, 50, 50, 50 +#endif + , INSTANCE_LIBRARY + ); + + Vhdl * vhdl = new Vhdl (_name); + + _interfaces->set_port(vhdl); + _component->vhdl_instance(vhdl); + + vhdl_declaration (vhdl); + vhdl_body (vhdl); + + vhdl->generate_file(); + + delete vhdl; +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue\_vhdl\_declaration.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl\_declaration.cpp}] +void Execute_queue::vhdl_declaration (Vhdl * & vhdl) +{ + vhdl->set_alias ("internal_QUEUE_INSERT_VAL ", + 1, + " in_EXECUTE_QUEUE_IN_VAL", + std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_INSERT_ACK ", + 1, + "out_EXECUTE_QUEUE_IN_ACK", + std_logic_range(1)); + vhdl->set_signal ("internal_QUEUE_INSERT_DATA", + _param->_size_internal_queue); + vhdl->set_signal ("internal_QUEUE_RETIRE_DATA", + _param->_size_internal_queue); + vhdl->set_alias ("internal_QUEUE_RETIRE_VAL ", + 1, + "out_EXECUTE_QUEUE_OUT_VAL", + std_logic_range(1)); + vhdl->set_alias ("internal_QUEUE_RETIRE_ACK ", + 1, + " in_EXECUTE_QUEUE_OUT_ACK", + std_logic_range(1)); + + uint32_t min = 0; + uint32_t max, size; + + if(_param->_have_port_context_id ) + { + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_PACKET_ID ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + } + + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_FLAGS ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_exception; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_EXCEPTION ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = 1; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_instruction_address; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_ADDRESS ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_alias ("internal_EXECUTE_QUEUE_OUT_DATA ", + std_logic(size), + "internal_QUEUE_RETIRE_DATA", + std_logic_range(_param->_size_internal_queue,max,min)); + min = max+1; +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue\_vhdl\_body.cpp} + +\lstparam{C++} +\begin{lstlisting}[caption={Execute\_queue\_vhdl\_body.cpp}] +void Execute_queue::vhdl_body (Vhdl * & vhdl) +{ + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Instance queue "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); + vhdl->set_body (0,"port map ("); + vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); + vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); + vhdl->set_body (1,", in_INSERT_VAL \t=>\tinternal_QUEUE_INSERT_VAL"); + vhdl->set_body (1,",out_INSERT_ACK \t=>\tinternal_QUEUE_INSERT_ACK"); + vhdl->set_body (1,", in_INSERT_DATA \t=>\tinternal_QUEUE_INSERT_DATA"); + vhdl->set_body (1,",out_RETIRE_VAL \t=>\tinternal_QUEUE_RETIRE_VAL"); + vhdl->set_body (1,", in_RETIRE_ACK \t=>\tinternal_QUEUE_RETIRE_ACK"); + vhdl->set_body (1,",out_RETIRE_DATA \t=>\tinternal_QUEUE_RETIRE_DATA"); + vhdl->set_body (0,");"); + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Input Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + { + uint32_t min = 0; + uint32_t max, size; + uint32_t size_queue = _param->_size_internal_queue; + + if(_param->_have_port_context_id ) + { + size = _param->_size_context_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_CONTEXT_ID;"); + min = max+1; + } + if(_param->_have_port_front_end_id ) + { + size = _param->_size_front_end_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_FRONT_END_ID;"); + min = max+1; + } + if(_param->_have_port_ooo_engine_id ) + { + size = _param->_size_ooo_engine_id; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID;"); + min = max+1; + } + if(_param->_have_port_rob_ptr) + { + size = _param->_size_rob_ptr; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_PACKET_ID;"); + min = max+1; + } + + size = _param->_size_special_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_FLAGS;"); + min = max+1; + + size = _param->_size_exception; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_EXCEPTION;"); + min = max+1; + + size = 1; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE;"); + min = max+1; + + size = _param->_size_instruction_address; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_ADDRESS;"); + min = max+1; + + size = _param->_size_general_data; + max = min-1+size; + vhdl->set_body (0,"internal_QUEUE_INSERT_DATA "+std_logic_range(size_queue,max,min)+ + " <= in_EXECUTE_QUEUE_IN_DATA;"); + min = max+1; + } + + vhdl->set_comment(0,""); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,"-- Output Buffer "); + vhdl->set_comment(0,"-----------------------------------"); + vhdl->set_comment(0,""); + + if(_param->_have_port_context_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID ;"); + if(_param->_have_port_front_end_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID ;"); + if(_param->_have_port_ooo_engine_id) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID"+ + " <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID;"); + if(_param->_have_port_rob_ptr) + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_PACKET_ID "+ + " <= internal_EXECUTE_QUEUE_OUT_PACKET_ID ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_FLAGS "+ + " <= internal_EXECUTE_QUEUE_OUT_FLAGS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_EXCEPTION "+ + " <= internal_EXECUTE_QUEUE_OUT_EXCEPTION ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE "+ + " <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_ADDRESS "+ + " <= internal_EXECUTE_QUEUE_OUT_ADDRESS ;"); + vhdl->set_body (0,"out_EXECUTE_QUEUE_OUT_DATA "+ + " <= internal_EXECUTE_QUEUE_OUT_DATA ;"); +}; +\end{lstlisting} + +\subsubSection{Fichier Execute\_queue.vhdl} + +\lstparam{VHDL} +\begin{lstlisting}[caption={Execute\_queue.cpp}] +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + +library work; +use work.Execute_queue_0_Pack.all; +use work.Execute_queue_0_queue_Pack.all; + +entity Execute_queue_0 is + port ( + in_CLOCK : in std_logic; + in_NRESET : in std_logic; + in_EXECUTE_QUEUE_IN_VAL : in std_logic; + out_EXECUTE_QUEUE_IN_ACK : out std_logic; + in_EXECUTE_QUEUE_IN_CONTEXT_ID : in std_logic; + in_EXECUTE_QUEUE_IN_FRONT_END_ID : in std_logic; + in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID : in std_logic; + in_EXECUTE_QUEUE_IN_PACKET_ID : in std_logic_vector(5 downto 0); + in_EXECUTE_QUEUE_IN_FLAGS : in std_logic_vector(1 downto 0); + in_EXECUTE_QUEUE_IN_EXCEPTION : in std_logic_vector(4 downto 0); + in_EXECUTE_QUEUE_IN_NO_SEQUENCE : in std_logic; + in_EXECUTE_QUEUE_IN_ADDRESS : in std_logic_vector(31 downto 0); + in_EXECUTE_QUEUE_IN_DATA : in std_logic_vector(31 downto 0); + out_EXECUTE_QUEUE_OUT_VAL : out std_logic; + in_EXECUTE_QUEUE_OUT_ACK : in std_logic; + out_EXECUTE_QUEUE_OUT_CONTEXT_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_FRONT_END_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : out std_logic; + out_EXECUTE_QUEUE_OUT_PACKET_ID : out std_logic_vector(5 downto 0); + out_EXECUTE_QUEUE_OUT_FLAGS : out std_logic_vector(1 downto 0); + out_EXECUTE_QUEUE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : out std_logic; + out_EXECUTE_QUEUE_OUT_ADDRESS : out std_logic_vector(31 downto 0); + out_EXECUTE_QUEUE_OUT_DATA : out std_logic_vector(31 downto 0) + ); +end Execute_queue_0; + +architecture behavioural of Execute_queue_0 is + + signal internal_QUEUE_INSERT_DATA : std_logic_vector(80 downto 0); + signal internal_QUEUE_RETIRE_DATA : std_logic_vector(80 downto 0); + + alias internal_QUEUE_INSERT_VAL : std_logic is + in_EXECUTE_QUEUE_IN_VAL; + alias internal_QUEUE_INSERT_ACK : std_logic is + out_EXECUTE_QUEUE_IN_ACK; + alias internal_QUEUE_RETIRE_VAL : std_logic is + out_EXECUTE_QUEUE_OUT_VAL; + alias internal_QUEUE_RETIRE_ACK : std_logic is + in_EXECUTE_QUEUE_OUT_ACK; + alias internal_EXECUTE_QUEUE_OUT_CONTEXT_ID : std_logic is + internal_QUEUE_RETIRE_DATA (0); + alias internal_EXECUTE_QUEUE_OUT_FRONT_END_ID : std_logic is + internal_QUEUE_RETIRE_DATA (1); + alias internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID : std_logic is + internal_QUEUE_RETIRE_DATA (2); + alias internal_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(5 downto 0) is + internal_QUEUE_RETIRE_DATA (8 downto 3); + alias internal_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0) is + internal_QUEUE_RETIRE_DATA (10 downto 9); + alias internal_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0) is + internal_QUEUE_RETIRE_DATA (15 downto 11); + alias internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic is + internal_QUEUE_RETIRE_DATA (16); + alias internal_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0) is + internal_QUEUE_RETIRE_DATA (48 downto 17); + alias internal_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0) is + internal_QUEUE_RETIRE_DATA (80 downto 49); + +begin + -- + -- ----------------------------------- + -- -- Instance queue + -- ----------------------------------- + -- + instance_Execute_queue_0_queue : Execute_queue_0_queue + port map ( + in_CLOCK => in_CLOCK + , in_NRESET => in_NRESET + , in_INSERT_VAL => internal_QUEUE_INSERT_VAL + ,out_INSERT_ACK => internal_QUEUE_INSERT_ACK + , in_INSERT_DATA => internal_QUEUE_INSERT_DATA + ,out_RETIRE_VAL => internal_QUEUE_RETIRE_VAL + , in_RETIRE_ACK => internal_QUEUE_RETIRE_ACK + ,out_RETIRE_DATA => internal_QUEUE_RETIRE_DATA + ); + -- + -- ----------------------------------- + -- -- Input Buffer + -- ----------------------------------- + -- + internal_QUEUE_INSERT_DATA (0) <= in_EXECUTE_QUEUE_IN_CONTEXT_ID; + internal_QUEUE_INSERT_DATA (1) <= in_EXECUTE_QUEUE_IN_FRONT_END_ID; + internal_QUEUE_INSERT_DATA (2) <= in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID; + internal_QUEUE_INSERT_DATA (8 downto 3) <= in_EXECUTE_QUEUE_IN_PACKET_ID; + internal_QUEUE_INSERT_DATA (10 downto 9) <= in_EXECUTE_QUEUE_IN_FLAGS; + internal_QUEUE_INSERT_DATA (15 downto 11) <= in_EXECUTE_QUEUE_IN_EXCEPTION; + internal_QUEUE_INSERT_DATA (16) <= in_EXECUTE_QUEUE_IN_NO_SEQUENCE; + internal_QUEUE_INSERT_DATA (48 downto 17) <= in_EXECUTE_QUEUE_IN_ADDRESS; + internal_QUEUE_INSERT_DATA (80 downto 49) <= in_EXECUTE_QUEUE_IN_DATA; + -- + -- ----------------------------------- + -- -- Output Buffer + -- ----------------------------------- + -- + out_EXECUTE_QUEUE_OUT_CONTEXT_ID <= internal_EXECUTE_QUEUE_OUT_CONTEXT_ID; + out_EXECUTE_QUEUE_OUT_FRONT_END_ID <= internal_EXECUTE_QUEUE_OUT_FRONT_END_ID; + out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID <= internal_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID; + out_EXECUTE_QUEUE_OUT_PACKET_ID <= internal_EXECUTE_QUEUE_OUT_PACKET_ID; + out_EXECUTE_QUEUE_OUT_FLAGS <= internal_EXECUTE_QUEUE_OUT_FLAGS; + out_EXECUTE_QUEUE_OUT_EXCEPTION <= internal_EXECUTE_QUEUE_OUT_EXCEPTION; + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE <= internal_EXECUTE_QUEUE_OUT_NO_SEQUENCE; + out_EXECUTE_QUEUE_OUT_ADDRESS <= internal_EXECUTE_QUEUE_OUT_ADDRESS; + out_EXECUTE_QUEUE_OUT_DATA <= internal_EXECUTE_QUEUE_OUT_DATA; + +end behavioural; +\end{lstlisting} + \Section {Test du VHDL}\label{testbench} @@ -388,2 +983,747 @@ \item Nous ne vérifions pas la compatibilité au bit près des données présente sur une interface qui ne fait pas de transaction lors d'un cycle. \end{itemize} + +\lstparam{VHDL} +\begin{lstlisting}[caption={Execute\_queue\_Testbench.vhdl}] +library ieee; + use ieee.numeric_bit.all; + use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_misc.all; +--use ieee.std_logic_signed.all; + use ieee.std_logic_unsigned.all; +--use ieee.std_logic_textio.all; + +library work; +use work.Execute_queue_0_Pack.all; + +entity Execute_queue_0_Testbench is +end Execute_queue_0_Testbench; + +architecture behavioural of Execute_queue_0_Testbench is + + signal in_CLOCK : std_logic := '0'; + signal in_NRESET : std_logic := '0'; + signal in_EXECUTE_QUEUE_IN_VAL : std_logic; + signal out_EXECUTE_QUEUE_IN_ACK : std_logic; + signal out_EXECUTE_QUEUE_IN_ACK_test : std_logic; + signal in_EXECUTE_QUEUE_IN_PACKET_ID : std_logic_vector(3 downto 0); + signal in_EXECUTE_QUEUE_IN_FLAGS : std_logic_vector(1 downto 0); + signal in_EXECUTE_QUEUE_IN_EXCEPTION : std_logic_vector(4 downto 0); + signal in_EXECUTE_QUEUE_IN_NO_SEQUENCE : std_logic; + signal in_EXECUTE_QUEUE_IN_ADDRESS : std_logic_vector(31 downto 0); + signal in_EXECUTE_QUEUE_IN_DATA : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_VAL : std_logic; + signal out_EXECUTE_QUEUE_OUT_VAL_test : std_logic; + signal in_EXECUTE_QUEUE_OUT_ACK : std_logic; + signal out_EXECUTE_QUEUE_OUT_PACKET_ID : std_logic_vector(3 downto 0); + signal out_EXECUTE_QUEUE_OUT_PACKET_ID_test : std_logic_vector(3 downto 0); + signal out_EXECUTE_QUEUE_OUT_FLAGS : std_logic_vector(1 downto 0); + signal out_EXECUTE_QUEUE_OUT_FLAGS_test : std_logic_vector(1 downto 0); + signal out_EXECUTE_QUEUE_OUT_EXCEPTION : std_logic_vector(4 downto 0); + signal out_EXECUTE_QUEUE_OUT_EXCEPTION_test : std_logic_vector(4 downto 0); + signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE : std_logic; + signal out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test : std_logic; + signal out_EXECUTE_QUEUE_OUT_ADDRESS : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_ADDRESS_test : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_DATA : std_logic_vector(31 downto 0); + signal out_EXECUTE_QUEUE_OUT_DATA_test : std_logic_vector(31 downto 0); + + signal counter : natural; + signal test : std_logic; + signal interface_test : std_logic; + signal interface_test_ok : std_logic; + signal interface_execute_queue_in_test : std_logic; + signal interface_execute_queue_in_test_ok : std_logic; + signal interface_execute_queue_in_test_transaction : std_logic; + signal interface_execute_queue_in_test_tmp : std_logic; + signal interface_execute_queue_out_test : std_logic; + signal interface_execute_queue_out_test_ok : std_logic; + signal interface_execute_queue_out_test_transaction : std_logic; + signal interface_execute_queue_out_test_tmp : std_logic; + +begin + + ------------------------------------------------------ + -- Component - Intanciation + ------------------------------------------------------ + + instance_Execute_queue_0 : Execute_queue_0 + port map ( + in_CLOCK => in_CLOCK + , in_NRESET => in_NRESET + , in_EXECUTE_QUEUE_IN_VAL => in_EXECUTE_QUEUE_IN_VAL + ,out_EXECUTE_QUEUE_IN_ACK => out_EXECUTE_QUEUE_IN_ACK + , in_EXECUTE_QUEUE_IN_PACKET_ID => in_EXECUTE_QUEUE_IN_PACKET_ID + , in_EXECUTE_QUEUE_IN_FLAGS => in_EXECUTE_QUEUE_IN_FLAGS + , in_EXECUTE_QUEUE_IN_EXCEPTION => in_EXECUTE_QUEUE_IN_EXCEPTION + , in_EXECUTE_QUEUE_IN_NO_SEQUENCE => in_EXECUTE_QUEUE_IN_NO_SEQUENCE + , in_EXECUTE_QUEUE_IN_ADDRESS => in_EXECUTE_QUEUE_IN_ADDRESS + , in_EXECUTE_QUEUE_IN_DATA => in_EXECUTE_QUEUE_IN_DATA + ,out_EXECUTE_QUEUE_OUT_VAL => out_EXECUTE_QUEUE_OUT_VAL + , in_EXECUTE_QUEUE_OUT_ACK => in_EXECUTE_QUEUE_OUT_ACK + ,out_EXECUTE_QUEUE_OUT_PACKET_ID => out_EXECUTE_QUEUE_OUT_PACKET_ID + ,out_EXECUTE_QUEUE_OUT_FLAGS => out_EXECUTE_QUEUE_OUT_FLAGS + ,out_EXECUTE_QUEUE_OUT_EXCEPTION => out_EXECUTE_QUEUE_OUT_EXCEPTION + ,out_EXECUTE_QUEUE_OUT_NO_SEQUENCE => out_EXECUTE_QUEUE_OUT_NO_SEQUENCE + ,out_EXECUTE_QUEUE_OUT_ADDRESS => out_EXECUTE_QUEUE_OUT_ADDRESS + ,out_EXECUTE_QUEUE_OUT_DATA => out_EXECUTE_QUEUE_OUT_DATA + ); + ------------------------------------------------------ + -- interface "" + ------------------------------------------------------ + + -- Test exhaustive + + interface_test_ok <= '1' when true + else '0'; + + interface_test <= '1' when (in_NRESET = '0') else interface_test_ok; + ------------------------------------------------------ + -- interface "execute_queue_in" + ------------------------------------------------------ + + with counter select + in_EXECUTE_QUEUE_IN_VAL <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '0' when 7, + '0' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '0' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '0' when 21, + '1' when 22, + '1' when 23, + '0' when 24, + '1' when 25, + '0' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_IN_ACK_test <= + '0' when 0, + '1' when 1, + '1' when 2, + '1' when 3, + '1' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_IN_PACKET_ID <= + "0000" when 0, + "0000" when 1, + "0000" when 2, + "0000" when 3, + "0000" when 4, + "0000" when 5, + "0001" when 6, + "0001" when 7, + "0001" when 8, + "0010" when 9, + "0011" when 10, + "0100" when 11, + "0101" when 12, + "0110" when 13, + "0111" when 14, + "1000" when 15, + "1001" when 16, + "1001" when 17, + "1010" when 18, + "1011" when 19, + "1100" when 20, + "1100" when 21, + "1101" when 22, + "1110" when 23, + "1110" when 24, + "1111" when 25, + "1111" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_FLAGS <= + "00" when 0, + "00" when 1, + "00" when 2, + "00" when 3, + "00" when 4, + "11" when 5, + "11" when 6, + "11" when 7, + "11" when 8, + "00" when 9, + "11" when 10, + "11" when 11, + "11" when 12, + "10" when 13, + "01" when 14, + "01" when 15, + "11" when 16, + "11" when 17, + "10" when 18, + "00" when 19, + "11" when 20, + "11" when 21, + "10" when 22, + "01" when 23, + "01" when 24, + "01" when 25, + "01" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_EXCEPTION <= + "00000" when 0, + "00000" when 1, + "00000" when 2, + "00000" when 3, + "00000" when 4, + "10001" when 5, + "10010" when 6, + "10010" when 7, + "10010" when 8, + "11011" when 9, + "10011" when 10, + "10001" when 11, + "11000" when 12, + "11011" when 13, + "00001" when 14, + "00001" when 15, + "01010" when 16, + "01010" when 17, + "01100" when 18, + "01100" when 19, + "11011" when 20, + "11011" when 21, + "00101" when 22, + "01001" when 23, + "01001" when 24, + "10001" when 25, + "10001" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_NO_SEQUENCE <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_IN_ADDRESS <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00101010111010001001010001001010" when 5, + "01111001111000101010100111100011" when 6, + "01111001111000101010100111100011" when 7, + "01111001111000101010100111100011" when 8, + "00010001100100001100110111100111" when 9, + "01000001101001111100010011001001" when 10, + "00100101011100010011000010100011" when 11, + "01100111011000111000010001011110" when 12, + "01110001111100110010010001010100" when 13, + "01110011011110111000110111011100" when 14, + "01000100000010111010110111111100" when 15, + "01010001111010101101001101101011" when 16, + "01010001111010101101001101101011" when 17, + "00011101010011101101010000111011" when 18, + "00111000010000110111111111011011" when 19, + "01111001101000011101111010101010" when 20, + "01111001101000011101111010101010" when 21, + "01100100100110111011011101111100" when 22, + "00010101101101011010111101011100" when 23, + "00010101101101011010111101011100" when 24, + "01010111100110111110010011110001" when 25, + "01010111100110111110010011110001" when 26, + (others => '0') when others; + + with counter select + in_EXECUTE_QUEUE_IN_DATA <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "01100010010101010101100011101100" when 5, + "01110101010001011110000101000110" when 6, + "01110101010001011110000101000110" when 7, + "01110101010001011110000101000110" when 8, + "01100110111011110100001110001101" when 9, + "01101011011010000000011110011010" when 10, + "01100010101110111101100101011010" when 11, + "01110101101000101010100011010100" when 12, + "00101100101010001000011000010001" when 13, + "01101100111010101111000010000111" when 14, + "00000101000001110010001101100111" when 15, + "00101101010100010111011110010110" when 16, + "00101101010100010111011110010110" when 17, + "01110010010110100000011011111011" when 18, + "01110110010001001010010001011100" when 19, + "01110101110001101100001100111010" when 20, + "01110101110001101100001100111010" when 21, + "00100111010110101100011110010100" when 22, + "01110100000100100010011010111011" when 23, + "01110100000100100010011010111011" when 24, + "00110001000011000101000010110011" when 25, + "00110001000011000101000010110011" when 26, + (others => '0') when others; + + -- Test partial + + interface_execute_queue_in_test_ok <= '1' when true + and out_EXECUTE_QUEUE_IN_ACK = out_EXECUTE_QUEUE_IN_ACK_test + else '0'; + + interface_execute_queue_in_test_transaction <= '1' + and in_EXECUTE_QUEUE_IN_VAL + and out_EXECUTE_QUEUE_IN_ACK + ; + + with counter select + interface_execute_queue_in_test_tmp <= + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 5, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 6, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 9, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 10, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 11, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 12, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 13, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 14, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 15, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 16, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 18, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 19, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 20, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 22, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 23, + interface_execute_queue_in_test_transaction and interface_execute_queue_in_test_ok + when 25, + not interface_execute_queue_in_test_transaction when others; + + interface_execute_queue_in_test <= '1' when (in_NRESET = '0') else + interface_execute_queue_in_test_tmp; + ------------------------------------------------------ + -- interface "execute_queue_out" + ------------------------------------------------------ + + with counter select + out_EXECUTE_QUEUE_OUT_VAL_test <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '0' when 5, + '1' when 6, + '1' when 7, + '0' when 8, + '0' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '0' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '0' when 25, + '1' when 26, + '0' when others; + + with counter select + in_EXECUTE_QUEUE_OUT_ACK <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '1' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '0' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '0' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_OUT_PACKET_ID_test <= + "0000" when 0, + "0000" when 1, + "0000" when 2, + "0000" when 3, + "0000" when 4, + "0000" when 5, + "0000" when 6, + "0001" when 7, + "0001" when 8, + "0001" when 9, + "0010" when 10, + "0011" when 11, + "0100" when 12, + "0101" when 13, + "0110" when 14, + "0111" when 15, + "1000" when 16, + "1001" when 17, + "1001" when 18, + "1010" when 19, + "1011" when 20, + "1100" when 21, + "1100" when 22, + "1101" when 23, + "1110" when 24, + "1110" when 25, + "1111" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_FLAGS_test <= + "00" when 0, + "00" when 1, + "00" when 2, + "00" when 3, + "00" when 4, + "00" when 5, + "11" when 6, + "11" when 7, + "11" when 8, + "11" when 9, + "00" when 10, + "11" when 11, + "11" when 12, + "11" when 13, + "10" when 14, + "01" when 15, + "01" when 16, + "11" when 17, + "11" when 18, + "10" when 19, + "00" when 20, + "11" when 21, + "11" when 22, + "10" when 23, + "01" when 24, + "01" when 25, + "01" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_EXCEPTION_test <= + "00000" when 0, + "00000" when 1, + "00000" when 2, + "00000" when 3, + "00000" when 4, + "00000" when 5, + "10001" when 6, + "10010" when 7, + "10010" when 8, + "10010" when 9, + "11011" when 10, + "10011" when 11, + "10001" when 12, + "11000" when 13, + "11011" when 14, + "00001" when 15, + "00001" when 16, + "01010" when 17, + "01010" when 18, + "01100" when 19, + "01100" when 20, + "11011" when 21, + "11011" when 22, + "00101" when 23, + "01001" when 24, + "01001" when 25, + "10001" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test <= + '0' when 0, + '0' when 1, + '0' when 2, + '0' when 3, + '0' when 4, + '0' when 5, + '1' when 6, + '1' when 7, + '1' when 8, + '1' when 9, + '1' when 10, + '1' when 11, + '1' when 12, + '1' when 13, + '1' when 14, + '1' when 15, + '1' when 16, + '1' when 17, + '1' when 18, + '1' when 19, + '1' when 20, + '1' when 21, + '1' when 22, + '1' when 23, + '1' when 24, + '1' when 25, + '1' when 26, + '0' when others; + + with counter select + out_EXECUTE_QUEUE_OUT_ADDRESS_test <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00000000000000000000000000000000" when 5, + "00101010111010001001010001001010" when 6, + "01111001111000101010100111100011" when 7, + "01111001111000101010100111100011" when 8, + "01111001111000101010100111100011" when 9, + "00010001100100001100110111100111" when 10, + "01000001101001111100010011001001" when 11, + "00100101011100010011000010100011" when 12, + "01100111011000111000010001011110" when 13, + "01110001111100110010010001010100" when 14, + "01110011011110111000110111011100" when 15, + "01000100000010111010110111111100" when 16, + "01010001111010101101001101101011" when 17, + "01010001111010101101001101101011" when 18, + "00011101010011101101010000111011" when 19, + "00111000010000110111111111011011" when 20, + "01111001101000011101111010101010" when 21, + "01111001101000011101111010101010" when 22, + "01100100100110111011011101111100" when 23, + "00010101101101011010111101011100" when 24, + "00010101101101011010111101011100" when 25, + "01010111100110111110010011110001" when 26, + (others => '0') when others; + + with counter select + out_EXECUTE_QUEUE_OUT_DATA_test <= + "00000000000000000000000000000000" when 0, + "00000000000000000000000000000000" when 1, + "00000000000000000000000000000000" when 2, + "00000000000000000000000000000000" when 3, + "00000000000000000000000000000000" when 4, + "00000000000000000000000000000000" when 5, + "01100010010101010101100011101100" when 6, + "01110101010001011110000101000110" when 7, + "01110101010001011110000101000110" when 8, + "01110101010001011110000101000110" when 9, + "01100110111011110100001110001101" when 10, + "01101011011010000000011110011010" when 11, + "01100010101110111101100101011010" when 12, + "01110101101000101010100011010100" when 13, + "00101100101010001000011000010001" when 14, + "01101100111010101111000010000111" when 15, + "00000101000001110010001101100111" when 16, + "00101101010100010111011110010110" when 17, + "00101101010100010111011110010110" when 18, + "01110010010110100000011011111011" when 19, + "01110110010001001010010001011100" when 20, + "01110101110001101100001100111010" when 21, + "01110101110001101100001100111010" when 22, + "00100111010110101100011110010100" when 23, + "01110100000100100010011010111011" when 24, + "01110100000100100010011010111011" when 25, + "00110001000011000101000010110011" when 26, + (others => '0') when others; + + -- Test partial + + interface_execute_queue_out_test_ok <= '1' when true + and out_EXECUTE_QUEUE_OUT_VAL = out_EXECUTE_QUEUE_OUT_VAL_test + and out_EXECUTE_QUEUE_OUT_PACKET_ID = out_EXECUTE_QUEUE_OUT_PACKET_ID_test + and out_EXECUTE_QUEUE_OUT_FLAGS = out_EXECUTE_QUEUE_OUT_FLAGS_test + and out_EXECUTE_QUEUE_OUT_EXCEPTION = out_EXECUTE_QUEUE_OUT_EXCEPTION_test + and out_EXECUTE_QUEUE_OUT_NO_SEQUENCE = out_EXECUTE_QUEUE_OUT_NO_SEQUENCE_test + and out_EXECUTE_QUEUE_OUT_ADDRESS = out_EXECUTE_QUEUE_OUT_ADDRESS_test + and out_EXECUTE_QUEUE_OUT_DATA = out_EXECUTE_QUEUE_OUT_DATA_test + else '0'; + + interface_execute_queue_out_test_transaction <= '1' + and out_EXECUTE_QUEUE_OUT_VAL + and in_EXECUTE_QUEUE_OUT_ACK + ; + + with counter select + interface_execute_queue_out_test_tmp <= + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 6, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 7, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 10, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 11, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 12, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 13, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 14, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 15, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 16, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 17, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 19, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 20, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 22, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 23, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 24, + interface_execute_queue_out_test_transaction and interface_execute_queue_out_test_ok + when 26, + not interface_execute_queue_out_test_transaction when others; + + interface_execute_queue_out_test <= '1' when (in_NRESET = '0') else + interface_execute_queue_out_test_tmp; + + ------------------------------------------------------ + -- Test + ------------------------------------------------------ + + test <= '1' + and interface_test + and interface_execute_queue_in_test + and interface_execute_queue_out_test; + + ------------------------------------------------------ + -- reset + ------------------------------------------------------ + + -- if the systemC simulate have multiple reset, we make the last + in_NRESET <= '1' after 150 ns; + + ------------------------------------------------------ + -- process clock_name + ------------------------------------------------------ + + in_CLOCK <= not in_CLOCK after 50 ns; + + process (in_CLOCK) + begin + if (in_CLOCK'event and in_CLOCK = '1') then + + if (in_NRESET = '0') then + counter <= 4; + else + counter <= counter+1; + + assert not (counter >= 27) report "Test OK" severity FAILURE; + assert not (test = '0') report "Test KO" severity FAILURE; + end if; + end if; + end process; +end behavioural; +\end{lstlisting} Index: trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty =================================================================== --- trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty (revision 97) +++ trunk/IPs/systemC/processor/Morpheo/Documentation/sty/doc-style.sty (revision 98) @@ -16,5 +16,5 @@ \usepackage[latin1]{inputenc} % Car j’écris selon le jeu de caractÚres ISO-8859-1 %\usepackage[utf8]{inputenc} % Car j’écris selon le jeu de caractÚres UTF-8 - +\usepackage{listings} \usepackage{openbib} \usepackage{fancyhdr} @@ -83,4 +83,14 @@ } +\newcommand{\lstparam}[1] +{ + \lstset{ + language=#1, + numbers=left, + numberstyle=\tiny, + stepnumber=5, + numbersep=5pt, + firstnumber=1} +} \newcommand{\TODO}[1] {